Semiconductor device

Abstract

Provided is a novel semiconductor device. The semiconductor device includes a first latch circuit, a second latch circuit, and a holding circuit, wherein the holding circuit includes a first transistor, a second transistor, and a capacitive element. An output part of the first latch circuit is connected to an input part of the second latch circuit, an output part of the second latch circuit is connected to one among a source and a drain of the first transistor via an inverter circuit, the other among the source and the drain of the first transistor is connected to one among one terminal of the capacitive element and the source or the drain of the second transistor, and the other among the source and the drain of the second transistor is connected to an input unit of a second circuit.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device or the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, and a driving method or a manufacturing method thereof.

[0003] Technological development of a semiconductor device capable of holding charge according to data has been progressing by combining a transistor using an oxide semiconductor in a semiconductor layer where a channel is formed (also referred to as an "OS transistor") and a transistor using silicon in a semiconductor layer where a channel is formed (also referred to as an "Si transistor").

[0004] The semiconductor device can achieve low power consumption through power gating by being configured to save (also referred to as "saving," "storing," or "backing up") or load (also referred to as "restoring," "restoring," or "recovery") programs or data held in flip-flops or the like. For example, Patent Document 1 discloses a configuration in which an OS transistor is connected to a flip-flop that is a volatile memory circuit to realize a non-volatile flip-flop.

[0005] JP 2016-82593 A

[0006] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0007] In the configuration described in Patent Document 1, data recovery from power gating is achieved by supplying the saved data to the input section of a flip-flop and writing the data back into the flip-flop in synchronization with a clock signal. In a semiconductor device configured to perform data recovery from power gating in synchronization with a clock signal, data recovery from multiple semiconductor devices may be performed sequentially in synchronization with the clock signal. In such cases, it takes time to complete data recovery for all semiconductor devices. For this reason, there is a demand for asynchronous data recovery from power gating that is not synchronized with a clock signal.

[0008] An object of one embodiment of the present invention is to provide a semiconductor device or the like in which a time required for returning to normal operation after power supply is resumed in power gating is short, or to provide a semiconductor device or the like that can operate at high speed, or to provide a power-saving semiconductor device or the like, or to provide a novel semiconductor device or the like.

[0009] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and / or other problems.

[0010] One embodiment of the present invention is a semiconductor device including a first circuit, a second circuit, a third circuit, and an inverter circuit. The third circuit includes a first transistor, a second transistor, and a capacitor. An output portion of the first circuit is electrically connected to an input portion of the second circuit. The output portion of the second circuit is electrically connected to an input portion of the inverter circuit. The output portion of the inverter circuit is electrically connected to a first terminal of the first transistor. The second terminal of the first transistor is electrically connected to a first terminal of the capacitor and a first terminal of the second transistor. The second terminal of the second transistor is electrically connected to the input portion of the second circuit.

[0011] Another embodiment of the present invention is a semiconductor device including a first circuit, a second circuit, a plurality of third circuits, and an inverter circuit, each of the plurality of third circuits including a first transistor, a second transistor, and a capacitor, a first terminal of the second transistor being electrically connected to a first terminal of the capacitor and a second terminal of the first transistor, an output portion of the first circuit being electrically connected to an input portion of the second circuit, an output portion of the second circuit being electrically connected to an input portion of the inverter circuit, a first terminal of the first transistor included in each of the plurality of third circuits being electrically connected to the output portion of the inverter circuit, and a second terminal of the second transistor included in each of the plurality of third circuits being electrically connected to the input portion of the second circuit.

[0012] The first circuit preferably has a first switch electrically connected to the output of the first circuit, and the second circuit preferably has a second switch electrically connected to the input of the second circuit.

[0013] Each of the first transistor and the second transistor preferably includes an oxide semiconductor in a semiconductor layer in which a channel is formed, and the oxide semiconductor preferably includes indium.

[0014] Each of the first circuit and the second circuit preferably includes a transistor containing silicon in a semiconductor layer in which a channel is formed. Each of the first circuit and the second circuit functions as, for example, a latch circuit.

[0015] According to one embodiment of the present invention, a semiconductor device or the like in which the time required for returning to normal operation after power supply is resumed in power gating can be short, a semiconductor device or the like capable of high-speed operation can be provided, a power-saving semiconductor device or the like can be provided, or a novel semiconductor device or the like can be provided.

[0016] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be found by a person skilled in the art from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc.

[0017] FIGS. 1A and 1B are block diagrams showing an example of a configuration of a semiconductor device. FIGS. 2A and 2B are diagrams showing an example of a circuit configuration of a semiconductor device. FIGS. 3A and 3B are diagrams showing an example of a circuit configuration of a semiconductor device. FIGS. 4A, 4B, 4C, and 4D are diagrams showing an example of a configuration of a semiconductor device. FIGS. 5A, 5B, 5C, and 5D are diagrams showing an example of a circuit configuration of an inverter circuit. FIG. 6 is a diagram showing an example of a circuit configuration of a semiconductor device. FIG. 7A is a block diagram showing an example of a configuration of a semiconductor device. FIG. 7B is a timing chart illustrating an example of an operation of a semiconductor device. FIG. 8 is a diagram illustrating an example of an operation of a semiconductor device. FIG. 9 is a diagram illustrating an example of an operation of a semiconductor device. FIGS. 10A and 10B are block diagrams showing an example of a configuration of a semiconductor device. FIG. 11A is a diagram showing an edge detection circuit. FIG. 11B is a timing chart illustrating the operation of the edge detection circuit. FIGS. 12A and 12B are diagrams showing an example of a configuration of a semiconductor device. FIG. 13 is a block diagram showing an example of a configuration of a semiconductor device. FIGS. 14A and 14B are block diagrams showing an example of a configuration of a semiconductor device. FIG. 15 is a block diagram showing an example of a configuration of a semiconductor device. 16A and 16B are block diagrams illustrating an example configuration of a semiconductor device. FIG. 17A is a diagram illustrating an example configuration of a semiconductor device. FIG. 17B is a timing chart illustrating an example operation of the semiconductor device. FIGS. 18A, 18B, 18C, 18D, and 18E are diagrams illustrating an example operation of the semiconductor device. FIG. 19 is a diagram illustrating an example operation of the semiconductor device. FIGS. 20A1, 20A2, 20A3, 20A4, 20A5, 20A6, and 20A7 are diagrams illustrating an example configuration of an electrical connection. FIGS. 20B1, 20B2, 20B3, 20B4, 20B5, and 20B6 are diagrams illustrating an example configuration of a non-electrical connection. FIGS. 21A, 21B, and 21C are diagrams illustrating an example configuration of a transistor. FIGS. 22A, 22B, and 22C are diagrams illustrating an example configuration of a transistor. 23A and 23B are diagrams illustrating the carrier concentration dependence of Hall mobility. Fig. 23C is a cross-sectional view illustrating an indium oxide film. Fig. 24 is a diagram illustrating an example of a stacked structure of the semiconductor device 100. Fig. 25 is a block diagram illustrating a CPU.Figs. 26A and 26B are perspective views of a semiconductor device. Figs. 27A and 27B are perspective views of a semiconductor device. Fig. 28A is a block diagram illustrating an example configuration of a storage device. Figs. 28B and 28C are perspective views illustrating an example configuration of a storage device. Fig. 29 is a conceptual diagram illustrating the hierarchy of a storage device. Figs. 30A and 30B are an example configuration of electronic components. Figs. 31A, 31B, and 31C are an example configuration of a mainframe computer. Fig. 32A is an example configuration of space equipment. Fig. 32B is an example configuration of a storage system.

[0018] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0019] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may also include semiconductor devices.

[0020] In the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the size, aspect ratio, etc. are not necessarily limited. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0021] In the configuration of the invention of the embodiment, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations may be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned. Furthermore, to make the drawings easier to understand, the illustration of some components may be omitted in plan views, perspective views, etc.

[0022] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components. Therefore, they do not limit the number of components or the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims. Even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0023] In this specification, terms indicating position, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0024] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0025] In this specification, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A, etc.

[0026] In this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, depending on the situation or circumstances, terms such as "film" and "layer" may be interchanged with other terms without using terms such as "film" and "layer." For example, the term "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, the term "conductor" may be interchanged with the term "conductive layer" or "conductive film." Or, for example, the term "insulating layer" or "insulating film" may be interchanged with the term "insulator." Or, the term "insulator" may be interchanged with the term "insulating layer" or "insulating film."

[0027] In this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" and "conductive layer" depending on the situation.

[0028] In this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." Furthermore, the term "wiring" may be changed to the term "power line." Similarly, the reverse is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Similarly, the reverse is also true, and terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Similarly, the reverse is also true, and terms such as "signal" may be changed to the term "potential."

[0029] In this specification, the term "source" refers to a source region, a source electrode, or a source wiring. The source region refers to one of two regions in a semiconductor layer that are adjacent to a channel formation region. The source electrode refers to a conductive layer that includes a portion connected to the source region.

[0030] In this specification, the term "drain" refers to a drain region, a drain electrode, or a drain wiring. The drain region refers to the other of two regions of a semiconductor layer that are adjacent to a channel formation region. The drain electrode refers to a conductive layer that includes a portion connected to the drain region.

[0031] In this specification, the term "gate" refers to a gate electrode or a gate wiring. The gate electrode is an electrode that overlaps with a semiconductor layer of a transistor and has a function of controlling the resistance between the source and drain of the transistor depending on a voltage supplied thereto.

[0032] In this specification, one of the source or the drain of a transistor may be referred to as a "first terminal of the transistor", and the other of the source or the drain of the transistor may be referred to as a "second terminal of the transistor".

[0033] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -15° or more and 15° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0034] In this specification, when referring to counting values ​​and measurement values, terms such as "same," "equal," or "uniform" (including synonyms thereof) are used, this includes an error of plus or minus 10%, unless otherwise specified.

[0035] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchanged. In this specification and elsewhere, unless otherwise specified, voltage and potential can be interchanged.

[0036] In this specification and the like, a high power supply potential VDD (hereinafter also simply referred to as "VDD") refers to a power supply potential that is higher than a low power supply potential VSS. A low power supply potential VSS (hereinafter also simply referred to as "VSS") refers to a power supply potential that is lower than a high power supply potential VDD. A ground potential GND (hereinafter also simply referred to as "GND") can also be used as VDD or VSS. For example, when VDD is GND, VSS is a lower potential than GND, and when VSS is GND, VDD is a higher potential than GND.

[0037] In this specification, the "on state" of a transistor means that the source and drain of the transistor are in an electrically conductive state (a state in which electricity can be passed), and the "off state" of a transistor means that the source and drain of the transistor are in an electrically non-conductive state (a state that can be considered to be electrically disconnected).

[0038] In this specification, the term "on-state current" refers to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" refers to a current that flows between a source and a drain when a transistor is off.

[0039] In this specification and the like, potential H is a potential that turns on an n-channel field effect transistor (also referred to as an "n-type transistor") and turns off a p-channel field effect transistor (also referred to as a "p-type transistor"). Potential L is a potential that turns off an n-type transistor and turns on a p-type transistor. Therefore, potential H is a potential higher than potential L. Potential H may be equal to VDD. Potential L may be equal to VSS.

[0040] In addition, in the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and no distinction is made between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, or Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0041] Generally, "capacitance" has a configuration in which two electrodes face each other via an insulator (dielectric). In this specification, etc., "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., "capacitance element" includes a configuration in which two electrodes face each other via an insulator, a configuration in which two wires face each other via an insulator, or a configuration in which two wires are arranged via an insulator. In addition, in this specification, one electrode of a capacitance element may be referred to as a "first terminal of the capacitance element." In addition, the other electrode of the capacitance element may be referred to as a "second terminal of the capacitance element."

[0042] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identifying symbol such as “A”, “b”, “_1”, "[n]”, or "[m, n]” may be added to the symbol.

[0043] In this specification, "connection" includes, for example, "electrical connection." When "electrical connection" is used to define the connection relationship between circuit elements as an object, "electrical connection" includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0044] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0045] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 20A1 and 20A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which a current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which a current can flow at least one time. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 20A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0046] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 20A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 20A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0047] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 20A6 and 20A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 20A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the connection relationship will be the same as in Figures 20A6 and 20A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0048] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0049] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 20B1, 20B2, and 20B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, as shown in FIGS. 20B4 and 20B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 20B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0050] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0051] Note that one embodiment of the present invention is all or part of the circuit configuration described in this specification, etc. Therefore, one embodiment of the present invention satisfies the support requirement and the clarity requirement even if it does not include all or part of the operations described in this specification, etc.

[0052] 1A and 1B are block diagrams of a semiconductor device 100. In this embodiment, a configuration example and an operation example of a semiconductor device according to one embodiment of the present invention will be described.

[0053] <Configuration Example> The semiconductor device 100 has a first circuit 110 and a second circuit 120. The first circuit 110 has a terminal RE, a terminal QD, a terminal D, a terminal CK, a terminal Q, and a terminal QB. The second circuit 120 has a terminal BK, a terminal RE, a terminal IN, and a terminal OUT.

[0054] The terminal OUT of the second circuit 120 is connected to the terminal QD of the first circuit 110. The terminal IN of the second circuit 120 is connected to the terminal Q or terminal QB of the first circuit 110. In FIG. 1A , the terminal IN of the second circuit 120 is connected to the terminal Q of the first circuit 110. In FIG. 1B , the terminal IN of the second circuit 120 is connected to the terminal QB of the first circuit 110. Whether the terminal IN is connected to the terminal Q or the terminal QB depends on the circuit configuration of the second circuit 120.

[0055] The first circuit 110 functions as a flip-flop circuit (also referred to as an "FF circuit") that holds 1-bit data while power is supplied to the semiconductor device 100. Therefore, the first circuit 110 functions as a memory circuit. In this embodiment, the first circuit 110 has a configuration in which a terminal QD is added to a D flip-flop circuit (also referred to as an "DFF circuit"), which is a type of FF circuit.

[0056] 2A shows a first circuit 110A as a specific circuit configuration example of the first circuit 110. The first circuit 110A includes an inverter circuit 111, a switch 112, an inverter circuit 113, a switch 114, an inverter circuit 115, a switch 116, a switch 117, an inverter circuit 118, an inverter circuit 119, an inverter circuit 131, a switch 132, a switch 133, and an inverter circuit 134.

[0057] An inverter circuit is also called a "NOT gate circuit" or "inverting circuit." An inverter circuit has the function of outputting a logical value different from the logical value of input data. For example, when a potential H is input as data "1," the inverter circuit has the function of outputting a potential L as data "0." Also, when a potential L is input as data "0," the inverter circuit has the function of outputting a potential H as data "1."

[0058] The input part of inverter circuit 111 is connected to terminal D, and the output part of inverter circuit 111 is connected to one terminal of switch 112. The other terminal of switch 112 is connected to the input part of inverter circuit 113 and one terminal of switch 116. The output part of inverter circuit 113 is connected to one terminal of switch 114. The other terminal of switch 114 is connected to the input part of inverter circuit 115 and one terminal of switch 117. The output part of inverter circuit 115 is connected to the other terminal of switch 116.

[0059] The other terminal of switch 117 is connected to the input portion of inverter circuit 118, one terminal of switch 133, and terminal QD. The output portion of inverter circuit 118 is connected to the input portion of inverter circuit 119, the input portion of inverter circuit 131, and terminal QB. The output portion of inverter circuit 119 is connected to terminal Q. The other terminal of switch 133 is connected to one terminal of switch 132. The other terminal of switch 132 is connected to the output portion of inverter circuit 131.

[0060] The input of the inverter circuit 134 is connected to the terminal CK. The terminal CK is supplied with the clock signal CLK. The inverter circuit 134 has a function of outputting an inverted clock signal CLKB, which is an inverted signal of the clock signal CLK. Therefore, the inverter circuit 134 functions as a clock signal generating circuit. It is also possible to provide a terminal CKB (not shown) in the first circuit 110A and input the inverted clock signal CLKB, which is an inverted signal of the clock signal CLK, to the terminal CKB. In this case, the inverter circuit 134 can be eliminated.

[0061] The switches 112, 117, 116, and 133 each change between an on state and an off state in response to the clock signal CLK or the inverted clock signal CLKB. For example, when the clock signal CLK is at a potential H, one terminal of each of the switches 112 and 133 is conductive to the other terminal, and when the clock signal CLK is at a potential L, one terminal of each of the switches 112 and 133 is non-conductive to the other terminal. Furthermore, when the inverted clock signal CLKB is at a potential H, one terminal of each of the switches 116 and 117 is conductive to the other terminal, and when the inverted clock signal CLKB is at a potential L, one terminal of each of the switches 116 and 117 is non-conductive to the other terminal.

[0062] A restore signal RES is supplied to the terminal RE. The switch 114 and the switch 132 each change between an on state and an off state in response to the restore signal RES. For example, when the restore signal RES is at a potential L, one terminal of the switch 114 and the other terminal of the switch 132 is in a conductive state, and when the restore signal RES is at a potential H, one terminal of the switch 114 and the other terminal is in a non-conductive state.

[0063] The first circuit 110A has a first latch circuit 141 and a second latch circuit 142. The first latch circuit 141 includes an inverter circuit 113, a switch 114, an inverter circuit 115, and a switch 116. The second latch circuit 142 includes an inverter circuit 118, an inverter circuit 131, a switch 132, and a switch 133.

[0064] 2B shows a first circuit 110B, which is a modified example of the first circuit 110A. The first circuit 110B differs from the first circuit 110A in the connection of the input part of the inverter circuit 115. Specifically, the input part of the inverter circuit 115 is connected to the output part of the inverter circuit 113 and one terminal of the switch 114. The first latch circuit 141 of the first circuit 110B can be configured with the inverter circuit 113, the inverter circuit 115, and the switch 116, excluding the switch 114.

[0065] 3A shows a first circuit 110C, which is a modified example of the first circuit 110A. In the circuit configuration of the first circuit 110A, the switches 132 and 133 can be interchanged. In the first circuit 110C, the other terminal of the switch 117 is connected to the input portion of the inverter circuit 118, one terminal of the switch 132, and the terminal QD. In addition, the other terminal of the switch 132 is connected to one terminal of the switch 133, and the other terminal of the switch 133 is connected to the output portion of the inverter circuit 131.

[0066] 3B shows a first circuit 110D, which is a modified example of the first circuit 110B. In the circuit configuration of the first circuit 110B, the switches 114 and 117 can be interchanged. In the first circuit 110D, one terminal of the switch 117 is connected to the output of the inverter circuit 113 and the input of the inverter circuit 115. The other terminal of the switch 117 is connected to one terminal of the switch 114. The other terminal of the switch 114 is connected to the input of the inverter circuit 118, one terminal of the switch 132, and the terminal QD.

[0067] Since the first circuit 110B is a modified version of the first circuit 110A, the first circuit 110D, which is a modified version of the first circuit 110B, is also a modified version of the first circuit 110A.

[0068] 2A, 2B, 3A, and 3B, a region in the first circuit 110 (first circuits 110A to 110D) that is connected to the other terminal of the switch 112, the input portion of the inverter circuit 113, and one terminal of the switch 116 and is always at the same potential is denoted as a node ND1. The node ND1 also serves as an input portion of the first latch circuit 141.

[0069] In the first circuit 110A and the first circuit 110C, a region that is connected to the other terminal of the switch 114, the input portion of the inverter circuit 115, and one terminal of the switch 117 and is always at the same potential is referred to as node ND2. In the first circuit 110B, a region that is connected to the output portion of the inverter circuit 113, one terminal of the switch 114, and the input portion of the inverter circuit 115 and is always at the same potential is referred to as node ND2. In the first circuit 110D, a region that is connected to the output portion of the inverter circuit 113, one terminal of the switch 117, and the input portion of the inverter circuit 115 and is always at the same potential is referred to as node ND2. The node ND2 is also the output portion of the first latch circuit 141.

[0070] In the first circuits 110A and 110B, a region that is connected to the other terminal of the switch 117, the input part of the inverter circuit 118, one terminal of the switch 133, and the terminal QD and is always at the same potential is referred to as node ND3. In the first circuit 110C, a region that is connected to the other terminal of the switch 117, the input part of the inverter circuit 118, one terminal of the switch 132, and the terminal QD and is always at the same potential is referred to as node ND3. In the first circuit 110D, a region that is connected to the other terminal of the switch 114, the input part of the inverter circuit 118, one terminal of the switch 132, and the terminal QD and is always at the same potential is referred to as node ND3. The node ND3 is also an input part of the second latch circuit 142.

[0071] In the first circuit 110 (first circuits 110A to 110D), the output part of the inverter circuit 118, the input part of the inverter circuit 119, the input part of the inverter circuit 131, and the terminal QB are connected to each other, and a region that is always at the same potential is referred to as a node ND4. The node ND4 is also the output part of the second latch circuit 142.

[0072] In this embodiment, terminal D is connected to the input of first latch circuit 141 via inverter circuit 111 and switch 112. The output of first latch circuit 141 is connected to the input of second latch circuit 142 via switch 117 or via switches 114 and 117. The output of second latch circuit 142 is connected to terminal QB. In addition, the output of second latch circuit 142 is connected to terminal Q via inverter circuit 119.

[0073] The second circuit 120 has a function of retaining 1-bit data input from a terminal IN, which is an input unit, while the power supply to the semiconductor device 100 is stopped. Therefore, the second circuit 120 also functions as a memory circuit. The second circuit 120 also has a function of outputting the retained data from a terminal OUT, which is an output unit. Specific circuit configuration examples of the second circuit 120 are shown in FIGS. 4A to 4D. As configuration examples of the second circuit 120, a second circuit 120A is shown in FIGS. 4A and 4B, a second circuit 120B is shown in FIG. 4C, and a second circuit 120C is shown in FIG. 4D.

[0074] 4A includes a transistor 121, a transistor 122, and a capacitor Cs. The gate of the transistor 121 is connected to the terminal BK, and the gate of the transistor 122 is connected to the terminal RE. One of the source and the drain of the transistor 121 is connected to the terminal IN, and the other of the source and the drain of the transistor 121 is connected to one electrode of the capacitor Cs and one of the source and the drain of the transistor 122. The other of the source and the drain of the transistor 122 is connected to the terminal OUT.

[0075] A fixed potential is supplied to the other electrode of the capacitance element Cs. Although the potential supplied to the other terminal of the capacitance element Cs can be a variable potential, a fixed potential is preferable because it stabilizes the potential of the node SN. The fixed potential can be a ground potential GND, a reference potential (e.g., 0 V), VDD, VSS, or the like.

[0076] In the second circuit 120A, one of the source and the drain of the transistor 121 is connected to the terminal Q of the first circuit 110 via the terminal IN. The other of the source and the drain of the transistor 122 is connected to the terminal QD of the first circuit 110 via the terminal OUT.

[0077] In FIG. 4A, a region where the other of the source and the drain of the transistor 121, one electrode of the capacitor Cs, and one of the source and the drain of the transistor 122 are connected and always at the same potential is denoted as a node SN.

[0078] The second circuit 120A has a function of writing data (potential) output from the terminal Q to the node SN through the terminal IN and the channel formation region of the transistor 121 by turning on the transistor 121 during backup operation. The second circuit 120A also has a function of retaining the data written to the node SN by turning off the transistors 121 and 122.

[0079] Although Si transistors can be used as the transistors 121 and 122, OS transistors are preferably used. Because the off-state current of an OS transistor is extremely small, the amount of charge held in the node SN is unlikely to fluctuate. That is, data written to the node SN can be held for a long period of time. Furthermore, the second circuit 120A requires almost no power to hold the data written to the node SN, and the data can be held even when the power supply is stopped. For this reason, the second circuit 120A can also be referred to as a "nonvolatile memory." Furthermore, OS transistors have a high withstand voltage between the source and drain, making them suitable as switches.

[0080] Furthermore, Si transistors often have a larger on-state current and faster operating speed than OS transistors. Furthermore, Si transistors can also be implemented as p-type transistors, making them suitable for logic circuits and the like. On the other hand, while Si transistors have a high operating speed, they tend to generate more heat. OS transistors operate stably even in high-temperature environments and exhibit little fluctuation in characteristics. Therefore, even if a second circuit 120A including an OS transistor is stacked on a first circuit 110 including a Si transistor, it is less susceptible to the heat generated by the first circuit 110. This improves the reliability of the semiconductor device 100. Furthermore, stacking the first circuit 110 and the second circuit 120 reduces the area occupied by the semiconductor device 100. This improves the integration density of the semiconductor device 100.

[0081] Furthermore, the second circuit 120A rewrites data by charging and discharging the capacitance element Cs, so that in principle there is no limit to the number of times data can be rewritten. Furthermore, data can be written and read at high speed with low energy.

[0082] A memory circuit including an OS transistor is also referred to as an “OS memory.” Therefore, the second circuit 120A in which the transistors 121 and 122 are OS transistors is an OS memory.

[0083] Note that transistors having back gates can also be used as the transistors 121 and 122. The threshold voltages of the transistors can be controlled by adjusting the potential supplied to the back gates.

[0084] Furthermore, the second circuit 120A has a function of supplying data held in node SN to the terminal QD of the first circuit 110 via the terminal OUT by turning on the transistor 122 during a restore operation. At this time, the node SN and the node ND3 are considered to be short-circuited, and the potential of the node SN changes. In other words, the second circuit 120A is a "destructive readout" type memory device in which the data held therein changes when the data is read out.

[0085] Note that the transistors 121 and 122 function as switches. Therefore, as shown in FIG. 4B, the transistors 121 and 122 can be replaced with switches.

[0086] 4C is a modified example of the second circuit 120A and includes an inverter circuit 123 instead of the transistor 122. The input of the inverter circuit 123 is connected to the node SN. That is, the input of the inverter circuit 123 is connected to the other of the source and the drain of the transistor 121 and one electrode of the capacitance element Cs. The output of the inverter circuit 123 is connected to the terminal OUT.

[0087] The inverter circuit 123 controls whether to output a signal in response to a restore signal RES supplied to a terminal RE. The inverter circuit 123 also has a function of inverting data held at a node SN and supplying the inverted data to a terminal OUT. Therefore, in the second circuit 120B, one of the source and drain of the transistor 121 is connected to a terminal QB via a terminal IN.

[0088] By using an OS transistor for the transistor 121, the second circuit 120B can also function as a nonvolatile memory like the second circuit 120A. Furthermore, in the second circuit 120B, the potential of the node SN does not change during the restore operation. That is, the second circuit 120B is a nondestructive readout type storage device in which stored data does not change during data read.

[0089] 4D is a modified example of the second circuit 120B, and includes a buffer circuit 124 instead of the inverter circuit 123. The input of the buffer circuit 124 is connected to the node SN. That is, the input of the buffer circuit 124 is connected to the other of the source and the drain of the transistor 121 and one electrode of the capacitance element Cs. The output of the buffer circuit 124 is connected to the terminal OUT.

[0090] The buffer circuit 124 controls whether to output or not by a restore signal RES supplied to a terminal RE. The buffer circuit 124 also has a function of supplying data held at a node SN to a terminal OUT without inverting it. Therefore, in the second circuit 120C, one of the source and drain of the transistor 121 is connected to a terminal Q via a terminal IN. The buffer circuit 124 can be realized by connecting an even number of inverter circuits in series.

[0091] By using an OS transistor for the transistor 121, the second circuit 120C can also function as a nonvolatile memory like the second circuits 120A and 120B. Furthermore, in the second circuit 120C, the potential of the node SN does not change during the restore operation. That is, the second circuit 120C is a nondestructive readout memory device in which stored data does not change during data read.

[0092] 5A to 5D show circuit configuration examples applicable to the inverter circuit 123. The inverter circuit 123A shown in FIG. 5A includes a transistor whose gate is connected to the terminal RE in the output section of a CMOS inverter circuit. Specifically, the inverter circuit 123A includes a p-type transistor 127 and n-type transistors 128 and 129, and the gates of the transistors 127 and 128 are connected to a node SN. The gate of the transistor 129 is connected to the terminal RE. VDD is supplied to one of the source or drain of the transistor 127. The other of the source or drain of the transistor 127 is connected to one of the source or drain of the transistor 128 and one of the source or drain of the transistor 129. VSS is supplied to the other of the source or drain of the transistor 128. The other of the source or drain of the transistor 129 is connected to the terminal OUT.

[0093] 5B is a modified example of the inverter circuit 123A, and illustrates an example in which n-type transistors are used for all of the transistors 127 to 129. The inverter circuit 123B differs from the inverter circuit 123A in that an n-type transistor is used for the transistor 127 and VDD is supplied to the gate of the transistor 127. The other configurations are the same as those of the inverter circuit 123A, and therefore description thereof will be omitted.

[0094] Since the inverter circuit 123B does not need to use transistors of different conductivity types, the number of manufacturing steps can be reduced, and productivity can be improved. On the other hand, when VDD is output to the terminal OUT, a potential that is lower than VDD by at least the threshold voltage of the transistor 127 may be output.

[0095] 5C is a modified example of the inverter circuit 123 B. To reduce repetition of the explanation, the following mainly describes the differences between the inverter circuit 123 C and the inverter circuit 123 B.

[0096] The inverter circuit 123C has a capacitor Cb between the gate of the transistor 127 and the other of the source and the drain of the transistor 127. One of the source and the drain of the transistor 126 is connected to the gate of the transistor 127, and a potential (for example, VDD) that turns on the transistor 126 is supplied to the gate of the transistor 126. VDD or an inverted potential of the node SN (potential L when the potential of the node SN is potential H, or potential H when the potential is potential L) is supplied to the other of the source and the drain of the transistor 126.

[0097] One electrode of the capacitor Cb is connected to the gate of the transistor 127, and the other electrode is connected to the other of the source and drain of the transistor 127. The capacitor Cb functions as a bootstrap capacitance. By providing the capacitor Cb, the voltage applied to the gate of the transistor 127 can be increased when the transistor 127 is turned on, and a decrease in the potential output to the terminal OUT can be suppressed. Furthermore, like the inverter circuit 123B, the inverter circuit 123C does not need to use transistors with different conductivity types, which reduces the number of manufacturing steps and improves productivity.

[0098] 5D is a modified example of the inverter circuit 123B. The inverter circuit 123D includes transistors 125 to 129. In addition, an example in which n-channel transistors are used for all of the transistors 125 to 129 is shown. Note that to avoid repetition of the description, differences between the inverter circuit 123D and the inverter circuit 123B will be mainly described.

[0099] In the inverter circuit 123D, a potential VH is supplied to the gate and one of the source and drain of the transistor 125. In order to reduce a potential drop when VDD is supplied to the terminal OUT, the potential VH is preferably set higher than VDD. In particular, the potential VH is preferably set higher than the sum of VDD and the threshold voltages of both the transistor 125 and the transistor 127. This can further reduce a potential drop when VDD is supplied to the terminal OUT.

[0100] The other of the source or the drain of the transistor 125 is connected to the one of the source or the drain of the transistor 126 and the gate of the transistor 127. VSS is supplied to the other of the source or the drain of the transistor 126. The gates of the transistors 126 and 128 are connected to a node SN.

[0101] In the inverter circuit 123D, by using a potential VH that is higher than VDD, it is possible to suppress a decrease in the potential output to the terminal OUT without using a bootstrap capacitance. Furthermore, like the inverter circuit 123B, the inverter circuit 123D does not need to use transistors of different conductivity types, which reduces the number of manufacturing steps and improves productivity.

[0102] 6 shows an example of the circuit configuration of the semiconductor device 100 in which the first circuit 110 is a first circuit 110A and the second circuit 120 is a second circuit 120A. In order to reduce repetition of explanation, the following mainly describes configurations that differ from those previously described.

[0103] 6 includes an inverter circuit 135. The input of the inverter circuit 135 is connected to the terminal RE. The inverter circuit 135 also has a function of outputting an inverted restore signal RESB, which is an inverted signal of the restore signal RES input via the terminal RE.

[0104] OS transistors can be used as the switches 112, 114, 116, 117, 132, and 133. OS transistors have extremely low off-state current and high withstand voltage between the source and drain, making them suitable for use as switches.

[0105] 6 also shows a configuration example in which analog switches are used as switches 112, 114, 116, 117, 132, and 133. Analog switches have a configuration in which an n-type transistor and a p-type transistor are connected in parallel, and can more reliably transmit signals of different polarities. For example, they can transmit both signals at potential H and signals at potential L with almost no attenuation. Therefore, analog switches are suitable as switches for transmitting signals of different polarities.

[0106] 6 , the on and off states of the switches 112, 116, 117, and 133 are controlled by a clock signal CLK and an inverted clock signal CLKB. Specifically, the switches 112 and 133 are conductive when the clock signal CLK is at a potential L and the inverted clock signal CLKB is at a potential H, and are non-conductive when the clock signal CLK is at a potential H and the inverted clock signal CLKB is at a potential L. Furthermore, the switches 116 and 117 are conductive when the clock signal CLK is at a potential H and the inverted clock signal CLKB is at a potential L, and are non-conductive when the clock signal CLK is at a potential L and the inverted clock signal CLKB is at a potential H.

[0107] The on and off states of the switch 114 and the switch 132 are controlled by a restore signal RES and an inverted restore signal RESB. Specifically, the switch 114 and the switch 132 are turned on when the restore signal RES is at a potential L and the inverted restore signal RESB is at a potential H, and turned off when the restore signal RES is at a potential H and the inverted restore signal RESB is at a potential L. The on and off states of the transistor 122 in the second circuit 120A are controlled by the restore signal RES.

[0108] <Operation Example> The semiconductor device 100 functions as a storage device capable of retaining written data even when power supply is stopped. Next, an operation example of the semiconductor device 100 will be described. Fig. 7A shows a block diagram of the semiconductor device 100. Fig. 7B shows a timing chart illustrating the operation of the semiconductor device 100. In this embodiment, an operation example will be described in which a first circuit 110A is used as the first circuit 110 and a second circuit 120A is used as the second circuit 120.

[0109] [Period T1] Period T1 is a normal operation period. During the normal operation period, at the timing when the clock signal CLK supplied to the terminal CK changes from potential L to potential H (also referred to as a "rising edge"), the same signal as the signal supplied to the terminal D is supplied to the terminal Q. For example, when the clock signal CLK changes from potential L to potential H, if the potential L is supplied to the terminal D, the potential L is supplied to the terminal Q. Furthermore, when the clock signal CLK changes from potential L to potential H, if the potential H is supplied to the terminal D, the potential H is supplied to the terminal Q.

[0110] [Period T2] Prior to the power supply being stopped in period T3, the potential supplied to terminal Q is held in the second circuit 120A during period T2. That is, period T2 is a period during which a data save operation (store) is performed. FIG. 7B illustrates a case in which potential H is supplied to terminal Q during period T2.

[0111] In the period T2, when a potential H is supplied to the terminal BK, the transistor 121 is turned on, and electrical continuity is established between the terminal Q and the node SN. Then, the potential of the output portion of the inverter circuit 119 is supplied to the node SN through the transistor 121. In this embodiment, the potential H is supplied to the node SN.

[0112] 8 shows a circuit diagram illustrating the operating state of the semiconductor device 100 in the period T2. FIG. 8 illustrates a case where the clock signal CLK is at a potential L. Note that in the drawings, to clearly indicate the potential of a wiring, an electrode, or the like, "H" indicating a potential H or "L" indicating a potential L may be added adjacent to the wiring, electrode, or the like. Also, "H" or "L" may be enclosed in a box around a wiring, electrode, or the like in which a potential change has occurred. Furthermore, when a transistor, switch, or the like is in an off state, an "x" symbol may be added over the transistor, switch, or the like. Also, an arrow indicating the direction of current flow may be added.

[0113] Next, the potential L is supplied to the terminal BK to turn off the transistor 121, so that the potential (charge) written to the node SN is held.

[0114] [Period T3] Period T3 is a period during which power gating is performed. Specifically, during period T3, power supply to semiconductor device 100 is stopped (Power off). Stopping the power supply to semiconductor device 100 stops the potential supply to terminals Q and QB. Meanwhile, the potential of node SN is maintained even during period T3 when the power supply is stopped.

[0115] Furthermore, during the period T3, the supply of the clock signal CLK can also be stopped. When the supply of the clock signal CLK is stopped, the generation of the inverted clock signal CLKB inside the semiconductor device 100 is also stopped. By providing the period T3, the power consumption of the semiconductor device 100 can be reduced.

[0116] [Period T4] Period T4 is a period for performing a data restore operation. During period T4, an operation is performed to restore the potential supplied to terminal Q to the state immediately before power gating (period T3). In this embodiment, data restoration is performed in a state where the supply of clock signal CLK is stopped. In other words, data restoration is performed asynchronously.

[0117] First, power supply to the semiconductor device 100 is resumed. Then, the inverter circuit 111, the inverter circuit 113, the inverter circuit 115, the inverter circuit 118, the inverter circuit 119, and the inverter circuit 131 each output a potential H or a potential L.

[0118] Next, a potential H is supplied to the terminal RE as the restore signal RES, whereupon the inverter circuit 135 outputs a potential L as the inverted restore signal RESB, and the switches 114 and 132 are turned off.

[0119] Furthermore, when a potential H is supplied to the terminal RE as the restore signal RES, the transistor 122 is turned on, and the potential H held by the node SN is supplied to the node ND3 via the terminal QD. That is, the potential H is supplied to the input portion of the second latch circuit 142. When the input portion of the second latch circuit 142 becomes the potential H, the potential L is output from the inverter circuit 118, and the potential H is output from the inverter circuit 119. Therefore, the potential H is supplied to the terminal Q, and the potential L is supplied to the terminal QB. In this manner, data can be restored from power gating. FIG. 9 shows a circuit diagram illustrating the operating state of the semiconductor device 100 when the potential H is supplied to the terminal RE as the restore signal RES.

[0120] If power supply to the semiconductor device 100 is resumed while the clock signal CLK is not being supplied, the states of the switches 112, 116, 117, and 133 are not determined. That is, it is not determined whether they are in the on state or the off state. If the states of these switches are not determined, the output of the inverter circuit 113 or the inverter circuit 131 may be supplied to the node ND3, and the data held in the node SN may be unintentionally rewritten.

[0121] In particular, when the second circuit 120A is used as the second circuit 120, unintentional data rewriting can be prevented by turning off both the switch 114 provided between the output terminal of the inverter circuit 113 and the node ND3 and the switch 132 provided between the output terminal of the inverter circuit 131 and the node ND3. This improves the reliability of the semiconductor device 100. Furthermore, when the second circuit 120A is used as the second circuit 120, the potential supplied from the node SN to the node ND3 during the restore operation varies depending on the ratio of the parasitic capacitance of the node ND3 to the capacitance of the capacitive element Cs. To reduce potential fluctuations during the restore operation, the capacitance of the capacitive element Cs is preferably four times or more, more preferably nine times or more, the parasitic capacitance of the node ND3. Note that if the capacitance of the capacitive element Cs is sufficiently larger than the parasitic capacitance of the node ND3, one or both of the switches 114 and 132 can be omitted.

[0122] When the second circuit 120B or the second circuit 120C is used as the second circuit 120, the output of the inverter circuit 123 or the buffer circuit 124 is supplied to the node ND3. Since the inverter circuit 123 or the buffer circuit 124 has a high potential supply capability, one or both of the switch 114 and the switch 132 can be omitted.

[0123] After the end of the period T4, a clock signal CLK is supplied to the terminal CK, thereby enabling normal operation. The semiconductor device 100 according to one embodiment of the present invention can restore data asynchronously, i.e., not in synchronization with the clock signal, when restoring data from power gating. Therefore, when restoring multiple semiconductor devices to which power supply has been stopped, it is not necessary to restore the data sequentially in synchronization with the clock signal CLK. According to one embodiment of the present invention, multiple semiconductor devices can be restored at individual timings and then operated in synchronization with the clock signal CLK, thereby substantially shortening the time required for data restoration from power gating.

[0124] Furthermore, during the recovery operation, the data held by the second circuit 120A is not supplied to the input side of the first latch circuit 141 such as terminal D or to the input part (node ​​ND1) of the first latch circuit 141, but is supplied to the input part (node ​​ND3) of the second latch circuit 142, thereby achieving asynchronous data recovery.

[0125] In the present embodiment, an example of operation and its effects have been described in which the first circuit 110A is used as the first circuit 110 and the second circuit 120A is used as the second circuit 120. The example of operation and its effects can be achieved in any combination of either the first circuit 110A or the first circuit 110B and any one of the second circuits 120A to 120C.

[0126] <Variation 1> Figure 10A shows a variation of the semiconductor device 100 shown in Figure 1A. The semiconductor device 100 shown in Figure 10A is a semiconductor device 100 to which a scan function for confirming operation has been added. The semiconductor device 100 shown in Figure 10A has a configuration in which an output section of a selection circuit 130 is connected to terminal D of the first circuit 110. The selection circuit 130 also has two data input terminals (terminals SD and D) and has a function of switching the input terminal connected to terminal D of the first circuit 110 in response to a selection signal SEL.

[0127] A test signal for checking the operation of the semiconductor device 100 is supplied to the terminal SD. Checking the operation of the semiconductor device 100 shown in FIG. 10A is performed as follows. First, the selection circuit 130 connects the terminal SD to the terminal D of the first circuit 110, and the test signal is supplied to the terminal D of the first circuit 110. For example, when a potential H is supplied as the test signal, if the operation of the first circuit 110 is normal, when the clock signal CLK changes from a potential L to a potential H, the potential H is supplied to the terminal Q of the first circuit 110. Furthermore, when the potential L is supplied as the test signal, the potential L is supplied to the terminal Q of the first circuit 110. In this way, it can be checked whether the semiconductor device 100 is operating correctly.

[0128] <Modification 2> Fig. 10B shows a modification of the semiconductor device 100 shown in Fig. 1A. The semiconductor device 100 shown in Fig. 10B has a configuration in which an edge detection circuit 160 is added to the semiconductor device 100 shown in Fig. 1A.

[0129] The edge detection circuit 160 has a terminal REout, which is connected to the terminal RE of the first circuit 110 and the terminal RE of the second circuit 120.

[0130] FIG. 11A shows a circuit configuration applicable to the edge detection circuit 160. The edge detection circuit 160 shown in FIG. 11A includes an inverter circuit 161, an AND circuit 162, a resistive element 163, and a capacitive element 164. The input of the inverter circuit 161 is connected to a first input IN1 of the AND circuit 162. VDD is supplied to the input of the inverter circuit 161 and the first input IN1 of the AND circuit 162. The output of the inverter circuit 161 is connected to one terminal of the resistive element 163. The other terminal of the resistive element 163 is connected to one terminal of the capacitive element 164 and a second input IN2 of the AND circuit 162. The output of the AND circuit 162 is connected to a terminal REout. GND is supplied to the other terminal of the capacitive element 164.

[0131] The resistive element 163 and the capacitive element 164 form a delay circuit 165. Therefore, the output of the inverter circuit 161 and the second input IN2 of the AND circuit 162 are connected via the delay circuit 165. In addition, a high power supply potential VDD2 (hereinafter also simply referred to as "VDD2") is supplied as a power supply for the inverter circuit 161.

[0132] 11B shows a timing chart illustrating the operation of the edge detection circuit 160. During a period T3, in conjunction with the stop of the power supply, the potentials of the input section of the inverter circuit 161 and the first input section IN1 become potential L. Because VDD2 continues to be supplied to the inverter circuit 161, potential H is supplied to the output section of the inverter circuit 161. Furthermore, because the output section of the inverter circuit 161 and the second input section IN2 of the AND circuit 162 are connected via the delay circuit 165, the potential supplied to the second input section IN2 gradually changes from potential L to potential H after the power supply is stopped.

[0133] When the period T3 ends and the power supply is resumed (period T4), a potential H is supplied to the input portion and the first input portion IN1 of the inverter circuit 161, and a potential L is supplied to the output portion of the inverter circuit 161. As described above, the output portion of the inverter circuit 161 and the second input portion IN2 of the AND circuit 162 are connected via the delay circuit 165. Therefore, the potential supplied to the second input portion IN2 changes smoothly from the potential H to the potential L. Therefore, immediately after the start of the period T4, a potential H is supplied from the output portion of the AND circuit 162, and after a certain time has elapsed, a potential L is supplied from the output portion of the AND circuit 162.

[0134] By providing the edge detection circuit 160, it is possible to eliminate the need for the restore signal RES to be supplied to the terminal RE, thereby reducing the number of types of signals required for operation and realizing a semiconductor device with good controllability.

[0135] <Stacked Structure Example> The circuits, transistors, and the like that constitute the semiconductor device 100 can be provided on the same plane, but it is preferable that they are provided so that at least a portion of them overlap.

[0136] 12A and 12B show a configuration example of a semiconductor device 100 in which a first circuit 110 is provided in an element layer 10 including a Si transistor and a second circuit 120 is provided in an element layer 20 including an OS transistor on the element layer 10. Note that FIG. 12A shows a configuration example of a second circuit 120A as the second circuit 120. By providing the first circuit 110 and the second circuit 120 so that they overlap each other, the area occupied by the semiconductor device 100 can be reduced. Therefore, the integration degree of the semiconductor device 100 can be increased.

[0137] For example, the first circuit 110 included in the semiconductor device 100 is configured as a CMOS circuit using Si transistors, and the second circuit 120 is configured to include an OS transistor. When one or more of the switches 112, 114, 116, 117, 132, and 133 are configured as OS transistors, the switches can be provided in the element layer 20. By providing the switches in the element layer 20, the area occupied by the switches in the element layer 10 can be reduced. Therefore, the area occupied by the semiconductor device 100 can be reduced.

[0138] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0139] Second Embodiment In the present embodiment, a semiconductor device 150 will be described, which is a modification of the semiconductor device 100. In order to reduce repetition of the description, differences from the semiconductor device 100 will be mainly described.

[0140] Fig. 13 shows a block diagram of a semiconductor device 150. The semiconductor device 150 shown in Fig. 13 has one first circuit 110 and multiple second circuits 120. Fig. 13 shows the semiconductor device 150 having one first circuit 110 and k second circuits 120. By having multiple second circuits 120, the semiconductor device 150 can hold multiple pieces of data.

[0141] 13 and the like, the first second circuit 120 is indicated as second circuit 120[1], the second second circuit 120 is indicated as second circuit 120[2], and the kth second circuit 120 is indicated as second circuit 120[k]. The k second circuits 120 are connected in parallel to one another. Specifically, the terminal IN of each of the k second circuits 120 is connected to the terminal Q of the first circuit 110, and the terminal OUT of each of the k second circuits 120 is connected to the terminal QD of the first circuit 110.

[0142] 13 and the like, the terminals IN, OUT, BK, and RE of the second circuit 120[1] are each marked with [1]. The terminals IN, OUT, BK, and RE of the second circuit 120[2] are each marked with [2]. The terminals IN, OUT, BK, and RE of the second circuit 120[k] are each marked with [k].

[0143] As with the semiconductor device 100, it is preferable that the semiconductor device 150 also has a first circuit 110 provided in an element layer 10 including a Si transistor, and a second circuit 120 provided in an element layer 20 including an OS transistor on the element layer 10.

[0144] 14A and 14B show a configuration example of a semiconductor device 150 in which a first circuit 110 is provided in an element layer 10 including Si transistors, and a second circuit 120 is provided in a plurality of element layers 20 including OS transistors on the element layer 10. Note that FIG. 14A shows a configuration example of a second circuit 120A as the second circuit 120.

[0145] 14A and 14B , a second circuit 120A[1] is provided in the element layer 20[1], which is the first element layer 20 on the element layer 10, a second circuit 120A[2] is provided in the element layer 20[2], which is the second element layer 20, and a second circuit 120A[k] is provided in the element layer 20[1], which is the kth element layer 20. Therefore, at least one second circuit 120 of the k second circuits 120 has an overlapping area with the first circuit 110.

[0146] By providing a plurality of second circuits 120 stacked above the first circuit 110, the area occupied by the semiconductor device 150 can be reduced, and therefore the integration degree of the semiconductor device 150 can be increased.

[0147] Furthermore, as shown in FIG. 15, when the second circuit 120B is used as the second circuit 120, the terminals IN[1] to IN[k] are connected to the terminal QB.

[0148] 16A and 16B , it is also possible to provide a plurality of second circuits 120 in one element layer 20. By providing a plurality of second circuits 120 in one element layer 20, the number of manufacturing steps is reduced, thereby improving the productivity of the semiconductor device 150. Furthermore, the manufacturing cost of the semiconductor device 150 can be reduced.

[0149] 17A illustrates a configuration in which three second circuits 120 (k=3) are used to explain the operation of the semiconductor device 150. In FIG. 17A, nodes SN[1] to SN[3] are illustrated as nodes SN that store data in the second circuits 120[1] to 120[3]. Also illustrated in FIG. 17A are a terminal BK[1] and a terminal RE[1] of the second circuit 120[1], a terminal BK[2] and a terminal RE[2] of the second circuit 120[2], and a terminal BK[3] and a terminal RE[3] of the second circuit 120[3].

[0150] FIG. 17B shows an example of a timing chart illustrating the operation of the semiconductor device 150 shown in FIG. 17A . Note that, in FIG. 17B , M0 to M7 represent time. FIG. 17B illustrates terminal CK, terminal D, terminal Q, terminal BK[1], terminal BK[2], terminal BK[3], terminal RE[1], terminal RE[2], terminal RE[3], node SN[1], and node SN[2]. As described above, the first circuit 110 can function as a DFF circuit. Therefore, the first circuit 110 has the function of supplying the same signal as that supplied to terminal D to terminal Q in synchronization with the rising edge of the clock signal CLK supplied to terminal CK, and the function of storing the data supplied to terminal D until the next rising edge.

[0151] 18A to 18E are schematic diagrams of the semiconductor device 150 for explaining the operation in the timing chart of FIG. 17B. FIG. 18A illustrates the first circuit 110 and the second circuits 120[1] to 120[3]. FIG. 18B to 18E are diagrams illustrating data input to and output from the first circuit 110 and the second circuits 120[1] to 120[3] at times M1, M3, M5, and M7 in FIG. 17B.

[0152] First, as a prerequisite, it is assumed that a potential L is supplied to the terminals BK[1] to BK[3] and the terminals RE[1] to RE[3] of the second circuit 120. Furthermore, when a potential H is supplied to any of the terminals RE[1] to RE[3] of the second circuit 120, it is assumed that a potential H is also supplied to the terminal RE of the first circuit 110.

[0153] At time M0, the first circuit 110 holds the data D0 supplied to the terminal D and supplies the data D0 to the terminal Q in synchronization with the rising edge of the clock signal CLK.

[0154] At time M1, in synchronization with the rising edge of the clock signal CLK, the first circuit 110 holds the data D1 supplied to the terminal D and supplies the data D1 to the terminal Q. Also, at time M1, by supplying a potential H to the terminal BK[1], the data D1 supplied to the terminal Q of the first circuit 110 is written to the node SN[1] of the second circuit 120[1] (see FIG. 18B ). Thereafter, by supplying a potential L to the terminal BK[1], the data written to the node SN[1] is held.

[0155] At time M2, the first circuit 110 holds the data D2 supplied to the terminal D and supplies the data D2 to the terminal Q in synchronization with the rising edge of the clock signal CLK.

[0156] At time M3, in synchronization with the rising edge of the clock signal CLK, the first circuit 110 holds the data D3 supplied to terminal D and supplies the data D3 to terminal Q. Also, at time M3, a potential H is supplied to terminal BK[2], so that the data D3 supplied to terminal Q of the first circuit 110 is written to node SN[2] of the second circuit 120[2] (see FIG. 18C ). Thereafter, a potential L is supplied to terminal BK[2], so that the data written to node SN[2] is held.

[0157] At time M4, the first circuit 110 holds the data D4 supplied to the terminal D and supplies the data D4 to the terminal Q in synchronization with the rising edge of the clock signal CLK.

[0158] At time M5, when a potential H is supplied to the terminal RE[1], the data D1 held by the second circuit 120[1] is returned to the first circuit 110, and the data D1 is supplied to the terminal Q (see FIG. 18D ). Thereafter, a potential L is supplied to the terminal RE[1]. At this time, if the second circuit 120A is used as the second circuit 120[1], the data D1 held by the second circuit 120[1] is destroyed. On the other hand, if the second circuit 120B or the second circuit 120C is used as the second circuit 120[1], the data D1 held by the second circuit 120[1] remains stored without being destroyed.

[0159] At time M6, the first circuit 110 holds the data D6 supplied to the terminal D and supplies the data D6 to the terminal Q in synchronization with the rising edge of the clock signal CLK.

[0160] At time M7, when a potential H is supplied to terminal RE[2], the data D3 held by second circuit 120[2] is returned to the first circuit 110, and data D3 is supplied to terminal Q (see FIG. 18E). Thereafter, a potential L is supplied to terminal RE[2]. At this time, if second circuit 120A is used as second circuit 120[1], data D3 held by second circuit 120[2] is destroyed. On the other hand, if second circuit 120B or second circuit 120C is used as second circuit 120[2], data D3 held by second circuit 120[2] remains stored without being destroyed.

[0161] For example, when an interrupt occurs in an arithmetic processing unit, which is a type of semiconductor device such as a CPU or a GPU, data held in a register or the like needs to be temporarily saved to a main memory. By using the semiconductor device 150 of one embodiment of the present invention as a register or the like of a CPU or a GPU, data of a process being executed before the interrupt can be saved to the second circuit 120, and data of the previously executed process can be quickly restored after the interrupt process ends. Furthermore, since the semiconductor device 150 of one embodiment of the present invention includes multiple second circuits 120, it can also handle multiple consecutive interrupt processes. Furthermore, the semiconductor device 150 of one embodiment of the present invention can restore data without synchronization with a clock signal CLK. By using the semiconductor device 150 of one embodiment of the present invention, multiple interrupt processes can be efficiently switched.

[0162] FIG. 19 is a timing chart of the interrupt process switching operation of the semiconductor device 150 described in FIGS. 17A and 17B, with the horizontal axis representing the elapsed time (Time).

[0163] At time Ma, while the arithmetic processing unit including the semiconductor device 150 is executing a first operation (Operation 1), the data held in the first circuit 110 of the semiconductor device 150 is saved to the second circuit 120[1] (Save to 120[1]), and then the data held in the second circuit 120[2] is written back to the first circuit 110 (Load from 120[2]). In this way, the arithmetic processing unit including the semiconductor device 150 can suspend the first operation and execute a second operation (Operation 2).

[0164] At time Mb, while the arithmetic processing unit including the semiconductor device 150 is executing the second operation, the data in the first circuit 110 of the semiconductor device 150 is saved to the second circuit 120[2] (Save to 120[2]), and then the data in the second circuit 120[3] is written back to the first circuit 110 (Load from 120[3]). In this way, the arithmetic processing unit including the semiconductor device 150 can suspend the second operation and execute the third operation (Ope3).

[0165] At time Mc, while the arithmetic processing unit including the semiconductor device 150 is executing the third process, the data held in the first circuit 110 of the semiconductor device 150 is saved to the second circuit 120[3] (Save to 120[3]), and then the data held in the second circuit 120[1] is written back to the first circuit 110 (Load from 120[1]). Here, the data written back to the first circuit 110 from the second circuit 120[1] is the data saved from the first circuit 110 to the second circuit 120[1] at time Ma. In other words, this data is necessary to resume the first process that was interrupted at time Ma. In this way, the state of the third process is saved, and the arithmetic processing unit including the semiconductor device 150 can resume the interrupted first process.

[0166] By using the semiconductor device 150 according to one embodiment of the present invention, a semiconductor device can be realized that can suspend an ongoing process, execute an interrupt process with a high priority, and then resume the suspended process. Therefore, a semiconductor device with improved computing performance can be provided.

[0167] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0168] Embodiment 3 In this embodiment, a transistor that can be used for a semiconductor device according to one embodiment of the present invention will be described.

[0169] <Transistor Structural Example 1> Fig. 21A is a plan view of a transistor 200A that can be used for a semiconductor device of one embodiment of the present invention. Fig. 21B is a cross-sectional view taken along the line A1-A2 indicated by a dashed dotted line in Fig. 21A. Fig. 21C is a cross-sectional view taken along the line A3-A4 indicated by a dashed dotted line in Fig. 21A. Note that Fig. 21A is a cross-sectional view of the transistor 200A in the channel length direction, and Fig. 21C is a cross-sectional view of the transistor 200A in the channel width direction.

[0170] 21A to 21C , the transistor 200A includes a semiconductor layer 520a disposed on a substrate 201, a semiconductor layer 520b disposed on the semiconductor layer 520a, conductive layers 542a and 542b disposed spaced apart from each other on the semiconductor layer 520b, an insulating layer 580 disposed on the conductive layers 542a and 542b and having an opening formed between the conductive layers 542a and 542b, a conductive layer 560 disposed in the opening, an insulating layer 550 disposed among the semiconductor layer 520b, the conductive layers 542a, 542b, and the insulating layer 580, and the conductive layer 560, and a semiconductor layer 520c disposed among the semiconductor layer 520b, the conductive layers 542a, 542b, the insulating layer 580, and the insulating layer 550.

[0171] 21B and 21C, the upper surface of the conductive layer 560 is substantially coincident with the upper surfaces of the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580. Note that hereinafter, the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c may be collectively referred to as the semiconductor layer 520.

[0172] The conductive layer 542a functions as one of a source electrode and a drain electrode of the transistor 200A. The conductive layer 542b functions as the other of the source electrode and the drain electrode of the transistor 200A. In this specification, the conductive layers 542a and 542b may be collectively referred to as conductive layers 542.

[0173] 21A to 21C , an insulating layer 554 is disposed between the insulating layer 524, the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542a, the conductive layer 542b, and the insulating layer 580. The insulating layer 554 is in contact with the side surface of the semiconductor layer 520c, the top surface and side surface of the conductive layer 542a, the top surface and side surface of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524.

[0174] The channel of the transistor 200A is formed in a region of the semiconductor layer 520 that overlaps with the conductive layer 560. Therefore, the channel length L of the transistor 200A can be expressed as the length of the conductive layer 560 in the X direction in the region that overlaps with the semiconductor layer 520. The channel of the transistor 200A is formed between a region that functions as a source and a region that functions as a drain of the semiconductor layer 520. Therefore, the channel length L of the transistor 200A can be expressed as the distance from the end of the conductive layer 542a to the end of the conductive layer 542b that face each other.

[0175] The channel width W of the transistor 200A can be expressed as the length of the semiconductor layer 520 in the Y direction in a region where the semiconductor layer 520 overlaps with the conductive layer 560 .

[0176] Although the transistor 200A has a three-layer structure including the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c in the channel formation region and its vicinity, the present invention is not limited to this. For example, a two-layer structure including the semiconductor layer 520b and the semiconductor layer 520c or a stacked structure of four or more layers may be used. Furthermore, each of the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c may also have a stacked structure of two or more layers.

[0177] For example, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer 520, and the semiconductor layer 520c has a stacked structure consisting of a first metal oxide and a second metal oxide on the first metal oxide, it is preferable that the first metal oxide has a composition similar to that of the semiconductor layer 520b, and the second metal oxide has a composition similar to that of the semiconductor layer 520a.

[0178] Here, the conductive layer 560 functions as the gate electrode of the transistor, and the conductive layers 542a and 542b function as source and drain electrodes, respectively. As described above, the conductive layer 560 is formed so as to fill the opening of the insulating layer 580 and the region sandwiched between the conductive layers 542a and 542b. Here, the conductive layers 560, 542a, and 542b are arranged in a self-aligned manner with respect to the opening of the insulating layer 580. That is, in the transistor 200A, the gate electrode can be arranged between the source and drain electrodes in a self-aligned manner. Therefore, the conductive layer 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 200A. This reduces the area occupied by the semiconductor device. Furthermore, the integration degree of the semiconductor device can be increased.

[0179] 21A to 21C , the conductive layer 560 includes a conductive layer 560a provided inside the insulating layer 550 and a conductive layer 560b provided so as to be embedded inside the conductive layer 560a. Although the conductive layer 560 in the transistor 200A has a two-layer stacked structure, the present invention is not limited to this. For example, the conductive layer 560 can have a single-layer structure or a stacked structure of three or more layers.

[0180] The transistor 200A includes an insulating layer 202 disposed on the substrate 201, an insulating layer 514 disposed on the insulating layer 202, an insulating layer 516 disposed on the insulating layer 514, a conductive layer 505 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 505, and an insulating layer 524 disposed on the insulating layer 522. In addition, a semiconductor layer 520a is disposed on the insulating layer 524.

[0181] Further, insulating layers 574 and 581 functioning as interlayer films are provided over the transistor 200A. The insulating layer 574 is provided in contact with top surfaces of the conductive layer 560, the insulating layer 550, the semiconductor layer 520c, and the insulating layer 580.

[0182] When an oxide semiconductor is used for the semiconductor layer 520, an insulating layer having a function of suppressing diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like) is preferably used for the insulating layer 522, the insulating layer 554, and the insulating layer 574. For example, an insulating layer having lower hydrogen permeability than the insulating layer 524, the insulating layer 550, and the insulating layer 580 is preferably used for the insulating layer 522, the insulating layer 554, and the insulating layer 574. For example, silicon nitride, silicon nitride oxide, or the like can be used.

[0183] Furthermore, an insulating layer having a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like) is preferably used for the insulating layer 522 and the insulating layer 554. For example, an insulating layer having lower oxygen permeability than the insulating layer 524, the insulating layer 550, and the insulating layer 580 is preferably used for the insulating layer 522 and the insulating layer 554. For example, silicon nitride, silicon nitride oxide, or the like can be used.

[0184] Here, the insulating layer 524, the semiconductor layer 520, and the insulating layer 550 are sandwiched between the insulating layer 522 and the insulating layer 574. Therefore, impurities such as hydrogen and excess oxygen contained in layers above the insulating layer 574 and below the insulating layer 522 can be prevented from diffusing into the insulating layer 524, the semiconductor layer 520, and the insulating layer 550.

[0185] 21B shows an example in which a conductive layer 545 (conductive layer 545a and conductive layer 545b) connected to the transistor 200A and functioning as a plug is provided. Note that an example is shown in which an insulating layer 541 (insulating layer 541a and insulating layer 541b) is provided in contact with the side surface of the conductive layer 545 functioning as a plug. That is, the insulating layer 541 is provided in contact with the inner walls of the openings of the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. In addition, in FIG. 21B, a first conductive layer of the conductive layer 545 is provided in contact with the side surface of the insulating layer 541, and a second conductive layer of the conductive layer 545 is provided further inside.

[0186] Here, the height of the top surface of the conductive layer 545 can be made approximately the same as the height of the top surface of the insulating layer 581. Note that although the transistor 200A shows a structure in which the first conductive layer of the conductive layer 545 and the second conductive layer of the conductive layer 545 are stacked, the present invention is not limited to this. For example, the conductive layer 545 can also have a single layer structure or a stacked structure of three or more layers.

[0187] Furthermore, the thickness of the semiconductor layer 520b in a region that does not overlap with the conductive layer 542 may be thinner than the thickness of the region that overlaps with the conductive layer 542. This is achieved by removing part of the top surface of the semiconductor layer 520b when forming the conductive layers 542a and 542b. When a conductive film that will become the conductive layer 542 is formed on the top surface of the semiconductor layer 520b, a low-resistance region may be formed near the interface with the conductive film. In this way, by removing the low-resistance region of the semiconductor layer 520b that is located between the conductive layer 542a and the conductive layer 542b in a plan view, it is possible to prevent a channel from being formed in that region.

[0188] Next, the detailed configuration of the transistor 200A will be described.

[0189] The conductive layer 505 is arranged to have a region overlapping with the conductive layer 560 with the semiconductor layer 520 interposed therebetween. By providing the conductive layer 505 so as to be embedded in the insulating layer 516, unevenness on the top surfaces of the conductive layer 505 and the insulating layer 516 can be reduced, and coverage with layers formed in later steps can be improved.

[0190] The conductive layer 505 includes a conductive layer 505a, a conductive layer 505b, and a conductive layer 505c. The conductive layer 505a is provided in contact with the bottom and sidewall of an opening provided in the insulating layer 516. The conductive layer 505b is provided so as to fill a recess formed in the conductive layer 505a. The top surface of the conductive layer 505b is lower than the top end (the highest position as viewed from the substrate surface) of the conductive layer 505a and the top surface of the insulating layer 516. The conductive layer 505c is provided in contact with the top surface of the conductive layer 505b and the side surface of the conductive layer 505a. The height of the top surface of the conductive layer 505c is equal to or approximately equal to the height of the top end of the conductive layer 505a and the height of the top surface of the insulating layer 516. In other words, the conductive layer 505b is surrounded by the conductive layers 505a and 505c.

[0191] In the case where an oxide semiconductor is used for the semiconductor layer 520, the conductive layer 505a and the conductive layer 505c can be formed of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N ２ O, NO, NO ２ It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, or a conductive material that has a function of suppressing the diffusion of oxygen.

[0192] By using a conductive material that can reduce hydrogen diffusion for the conductive layers 505a and 505c, impurities such as hydrogen contained in the conductive layer 505b can be prevented from diffusing into the semiconductor layer 520 through the insulating layer 524 or the like. Furthermore, by using a conductive material that can reduce oxygen diffusion for the conductive layers 505a and 505c, it is possible to prevent the conductive layer 505b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can reduce oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductive layer 505a can be formed as a single layer or a stack of any of the above conductive materials. For example, titanium nitride can be used for the conductive layer 505a.

[0193] The conductive layer 505b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 505b may be formed using tungsten. When the conductive layer 560 is used as a gate electrode, the conductive layer 505 functions as a back gate electrode.

[0194] The conductive layer 505 is preferably provided to be larger than the channel formation region in the semiconductor layer 520. In particular, as shown in Fig. 21C, the conductive layer 505 preferably extends to a region outside the end portion intersecting with the channel width direction of the semiconductor layer 520. In other words, the conductive layer 505 and the conductive layer 560 preferably overlap with each other with an insulating layer interposed therebetween on the outside of the side surface of the semiconductor layer 520 in the channel width direction.

[0195] With the above structure, the channel formation region of the semiconductor layer 520 can be surrounded by the electric field of the conductive layer 560 functioning as a gate electrode and the electric field of the conductive layer 505 functioning as a back gate electrode.

[0196] The conductive layer 505 can be used as a wiring by extending it beyond the end of the semiconductor layer 520. However, without being limited thereto, a conductive layer that functions as a wiring can also be provided under the conductive layer 505.

[0197] The insulating layer 514 may be formed using an insulating material that functions as a barrier insulating film that prevents impurities such as water or hydrogen from diffusing from the substrate side to the transistor 200A. Therefore, the insulating layer 514 may be formed using an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, the insulating layer 514 may be formed using an insulating material that has a function of preventing the diffusion of oxygen (i.e., through which the oxygen is less likely to permeate).

[0198] For example, aluminum oxide, silicon nitride, or the like is used for the insulating layer 514. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulating layer 514 to the transistor 200A side. Alternatively, it can prevent oxygen contained in the insulating layer 524 or the like from diffusing to the substrate side of the insulating layer 514.

[0199] The insulating layer 516, the insulating layer 580, and the insulating layer 581, which function as interlayer films, may be formed using an insulating material having a lower dielectric constant than the insulating layer 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, the insulating layer 516, the insulating layer 580, and the insulating layer 581 may be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0200] When the conductive layer 505 is used as a gate electrode, the insulating layers 522 and 524 function as gate insulating layers.

[0201] Here, the insulating layer 524 in contact with the semiconductor layer 520 preferably contains excess oxygen. For example, silicon oxide, silicon oxynitride, or the like may be used as appropriate for the insulating layer 524. By providing an insulating layer containing oxygen in contact with the semiconductor layer 520, oxygen vacancies in the semiconductor layer 520 are reduced, and the reliability of the transistor 200A is improved.

[0202] 21C , the thickness of the insulating layer 524 in a region that does not overlap with the insulating layer 554 and the semiconductor layer 520b may be thinner than the thickness of the other region. The thickness of the insulating layer 524 in a region that does not overlap with the insulating layer 554 and the semiconductor layer 520b is preferably set to a thickness that allows sufficient diffusion of the oxygen.

[0203] The insulating layer 522 is made of a material that functions as a barrier insulating film that suppresses diffusion of impurities such as water or hydrogen from the substrate side into the transistor 200A, similar to the insulating layer 514. For example, the insulating layer 522 is made of a material that has lower hydrogen permeability than the insulating layer 524. By surrounding the insulating layer 524, the semiconductor layer 520, the insulating layer 550, and the like with the insulating layer 522, the insulating layer 554, and the insulating layer 574, impurities such as water or hydrogen can be suppressed from entering the transistor 200A from the outside.

[0204] Furthermore, a material having a function of suppressing oxygen diffusion (the above-mentioned oxygen is less likely to permeate) is preferably used for the insulating layer 522. For example, a material having lower oxygen permeability than the insulating layer 524 is used for the insulating layer 522. The insulating layer 522 has a function of suppressing the diffusion of oxygen and impurities, so that oxygen diffusing from the semiconductor layer 520 toward the substrate can be reduced. Furthermore, reaction of the conductive layer 505 with oxygen contained in the insulating layer 524 or the semiconductor layer 520 can be suppressed.

[0205] An insulating layer containing an oxide of one or both of aluminum and hafnium, which are insulating materials, may be used as the insulating layer 522. Examples of the insulating layer containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxide containing aluminum and hafnium (hafnium aluminate). When the insulating layer 522 is formed using such a material, the insulating layer 522 functions as a layer that suppresses oxygen release from the semiconductor layer 520 and the intrusion of impurities such as hydrogen into the semiconductor layer 520 from the periphery of the transistor 200A.

[0206] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to the insulating layer 522. Alternatively, the insulating layer 522 can be subjected to nitriding treatment. Alternatively, silicon oxide, silicon oxynitride, or silicon nitride can be stacked on the insulating layer 522. For example, the insulating layer 522 can have a three-layer structure in which silicon nitride, silicon oxide, and aluminum oxide are stacked in this order.

[0207] The insulating layer 522 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), or strontium titanate (SrTiO ３ ), (Ba,Sr)TiO ３An insulating layer containing a so-called high-k material such as BST can be used as a single layer or a laminate. As transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulating layers. By using a high-k material for the insulating layer that functions as the gate insulating layer, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0208] Note that each of the insulating layer 522 and the insulating layer 524 can have a stacked structure of two or more layers. In this case, the insulating layer 522 and the insulating layer 524 are not limited to a stacked structure made of the same material, and can have a stacked structure made of different materials.

[0209] The semiconductor layer 520 includes a semiconductor layer 520a, a semiconductor layer 520b on the semiconductor layer 520a, and a semiconductor layer 520c on the semiconductor layer 520b. By providing the semiconductor layer 520a below the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed below the semiconductor layer 520a to the semiconductor layer 520b. Furthermore, by providing the semiconductor layer 520c on the semiconductor layer 520b, it is possible to suppress the diffusion of impurities from structures formed above the semiconductor layer 520c to the semiconductor layer 520b.

[0210] When an oxide semiconductor is used for the semiconductor layer 520, the semiconductor layer 520 preferably has a stacked structure of multiple oxide layers with different atomic ratios of metal atoms. For example, when the semiconductor layer 520 includes at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the semiconductor layer 520a to the number of atoms of all elements constituting the semiconductor layer 520a is made higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520a to In is made higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In. Here, the semiconductor layer 520c can use the metal oxide used for the semiconductor layer 520a or the semiconductor layer 520b.

[0211] The energy of the conduction band minimum of the semiconductor layer 520a and the semiconductor layer 520c is preferably higher than the energy of the conduction band minimum of the semiconductor layer 520b. In other words, the electron affinity of the semiconductor layer 520a and the semiconductor layer 520c is preferably lower than the electron affinity of the semiconductor layer 520b. In this case, the semiconductor layer 520c may be made of a metal oxide that can be used for the semiconductor layer 520a. Specifically, the ratio of the number of atoms of the element M contained in the semiconductor layer 520c to the number of atoms of all elements constituting the semiconductor layer 520c is preferably higher than the ratio of the number of atoms of the element M contained in the semiconductor layer 520b to the number of atoms of all elements constituting the semiconductor layer 520b. Furthermore, the atomic ratio of the element M contained in the semiconductor layer 520c to In is preferably higher than the atomic ratio of the element M contained in the semiconductor layer 520b to In.

[0212] Here, the energy level of the conduction band minimum changes gradually at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c. In other words, the energy level of the conduction band minimum at the junction between the semiconductor layer 520a, the semiconductor layer 520b, and the semiconductor layer 520c changes continuously or can be said to be a continuous junction. To achieve this, it is preferable that the defect level density of the mixed layer formed at the interface between the semiconductor layer 520a and the semiconductor layer 520b and the interface between the semiconductor layer 520b and the semiconductor layer 520c is low.

[0213] Specifically, the semiconductor layers 520a and 520b, and the semiconductor layers 520b and 520c, have a common element other than oxygen (as a main component), thereby forming a mixed layer with a low defect level density. For example, when the semiconductor layer 520b is an In—Ga—Zn oxide, the semiconductor layers 520a and 520c can be made of In—Ga—Zn oxide, Ga—Zn oxide, gallium oxide, or the like. The semiconductor layer 520c can also have a stacked structure. For example, a stacked structure of In—Ga—Zn oxide and Ga—Zn oxide on the In—Ga—Zn oxide, or a stacked structure of In—Ga—Zn oxide and gallium oxide on the In—Ga—Zn oxide can be used. In other words, a stacked structure of In—Ga—Zn oxide and an oxide not containing In can be used as the semiconductor layer 520c.

[0214] Specifically, the semiconductor layer 520a may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of 1:1:0.5 or thereabouts. The semiconductor layer 520b may be made of a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of 3:1:2 or thereabouts, or an atomic ratio of 1:1:1 or thereabouts. The semiconductor layer 520c may be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or thereabouts, or an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, or an atomic ratio of Ga:Zn=2:1 or thereabouts, or an atomic ratio of Ga:Zn=2:5 or thereabouts. Specific examples of the semiconductor layer 520c having a stacked structure include a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or the vicinity thereof and Ga:Zn=2:1 [atomic ratio] or the vicinity thereof, a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or the vicinity thereof and Ga:Zn=2:5 [atomic ratio] or the vicinity thereof, and a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or the vicinity thereof and gallium oxide.

[0215] In this case, the main carrier path is the semiconductor layer 520b. By configuring the semiconductor layers 520a and 520c as described above, the defect state density at the interface between the semiconductor layers 520a and 520b and the interface between the semiconductor layers 520b and 520c can be reduced. This reduces the effect of interface scattering on carrier conduction, allowing the transistor 200A to achieve high on-state current and high frequency characteristics. Note that if the semiconductor layer 520c has a stacked structure, in addition to the effect of reducing the defect state density at the interface between the semiconductor layers 520b and 520c, it is expected that the diffusion of constituent elements of the semiconductor layer 520c toward the insulating layer 550 can be suppressed. More specifically, since the semiconductor layer 520c has a stacked structure and an oxide not containing In is located above the stacked structure, it is possible to suppress In diffusion toward the insulating layer 550. The insulating layer 550 functions as a gate insulating layer, and diffusion of In can cause poor transistor characteristics. Therefore, by forming the semiconductor layer 520c into a stacked structure, a highly reliable semiconductor device can be provided.

[0216] A conductive layer 542 (a conductive layer 542a and a conductive layer 542b) functioning as a source electrode and a drain electrode is provided over the semiconductor layer 520b. When an oxide semiconductor is used for the semiconductor layer 520b, the conductive layer 542 is preferably made of a conductive material that is not easily oxidized or that maintains its conductivity even when it absorbs oxygen.

[0217] A region of the semiconductor layer 520 in contact with the conductive layer 542 functions as a source region or a drain region of the transistor 200A. Here, the region between the conductive layer 542a and the conductive layer 542b is formed to overlap with the opening of the insulating layer 580. This allows the conductive layer 560 to be disposed in a self-aligned manner between the conductive layer 542a and the conductive layer 542b.

[0218] The insulating layer 550 functions as a gate insulating layer. The insulating layer 550 is disposed in contact with the top surface of the semiconductor layer 520c. The insulating layer 550 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. For example, silicon oxide or silicon oxynitride is used as the insulating layer 550.

[0219] The insulating layer 550 is formed using an insulating material in which the concentration of impurities such as water or hydrogen is reduced, similarly to the insulating layer 524. The thickness of the insulating layer 550 is greater than or equal to 1 nm and less than or equal to 20 nm.

[0220] A metal oxide may be provided between the insulating layer 550 and the conductive layer 560. The metal oxide suppresses oxygen diffusion from the insulating layer 550 to the conductive layer 560. This can suppress oxidation of the conductive layer 560 due to oxygen contained in the insulating layer 550.

[0221] Although the conductive layer 560 is shown as a two-layer structure in FIGS. 21A to 21C, a single-layer structure or a stacked structure of three or more layers can also be used.

[0222] The conductive layer 560a may be formed using the above-described conductive layer having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms, or may be formed using a conductive material having a function of suppressing diffusion of oxygen.

[0223] The conductive layer 560a has a function of suppressing oxygen diffusion, which can suppress a decrease in conductivity due to oxidation of the conductive layer 560b caused by oxygen contained in the insulating layer 550. Examples of conductive materials that can suppress oxygen diffusion include tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0224] The conductive layer 560b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, since the conductive layer 560 also functions as a wiring, a conductive layer with high conductivity may be used. For example, a conductive material containing tungsten, copper, or aluminum as a main component may be used. Furthermore, the conductive layer 560b may have a layered structure. For example, the conductive layer 560b may have a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0225] 21B and 21C , in a region of the semiconductor layer 520b that does not overlap with the conductive layer 542, in other words, in the channel formation region of the semiconductor layer 520, the side surface of the semiconductor layer 520 is arranged to be covered with the conductive layer 560. This makes it easier for the electric field of the conductive layer 560, which functions as the gate electrode of the transistor 200A, to act on the side surface of the semiconductor layer 520. This increases the on-state current of the transistor 200A and improves its frequency characteristics.

[0226] Like the insulating layer 514, the insulating layer 554 is made of an insulating material that prevents impurities such as water or hydrogen from diffusing from the insulating layer 580 side into the transistor 200A. For example, the insulating layer 554 is made of an insulating material that has lower hydrogen permeability than the insulating layer 524. Furthermore, as shown in FIGS. 21B and 21C , the insulating layer 554 is provided in contact with the side surfaces of the semiconductor layer 520c, the top and side surfaces of the conductive layer 542a, the top and side surfaces of the conductive layer 542b, the side surfaces of the semiconductor layer 520a and the semiconductor layer 520b, and the top surface of the insulating layer 524. This structure can prevent hydrogen contained in the insulating layer 580 from penetrating into the semiconductor layer 520 from the top surfaces or side surfaces of the conductive layer 542a, the conductive layer 542b, the semiconductor layer 520a, the semiconductor layer 520b, and the insulating layer 524.

[0227] Furthermore, an insulating material that has a function of suppressing oxygen diffusion (is less permeable to oxygen) is used for the insulating layer 554. For example, an insulating material that has lower oxygen permeability than the insulating layer 580 or the insulating layer 524 is used for the insulating layer 554.

[0228] When an oxide semiconductor is used for the semiconductor layer 520, the insulating layer 554 can be formed by a sputtering method. By forming the insulating layer 554 by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulating layer 524 near a region in contact with the insulating layer 554. This allows oxygen to be supplied from this region into the semiconductor layer 520 through the insulating layer 524. The insulating layer 554 has a function of suppressing upward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 to the insulating layer 580. The insulating layer 522 has a function of suppressing downward diffusion of oxygen, thereby preventing oxygen from diffusing from the semiconductor layer 520 toward the substrate. In this manner, oxygen is supplied to the channel formation region of the semiconductor layer 520. This reduces oxygen vacancies in the semiconductor layer 520, thereby preventing the transistor from becoming normally on.

[0229] For example, an insulating layer containing an oxide of one or both of aluminum and hafnium is formed as the insulating layer 554. Note that as the insulating layer containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium, or the like can be used.

[0230] The insulating layer 580 is provided over the insulating layer 524, the semiconductor layer 520, and the conductive layer 542 with the insulating layer 554 interposed therebetween. For example, the insulating layer 580 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly suitable because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are particularly suitable because they can easily form a region containing oxygen that is released by heating.

[0231] The insulating layer 574, like the insulating layer 514, is formed using an insulating material that functions as a barrier insulating film that suppresses diffusion of impurities such as water or hydrogen from above into the insulating layer 580. The insulating layer 574 is formed using an insulating material that can be used for the insulating layer 514, the insulating layer 554, and the like, for example.

[0232] 21A to 21C show an example in which an insulating layer 581 functioning as an interlayer film is provided over the insulating layer 574. As the insulating layer 581, an insulating material in which the concentration of impurities such as water or hydrogen is reduced is used, similar to the insulating layer 524.

[0233] Conductive layers 545a and 545b are disposed in openings formed in insulating layers 581, 574, 580, and 554. The conductive layers 545a and 545b are provided so as to sandwich the conductive layer 560. Note that when viewed from a direction perpendicular to the Z direction, the positions of the upper surfaces of the conductive layers 545a and 545b preferably coincide or substantially coincide with the position of the upper surface of the insulating layer 581.

[0234] Note that an insulating layer 541a is provided in contact with the inner walls of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545a is formed in contact with the side surface of the insulating layer 541a. A conductive layer 542a is located in at least a part of the bottom of the opening, and the conductive layer 545a is in contact with the conductive layer 542a. Similarly, an insulating layer 541b is provided in contact with the inner walls of the openings of the insulating layer 581, the insulating layer 574, the insulating layer 580, and the insulating layer 554, and a first conductive layer of the conductive layer 545b is formed in contact with the side surface of the insulating layer 541b. A conductive layer 542b is located in at least a part of the bottom of the opening, and the conductive layer 545b is in contact with the conductive layer 542b.

[0235] The conductive layers 545a and 545b may be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Each of the conductive layers 545a and 545b can also have a stacked structure of two or more layers.

[0236] When the conductive layer 545 has a stacked structure, a conductive layer having a function of suppressing diffusion of impurities such as water or hydrogen may be used for the conductive layers in contact with the semiconductor layer 520a, the semiconductor layer 520b, the conductive layer 542, the insulating layer 554, the insulating layer 580, the insulating layer 574, and the insulating layer 581. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is used. By using such a conductive material, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b. Furthermore, impurities such as water or hydrogen can be prevented from diffusing from above the insulating layer 581 into the semiconductor layer 520 through the conductive layers 545a and 545b.

[0237] The insulating layer 541a and the insulating layer 541b may be, for example, an insulating layer that can be used for the insulating layer 554. The insulating layer 541a and the insulating layer 541b are provided in contact with the insulating layer 554, and thus can prevent impurities such as water or hydrogen from the insulating layer 580 or the like from diffusing into the semiconductor layer 520 through the conductive layers 545a and 545b. Furthermore, oxygen contained in the insulating layer 580 can be prevented from being absorbed by the conductive layers 545a and 545b.

[0238] <Transistor Configuration Example 2> A variation of the transistor 200A shown in FIG. 21 is shown in FIG. 22. FIG. 22A is a plan view of a transistor 200B which is a variation of the transistor 200A. FIG. 22B is a cross-sectional view taken along the line A1-A2 indicated by the dashed dotted line in FIG. 22A. FIG. 22C is a cross-sectional view taken along the line A3-A4 indicated by the dashed dotted line in FIG. 22A. Because the transistor 200B is a variation of the transistor 200A, differences between the transistor 200B and the transistor 200A will be mainly described.

[0239] The transistor 200B has a structure in which the semiconductor layer 520c and the conductive layer 505c are removed from the structure of the transistor 200A. Reducing the number of components of the transistor can reduce production costs. Furthermore, reducing the number of components of the transistor shortens the manufacturing process, thereby improving manufacturing yield.

[0240] Furthermore, the transistor 200B has a region where the insulating layer 554 and the insulating layer 522 are in contact with each other outside the semiconductor layer 520, and the side surface of the insulating layer 524 is covered with the insulating layer 554. When an oxide semiconductor is used for the semiconductor layer 520, covering the side surface of the insulating layer 524 with the insulating layer 554 not only prevents oxygen from diffusing to the outside through the insulating layer 524 but also prevents excessive oxygen from being supplied to the semiconductor layer 520 from the insulating layer 524 side.

[0241] Note that an insulating layer is preferably provided between the insulating layer 580, the insulating layer 554, the conductive layer 542, and the semiconductor layer 520b and the insulating layer 550. Aluminum oxide, hafnium oxide, or the like is preferably used for the insulating layer. By providing the insulating layer, it is possible to suppress desorption of oxygen from the semiconductor layer 520 to the insulating layer 550 side, excessive supply of oxygen from the insulating layer 550 side to the semiconductor layer 520, oxidation of the conductive layer 542, and the like.

[0242] <Constituent Materials of Transistor> Next, constituent materials that can be used for the transistor 200 (transistor 200A and transistor 200B) will be described.

[0243] [Substrate] When a transistor is provided on a substrate, the material used for the substrate is not particularly limited. The material used for the substrate is determined depending on the purpose, taking into consideration the presence or absence of light transparency, heat resistance sufficient to withstand heat treatment, and the like. For example, an insulating layer substrate, a semiconductor substrate, or a conductive layer substrate can be used as the substrate. Examples of insulating layer substrates that can be used include glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (such as yttria-stabilized zirconia substrates). Furthermore, semiconductor substrates, flexible substrates, resin substrates, and the like can also be used as the substrate.

[0244] Examples of semiconductor substrates include semiconductor substrates made of silicon, germanium, or the like, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having an insulating layer region inside the aforementioned semiconductor substrate, such as SOI (Silicon On Insulator) substrates. Furthermore, the semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0245] Examples of conductive layer substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having metal nitrides and substrates having metal oxides. Furthermore, examples include substrates in which a conductive layer or a semiconductor layer is provided on an insulating layer substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive layer substrate.

[0246] Examples of materials that can be used for flexible substrates, resin substrates, etc. include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofiber.

[0247] By using the above materials for the substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is resistant to impact can be provided. Furthermore, by using the above materials for the substrate, a semiconductor device that is less likely to break can be provided. Furthermore, it is also possible to use a substrate on which elements are provided. Elements that can be provided on the substrate include capacitance elements, resistance elements, switching elements, light-emitting elements, memory elements, and the like.

[0248] [Insulating Layer] An inorganic insulating film is used for each of the insulating layers (insulating layer 202, insulating layer 516, insulating layer 522, insulating layer 524, insulating layer 541, insulating layer 554, insulating layer 580, insulating layer 574, insulating layer 581, etc.). Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An organic insulating film can also be used for an insulating layer included in a semiconductor device.

[0249] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen. The content of each element can be measured, for example, by Rutherford backscattering spectrometry (RBS).

[0250] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using high-k materials for the insulating layer that functions as the gate insulating layer allows for lower voltages during transistor operation while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is important to select materials according to the function of the insulating layer. Materials with a low dielectric constant also have high dielectric strength.

[0251] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0252] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low relative dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0253] [Conductive Layer] For the conductive layers (conductive layer 505, conductive layer 545, conductive layer 560, etc.) used in the transistor 200, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements, or an alloy combining the above metal elements, etc. As the alloy containing any of the above metal elements, a nitride of the alloy or an oxide of the alloy can also be used. For example, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide can also be used.

[0254] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, and nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, and ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (ITSO), indium zinc oxide (IZO®), and indium zinc oxide containing tungsten oxide. In this specification and elsewhere, a conductive layer formed using a conductive material containing oxygen may be referred to as an oxide conductive layer.

[0255] Conductive materials containing tungsten, copper or aluminum as a main component are preferred because they have high conductivity.

[0256] It is also possible to use a plurality of conductive layers formed from the above materials in a stacked state. For example, a stacked structure can be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. Also, a stacked structure can be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. Also, a stacked structure can be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0257] When an oxide semiconductor, which is a type of metal oxide, is used for the semiconductor layer 520, the conductive layers 542a and 542b are conductive layers in contact with the semiconductor layer 520. Therefore, a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductive layer), or a conductive material that has a function of suppressing oxygen diffusion can be used for each of the conductive layers 542a and 542b. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 542a and 542b.

[0258] By using a conductive material containing oxygen for the conductive layers 542a and 542b, the conductive layers 542a and 542b can maintain their conductivity even when they absorb oxygen. For example, even when an insulating layer containing excess oxygen is used as an insulating layer in contact with the conductive layers 542a and 542b, this is preferable because the conductive layers 542a and 542b can maintain their conductivity. For example, ITO, ITSO, IZO (registered trademark), or the like can be used for the conductive layers 542a and 542b.

[0259] [Semiconductor Layer] As the semiconductor layer, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. Using a single crystal semiconductor or a crystalline semiconductor for the semiconductor layer in which a channel is formed is preferable because it can suppress deterioration of transistor characteristics. As the semiconductor material, for example, a semiconductor made of an element such as silicon or germanium can be used. Alternatively, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, or a nitride semiconductor can be used. As the compound semiconductor, an organic material having semiconductor properties (also referred to as an "organic semiconductor"), a metal nitride having semiconductor properties (also referred to as a "nitride semiconductor"), or a metal oxide having semiconductor properties (also referred to as an "oxide semiconductor") can be used. Note that these semiconductor materials can contain impurities as dopants.

[0260] When silicon is used for the semiconductor layer, examples of silicon that can be used for the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon.

[0261] Two-dimensional materials that function as semiconductors can also be used as the semiconductor layer of a transistor. Two-dimensional materials, also known as layered materials, are a general term for a group of materials with a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. Layered materials have high electrical conductivity within a unit layer, i.e., high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity for the semiconductor layer, a transistor with a large on-state current can be provided.

[0262] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0263] [Metal Oxide Layer] The transistor 200 preferably includes an oxide semiconductor, which is a type of metal oxide, in the semiconductor layer 520 including a channel formation region. That is, the transistor 200 is preferably an OS transistor.

[0264] An OS transistor is a transistor that has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if the channel formation region in the metal oxide contains oxygen vacancies, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that the oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration in the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.

[0265] On the other hand, the source and drain regions in a metal oxide that functions as a semiconductor of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, and have a high carrier concentration and low resistance due to a high concentration of H or impurities such as hydrogen, nitrogen, or a metal element.

[0266] The band gap of the metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide functioning as a semiconductor and having a wide band gap for the semiconductor layer 520, the off-state current of the transistor 200 can be reduced. Because the off-state current of an OS transistor is low, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0267] A metal oxide that can be used for a semiconductor layer of an OS transistor preferably contains at least indium (In). The metal oxide preferably contains at least one of indium (In) and zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. The element M is a metal element or a metalloid element that has a high bond energy with oxygen, for example, a metal element or a metalloid element that has a higher bond energy with oxygen than indium.

[0268] Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, antimony, etc. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.

[0269] For example, examples of metal oxides that can be used for the semiconductor layer of an OS transistor include indium oxide (In oxide, indium oxide). Examples of the metal oxide include zinc oxide (Zn oxide, zinc oxide), indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as “GZO”), aluminum zinc oxide (Al—Zn oxide, also referred to as “AZO”), and indium. Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as "IGAZO" or "IAGZO"). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), and the like can be used.

[0270] Examples of the crystalline structure of metal oxides that function as semiconductors include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0271] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide that functions as a semiconductor, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0272] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0273] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased. Typically, by using single-crystal or polycrystalline indium oxide for the semiconductor layer, the field-effect mobility of the transistor can be significantly increased. Furthermore, a transistor using single-crystal or polycrystalline indium oxide for the semiconductor layer can achieve good frequency characteristics.

[0274] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0275] Embodiment 4 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0276] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0277] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0278] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 23A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 23B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0279] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 23B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 23A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 23A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 23A.

[0280] 23A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0281] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0282] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistance can be reduced to Ω·cm or less.

[0283] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0284] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 23A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0285] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0286] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0287] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0288] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0289] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0290] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0291] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0292] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0293] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0294] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 23C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0295] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0296] Furthermore, as shown in FIG. 23C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0297] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0298] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0299]

[0300] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0301] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0302] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0303] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0304] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0305] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0306] Embodiment 5 In this embodiment, an example of a stacked structure of a semiconductor device 100 according to one embodiment of the present invention will be described.

[0307] 24 shows an example of a stacked structure of the semiconductor device 100. FIG.

[0308] 24 illustrates a transistor 400 as an example of a transistor included in the first circuit 110. The transistor 400 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 400 can be either a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single crystal silicon substrate.

[0309] Here, in the transistor 400 shown in FIG. 24 , a semiconductor region 313 (a part of the substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 can be made of a material that adjusts the work function. Such a transistor 400 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may also be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but it is also possible to form a semiconductor film having a convex shape by processing an SOI substrate.

[0310] Note that the transistor 400 illustrated in FIG. 24 is just an example, and the structure is not limited to this example. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0311] The element layer 10 and the element layer 20 may be provided with a wiring layer provided with an interlayer film, wiring, plugs, etc. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring and cases where a part of the conductive layer functions as the plug.

[0312] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film in the element layer 10. Conductive layers 328 and 330 are embedded in the insulating layers 320, 322, 324, and 326. Note that the conductive layers 328 and 330 function as contact plugs or wirings.

[0313] Furthermore, the insulating layer functioning as an interlayer film preferably functions as a planarizing film that covers the uneven shape below it. For example, CMP treatment or the like can be performed to improve the planarity of the top surface of the insulating layer 322. By improving the planarity of the top surface of the interlayer film, the coverage of wiring and the like formed on the interlayer film can be improved.

[0314] A wiring layer can be provided over the insulating layer 326 and the conductive layer 330. For example, in FIG. 24 , an insulating layer 350, an insulating layer 382, ​​and an insulating layer 384 are stacked in this order over the insulating layer 326 and the conductive layer 330. A conductive layer 386 is formed in the insulating layer 350, the insulating layer 382, ​​and the insulating layer 384. The conductive layer 386 functions as a contact plug or a wiring.

[0315] 24 illustrates the transistor 121, the transistor 122, and the capacitor Cs included in the second circuit 120 formed in the element layer 20. In FIG. 24, the transistor 200B described in the above embodiment is used as the transistor 121 and the transistor 122. To reduce repetition of the description, description of the configuration of the transistor 200B will be omitted.

[0316] 24 , a conductive layer 368 is embedded in the insulating layer 281, the insulating layer 274, the insulating layer 280, the insulating layer 254, the insulating layer 222, the insulating layer 216, and the insulating layer 214. The conductive layer 368 functions as a contact plug or a wiring. In addition, a conductive layer 283, a conductive layer 284, and an insulating layer 282 are provided over the insulating layer 281. One of the source and drain of the transistor 121 is connected to a conductive layer 386 via the conductive layer 283, the conductive layer 368, or the like.

[0317] An insulating layer 285 is provided over the conductive layer 283, the conductive layer 284, and the insulating layer 282. A conductive layer 287 and an insulating layer 286 are provided over the insulating layer 285. A region where the conductive layer 284, the insulating layer 285, and the conductive layer 287 overlap with each other functions as a capacitor Cs.

[0318] A conductive layer 289 and an insulating layer 288 are provided over the conductive layer 287 and the insulating layer 286. A conductive layer 292 and an insulating layer 291 are provided over the conductive layer 289 and the insulating layer 288. An insulating layer 293 is provided over the conductive layer 292 and the insulating layer 291.

[0319] By providing the element layer 10 and the element layer 20 so that they overlap, the area occupied by the semiconductor device 100 can be reduced. Furthermore, by providing the transistor 400 and the transistor 121 or the transistor 122 so that they overlap, the length of the wiring connecting them can be shortened. Therefore, the parasitic capacitance and wiring resistance associated with the wiring are reduced, and the power consumption of the semiconductor device 100 can be reduced. Furthermore, since the signal propagation distance is shortened, the operating speed of the semiconductor device 100 can be increased.

[0320] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0321] Embodiment 6 In this embodiment, an example of a processing unit that can include a semiconductor device according to one embodiment of the present invention will be described.

[0322] 25 shows a block diagram of the arithmetic processing device 960. The arithmetic processing device 960 shown in FIG. 25 can be applied to, for example, a CPU. The arithmetic processing device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0323] The arithmetic processing device 960 shown in FIG. 25 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The arithmetic processing device 960 may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0324] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0325] The semiconductor device 100 can be used as a memory cell that constitutes a cache 999. As will be described later, the semiconductor device 100 can be stacked on the processor 960. In this case, the first circuit 110 of the semiconductor device 100 can be included in a part of the cache interface 989.

[0326] A cache 999 configured in the semiconductor device 100 can retain data using a first circuit 110 including Si transistors when power is supplied, and retain data using a second circuit 120 including OS transistors when power supply is stopped. The first circuit 110 including Si transistors has a faster operating speed than the second circuit 120 including OS transistors. By retaining data using the second circuit 120 when power supply is stopped, data written to the cache 999 can be retained even if power supply is stopped by power gating. Furthermore, data can be restored in a short time when power supply is resumed.

[0327] The arithmetic processing device 960 shown in FIG. 25 is merely an example of a simplified configuration, and actual arithmetic processing devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic processing device 960 shown in FIG. 25 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic processing device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0328] An instruction input to the arithmetic processing unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0329] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic processing unit 960 is executing a program. The register controller 997 generates addresses for registers 996 and performs read and write operations on the registers 996 depending on the state of the arithmetic processing unit 960.

[0330] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0331] 25 , a register controller 997 selects a data holding operation in the register 996 in accordance with an instruction from the ALU 991. That is, in the semiconductor device 100 functioning as a memory cell constituting the register 996, a selection is made between holding data in the first circuit 110 including a Si transistor and holding data in the second circuit 120 including an OS transistor. When holding data in the first circuit 110 is selected, power is supplied to the memory cells in the register 996. When holding data in the second circuit 120 is selected, data is rewritten to the second circuit 120, and power supply to the memory cells in the register 996 can be stopped.

[0332] The semiconductor device 100 and the arithmetic processing unit 960 can be provided overlapping each other. FIGS. 26A and 26B show perspective views of a semiconductor device 970A. For example, a memory cell array can be configured by arranging semiconductor devices 100 functioning as memory cells in a matrix. The semiconductor device 970A has an element layer 930 on which a memory cell array MCA is provided, on the arithmetic processing unit 960. The element layer 930 shown in FIG. 26A is provided with memory cell arrays MCA1, MCA2, and MCA3 as the memory cell arrays MCA. The arithmetic processing unit 960 and each memory cell array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic processing unit 960 and the element layer 930 are shown separately in FIG. 26B.

[0333] By overlapping the element layer 930 having the memory cell array and the arithmetic processing unit 960, the connection distance between them can be shortened. Therefore, the communication speed between them can be increased. In addition, the short connection distance can reduce power consumption.

[0334] As a method for stacking the element layer 930 having a memory cell array and the arithmetic processing unit 960, a method (also referred to as monolithic stacking) in which the element layer 930 having the memory cell array is stacked directly on the arithmetic processing unit 960 can be used, or a method in which the arithmetic processing unit 960 and the element layer 930 are formed on different substrates, the two substrates are bonded together, and connection is made using a through-via or a conductive film bonding technique (Cu-Cu bonding, etc.) can be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce the manufacturing cost.

[0335] The arithmetic processing unit 960 does not include a cache 999, and each of the memory cell arrays MCA1, MCA2, and MCA3 provided in the element layer 930 can be used as a cache. In this case, for example, the memory cell array MCA1 can be used as an L1 cache (also referred to as a level 1 cache), the memory cell array MCA2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory cell array MCA3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory cell arrays MCA, the memory cell array MCA3 has the largest capacity and is accessed least frequently. Furthermore, the memory cell array MCA1 has the smallest capacity and is accessed most frequently.

[0336] When the cache 999 provided in the arithmetic processing unit 960 is used as an L1 cache, each memory cell array MCA provided in the element layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0337] 26B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are also provided. The driving circuit 910L1 is connected to the memory cell array MCA1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory cell array MCA2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory cell array MCA3 via a connection electrode 940L3.

[0338] Although the number of memory cell arrays functioning as caches is three in this example, the number of memory cell arrays functioning as caches is not limited to three. The number of memory cell arrays functioning as caches can be one, two, or four or more.

[0339] When the memory cell array MCA1 is used as a cache, the drive circuit 910L1 can be configured to function as part of the cache interface 989, or the drive circuit 910L1 can be configured to be connected to the cache interface 989. Similarly, the drive circuit 910L2 and the drive circuit 910L3 can also be configured to function as part of the cache interface 989, or the drive circuit 910L3 can be configured to be connected to the cache interface 989.

[0340] It is also possible to provide an element layer 930 having one memory cell array MCA overlapping the arithmetic processing device 960. Fig. 27A shows a perspective view of a semiconductor device 970B.

[0341] In the semiconductor device 970B, one memory cell array MCA can be divided into multiple areas, each of which can be used for a different function. Fig. 27A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0342] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0343] It is also possible to stack a plurality of memory cell arrays. Figure 27B shows a perspective view of a semiconductor device 970C.

[0344] The semiconductor device 970C has an element layer 930L1 having a memory cell array MCA1 stacked on top of an element layer 930L2 having a memory cell array MCA2 stacked on top of that, and an element layer 930L3 having a memory cell array MCA3 stacked on top of that. The memory cell array MCA1, which is physically closest to the arithmetic processing unit 960, can be used as a higher-level cache, and the memory cell array MCA3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory cell array to be increased, thereby further improving processing power.

[0345] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0346] Embodiment 7 In this embodiment, a memory device 900 to which the semiconductor device 100 according to one embodiment of the present invention can be applied will be described. The semiconductor device 100 according to one embodiment of the present invention can be used as a memory cell.

[0347] FIG. 28A is a block diagram showing an example configuration of a memory device 900. FIG. 28B is a schematic perspective view of the memory device 900. The memory device 900 shown in FIG. 28A includes a drive circuit 910 and a memory cell array MCA. The memory cell array MCA includes a plurality of semiconductor devices 100 that function as memory cells. FIG. 28A shows an example in which the memory cell array MCA includes a plurality of semiconductor devices 100 arranged in a matrix of m rows and n columns (m and n are each integers of 2 or greater). In FIG. 28A, the semiconductor device 100 in the first row and first column is indicated as semiconductor device 100[1,1], and the semiconductor device 100 in the mth row and nth column is indicated as semiconductor device 100[m,n].

[0348] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0349] In the storage device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. The signals BW, CE, GW, clock signal CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside.

[0350] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 can also be generated by the control circuit 912.

[0351] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the memory device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0352] The voltage generation circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the clock signal CLK to the voltage generation circuit 928. For example, when an H-level signal is given as the signal WAKE, the clock signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0353] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cell array MCA, and includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0354] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cell array MCA, the function of reading data from the memory cell array MCA, the function of holding the read data, etc.

[0355] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell array MCA. The data (Dout) read from the memory cell array MCA by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. The output circuit 926 also has a function of outputting Dout to the outside of the memory device 900. The data output from the output circuit 926 is a signal RDA.

[0356] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this example, the high power supply potential of the memory device 900 is VDD, and the low power supply potential is GND (ground potential). VHM is a high power supply potential used to set the word line to a high level and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 28A, the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0357] 28B , the memory device 900 can be configured such that a drive circuit 910 is provided in the element layer 70, a memory cell array MCA is provided in the element layer 80, and the element layer 80 is stacked on the element layer 70. For example, a single-crystal silicon substrate can be used as the element layer 70, and the drive circuit 910 can be formed on the silicon substrate. By forming the channel formation region of the Si transistor included in the drive circuit 910 on the silicon substrate, a Si transistor having a single-crystal semiconductor in the channel formation region and having a high operating speed can be formed.

[0358] By stacking the element layer 70 including the drive circuit 910 and the element layer 80 including the memory cell array MCA, the signal propagation distance between the drive circuit 910 and the memory cell array MCA can be shortened. Therefore, the parasitic resistance and parasitic capacitance between the drive circuit 910 and the memory cell array MCA can be reduced, thereby reducing power consumption and signal delay. Furthermore, the memory device 900 can be miniaturized. Furthermore, the memory capacity per unit area can be increased.

[0359] It is also possible to provide a part of the semiconductor device 100 that functions as a memory cell in a part of the element layer 70. For example, it is possible to provide a first circuit 110 of the semiconductor device 100 in a part of the element layer 70 and a second circuit 120 in the element layer 80.

[0360] 28C , it is possible to provide a plurality of element layers 80 including memory cell arrays MCA stacked on an element layer 70 including a driver circuit 910. Fig. 28C shows an example in which k (k is an integer of 2 or more) element layers 80 are stacked on the element layer 70. In Fig. 28C , the first element layer 80 provided on the element layer 70 is indicated as element layer 80[1], and the kth element layer 80 is indicated as element layer 80[k].

[0361] For example, in a semiconductor device 100 in which multiple second circuits 120 are connected to one first circuit 110, it is also possible to provide the first circuit 110 in the element layer 70 and provide the second circuits 120 in some or all of the layers of the element layer 80, which has k layers.

[0362] Furthermore, it is preferable to use OS transistors as the transistors provided in the element layer 80. Because OS transistors are thin film transistors, they can easily be provided overlapping the element layer 70 as the element layer 80. In addition, as described above, OS transistors operate stably even in high-temperature environments and exhibit little fluctuation in characteristics. Therefore, even if a memory cell array MCA including OS transistors is provided overlapping a driver circuit 910 including Si transistors, the memory cell array MCA is less susceptible to heat generation from the driver circuit 910. This can improve the reliability of the memory device 900.

[0363] For example, an SOI substrate or the like can be used as the element layer 70. Examples of SOI substrates that can be used include a SIMOX (Separation by Implanted Oxygen) substrate formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer to a certain depth from the surface and eliminate defects that occur in the surface layer, a Smart Cut method in which a semiconductor substrate is cleaved by utilizing the growth of microvoids formed by hydrogen ion implantation through heat treatment, and an ELTRAN method (registered trademark: Epitaxial Layer Transfer). Si transistors fabricated using an SOI substrate have reduced parasitic capacitance and can achieve high-speed operation.

[0364] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0365] Embodiment 8 In this embodiment, an example of an applicability of a memory device including a semiconductor device 100 as a memory device according to one embodiment of the present invention will be described with reference to FIGS.

[0366] In semiconductor devices such as computers, various memory devices are used depending on the application. Figure 29 shows a conceptual diagram explaining the hierarchy of memory devices used in semiconductor devices. In Figure 29, the conceptual diagram explaining the hierarchy of memory devices is shown as a triangle, with memory devices located higher in the triangle being required to have a faster operating speed, and memory devices located lower in the triangle being required to have a larger memory capacity and a higher recording density.

[0367] In FIG. 29 , from the top layer of the triangle, there are shown memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs, cache memories (sometimes simply referred to as caches, and representative examples include L1, L2, and L3 caches), main memories such as DRAMs, and storage memories such as 3D NANDs and hard disks (also called HDDs: hard disk drives).

[0368] The memory embedded as a register in a processing unit such as a CPU, GPU, or NPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a high operating speed is required rather than a large storage capacity. Registers also have the function of storing setting information for the processing unit.

[0369] Cache memory has the function of duplicating and storing a portion of the data stored in DRAM. By duplicating frequently used data and storing it in cache memory, the speed of accessing the data can be increased. The storage capacity required for cache memory is smaller than that of DRAM, but it is required to have a faster operating speed than DRAM. In addition, data rewritten in cache memory is duplicated and supplied to DRAM.

[0370] 29 illustrates only up to the L3 cache as a cache memory, but the present invention is not limited to this. For example, a storage device according to one embodiment of the present invention can be used as a last level cache (LLC) or a final level cache (FLC), which are located at the lowest level of the cache.

[0371] DRAM has the function of storing programs, data, etc. read from 3D NAND. 3D NAND has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speed.

[0372] Hard disks have large capacity and are non-volatile. Instead of hard disks, solid state drives (SSDs) can be used.

[0373] By using the semiconductor device 100 in a memory device according to one embodiment of the present invention, it can be monolithically integrated with peripheral circuits. Furthermore, by using an OS transistor, it is possible to monolithically stack the semiconductor device 100 with the peripheral circuits. Therefore, this has advantages in terms of data access with the peripheral circuits. Furthermore, since the semiconductor device 100 can be stacked with the peripheral circuits, the degree of integration can be increased. Furthermore, the memory device according to one embodiment of the present invention can retain data for a long period of time. Therefore, when the memory device according to one embodiment of the present invention is used as a DRAM, the frequency of refresh can be reduced.

[0374] A storage device according to one embodiment of the present invention can be used for the Target2 area and the Target1 area illustrated in FIG. 29 of the storage device.

[0375] 29, Target1 includes a boundary area (Target1_1) between the DRAM and 3D NAND, and a boundary area (Target1_2) between the DRAM and cache (L1, L2, L3). Examples of Target1_2 include the LLC and FLC mentioned above.

[0376] A storage device including the semiconductor device 100 according to one embodiment of the present invention can also function as a DRAM. The storage device according to one embodiment of the present invention can retain data for a long time even when power supply is stopped. Therefore, by replacing a DRAM with a storage device according to one embodiment of the present invention, power consumption can be reduced. For example, power consumption can be reduced to half or less, preferably one-tenth or less, more preferably one-hundredth, and even more preferably one-thousandth or less, of that of a configuration using a DRAM. Therefore, the storage device according to one embodiment of the present invention is suitable for Target 1.

[0377] A memory device according to one embodiment of the present invention is particularly suitable for Target1_1, which is a region of Target1 that is rewritten relatively infrequently. By applying a memory device according to one embodiment of the present invention to Target1_1, the reliability of the semiconductor device can be improved. Furthermore, the degree of integration of the semiconductor device functioning as a memory device can be increased. Furthermore, the power consumption of the semiconductor device functioning as a memory device can be reduced.

[0378] Furthermore, the memory device according to one embodiment of the present invention has high operating speed and is advantageous in terms of data access, and is therefore suitable for Target1_2, which is rewritten more frequently than Target1. By applying the memory device according to one embodiment of the present invention to Target1_2, the computational efficiency of the semiconductor device can be improved and power consumption can be reduced.

[0379] Furthermore, a storage device using the semiconductor device 100 according to one embodiment of the present invention can be used as a register or a cache memory of a processing unit such as a CPU, a GPU, or an NPU. Furthermore, the storage device according to one embodiment of the present invention can be provided overlaid on the processing unit. A structure in which a processing unit and a storage device are stacked is called a monolithic stack. By forming the processing unit and the storage device in a monolithic stack, for example, power consumption required for data access between the processing unit and the storage device can be significantly reduced. Therefore, by deploying information processing devices including supercomputers (also called high performance computers (HPCs)), computers, servers, and the like to which such a configuration is applied throughout the world, global warming can be suppressed.

[0380] As described above, a memory device using the semiconductor device 100 according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs to memories in the boundary region between DRAMs and 3D NANDs.

[0381] At least a part of the configuration examples exemplified in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples or drawings.

[0382] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0383] Embodiment 9 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described. The memory device according to one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). The electronic components, electronic devices, mainframes, space equipment, and data centers using the memory device according to one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0384] [Electronic Component] FIG. 30A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 30A has memory device 710 in mold 711. Memory device 900 described in the above embodiment can be used as memory device 710. FIG. 30A omits some details in order to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are connected to electrode pads 713, and electrode pads 713 are connected to memory device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and connected on printed circuit board 702 to complete mounting substrate 704.

[0385] The memory device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration makes it possible to increase the operation speed of the interface between the processor and the memory.

[0386] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0387] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0388] The memory device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0389] 30B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of memory devices 710 provided on the interposer 731.

[0390] The electronic component 730 shows an example in which the memory device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a CPU, a GPU, an NPU, or an FPGA (Field Programmable Gate Array).

[0391] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0392] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are connected using the through electrodes. In addition, with a silicon interposer, a TSV can also be used as the through electrode.

[0393] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0394] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0395] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space corresponding to the width of the terminal pitch is required. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may become difficult to provide the many wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure can be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0396] It is also preferable to provide a heat sink (heat dissipation plate) overlapping the electronic component 730. When providing a heat sink, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 710 and the height of the semiconductor device 735.

[0397] In order to mount the electronic component 730 on another substrate, it is preferable to provide electrodes 733 on the bottom of the package substrate 732. Fig. 30B shows an example in which the electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. The electrodes 733 can also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0398] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0399] 31A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0400] 31B shows a perspective view of an example of a computer 5620. The computer 5620 has a motherboard 5630. The motherboard 5630 is provided with a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0401] Fig. 31C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629, etc., which are mounted on the board 5622. Note that Fig. 31C illustrates components other than electronic components 5626, 5627, and 5628.

[0402] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0403] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0404] The electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0405] The electronic components 5627 and 5628 have multiple terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0406] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for learning and inference in artificial intelligence, for example.

[0407] [Space Equipment] A semiconductor device according to one aspect of the present invention is suitable for space equipment.

[0408] A semiconductor device according to one embodiment of the present invention preferably includes an OS transistor. The change in electrical characteristics of an OS transistor due to radiation exposure is small. That is, because of its high radiation resistance, it is suitable for use in an environment where radiation may be incident. For example, an OS transistor is suitable for use in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification includes one or more of the thermosphere, the mesosphere, and the stratosphere.

[0409] Fig. 32A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 32A shows a planet 6804 in space as an example.

[0410] 32A, a battery management system (also referred to as a BMS) or a battery control circuit is preferably provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes less power and has high reliability even in space.

[0411] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0412] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0413] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0414] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has higher reliability than a Si transistor in an environment where radiation may be incident.

[0415] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0416] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention is suitable for space equipment such as a spaceship, a space capsule, and a space probe.

[0417] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0418] [Data Center] The semiconductor device according to one embodiment of the present invention is suitable for a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring the immutability of data. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0419] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of cooling equipment, etc. Therefore, it is possible to reduce the space required for the data center.

[0420] Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0421] Fig. 32B shows a storage system applicable to a data center. The storage system 6000 shown in Fig. 32B has a plurality of servers 6001sb as hosts 6001 (illustrated as Host Computers). It also has a plurality of storage devices 6003md as storage 6003 (illustrated as Storage). The host 6001 and storage 6003 are shown connected via a storage area network 6004 (illustrated as SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as Storage Controller).

[0422] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 can be connected to each other via a network.

[0423] Although the storage 6003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 6003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0424] The cache memory described above is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is stored in the cache memory in the storage control circuit 6002 and the storage 6003, and then output to the host 6001 or the storage 6003.

[0425] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0426] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention is expected to contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0427] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0428] ADDR: signal, BK[1]: terminal, BK[2]: terminal, BK[3]: terminal, BK: terminal, BW: signal, Cb: capacitance element, CE: signal, CK: terminal, CKB: terminal, CLK: clock signal, CLKB: inverted clock signal, Cs: capacitance element, GND: ground potential, GW: signal, IN[1]: terminal, IN[k]: terminal, IN: terminal, Ma: time, Mb: time, Mc: time, MCA: memory cell array, OUT: terminal, QB: terminal, QD: terminal, RDA: signal, RE[1]: terminal, RE[2]: terminal, RE[3]: terminal, RE: terminal, REout: terminal, RES : restore signal, RESB: inverted restore signal, SD: terminal, SEL: select signal, SN[1]: node, SN[2]: node, SN: node, TrP: transistor, TrQ: transistor, VDD: high power supply potential, VH: potential, VSS: low power supply potential, WAKE: signal, WDA: signal, 10: element layer, 20[1]: element layer, 20[2]: element layer, 20: element layer, 70: element layer, 80[1]: element layer, 80[k]: element layer, 80: element layer, 100[1,1]: semiconductor device, 100[m,n]: semiconductor device, 100: semiconductor device, 110: first circuit, 110A: First circuit, 110B: First circuit, 110C: First circuit, 110D: First circuit, 111: Inverter circuit, 112: Switch, 113: Inverter circuit, 114: Switch, 115: Inverter circuit, 116: Switch, 117: Switch, 118: Inverter circuit, 119: Inverter circuit, 120[1]: Second circuit, 120[2]: Second circuit, 120[3]: Second circuit, 120[k]: Second circuit, 120: Second circuit, 120A: Second circuit, 120A[1]: Second circuit, 120A[2]: Second circuit, 120A[k]: Second circuit, 120B: Second circuit, 1 20C: second circuit, 121: transistor, 122: transistor, 123: inverter circuit, 123A: inverter circuit, 123B: inverter circuit, 123C: inverter circuit, 123D: inverter circuit, 124: buffer circuit, 125: transistor, 126: transistor, 127: transistor, 128: transistor, 129: transistor, 130: selection circuit, 131: inverter circuit, 132: switch, 133: switch, 134: inverter circuit, 135: inverter circuit, 141: first latch circuit, 142: second latch circuit,150: semiconductor device, 160: edge detection circuit, 161: inverter circuit, 162: AND circuit, 163: resistive element, 164: capacitive element, 165: delay circuit, 200: transistor, 200A: transistor, 200B: transistor, 201: substrate, 202: insulating layer, 214: insulating layer, 216: insulating layer, 222: insulating layer, 254: insulating layer, 274: insulating layer, 280: insulating layer, 281: insulating layer, 282: insulating layer, 283: conductive layer, 284: conductive layer, 285: insulating layer, 286: insulating layer, 287: conductive layer, 288: insulating layer, 289: conductive layer, 291: insulating layer, 292: conductive layer, 293: insulating layer, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulating layer, 316: conductive layer, 320: insulating layer, 322: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer, 350: insulating layer, 368: conductive layer, 382: insulating layer, 384: insulating layer, 386: conductive layer, 400: transistor, 505: conductive layer, 505a: conductive layer, 505b: conductive layer, 505c: conductive layer, 514: insulating layer, 516: insulating layer, 520: semiconductor layer, 520a: semiconductor layer, 520b: semiconductor layer , 520c: semiconductor layer, 522: insulating layer, 524: insulating layer, 541: insulating layer, 541a: insulating layer, 541b: insulating layer, 542: conductive layer, 542a: conductive layer, 542b: conductive layer, 545: conductive layer, 545a: conductive layer, 545b: conductive layer, 550: insulating layer, 554: insulating layer, 560: conductive layer, 560a: conductive layer, 560b: conductive layer, 574: insulating layer, 580: insulating layer, 581: insulating layer, 700: electronic component, 702: printed circuit board, 704: mounting board, 710: storage device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: driver Dynamic circuit layer, 716: memory layer, 730: electronic components, 731: interposer, 732: package substrate, 733: electrodes, 735: semiconductor device, 900: memory device, 910: drive circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: element layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 960: arithmetic processing unit, 970A: semiconductor device, 970B: semiconductor device,970C: semiconductor device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller, 993: instruction decoder, 994: interrupt controller, 995: timing controller, 996: register, 997: register controller, 998: bus interface, 999: cache, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 562 4: connection terminal, 5625: connection terminal, 5626: electronic component, 5627: electronic component, 5628: electronic component, 5629: connection terminal, 5630: motherboard, 5631: slot, 6000: storage system, 6001: host, 6001sb: server, 6002: storage control circuit, 6003: storage, 6003md: storage device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device,

Claims

a first circuit, a second circuit, a third circuit, and an inverter circuit; the third circuit includes a first transistor, a second transistor, and a capacitive element; an output of the first circuit electrically connected to an input of the second circuit; an output portion of the second circuit electrically connected to an input portion of the inverter circuit; an output portion of the inverter circuit electrically connected to a first terminal of the first transistor; a second terminal of the first transistor is electrically connected to a first terminal of the capacitive element and a first terminal of the second transistor; The second terminal of the second transistor is electrically connected to the input of the second circuit. 　 In claim 1, The first circuit has a first switch electrically connected to an output section of the first circuit. 　 In claim 1, The second circuit has a second switch electrically connected to an input portion of the second circuit. 　 In any one of claims 1 to 3, The first transistor and the second transistor each include an oxide semiconductor in a semiconductor layer in which a channel is formed. 　 In claim 4, The semiconductor device wherein the oxide semiconductor contains indium. 　 In any one of claims 1 to 3, The first circuit and the second circuit each include a transistor containing silicon in a semiconductor layer in which a channel is formed. 　 In any one of claims 1 to 3, The semiconductor device wherein each of the first circuit and the second circuit functions as a latch circuit. 　 a first circuit, a second circuit, a plurality of third circuits, and an inverter circuit; each of the plurality of third circuits includes a first transistor, a second transistor, and a capacitance element; a first terminal of the second transistor is electrically connected to a first terminal of the capacitive element and a second terminal of the first transistor; an output of the first circuit electrically connected to an input of the second circuit; an output portion of the second circuit electrically connected to an input portion of the inverter circuit; a first terminal of the first transistor included in each of the plurality of third circuits is electrically connected to an output portion of the inverter circuit; The semiconductor device in which the second terminal of the second transistor included in each of the plurality of third circuits is electrically connected to the input portion of the second circuit. 　 In claim 8, The first circuit has a first switch electrically connected to an output section of the first circuit. 　 In claim 8, The second circuit has a second switch electrically connected to an input portion of the second circuit. 　 In any one of claims 8 to 10, The first transistor and the second transistor each include an oxide semiconductor in a semiconductor layer in which a channel is formed. 　 In claim 11, The semiconductor device wherein the oxide semiconductor contains indium. 　 In any one of claims 8 to 10, The first circuit and the second circuit each include a transistor containing silicon in a semiconductor layer in which a channel is formed. 　 In any one of claims 8 to 10, The semiconductor device wherein each of the first circuit and the second circuit functions as a latch circuit.

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