Enhancing test-control connectivity for clock gating

Abstract

Clock gating circuitry is often inserted within digital circuitry to optimize the circuit design for efficient power consumption. Example implementations provide for enhancing test-control connectivity for clock gating by using one or more multiplexers within testing circuitry to control test enable signals provided to the clock gating circuitry. In an example implementation, testing circuitry includes a first multiplexer (704-1) configured to receive a first test enablement signal (714-1) from a first test control circuit (702-1) and a second test enablement signal (714-2) from a second test control circuit (702-2). The first multiplexer is configured to provide the first test enablement signal to a first clock-gating cell responsive to a selection signal (716) having a first value and provide the second test enablement signal to the first clock-gating cell responsive to the selection signal having a second value. The multiplexer enables additional merging of clock-gating cells during the design phase.

Description

ENHANCING TEST-CONTROL CONNECTIVITY FOR CLOCK GATINGBACKGROUND

[0001] Computing and other electronic devices play integral roles in manufacturing, communication, transportation, healthcare, commerce, social interaction, entertainment, and other services. For example, electronic devices power the server farms that provide cloud-based, distributed computing functionality for commerce, communication, and artificial intelligence (Al). Electronic devices are also embedded in many different types of modem equipment, from medical devices to appliances and from vehicles to industrial tools. Personal electronic devices enable portable video viewing and convenient access to smart digital assistants. Additionally, one versatile electronic device — the smartphone — has practically become a necessity to have within arm’s reach.

[0002] To provide these diverse functionalities, electronic devices typically include various circuitries, such as processors, memories, logic circuitry, and other digital circuitry. For proper functioning, these circuitries rely on clock signals provided by one or more clock generators to synchronize various operations of the circuitry. However, electronic devices such as mobile devices often have constrained power budgets, and implementing circuitry to reduce power consumption is of importance during design of such devices. One technique that is ty pically used to reduce power consumption is the use of clock gating circuitry to enable or disable the clock signal for portions of an electronic circuit. By disabling the clock signal provided to certain circuitry, the switching activity7of the circuitry is reduced, which in turn reduces pow er consumption of the circuitry. Clock gating can be applied to individual components of a circuit design, such as a single flip-flop, or to a group of flip-flops, a processing core, or a subsystem of the design. By doing so, computer engineers, electrical engineers, and other designers of electronic devices endeavor to improve power efficiency of an electronic device to facilitate their use in providing the services described above.SUMMARY

[0003] Various implementations described herein provide for enhancing test-control connectivity for clock gating by inserting one or more multiplexers within testing circuitry during a register transfer level (RTL) design stage and allowing the output of the multiplexers to control the test enable signals provided to clock gating circuits (CGCs). In a particular example, the testing circuitry includes a design-for-testing (DFT) subsystem (DFTSS). During an initial synthesis stage, CGCs are inserted into the circuitry design and are merged based on the CGCshaving the same functional enables and the same test enables. At the RTL design level, however, additional multiplexers are inserted into testing circuitry. The multiplexers can have one data input connected to a common data source (e.g., a single register bit) and another data input of the multiplexer connected to another data source (e g., at least one data register of multiple data registers), which may be unique to the multiplexer. This can control how many CGCs have common test enables.

[0004] During testing (e.g., as part of automatic test pattern generation (ATPG) testing), a selection input of the multiplexer is connected to a first constant value, and the test enable inputs of the CGCs are selected to be connected to multiple data registers to provide granular control. In a particular example, the first constant value is a logical low provided by a tie-low cell (TIE-0). At the physical design level, the selection input of the multiplexer is connected to a second constant value, and the test enable inputs of the CGCs are selected to be connected to the common data source (e.g.. a single data register), which at least temporarily causes multiple “additional'’ CGCs to have the same test enables. In a particular example, the second constant value is a logical high value provided by a tie-high cell (TIE-1). Usage of the tie-high and tie-low cells, however, may be swapped.

[0005] Other multiplexers in the testing circuitry' can also be coupled to the common data source (e.g., the single data register bit) for merging purposes and to the respective unique data source (e.g., different sets of, or at least one data register of, multiple data registers) for actual testing purposes. As a result, two or more CGCs with identical functional controls but different test controls are capable of being merged into a single CGC based on the selection signal applied to the multiplexers during the design phase to “mimic” having common test enables. Accordingly, two or more CGCs with the same functional enable signal may be merged into a single CGC irrespective of their actual test enable inputs that are in effect during the testing phase.

[0006] Various implementations enable functional clock power reduction by architectural modification of test-enable controls of CGCs. The improvements in design at the RTL design level and flow enhancements at the physical design level described herein enable additional CGCs to be combined in the physical circuitry. This enables further power reduction during functional operation without impacting peak power during testing operations.

[0007] The following and other example implementations are described herein.

[0008] In example implementations, an apparatus for enhancing test-control connectivity’ for clock gating includes a first multiplexer. The first multiplexer includes a first input configured to receive a first test enablement signal from a first test control circuit and a second input configured to receive a second test enablement signal from a second test control circuit. The first multiplexer also includes a first selection input configured to receive a selection signal and a firstoutput coupled to a first clock-gating cell. The first multiplexer is configured to provide the first test enablement signal to the first clock-gating cell responsive to the selection signal having a first value and to provide the second test enablement signal to the first clock-gating cell responsive to the selection signal having a second value.

[0009] In example implementations, a method for enhancing test-control connectivity for clock gating includes receiving, at a first input of a first multiplexer, a first test enablement signal from a first test control circuit. The method also includes receiving, at a second input of the first multiplexer, a second test enablement signal from a second test control circuit. The method additionally includes receiving, at a first selection input of the first multiplexer, a selection signal. The method further includes providing, by the first multiplexer, the first test enablement signal to a first clock-gating cell responsive to the selection signal having a first value.

[0010] In example implementations, an apparatus for enhancing test-control connectivity for clock gating includes a first test control circuit, a second test control circuit, a first clock-gating cell, and a first multiplexer. The first multiplexer includes a first input coupled to the first test control circuit and a second input coupled to the second test control circuit. The first multiplexer also includes a first output coupled to a first test-enable input of the first clock-gating cell.

[0011] In other example implementations, an apparatus includes an integrated circuit configured to perform a method for enhancing test-control connectivity for clock gating as described herein.BRIEF DESCRIPTION OF DRAWINGS

[0012] Apparatuses of and techniques for enhancing test-control connectivity for clock gating are described with reference to the following drawings. The same numbers are used throughout the drawings to reference like features and components.Fig. 1 illustrates an example apparatus with at least one integrated circuit (IC) that includes one or more clock sources, test circuitry, clock-gating cells (CGCs), and flip-flops that can implement enhanced test-control connectivity’ for clock gating.Fig. 2 is a circuit diagram illustrating an example clock gating circuit that can be used to implement enhanced test-control connectivity for clock gating.Fig. 3 is a flowchart illustrating an example process for clock-gating cell (CGC) insertion and optimization flow for enhancing test-control connectivity for clock gating.Fig. 4 is a schematic diagram illustrating an example electronic circuit at a first synthesis stage of a circuit design process.Fig. 5 is a schematic diagram illustrating an example of clock-gating cell (CGC) insertion in an electronic circuit at a second synthesis stage of the circuit design process.Fig. 6 is a schematic diagram illustrating example implementations of enhanced test-control connectivity in an electronic circuit at a third synthesis stage of the circuit design process.Fig. 7 is a circuit diagram illustrating example test circuitry for implementing enhanced test-control connectivity in the electronic circuit of Fig. 6.Fig. 8 is a schematic diagram illustrating example implementations of enhanced test-control connectivity by CGC merging in an electronic circuit at a fourth synthesis stage of the circuit design process.Fig. 9 is a flow diagram illustrating an example process for implementing enhanced test-control connectivity for clock gating.Fig. 10 illustrates various components of an example electronic device that can implement enhanced test-control connectivity for clock gating in accordance with one or more described aspects.DETAILED DESCRIPTIONOverview

[0013] Electronic devices provide features and perform functions to make important contributions to modem society, such as those related to communication, safety, manufacturing, and content creation. To provide these features and functions, electronic devices include circuitry that relies on clock signals provided by one or more clock generators to synchronize various operations of the circuitry. However, the clock tree of an electronic circuit is a major contributor to dynamic power consumption because an active clock signal causes maximum switching activities of the components connected to the clock signal, including such components as flipflops.

[0014] In a typical example, the clock signal may consume 20% to 40% of the dynamic power in a circuit. One technique that is typically used to reduce power consumption is employing clock gating cells (CGCs) or other clock gating circuitry to enable or disable the clock signal for “downstream” portions of an electronic circuit. Clock gating is a technique that selectively disables the clock signal to idle or unused parts of a circuit design. When provided with a disable signal, the CGC stops the clock signal from propagating beyond the CGC thereby reducing power consumption in the logic circuitry coupled downstream to the CGC.

[0015] This document describes hardware and techniques that enable the components of electronic devices to operate while using less power in relation to certain clock tree components. Electronic circuit designers utilize design software tools, such as electronic design automation(EDA) tools, to design electronic device circuitry such as integrated circuits. The EDA tool design flow includes a register transfer level (RTL) component and a synthesis level component. The RTL component converts a high-level design description of the circuitry' into an RTL design description in which the high-level design description is represented by circuitry’ utilizing interactions between registers. The synthesis level component translates the RTL design description into a discrete representation of logic gates and other associated circuitry components. The synthesis component can further determine the placement of the circuitry components and the routing between components.

[0016] During an RTL conversion phase or a circuit synthesis phase, the EDA tool can insert clock gating circuitry to optimize the circuit design for power consumption and circuit area utilization. An example of such clock gating circuitry' is a clock gating cell (CGC). A CGC is a logic circuit configured to receive a clock signal from a clock generator and one or more enable signals from a controller and to output a gated clock signal to circuitry (e.g., a flip-flop) coupled to the CGC responsive to the one or more enable signals. When the CGC is enabled, the CGC outputs the received clock signal as the gated clock signal. When the CGC is disabled, the CGC can output a non-oscillating signal (e.g., a constant-valued signal) as the gated clock signal. Accordingly, the clock signal can be selectively disabled to idle or unused portions of a circuit design. By disabling the clock signal to such circuitry, the circuitry does not consume as much power due to the inactivity of the circuitry. An example of components that are frequently coupled to CGCs are groups of flip-flops implementing one or more registers.

[0017] An important consideration in the design of digital circuits is the utilization of testing circuitry’, such as design for testing (DFT) circuitry, which adds testability features to the circuit design. DFT circuitry allows for testing of the circuit during or after manufacturing to identify manufacturing or other defects. Tests of the circuitry is generally' performed using automatic test pattern generation (ATPG) techniques in which test patterns are applied to the circuitry to enable automated test equipment (ATE) to distinguish between correct circuit behavior and faulty circuit behavior. Power reduction capability is desirable during both a functional mode of operation and a test mode of operation of the circuitry. Accordingly, a CGC is often provided with both a functional enable (FE) input to control power saving during functional operation of the circuitry' and a test enable (TE) input to control power saving during testing of the circuitry.

[0018] To generate test patterns having low flip-flop toggle and reduce local voltage (e.g., IR) drop, the ATPG tool should have dedicated control over the CGCs during testing. During synthesis, the EDA tool inserts CGCs with a goal to optimize the circuit design for power and area. To control peak power during testing and reduce test time, test control pins (e.g., test enables) of CGCs are often connected to multiple bit registers to allow granular control duringtesting. In a particular example, the data register bits are Joint Test Action Group (JTAG) register bits. In contrast, at-speed ATPG testing is typically performed in the functional mode in which the CGCs are controlled by a single data register and all the clock-gating cells can either be turned- off or tumed-on together. In some cases, however, a testing tool can be provided a particular level of granularity so that which CGCs are turned ON and which CGCs are turned OFF can be controlled for a given at-speed testing. Turning on all CGCs together during testing, however, can lead to peak power issues while turning off the CGCs leads to test quality gaps due to low ATPG coverage.

[0019] At the physical design level, based on routing / placement considerations, the EDA tool can often perform further design optimizations by merging two or more clock-gating cells with similar functionality to reduce CGC count within the circuitry'. In some methodologies, CGCs with identical functional controls and test controls (e.g., functional enables and test enables) can be merged while the CGCs with identical functional controls and different test controls cannot be merged.

[0020] Various implementations described herein provide for enhanced test-control connectivity for clock gating by inserting one or more multiplexers within testing circuitry' and allowing the output of the multiplexers to separately control the test enable signals provided to the CGCs during both testing and functional operating modes. In example implementations, at the RTL design level, additional multiplexers are inserted into testing circuitry. In some cases, one data input of a multiplexer is connected to a single register bit and another data input of the multiplexer is connected to at least one data register of multiple data registers. A selection input of the multiplexer is connected to a configurable constant value to control which of the inputs is provided to the output of the multiplexer during a particular testing or functional operation mode. Accordingly, the output of the multiplexer controls a test enable input of the CGCs based on the constant value.

[0021] During ATPG testing, the selection input is connected to a first constant value (e.g. , a logical low), and the test enable inputs of the CGCs will be connected to multiple data registers to provide granular control. The granular control facilitates controlling of peak power during tests and enables high test quality (e.g., high ATPG coverage). At the physical design level, the selection input is connected to a second constant value and the test enable inputs of the CGCs are connected to a single data register. As a result, two or more CGCs with identical functional controls but different test controls appear to have the same test control, so the CGCs can be merged.

[0022] Various implementations enable functional-clock power reduction by architectural modification of test-enable controls of CGCs. The improvements in design at the RTL designlevel and flow enhancements at the physical design level that are described herein enable further power reduction during functional operation without impacting peak power during testing operations. These and other example implementations are described herein.Example Environments and Electronic Devices

[0023] Fig. 1 illustrates, at 100 generally, an example apparatus 102 with at least one integrated circuit 104 (IC 104) that includes test circuitry 108, multiple CGCs 110. multiple flipflops 112, and one or more clock sources 114 that can implement enhanced test-control connectivity for clock gating. The integrated circuit 104 can include or realize a system-on-chip 106 (SoC 106). The apparatus 102, the integrated circuit 104, and / or the SoC 106, can implement enhanced test-control connectivity for clock gating as described herein. The SoC 106, for instance, can implement enhanced test-control connectivity for clock gating by including one or more multiplexers within the test circuity 108 to selectively control the test enable signals provided to the CGCs 110 during a functional operational mode or a testing operational mode of the SoC 106. In this example, the apparatus 102 is depicted as a smartphone. The apparatus 102 may, however, be implemented as any suitable computing or other electronic device as described herein.

[0024] Examples of the apparatus 102 include a mobile electronic device or mobile device, mobile communication device, modem, cellular or mobile phone, mobile station, gaming device, navigation device, media or entertainment device (e.g., a media streamer or gaming controller), laptop computer, desktop computer, tablet computer, smart appliance, vehicle-based electronic system, wearable computing device (e.g., clothing, watch, or reality-altering glasses), Internet of Things (loTs) device, sensor, stock management device, electronic portion of a machine or piece of equipment (e.g.. a vehicle or robot), memory' storage device (e.g., a solid-state drive (SSD)), server computer or portion thereof (e.g., a server blade or rack or another part of a datacenter), and the like. Illustrated examples of the apparatus 102 include a tablet device 102-1, a smart television 102-2, a desktop computer 102-3, a server computer 102-4, a smartwatch 102-5, a smartphone (or document reader) 102-6, and intelligent glasses 102-7.

[0025] In example implementations, the apparatus 102 includes at least one integrated circuit 104. The integrated circuit 104 can be part of or realized as a chip, a package, a module, an assembly, or at least one printed circuit board (PCB) (not shown). Examples of a PCB include a flexible PCB, a rigid PCB, a single or multi-layered PCB, a surface-mounted or through-hole PCB, combinations thereof, and so forth. In some instances, one or more integrated circuit (IC) chips can be mounted on a PCB.

[0026] Each IC chip can be realized as a general-purpose processor, a microcontroller, an application-specific IC (ASIC), and so forth. Other examples of IC chips include a system-on-a- chip (SoC), a securit -oriented IC chip, a memory chip, a communications IC chip (e.g., a modem or radio-frequency IC), a graphics processor, an artificial intelligence (Al) accelerator, sensor chips, combinations thereof, and so forth. Sensor chips may include, for example, an accelerometer, a camera or other light sensor, a satellite positioning system (e g., a Global Positioning System (GPS)) chip, and the like. An integrated circuit chip can be packaged alone or together with other IC chips.

[0027] As shown in Fig. 1, the integrated circuit 104 includes the test circuitry 108, the CGCs 110, the flip-flops 112, and the one or more clock sources 114. In some cases, the integrated circuit 104 can be realized as an SoC 106. If so, the SoC 106 can include the test circuitry 108, the CGCs 110, the flip-flops 112, and the one or more clock sources 114. However, the principles that are described herein are applicable to implementations in which at least one of the test circuitry 108, the CGCs 110, the flip-flops 112, and the one or more clock sources 114 are part of different chips, are on different PCBs, or are even in different electronic devices. Accordingly, although not explicitly shown in Fig. 1, the components used to implement enhanced test-control connectivity for clock gating may include other aspects, including other parts or other devices.

[0028] Although a single integrated circuit 104 is depicted in Fig. 1, the illustrated components can be distributed across multiple ICs. In other words, although the components for implementing enhanced test-control connectivity for clock gating may be disposed together on a single IC 104 as shown, such components may alternatively be distributed across two or more ICs. For example, the test circuitry 108 may be part of a first IC, the one or more CGCs 110 and the flip-flops 1 12 may be part of a second IC, and the one or more clock sources 114 may be part of a third IC.

[0029] In example implementations, the test circuitry' 108 includes one or more multiplexers (not shown in Fig. 1) having outputs that are coupled to a test enable input of each of the CGCs 110. A clock input of each of the CGCs is coupled to one of the clock sources 114 to receive a clock signal. Outputs of one or more of the CGCs 110 are coupled to one or more of the flip-flops 112. Thus, the test circuity 108 includes one or more multiplexers having outputs of the multiplexers coupled to the CGCs 110. As further described herein, one data input of a multiplexer can be connected to a single register bit as data source common to multiple multiplexers, and another data input of the multiplexer can be connected to at least one data register of multiple data registers as a respective data source for a respective multiplexer. A selection input of the multiplexer is connected to a configurable constant value to control whichof the inputs is provided to the output of the multiplexer and subsequently to the test enable input of the CGC.

[0030] In an implementation, during testing, the selection input is connected to a first constant value (e.g., a logical low), and the test enable inputs of the CGCs are connected to multiple data registers to provide granular control. At the physical design level, the selection input is connected to a second constant value (e g., a logical high) and the test enable inputs of the CGCs are connected to a single data register such that the circuit is emulated to have multiple common test enables for multiple CGCs. As a result, two or more CGCs with identical functional controls but different test controls during a testing phase may be merged into a single CGC in the physical circuit, thereby reducing power consumption during the functional operational mode of the integrated circuit 104.

[0031] An example circuit diagram illustrating a clock gating circuit is further described below with reference to Fig. 2. An example process for clock-gating cell insertion and optimization flow for enhancing test-control connectivity for clock gating is described below with reference to Fig. 3.

[0032] Example schematic diagrams illustrating circuitry for enhancing test-control connectivity for clock gating are described below with reference to Figs. 2, 4-6, and 8. A flowchart illustrating a process for clock-gating cell insertion and optimization flow for enhancing testcontrol connectivity for clock gating is described below with reference to Fig. 3. An example circuit diagram that depicts testing circuitry for enhancing test-control connectivity for clock gating is described below with reference to Fig. 7. This document also describes Fig. 9, which depicts an example process for enhancing test-control connectivity for clock gating. An electronic device that can implement enhanced test-control connectivity for clock gating is described, byway of example only, with reference to Fig. 10.Example Apparatuses and Operational Schemes

[0033] Fig. 2 is a circuit diagram 200 illustrating an example clock gating circuit 202 to implement enhanced test-control connectivity for clock gating that includes an OR gate 204, a latch 206, and an AND gate 208. The clock gating circuit 202 is coupled to a set of registers 210. In a particular implementation, the set of registers 210 includes a group of flip-flops. The OR gate 204 includes a test enable (TE) input 212 to enable the clock gating circuit 202 during a testing operational mode and a functional enable (FE) input 214 to enable the clock gating circuit 202 during a functional operational mode. An output of the OR gate 204 is coupled to an input of the latch 206 and configured to provide an enable signal 218 to the latch 206. A clock input of the latch 206 is coupled to a clock signal (CLK) 216.

[0034] In a particular implementation, the clock input of the latch 206 is a negative edge- triggered input that is triggered on a negative edge (or falling edge) of the CLK 216 to prevent glitches from occurring in the gated clock signal. A first input of the AND gate 208 is coupled to the output of the latch 206, and a second input of the AND gate 208 is coupled the clock signal 208. An output of the AND gate 208 provides a gated clock signal 220 to the set of registers 210. In a particular implementation, the clock gating circuit 202 is a clock-gating cell (CGC) such as one of the CGCs illustrated in Fig. 1. In the particular implementation of Fig. 2, the clock gating circuit 202 is referred to as an integrated clock-gating cell (ICG) because it includes both a functional enable input and a test enable input.

[0035] If either the TE input 212 receives a test enable signal or the FE input 214 receives a functional enable signal, a clock enable signal 218 is provided to the latch 206. Upon receiving a negative edge of the CLK 216, the latch 206 outputs a latched value to the first input of the AND gate 208, and the AND gate 208 outputs a gated clock signal 220 to the set of registers 210. As a result, the set of registers 210 responds to the clock signal 216 and operates according to their designed functionality. If the TE input 212 and the FE input 214 do not receive an enable signal, the gated clock signal 220 is maintained at a constant value and the set of registers 210 are disabled or idled. Accordingly, the clock gating functionality' provided by the clock gating circuit 202 selectively disables the clock signal 216 to idle or unused circuitry by preventing clock signal propagation. From an alternative perspective, the clock gating functionality provided by the clock gating circuit 202 selectively forwards the clock signal 216 responsive to an asserted test enable signal or functional enable signal.

[0036] It should be understood that the clock gating circuit 202 is provided as an example of a clock gating circuit (CGC) that may be used in various implementations for providing a gated clock signal. In some implementations other suitable clocking gating circuitry, CGCs, or ICGs may be used. Further, a clock gating circuit may be realized in alternative manners.

[0037] Fig. 3 is an example flowchart illustrating a process 300 for clock-gating cell insertion and optimization flow for enhancing test-control connectivity for clock gating. The process 300 includes four blocks 302-308. The operations of the example processes can be performed, for instance, during design of an electronic circuit as described herein using an EDA tool or another suitable circuit design software tool. At block 302, an RTL circuit design stage is initiated. During the RTL circuit design stage, an RTL component converts a high-level design description of the circuitry- into an RTL design description. In the RTL design description, the high-level design description is represented by circuitry utilizing interactions between registers.

[0038] At block 304, a synthesis design stage is initiated. During the synthesis design stage, a synthesis level component translates the RTL design description into a discreterepresentation of logic gates and other associated circuitry components. The synthesis component further determines the placement of the circuitry components and the routing between components. During synthesis, the EDA tool performs extensive CGC insertion and test-enable hookup during a scan insertion procedure. The CGCs are inserted with their functional enable pins connected, but their test enable pins are left unconnected. During scan stitching, the testenable pins of inserted CGCs are connected to test circuity 108 for multiple bit control.

[0039] At block 306, the EDA tool initiates a clock tree synthesis (CTS) stage. The CTS stage is used to reduce (e.g., minimize) the routing resources used by the clock signal as well as reduce the area occupied by clock repeaters while meeting the clock requirements of the circuit. During CTS, the EDA tool merges the CGCs to save power based on, for example, whether the CGCs have unique enables and any placement / timing requirements. During the initial CTS stage, two or more CGCs with identical functional controls and test controls are merged, taking into consideration placement / timing requirements; however, the CGCs with identical functional controls but different test controls are not merged.

[0040] In block 308, the CGC merging is improved by inserting multiplexers within the testing circuitry 108 as described herein with respect to various implementations to reduce the unique test-enables count within the circuit. The operation(s) of block 308 may be part of the operation(s) of block 306. By way of example, one data input of a multiplexer can be connected to a shared register source (e.g., a single register bit), and another data input of the multiplexer can be connected to a respective register source (e.g., at least one data register of multiple data registers). A selection input of the multiplexer is connected to a configurable value to control which of the inputs is provided to the output of the multiplexer. The output of the multiplexer controls a test enable input of the CGCs based on the configured value, which may be a constant.

[0041] During ATPG testing, the selection input of the multiplexer is connected to a first constant value (e.g., a logical low), and the test-enable inputs of the CGCs will be connected to multiple data registers to provide granular control. At the physical design level, the selection input of the multiplexer is connected to a second constant value and the test enable inputs of the CGCs are connected to a single data register to provide a common test-enable signal source. As a result, two or more CGCs with identical functional controls but different actual test controls temporarily appear to have identical test controls; consequently, the two or more CGC are merged. As previously discussed, the improvements in design at the RTL design level and in flowenhancements at the physical design level, as described herein, enable additional CGC merging to be performed. The additional CGC merging enables further powder reduction during functional operation without impacting peak power during testing operations.

[0042] Fig. 4 is a schematic diagram illustrating an example electronic circuit 400 at a first synthesis stage of a circuit design process. As shown, the electronic circuit 400 includes the test circuitry7108, a first clock source 114-1, a second clock source 114-2, a first group of flip-flops 112-1, a second group of flip-flops 112-2, and a third group of flip-flops 112-3. In some cases, the first clock source 114-1 is configured to provide a first clock signal 402-1 to clock inputs of each flip-flop of the first group of flip-flops 112-1 and the second group of flip-flops 1 12-2. The second clock source 114-2 is configured to provide a second clock signal 402-2 to a clock input of each flip-flop of the third group of flip-flops 112-3.

[0043] The test circuity 108 includes multiple multiplexers (not shown in Fig. 4) as described herein with respect to various implementations. The test circuitry 108 is configured to generate multiple test enable signals 404 during testing operations. In the first synthesis stage of the circuit design process as illustrated in Fig. 4, the electronic circuit 400 does not yet include CGCs. Accordingly, there is no connection of the test enable signals 404 to enable inputs of the CGCs to be propagated.

[0044] Fig. 5 is a schematic diagram illustrating clock-gating cell (CGC) insertion in an example electronic circuit 500 at a second synthesis stage of the circuit design process. As shown, the electronic circuit 500 is representative of the electronic circuit 400 of Fig. 4 with the additional insertion of a first CGC (CGC1) 110-1, a second CGC (CGC2) 110-2, and a third CGC (CGC3) 110-3 during the second synthesis stage. As previously discussed, CGCs can be inserted into an electronic circuit design to facilitate power savings during functional operation. The first CGC 110-1 is inserted between the first clock source 114-1 and the first group of flip-flops 112-1, and the second CGC 110-2 is inserted between the first clock source 114-1 and the second group of flip-flops 1 12-2. The third CGC 110-3 is inserted between the second clock source 114-2 and the third group of flip-flops 112-3.

[0045] Functional enable (FE) inputs of each of the first CGC 110-1, the second CGC 110- 2, and the third CGC 110-3 are connected to a functional enable signal source provided by a controller (not shown). In an implementation, the FE signals are provided by a controller or processor of the IC 104. In another implementation, the FE signals are provided by the test circuitry 108, such as when the circuitry' is to be operating and no test mode is in effect. The test enable (TE) inputs of each of the first CGC 110- 1 , the second CGC 110-2, and the third CGC 110- 3 remain unconnected during the second synthesis stage as illustrated in Fig. 5.

[0046] Fig. 6 is a schematic diagram that illustrates the implementing of enhanced testcontrol connectivity in an example electronic circuit 600 at a third synthesis stage of the circuit design process. The electronic circuit 600 is representative of the electronic circuit 500 of Fig. 5 with the additional coupling of the outputs of the multiplexers (as shown in Fig. 7) of the testcircuitry 108 to the test enable (TE) inputs of each of the depicted CGCs. Although more or fewer CGCs can be included, the electronic circuit 600 includes three by way of example: the first CGC (CGC1) 110-1, the second CGC (CGC2) 110-2, and the third CGC (CGC3) 110-3. In some cases, the test circuitry 108 can include or be realized with a DFTSS.

[0047] In example implementations, a first test enable signal 602-1 is provided from the test circuity 108 to a first TE input of the first CGC 110-1. A second test enable signal 602-2 is routed from the test circuitry 108 to a second TE input of the second CGC 110-2. The test circuitry' 108 also provides a third test enable signal 602-3 to a third TE input of the third CGC 110-3 during the third synthesis stage. Based on a respective clock signal 402, and responsive to a functional enable (FE) signal or a test enable signal 602, each respective CGC 110 produces a respective clock gated signal 604. Thus, the first CGC 110-1 produces a first clock gated signal 604-1, and the second CGC 110-2 provides a second clock gated signal 604-2. Similarly, the third CGC 110- 3 propagates a third clock gated signal 604-3. Each CGC 110 forwards its respective clock gated signal 604 to a respective group of flip-flops 112. Examples of configurations and operations of the test circuitry 108 are further described next with respect to Fig. 7.

[0048] Fig. 7 is a circuit diagram 700 illustrating example test circuitry' 108 for implementing enhanced test-control connectivity' in the electronic circuit 600 of Fig. 6. As shown, the example test circuitry 108 includes a first test control circuit 702-1. a second test control circuit 702-2, a third test control circuit 702-3, a first multiplexer 704-1, a second multiplexer 704-2, a third multiplexer 704-3, and a tie cell 706. In example implementations, the first multiplexer 704- 1 includes a first input 708-1 configured to receive a first test enablement signal 714-1 from the first test control circuit 702-1. The first multiplexer 704-1 also includes a second input 710-1 configured to receive a second test enablement signal 714-2 from the second test control circuit 702-2. In an implementation, the first test enablement signal 714-1 is derived from at least one data register bit such as a JTAG register bit.

[0049] The first multiplexer 704-1 includes a first selection input 712-1 configured to receive a selection signal 716 from the tie cell 706. The first multiplexer 704-1 further includes a first output 718-1 coupled to the first TE input of the first CGC 110-1 (both of Fig. 6), which “becomes” a first CGC 720 after merging, as is described herein. The first multiplexer 704-1 is configured to provide the first test enablement signal 714-1 to the first CGC 720 as the first test enable signal 602-1 responsive to the selection signal 716 having a first value. The first multiplexer 704-1 is configured to provide the second test enablement signal 714-2 to the first CGC 720 responsive to the selection signal having a second value. The tie cell 706 is configured to provide the selection signal having the first value based on a constant voltage level such that the test circuitry 108 prevents the first multiplexer 704-1 from providing the second testenablement signal 714-2 as the test enable signal 602-1 during operation (e.g., during functional operation). In a particular implementation, the second test enablement signal 714-2 is derived from one or more of multiple register bits, such as JTAG register bits.

[0050] The second multiplexer 704-2 includes a third input 708-2 configured to receive the second test enablement signal 714-2 from the second test control circuit 702-2 and a second selection input 712-2 configured to receive the selection signal 716 from the tie cell 706. The second multiplexer 704-2 includes a second output 718-2 coupled to the second CGC 110-2. The second multiplexer 704-2 is configured to provide the second test enablement signal 714-2 as the second enable signal 602-2 to the second TE input of the second CGC 110-2 responsive to the selection signal 716 having the first value. The second multiplexer 704-2 further includes a fourth input 710-2 configured to receive the second test enablement signal 714-2 from the second test control circuit 702-2. The second multiplexer 704-2 is therefore further configured to provide the second test enablement signal 714-2 to the second CGC 110-2 responsive to the selection signal 716 having the second value.

[0051] The third multiplexer 704-3 includes a fifth input 708-3 configured to receive a third test enablement signal 714-3 from the third test control circuit 702-3 and a sixth input 710- 3 configured to receive the second test enablement signal 714-2 from the second test control circuit 702-2. The third multiplexer 704-3 also includes a third selection input 712-3 configured to receive the selection signal 716 from the tie cell 706. The third multiplexer 704-3 further includes a third output 718-3 coupled to the third TE input of the third CGC 110-3. The third multiplexer 704-3 is configured to provide the third test enablement signal 714-3 to the third CGC 110-3 as the third test enable signal 602-3 responsive to the selection signal 716 having the first value and to provide the second test enablement signal 714-2 to the third CGC 110-3 as the third test enable signal 602-3 responsive to the selection signal 716 having the second value.

[0052] A tie cell 706 can couple a node (e.g., an input of a component) to a voltage, such as a constant voltage level. With a constant voltage level, the tie cell 706 can provide a constant logical value, such as '“0” or “1.” Atie cell 706 may be realized in different manners. For example, a tie cell 706 may include one or more circuit components that safely couple a selection input of a multiplexer (e.g., that safely couple at least one gate of a field-effect transistor (FET) thereof) to a supply voltage node (VDD) for a tie-high cell or to a ground node (Vss or GND) for a tie-high cell. A tie cell can provide protection for a transistor terminal (e.g., a gate terminal or a base terminal) that is relatively sensitive as compared to the current flows or electromagnetic flux experienced by a power network node (e.g., a supply voltage rail or a ground plane). A tie cell 706 can be built using, for instance, two or more transistors.

[0053] Although the example implementations illustrated in Fig. 7 include a single tie cell 706, in other implementations multiple tie cells may be used. For example, in a particular implementation the test circuitry 108 may include a first tie cell configured to provide the selection signal 716 having the first value and a second tie cell configured to provide the selection signal 716 having the second value. In an implementation illustrated in Fig. 7, the tie cell 706 is included within the test circuitry’ 108. In other implementations, the tie cell 706 may be located external to the test circuitry 108. In still other implementations, different circuitry' may be used to generate or provide the selection signal 716. Thus, the circuitry may provide a given voltage level, like a constant voltage level, using a different approach, such as a voltage divider, a voltage regulator, a direct connection to a power network node, a combinational logic circuit or gate, and so forth.

[0054] In an implementation, with reference also to Fig. 6, the first CGC 110-1 (or 720 in Figs. 7 and 8) further includes a first clock input 606-1 configured to receive the clock signal 402- 1 from the first clock source 114-1. The first CGC 110-1 is configured to provide a first gated clock signal 604-1 (e.g., without clock pulses) from a first clock output 608-1 based on the clock signal 402-1 and the first test enable signal 602-1 being unasserted during a test operation. The first CGC 110-1 is also configured to provide the first gated clock signal 604-1 (e.g., with clock pulses as derived from the clock signal 402-1) from the first clock output 608-1 based on the clock signal 402-1 and the first test enable 602-1 signal being asserted during the test operation.

[0055] In an implementation, the test circuitry 108 of Fig. 7 provides for supporting both granular (e.g., multibit) control and single bit control of the TE registers of the first CGC 110-1 (or 720), the second CGC 110-2, and the third CGC 110-3. For example, during ATPG testing, granular control may be used to control the first CGC 110-1, the second CGC 110-2, and the third CGC 110-3 to limit test peak power and reduce (e.g., lower or minimize) IR drop during the testing procedure. During a design-time emulation of a functional operational mode, common-signal control (e.g., single-bit control) may be used to allow for CGC merging as further described with respect to Fig. 8.

[0056] Fig. 8 is a schematic diagram that illustrates implementing enhanced test-control connectivity by CGC merging in an electronic circuit 800 at a fourth synthesis stage of the circuit design process. In the electronic circuit 800 of Fig. 8, the first CGC 110-1 and the second CGC 110-2 illustrated in Fig. 6 are merged into a single fourth CGC (CGC 4) 720, which is also referred to as a first clock gating circuit 720 herein after merging. The fourth CGC 720 receives the first test enable signal 602-1 from the test circuitry 108 at a TE input and the first clock signal 402-1 from the first clock source 114-1. The fourth CGC 720 is configured to provide a single gated clock signal 804 that is coupled to clock inputs of both the first group of flip-flops 112-1 and the second group of flip-flops 112-2.

[0057] In an example implementation, the first group of flip-flops 112-1 is configured to selectively receive the first gated clock signal 804, or the clock signal from the first clock output 806-1, of the fourth CGC 720. The second group of flip-flop circuits 112-2 is configured to selectively receive the first gated clock signal 804, or the clock signal from the first clock output 806-1, of the fourth CGC 720. The first gated clock signal 804 may correspond to the oscillations of the first clock signal 402-1 or to a constant value, depending on the value(s) of the signals at the enable inputs: the functional enable (FE) input or the test enable (TE) input.

[0058] In another example implementation, the third CGC 110-3 is not merged with either of the first CGC 110-1 or the second CGC 110-2. The third CGC 110-3 therefore remains coupled to the second clock source 114-2 and receives the third test enable signal 602-3 from the test circuitry 108. The third CGC 110-3 outputs the third gated clock signal 604-3 to the third group of flip-flops 112-3. Increasing the quantity of CGCs that can be merged during circuit design, as enabled by the test circuitry 108 that is described herein, provides for increased power savings with the digital circuitry.

[0059] Having generally described schemes, techniques, and hardware for implementing enhanced test-control connectivity for clock gating, this discussion now turns to example methods.Example Methods

[0060] Example methods are described below with reference to the flow diagram of Figs. 9. Fig. 9 is a flow diagram illustrating an example process 900 for implementing enhanced testcontrol connectivity for clock gating. The flow chart 900 includes seven blocks 902-914. The operations of example processes can be performed by electronic circuit components as described herein. For example, the operations may be performed by at least one instance of test circuitry 108 in conjunction with one or more CGCs and flip-flops.

[0061] At block 902, the process 900 includes receiving, at a first input 708-1 of a first multiplexer 704-1, a first test enablement signal 714-1 from a first test control circuit 702-1. At block 904, the process 900 includes receiving, at a second input 710-1 of the first multiplexer 704- 1, a second test enablement signal 714-2 from a second test control circuit 702-2. At block 906, the process 900 includes receiving, at a first selection input 712-1 of the first multiplexer 704-1, a selection signal 716. At block 908. the process 900 includes providing, by the first multiplexer 704-1, the first test enablement signal 714-1 to afirst CGC 110-1 responsive to the selection signal 716 having a first value. For example, the first multiplexer 704-1 can provide the first test enablement signal 714-1 as a first test enable signal 602-1 to a first test enable input of the first CGC 110-1.

[0062] In an implementation, the process 900 may further include, at block 910, receiving, at a third input 708-2 of a second multiplexer 704-2, the second test enablement signal 714-2 from the second test control circuit 702-2. At block 912, the process 900 may further include receiving, at a second selection input 712-2 of the second multiplexer 704-2. the selection signal 716. At block 914, the process 900 may further include providing, by the second multiplexer 704-2, the second test enablement signal 714-2 to a second CGC 110-2 responsive to the selection signal 716 having the first value.

[0063] In an implementation, the process 900 or another process may further include providing the selection signal 716 having the first value based on a constant voltage level such that the first multiplexer 704-1 is prevented from providing the second test enablement signal 714- 2 during operation. In another implementation, the process 900 or another process may further include providing a clock signal 402-1 to the first CGC 110-1 and providing a first gated clock signal 604-1 from the first CGC 110-1 based on the clock signal 402-1 and the first test enable signal 602-1.

[0064] In another implementation, the process 900 or another process may additionally include receiving the first gated clock signal 804 by the first group of flip-flop circuits 112-1 and receiving the first gated clock signal 804 by the second group of flip-flop circuits 112-2 as a result of a merging operation of at least two clock-gating cells that produced the first clock-gating cell 720.

[0065] Aspects of these methods may be implemented in, for example, hardware (e.g., fixed logic circuitry, a controller, a finite state machine, or a processor in conjunction with a memory), fimiware, software, or some combination thereof. The methods may be realized using one or more of the apparatuses or components shown in Figs. 1, 2, 4-8, or 10, which components may be further divided, combined, and so on. The devices and components of these figures generally represent hardware, such as electronic devices, PCBs, packaged modules, IC chips, components, or circuits; finnware; software; or a combination thereof. Thus, these figures illustrate some of the many possible systems or apparatuses capable of implementing the described methods.

[0066] For the methods described herein and the associated flow chart(s) and / or flow diagram(s), the orders in which operations are shown and / or described are not intended to be construed as a limitation. Instead, any number or combination of the described method operations can be combined in any order to implement a given method or an alternative method, including by combining operations from different ones of the flow chart(s) and flow diagram(s) and the earlier-described schemes and techniques into one or more methods. Operations may also beomitted from or added to the described methods. Further, described operations can be implemented in fully or partially overlapping manners.Additional Example Apparatuses and Electronic Devices

[0067] Fig. 10 illustrates various components of an example electronic device 1000 that can implement enhanced test-control connectivity for clock gating in accordance with one or more described aspects. The electronic device 1000 may be implemented as any one or combination of a fixed, mobile, stand-alone, or embedded device or in any form of a consumer, computer, portable, user, server, communication, phone, navigation, gaming, audio, camera, messaging, media playback, and / or other type of electronic device 1000, such as the smartphone that is depicted in Fig. 1 as the apparatus 102. One or more of the illustrated components may be realized as discrete components or as integrated components on at least one integrated circuit of the electronic device 1000.

[0068] The electronic device 1000 can include one or more communication transceivers 1002 that enable wired and / or wireless communication of device data 1004, such as received data, transmitted data, or other information identified above. Example communication transceivers 1002 include near-held communication (NFC) transceivers, wireless personal area network (PAN) (WPAN) radios compliant with various IEEE 802.15 (Bluetooth®) standards, wireless local area network (LAN) (WLAN) radios compliant with any of the various IEEE 802.11 (WiFi®) standards, wireless wide area network (WAN) (WWAN) radios (e.g., those that are 3GPP- compliant) for cellular telephony, wireless metropolitan area network (MAN) (WMAN) radios compliant with various IEEE 802. 16 (WiMAX™) standards, infrared (IR) transceivers compliant with an Infrared Data Association (IrDA) protocol, and wired local area network (LAN) (WLAN) Ethernet transceivers.

[0069] The electronic device 1000 may also include one or more data input ports 1006 via which any type of data, media content, and / or other inputs can be received, such as user-selectable inputs, messages, applications, music, television content, recorded video content, and any other type of audio, video, and / or image data received from any content and / or data source, including a sensor like a microphone or a camera. The data input ports 1006 may include USB ports, coaxial cable ports, fiber optic ports for optical fiber interconnects or cabling, and other serial or parallel connectors (including internal connectors) for flash memory, DVDs, CDs, and the like. These data input ports 1006 may be used to couple the electronic device to components, peripherals, or accessories such as keyboards, microphones, cameras, or other sensors.

[0070] The electronic device 1000 of this example includes at least one processor 1008 (e.g., any one or more of application processors, microprocessors, digital-signal processors(DSPs), controllers, and the like), which can include a combined processor and memory system (e.g., implemented as part of an SoC), that processes (e.g., executes) computer-executable instructions to control operation of the device. The processor 1008 may be implemented as an application processor, embedded controller, microcontroller, security processor, artificial intelligence (Al) accelerator, and the like. Generally, a processor or processing system may be implemented at least partially in hardware, which can include components of an integrated circuit or on-chip system, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), and other implementations in silicon and / or other materials.

[0071] Alternatively or additionally, the electronic device 1000 can be implemented with any one or combination of electronic circuitry, which may include software, hardware, firmware, or fixed logic circuitry that is implemented in connection with processing and control circuits, which are generally indicated at 1010 (as electronic circuitry 1010). This electronic circuitry 1010 can implement executable or hardware-based modules (not shown in Fig. 10), such as through processing / computer-executable instructions stored on computer-readable media, through logic circuitry and / or hardware (e.g., such as an FPGA), and so forth.

[0072] The electronic device 1000 also includes one or more memory devices 1012 that enable data storage, examples of which include random-access memory (RAM), non-volatile memory (e.g., read-only memory (ROM), flash memory, EPROM, and EEPROM), and a disk storage device. Thus, the memory device(s) 1012 can be distributed across different logical storage levels of a system as well as at different physical components. The memory device(s) 1012 provide data storage mechanisms to store the device data 1004, other types of code and / or data, and various device applications 1020 (e.g., software applications or programs). For example, an operating system 1014 can be maintained as software instructions within the memory device 1012 and executed by the processor 1008.

[0073] In some implementations, the electronic device 1000 also includes an audio and / or video processing system 1016 that processes audio and / or video data and / or that passes through the audio and / or video data to an audio system 1018 and / orto a display system 1022 (e.g., a video buffer or a screen of a smartphone or camera). The audio system 1018 and / or the display system 1022 may include any devices that process, display, and / or otherwise render audio, video, display, and / or image data. Display data and audio signals can be communicated to an audio component and / or to a display component via an RF (radio-frequency) link, an S-video link, an HD MI (high- definition multimedia interface) link, a composite video link, a component video link, a DVI (digital video interface) link, an analog audio connection, a video bus, or another similar communication link, such as a media data port 1024. In some implementations, the audio system1018 and / or the display system 1022 are external or separate components of the electronic device 1000. Alternatively, the display system 1022, for example, can be an integrated component of the example electronic device 1000, such as part of an integrated touch interface.

[0074] The electronic device 1000 of Fig. 10 illustrates example implementations of the apparatus 102 of Fig. 1; of a device that can implement the example aspects of Figs. 2, 4-8. and 10; of a device that can implement the example circuitries of Figs. 7 and 8, and of a device that can implement the example method of Fig. 9. The electronic device 1000, including one or more components thereof, can thus include test circuitry 108, one or more CGCs 110, one or more groups of flip-flops 112, and one or more clock sources 114. One or more of the components illustrated in Fig. 10 may be integrated on a same IC chip (e.g., the IC 104 of Figs. 1 and 10), like the processor 1008 and / or an SoC (e.g., the SoC 106 of Fig. 1).Example Aspects and Implementations for Enhanced Test-Control Connectivity For Clock Gating

[0075] In the following, some example aspects and implementations are described:

[0076] Example aspect 1: An apparatus for enhancing test-control connectivity’ for clock gating, the apparatus comprising: a first multiplexer including: a first input configured to receive a first test enablement signal from a first test control circuit; a second input configured to receive a second test enablement signal from a second test control circuit; a first selection input configured to receive a selection signal; and a first output coupled to a first clock-gating cell, the first multiplexer configured to: provide the first test enablement signal to the first clock-gating cell responsive to the selection signal having a first value; and provide the second test enablement signal to the first clock-gating cell responsive to the selection signal having a second value.

[0077] Example aspect 2: The apparatus of example aspect 1, or any other described example, further comprising: a second multiplexer including: a third input configured to receive the second test enablement signal from the second test control circuit; a second selection input configured to receive the selection signal; and a second output coupled to a second clock-gating cell, wherein the second multiplexer is configured to provide the second test enablement signal to the second clock-gating cell responsive to the selection signal having the first value.

[0078] Example aspect 3: The apparatus of example aspect 2, or any other described example, wherein: the second multiplexer includes a fourth input configured to receive the second test enablement signal from the second test control circuit; and the second multiplexer is configured to provide the second test enablement signal to the second clock-gating cell responsive to the selection signal having the second value.

[0079] Example aspect 4: The apparatus of any one of example aspects 1-3, or any other described example, further comprising: a clock source configured to provide a clock signal; and the first clock-gating cell including: a first test enable input configured to receive the first test enablement signal from the first multiplexer; a first clock input configured to receive the clock signal; and a first clock output, the first clock-gating cell configured to provide: a first gated clock signal from the first clock output based on the clock signal and the first test enablement signal being unasserted during a test operation; and the clock signal from the first clock output based on the clock signal and the first test enablement signal being asserted during the test operation.

[0080] Example aspect 5: The apparatus of example aspect 4, or any other described example, further comprising: a first group of flip-flop circuits configured to selectively receive the first gated clock signal or the clock signal from the first clock output of the first clock-gating cell.

[0081] Example aspect 6: The apparatus of example aspect 5, or any other described example, further comprising: a second group of flip-flop circuits configured to selectively receive the first gated clock signal or the clock signal from the first clock output of the first clock-gating cell.

[0082] Example aspect 7: The apparatus of any one of example aspects 2-6, or any other described example, further comprising, a third multiplexer including: a fifth input configured to receive a third test enablement signal from a third test control circuit; a sixth input configured to receive the second test enablement signal from the second test control circuit; a third selection input configured to receive the selection signal; and a third output coupled to a third clock-gating cell, the third multiplexer configured to: provide the third test enablement signal to the third clockgating cell responsive to the selection signal having the first value; and provide the second test enablement signal to the third clock -gating cell responsive to the selection signal having the second value.

[0083] Example aspect 8: The apparatus of any one of the previous example aspects, or any other described example, wherein the first test enablement signal is derived from at least one data register bit.

[0084] Example aspect 9: The apparatus of any one of the previous example aspects, or any other described example, further comprising: a tie cell configured to provide the selection signal having the first value based on a constant voltage level such that the apparatus prevents the first multiplexer from providing the second test enablement signal dunng operation.

[0085] Example aspect 10: A method for enhancing test-control connectivity for clock gating, the method comprising: receiving, at a first input of a first multiplexer, a first test enablement signal from a first test control circuit; receiving, at a second input of the firstmultiplexer, a second test enablement signal from a second test control circuit; receiving, at a first selection input of the first multiplexer, a selection signal; and providing, by the first multiplexer, the first test enablement signal to a first clock-gating cell responsive to the selection signal having a first value.

[0086] Example aspect 11: The method of example aspect 10, or any other described example, further comprising: receiving, at a third input of a second multiplexer, the second test enablement signal from the second test control circuit; receiving, at a second selection input of the second multiplexer, the selection signal; and providing, by the second multiplexer, the second test enablement signal to a second clock-gating cell responsive to the selection signal having the first value.

[0087] Example aspect 12: The method of example aspect 10 or 11 , or any other described example, further comprising: providing the selection signal having the first value based on a constant voltage level such that the first multiplexer is prevented from providing the second test enablement signal during operation.

[0088] Example aspect 13: The method of any one of example aspects 10-12, or any other described example, further comprising: providing a clock signal to the first clock-gating cell; and providing a first gated clock signal from the first clock-gating cell based on the clock signal and the first test enablement signal.

[0089] Example aspect 14: The method of example aspect 13, or any other described example, further comprising: receiving the first gated clock signal by a first group of flip-flop circuits; and receiving the first gated clock signal by a second group of flip-flop circuits as a result of a merging operation of at least two clock-gating cells that produced the first clock-gating cell.

[0090] Example aspect 15: An apparatus for enhancing test-control connectivity for clock gating, the apparatus comprising: a first test control circuit; a second test control circuit; a first clock-gating cell; and a first multiplexer including: a first input coupled to the first test control circuit; a second input coupled to the second test control circuit; and a first output coupled a first test-enable input of the first clock-gating cell.

[0091] Example aspect 16: The apparatus of example aspect 15, or any other described example, further comprising: a tie cell coupled to a first selection input of the first multiplexer.

[0092] Example aspect 17: The apparatus of example aspect 16, or any other described example, further comprising: a second clock-gating cell; and a second multiplexer including: a third input coupled to the second test control circuit; and a second output coupled to a second testenable input of the second clock-gating cell.

[0093] Example aspect 18: The apparatus of example aspect 17, or any other described example, wherein the second multiplexer further includes a second selection input coupled to the tie cell.

[0094] Example aspect 19: The apparatus of example aspect 17 or 18, or any other described example, wherein the first multiplexer is configured to: receive a first test enablement signal from the first test control circuit: receive a second test enablement signal from a second test control circuit; receive a selection signal from the tie cell; provide the first test enablement signal to the first clock-gating cell responsive to the selection signal having a first value; and provide the second test enablement signal to the first clock-gating cell responsive to the selection signal having a second value.

[0095] Example aspect 20: The apparatus of example aspect 19, or any other described example, wherein the second multiplexer is configured to: receive the second test enablement signal from the second test control circuit; receive the selection signal from the tie cell; and provide the second test enablement signal to the second clock-gating cell responsive to the selection signal having the first value or the second value.

[0096] Example aspect 21 : An apparatus configured to perform the method of any one of example aspects 10-14, or any other described example.

[0097] Example aspect 22: The apparatus of any one of example aspects 1-9, or any other described example, further comprising: the first test control circuit configured to generate the first test enablement signal, the apparatus being configured to provide the first test enablement signal to the first input.

[0098] Example aspect 23: The apparatus of any one of example aspects 1-9 or 22, or any other described example, further comprising: the second test control circuit configured to generate the second test enablement signal, the apparatus being configured to provide the second test enablement signal to the second input.

[0099] Example aspect 24: The apparatus of example aspect 23, or any other described example, the apparatus being further configured to provide the second test enablement signal to the third input.

[0100] Example aspect 25: The apparatus of any one of example aspects 23 or 24, or any other described example, the apparatus being further configured to provide the second test enablement signal to the fourth input.

[0101] Example aspect 26: The apparatus of any one of example aspects 23 to 25, or any other described example, further comprising: the third test control circuit configured to generate the third test enablement signal, the apparatus being configured to provide the third testenablement signal to the fifth input, and to provide the second test enablement signal to the sixth input.

[0102] Example aspect 27: The apparatus of any one of example aspects 1 to 9, 22 to 26, or any other described example, further comprising: the first clock-gating cell.

[0103] Example aspect 28: The apparatus of any one of example aspects 1 to 9, 22 to 27, or any other described example, further comprising: the second clock-gating cell.

[0104] Features described in the context of one aspect (e.g., a method or an apparatus) may be used in combination with other aspects (e.g., an apparatus or a method, respectively, or a different method or a different apparatus).

[0105] Unless context dictates otherwise, use herein of the word ’‘or” may be considered use of an “inclusive or,” or a term that permits inclusion or application of one or more items that are linked by the word “or” (e.g., a phrase “A or B” may be interpreted as permitting just “A,” as permitting j ust “B,” or as permitting both “A" and “B”). Also, as used herein, a phrase referring to “at least one of’ a list of items refers to any combination of those items, including single members. For instance, “at least one of a, b, or c” can cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a- a- a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c, or any other ordering of a, b, and c). Further, items represented in the accompanying figures and terms discussed herein may be indicative of one or more items or terms, and thus reference may be made interchangeably to single or plural forms of the items and terms in this written description.

[0106] Although implementations for enhanced test-control connectivity for clock gating have been described in language specific to certain features and / or methods, the subject of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as example implementations for realizing enhanced test-control connectivity' for clock gating.

Claims

CLAIMSWhat is claimed is:

1. An apparatus for enhancing test-control connectivity for clock gating, the apparatus comprising: a first multiplexer including: a first input configured to receive a first test enablement signal from a first test control circuit; a second input configured to receive a second test enablement signal from a second test control circuit; a first selection input configured to receive a selection signal; and a first output coupled to a first clock-gating cell, the first multiplexer configured to: provide the first test enablement signal to the first clock-gating cell responsive to the selection signal having a first value; and provide the second test enablement signal to the first clock-gating cell responsive to the selection signal having a second value.

2. The apparatus of claim 1. further comprising: a second multiplexer including: a third input configured to receive the second test enablement signal from the second test control circuit; a second selection input configured to receive the selection signal; and a second output coupled to a second clock-gating cell, wherein the second multiplexer is configured to provide the second test enablement signal to the second clock-gating cell responsive to the selection signal having the first value.

3. The apparatus of claim 2. wherein: the second multiplexer includes a fourth input configured to receive the second test enablement signal from the second test control circuit; and the second multiplexer is configured to provide the second test enablement signal to the second clock-gating cell responsive to the selection signal having the second value.

4. The apparatus of any one of claims 1-3, further comprising: a clock source configured to provide a clock signal; and the first clock-gating cell including: a first test enable input configured to receive the first test enablement signal from the first multiplexer; a first clock input configured to receive the clock signal; and a first clock output, the first clock-gating cell configured to provide: a first gated clock signal from the first clock output based on the clock signal and the first test enablement signal being unasserted during a test operation; and the clock signal from the first clock output based on the clock signal and the first test enablement signal being asserted during the test operation.

5. The apparatus of claim 4. further comprising: a first group of flip-flop circuits configured to selectively receive the first gated clock signal or the clock signal from the first clock output of the first clock-gating cell.

6. The apparatus of claim 5. further comprising: a second group of flip-flop circuits configured to selectively receive the first gated clock signal or the clock signal from the first clock output of the first clock-gating cell.

7. The apparatus of any one of claims 2-6, further comprising. a third multiplexer including: a fifth input configured to receive a third test enablement signal from a third test control circuit; a sixth input configured to receive the second test enablement signal from the second test control circuit; a third selection input configured to receive the selection signal; and a third output coupled to a third clock-gating cell, the third multiplexer configured to: provide the third test enablement signal to the third clock-gating cell responsive to the selection signal having the first value; and provide the second test enablement signal to the third clock-gating cell responsive to the selection signal having the second value.

8. The apparatus of any one of claims 1-7, wherein the first test enablement signal is derived from at least one data register bit.

9. The apparatus of any one of claims 1-8, further comprising: a tie cell configured to provide the selection signal having the first value based on a constant voltage level such that the apparatus prevents the first multiplexer from providing the second test enablement signal during operation.

10. A method for enhancing test-control connectivity for clock gating, the method comprising: receiving, at a first input of a first multiplexer, a first test enablement signal from a first test control circuit; receiving, at a second input of the first multiplexer, a second test enablement signal from a second test control circuit; receiving, at a first selection input of the first multiplexer, a selection signal; and providing, by the first multiplexer, the first test enablement signal to a first clock-gating cell responsive to the selection signal having a first value.

11. The method of claim 10, further comprising: receiving, at a third input of a second multiplexer, the second test enablement signal from the second test control circuit; receiving, at a second selection input of the second multiplexer, the selection signal; and providing, by the second multiplexer, the second test enablement signal to a second clockgating cell responsive to the selection signal having the first value.

12. The method of claim 10 or 11, further comprising: providing the selection signal having the first value based on a constant voltage level such that the first multiplexer is prevented from providing the second test enablement signal during operation.

13. The method of any one of claims 10-12, further comprising: providing a clock signal to the first clock-gating cell; and providing a first gated clock signal from the first clock-gating cell based on the clock signal and the first test enablement signal.

14. The method of claim 13, further comprising: receiving the first gated clock signal by a first group of flip-flop circuits; and receiving the first gated clock signal by a second group of flip-flop circuits as a result of a merging operation of at least two clock-gating cells that produced the first clock-gating cell.

15. An apparatus configured to perform the method of any one of claims 10-14.

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