Driving circuit, display apparatus, and driving method

Abstract

A driving circuit, a display apparatus, and a driving method. The driving circuit comprises a node control circuit (11), a first node charging circuit (12), a first energy storage circuit (13), and an input circuit (14); under the control of a scanning control signal (LSP), the node control circuit (11) controls connection or disconnection between an input end (I1) and an intermediate node (NZ), and controls connection or disconnection between the intermediate node (NZ) and a control node (M), and under the control of the potential of the control node (M), the node control circuit (11) controls connection or disconnection between a first voltage end (V1) and the intermediate node (NZ); under the control of the potential of the control node (M) and a set control signal (GRST), the first node charging circuit (12) controls connection or disconnection between a first node (PU) and the first voltage end (V1). The driving circuit can realize refresh and display of any row.

Description

Driving circuit, display device and driving method TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a driving circuit, a display device and a driving method. BACKGROUND

[0002] If the related driving module wants to realize partial display by starting from a middle row of driving circuits included in the driving module, the driving circuits in the front non-display area also need to be opened row by row for cascading transmission, and real arbitrary row refresh display cannot be realized.

[0003] SUMMARY

[0004] In one aspect, the embodiment of the present disclosure provides a driving circuit, comprising a node control circuit, a first node charging circuit, a first energy storage circuit and an input circuit;

[0005] The node control circuit is electrically connected with a scan control end, an input end, an intermediate node, a first voltage end and a control node, respectively, for controlling the input end and the intermediate node to be connected or disconnected under the control of a scan control signal provided by the scan control end, controlling the intermediate node and the control node to be connected or disconnected, and controlling the first voltage end and the intermediate node to be connected or disconnected under the control of the potential of the control node;

[0006] The first node charging circuit is electrically connected with the control node, a set control end, a first node and a first voltage end, respectively, for controlling the first node and the first voltage end to be connected or disconnected under the control of the potential of the control node and a set control signal provided by the set control end;

[0007] The first energy storage circuit is electrically connected with the control node, for maintaining the potential of the control node;

[0008] The input circuit is electrically connected with the input end and the first node, respectively, for controlling the potential of the first node under the control of an input signal provided by the input end.

[0009] Optionally, the driving circuit further comprises a reset circuit.

[0010] The reset circuit is electrically connected with a reset control end, the first node and a second voltage end, respectively, for controlling the first node and the second voltage end to be connected or disconnected under the control of a reset control signal provided by the reset control end.

[0011] Optionally, the node control circuit comprises a first transistor, a second transistor and a third transistor.

[0012] a gate of the first transistor is electrically connected with the scan control end, a first pole of the first transistor is electrically connected with the input end, and a second pole of the first transistor is electrically connected with the intermediate node;

[0013] a gate of the second transistor is electrically connected with the scan control end, a first pole of the second transistor is electrically connected with the intermediate node, and a second pole of the second transistor is electrically connected with the control node;

[0014] a gate of the third transistor is electrically connected with the control node, a first pole of the third transistor is electrically connected with the first voltage end, and a second pole of the third transistor is electrically connected with the intermediate node.

[0015] Optionally, the first node charging circuit comprises a fourth transistor and a fifth transistor, and the first energy storage circuit comprises a first capacitor.

[0016] a gate of the fourth transistor is electrically connected with the control node, a first pole of the fourth transistor is electrically connected with the first voltage end, and a second pole of the fourth transistor is electrically connected with a first pole of the fifth transistor;

[0017] a gate of the fifth transistor is electrically connected with the set control end, and a second pole of the fifth transistor is electrically connected with the first node.

[0018] a first end of the first capacitor is electrically connected with the control node, and a second end of the first capacitor is electrically connected with a direct current voltage end.

[0019] Optionally, the input circuit comprises a sixth transistor.

[0020] a gate of the sixth transistor is electrically connected with a first pole of the sixth transistor and the input end, and a second pole of the sixth transistor is electrically connected with the first node.

[0021] Optionally, the reset circuit comprises a seventh transistor.

[0022] a gate of the seventh transistor is electrically connected with the reset control end, a first pole of the seventh transistor is electrically connected with the first node, and a second pole of the seventh transistor is electrically connected with the second voltage end.

[0023] Optionally, the driving circuit further comprises a first node reset circuit and an up pull node control circuit.

[0024] The first node reset circuit is electrically connected with the pull-up reset end, the first node and the second voltage end respectively, and is used for controlling the first node and the second voltage end to be connected or disconnected under the control of a pull-up reset signal provided by the pull-up reset end.

[0025] The pull-up node control circuit is electrically connected with the first second node, the second second node, the first node and the second voltage end respectively, and is used for controlling the first node and the second voltage end to be connected or disconnected under the control of the potential of the first second node, and controlling the first node and the second voltage end to be connected or disconnected under the control of the potential of the second second node.

[0026] Optionally, the driving circuit further comprises a carry signal output circuit and a driving signal output circuit.

[0027] The carry signal output circuit is electrically connected with the first node, the first second node, the second second node, a carry signal output end, an output clock signal end and the second voltage end respectively, and is used for controlling the carry signal output end and the output clock signal end to be connected or disconnected under the control of the potential of the first node, controlling the carry signal output end and the second voltage end to be connected or disconnected under the control of the potential of the first second node, and controlling the carry signal output end and the second voltage end to be connected or disconnected under the control of the potential of the second second node.

[0028] The driving signal output circuit is electrically connected with the first node, the first second node, the second second node, a driving signal output end, an output clock signal end and the third voltage end respectively, and is used for controlling the driving signal output end and the output clock signal end to be connected or disconnected under the control of the potential of the first node, controlling the driving signal output end and the third voltage end to be connected or disconnected under the control of the potential of the first second node, and controlling the driving signal output end and the third voltage end to be connected or disconnected under the control of the potential of the second second node.

[0029] Optionally, the driving circuit further comprises a second energy storage circuit.

[0030] The first end of the second energy storage circuit is electrically connected with the first node, the second end of the second energy storage circuit is electrically connected with the driving signal output end, and the second energy storage circuit is used for storing electric energy.

[0031] Optionally, the driving circuit further comprises a first second node control circuit and a second second node control circuit.

[0032] The first second node control circuit is electrically connected with the first control voltage terminal, the first node, the first second node and the second voltage terminal respectively, and is configured to control the electric potential of the first second node under the control of the first control voltage provided by the first control voltage terminal, control the communication or disconnection between the first second node and the second voltage terminal under the control of the electric potential of the first node, control the communication or disconnection between the first control voltage terminal and the first second node under the control of the electric potential of the first intermediate control node, and control the communication or disconnection between the first second node and the second voltage terminal under the control of the electric potential of the first node.

[0033] The second second node control circuit is electrically connected with the second control voltage terminal, the first node, the second second node and the second voltage terminal respectively, and is configured to control the electric potential of the second second node under the control of the second control voltage provided by the second control voltage terminal, control the communication or disconnection between the second second node and the second voltage terminal under the control of the electric potential of the first node, control the communication or disconnection between the second control voltage terminal and the second second node under the control of the electric potential of the second intermediate control node, and control the communication or disconnection between the second second node and the second voltage terminal under the control of the electric potential of the first node.

[0034] Optionally, the driving circuit further comprises a first second node control circuit and a second second node control circuit.

[0035] The first second node control circuit is electrically connected with the first control voltage terminal, the first node, the first second node and the second voltage terminal respectively, and is configured to control the electric potential of the first second node under the control of the first control voltage provided by the first control voltage terminal, control the communication or disconnection between the first second node and the second voltage terminal under the control of the electric potential of the first node, control the communication or disconnection between the first control voltage terminal and the first second node under the control of the electric potential of the first intermediate control node, and control the communication or disconnection between the first second node and the second voltage terminal under the control of the electric potential of the first node.

[0036] The second second node control circuit is electrically connected with the second control voltage terminal, the first node, the second second node and the second voltage terminal respectively, and is configured to control the electric potential of the second second node under the control of the second control voltage provided by the second control voltage terminal, control the communication or disconnection between the second second node and the second voltage terminal under the control of the electric potential of the first node, control the communication or disconnection between the second control voltage terminal and the second second node under the control of the electric potential of the second intermediate control node, and control the communication or disconnection between the second second node and the second voltage terminal under the control of the electric potential of the first node.

[0037] Optionally, the driving circuit further comprises a second node reset circuit.

[0038] The second node reset circuit is electrically connected with the input end, the first second node, the second second node and the second voltage end respectively, and is used for controlling the first second node and the second voltage end to be in communication or disconnected and controlling the second second node and the second voltage end to be in communication or disconnected under the control of an input signal provided by the input end.

[0039] Optionally, the first node reset circuit comprises an eighth transistor, and the pull-up node control circuit comprises a ninth transistor and a tenth transistor.

[0040] The gate of the eighth transistor is electrically connected with the pull-up reset end, the first pole of the eighth transistor is electrically connected with the first node, and the second pole of the eighth transistor is electrically connected with the second voltage end.

[0041] The gate of the ninth transistor is electrically connected with the first second node, the first pole of the ninth transistor is electrically connected with the first node, and the second pole of the ninth transistor is electrically connected with the second voltage end.

[0042] The gate of the tenth transistor is electrically connected with the second second node, the first pole of the tenth transistor is electrically connected with the first node, and the second pole of the tenth transistor is electrically connected with the second voltage end.

[0043] Optionally, the carry signal output circuit comprises an eleventh transistor, a twelfth transistor and a thirteenth transistor.

[0044] The gate of the eleventh transistor is electrically connected with the first node, the first pole of the eleventh transistor is electrically connected with the output clock signal end, and the second pole of the eleventh transistor is electrically connected with the carry signal output end.

[0045] The gate of the twelfth transistor is electrically connected with the first second node, the first pole of the twelfth transistor is electrically connected with the carry signal output end, and the second pole of the twelfth transistor is electrically connected with the second voltage end.

[0046] The gate of the thirteenth transistor is electrically connected with the second second node, the first pole of the thirteenth transistor is electrically connected with the carry signal output end, and the second pole of the thirteenth transistor is electrically connected with the second voltage end.

[0047] The drive signal output circuit comprises a fourteenth transistor, a fifteenth transistor and a sixteenth transistor.

[0048] The gate of the fourteenth transistor is electrically connected with the first node, the first pole of the fourteenth transistor is electrically connected with the output clock signal end, and the second pole of the fourteenth transistor is electrically connected with the drive signal output end.

[0049] a gate of the fifteenth transistor is electrically connected with the first second node, a first pole of the fifteenth transistor is electrically connected with the driving signal output end, and a second pole of the fifteenth transistor is electrically connected with the third voltage end;

[0050] a gate of the sixteenth transistor is electrically connected with the second second node, a first pole of the sixteenth transistor is electrically connected with the driving signal output end, and a second pole of the sixteenth transistor is electrically connected with the third voltage end.

[0051] Optionally, the second energy storage circuit includes a second capacitor.

[0052] a first end of the second capacitor is electrically connected with the first node, and a second end of the second capacitor is electrically connected with the driving signal output end.

[0053] Optionally, the first second node control circuit includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a twentieth transistor.

[0054] a gate of the seventeenth transistor and a first pole of the seventeenth transistor are electrically connected with the first control voltage end, and a second pole of the seventeenth transistor is electrically connected with the first intermediate control node;

[0055] a gate of the eighteenth transistor is electrically connected with the first node, a first pole of the eighteenth transistor is electrically connected with the first intermediate control node, and a second pole of the eighteenth transistor is electrically connected with the second voltage end.

[0056] a gate of the nineteenth transistor is electrically connected with the first intermediate control node, a first pole of the nineteenth transistor is electrically connected with the first control voltage end, and a second pole of the nineteenth transistor is electrically connected with the first second node;

[0057] a gate of the twentieth transistor is electrically connected with the first node, a first pole of the twentieth transistor is electrically connected with the first second node, and a second pole of the twentieth transistor is electrically connected with the second voltage end.

[0058] the second second node control circuit includes a twenty-first transistor, a twenty-second transistor, a twenty-third transistor and a twenty-fourth transistor.

[0059] a gate of the twenty-first transistor and a first pole of the twenty-first transistor are electrically connected with the second control voltage end, and a second pole of the twenty-first transistor is electrically connected with the second intermediate control node;

[0060] The gate of the twenty-second transistor is electrically connected with the first node, the first electrode of the twenty-second transistor is electrically connected with the second intermediate control node, and the second electrode of the twenty-second transistor is electrically connected with the second voltage end;

[0061] The gate of the twenty-third transistor is electrically connected with the second intermediate control node, the first electrode of the twenty-third transistor is electrically connected with the second control voltage end, and the second electrode of the twenty-second transistor is electrically connected with the second second node;

[0062] The gate of the twenty-fourth transistor is electrically connected with the first node, the first electrode of the twenty-fourth transistor is electrically connected with the second second node, and the second electrode of the twenty-fourth transistor is electrically connected with the second voltage end.

[0063] Optionally, the first second node control circuit comprises a twenty-fifth transistor and a twenty-sixth transistor;

[0064] The gate of the twenty-fifth transistor and the first electrode of the twenty-fifth transistor are both electrically connected with the first control voltage end, and the second electrode of the twenty-fifth transistor is electrically connected with the first second node;

[0065] The gate of the twenty-sixth transistor is electrically connected with the first node, the first electrode of the twenty-sixth transistor is electrically connected with the first second node, and the second electrode of the twenty-sixth transistor is electrically connected with the second voltage end.

[0066] The second second node control circuit comprises a twenty-seventh transistor and a twenty-eighth transistor;

[0067] The gate of the twenty-seventh transistor and the first electrode of the twenty-seventh transistor are both electrically connected with the second control voltage end, and the second electrode of the twenty-seventh transistor is electrically connected with the second second node;

[0068] The gate of the twenty-eighth transistor is electrically connected with the first node, the first electrode of the twenty-eighth transistor is electrically connected with the second second node, and the second electrode of the twenty-eighth transistor is electrically connected with the second voltage end.

[0069] Optionally, the second node reset circuit comprises a twenty-ninth transistor and a thirtieth transistor;

[0070] The gate of the twenty-ninth transistor is electrically connected with the input end, the first electrode of the twenty-ninth transistor is electrically connected with the first second node, and the second electrode of the twenty-ninth transistor is electrically connected with the second voltage end.

[0071] The gate of the thirtieth transistor is electrically connected with the input terminal, the first pole of the thirtieth transistor is electrically connected with the second node, and the second pole of the thirtieth transistor is electrically connected with the second voltage terminal.

[0072] In a second aspect, the display device comprises a driving module, and the driving module comprises a plurality of driving circuits as described above.

[0073] The input terminal of the driving circuit is electrically connected with the carry signal output terminal of the adjacent m-level driving circuit.

[0074] m is a positive integer.

[0075] In a third aspect, the display device comprises a driving method, and the display stage comprises a j-1 frame and a j frame, the j-1 frame is arranged before the j frame and is adjacent to the j frame, the j-1 frame is a global display frame, the j frame is a local display frame, j is a positive integer greater than 1, and the driving method comprises the following steps.

[0076] In the global display frame, each level of the driving circuit outputs a corresponding driving signal in sequence, and the global display frame is used to charge the control node of the driving circuit of the local display frame.

[0077] Optionally, the driving method further comprises the following steps.

[0078] When the n-level driving circuit starts local display in the j frame, in the n-level driving stage included in the global display frame, the n-level input terminal included in the n-level driving circuit of the display device is connected to the effective voltage signal, the node control circuit in the n-level driving circuit controls the communication between the n-level input terminal and the n-level intermediate node, controls the communication between the n-level intermediate node and the n-level control node, controls the communication or disconnection between the first voltage terminal and the n-level intermediate node under the control of the potential of the n-level control node, and the first energy storage circuit in the n-level driving circuit maintains the potential of the n-level first node.

[0079] In the n-level driving stage included in the local display frame, the first node charging circuit in the n-level driving circuit controls the communication between the n-level first node and the first voltage terminal under the control of the potential of the n-level control node and the set control signal, and n is a positive integer.

[0080] Optionally, the n-level driving circuit is cascaded with the n-k-level driving circuit, the time sequence of the scanning control signal connected to the n-level driving circuit is the same as the time sequence of the output clock signal connected to the n-k-level driving circuit.

[0081] k is a positive integer.

[0082] Optionally, the driving circuit further comprises a reset circuit; and the driving method further comprises:

[0083] In the a-th driving stage included in the partial display frame, the reset circuit in the a-th driving circuit controls the communication between the a-th first node and the second voltage terminal under the control of the reset control signal.

[0084] a is a positive integer, and a is greater than n.

[0085] Optionally, the display stage further comprises a (j+1)-th frame, the (j+1)-th frame is arranged after the j-th frame and is adjacent to the j-th frame; and the (j+1)-th frame is a partial display frame.

[0086] The driving method comprises:

[0087] In the n-th driving stage included in the (j+1)-th frame, the set control terminal provides an effective set control signal, and the first node charging circuit in the n-th driving circuit controls the communication between the n-th first node and the first voltage terminal under the control of the potential of the n-th control node and the set control signal; n is a positive integer. BRIEF DESCRIPTION OF DRAWINGS

[0088] FIG. 1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0089] FIG. 2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0090] FIG. 3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0091] FIG. 4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0092] FIG. 5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0093] FIG. 6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0094] FIG. 7 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0095] FIG. 8 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0096] FIG. 9 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0097] FIG. 10 is a working timing diagram of a driving module comprising at least one embodiment of the driving circuit shown in FIG. 9 of the present disclosure;

[0098] FIG. 11 is a simulation working timing diagram of a drive module including at least one embodiment of the drive circuit shown in FIG. 9 of the present disclosure;

[0099] FIG. 12 is a working timing diagram of a drive module including at least one embodiment of the drive circuit shown in FIG. 9 of the present disclosure

[0100] FIG. 13 is a circuit diagram of a drive circuit according to at least one embodiment of the present disclosure;

[0101] FIG. 14 is a circuit diagram of a drive circuit according to at least one embodiment of the present disclosure;

[0102] FIG. 15A is a circuit diagram of a drive circuit according to at least one embodiment of the present disclosure;

[0103] FIG. 15B is a circuit diagram of a drive circuit according to at least one embodiment of the present disclosure;

[0104] FIG. 16A is a structural diagram of at least one embodiment of a drive module according to at least one embodiment of the present disclosure;

[0105] FIG. 16B is a structural diagram of at least one embodiment of a drive module according to at least one embodiment of the present disclosure;

[0106] FIG. 17 is a structural diagram of at least one embodiment of a drive module according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0107] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0108] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two poles of the transistor other than the gate, one of the poles is referred to as the first pole and the other is referred to as the second pole.

[0109] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0110] As shown in FIG. 1, the drive circuit according to the embodiments of the present disclosure includes a node control circuit 11, a first node charging circuit 12, a first energy storage circuit 13 and an input circuit 14.

[0111] The node control circuit 11 is electrically connected with a scan control end LSP, an input end I1, an intermediate node NZ, a first voltage end V1 and a control node M respectively, for controlling the communication or disconnection between the input end I1 and the intermediate node NZ under the control of a scan control signal provided by the scan control end LSP, controlling the communication or disconnection between the intermediate node NZ and the control node M, and controlling the communication or disconnection between the first voltage end V1 and the intermediate node NZ under the control of the potential of the control node M;

[0112] The first node charging circuit 12 is electrically connected with the control node M, a set control end GRST, a first node PU and a first voltage end V1 respectively, for controlling the communication or disconnection between the first node PU and the first voltage end V1 under the control of the potential of the control node M and a set control signal provided by the set control end GRST;

[0113] The first energy storage circuit 13 is electrically connected with the control node M, for maintaining the potential of the control node M;

[0114] The input circuit 14 is electrically connected with the input end I1 and the first node PU respectively, for controlling the potential of the first node PU under the control of an input signal provided by the input end I1.

[0115] In at least one embodiment of the present disclosure, the driving module comprises at least one embodiment of the driving circuit shown in Figure 1, and before a local display frame, a global display frame is provided, which is adjacent to the local display frame. When the local display frame starts to display from the nth row of driving circuit (n is a positive integer) in the local display frame, in the global display frame, when the input end I1 of the nth row of driving circuit is connected to the effective voltage signal, the node control circuit 11 controls the communication between the input end I1 and the intermediate node NZ and the communication between the intermediate node NZ and the control node M under the control of the scan control signal provided by the scan control end LSP, and charges the control node M through the input signal provided by the input end I1. After the potential of the control node M is raised, the node control circuit 11 controls the communication between the first voltage end V1 and the intermediate node NZ under the control of the potential of the control node M, and the first voltage signal provided by the first voltage end V1 further charges the control node M, which raises the potential of the control node M. The first energy storage circuit 13 maintains the potential of the control node M; after the input end I1 of the nth row of driving circuit is connected to the invalid voltage signal, the scan control signal provided by LSP is switched to the invalid voltage signal, and the high potential of the control node M is maintained by the first energy storage circuit 13 at this time; when switching from the global display frame to the local display frame, when the set control end GRST provides an effective set control signal, the first node charging circuit controls the communication between the first node PU and the first voltage end V1 under the control of the potential of the control node M and the set control signal provided by the set control end GRST, and the first voltage signal provided by the first voltage end V1 charges the first node PU in the nth row of driving circuit. When the output clock signal connected by the nth row of driving circuit is an effective voltage signal, the driving signal output circuit in the nth row of driving circuit controls the effective nth row driving signal provided by the driving signal output end under the control of the potential of the first node PU, and normally cascades the subsequent driving circuit to realize the local display function starting from the nth row of driving circuit. If the next frame is still a local display frame starting from the nth row, no global display frame is needed, and the nth row local display function can be repeatedly realized by repeatedly inputting the set control signal.

[0116] Optionally, the first voltage end can be a high voltage end.

[0117] In at least one embodiment of the present disclosure, each driving circuit in the driving module is electrically connected with LSP, GRST and VDD.

[0118] The driving circuit in at least one embodiment of the present disclosure further comprises a reset circuit.

[0119] The reset circuit is electrically connected with the reset control end, the first node and the second voltage end respectively, and is used for controlling the first node to be connected or disconnected with the second voltage end under the control of a reset control signal provided by the reset control end.

[0120] In a specific implementation, the driving circuit further includes a reset circuit, which controls the first node to be connected or disconnected with the second voltage end under the control of a reset control signal.

[0121] Optionally, the second voltage end is a first low-voltage end.

[0122] As shown in FIG. 2, on the basis of at least one of the embodiments of the driving circuit shown in FIG. 1, the driving circuit in at least one of the embodiments of the present disclosure further includes a reset circuit 21.

[0123] The reset circuit 21 is electrically connected with a reset control end STV, the first node PU and a second voltage end V2 respectively, and is used for controlling the first node PU to be connected or disconnected with the second voltage end V2 under the control of a reset control signal provided by the reset control end STV.

[0124] When the reset control signal is a valid voltage signal, the reset circuit 21 controls the first node PU to be connected with the second voltage end V2 under the control of the reset control signal provided by the reset control end STV, so as to reset the potential of PU, so that the corresponding row driving circuit outputs an invalid driving signal, the corresponding row driving circuit is closed, and it can be determined which row the display stops at. The reset control signal is used as a local display stop control signal, and in global scanning, the reset control signal is used as a frame reset signal, so as to reset the PU node before a frame starts.

[0125] Optionally, the node control circuit includes a first transistor, a second transistor and a third transistor.

[0126] The gate of the first transistor is electrically connected with the scan control end, the first pole of the first transistor is electrically connected with the input end, and the second pole of the first transistor is electrically connected with the intermediate node.

[0127] The gate of the second transistor is electrically connected with the scan control end, the first pole of the second transistor is electrically connected with the intermediate node, and the second pole of the second transistor is electrically connected with the control node.

[0128] The gate of the third transistor is electrically connected with the control node, the first pole of the third transistor is electrically connected with the first voltage end, and the second pole of the third transistor is electrically connected with the intermediate node.

[0129] Optionally, the first node charging circuit comprises a fourth transistor and a fifth transistor, and the first energy storage circuit comprises a first capacitor;

[0130] The gate of the fourth transistor is electrically connected with the control node, the first pole of the fourth transistor is electrically connected with the first voltage terminal, and the second pole of the fourth transistor is electrically connected with the first pole of the fifth transistor;

[0131] The gate of the fifth transistor is electrically connected with the set control terminal, and the second pole of the fifth transistor is electrically connected with the first node.

[0132] The first end of the first capacitor is electrically connected with the control node, and the second end of the first capacitor is electrically connected with the direct current voltage terminal.

[0133] Optionally, the direct current voltage terminal can be a high voltage terminal (when the transistor is an N-type transistor, it is a high voltage terminal, and when the transistor is a P-type transistor, it is a low voltage terminal. In this case, an N-type transistor is used as an example for illustration).

[0134] Optionally, the input circuit comprises a sixth transistor.

[0135] The gate of the sixth transistor is electrically connected with the first pole of the sixth transistor and the input terminal, and the second pole of the sixth transistor is electrically connected with the first node.

[0136] Optionally, the reset circuit comprises a seventh transistor.

[0137] The gate of the seventh transistor is electrically connected with the reset control terminal, the first pole of the seventh transistor is electrically connected with the first node, and the second pole of the seventh transistor is electrically connected with the second voltage terminal.

[0138] The driving circuit in at least one embodiment of the present disclosure further comprises a first node reset circuit and a pull-up node control circuit.

[0139] The first node reset circuit is electrically connected with the pull-up reset terminal, the first node and the second voltage terminal respectively, and is used to control the communication or disconnection between the first node and the second voltage terminal under the control of the pull-up reset signal provided by the pull-up reset terminal.

[0140] The pull-up node control circuit is electrically connected with the first second node, the second second node, the first node and the second voltage terminal respectively, and is used to control the communication or disconnection between the first node and the second voltage terminal under the control of the potential of the first second node, and control the communication or disconnection between the first node and the second voltage terminal under the control of the potential of the second second node.

[0141] In specific implementation, the driving circuit can further include a first node reset circuit and a pull-up node control circuit, the first node reset circuit controls the first node to be connected or disconnected with the second voltage terminal under the control of a pull-up reset signal, and the pull-up node control circuit controls the first node to be connected or disconnected with the second voltage terminal under the control of the potential of the first second node and under the control of the potential of the second second node.

[0142] As shown in FIG. 3, on the basis of at least one embodiment of the driving circuit shown in FIG. 2, the driving circuit in at least one embodiment of the present disclosure further includes a first node reset circuit 31 and a pull-up node control circuit 32.

[0143] The first node reset circuit 31 is electrically connected with a pull-up reset terminal RSTP, the first node PU and the second voltage terminal V2 respectively, and is configured to control the first node PU to be connected or disconnected with the second voltage terminal V2 under the control of a pull-up reset signal provided by the pull-up reset terminal RSTP.

[0144] The pull-up node control circuit 32 is electrically connected with a first second node PD1, a second second node PD2, the first node PU and the second voltage terminal V2 respectively, and is configured to control the first node PU to be connected or disconnected with the second voltage terminal V2 under the control of the potential of the first second node PD1 and under the control of the potential of the second second node PD2.

[0145] In at least one embodiment of the present disclosure, two second nodes are taken as an example for the driving circuit; in specific implementation, the driving circuit can also use only one second node.

[0146] In at least one embodiment of the present disclosure, the driving circuit further includes a carry signal output circuit and a driving signal output circuit.

[0147] The carry signal output circuit is electrically connected with the first node, the first second node, the second second node, a carry signal output terminal, an output clock signal terminal and the second voltage terminal respectively, and is configured to control the carry signal output terminal to be connected or disconnected with the output clock signal terminal under the control of the potential of the first node, to be connected or disconnected with the second voltage terminal under the control of the potential of the first second node, and to be connected or disconnected with the second voltage terminal under the control of the potential of the second second node.

[0148] The drive signal output circuit is electrically connected with the first node, the first second node, the second second node, the drive signal output end, the output clock signal end and the third voltage end respectively, and is used for controlling the drive signal output end to be connected or disconnected with the output clock signal end under the control of the potential of the first node, controlling the drive signal output end to be connected or disconnected with the third voltage end under the control of the potential of the first second node, and controlling the drive signal output end to be connected or disconnected with the third voltage end under the control of the potential of the second second node.

[0149] In a specific implementation, the drive circuit can further include a carry signal output circuit and a drive signal output circuit; the carry signal output circuit controls the carry signal output end to be connected or disconnected with the output clock signal end under the control of the potential of the first node, controls the carry signal output end to be connected or disconnected with the second voltage end under the control of the potential of the first second node, and controls the carry signal output end to be connected or disconnected with the second voltage end under the control of the potential of the second second node; and the drive signal output circuit controls the drive signal output end to be connected or disconnected with the output clock signal end under the control of the potential of the first node, controls the drive signal output end to be connected or disconnected with the third voltage end under the control of the potential of the first second node, and controls the drive signal output end to be connected or disconnected with the third voltage end under the control of the potential of the second second node. The carry signal output circuit outputs a carry signal, and the carry signal is used for cascading; and the drive signal output circuit outputs a drive signal, and the drive signal is used for driving a corresponding row scanning line.

[0150] The drive circuit in at least one embodiment of the present disclosure further includes a second energy storage circuit;

[0151] The first end of the second energy storage circuit is electrically connected with the first node, and the second end of the second energy storage circuit is electrically connected with the drive signal output end, and the second energy storage circuit is used for storing electric energy.

[0152] In a specific implementation, the drive circuit can further include a second energy storage circuit, and the second energy storage circuit can control the potential of the first node according to the drive signal.

[0153] As shown in FIG. 4, on the basis of at least one embodiment of the drive circuit shown in FIG. 3, the drive circuit in at least one embodiment of the present disclosure further includes a carry signal output circuit 41, a drive signal output circuit 42 and a second energy storage circuit 43.

[0154] The carry signal output circuit 41 is electrically connected with the first node PU, the first second node PD1, the second second node PD2, a carry signal output end OC, an output clock signal end CLK and a second voltage end V2, for controlling the communication or disconnection between the carry signal output end OC and the output clock signal end CLK under the control of the potential of the first node PU, controlling the communication or disconnection between the carry signal output end OC and the second voltage end V2 under the control of the potential of the first second node PD1, and controlling the communication or disconnection between the carry signal output end OC and the second voltage end V2 under the control of the potential of the second second node PD2.

[0155] The drive signal output circuit 42 is electrically connected with the first node PU, the first second node PD1, the second second node PD2, a drive signal output end GT, the output clock signal end CLK and a third voltage end V3, for controlling the communication or disconnection between the drive signal output end GT and the output clock signal end CLK under the control of the potential of the first node PU, controlling the communication or disconnection between the drive signal output end GT and the third voltage end V3 under the control of the potential of the first second node PD1, and controlling the communication or disconnection between the drive signal output end GT and the third voltage end V3 under the control of the potential of the second second node PD2.

[0156] The first end of the second energy storage circuit 43 is electrically connected with the first node PU, and the second end of the second energy storage circuit 43 is electrically connected with the drive signal output end GT, and the second energy storage circuit 43 is used for storing electric energy.

[0157] Optionally, the second voltage end can be a first low voltage end, and the third voltage end can be a second low voltage end.

[0158] The drive circuit in at least one embodiment of the present disclosure further comprises a first second node control circuit and a second second node control circuit.

[0159] The first second node control circuit is electrically connected with a first control voltage end, a first intermediate control node, a first node, a first second node and a second voltage end, for controlling the potential of the first intermediate control node under the control of a first control voltage provided by the first control voltage end, controlling the communication or disconnection between the first intermediate control node and the second voltage end under the control of the potential of the first node, controlling the communication or disconnection between the first control voltage end and the first second node under the control of the potential of the first intermediate control node, and controlling the communication or disconnection between the first second node and the second voltage end under the control of the potential of the first node.

[0160] The second second node control circuit is electrically connected with the second control voltage terminal, the second intermediate control node, the first node, the second second node and the second voltage terminal respectively, and is configured to control the electric potential of the second intermediate control node under the control of the second control voltage provided by the second control voltage terminal, control the communication or disconnection between the second intermediate control node and the second voltage terminal under the control of the electric potential of the first node, control the communication or disconnection between the second control voltage terminal and the second second node under the control of the electric potential of the second intermediate control node, and control the communication or disconnection between the second second node and the second voltage terminal under the control of the electric potential of the first node.

[0161] In a specific implementation, the driving circuit further includes a first second node control circuit and a second second node control circuit; the first second node control circuit controls the electric potential of the first intermediate control node under the control of the first control voltage, controls the communication or disconnection between the first intermediate control node and the second voltage terminal under the control of the electric potential of the first node, controls the communication or disconnection between the first control voltage terminal and the first second node under the control of the electric potential of the first intermediate control node, and controls the communication or disconnection between the first second node and the second voltage terminal under the control of the electric potential of the first node; and the second second node control circuit controls the electric potential of the second intermediate control node under the control of the second control voltage, controls the communication or disconnection between the second intermediate control node and the second voltage terminal under the control of the electric potential of the first node, controls the communication or disconnection between the second control voltage terminal and the second second node under the control of the electric potential of the second intermediate control node, and controls the communication or disconnection between the second second node and the second voltage terminal under the control of the electric potential of the first node.

[0162] As shown in FIG. 5, on the basis of at least one embodiment of the driving circuit shown in FIG. 4, the driving circuit in at least one embodiment of the present disclosure further includes a first second node control circuit 51 and a second second node control circuit 52.

[0163] The first second node control circuit 51 is electrically connected with the first control voltage terminal VDDO, the first intermediate control node PD CN1, the first node PU, the first second node PD1 and the second voltage terminal V2 respectively, and is configured to control the potential of the first intermediate control node PD CN1 under the control of the first control voltage provided by the first control voltage terminal VDDO, control the communication or disconnection between the first intermediate control node PD CN1 and the second voltage terminal V2 under the control of the potential of the first node PU, control the communication or disconnection between the first control voltage terminal VDDO and the first second node PD1 under the control of the potential of the first intermediate control node PD CN1, and control the communication or disconnection between the first second node PD2 and the second voltage terminal V2 under the control of the potential of the first node PU.

[0164] The second second node control circuit 52 is electrically connected with the second control voltage terminal VDDE, the second intermediate control node PD CN2, the first node PU, the second second node PD2 and the second voltage terminal V2 respectively, and is configured to control the potential of the second intermediate control node PD CN2 under the control of the second control voltage provided by the second control voltage terminal VDD3, control the communication or disconnection between the second intermediate control node PD CN2 and the second voltage terminal V2 under the control of the potential of the first node PU, control the communication or disconnection between the second control voltage terminal VDDE and the second second node PD2 under the control of the potential of the second intermediate control node PD CN2, and control the communication or disconnection between the second second node PD2 and the second voltage terminal V2 under the control of the potential of the first node PU.

[0165] The driving circuit also includes a first second node control circuit and a second second node control circuit.

[0166] The first second node control circuit is electrically connected with the first control voltage terminal, the first node, the first second node and the second voltage terminal respectively, and is configured to control the potential of the first second node under the control of the first control voltage provided by the first control voltage terminal, and control the communication or disconnection between the first second node and the second voltage terminal under the control of the potential of the first node.

[0167] The second second node control circuit is electrically connected with the second control voltage terminal, the first node, the second second node and the second voltage terminal respectively, and is configured to control the potential of the second second node under the control of the second control voltage provided by the second control voltage terminal, and control the communication or disconnection between the second second node and the second voltage terminal under the control of the potential of the first node.

[0168] In a specific implementation, the driving circuit can further include a first second-node control circuit and a second second-node control circuit; the first second-node control circuit is configured to control the potential of the first second node under the control of the first control voltage, and control the communication or disconnection between the first second node and the second voltage end under the control of the potential of the first node; the second second-node control circuit is configured to control the potential of the second second node under the control of the second control voltage, and control the communication or disconnection between the second second node and the second voltage end under the control of the potential of the first node.

[0169] As shown in FIG. 6, on the basis of at least one embodiment of the driving circuit shown in FIG. 4, the driving circuit according to at least one embodiment of the present disclosure further includes a first second-node control circuit 51 and a second second-node control circuit 52.

[0170] The first second-node control circuit 51 is electrically connected with the first control voltage end VDDO, the first node PU, the first second node PD1 and the second voltage end V2 respectively, and is configured to control the potential of the first second node PD1 under the control of the first control voltage provided by the first control voltage end VDDO, and control the communication or disconnection between the first second node PD1 and the second voltage end V2 under the control of the potential of the first node PU.

[0171] The second second-node control circuit 52 is electrically connected with the second control voltage end VDDE, the first node PU, the second second node PD2 and the second voltage end V2 respectively, and is configured to control the potential of the second second node PD2 under the control of the second control voltage provided by the second control voltage end VDDE, and control the communication or disconnection between the second second node PD2 and the second voltage end V2 under the control of the potential of the first node PU.

[0172] The driving circuit according to at least one embodiment of the present disclosure further includes a second-node reset circuit.

[0173] The second-node reset circuit is electrically connected with the input end, the first second node, the second second node and the second voltage end respectively, and is configured to control the communication or disconnection between the first second node and the second voltage end, and control the communication or disconnection between the second second node and the second voltage end under the control of the input signal provided by the input end.

[0174] In a specific implementation, the driving circuit can further include a second node reset circuit, which is controlled by the input signal to control the first second node and the second voltage terminal to be connected or disconnected, and control the second second node and the second voltage terminal to be connected or disconnected.

[0175] As shown in FIG. 7, based on at least one embodiment of the driving circuit shown in FIG. 5, the driving circuit according to at least one embodiment of the present disclosure further includes a second node reset circuit 71.

[0176] The second node reset circuit 71 is electrically connected with the input terminal I1, the first second node PD1, the second second node PD2 and the second voltage terminal V2 respectively, and is used to control the first second node PD1 and the second voltage terminal V2 to be connected or disconnected under the control of the input signal provided by the input terminal I1, and control the second second node PD2 and the second voltage terminal V2 to be connected or disconnected.

[0177] As shown in FIG. 8, based on at least one embodiment of the driving circuit shown in FIG. 6, the driving circuit according to at least one embodiment of the present disclosure further includes a second node reset circuit 71.

[0178] The second node reset circuit 71 is electrically connected with the input terminal I1, the first second node PD1, the second second node PD2 and the second voltage terminal V2 respectively, and is used to control the first second node PD1 and the second voltage terminal V2 to be connected or disconnected under the control of the input signal provided by the input terminal I1, and control the second second node PD2 and the second voltage terminal V2 to be connected or disconnected.

[0179] Optionally, the first node reset circuit includes an eighth transistor, and the pull-up node control circuit includes a ninth transistor and a tenth transistor.

[0180] The gate of the eighth transistor is electrically connected with the pull-up reset terminal, the first pole of the eighth transistor is electrically connected with the first node, and the second pole of the eighth transistor is electrically connected with the second voltage terminal.

[0181] The gate of the ninth transistor is electrically connected with the first second node, the first pole of the ninth transistor is electrically connected with the first node, and the second pole of the ninth transistor is electrically connected with the second voltage terminal.

[0182] The gate of the tenth transistor is electrically connected with the second second node, the first pole of the tenth transistor is electrically connected with the first node, and the second pole of the tenth transistor is electrically connected with the second voltage terminal.

[0183] Optionally, the carry signal output circuit comprises an eleventh transistor, a twelfth transistor and a thirteenth transistor;

[0184] The gate of the eleventh transistor is electrically connected with the first node, the first pole of the eleventh transistor is electrically connected with the output clock signal end, and the second pole of the eleventh transistor is electrically connected with the carry signal output end;

[0185] The gate of the twelfth transistor is electrically connected with the first second node, the first pole of the twelfth transistor is electrically connected with the carry signal output end, and the second pole of the twelfth transistor is electrically connected with the second voltage end;

[0186] The gate of the thirteenth transistor is electrically connected with the second second node, the first pole of the thirteenth transistor is electrically connected with the carry signal output end, and the second pole of the thirteenth transistor is electrically connected with the second voltage end;

[0187] The drive signal output circuit comprises a fourteenth transistor, a fifteenth transistor and a sixteenth transistor;

[0188] The gate of the fourteenth transistor is electrically connected with the first node, the first pole of the fourteenth transistor is electrically connected with the output clock signal end, and the second pole of the fourteenth transistor is electrically connected with the drive signal output end;

[0189] The gate of the fifteenth transistor is electrically connected with the first second node, the first pole of the fifteenth transistor is electrically connected with the drive signal output end, and the second pole of the fifteenth transistor is electrically connected with the third voltage end;

[0190] The gate of the sixteenth transistor is electrically connected with the second second node, the first pole of the sixteenth transistor is electrically connected with the drive signal output end, and the second pole of the sixteenth transistor is electrically connected with the third voltage end.

[0191] Optionally, the second energy storage circuit comprises a second capacitor;

[0192] The first end of the second capacitor is electrically connected with the first node, and the second end of the second capacitor is electrically connected with the drive signal output end.

[0193] Optionally, the first second node control circuit comprises a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a twentieth transistor;

[0194] The gate of the seventeenth transistor and the first pole of the seventeenth transistor are electrically connected with the first control voltage end, and the second pole of the seventeenth transistor is electrically connected with the first intermediate control node;

[0195] The gate of the eighteenth transistor is electrically connected with the first node, the first pole of the eighteenth transistor is electrically connected with the first intermediate control node, and the second pole of the eighteenth transistor is electrically connected with the second voltage end;

[0196] The gate of the nineteenth transistor is electrically connected with the first intermediate control node, the first pole of the nineteenth transistor is electrically connected with the first control voltage end, and the second pole of the nineteenth transistor is electrically connected with the first second node;

[0197] The gate of the twentieth transistor is electrically connected with the first node, the first pole of the twentieth transistor is electrically connected with the first second node, and the second pole of the twentieth transistor is electrically connected with the second voltage end;

[0198] The second second node control circuit comprises twenty-first, twenty-second, twenty-third and twenty-fourth transistors;

[0199] The gate of the twenty-first transistor and the first pole of the twenty-first transistor are electrically connected with the second control voltage end, and the second pole of the twenty-first transistor is electrically connected with the second intermediate control node;

[0200] The gate of the twenty-second transistor is electrically connected with the first node, the first pole of the twenty-second transistor is electrically connected with the second intermediate control node, and the second pole of the twenty-second transistor is electrically connected with the second voltage end;

[0201] The gate of the twenty-third transistor is electrically connected with the second intermediate control node, the first pole of the twenty-third transistor is electrically connected with the second control voltage end, and the second pole of the twenty-second transistor is electrically connected with the second second node;

[0202] The gate of the twenty-fourth transistor is electrically connected with the first node, the first pole of the twenty-fourth transistor is electrically connected with the second second node, and the second pole of the twenty-fourth transistor is electrically connected with the second voltage end.

[0203] Optionally, the first second node control circuit comprises twenty-fifth and twenty-sixth transistors;

[0204] The gate of the twenty-fifth transistor and the first pole of the twenty-fifth transistor are electrically connected with the first control voltage end, and the second pole of the twenty-fifth transistor is electrically connected with the first second node;

[0205] A gate of the twenty-sixth transistor is electrically connected with the first node, a first electrode of the twenty-sixth transistor is electrically connected with the first second node, and a second electrode of the twenty-sixth transistor is electrically connected with the second voltage terminal;

[0206] The second second node control circuit includes a twenty-seventh transistor and a twenty-eighth transistor;

[0207] A gate of the twenty-seventh transistor and a first electrode of the twenty-seventh transistor are electrically connected with the second control voltage terminal, and a second electrode of the twenty-seventh transistor is electrically connected with the second second node;

[0208] A gate of the twenty-eighth transistor is electrically connected with the first node, a first electrode of the twenty-eighth transistor is electrically connected with the second second node, and a second electrode of the twenty-eighth transistor is electrically connected with the second voltage terminal.

[0209] Optionally, the second node reset circuit includes a twenty-ninth transistor and a thirtieth transistor;

[0210] A gate of the twenty-ninth transistor is electrically connected with the input terminal, a first electrode of the twenty-ninth transistor is electrically connected with the first second node, and a second electrode of the twenty-ninth transistor is electrically connected with the second voltage terminal.

[0211] A gate of the thirtieth transistor is electrically connected with the input terminal, a first electrode of the thirtieth transistor is electrically connected with the second second node, and a second electrode of the thirtieth transistor is electrically connected with the second voltage terminal.

[0212] As shown in FIG. 9, on the basis of at least one embodiment of the driving circuit shown in FIG. 7,

[0213] The node control circuit includes a first transistor M1, a second transistor M2 and a third transistor M3;

[0214] A gate of the first transistor M1 is electrically connected with the scan control terminal LSP, a drain of the first transistor M1 is electrically connected with the input terminal I1, and a source of the first transistor M1 is electrically connected with the intermediate node NZ;

[0215] A gate of the second transistor M2 is electrically connected with the scan control terminal LSP, a drain of the second transistor M2 is electrically connected with the intermediate node NZ, and a second electrode of the second transistor M2 is electrically connected with the control node M;

[0216] A gate of the third transistor M3 is electrically connected with the control node M, a drain of the third transistor M3 is electrically connected with the high voltage terminal VDD, and a source of the third transistor M3 is electrically connected with the intermediate node NZ.

[0217] The first node charging circuit comprises a fourth transistor M4 and a fifth transistor M5, and the first energy storage circuit comprises a first capacitor C1;

[0218] The gate of the fourth transistor M4 is electrically connected with the control node M, the drain of the fourth transistor M4 is electrically connected with the high voltage end VDD, and the source of the fourth transistor M4 is electrically connected with the drain of the fifth transistor M5;

[0219] The gate of the fifth transistor M5 is electrically connected with the set control end GRST, and the source of the fifth transistor M5 is electrically connected with the first node PU;

[0220] The first end of the first capacitor C1 is electrically connected with the control node M, and the second end of the first capacitor C1 is electrically connected with the high voltage end VDD;

[0221] The input circuit comprises a sixth transistor M6;

[0222] The gate of the sixth transistor M6 is electrically connected with the drain of the sixth transistor M6 and the input end I1, and the source of the sixth transistor M6 is electrically connected with the first node PU;

[0223] The reset circuit comprises a seventh transistor M7;

[0224] The gate of the seventh transistor M7 is electrically connected with the reset control end STV, the drain of the seventh transistor M7 is electrically connected with the first node PU, and the source of the seventh transistor M7 is electrically connected with the first low voltage end LVSS;

[0225] The first node reset circuit comprises an eighth transistor M8, and the pull-up node control circuit comprises a ninth transistor M9 and a tenth transistor M10;

[0226] The gate of the eighth transistor M8 is electrically connected with the pull-up reset end RSTP, the drain of the eighth transistor M8 is electrically connected with the first node PU, and the source of the eighth transistor M8 is electrically connected with the first low voltage end LVSS;

[0227] The gate of the ninth transistor M9 is electrically connected with the first second node PD1, the drain of the ninth transistor M9 is electrically connected with the first node PU, and the source of the ninth transistor M9 is electrically connected with the first low voltage end LVSS;

[0228] The gate of the tenth transistor M10 is electrically connected with the second node PD2, the drain of the tenth transistor is electrically connected with the first node PU, and the source of the tenth transistor M9 is electrically connected with the first low voltage terminal LVSS;

[0229] The carry signal output circuit comprises an eleventh transistor M11, a twelfth transistor M12 and a thirteenth transistor M13;

[0230] The gate of the eleventh transistor M11 is electrically connected with the first node PU, the drain of the eleventh transistor M11 is electrically connected with the output clock signal terminal CLK, and the source of the eleventh transistor M11 is electrically connected with the carry signal output terminal OC;

[0231] The gate of the twelfth transistor M12 is electrically connected with the first node PD1, the drain of the twelfth transistor M12 is electrically connected with the carry signal output terminal OC, and the source of the twelfth transistor M12 is electrically connected with the first low voltage terminal LVSS;

[0232] The gate of the thirteenth transistor M13 is electrically connected with the second node PD2, the drain of the thirteenth transistor M13 is electrically connected with the carry signal output terminal OC, and the source of the thirteenth transistor M13 is electrically connected with the first low voltage terminal LVSS;

[0233] The drive signal output circuit comprises a fourteenth transistor M14, a fifteenth transistor M15 and a sixteenth transistor M16;

[0234] The gate of the fourteenth transistor M14 is electrically connected with the first node PU, the drain of the fourteenth transistor M14 is electrically connected with the output clock signal terminal CLK, and the source of the fourteenth transistor M14 is electrically connected with the drive signal output terminal GT;

[0235] The gate of the fifteenth transistor M15 is electrically connected with the first node PD1, the drain of the fifteenth transistor M15 is electrically connected with the drive signal output terminal GT, and the source of the fifteenth transistor M15 is electrically connected with the second low voltage terminal VSS;

[0236] The gate of the sixteenth transistor M16 is electrically connected with the second node PD2, the drain of the sixteenth transistor M16 is electrically connected with the drive signal output terminal GT, and the source of the sixteenth transistor M16 is electrically connected with the second low voltage terminal VSS;

[0237] The second energy storage circuit comprises a second capacitor C2;

[0238] A first end of the second capacitor C2 is electrically connected with the first node PU, and a second end of the second capacitor C2 is electrically connected with the driving signal output end GT.

[0239] The first second node control circuit comprises a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19 and a twentieth transistor M20.

[0240] The gate of the seventeenth transistor M17 and the drain of the seventeenth transistor M17 are electrically connected with the first control voltage end VDDO, and the source of the seventeenth transistor M17 is electrically connected with the first intermediate control node PD_CN1.

[0241] The gate of the eighteenth transistor M18 is electrically connected with the first node PU, the drain of the eighteenth transistor M18 is electrically connected with the first intermediate control node PD_CN1, and the source of the eighteenth transistor M18 is electrically connected with the first low voltage end LVSS.

[0242] The gate of the nineteenth transistor M19 is electrically connected with the first intermediate control node PD_CN1, the drain of the nineteenth transistor M19 is electrically connected with the first control voltage end VDDO, and the source of the nineteenth transistor M19 is electrically connected with the first second node PD1.

[0243] The gate of the twentieth transistor M20 is electrically connected with the first node PU, the drain of the twentieth transistor M20 is electrically connected with the first second node PD1, and the source of the twentieth transistor M20 is electrically connected with the first low voltage end LVSS.

[0244] The second second node control circuit comprises a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23 and a twenty-fourth transistor M24.

[0245] The gate of the twenty-first transistor M21 and the drain of the twenty-first transistor M21 are electrically connected with the second control voltage end VDDE, and the source of the twenty-first transistor M21 is electrically connected with the second intermediate control node PD_CN2.

[0246] The gate of the twenty-second transistor M22 is electrically connected with the first node PU, the drain of the twenty-second transistor M22 is electrically connected with the second intermediate control node PD_CN2, and the source of the twenty-second transistor M22 is electrically connected with the first low voltage end LVSS.

[0247] The gate of the twenty-third transistor M23 is electrically connected with the second intermediate control node PD CN2, the drain of the twenty-third transistor M23 is electrically connected with the second control voltage terminal VDDE, and the source of the twenty-third transistor M23 is electrically connected with the second second node PD2;

[0248] The gate of the twenty-fourth transistor M24 is electrically connected with the first node PU, the drain of the twenty-fourth transistor M24 is electrically connected with the second second node PD2, and the source of the twenty-fourth transistor M24 is electrically connected with the first low voltage terminal LVSS;

[0249] The second node reset circuit includes a twenty-ninth transistor M29 and a thirtieth transistor M30;

[0250] The gate of the twenty-ninth transistor M29 is electrically connected with the input terminal I1, the drain of the twenty-ninth transistor M29 is electrically connected with the first second node PD1, and the source of the twenty-ninth transistor M29 is electrically connected with the first low voltage terminal LVSS;

[0251] The gate of the thirtieth transistor M30 is electrically connected with the input terminal I1, the drain of the thirtieth transistor M30 is electrically connected with the second second node PD2, and the source of the thirtieth transistor M30 is electrically connected with the first low voltage terminal LVSS.

[0252] In at least one embodiment of the driving circuit shown in FIG. 9, all the transistors are n-type transistors.

[0253] At least one embodiment of the present disclosure proposes a driving circuit supporting the arbitrary row display function, which can realize arbitrary row display corresponding to the driving signal. Compared with related driving circuits, the driving circuit has the following advantages:

[0254] 1. Compatible with existing process, no additional circuit cost, and mass production;

[0255] 2. Better flexibility, can support single row opening in frame;

[0256] 3. Stronger reliability, the introduction of the 5T1C unit (the 5T1C unit includes M1-M5 and C1) makes the potential of the first node in the driving circuit of the non-display area not need to be high, avoiding the risk of abnormal display due to leakage, and the transistor has a long service life.

[0257] When the driving module including at least one embodiment of the driving circuit shown in FIG. 9 works, the last frame before switching the local display mode is a global display frame, and each row driving circuit included in the driving module is opened in turn;

[0258] If the display starts from the nth row driving circuit in the local display mode, when the input end I1 of the nth row driving circuit is connected to the high voltage signal in the global display frame, the LSP provides the high voltage signal, at this time, M1 and M2 are opened, the input signal provided by I1 charges the control node M through M1 and M2, when the potential of the control node M rises, M3 is opened, the high voltage signal provided by VDD further charges the control node M through M3, the potential of the control node M is lifted, M4 is opened, and C1 plays a potential maintaining role; when the input signal of the nth row driving circuit becomes a low voltage signal, the LSP provides a low voltage signal, and due to the potential maintaining role of C1, the high potential of the control node M is maintained; when the local display mode is switched, the frame start signal STV1 stops inputting, the signal provided by GRST is switched to a high voltage signal, M5 is opened, at this time, the high voltage signal provided by VDD charges the first node PU in the nth row driving circuit through M4 and M5, M14 is opened, when the output clock signal end CLK connected with the nth row driving circuit outputs a high voltage signal, the nth row driving circuit outputs a high voltage signal through its driving signal output end, and normally cascades and opens the subsequent driving circuit, in the local display area, M6, M14 and M11 normally open / close according to the cascade signal, and the local display function starting from the nth row driving circuit is realized; if the next frame is still the local display starting from the nth row driving circuit, the global display frame is not needed, and the local display function starting from the nth row driving circuit can be repeatedly realized by repeatedly inputting the set control signal.

[0259] The reset control signal provided by STV is used as a local display stop signal, and it can be determined which row the display stops at; when the reset control signal provided by STV is a high voltage signal, M7 is opened, the potential of PU is pulled low to a low level, M14 is closed, and the row driving circuit is closed.

[0260] When the driving module including the driving circuit described in at least one embodiment of the present disclosure works, when the display function of any row is opened, the first node in the driving circuit in the non-display area will not be pulled high, M14 and M11 are always in the closed state, only the driving circuit in the display area can normally cascade and open, and the effect of single-row display in a frame can be realized, and the real meaning of arbitrary row display is achieved, in addition, cooperating with the timing adjustment of the driving signal, only the set control signal is started in the local display mode, the cascade signal in the non-display area is not needed to start, and the refresh rate can be improved.

[0261] In the driving module comprising at least one embodiment of the driving circuit shown in FIG. 9 of the present disclosure, referring to FIG. 16A and FIG. 12 simultaneously, when 12 clock signal lines are adopted, the first row driving circuit inputs for the seventh row driving circuit, and the ninth row driving circuit resets for the first row driving circuit. If local display is performed from the ninth row of the jth frame, in order to charge the M point in the ninth row driving circuit of the jth frame, the scan control signal provided by the scan control end LSP in the ninth row driving circuit of the j-1th frame needs to be in phase with the input signal in the ninth row driving circuit of the j-1th frame, that is, in phase with the cascade signal provided by the cascade signal output end in the third row driving circuit of the j-1th frame, and the control node in the ninth row driving circuit of the j-1th frame is pulled high to high potential. The jth frame switches to the local display mode started by the ninth row driving circuit, the reset control signal provided by the STV stops inputting, and the set control signal provided by the GRST is used to start display. When the GRST provides a high voltage signal, the potential of the first node in the driving circuit with the control node M at high potential is pulled high, M14 in the driving circuit is opened, and when the output clock signal end connected to the driving circuit provides a high voltage signal, the driving circuit can be opened and normally output the cascade signal.

[0262] In the driving module comprising at least one embodiment of the driving circuit shown in FIG. 9 of the present disclosure, all M7 in the driving circuit are electrically connected with the STV. When local display is performed, for example, scanning from the ninth row driving circuit to the twentieth row driving circuit, and the twenty-first row pixel circuit does not display, after scanning the twentieth row driving circuit, the STV provides a high voltage signal to make M7 open and stop scanning.

[0263] In FIG. 10, the first clock signal line is labeled as CLK1, the second clock signal line is labeled as CLK2, the third clock signal line is labeled as CLK3, the fourth clock signal line is labeled as CLK4, the fifth clock signal line is labeled as CLK5, the sixth clock signal line is labeled as CLK6, the seventh clock signal line is labeled as CLK7, the eighth clock signal line is labeled as CLK8, the ninth clock signal line is labeled as CLK9, the tenth clock signal line is labeled as CLK10, the eleventh clock signal line is labeled as CLK11, and the twelfth clock signal line is labeled as CLK12;

[0264] The 12th row of the driving circuit is electrically connected with CLK1, the 12th row of the driving circuit is electrically connected with CLK2, the 12th row of the driving circuit is electrically connected with CLK3, the 12th row of the driving circuit is electrically connected with CLK4, the 12th row of the driving circuit is electrically connected with CLK5, the 12th row of the driving circuit is electrically connected with CLK6, the 12th row of the driving circuit is electrically connected with CLK7, the 12th row of the driving circuit is electrically connected with CLK8, the 12th row of the driving circuit is electrically connected with CLK9, the 12th row of the driving circuit is electrically connected with CLK10, the 12th row of the driving circuit is electrically connected with CLK1, the 12th row of the driving circuit is electrically connected with CLK2, and c is a positive integer.

[0265] As shown in FIG. 10, when the at least one embodiment of the driving circuit shown in FIG. 9 of the present disclosure is working, the (j-1)th frame Fj-1 is a global display frame, and the jth frame Fj is a local display frame.

[0266] In the (j-1)th frame Fj-1, CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, CLK8, CLK9, CLK10, CLK11 and CLK12 respectively provide corresponding clock signals, and the first row of driving circuit to the twelfth row of driving circuit outputs high voltage signals in turn.

[0267] In the jth frame Fj, when CLK9 outputs a high voltage signal for the first time, the ninth row of driving circuit outputs a high voltage signal, when CLK1 outputs a high voltage signal for the first time, the thirteenth row of driving circuit outputs a high voltage signal, and local display starts from the ninth row of driving circuit.

[0268] When the ninth row of driving circuit is reset as the first row of driving circuit, in order to charge the control node of the ninth row of driving circuit, the scan control signal provided by LSP needs to be in phase with the input signal accessed by the ninth row of driving circuit, that is, in phase with the carry signal output by the third row of driving circuit (the third row of driving circuit provides the input signal for the ninth row of driving circuit), and the potential of the control node of the ninth row of driving circuit is pulled to high potential. In the (j+1)th frame, the local display mode starting from the ninth row is switched, the frame start signal STV1 stops inputting, and the signal provided by GRST is used to start display instead. When the signal provided by GRST is a high voltage signal, the potential of the first node in the driving circuit with high potential control node will be pulled high, M11 in the driving circuit will be opened, and when the output clock signal is a high voltage signal, the driving circuit can be opened and normally output the carry signal.

[0269] FIG. 11 is a simulation working timing diagram of the driving module comprising the at least one embodiment of the driving circuit shown in FIG. 9 of the present disclosure.

[0270] In FIG. 11, the label PU_G9 is a first node in the ninth row driving circuit, the label M_G9 is a control node in the ninth row driving circuit, the label G9 is a driving signal output end of the ninth row driving circuit, the label G10 is a driving signal output end of the tenth row driving circuit, the label G11 is a driving signal output end of the eleventh row driving circuit, the label G12 is a driving signal output end of the twelfth row driving circuit, the label G13 is a driving signal output end of the thirteenth row driving circuit, the label G14 is a driving signal output end of the fourteenth row driving circuit, the label G15 is a driving signal output end of the fifteenth row driving circuit, the label G16 is a driving signal output end of the sixteenth row driving circuit, the label G17 is a driving signal output end of the seventeenth row driving circuit, the label G18 is a driving signal output end of the eighteenth row driving circuit, and the label G19 is a driving signal output end of the nineteenth row driving circuit.

[0271] In FIG. 11, the label Fj-1 is a j-1 frame, the label Fj is a j frame, and the label Fj+1 is a j+1 frame; j is a positive integer.

[0272] The j-1 frame Fj-1 is a global display frame, the j frame Fj is a partial display frame, and the j+1 frame Fj+1 is a partial display frame.

[0273] In the j frame Fj, partial scanning is performed starting from the ninth row driving circuit.

[0274] In the j+1 frame Fj+1, only the ninth row driving circuit performs scanning.

[0275] In the j-1 frame Fj-1, each row driving circuit outputs a high voltage signal in turn.

[0276] In the j+1 frame Fj+1, after the ninth row driving circuit is turned on, the STV connected to each row driving circuit provides a high voltage signal to pull down the potential of the first node in all row driving circuits, and the clock signal provided by each clock signal line is all set to low, thereby realizing the ninth row partial display.

[0277] FIG. 12 is a working timing diagram of a driving module comprising at least one embodiment of the driving circuit shown in FIG. 9 of the present disclosure.

[0278] In FIG. 12, the label Fj is a j frame, and the label Fj+1 is a j+1 frame.

[0279] The j frame Fj and the j+1 frame Fj are partial display frames.

[0280] In the jth frame Fj and the j+1th frame Fj+1, the local scanning is started from the same row driving circuit, for example, the local scanning is started from the ninth row driving circuit; before the j+1th frame Fj+1, the global refresh frame does not need to be set, and the reset control signal is repeatedly input to repeatedly realize the local display function started from the ninth row driving circuit.

[0281] As shown in FIG. 12, when the driving module comprising at least one embodiment of the driving circuit shown in FIG. 9 of the present disclosure is working, the 5T1C unit (the 5T1C unit comprises M1-M5 and C1) can independently raise the potential of the first node of the corresponding row driving circuit, without the input signal from the previous driving circuit, so the driving circuit of the previous display row does not need to be turned on. When the local display starts from a certain row in the middle, the STV1A and the STV1B input invalid signals, and the local display mode of the continuous frame is performed, the CLK1-CLK8 are skipped at the beginning of each frame, and the input directly starts from CLK9.

[0282] If the opening time of each row is 1H, there are 2160 rows, the time for global scanning in one frame is 2160H, and the refresh rate is 1 / (2160H); the time required for scanning in one frame in the local scanning mode starting from the ninth row is (2160-8)H, and the refresh rate is 1 / (2152H). The fewer the number of rows displayed in the local scanning mode, the more obvious the refresh rate is provided, and the data voltage signal timing needs to be adjusted accordingly.

[0283] The difference between at least one embodiment of the driving circuit shown in FIG. 13 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 9 of the present disclosure is that:

[0284] The twenty-ninth transistor M29 and the thirtieth transistor M30 are not included.

[0285] The difference between at least one embodiment of the driving circuit shown in FIG. 14 of the present disclosure and at least one embodiment of the driving circuit shown in FIG. 9 of the present disclosure is that:

[0286] The first second node control circuit comprises a twenty-fifth transistor M25 and a twenty-sixth transistor M26.

[0287] The gate of the twenty-fifth transistor M25 and the drain of the twenty-fifth transistor M25 are electrically connected with a first control voltage terminal VDDO, and the source of the twenty-fifth transistor M25 is electrically connected with the first second node PD1.

[0288] The gate of the twenty-sixth transistor M26 is electrically connected with the first node PU, the drain of the twenty-sixth transistor M26 is electrically connected with the first second node PD1, and the source of the twenty-sixth transistor M26 is electrically connected with a first low voltage terminal LVSS.

[0289] The second second node control circuit comprises a twenty-seventh transistor M27 and a twenty-eighth transistor M28.

[0290] The gate of the twenty-seventh transistor M27 is electrically connected with the drain of the twenty-seventh transistor M27, and the source of the twenty-seventh transistor M27 is electrically connected with the second second node PD2.

[0291] The gate of the twenty-eighth transistor M28 is electrically connected with the first node PU, the drain of the twenty-eighth transistor M28 is electrically connected with the second second node PD2, and the source of the twenty-eighth transistor M28 is electrically connected with the first low-voltage terminal LVSS.

[0292] At least one embodiment of the driving circuit shown in FIG. 15A of the present disclosure is different from at least one embodiment of the driving circuit shown in FIG. 9 of the present disclosure in that:

[0293] The seventh transistor M7 is not included.

[0294] The twenty-ninth transistor M29 and the thirtieth transistor M30 are not included.

[0295] At least one embodiment of the driving circuit shown in FIG. 15B of the present disclosure is different from at least one embodiment of the driving circuit shown in FIG. 15A of the present disclosure in that:

[0296] The seventh transistor M7 is further included.

[0297] The gate of the seventh transistor M7 is electrically connected with the reset control terminal STV, the drain of the seventh transistor M7 is electrically connected with the first node PU, and the source of the seventh transistor M7 is electrically connected with the first low-voltage terminal LVSS.

[0298] In a specific implementation, when the driving circuit comprises the seventh transistor M7, the reset control signal can be used as a local display stop control signal to determine a display stop line.

[0299] The display device provided by the embodiment of the present disclosure comprises a driving module, and the driving module comprises a plurality of levels of the above-described driving circuit.

[0300] The input end of the driving circuit is electrically connected with the carry signal output end of the adjacent m-level driving circuit.

[0301] m is a positive integer.

[0302] In at least one embodiment of the present disclosure, the first row of driving circuits in the driving module, or the first several rows of driving circuits included in the driving module are connected with a frame start signal.

[0303] As shown in FIG. 16A, in at least one embodiment of the present disclosure, at least one embodiment of the driving module includes a first-stage driving circuit GA1, a second-stage driving circuit GA2, a third-stage driving circuit GA3, a fourth-stage driving circuit GA4, a fifth-stage driving circuit GA5, a sixth-stage driving circuit GA6, a seventh-stage driving circuit GA7, an eighth-stage driving circuit GA8, a ninth-stage driving circuit GA9, a tenth-stage driving circuit GA10, an eleventh-stage driving circuit GA11, and a twelfth-stage driving circuit GA12;

[0304] The GA1 is electrically connected with the first clock signal line CLK1, the GA2 is electrically connected with the second clock signal line CLK2, the GA3 is electrically connected with the third clock signal line CLK3, the GA4 is electrically connected with the fourth clock signal line CLK4, the GA5 is electrically connected with the fifth clock signal line CLK5, the GA6 is electrically connected with the sixth clock signal line CLK6, the GA7 is electrically connected with the seventh clock signal line CLK7, the GA8 is electrically connected with the eighth clock signal line CLK8, the GA9 is electrically connected with the ninth clock signal line CLK9, the GA10 is electrically connected with the tenth clock signal line CLK10, the GA11 is electrically connected with the eleventh clock signal line CLK11, and the GA12 is electrically connected with the twelfth clock signal line CLK12;

[0305] Each stage driving circuit is electrically connected with the VDDO, the VDDE, the LSP, the GRST, and the STV;

[0306] The input end of the GA1, the input end of the GA3, and the input end of the GA5 are connected with the first frame start signal STV1A, and the input end of the GA2, the input end of the GA4, and the input end of the GA6 are connected with the second frame start signal STV1B;

[0307] The carry signal output end of the GA1 is electrically connected with the input end of the GA7, the carry signal output end of the GA2 is electrically connected with the input end of the GA8, the carry signal output end of the GA3 is electrically connected with the input end of the GA9, the carry signal output end of the GA4 is electrically connected with the input end of the GA10, the carry signal output end of the GA5 is electrically connected with the input end of the GA11, and the carry signal output end of the GA6 is electrically connected with the input end of the GA12;

[0308] The carry output end of the GA9 is electrically connected with the pull-up reset end of the GA1, the carry output end of the GA10 is electrically connected with the pull-up reset end of the GA2, the carry output end of the GA11 is electrically connected with the pull-up reset end of the GA3, and the carry output end of the GA12 is electrically connected with the pull-up reset end of the GA4;

[0309] The pull-up reset end of the GA5 is electrically connected with the carry signal output end OC13 of the thirteenth row driving circuit, the pull-up reset end of the GA6 is electrically connected with the carry signal output end OC14 of the fourteenth row driving circuit, the pull-up reset end of the GA7 is electrically connected with the carry signal output end OC15 of the fifteenth row driving circuit, the pull-up reset end of the GA8 is electrically connected with the carry signal output end OC16 of the sixteenth row driving circuit, the pull-up reset end of the GA9 is electrically connected with the carry signal output end OC17 of the seventeenth row driving circuit, the pull-up reset end of the GA10 is electrically connected with the carry signal output end OC18 of the eighteenth row driving circuit, the pull-up reset end of the GA11 is electrically connected with the carry signal output end OC19 of the nineteenth row driving circuit, and the pull-up reset end of the GA12 is electrically connected with the carry signal output end OC20 of the twentieth row driving circuit.

[0310] The difference between at least one embodiment of the driving module shown in FIG. 16B and at least one embodiment of the driving module shown in FIG. 16A is that each row driving circuit is not electrically connected with the STV.

[0311] In a specific implementation, when the reset control signal provided by the STV is not required to be used as the local display stop control signal, each row driving circuit can not be electrically connected with the STV.

[0312] As shown in FIG. 17, at least one embodiment of the driving module according to at least one embodiment of the present disclosure can include eight row virtual driving circuits.

[0313] In FIG. 17, GAm-7 is the m-7th row driving circuit, GAm-6 is the m-6th row driving circuit, GAm-5 is the m-5th row driving circuit, GAm-4 is the m-4th row driving circuit, GAm-3 is the m-3rd row driving circuit, GAm-2 is the m-2nd row driving circuit, GAm-1 is the m-1st row driving circuit, and GAm is the mth row driving circuit; m is a positive integer.

[0314] GAm-7, GAm-6, GAm-5, GAm-4, GAm-3, GAm-2, GAm-1 and GAm are all virtual driving circuits.

[0315] GAm-7 is electrically connected with the first clock signal line CLK1, GAm-6 is electrically connected with the second clock signal line CLK2, GAm-5 is electrically connected with the third clock signal line CLK3, GAm-4 is electrically connected with the fourth clock signal line CLK4, GAm-3 is electrically connected with the fifth clock signal line CLK5, GAm-2 is electrically connected with the sixth clock signal line CLK6, GAm-1 is electrically connected with the seventh clock signal line CLK7, and GAm is electrically connected with the eighth clock signal line CLK8.

[0316] Each row driving circuit is electrically connected with VDDO, VDDE, LSP, GRST and STV;

[0317] The pull-up reset end of each row driving circuit is electrically connected with STV, and STV provides a pull-up reset signal for each virtual driving circuit;

[0318] OCm-7 is a carry signal output end of GAm-7, OCm-6 is a carry signal output end of GAm-6, OCm-5 is a carry signal output end of GAm-5, OCm-4 is a carry signal output end of GAm-4, OCm-3 is a carry signal output end of GAm-3, OCm-2 is a carry signal output end of GAm-2, OCm-1 is a carry signal output end of GAm-1, and OCm is a carry signal output end of GAm;

[0319] OCm-7, OCm-6, OCm-5, OCm-4, OCm-3, OCm-2, OCm-1 and OCm are respectively set on the upper level of each virtual driving circuit and reset the eight-level driving circuit of the virtual driving circuit.

[0320] The driving method provided in the embodiments of the present disclosure is applied to the display device described above; the display stage includes a (j-1)th frame and a jth frame, the (j-1)th frame is arranged before the jth frame and is adjacent to the jth frame; the (j-1)th frame is a global display frame, and the jth frame is a local display frame; j is a positive integer greater than 1; the driving method includes:

[0321] In the global display frame, each level driving circuit outputs a corresponding driving signal in turn; the global display frame is used to charge the control node of the driving circuit of the local display frame.

[0322] The driving method provided in at least one embodiment of the present disclosure further includes:

[0323] When the nth level driving circuit starts local display in the jth frame, in the nth level driving stage included in the global display frame, the nth level input end included in the nth level driving circuit in the display device is connected to the effective voltage signal, the node control circuit in the nth driving circuit controls the communication between the nth level input end and the nth level intermediate node, controls the communication between the nth level intermediate node and the nth level control node under the control of the potential of the nth level control node, and controls the communication or disconnection between the first voltage end and the nth level intermediate node under the control of the potential of the nth level control node; the first energy storage circuit in the nth driving circuit maintains the potential of the nth level first node;

[0324] In the n-th stage of the partial display frame, the first node charging circuit in the n-th drive circuit is controlled to connect the n-th first node and the first voltage terminal under the control of the potential of the n-th control node and the set control signal.

[0325] In at least one embodiment of the present disclosure, a global display frame is provided before the partial display frame, and the global display frame is adjacent to the partial display frame. When the n-th row of drive circuits starts to display in the partial display frame, the node control circuit controls the connection between the input terminal of the n-th row of drive circuits and the intermediate node, and controls the connection between the intermediate node and the control node under the control of the scan control signal provided by the scan control terminal, and charges the control node through the input signal provided by the input terminal. After the potential of the control node rises, the node control circuit controls the connection between the first voltage terminal and the intermediate node under the control of the potential of the control node, and the control node is further charged by the first voltage signal provided by the first voltage terminal, so as to raise the potential of the control node, and the first energy storage circuit maintains the potential of the control node. When the input terminal of the n-th row of drive circuits is connected to the invalid voltage signal, the scan control signal provided is switched to the invalid voltage signal, and the high potential of the control node is maintained by the first energy storage circuit. When the global display frame is switched to the partial display frame, when the set control terminal provides the valid set control signal, the first node charging circuit controls the connection between the first node and the first voltage terminal under the control of the potential of the control node and the set control signal provided by the set control terminal, and the first voltage signal provided by the first voltage terminal charges the first node in the n-th row of drive circuits. When the output clock signal connected by the n-th row of drive circuits is the valid voltage signal, the drive signal output circuit in the n-th row of drive circuits provides the valid n-th row of drive signals through the drive signal output terminal under the control of the potential of the first node, so as to normally cascade the subsequent drive circuit, and realize the partial display function starting from the n-th row of drive circuits.

[0326] In at least one embodiment of the present disclosure, the n-th drive circuit is cascaded with the n-k-th drive circuit, and the timing of the scan control terminal of the n-th drive circuit is the same as the timing of the output clock signal connected by the n-k-th drive circuit.

[0327] k is a positive integer.

[0328] In at least one embodiment of the present disclosure, the drive circuit further comprises a reset circuit; and the drive method further comprises:

[0329] In the a-th stage of driving included in the partial display frame, a reset circuit in the a-th driving circuit in the display device controls the communication between the a-th first node and the second voltage terminal under the control of a reset control signal;

[0330] a is a positive integer, and a is greater than n.

[0331] In the a-th driving circuit, when the reset control signal is a valid voltage signal, the reset circuit controls the communication between the first node and the second voltage terminal V2 under the control of the reset control signal provided at the reset control terminal, so as to reset the potential of the first node, so that the a-th driving circuit outputs an invalid driving signal, and the corresponding row driving circuit is closed, so that it can be determined which row the display stops at. The reset control signal is used as a partial display stop control signal.

[0332] In at least one embodiment of the present disclosure, the display stage further includes a j+1 frame, which is arranged after the j-th frame and is adjacent to the j-th frame; the j+1 frame is a partial display frame.

[0333] The driving method comprises:

[0334] In the n-th stage of driving included in the j+1 frame, an effective set control signal is provided at the set control terminal, and a first node charging circuit in the n-th driving circuit controls the communication between the n-th first node and the first voltage terminal under the control of the potential at the n-th control node and the set control signal; n is a positive integer.

[0335] In the specific implementation, when the j-th frame and the j+1 frame that is adjacent to the j-th frame are still partial display frames starting from the n-th row, a global display frame is not needed, and the set control signal can be repeatedly input to repeatedly implement the partial display function starting from the n-th row.

[0336] The above is the preferred embodiment of the present disclosure. It should be noted that for those skilled in the art, without departing from the principles of the present disclosure, a number of improvements and refinements can be made, which should also be considered as the protection scope of the present disclosure.

Claims

1. A driving circuit, comprising a node control circuit, a first node charging circuit, a first energy storage circuit, and an input circuit; The node control circuit is electrically connected to the scan control terminal, the input terminal, the intermediate node, the first voltage terminal, and the control node, respectively. It is used to control the connection or disconnection between the input terminal and the intermediate node under the control of the scan control signal provided by the scan control terminal, control the connection or disconnection between the intermediate node and the control node, and control the connection or disconnection between the first voltage terminal and the intermediate node under the control of the potential of the control node. The first node charging circuit is electrically connected to the control node, the set control terminal, the first node, and the first voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the first voltage terminal under the control of the potential of the control node and the set control signal provided by the set control terminal. The first energy storage circuit is electrically connected to the control node and is used to maintain the potential of the control node; The input circuit is electrically connected to the input terminal and the first node respectively, and is used to control the potential of the first node under the control of the input signal provided by the input terminal.

2. The driving circuit as described in claim 1, wherein, It also includes a reset circuit; The reset circuit is electrically connected to the reset control terminal, the first node, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the first node and the second voltage terminal under the control of the reset control signal provided by the reset control terminal.

3. The driving circuit as described in claim 1, wherein, The node control circuit includes a first transistor, a second transistor, and a third transistor; The gate of the first transistor is electrically connected to the scan control terminal, the first electrode of the first transistor is electrically connected to the input terminal, and the second electrode of the first transistor is electrically connected to the intermediate node. The gate of the second transistor is electrically connected to the scan control terminal, the first terminal of the second transistor is electrically connected to the intermediate node, and the second terminal of the second transistor is electrically connected to the control node. The gate of the third transistor is electrically connected to the control node, the first terminal of the third transistor is electrically connected to the first voltage terminal, and the second terminal of the third transistor is electrically connected to the intermediate node.

4. The driving circuit as described in claim 1, wherein, The first node charging circuit includes a fourth transistor and a fifth transistor, and the first energy storage circuit includes a first capacitor; The gate of the fourth transistor is electrically connected to the control node, the first terminal of the fourth transistor is electrically connected to the first voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor. The gate of the fifth transistor is electrically connected to the set control terminal, and the second terminal of the fifth transistor is electrically connected to the first node; The first terminal of the first capacitor is electrically connected to the control node, and the second terminal of the first capacitor is electrically connected to the DC voltage terminal.

5. The driving circuit as described in claim 1, wherein, The input circuit includes a sixth transistor; The gate of the sixth transistor is electrically connected to the first terminal of the sixth transistor and the input terminal, and the second terminal of the sixth transistor is electrically connected to the first node.

6. The driving circuit as described in claim 2, wherein, The reset circuit includes a seventh transistor; The gate of the seventh transistor is electrically connected to the reset control terminal, the first terminal of the seventh transistor is electrically connected to the first node, and the second terminal of the seventh transistor is electrically connected to the second voltage terminal.

7. The driving circuit as described in claim 1, wherein, It also includes a first node reset circuit and a pull-up node control circuit; The first node reset circuit is electrically connected to the pull-up reset terminal, the first node and the second voltage terminal respectively, and is used to control the connection or disconnection between the first node and the second voltage terminal under the control of the pull-up reset signal provided by the pull-up reset terminal; The pull-up node control circuit is electrically connected to the first second node, the second second node, the first node, and the second voltage terminal, respectively, and is used to control the first node to be connected or disconnected from the second voltage terminal under the control of the potential of the first second node, and to control the first node to be connected or disconnected from the second voltage terminal under the control of the potential of the second second node.

8. The driving circuit as described in claim 1, wherein, It also includes a carry signal output circuit and a drive signal output circuit; The carry signal output circuit is electrically connected to the first node, the first second node, the second second node, the carry signal output terminal, the output clock signal terminal, and the second voltage terminal, respectively. It is used to control the connection or disconnection between the carry signal output terminal and the output clock signal terminal under the control of the potential of the first node, to control the connection or disconnection between the carry signal output terminal and the second voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the carry signal output terminal and the second voltage terminal under the control of the potential of the second second node. The drive signal output circuit is electrically connected to the first node, the first second node, the second second node, the drive signal output terminal, the output clock signal terminal, and the third voltage terminal, respectively. It is used to control the connection or disconnection between the drive signal output terminal and the output clock signal terminal under the control of the potential of the first node, to control the connection or disconnection between the drive signal output terminal and the third voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the drive signal output terminal and the third voltage terminal under the control of the potential of the second second node.

9. The driving circuit as described in claim 8, wherein, It also includes a second energy storage circuit; The first end of the second energy storage circuit is electrically connected to the first node, and the second end of the second energy storage circuit is electrically connected to the drive signal output terminal. The second energy storage circuit is used to store electrical energy.

10. The driving circuit as claimed in claim 1, wherein, It also includes the first second node control circuit and the second second node control circuit; The first second node control circuit is electrically connected to the first control voltage terminal, the first intermediate control node, the first node, the first second node, and the second voltage terminal, respectively, and is used to provide the first control voltage at the first control voltage terminal. Under control, the potential of the first intermediate control node is controlled, and under the control of the potential of the first node, the connection or disconnection between the first intermediate control node and the second voltage terminal is controlled. Under the control of the potential of the first intermediate control node, the connection or disconnection between the first control voltage terminal and the first second node is controlled. Under the control of the potential of the first node, the connection or disconnection between the first second node and the second voltage terminal is controlled. The second second node control circuit is electrically connected to the second control voltage terminal, the second intermediate control node, the first node, the second second node, and the second voltage terminal, respectively. It is used to control the potential of the second intermediate control node under the control of the second control voltage provided by the second control voltage terminal, control the connection or disconnection between the second intermediate control node and the second voltage terminal under the control of the potential of the first node, control the connection or disconnection between the second control voltage terminal and the second second node under the control of the potential of the second intermediate control node, and control the connection or disconnection between the second second node and the second voltage terminal under the control of the potential of the first node.

11. The driving circuit as claimed in claim 1, wherein, It also includes the first second node control circuit and the second second node control circuit; The first second node control circuit is electrically connected to the first control voltage terminal, the first node, the first second node, and the second voltage terminal, respectively, and is used to control the potential of the first second node under the control of the first control voltage provided by the first control voltage terminal, and to control the connection or disconnection between the first second node and the second voltage terminal under the control of the potential of the first node. The second second node control circuit is electrically connected to the second control voltage terminal, the first node, the second second node, and the second voltage terminal, respectively. It is used to control the potential of the second second node under the control of the second control voltage provided by the second control voltage terminal, and to control the connection or disconnection between the second second node and the second voltage terminal under the control of the potential of the first node.

12. The driving circuit as described in claim 10 or 11, wherein, It also includes a second node reset circuit; The second node reset circuit is electrically connected to the input terminal, the first second node, the second second node, and the second voltage terminal, respectively, and is used to control the connection or disconnection between the first second node and the second voltage terminal under the control of the input signal provided by the input terminal, and to control the connection or disconnection between the second second node and the second voltage terminal.

13. The driving circuit as described in claim 7, wherein, The first node reset circuit includes an eighth transistor, and the pull-up node control circuit includes a ninth transistor and a tenth transistor; The gate of the eighth transistor is electrically connected to the pull-up reset terminal, the first terminal of the eighth transistor is electrically connected to the first node, and the second terminal of the eighth transistor is electrically connected to the second voltage terminal. The gate of the ninth transistor is electrically connected to the first second node, the first terminal of the ninth transistor is electrically connected to the first node, and the second terminal of the ninth transistor is electrically connected to the second voltage terminal. The gate of the tenth transistor is electrically connected to the second node, the first terminal of the tenth transistor is electrically connected to the first node, and the second terminal of the tenth transistor is electrically connected to the second voltage terminal.

14. The driving circuit as described in claim 8, wherein, The carry signal output circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; The gate of the eleventh transistor is electrically connected to the first node, and the first electrode of the eleventh transistor is connected to the... The output clock signal terminal is electrically connected, and the second terminal of the eleventh transistor is electrically connected to the carry signal output terminal. The gate of the twelfth transistor is electrically connected to the first second node, the first terminal of the twelfth transistor is electrically connected to the carry signal output terminal, and the second terminal of the twelfth transistor is electrically connected to the second voltage terminal. The gate of the thirteenth transistor is electrically connected to the second second node, the first terminal of the thirteenth transistor is electrically connected to the carry signal output terminal, and the second terminal of the thirteenth transistor is electrically connected to the second voltage terminal. The drive signal output circuit includes a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor; The gate of the fourteenth transistor is electrically connected to the first node, the first terminal of the fourteenth transistor is electrically connected to the output clock signal terminal, and the second terminal of the fourteenth transistor is electrically connected to the drive signal output terminal. The gate of the fifteenth transistor is electrically connected to the first second node, the first terminal of the fifteenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the fifteenth transistor is electrically connected to the third voltage terminal. The gate of the sixteenth transistor is electrically connected to the second node, the first terminal of the sixteenth transistor is electrically connected to the drive signal output terminal, and the second terminal of the sixteenth transistor is electrically connected to the third voltage terminal.

15. The driving circuit as described in claim 9, wherein, The second energy storage circuit includes a second capacitor; The first end of the second capacitor is electrically connected to the first node, and the second end of the second capacitor is electrically connected to the drive signal output terminal.

16. The driving circuit as claimed in claim 10, wherein, The first second node control circuit includes the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, and the twentieth transistor; The gate and first terminal of the seventeenth transistor are electrically connected to the first control voltage terminal, and the second terminal of the seventeenth transistor is electrically connected to the first intermediate control node. The gate of the eighteenth transistor is electrically connected to the first node, the first terminal of the eighteenth transistor is electrically connected to the first intermediate control node, and the second terminal of the eighteenth transistor is electrically connected to the second voltage terminal. The gate of the nineteenth transistor is electrically connected to the first intermediate control node, the first terminal of the nineteenth transistor is electrically connected to the first control voltage terminal, and the second terminal of the nineteenth transistor is electrically connected to the first second node. The gate of the twentieth transistor is electrically connected to the first node, the first terminal of the twentieth transistor is electrically connected to the first second node, and the second terminal of the twentieth transistor is electrically connected to the second voltage terminal. The second node control circuit includes a 21st transistor, a 22nd transistor, a 23rd transistor, and a 24th transistor. The gate and first terminal of the 21st transistor are electrically connected to the second control voltage terminal, and the second terminal of the 21st transistor is electrically connected to the second intermediate control node. The gate of the 22nd transistor is electrically connected to the first node, the first terminal of the 22nd transistor is electrically connected to the second intermediate control node, and the second terminal of the 22nd transistor is electrically connected to the second voltage terminal. The gate of the 23rd transistor is electrically connected to the second intermediate control node, the first terminal of the 23rd transistor is electrically connected to the second control voltage terminal, and the second terminal of the 22nd transistor is electrically connected to the second second node. The gate of the 24th transistor is electrically connected to the first node, the first terminal of the 24th transistor is electrically connected to the second node, and the second terminal of the 24th transistor is electrically connected to the second voltage terminal.

17. The driving circuit as claimed in claim 11, wherein, The first second node control circuit includes a twenty-fifth transistor and a twenty-sixth transistor; The gate and the first terminal of the 25th transistor are both electrically connected to the first control voltage terminal, and the second terminal of the 25th transistor is electrically connected to the first second node. The gate of the 26th transistor is electrically connected to the first node, the first terminal of the 26th transistor is electrically connected to the first second node, and the second terminal of the 26th transistor is electrically connected to the second voltage terminal. The second second node control circuit includes a twenty-seventh transistor and a twenty-eighth transistor; The gate and the first terminal of the 27th transistor are both electrically connected to the second control voltage terminal, and the second terminal of the 27th transistor is electrically connected to the second second node. The gate of the 28th transistor is electrically connected to the first node, the first terminal of the 28th transistor is electrically connected to the second node, and the second terminal of the 28th transistor is electrically connected to the second voltage terminal.

18. The driving circuit as claimed in claim 12, wherein, The second node reset circuit includes the twenty-ninth transistor and the thirtieth transistor; The gate of the 29th transistor is electrically connected to the input terminal, the first terminal of the 29th transistor is electrically connected to the first second node, and the second terminal of the 29th transistor is electrically connected to the second voltage terminal. The gate of the thirtieth transistor is electrically connected to the input terminal, the first terminal of the thirtieth transistor is electrically connected to the second second node, and the second terminal of the thirtieth transistor is electrically connected to the second voltage terminal.

19. A display device comprising a driving module, the driving module comprising multiple stages of driving circuits as described in any one of claims 1 to 18; The input terminal of the driving circuit is electrically connected to the carry signal output terminal of the adjacent upper m-level driving circuit. m is a positive integer.

20. A driving method applied to a display device as described in claim 19; the display stage includes a (j-1)th frame and a jth frame, the (j-1)th frame being disposed before and adjacent to the jth frame; the (j-1)th frame being a global display frame, and the jth frame being a local display frame; j being a positive integer greater than 1; the driving method comprising: In the global display frame, each level of the driving circuit outputs the corresponding driving signal in sequence; The global display frame is used to charge the control node of the driving circuit of the local display frame.

21. The driving method as described in claim 20, wherein, Also includes: When the nth-level driving circuit starts local display in frame j, during the nth-level driving stage included in the global display frame, an effective voltage signal is connected to the nth-level input terminal of the nth-level driving circuit in the display device. Under the control of the scanning control signal, the node control circuit in the nth-level driving circuit controls the connection between the nth-level input terminal and the nth-level intermediate node, and controls the connection between the nth-level intermediate node and the nth-level control node. Under the control of the potential of the nth-level control node, the first voltage terminal is controlled to connect or disconnect from the nth-level intermediate node. The first energy storage circuit in the nth-level driving circuit maintains the potential of the first node of the nth level. In the nth driving stage included in the partial display frame, the first node charging circuit in the nth driving circuit controls the connection between the nth first node and the first voltage terminal under the control of the potential and set control signal of the nth control node; n is a positive integer.

22. The driving method as described in claim 21, wherein, The nth stage driver circuit is cascaded with the nkth stage driver circuit. The timing of the scan control signal connected to the nth stage driver circuit is the same as the timing of the output clock signal connected to the nkth stage driver circuit. k is a positive integer.

23. The driving method as described in claim 22, wherein, The driving circuit further includes a reset circuit; the driving method further includes: During the a-level driving stage included in the partial display frame, the reset circuit in the a-level driving circuit of the display device controls the connection between the first node of the a-level and the second voltage terminal under the control of the reset control signal; a is a positive integer, and a is greater than n.

24. The driving method as described in claim 22, wherein, The display phase also includes a (j+1)th frame, which is set after the jth frame and adjacent to the jth frame; The (j+1)th frame is a partial display frame; The driving method includes: In the nth driving stage included in the j+1th frame, the set control terminal provides an effective set control signal. Under the control of the potential of the nth control node and the set control signal, the first node charging circuit in the nth driving circuit controls the connection between the nth first node and the first voltage terminal; n is a positive integer.

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