Inverter, pixel circuit, demultiplexer, driving assembly, and display chip

Abstract

The present application discloses an inverter, a pixel circuit, a demultiplexer, a driving assembly, and a display chip, and belongs to the technical field of display. The inverter comprises: a first substrate, and an input end, an output end, a first thin film transistor, and a second thin film transistor which are located on the first substrate. The orthographic projection of a channel of the first thin film transistor on the first substrate overlaps the orthographic projection of the second thin film transistor on the first substrate. That is, the two thin film transistors in the inverter are configured in an overlapping state, so that the space occupied by the two thin film transistors in the inverter can be reduced, thereby achieving the effect of reducing the size of the inverter.

Description

Inverter, pixel circuit, multiplexer, driving component and display chip TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an inverter, a pixel circuit, a multiplexer, a driving component and a display chip. BACKGROUND

[0002] An inverter is a kind of circuit element.

[0003] The current inverter includes a first substrate and two thin film transistors arranged on the first substrate in a direction parallel to the first substrate, the two thin film transistors are electrically connected and constitute an inverter circuit including an input terminal and an output terminal, and the inverter circuit can invert the phase of the input signal.

[0004] However, the above two thin film transistors occupy a large space, resulting in a large size of the inverter.

[0005] SUMMARY

[0006] The present application provides an inverter, a pixel circuit, a multiplexer, a driving component and a display chip. The technical solution is as follows:

[0007] According to an aspect of the present application, an inverter is provided, comprising: a first substrate and an input terminal, an output terminal, a first thin film transistor and a second thin film transistor located on the first substrate, the first thin film transistor is a P-type thin film transistor, and the second thin film transistor is an N-type thin film transistor.

[0008] The first thin film transistor includes a first source, a first drain and a first gate, the second thin film transistor includes a second source, a second drain and a second gate, the input terminal is electrically connected with the first gate and the second gate, and the output terminal is electrically connected with the first drain and the second drain.

[0009] The orthogonal projection of the channel of the first thin film transistor on the first substrate overlaps with the orthogonal projection of the channel of the second thin film transistor on the first substrate.

[0010] Optionally, the first thin film transistor is a low-temperature polysilicon thin film transistor, and the second thin film transistor is an oxide thin film transistor.

[0011] The second thin film transistor is located on the side of the first thin film transistor away from the first substrate, the first thin film transistor includes a first active layer, and the second thin film transistor includes a second active layer.

[0012] The first gate is located between the first active layer and the second active layer, the second gate comprises a first sub-gate and a second sub-gate, the first sub-gate is located on one side of the second active layer close to the first substrate, and the second sub-gate is located on one side of the second active layer away from the first substrate, or,

[0013] The first gate is located between the first active layer and the second active layer, and the second gate is located on one side of the second active layer away from the first substrate, or,

[0014] The first gate is located between the first active layer and the second active layer, and the second gate is located on one side of the second active layer away from the first substrate, or,

[0015] The first gate is located between the first active layer and the second active layer, and the second gate is located between the first gate and the second active layer, or,

[0016] The first gate comprises a third sub-gate located between the first active layer and the second active layer and a fourth sub-gate located between the first active layer and the first substrate.

[0017] Optionally, the first thin film transistor further comprises a first active layer, and the second thin film transistor comprises a second active layer;

[0018] The first source electrode and the first drain electrode are located on one side of the first active layer, and the second source electrode and the second drain electrode are located on one side of the second active layer.

[0019] The first source electrode and the first drain electrode are located on one side of the first active layer, and the second source electrode and the second drain electrode are located on one side of the second active layer.

[0020] The first direction of the first thin film transistor is parallel to the second direction of the second thin film transistor, the first direction is the connecting direction of the first source electrode and the first drain electrode, and the second direction is the connecting direction of the second source electrode and the second drain electrode.

[0021] Optionally, the first thin film transistor further comprises a first active layer, and the second thin film transistor comprises a second active layer;

[0022] The first source electrode has an orthogonal projection on the first substrate that overlaps with an orthogonal projection of the first active layer on the first substrate, and the first drain electrode has an orthogonal projection on the first substrate that overlaps with an orthogonal projection of the first active layer on the first substrate;

[0023] The second source electrode has an orthogonal projection on the first substrate that overlaps with an orthogonal projection of the second active layer on the first substrate, and the second drain electrode has an orthogonal projection on the first substrate that overlaps with an orthogonal projection of the second active layer on the first substrate;

[0024] The first direction of the first thin film transistor is perpendicular to the second direction of the second thin film transistor, the first direction is a connection direction of the first source electrode and the first drain electrode, and the second direction is a connection direction of the second source electrode and the second drain electrode.

[0025] Optionally, the inverter further comprises a first gate insulating layer, a second gate insulating layer, a first interlayer dielectric layer, a buffer layer, a third gate insulating layer, and a second interlayer dielectric layer.

[0026] The second gate electrode comprises a first sub-gate electrode and a second sub-gate electrode.

[0027] The first active layer, the first gate insulating layer, the first gate electrode, the second gate insulating layer, the first sub-gate electrode, the first interlayer dielectric layer, the buffer layer, the second active layer, the third gate insulating layer, the second sub-gate electrode, and the second interlayer dielectric layer are arranged on the first substrate in a direction away from the first substrate.

[0028] The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are located on the first substrate provided with the second interlayer dielectric layer, the first gate insulating layer, the second gate insulating layer, the first interlayer dielectric layer, the buffer layer, the third gate insulating layer, and the second interlayer dielectric layer have a first source electrode via hole and a first drain electrode via hole, the first source electrode is electrically connected to the first active layer through the first source electrode via hole, and the first drain electrode is electrically connected to the first active layer through the first drain electrode via hole.

[0029] The third gate insulating layer and the second interlayer dielectric layer have a second source electrode via hole and a second drain electrode via hole, the second source electrode is electrically connected to the second active layer through the second source electrode via hole, and the second drain electrode is electrically connected to the second active layer through the second drain electrode via hole.

[0030] Optionally, the inverter further comprises a first connection pattern, the first connection pattern comprises a first connection line, and the first connection line and the first source electrode are a same layer structure.

[0031] The first connection line is electrically connected with the first drain and the second drain, respectively.

[0032] Optionally, the first thin film transistor comprises a first gate, the second thin film transistor comprises a second active layer, the first gate is located at a side of the second active layer close to the first substrate, and a normal projection of a channel in the second active layer on the first substrate is located in a normal projection of the first gate on the first substrate.

[0033] Optionally, the first thin film transistor further comprises a first gate, a size of the first gate in a width direction of a channel of the first thin film transistor is greater than a size of the first active layer in the width direction of the channel of the first thin film transistor, and a minimum distance between an edge of the first gate and an edge of the first active layer is greater than or equal to 2.5 microns.

[0034] Optionally, the inverter satisfies: Lp≥Ln.

[0035] The Lp is a length of a channel of the first thin film transistor, and the Ln is a length of a channel of the second thin film transistor.

[0036] According to another aspect of the embodiments of the present application, a pixel circuit is provided, comprising a pulse amplitude modulation module and a pulse width modulation module, the pulse amplitude modulation module is electrically connected with the pulse width modulation module.

[0037] The pulse width modulation module comprises the above-mentioned inverter.

[0038] Optionally, the pulse amplitude modulation module comprises a line connection end.

[0039] The pulse width modulation module comprises a first transmission gate, a second transmission gate, a first inverter and a second inverter.

[0040] The output ends of the first transmission gate and the second transmission gate are electrically connected with the line connection end, the input end of the first transmission gate is coupled with a first light-emitting control signal end, the input end of the second transmission gate is coupled with a second light-emitting control signal end, the control end of the first transmission gate is electrically connected with the input end of the first inverter and the output end of the second inverter, and the control end of the second transmission gate is electrically connected with the output end of the first inverter and the input end of the second inverter.

[0041] Optionally, the pulse amplitude modulation module comprises at least one third thin film transistor and at least one fourth thin film transistor, the third thin film transistor comprises a third gate, a third active layer, a third source and a third drain, and the fourth thin film transistor comprises a fourth gate, a fourth active layer, a fourth source and a fourth drain.

[0042] The third thin film transistor and the first thin film transistor in the inverter are low-temperature polysilicon thin film transistors, and the fourth thin film transistor and the second thin film transistor in the inverter are oxide thin film transistors.

[0043] The pulse amplitude modulation module and the pulse width modulation module satisfy at least one of the following conditions:

[0044] The third gate and the first gate in the first thin film transistor are in a same layer structure, the third active layer and the first active layer in the first thin film transistor are in a same layer structure, the third source and the first source in the first thin film transistor are in a same layer structure, and the third drain and the first drain in the first thin film transistor are in a same layer structure.

[0045] The fourth gate and the second gate in the second thin film transistor are in a same layer structure, the fourth active layer and the second active layer in the second thin film transistor are in a same layer structure, the fourth source and the second source in the second thin film transistor are in a same layer structure, and the fourth drain and the second drain in the second thin film transistor are in a same layer structure.

[0046] According to another aspect of the embodiments of the present application, a transmission gate is provided, which comprises a second substrate, a first port, a second port, a first control terminal and a second control terminal, a fifth thin film transistor and a sixth thin film transistor on the second substrate, the fifth thin film transistor comprising a fifth source, a fifth drain and a fifth gate, the sixth thin film transistor comprising a sixth source, a sixth drain and a sixth gate, the first port being electrically connected with the fifth source and the sixth source, the second port being electrically connected with the fifth drain and the sixth drain, the first control terminal being electrically connected with the fifth gate, and the second control terminal being electrically connected with the sixth gate.

[0047] The first connection terminal is electrically connected with the fifth source and the sixth source, and the second connection terminal is electrically connected with the fifth drain and the sixth drain.

[0048] The fifth thin film transistor and the sixth thin film transistor are in a same layer structure.

[0049] According to another aspect of the embodiments of the present application, a NAND gate is provided, which includes a third substrate, and six ports and three pairs of thin film transistors on the third substrate, one of the pairs of thin film transistors including an upper thin film transistor and a lower thin film transistor, a channel of the lower thin film transistor in orthographic projection onto the third substrate overlapping a channel of the upper thin film transistor in orthographic projection onto the third substrate;

[0050] The three pairs of thin film transistors include a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, an eleventh thin film transistor and a twelfth thin film transistor.

[0051] A first port of the six ports is electrically connected to a gate of the seventh thin film transistor and a gate of the eighth thin film transistor.

[0052] A second port of the six ports is electrically connected to a gate of the ninth thin film transistor and a gate of the tenth thin film transistor.

[0053] A third port of the six ports is electrically connected to a gate of the eleventh thin film transistor and a gate of the twelfth thin film transistor.

[0054] A fourth port of the six ports is electrically connected to a first electrode of the seventh thin film transistor, a first electrode of the ninth thin film transistor and a first electrode of the eleventh thin film transistor.

[0055] A fifth port of the six ports is electrically connected to a second electrode of the seventh thin film transistor, a second electrode of the ninth thin film transistor and a second electrode of the eleventh thin film transistor.

[0056] A second electrode of the eighth thin film transistor is electrically connected to the fifth port, a first electrode of the eighth thin film transistor is electrically connected to a second electrode of the tenth thin film transistor, a first electrode of the tenth thin film transistor is electrically connected to a second electrode of the twelfth thin film transistor, and a first electrode of the twelfth thin film transistor is electrically connected to a sixth port of the six ports.

[0057] Wherein, the first electrode is a source electrode, and the second electrode is a drain electrode.

[0058] According to another aspect of the embodiments of the present application, a multiplexer is provided, which includes at least one inverter and at least one NAND gate, the inverter including the above-mentioned inverter, and / or the NAND gate including the above-mentioned NAND gate.

[0059] According to another aspect of the embodiments of the present application, a driving assembly is provided, the driving assembly comprises a pixel circuit, a transfer gate and a multiplexer, the pixel circuit is electrically connected with the multiplexer and the transfer gate, the transfer gate is electrically connected with the multiplexer, and the driving assembly satisfies at least one of the following conditions:

[0060] The pixel circuit comprises the pixel circuit described above.

[0061] The multiplexer comprises the multiplexer described above.

[0062] The transfer gate comprises the transfer gate described above.

[0063] According to another aspect of the embodiments of the present application, a display chip is provided, the display chip comprises:

[0064] A light emitting unit, the light emitting unit comprises a first electrode, a second electrode and a light emitting part electrically connected with the first electrode and the second electrode respectively.

[0065] A driving unit, the driving unit comprises a first driving circuit layer and a second driving circuit layer arranged in a stack, the first driving circuit layer is located between the light emitting unit and the second driving circuit layer, the first driving circuit layer comprises a third electrode and a fourth electrode, the third electrode and the fourth electrode are both located on a side of the first driving circuit layer facing the light emitting unit, the third electrode is electrically connected with the first electrode, and the fourth electrode is electrically connected with the second electrode.

[0066] The first driving circuit layer comprises at least one first thin film transistor, the second driving circuit layer comprises at least one second thin film transistor, the first thin film transistor and the second thin film transistor constitute an inverter, and the inverter comprises the inverter described above.

[0067] The technical scheme provided by the embodiments of the present application has at least the following beneficial effects:

[0068] An inverter comprising a first thin film transistor and a second thin film transistor is provided, the channel of the first thin film transistor overlaps the orthographic projection of the second thin film transistor on a first substrate, that is, the two thin film transistors in the inverter are in an overlapping state, so that the space occupied by the two thin film transistors in the inverter can be reduced, and the size of the inverter can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0069] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0070] FIG. 1 is a structural schematic diagram of an inverter in the related art;

[0071] FIG. 2 is a structural schematic diagram of an inverter provided by an embodiment of the present application;

[0072] FIG. 3 is a sectional structural schematic diagram of the inverter shown in FIG. 2;

[0073] FIG. 4 is a circuit schematic diagram of the inverter shown in FIG. 3;

[0074] FIG. 5 is a partial structural schematic diagram of a first thin film transistor in the inverter shown in FIG. 2;

[0075] FIG. 6 is a partial structural schematic diagram of a second thin film transistor in the inverter shown in FIG. 2;

[0076] FIG. 7 is a structural schematic diagram of a transmission gate provided by an embodiment of the present application;

[0077] FIG. 8 is a sectional structural schematic diagram of the transmission gate shown in FIG. 7;

[0078] FIG. 9 is a circuit schematic diagram of the transmission gate shown in FIG. 7;

[0079] FIG. 10 is a structural schematic diagram of an NAND gate provided by an embodiment of the present application;

[0080] FIG. 11 is a sectional structural schematic diagram of the NAND gate shown in FIG. 10;

[0081] FIG. 12 is a circuit schematic diagram of the NAND gate shown in FIG. 10;

[0082] FIG. 13 is a voltage transfer characteristic curve of the inverter provided by an embodiment of the present application;

[0083] FIG. 14 is a structural schematic diagram of two thin film transistors overlapping each other provided by an embodiment of the present application;

[0084] FIG. 15 is a partial structural schematic diagram of a first thin film transistor in FIG. 14;

[0085] FIG. 16 is a partial structural schematic diagram of a second thin film transistor in FIG. 14;

[0086] FIG. 17 is a sectional structural schematic diagram of the structure shown in FIG. 14;

[0087] FIG. 18 is another cross-sectional view of the overlapped thin film transistor according to an embodiment of the present application;

[0088] FIG. 19 is another cross-sectional view of the overlapped thin film transistor according to an embodiment of the present application;

[0089] FIG. 20 is another cross-sectional view of the overlapped thin film transistor according to an embodiment of the present application;

[0090] FIG. 21 is another cross-sectional view of the overlapped thin film transistor according to an embodiment of the present application;

[0091] FIG. 22 is a circuit diagram of a pixel circuit according to an embodiment of the present application;

[0092] FIG. 23 is a cross-sectional view of a pulse amplitude modulation module according to an embodiment of the present application;

[0093] FIG. 24 is a structural diagram of a demultiplexer according to an embodiment of the present application;

[0094] FIG. 25 is a diagram of a first active layer pattern and a first gate pattern in the demultiplexer according to an embodiment of the present application;

[0095] FIG. 26 is a diagram of a second gate pattern and a first interlayer dielectric layer in the demultiplexer according to an embodiment of the present application;

[0096] FIG. 27 is a diagram of an oxide active layer pattern and a second interlayer dielectric layer in the demultiplexer according to an embodiment of the present application;

[0097] FIG. 28 is a diagram of a third gate pattern and a source-drain pattern in the demultiplexer according to an embodiment of the present application;

[0098] FIG. 29 is a diagram of a stack of partial film layers in the demultiplexer according to an embodiment of the present application;

[0099] FIG. 30 is a structural diagram of a driving component according to an embodiment of the present application;

[0100] FIG. 31 is a structural diagram of a display chip according to an embodiment of the present application;

[0101] FIG. 32 is a structural diagram of a display substrate according to an embodiment of the present application;

[0102] FIG. 33 is a structural diagram of a flip-flop according to an embodiment of the present application;

[0103] FIG. 34 is a circuit diagram of a clock signal rising edge detector in the flip-flop according to an embodiment of the present application;

[0104] FIG. 35 is a circuit diagram of a clock signal falling edge detector in the flip-flop shown in FIG. 33;

[0105] FIG. 36 is a circuit diagram of a frame start signal generation latch in the flip-flop shown in FIG. 33;

[0106] FIG. 37 is a circuit diagram of an RS flip-flop in the flip-flop shown in FIG. 33.

[0107] The specific embodiments of the present application have been shown and described in the above-mentioned drawings, and will be described in more detail hereinafter. These drawings and written descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0108] In order to make the purposes, technical solutions and advantages of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the drawings.

[0109] FIG. 1 is a structural schematic diagram of an inverter in the related art, which includes a first substrate 11 and a first thin film transistor (TFT) 12 and a second TFT 13 located on the first substrate 11, the first TFT 12 and the second TFT 13 being arranged along a direction 1f parallel to the first substrate 11 on the first substrate 11.

[0110] Among them, the first TFT 11 can be a low temperature poly-silicon (LTPS) TFT, and the second TFT 12 can be an oxide TFT. Thus, FIG. 1 is an inverter applying a low temperature polycrystalline oxide (LTPO) technology.

[0111] However, the two TFTs in the above-mentioned inverter occupy a large space, resulting in a large size of the inverter.

[0112] The embodiments of the present application provide an inverter, a pixel circuit, a multiplexer, a driving assembly and a display chip, which can solve some problems existing in the above-mentioned related art.

[0113] Fig. 2 is a structural schematic diagram of an inverter provided in an embodiment of the present application, and Fig. 3 is a sectional structural schematic diagram of the inverter shown in Fig. 2 (the sectional position is at A-A). Referring to Figs. 2 and 3, the inverter comprises a first substrate 21, an input terminal s1, an output terminal s2, a first thin film transistor 22 and a second thin film transistor 23 located on the first substrate 21. The first thin film transistor 22 is a P-type thin film transistor, and the second thin film transistor 23 is an N-type thin film transistor.

[0114] The first thin film transistor 22 comprises a first source electrode 221, a first drain electrode 222 and a first gate electrode 223, and the second thin film transistor 23 comprises a second source electrode 231, a second drain electrode 232 and a second gate electrode 233.

[0115] The orthogonal projection of a channel q1 of the first thin film transistor 22 on the first substrate 21 overlaps with the orthogonal projection of a channel q2 of the second thin film transistor 23 on the first substrate 21.

[0116] Referring to Fig. 4, Fig. 4 is a circuit schematic diagram of the inverter shown in Fig. 3. The input terminal s1 is electrically connected with the first gate electrode 223 and the second gate electrode 233, and the output terminal s2 is electrically connected with the first drain electrode 222 and the second drain electrode 232.

[0117] The first thin film transistor 22 further comprises a first active layer 224, and the second thin film transistor 23 further comprises a second active layer 234. The channel q1 of the first thin film transistor 22 is a partial region in the first active layer 224, and the channel q2 of the second thin film transistor 23 is a partial region in the second active layer 234.

[0118] In addition, the first source electrode 221 of the first thin film transistor 22 is electrically connected with a driving power supply terminal VDD, and the second source electrode 231 of the second thin film transistor 23 is electrically connected with a common ground terminal VSS.

[0119] In summary, the present application provides an inverter comprising a first thin film transistor and a second thin film transistor. The orthogonal projection of a channel of the first thin film transistor on a first substrate overlaps with the orthogonal projection of a channel of the second thin film transistor on the first substrate, i.e., the two thin film transistors in the inverter are in an overlapping state. In this way, the space occupied by the two thin film transistors in the inverter can be reduced, and the size of the inverter can be reduced.

[0120] The channel of a certain thin film transistor involved in the embodiments of the present application refers to a conductive region formed in the active layer of the thin film transistor under the action of a gate electrode. Specifically, the channel can be a region of the active layer that overlaps the gate electrode. For example, referring to FIG. 5, which is a schematic diagram of a partial structure of a first thin film transistor in the inverter shown in FIG. 2 (in order to show the channel q1, the first gate electrode is not filled, but this is not a limitation), the channel q1 is a region of the first active layer 224 that overlaps the first gate electrode 223, and this region can have a conductive ability under the action of an electric field applied by the first gate electrode 223. In addition, the region of the first active layer 224 other than the channel q1 can be a conductive region, and the active layer of the conductive region is a conductor. The conductive region can be a region of the active layer that has a dopant that can improve conductivity.

[0121] In addition, the channel q1 has a length L1 and a width W1. The length L1 can refer to the size of the channel q1 in the current transmission direction (which can be parallel to the connection direction f1 of the source electrode and the drain electrode), and the width W1 is the size of the channel q1 in the direction f2 perpendicular to the current transmission direction (which is perpendicular to the connection direction f1).

[0122] In addition, referring to FIG. 6, which is a schematic diagram of a partial structure of a second thin film transistor in the inverter shown in FIG. 2, the channel q2 is a region of the second active layer 234 that overlaps the second gate electrode 233, and this region can have a conductive ability under the action of an electric field applied by the second gate electrode 233.

[0123] FIG. 7 is a schematic diagram of a structure of a transmission gate provided in the embodiments of the present application, FIG. 8 is a schematic diagram of a cross-sectional structure of the transmission gate shown in FIG. 7 (the cross-sectional position is at B-B), and FIG. 9 is a schematic diagram of a circuit of the transmission gate shown in FIG. 7. For reference, FIGS. 7, 8, and 9 are provided.

[0124] The transmission gate includes a second substrate 31, a first connection end d1, a second connection end d2, a first control end k1, and a second control end k2, a fifth thin film transistor 32, and a sixth thin film transistor 33 on the second substrate 31. The fifth thin film transistor 32 includes a fifth source electrode 321, a fifth drain electrode 322, and a fifth gate electrode 323. The sixth thin film transistor 33 includes a sixth source electrode 331, a sixth drain electrode 332, and a sixth gate electrode 333. The first connection end d1 is electrically connected to the fifth source electrode 321 and the sixth source electrode 331. The second connection end d2 is electrically connected to the fifth drain electrode 322 and the sixth drain electrode 332. The first control end k1 is electrically connected to the fifth gate electrode 323. The second control end k2 is electrically connected to the sixth gate electrode 333.

[0125] The first connection end d1 is electrically connected with the fifth source electrode 321 and the sixth source electrode 331, and the second connection end d2 is electrically connected with the fifth drain electrode 322 and the sixth drain electrode 332.

[0126] The orthogonal projection of the channel q3 of the fifth thin film transistor 32 on the second substrate 31 overlaps with the orthogonal projection of the channel q4 of the sixth thin film transistor 33 on the second substrate 31.

[0127] The fifth thin film transistor 32 further includes a fifth active layer 324, and the sixth thin film transistor 33 further includes a sixth active layer 334. The channel q3 of the fifth thin film transistor 32 is located on the fifth active layer 324, and the channel q4 of the sixth thin film transistor 33 is located on the sixth active layer 334. For details of the channel, refer to the above description of FIGS. 2 to 6 and the corresponding embodiments, which will not be repeated here.

[0128] The transmission gate is a controllable switch circuit that can transmit signals, and can be applied to a driving circuit of a display device.

[0129] In summary, the embodiment of the present application provides a transmission gate including a fifth thin film transistor and a sixth thin film transistor. The orthogonal projection of the channel of the fifth thin film transistor on the second substrate overlaps with the orthogonal projection of the channel of the sixth thin film transistor on the second substrate, that is, the two thin film transistors in the transmission gate are in an overlapping state. In this way, the space occupied by the two thin film transistors in the transmission gate can be reduced, and the size of the transmission gate can be reduced.

[0130] FIG. 10 is a structural schematic diagram of an AND gate according to an embodiment of the present application, FIG. 11 is a sectional structural schematic diagram of the AND gate shown in FIG. 10 (the section position is C-C), and FIG. 12 is a circuit schematic diagram of the AND gate shown in FIG. 10. The AND gate includes a third substrate 41 and six ports and three thin film transistor pairs on the third substrate 41. One thin film transistor pair includes an upper thin film transistor and a lower thin film transistor. The orthogonal projection of the channel of the lower thin film transistor on the third substrate 41 overlaps with the orthogonal projection of the channel of the upper thin film transistor on the third substrate 41.

[0131] The three thin film transistor pairs include a seventh thin film transistor 42, an eighth thin film transistor 43, a ninth thin film transistor 44, a tenth thin film transistor 45, an eleventh thin film transistor 46, and a twelfth thin film transistor 47.

[0132] Please refer to FIG. 10 and FIG. 11, wherein the seventh thin film transistor 42 is a lower thin film transistor, the eighth thin film transistor 43 is an upper thin film transistor, and the orthogonal projection of the channel q5 of the seventh thin film transistor 42 on the third substrate 41 overlaps with the orthogonal projection of the channel q6 of the eighth thin film transistor 43 on the third substrate 41.

[0133] Please refer to FIG. 12, the first port a1 of the six ports is electrically connected with the gate 423 of the seventh thin film transistor 42 and the gate 433 of the eighth thin film transistor 43.

[0134] The second port a2 of the six ports is electrically connected with the gate 443 of the ninth thin film transistor 44 and the gate 453 of the tenth thin film transistor 45.

[0135] The third port a3 of the six ports is electrically connected with the gate 463 of the eleventh thin film transistor 46 and the gate 473 of the twelfth thin film transistor 47.

[0136] The fourth port a4 of the six ports is electrically connected with the first electrode 421 of the seventh thin film transistor 42, the first electrode 441 of the ninth thin film transistor 44 and the first electrode 461 of the eleventh thin film transistor 46.

[0137] The fifth port a5 of the six ports is electrically connected with the second electrode 422 of the seventh thin film transistor 42, the second electrode 442 of the ninth thin film transistor 44 and the second electrode 462 of the eleventh thin film transistor 46.

[0138] The second electrode 432 of the eighth thin film transistor 43 is electrically connected with the fifth port a5, the first electrode 431 of the eighth thin film transistor 43 is electrically connected with the second electrode 452 of the tenth thin film transistor 45, the first electrode 451 of the tenth thin film transistor 45 is electrically connected with the second electrode 472 of the twelfth thin film transistor 47, and the first electrode 471 of the twelfth thin film transistor 47 is electrically connected with the sixth port a6 of the six ports.

[0139] Among the above-mentioned seventh thin film transistor 42 to twelfth thin film transistor 47, the first electrode is the source electrode, and the second electrode is the drain electrode.

[0140] Among the above-mentioned seventh thin film transistor 42 to twelfth thin film transistor 47, the first electrode is the source electrode, and the second electrode is the drain electrode.

[0141] In summary, the embodiment of the present application provides an NAND gate, comprising three thin film transistor pairs, one thin film transistor pair comprising one upper thin film transistor and one lower thin film transistor, the channel of the lower thin film transistor on the third substrate has an overlapping projection with the channel of the upper thin film transistor on the third substrate, that is, the two thin film transistors in the NAND gate are in an overlapping state, so as to reduce the space occupied by the two thin film transistors in the NAND gate, thereby realizing the effect of reducing the size of the NAND gate.

[0142] The above embodiment provides an inverter, a transmission gate and an NAND gate, and the common point of these structures is that they all comprise two channel-overlapping thin film transistors, so as to realize the effect of reducing the size of the overall structure. The first thin film transistor and the second thin film transistor are taken as an example to describe the two channel-overlapping thin film transistors, and the thin film transistors in the transmission gate and the NAND gate can refer to the structure of the first thin film transistor and the second thin film transistor.

[0143] Please refer to FIG. 2 and FIG. 3, wherein the first thin film transistor 22 is a low-temperature polysilicon thin film transistor, and the second thin film transistor 23 is an oxide thin film transistor.

[0144] The second thin film transistor 23 is located on the side of the first thin film transistor 22 away from the first substrate 21, the first thin film transistor 22 comprises a first active layer 224, and the second thin film transistor 23 comprises a second active layer 234.

[0145] The first gate 223 is located between the first active layer 224 and the second active layer 234, the second gate 233 comprises a first sub-gate 2331 and a second sub-gate 2332, the first sub-gate 2331 is located on the side of the second active layer 234 close to the first substrate 21, and the second sub-gate 2332 is located on the side of the second active layer 234 away from the first substrate 21.

[0146] In this structure, it is a kind of low-temperature polysilicon thin film transistor under, oxide thin film transistor in the upper layer structure, and the oxide thin film transistor is double-gate oxide thin film transistor, compared with single-gate oxide thin film transistor, the stability of double-gate oxide thin film transistor is stronger, so as to reduce the interference between the two overlapping thin film transistors.

[0147] In addition, the above first thin film transistor 22 and second thin film transistor 23 satisfy: (i1-i2)*10≤i2;

[0148] i1 is the on current of the thin film transistor with smaller on current value between the first thin film transistor 22 and the second thin film transistor 23, and i2 is the on current of the thin film transistor with larger on current value between the first thin film transistor 22 and the second thin film transistor 23. In this way, the on current of the first thin film transistor 22 and the on current of the second thin film transistor 23 are closer, the difference between the first thin film transistor 22 and the second thin film transistor 23 is reduced, and the interference between the first thin film transistor 22 and the second thin film transistor 23 is reduced, so that the performance of the device using the overlapping thin film transistors provided in the embodiment of the present application is improved. Based on this principle, the on current of the first thin film transistor 22 and the on current of the second thin film transistor 23 can be equal.

[0149] Please refer to FIG. 13, which is a schematic diagram of voltage transfer characteristic curve of an inverter provided in the embodiment of the present application, wherein the horizontal axis is input voltage, and the vertical axis is output voltage, both in units of volts (V). When the on current of the low-temperature polysilicon thin film transistor is equal to the on current of the oxide thin film transistor (i.e., the driving capability of the low-temperature polysilicon thin film transistor is equal to the driving capability of the oxide thin film transistor), the voltage transfer characteristic (VTC) curve is curve j1. When the on current of the low-temperature polysilicon thin film transistor is greater than the on current of the oxide thin film transistor, the VTC curve is shifted to the right to become curve j2. When the on current of the low-temperature polysilicon thin film transistor is less than the on current of the oxide thin film transistor, the VTC curve is shifted to the left to become curve j3. Both curve j2 and curve j3 will cause the inverter or the electronic device using this structure to operate normally.

[0150] Please refer to FIG. 5 and FIG. 6, the active layer material of the low-temperature polysilicon thin film transistor includes low-temperature polysilicon, and the active layer material of the oxide thin film transistor includes oxide (such as indium gallium zinc oxide (IGZO)), but the carrier concentration in the active layer composed of low-temperature polysilicon is usually greater than the carrier concentration in the active layer composed of oxide. In order to reduce the performance difference between the low-temperature polysilicon thin film transistor and the oxide thin film transistor, L1≥L2 can be achieved.

[0151] L1 is the length of the channel of the first thin film transistor 22, and L2 is the length of the channel of the second thin film transistor 23.

[0152] Further, the first thin film transistor 22 and the second thin film transistor 23 can satisfy: W1*a / L1=W2*b / L2;

[0153] W1 is the width of the channel of the first thin film transistor 22, L1 is the length of the channel of the first thin film transistor 22, a is the carrier concentration in the active layer of the first thin film transistor 22; W2 is the width of the channel of the second thin film transistor 23, L2 is the length of the channel of the second thin film transistor 23, b is the carrier concentration in the active layer of the second thin film transistor 23. In a specific example, the ratio of the width to the length of the channel of the first thin film transistor 22 is 3 / 10, and the ratio of the width to the length of the channel of the second thin film transistor 23 is 8 / 4.

[0154] In addition, when the first thin film transistor 22 and the second thin film transistor 23 are applied to an inverter, the following conditions can also be met:

[0155] The threshold voltage of the first thin film transistor 22 is less than 0 volts, the threshold voltage of the second thin film transistor 23 is greater than 0 volts, and the 0-volt current of the second thin film transistor 23 is greater than 10e-12 amperes. In this way, the first thin film transistor 22 and the second thin film transistor 23 can realize the function of an inverter.

[0156] The size of the first gate 223 of the first thin film transistor 22 in the width direction f2 of the channel of the first thin film transistor 22 is greater than the size of the first active layer 224 in the width direction f2 of the channel of the first thin film transistor 22, and the minimum distance c between the edge of the first gate 223 and the edge of the first active layer 224 is greater than or equal to 2.5 microns. In this way, on the one hand, it can be ensured that the first gate 223 can cover the first active layer 224, and on the other hand, it can avoid the edge of the first gate 223 being too close to the edge of the first active layer 224 to affect the performance of the channel in the first active layer 224.

[0157] The first thin film transistor and the second thin film transistor provided by the embodiments of the present application can have various overlapping modes, which will be described below:

[0158] An overlapping structure please refer to FIG. 3, FIG. 5 and FIG. 6, the first source 221 on the first substrate 21 with the first active layer 224 on the first substrate 21 on the projection exists overlap, the first drain 222 on the first substrate 21 with the first active layer 224 on the first substrate on the projection exists overlap.

[0159] The second source 231 on the first substrate 21 with the second active layer 234 on the first substrate 21 on the projection exists overlap, the second drain 232 on the first substrate 21 with the second active layer 234 on the first substrate 21 on the projection exists overlap.

[0160] The first direction of the first thin film transistor 22 is parallel to the second direction of the second thin film transistor 23, the first direction is the connecting direction of the first source 221 and the first drain 222, and the second direction is the connecting direction of the second source 231 and the second drain 232. In FIG. 5 and FIG. 6, the first direction and the second direction are parallel to the direction f1.

[0161] In an exemplary embodiment, referring to FIG. 3, the orthogonal projection of the channel q2 in the second active layer 234 on the first substrate 21 is located in the orthogonal projection of the first gate 223 on the first substrate 21. In this way, the second active layer 234 is formed on a flat film layer surface, thereby improving the flatness of the second active layer 234 to avoid problems such as reduced mobility and increased leakage current of the second thin film transistor 23.

[0162] Optionally, considering that there is a certain error in forming the film layer, the first thin film transistor 22 and the second thin film transistor 23 satisfy: W1≤W2+2c+ovl;

[0163] wherein W2 is the width of the channel of the second thin film transistor 23, W1 is the width of the channel of the first thin film transistor 22, ovl is the alignment deviation in manufacturing the first thin film transistor 22 and the second thin film transistor 23, ovl ranges from 0.5 microns to 1 micron, and c is the minimum distance between the edge of the first gate 223 and the edge of the first active layer 224 in the width direction f2 of the channel of the first thin film transistor, c is greater than or equal to 2.5 microns. In this way, the orthogonal projection of the channel q2 in the second active layer 234 on the first substrate 21 is located in the orthogonal projection of the first gate 223 on the first substrate 21, thereby improving the flatness of the second active layer.

[0164] When the second thin film transistor 23 is an oxide thin film transistor, the second active layer 234 is an oxide active layer, and the carrier concentration and stability of the oxide active layer are lower than those of the low-temperature polysilicon thin film transistor. Therefore, when the oxide thin film transistor satisfies the above structure, problems such as reduced mobility and increased leakage current of the oxide thin film transistor can be avoided.

[0165] FIG. 3, FIG. 5 and FIG. 6 provide a structure in which two thin film transistors are parallel and overlapped.

[0166] Another overlapping structure is shown in FIG. 14, FIG. 15 and FIG. 16. FIG. 14 is a schematic diagram of a structure in which two thin film transistors are overlapped according to an embodiment of the present application, FIG. 15 is a schematic diagram of a partial structure of the first thin film transistor in FIG. 14, and FIG. 16 is a schematic diagram of a partial structure of the second thin film transistor in FIG. 14.

[0167] The first source 221 and the first active layer 224 are overlapped in the orthographic projection on the first substrate 21, and the first drain 222 and the first active layer 224 are overlapped in the orthographic projection on the first substrate 21.

[0168] The second source 231 and the first active layer 224 are overlapped in the orthographic projection on the first substrate 21, and the second drain 232 and the first active layer 224 are overlapped in the orthographic projection on the first substrate 21.

[0169] The first direction of the first thin film transistor 22 and the second direction of the second thin film transistor are perpendicular, the first direction is the connecting direction of the first source 221 and the first drain 222, and the second direction is the connecting direction of the second source 231 and the second drain 232. In FIG. 15 and FIG. 16, the first direction is parallel to the direction f2, the second direction is parallel to the direction f1, and the direction f1 is perpendicular to the direction f2.

[0170] FIG. 17 is a schematic diagram of a cross-sectional structure (the cross-sectional position is D-D) of the structure shown in FIG. 14, wherein the orthographic projection of the channel q2 in the second active layer 234 on the first substrate 21 is located in the orthographic projection of the first gate 223 on the first substrate 21. In this way, the second active layer 234 can be formed on a flat film layer surface, thereby improving the flatness of the second active layer 234 to avoid problems such as reduced mobility and increased leakage current of the second thin film transistor 23.

[0171] Optionally, referring to FIG. 15 and FIG. 16, considering that there is a certain error when forming a film layer, the first thin film transistor 22 and the second thin film transistor 23 satisfy: L2≤W1+2c+ovl; W2≤L1;

[0172] W2 is the width of the channel q2 of the second thin film transistor 23, W1 is the width of the channel q1 of the first thin film transistor 22, L1 is the length of the channel of the first thin film transistor 22, L2 is the length of the channel q2 of the second thin film transistor 23, ovl is the alignment deviation when manufacturing the first thin film transistor 22 and the second thin film transistor 23, the range of ovl is 0.5 microns to 1 micron, and c is the minimum distance between the edge of the first gate 223 and the edge of the first active layer 224 in the width direction f1 of the channel q1 of the first thin film transistor 22, c is greater than or equal to 2.5 microns. In this way, the orthographic projection of the channel q2 in the second active layer 234 on the first substrate 21 is located in the orthographic projection of the first gate 223 on the first substrate 21, thereby improving the flatness of the second active layer.

[0173] When the second thin film transistor 23 is an oxide thin film transistor, the second active layer 234 is an oxide active layer, and the oxide active layer has lower carrier concentration and stability than a low-temperature polysilicon thin film transistor. Therefore, when the oxide thin film transistor satisfies the above structure, the oxide thin film transistor can avoid problems such as a decrease in mobility and an increase in leakage current.

[0174] FIGS. 14, 15, 16, and 17 show a structure in which two thin film transistors are vertically overlapped.

[0175] The above embodiments provide a cross-sectional structure diagram of each film layer of the overlapped first thin film transistor and the second thin film transistor. However, the overlapped thin film transistor provided by the embodiments of the present application can also have other structures, which are described below.

[0176] Another structure is shown in FIG. 18, which is another cross-sectional structure diagram of the overlapped thin film transistor provided by the embodiments of the present application. In this structure, the first gate 223 of the first thin film transistor 22 includes a third sub-gate 2231 between the first active layer 224 and the second active layer 234 and a fourth sub-gate 2232 between the first active layer 224 and the first substrate 21, and the second gate 233 is located on a side of the second active layer 234 away from the first substrate 21. The first thin film transistor 22 in this structure is a double-gate first thin film transistor. The second thin film transistor 23 is a top-gate thin film transistor, which can reduce the number of film layers and the thickness of the overall structure compared with the double-gate thin film transistor.

[0177] Another structure is shown in FIG. 19, which is another cross-sectional structure diagram of the overlapped thin film transistor provided by the embodiments of the present application. In this structure, the first gate 223 of the first thin film transistor 22 is located between the first active layer 224 and the second active layer 234, and the second gate 233 is located on a side of the second active layer 234 away from the first substrate 21. The second thin film transistor 23 in this structure is a top-gate thin film transistor, which can reduce the number of film layers and the thickness of the overall structure compared with the double-gate thin film transistor.

[0178] Another structure please refer to Figure 20, Figure 20 is another cross-section structure schematic diagram of the overlapped thin film transistor provided by the embodiment of the present application. Wherein, the first gate 223 is located between the first active layer 224 and the second active layer 234, and the second gate 233 is located between the first gate 223 and the second active layer 234. The first gate of the first thin film transistor 22 in this structure is located above the first active layer 224, which is a top gate first thin film transistor. The second thin film transistor 23 is a bottom gate thin film transistor, compared with the above-mentioned double gate second thin film transistor, this kind of bottom gate thin film transistor can reduce the number of film layers, reduce the thickness of the overall structure.

[0179] Another structure please refer to Figure 21, Figure 21 is another cross-section structure schematic diagram of the overlapped thin film transistor provided by the embodiment of the present application. Wherein, the first gate 223 of the first thin film transistor 22 is located between the first active layer 224 and the second active layer 234, and the first gate 223 of the first thin film transistor 22 and the first gate 233 of the second thin film transistor 23 are the same gate, that is, the first thin film transistor 22 and the second thin film transistor 23 share a gate, so as to further reduce the number of film layers and reduce the thickness of the overall structure.

[0180] Some other film layers included in the laminated thin film transistor provided by the embodiment of the present application are described below. Please refer to Figure 3, wherein the structure further includes a first gate insulating layer 511, a second gate insulating layer 512, a first interlayer dielectric layer 514, a buffer layer 515, a third gate insulating layer 516 and a second interlayer dielectric layer 517.

[0181] The second gate 233 of the second thin film transistor 23 includes a first sub-gate 2331 and a second sub-gate 2332.

[0182] The first active layer 224, the first gate insulating layer 511, the first gate 223, the second gate insulating layer 512, the first sub-gate 2331, the first interlayer dielectric layer 514, the buffer layer 515, the second active layer 234, the third gate insulating layer 516, the second sub-gate 2332 and the second interlayer dielectric layer 517 are on the first substrate 21, and are arranged in the direction f3 away from the first substrate 21.

[0183] The first source electrode 221, the first drain electrode 222, the second source electrode 231 and the second drain electrode 232 are located on the first substrate 21 provided with the second interlayer dielectric layer 517, and the first source electrode via hole h1 and the first drain electrode via hole h2 are formed on the first gate insulating layer 511, the second gate insulating layer 512, the first interlayer dielectric layer 514, the buffer layer 515, the third gate insulating layer 516 and the second interlayer dielectric layer 517, the first source electrode 221 is electrically connected to the first active layer 224 through the first source electrode via hole h1, and the first drain electrode 222 is electrically connected to the first active layer 224 through the first drain electrode via hole h2.

[0184] The second source electrode via hole h3 and the second drain electrode via hole h4 are formed on the third gate insulating layer 516 and the second interlayer dielectric layer 517, the second source electrode 231 is electrically connected to the second active layer 234 through the second source electrode via hole h3, and the second drain electrode 232 is electrically connected to the second active layer 234 through the second drain electrode via hole h4.

[0185] Optionally, the structure further includes a first connection pattern 52, the first connection pattern 52 includes a first connection line 521, and the first connection line 521 is a same layer structure with the first source electrode 221. The first connection line 521 is electrically connected to the first drain electrode 222 and the second drain electrode 232 respectively.

[0186] In addition, referring to FIG. 2, FIG. 5 and FIG. 6, the structure can further include a first gate via hole h5, a second gate via hole h6 and a third gate via hole h7, and the first connection pattern 52 can further include a second connection line 522, the second connection line 522 is a same layer structure with the first source electrode 221. The second connection line 522 is electrically connected to the underlying first gate 223 through the first gate via hole h5, the second connection line 522 is electrically connected to the underlying first sub-gate 2331 through the second gate via hole h6, and the second connection line 522 is electrically connected to the underlying second sub-gate 2332 through the third gate via hole h7. In this way, the connection structure that the gate of the first thin film transistor is electrically connected to the gate of the second thin film transistor is realized.

[0187] In addition, the structure can further include a polyimide (PI) layer 611, a first passivation layer (pvx1) 612, a barrier layer 613 and a bottom buffer layer 614 arranged in a direction f3 away from the first substrate between the first gate insulating layer 511 and the first substrate 21. The structure can further include a planarization layer (PLN) 615, a second passivation layer (pvx2) 616 and a third passivation layer (pvx3) 617 arranged in the direction f3 away from the first substrate on the side of the first source electrode 221 away from the first substrate 21.

[0188] Other intersecting thin film transistor cross-sections of the film layer provided by the embodiments of the present application can refer to FIG. 3, which will not be described here in detail.

[0189] In summary, the embodiment of the present application provides an overlapped thin film transistor, including an upper thin film transistor and a lower thin film transistor, a normal projection of a channel of the lower thin film transistor on a third substrate overlaps a normal projection of a channel of the upper thin film transistor on the third substrate, that is, the two thin film transistors in the NAND gate are in an overlapped state, so that the space occupied by the two thin film transistors in the circuit can be reduced, and the size of the circuit can be reduced.

[0190] The following describes some application scenarios of the overlapped thin film transistor provided by the embodiment of the present application.

[0191] One scenario is applied to a pixel circuit, please refer to FIG. 22, which is a circuit diagram of a pixel circuit provided by an embodiment of the present application, wherein the pixel circuit 70 includes a pulse amplitude modulation module 71 and a pulse width modulation module 72, and the pulse amplitude modulation module 71 is electrically connected with the pulse width modulation module 72.

[0192] The pulse width modulation module 72 includes any inverter provided by the above embodiment.

[0193] In an exemplary embodiment, the pulse amplitude modulation module 71 includes a line connection end d3.

[0194] The pulse width modulation module 72 includes a first transmission gate TG1, a second transmission gate TG2, a first inverter N1 and a second inverter N2.

[0195] The output end d4 of the first transmission gate TG1 and the output end d5 of the second transmission gate TG2 are both electrically connected with the line connection end d3, the input end d6 of the first transmission gate TG1 is coupled with a first light-emitting control signal end Hf, the input end d7 of the second transmission gate TG2 is coupled with a second light-emitting control signal end EM, the control end d8 of the first transmission gate TG1 is electrically connected with the input end n11 of the first inverter N1 and the output end n22 of the second inverter N2, and the control end d9 of the second transmission gate TG2 is electrically connected with the output end n12 of the first inverter N1 and the input end n21 of the second inverter N2.

[0196] Optionally, please refer to FIG. 23, which is a sectional structure diagram of the pulse amplitude modulation module shown in FIG. 22. The pulse amplitude modulation module 71 includes at least one third thin film transistor 711 and at least one fourth thin film transistor 712, the third thin film transistor 711 includes a third gate 7111, a third active layer 7112, a third source 7113 and a third drain 7114, and the fourth thin film transistor 712 includes a fourth gate 7121, a fourth active layer 7122, a fourth source 7123 and a fourth drain 7124.

[0197] The third thin film transistor 711 and the first thin film transistor 22 are low-temperature polysilicon thin film transistors, and the fourth thin film transistor 712 and the second thin film transistor 23 are oxide thin film transistors.

[0198] Please refer to FIG. 23 and FIG. 3, the pulse amplitude modulation module 71 and the pulse width modulation module 72 satisfy at least one of the following conditions:

[0199] The third gate 7111 and the first gate 223 in the first thin film transistor 22 are in the same layer structure, the third active layer 7112 and the first active layer 224 in the first thin film transistor 22 are in the same layer structure, the third source 7113 and the first source 221 in the first thin film transistor 22 are in the same layer structure, and the third drain 7114 and the first drain 222 in the first thin film transistor 22 are in the same layer structure.

[0200] In addition, when the fourth gate 7121 in the fourth thin film transistor includes two sub-gates (7121a and 7121b), the two sub-gates in the fourth gate 7121 can also be in the same layer structure with the two sub-gates (2331 and 2332) of the second gate 233 in the second thin film transistor, respectively.

[0201] That is, the film layers in the overlapping thin film transistors provided by the embodiments of the present application can be in the same layer structure with the film layers in some thin film transistors in the pixel circuit, so that the effect of reducing the film layers and the manufacturing industry can be achieved.

[0202] That is, the film layers in the overlapping thin film transistors provided by the embodiments of the present application can be in the same layer structure with the film layers in some thin film transistors in the pixel circuit, so that the effect of reducing the film layers and the manufacturing industry can be achieved.

[0203] Optionally, the pulse amplitude modulation module 71 can be a structure similar to 7T1C, that is, the pulse amplitude modulation module 71 can include 7 thin film transistors and one capacitor.

[0204] For example, the driving unit 200 further includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.

[0205] The gate of the first transistor T1 is coupled with the line connection end d3, the first pole of the first transistor T1 is coupled with the first node J1, and the second pole of the first transistor T1 is the drain of the first transistor T1. The first transistor T1 can be referred to as a light-emitting control transistor.

[0206] The gate of the second transistor T2 is coupled with a reset signal terminal RST, the first pole of the second transistor T2 is coupled with a common ground terminal VSS, and the second pole of the second transistor T2 is coupled with the second node J2. The second transistor T2 can also be referred to as a reset transistor.

[0207] The gate of the third transistor T3 is coupled with a gate signal terminal Gate, the first pole of the third transistor T3 is coupled with the first node J1, and the second pole of the third transistor T3 is coupled with the second node J2. The third transistor T3 can also be referred to as a compensation transistor.

[0208] The gate of the fourth transistor T4 is coupled with the second node J2, the first pole of the fourth transistor T4 is coupled with the first node J1, and the second pole of the fourth transistor T4 is coupled with the third node J3. The fourth transistor T4 can also be referred to as a driving transistor.

[0209] The gate of the fifth transistor T5 is coupled with the gate signal terminal Gate, the first pole of the fifth transistor T5 is coupled with a data signal terminal DATA, and the second pole of the fifth transistor T5 is coupled with the third node J3.

[0210] The gate of the sixth transistor T6 is coupled with a second light-emitting control signal terminal EM, the first pole of the sixth transistor T6 is coupled with a driving power terminal VDD, and the second pole of the sixth transistor T6 is coupled with the third node J3. Since the gate of the sixth transistor T6 is connected with the second light-emitting control signal terminal EM, the sixth transistor T6 can also be referred to as a light-emitting control transistor.

[0211] The gate of the seventh transistor T7 is coupled with the reset signal terminal RST, the first pole of the seventh transistor T7 is coupled with a pull-down power terminal VSS, and the second pole of the seventh transistor T7 is coupled with the second electrode of the light-emitting unit 100.

[0212] The first pole of the first capacitor C1 is coupled with the second node J2, and the second pole of the second electrode 102 is coupled with the driving power terminal VDD. Optionally, the first capacitor C1 can be a storage capacitor, which can include two capacitor plates Cst1 and Cst2. In the embodiment of the present application, the capacitor plate Cst1 can be referred to as one end, a first end, or a first storage capacitor electrode of a storage capacitor Cst, and the capacitor plate Cst2 can be referred to as the other end, a second end, or a second storage capacitor electrode of the storage capacitor Cst.

[0213] In the embodiment of the present application, the signals received by the first light-emitting control signal terminal HF, the reset signal terminal RST, the pull-down power terminal VSS, the gate signal terminal Gate, the data signal terminal DATA, the second light-emitting control signal terminal EM, and the driving power terminal VDD are all from a driving backplane. In addition, DT and DTB in FIG. 22 are data signals.

[0214] Any two transistors in the first transistor T1 to the seventh transistor T7 can be the third thin film transistor and the fourth thin film transistor, and the embodiments of the present application do not limit this.

[0215] In summary, the embodiments of the present application provide a pixel circuit, which includes overlapping thin film transistors, the channel of a lower thin film transistor in the overlapping thin film transistors has an overlapping projection on a substrate with the channel of an upper thin film transistor, that is, the two thin film transistors in the pixel circuit are in an overlapping state, so as to reduce the space occupied by the two thin film transistors in the circuit, and further to achieve the effect of reducing the size of the pixel circuit.

[0216] Another scenario is applied to a demultiplexer, please refer to FIG. 24, which is a structural schematic diagram of a demultiplexer provided by an embodiment of the present application. The demultiplexer includes at least one inverter and at least one NAND gate, the inverter includes any one of the inverters provided by the above embodiments, and / or the NAND gate includes any one of the NAND gates provided by the above embodiments.

[0217] In an exemplary embodiment, the demultiplexer (Demux) includes 6 inverters (fx1 to fx6) and 7 NAND gates (yf1 to yf7), and the connection relationship can be as shown in FIG. 24. The demultiplexer can accept 3 input signals x1, x2 and x0, and output 3 data signals DT1, DT2 and DT3, and output 3 gate signals G1, G2 and G3, and output a light-emitting control signal EM.

[0218] FIG. 25 is a schematic diagram of a first active layer pattern and a first gate pattern in a demultiplexer provided by an embodiment of the present application. The first active layer pattern po can include a first active layer in a plurality of first thin film transistors. The first gate pattern gt1 can include a first gate in the plurality of first thin film transistors.

[0219] FIG. 26 is a schematic diagram of a second gate pattern and a first interlayer dielectric layer in a demultiplexer provided by an embodiment of the present application.

[0220] The second gate pattern gt2 can include a first sub-gate in a plurality of second thin film transistors, and the first interlayer dielectric layer 514 can include a plurality of vias 1h. The via 1h can be used to enable the circuit on the first interlayer dielectric layer 514 to be electrically connected with the circuit below the first interlayer dielectric layer 514.

[0221] FIG. 27 is a schematic diagram of an oxide active layer pattern and a second interlayer dielectric layer in a demultiplexer provided by an embodiment of the present application.

[0222] The oxide active layer pattern IGZO can include oxide active layers in the plurality of second thin film transistors, and the second interlayer dielectric layer 517 can include a plurality of vias 2h, which can be used to enable electrical connection of a line above the second interlayer dielectric layer 517 to a line below the second interlayer dielectric layer 517.

[0223] FIG. 28 is a schematic diagram of a third gate pattern and a source-drain pattern in a multiplexer according to an embodiment of the present application.

[0224] The third gate pattern gt3 includes second sub-gates in the plurality of second thin film transistors, and the source-drain pattern sd can include first sources and first drains in the plurality of first thin film transistors, and can also include second sources and second drains in the plurality of second thin film transistors.

[0225] FIGS. 25-28 are schematic diagrams of layers of a multiplexer according to an embodiment of the present application, and FIG. 29 is a schematic diagram of layers of a multiplexer according to an embodiment of the present application.

[0226] The multiplexer described above includes 48 thin film transistors, and has a length of 280 microns and a width of 112 microns. In contrast, a multiplexer in the related art that does not use overlapping thin film transistors has a length of 437 microns and a width of 87 microns. Thus, the multiplexer according to an embodiment of the present application has a smaller area, and thus achieves the effect of reducing the space occupied by the multiplexer.

[0227] In summary, the multiplexer according to an embodiment of the present application includes overlapping thin film transistors, and the channel of a lower thin film transistor in the overlapping thin film transistors has an orthogonal projection on the substrate that overlaps the orthogonal projection on the substrate of the channel of an upper thin film transistor. That is, two thin film transistors in the multiplexer are in an overlapping state, which reduces the space occupied by the two thin film transistors in the circuit, and thus achieves the effect of reducing the size of the multiplexer.

[0228] FIG. 30 is a schematic diagram of a structure of a drive component according to an embodiment of the present application. The drive component 70 includes a pixel circuit 71, a transfer gate 72, and a multiplexer 73. The pixel circuit 71 is electrically connected to the multiplexer 73 and the transfer gate 72, and the transfer gate 72 is electrically connected to the multiplexer 73. The drive component satisfies at least one of the following conditions.

[0229] The pixel circuit 71 includes any one of the pixel circuits according to the embodiments described above;

[0230] The multiplexer 73 includes any one of the multiplexers according to the embodiments described above;

[0231] The transfer gate 72 includes any one of the transfer gates provided in the above embodiments.

[0232] In FIG. 30, PR is the pixel circuit of the red sub-pixel, PG is the pixel circuit of the green sub-pixel, and PB is the pixel circuit of the blue sub-pixel.

[0233] DA is a data signal terminal, LVDD is a driving power terminal, LVSS is a pull-down power terminal, RST is a reset signal terminal, HF is a first light-emitting control signal terminal, and EM is a second light-emitting control signal terminal. The signal provided by the data signal terminal Da includes a data signal terminal Rd corresponding to the red sub-pixel, a data signal terminal Gd corresponding to the green sub-pixel, and a data signal terminal Bd corresponding to the blue sub-pixel.

[0234] In addition, the demultiplexer 73 can provide the red sub-pixel with a red gate signal GR, provide the green sub-pixel with a green gate signal GG, and provide the blue sub-pixel with a blue gate signal GB.

[0235] When the driving circuit is applied to a display chip, the HF signal, the RST signal, the LVSS signal, the Rd signal, the Gd signal, the Bd signal, the EM signal, and the LVDD signal can be provided by a driving backplane in the display chip.

[0236] In summary, the embodiment of the present application provides a driving assembly, the driving assembly includes overlapping thin film transistors, the channel of the lower thin film transistor in the overlapping thin film transistors on the substrate has an overlapping projection with the channel of the upper thin film transistor on the substrate, that is, the two thin film transistors in the driving assembly are in an overlapping state, so as to reduce the space occupied by the two thin film transistors in the circuit, and further to realize the effect of reducing the size of the driving assembly.

[0237] FIG. 31 is a structural schematic diagram of a display chip provided by an embodiment of the present application, the display chip 80 includes:

[0238] The light-emitting unit 81 includes a first electrode 811, a second electrode 812, and a light-emitting part 813 electrically connected to the first electrode 811 and the second electrode 812, respectively.

[0239] The driving unit 82 includes a first driving circuit layer 821 and a second driving circuit layer 822 arranged in layers, and the first driving circuit layer 821 is located between the light-emitting unit 81 and the second driving circuit layer 822; the first driving circuit layer 821 includes a third electrode 8211 and a fourth electrode 8212, both of which are located on the side of the first driving circuit layer 821 facing the light-emitting unit 81, the third electrode 8211 is electrically connected to the first electrode 811, and the fourth electrode 8212 is electrically connected to the second electrode 812.

[0240] The first driving circuit layer 821 includes at least one first thin film transistor, and the second driving circuit layer 822 includes at least one second thin film transistor. The first thin film transistor and the second thin film transistor constitute an inverter. The inverter can be any inverter provided in the above embodiments.

[0241] In addition, the second driving circuit layer 822 includes a pin 8221. The driving unit 82 can include a plurality of pins 8221. The plurality of pins 8221 are located on the side of the second driving circuit layer 822 away from the first driving circuit layer 821. The material of the pin 8221 can be copper (Cu). One or more of the plurality of pins 8221 are electrically connected to the first thin film transistor, and one or more of the plurality of pins 8221 are electrically connected to the second thin film transistor. The plurality of pins 8221 are used for subsequent die bonding and bonding with the driving backplate.

[0242] In summary, the display chip provided in the embodiments of the present application includes overlapping thin film transistors. The orthogonal projection of the channel of the lower thin film transistor on the substrate overlaps with the orthogonal projection of the channel of the upper thin film transistor on the substrate. That is, the two thin film transistors in the display chip are in an overlapping state. In this way, the space occupied by the two thin film transistors in the circuit can be reduced, and the size of the display chip can be reduced.

[0243] In addition, the display substrate provided in the embodiments of the present application includes a driving backplate 111 and the display chip 80 provided in the above embodiments. The driving backplate 111 includes a driving substrate and a pad on the driving substrate. The pad includes a plurality of conductive pads. The conductive pads are used to be electrically connected to the pins in the display chip 80.

[0244] The plurality of display chips 80 are located in the display area a of the display substrate, and the plurality of display chips 80 are arranged in an array. The driving backplate 111 is used to provide driving signals for the driving unit 82 through the plurality of pins 8221 in the display chip 80, so that the driving unit 82 drives the light emitting unit 81 to emit light.

[0245] In addition, the plurality of display chips 80 in the display substrate are independently arranged, that is, the display chips 80 are independent of each other. In this way, the maintenance and replacement of a single light emitting component can be realized. Optionally, the display chip 80 can be an independent chip structure, and different display chips 80 are distributed at intervals. For example, different display chips 80 are isolated by air.

[0246] Optionally, the display substrate can be a display screen in a mobile phone, a notebook computer or a flat computer, or an outdoor advertising screen.

[0247] Since the display substrate can have substantially the same technical effects as the light-emitting component described in the foregoing embodiments, for the purpose of brevity, the technical effects of the display substrate are not described herein again.

[0248] FIG. 33 is a structural schematic diagram of a flip-flop provided in an embodiment of the present application, which includes a plurality of clock signal rising edge detectors 331, a plurality of clock signal falling edge detectors 332, a frame start signal generating latch 333, and a plurality of reset / set (RS) flip-flops 334. The connection structure of these elements is shown in FIG. 33, FIG. 34 is a circuit diagram of a clock signal rising edge detector in the flip-flop shown in FIG. 33, FIG. 35 is a circuit diagram of a clock signal falling edge detector in the flip-flop shown in FIG. 33, FIG. 36 is a circuit diagram of a frame start signal generating latch in the flip-flop shown in FIG. 33, and FIG. 37 is a circuit diagram of an RS flip-flop in the flip-flop shown in FIG. 33.

[0249] The clock signal rising edge detector 331 includes 3 inverters N and a NAND gate y1. The clock signal falling edge detector 332 includes 4 inverters N and a NAND gate y1. The frame start signal generating latch 333 includes 2 inverters N and 2 NAND gates y1. The RS flip-flop includes 4 inverters N and a NAND gate y1.

[0250] The NAND gate y1 includes any one of the NAND gates provided in the foregoing embodiments, and / or the inverter N includes any one of the inverters provided in the foregoing embodiments.

[0251] In addition, the clock signal rising edge detector 331 further includes an OR gate y2, a bidirectional TVS transient voltage suppression diode y3, and a transistor y4.

[0252] The clock signal falling edge detector 332 further includes an OR gate y2 and a bidirectional TVS transient voltage suppression diode y3. The frame start signal generating latch 333 further includes an OR gate y2. The RS flip-flop 334 further includes an OR gate y2.

[0253] In addition, for FIGS. 34 to 37, a is a signal to be measured, SCS is a control switch, SCLK is a clock signal, RST is a reset signal, and SET is a set signal.

[0254] Since the flip-flop can apply the inverters and the NAND gates provided in the foregoing embodiments, the flip-flop can also have similar technical effects, which are not described herein again in the embodiments of the present application.

[0255] The flip-flop can be applied in a driving component to drive a pixel circuit.

[0256] In related technologies, the pins of a display chip are bonded to the driving backplane via die bonding. The more pins a display chip has, the more defects will occur due to the yield rate of die bonding. Therefore, reducing the number of pins is one way to reduce defects caused by die bonding. However, to achieve the same function with fewer pins, the number of thin-film transistors (TFTs) in the display chip's circuitry must increase, which will severely affect the size of the display chip. The overlapping arrangement of multiple TFTs provided in this application can reduce the space occupied by the TFTs, thereby reducing the impact of the number of TFTs on the size of the circuitry in the display chip while reducing the number of pins.

[0257] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0258] In this application, the term "at least one of A and B" merely describes the relationship between related objects, indicating that three relationships can exist. For example, "at least one of A and B" can represent: A existing alone, A and B existing simultaneously, and B existing alone. Similarly, "at least one of A, B, and C" indicates that seven relationships can exist, representing: A existing alone, B existing alone, C existing alone, A and B existing simultaneously, A and C existing simultaneously, C and B existing simultaneously, and A, B, and C existing simultaneously. Likewise, "at least one of A, B, C, and D" indicates that fifteen relationships can exist, representing: A existing alone, B existing alone, C existing alone, D existing alone, A and B existing simultaneously, A and C existing simultaneously, A and D existing simultaneously, C and B existing simultaneously, D and B existing simultaneously, C and D existing simultaneously, A, B, and C existing simultaneously, A, B, and D existing simultaneously, A, C, and D existing simultaneously, and A, B, C, and D existing simultaneously.

[0259] It is to be understood that the figures illustrate the concept, and that for clarity's sake the size of layers and regions can have been exaggerated. It is to be further understood that, when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer, or intervening layers can also be present. Furthermore, it can be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or layer, or one or more intervening layers or elements can also be present. In addition, it can be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer or element between the two layers or elements, or one or more intervening layers or elements can also be present. Similar reference characters do not indicate similar elements throughout the several views.

[0260] In this application, the terms "first", "second", "third", and "fourth" are used only to describe the relative importance of the elements, and are not used to indicate or imply a relative importance or a ranking of the elements. The term "plurality" means two or more, unless otherwise expressly specified.

[0261] The above description is only optional embodiments of the present application, and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. An inverter, characterized in that, The inverter includes: a first substrate and an input terminal, an output terminal, a first thin-film transistor, and a second thin-film transistor located on the first substrate, wherein the first thin-film transistor is a P-type thin-film transistor and the second thin-film transistor is an N-type thin-film transistor; The first thin-film transistor includes a first source, a first drain, and a first gate; the second thin-film transistor includes a second source, a second drain, and a second gate; the input terminal is electrically connected to the first gate and the second gate; and the output terminal is electrically connected to the first drain and the second drain. The orthographic projection of the channel of the first thin-film transistor onto the first substrate overlaps with the orthographic projection of the channel of the second thin-film transistor onto the first substrate.

2. The inverter according to claim 1, characterized in that, The first thin-film transistor is a low-temperature polycrystalline silicon thin-film transistor, and the second thin-film transistor is an oxide thin-film transistor; The second thin-film transistor is located on the side of the first thin-film transistor away from the first substrate, the first thin-film transistor includes a first active layer, and the second thin-film transistor includes a second active layer; The first gate is located between the first active layer and the second active layer. The second gate includes a first sub-gate and a second sub-gate. The first sub-gate is located on the side of the second active layer closer to the first substrate, and the second sub-gate is located on the side of the second active layer away from the first substrate. The first gate is located between the first active layer and the second active layer, and the second gate is located on the side of the second active layer away from the first substrate, or... The first gate is located between the first active layer and the second active layer, and the second gate is located on the side of the second active layer away from the first substrate, or... The first gate is located between the first active layer and the second active layer, and the second gate is located between the first gate and the second active layer, or... The first gate includes a third sub-gate located between the first active layer and the second active layer, and a fourth sub-gate located between the first active layer and the first substrate.

3. The inverter according to claim 1, characterized in that, The first thin-film transistor further includes a first active layer, and the second thin-film transistor includes a second active layer; The orthographic projection of the first source electrode onto the first substrate and the first active layer onto the first substrate The orthographic projections on the bottom overlap, and the orthographic projection of the first drain electrode on the first substrate overlaps with the orthographic projection of the first active layer on the first substrate. The orthographic projection of the second source electrode on the first substrate overlaps with the orthographic projection of the second active layer on the first substrate, and the orthographic projection of the second drain electrode on the first substrate overlaps with the orthographic projection of the second active layer on the first substrate. The first direction of the first thin-film transistor is parallel to the second direction of the second thin-film transistor. The first direction is the line direction connecting the first source and the first drain, and the second direction is the line direction connecting the second source and the second drain.

4. The inverter according to claim 1, characterized in that, The first thin-film transistor further includes a first active layer, and the second thin-film transistor includes a second active layer; The orthographic projection of the first source electrode on the first substrate overlaps with the orthographic projection of the first active layer on the first substrate, and the orthographic projection of the first drain electrode on the first substrate overlaps with the orthographic projection of the first active layer on the first substrate. The orthographic projection of the second source electrode on the first substrate overlaps with the orthographic projection of the second active layer on the first substrate, and the orthographic projection of the second drain electrode on the first substrate overlaps with the orthographic projection of the second active layer on the first substrate. The first direction of the first thin-film transistor is perpendicular to the second direction of the second thin-film transistor. The first direction is the line direction connecting the first source and the first drain, and the second direction is the line direction connecting the second source and the second drain.

5. The inverter according to claim 3 or 4, characterized in that, The inverter further includes a first gate insulating layer, a second gate insulating layer, a first interlayer dielectric layer, a buffer layer, a third gate insulating layer, and a second interlayer dielectric layer; The second gate includes a first sub-gate and a second sub-gate; The first active layer, the first gate insulating layer, the first gate, the second gate insulating layer, the first sub-gate, the first interlayer dielectric layer, the buffer layer, the second active layer, the third gate insulating layer, the second sub-gate, and the second interlayer dielectric layer are disposed on the first substrate in a direction away from the first substrate; The first source, the first drain, the second source, and the second drain are located on a first substrate having a second interlayer dielectric layer, and the first gate insulating layer, the second gate insulating layer, The first interlayer dielectric layer, the buffer layer, the third gate insulating layer, and the second interlayer dielectric layer have a first source via and a first drain via. The first source is electrically connected to the first active layer through the first source via, and the first drain is electrically connected to the first active layer through the first drain via. The third gate insulating layer and the second interlayer dielectric layer have a second source via and a second drain via. The second source is electrically connected to the second active layer through the second source via, and the second drain is electrically connected to the second active layer through the second drain via.

6. The inverter according to claim 5, characterized in that, The inverter further includes a first connection pattern, the first connection pattern including a first connection line, the first connection line and the first source electrode having the same layer structure; The first connecting line is electrically connected to the first drain and the second drain, respectively.

7. The display circuit according to claim 3 or 4, characterized in that, The first thin-film transistor includes a first gate, and the second thin-film transistor includes a second active layer. The first gate is located on the side of the second active layer close to the first substrate, and the orthographic projection of the channel in the second active layer onto the first substrate is located in the orthographic projection of the first gate onto the first substrate.

8. The inverter according to claim 7, characterized in that, The first thin-film transistor further includes a first gate, the dimension of the first gate in the width direction of the channel of the first thin-film transistor is greater than the dimension of the first active layer in the width direction of the channel of the first thin-film transistor, and the minimum distance between the edge of the first gate and the edge of the first active layer is greater than or equal to 2.5 micrometers.

9. The inverter according to claim 1, characterized in that, The inverter satisfies: L1≥L2; L1 is the length of the channel of the first thin-film transistor, and L2 is the length of the channel of the second thin-film transistor.

10. A pixel circuit, characterized in that, The pixel circuit includes a pulse width modulation module and a pulse amplitude modulation module, and the pulse width modulation module is electrically connected to the pulse amplitude modulation module. The pulse width modulation module includes the inverter as described in any one of claims 1 to 9.

11. The pixel circuit according to claim 10, characterized in that, The pulse amplitude modulation module includes a line connection terminal; The pulse width modulation module includes a first transmission gate, a second transmission gate, a first inverter, and a second inverter; The output terminals of both the first transmission gate and the second transmission gate are electrically connected to the line connection terminal. The input terminal of the first transmission gate is coupled to the first light emission control signal terminal, and the input terminal of the second transmission gate is coupled to the second light emission control signal terminal. The control terminal of the first transmission gate is electrically connected to the input terminal of the first inverter and the output terminal of the second inverter, and the control terminal of the second transmission gate is electrically connected to the output terminal of the first inverter and the input terminal of the second inverter.

12. The pixel circuit according to claim 10, characterized in that, The pulse amplitude modulation module includes at least one third thin-film transistor and at least one fourth thin-film transistor. The third thin-film transistor includes a third gate, a third active layer, a third source, and a third drain. The fourth thin-film transistor includes a fourth gate, a fourth active layer, a fourth source, and a fourth drain. The third thin-film transistor and the first thin-film transistor in the inverter are low-temperature polycrystalline silicon thin-film transistors, and the fourth thin-film transistor and the second thin-film transistor in the inverter are oxide thin-film transistors. The pulse width modulation module and the pulse amplitude modulation module satisfy at least one of the following conditions: The third gate is in the same layer as the first gate in the first thin film transistor, the third active layer is in the same layer as the first active layer in the first thin film transistor, the third source is in the same layer as the first source in the first thin film transistor, and the third drain is in the same layer as the first drain in the first thin film transistor. Furthermore, the fourth gate is in the same layer as the second gate in the second thin-film transistor, the fourth active layer is in the same layer as the second active layer in the second thin-film transistor, the fourth source is in the same layer as the second source in the second thin-film transistor, and the fourth drain is in the same layer as the second drain in the second thin-film transistor.

13. A transmission gate, characterized in that, The transmission gate includes a second substrate and a first connection terminal, a second connection terminal, a first control terminal, a second control terminal, a fifth thin-film transistor, and a sixth thin-film transistor located on the second substrate. The fifth thin-film transistor includes a fifth source, a fifth drain, and a fifth gate. The sixth thin-film transistor includes a sixth source, a sixth drain, and a sixth gate. The first connection terminal is electrically connected to the fifth source and the sixth source. The second connection terminal is electrically connected to the fifth drain and the sixth drain. The first control terminal is electrically connected to the fifth gate. The second control terminal is electrically connected to the sixth gate. The first connection terminal is electrically connected to the fifth source and the sixth source, and the second connection terminal is electrically connected to the fifth drain and the sixth drain; The orthographic projection of the channel of the fifth thin-film transistor onto the second substrate overlaps with the orthographic projection of the channel of the sixth thin-film transistor onto the second substrate.

14. A NAND gate, characterized in that, The NAND gate includes a third substrate and six ports and three thin-film transistor pairs located on the third substrate. Each thin-film transistor pair includes an upper thin-film transistor and a lower thin-film transistor. The orthogonal projection of the channel of the lower thin-film transistor on the third substrate overlaps with the orthogonal projection of the channel of the upper thin-film transistor on the third substrate. The three thin-film transistor pairs include a seventh thin-film transistor, an eighth thin-film transistor, a ninth thin-film transistor, a tenth thin-film transistor, an eleventh thin-film transistor, and a twelfth thin-film transistor; The first of the six ports is electrically connected to the gate of the seventh thin-film transistor and the gate of the eighth thin-film transistor. The second port of the six ports is electrically connected to the gate of the ninth thin-film transistor and the gate of the tenth thin-film transistor. The third of the six ports is electrically connected to the gate of the eleventh thin-film transistor and the gate of the twelfth thin-film transistor. The fourth port of the six ports is electrically connected to the first electrode of the seventh thin-film transistor, the first electrode of the ninth thin-film transistor, and the first electrode of the eleventh thin-film transistor. The fifth port of the six ports is electrically connected to the second electrode of the seventh thin-film transistor, the second electrode of the ninth thin-film transistor, and the second electrode of the eleventh thin-film transistor. The second terminal of the eighth thin-film transistor is electrically connected to the fifth port, the first terminal of the eighth thin-film transistor is electrically connected to the second terminal of the tenth thin-film transistor, the first terminal of the tenth thin-film transistor is electrically connected to the second terminal of the twelfth thin-film transistor, and the first terminal of the twelfth thin-film transistor is electrically connected to the sixth port among the six ports. The first electrode is the source, and the second electrode is the drain.

15. A multiplexer, characterized in that, The multiplexer includes at least one inverter and at least one NAND gate, wherein the inverter includes the inverter described in any one of claims 1 to 9, and / or the NAND gate includes the NAND gate described in claim 14.

16. A driving component, characterized in that, The driving component includes a pixel circuit, a transmission gate, and a multiplexer. The pixel circuit is electrically connected to the multiplexer and the transmission gate. The transmission gate is electrically connected to the multiplexer. The driving component satisfies at least one of the following conditions. The pixel circuit includes the pixel circuit according to any one of claims 10 to 12; And the multiplexer includes the multiplexer of claim 15; The transmission gate includes the transmission gate of claim 13.

17. A display chip, characterized in that, The display chip includes: A light-emitting unit, comprising: a first electrode, a second electrode, and a light-emitting portion electrically connected to the first electrode and the second electrode respectively; A driving unit, the driving unit includes a first driving circuit layer and a second driving circuit layer stacked together, the first driving circuit layer being located between the light-emitting unit and the second driving circuit layer; the first driving circuit layer includes a third electrode and a fourth electrode, the third electrode and the fourth electrode being located on the side of the first driving circuit layer facing the light-emitting unit, the third electrode being electrically connected to the first electrode, and the fourth electrode being electrically connected to the second electrode; Wherein, the first driving circuit layer includes at least one first thin-film transistor, the second driving circuit layer includes at least one second thin-film transistor, the first thin-film transistor and the second thin-film transistor constitute an inverter, and the inverter includes the inverter according to any one of claims 1 to 9.

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