Array substrate, display panel and display apparatus

Abstract

Provided in the present disclosure are an array substrate, a display panel and a display apparatus. The array substrate comprises: a base substrate, which has a display area and a non-display area, wherein the non-display area comprises a gate drive circuit area and a dummy pixel area located between the gate drive circuit area and the display area; a first conductive layer, which is located on the base substrate, and comprises gate lines and gate electrodes, which gate lines and gate electrodes are located in the display area, wherein the gate lines extend to the dummy pixel area; a second conductive layer, which is located on the side of the first conductive layer facing away from the base substrate, and comprises data lines, source electrodes and drain electrodes, which are located in the display area, and dummy data lines, which are located in the dummy pixel area, wherein the data lines and the dummy data lines intersect the gate lines; and a semiconductor layer, which is located between the second conductive layer and the first conductive layer, and comprises a first active layer located in the display area and a second active layer located in the dummy pixel area, wherein at points adjacent to the intersection points of the data lines and the dummy data lines with the gate lines, the width of the first active layer in the extension direction of the gate lines is greater than the width of the second active layer in the extension direction of the gate lines.

Description

An array substrate, a display panel, and a display device. Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] Liquid crystal display (LCD) panels are increasingly widely used due to their advantages such as low power consumption, miniaturization, and thinness.

[0003] A liquid crystal display panel mainly consists of an array substrate and a color filter substrate arranged opposite each other, as well as a liquid crystal layer located between the array substrate and the color filter substrate. The array substrate has multiple pixel units, each containing a TFT (Thin Film Transistor) and a pixel electrode. The array substrate can typically be divided into a display area and a non-display area. Pixel units in the display area are used for image display, while pixel units in the non-display area, called dummy pixel units, do not display images and are mainly used to ensure etching uniformity at the edges of the display area.

[0004] Summary of the Invention

[0005] This disclosure provides an array substrate, a display panel, and a display device, with the specific solutions as follows:

[0006] An array substrate provided in this disclosure includes:

[0007] A substrate having a display area and a non-display area surrounding the display area, the non-display area including a gate driving circuit area and a virtual pixel area located between the gate driving circuit area and the display area;

[0008] A first conductive layer is located on the substrate, and the first conductive layer includes a gate line and a gate located in the display area, the gate line extending to the virtual pixel area;

[0009] The second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes multiple data lines, a source and a drain located in the display area, and a dummy data line located in the virtual pixel area. The data lines and the dummy data lines are all arranged to intersect with the gate line.

[0010] A semiconductor layer is located between the second conductive layer and the first conductive layer. The semiconductor layer includes a first active layer located in the display area and a second active layer located in the virtual pixel area. At the intersection of the data line, the virtual data line and the gate line, the width of the first active layer along the extension direction of the gate line is greater than the width of the second active layer along the extension direction of the gate line. The shapes of the first active layer and the second active layer are different.

[0011] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the distance between adjacent dummy data lines and data lines is less than the distance between adjacent data lines.

[0012] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the ratio of the distance between adjacent dummy data lines and the distance between adjacent data lines is in the range of 0.2 to 0.5.

[0013] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, at the same location, the ratio of the width of the second active layer to the width of the first active layer along the extension direction of the gate line is 0.2 to 0.5.

[0014] The ratio of the width of the second active layer to the width of the first active layer along the data line extension direction is 0.5 to 0.85.

[0015] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the ratio of the projected area of ​​the second active layer and the first active layer on the substrate ranges from 0.15 to 0.45.

[0016] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, both the dummy data line and the data line have a widened portion near the intersection with the gate line, and the width of the widened portion of the dummy data line along the extension direction of the gate line is smaller than the width of the widened portion of the data line along the extension direction of the gate line.

[0017] The first active layer includes a source contact, a drain contact, and a channel disposed adjacent to the widened portion of the data line;

[0018] The widened portion of the dummy data line has an opening, and the area of ​​the second active layer corresponding to the opening is a dummy channel.

[0019] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the shape of the opening is a strip structure, and the extending direction of the strip structure is the same as the extending direction of the dummy data line.

[0020] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the opening is located in the middle region of the widened portion.

[0021] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the minimum width of the widened portion of the dummy data line along the extension direction of the gate line is 8.5 μm.

[0022] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the gate line extends along the data line extension direction after passing through the virtual pixel area, and the orthographic projection of the widened portion of the virtual data line on the substrate does not overlap with the orthographic projection of the gate line and the gate electrode extending along the data line extension direction on the substrate.

[0023] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the widened portion of the dummy data line includes a first edge near the display area and a second edge away from the display area; wherein...

[0024] The minimum distance between the first edge and the adjacent gate is 2.5 μm, and the minimum distance between the second edge and the gate line extending along the data line extension direction is 2.5 μm.

[0025] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the pattern outline of the second conductive layer is substantially the same as the pattern outline of the semiconductor layer.

[0026] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the plurality of data lines and the plurality of gate lines define a plurality of sub-pixels in the display area. The sub-pixels include pixel electrodes located on the side of the second conductive layer away from the substrate. The virtual pixel area includes dummy pixel electrodes disposed on the same layer and with the same material as the pixel electrodes.

[0027] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the width of the dummy pixel electrode is smaller than the width of the pixel electrode.

[0028] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the distances from adjacent dummy pixel electrodes and the distances from the pixel electrodes to the data lines between them are the same.

[0029] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the non-display area further includes a ring-shaped common signal line located between the gate driving circuit area and the virtual pixel area, and at least one end of the dummy data line is electrically connected to the common signal line.

[0030] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the common signal line includes a first common signal line disposed on the same layer and material as the gate line and a second common signal line disposed on the same layer and material as the pixel electrode. The second common signal line and the first common signal line are electrically connected through vias, and the dummy data line and the second common signal line are electrically connected through vias.

[0031] In one possible implementation, the array substrate provided in the embodiments of this disclosure further includes: a common electrode layer located between the second conductive layer and the pixel electrode, and a metal layer located between the common electrode layer and the pixel electrode and electrically connected to the common electrode layer in direct contact; the metal layer has a mesh structure, the mesh openings of the mesh structure expose the sub-pixel, and the metal layer is electrically connected to the second common signal line through vias.

[0032] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the orthographic projection of the first grid line extending along the data line extension direction in the mesh structure on the substrate is located within the orthographic projection of the data line on the substrate, and the orthographic projection of the second grid line extending along the gate line extension direction in the mesh structure on the substrate is located within the orthographic projection of the gate line on the substrate.

[0033] In one possible implementation, the array substrate provided in the embodiments of this disclosure further includes spacers, the orthographic projection of the spacers on the substrate overlapping the orthographic projections of at least a portion of the data lines and at least a portion of the channels of the first active layer on the substrate.

[0034] The first grid line corresponding to the spacer includes at least two disconnected first metal lines, and the spacer is located between the two first metal lines.

[0035] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, one of the first metal lines includes a first blocking portion extending from the disconnected position to both sides in the extension direction of the gate line, the first blocking portion being a partial structure of the second grid line; the other first metal line includes a second blocking portion extending from the disconnected position to both sides in the extension direction of the gate line.

[0036] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the distance from the first blocking portion to the spacer is approximately the same as the distance from the second blocking portion to the spacer.

[0037] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the material of the semiconductor layer includes at least one of polycrystalline silicon and metal oxide.

[0038] Accordingly, this disclosure also provides a display panel, including the array substrate described in any of the above embodiments.

[0039] In one possible implementation, the display panel provided in the embodiments of this disclosure further includes: a counter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the counter substrate.

[0040] Accordingly, this disclosure also provides a display device, including the display panel provided in the embodiments of this disclosure. Attached Figure Description

[0041] Figure 1 is a top view of a display substrate provided in an embodiment of this disclosure;

[0042] Figure 2 is an enlarged view of the area within the dashed box E in Figure 1;

[0043] Figure 3 is a schematic cross-sectional view along the CC' direction in Figure 2;

[0044] Figure 4 is an enlarged schematic diagram of the area within the dashed box G in Figure 2;

[0045] Figure 5 is a magnified view of the area within the dashed box E in Figure 1;

[0046] Figure 6 is a magnified view of a portion of the area AA shown in Figure 1;

[0047] Figure 7 is a cross-sectional view of the data line side within display area AA in Figure 6;

[0048] Figure 8 is a cross-sectional view of the grid line side in the display area AA of Figure 6;

[0049] Figure 9 is a magnified view of the area within the dashed box Q in Figure 1;

[0050] Figure 10A is a schematic diagram of the structure of the array substrate provided in the present disclosure during the manufacturing process;

[0051] Figure 10B is another structural schematic diagram of the array substrate provided in the present disclosure during the manufacturing process;

[0052] Figure 10C is another structural schematic diagram of the array substrate provided in the present disclosure during the manufacturing process;

[0053] Figure 10D is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0054] Figure 10E is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0055] Figure 10F is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0056] Figure 10G is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0057] Figure 10H is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0058] Figure 10I is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0059] Figure 10J is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0060] Figure 10K is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0061] Figure 10L is another structural schematic diagram of the array substrate provided in the embodiment of this disclosure during the manufacturing process;

[0062] Figure 11 is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0064] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "comprising" or "including," and similar terms as used in this disclosure, mean that an element or object preceding the term encompasses the elements or objects listed following the term and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "inner," "outer," "upper," and "lower" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0065] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0066] In related technologies, display product designs often incorporate a column or row of dummy pixels around the perimeter of the display area (AA area). This aims to improve the uniformity of channel etching around the display area's edges and prevent channel opening defects. However, dummy pixels occupy significant space, especially when the space on the left and right sides of the display panel is limited, posing design challenges. For example, in the design of medium to large-sized products like MNTs and notebooks, typically one column of dummy pixels is placed on each side of the AA area, with each column occupying approximately 290μm. Even in cases of limited space, a half-column of dummy pixels is required, still occupying approximately 82μm of space.

[0067] With the development of display technology, consumers have increasingly higher demands for narrow bezels in display panels. Ultra-narrow bezel products have a huge competitive advantage in the market. However, with the increase in resolution, the amount of peripheral wiring, and the increasingly stringent specification requirements, the design of setting up a column of dummy pixels on both the left and right sides in related technologies is very unfavorable to the design requirements of ultra-narrow bezels and high-resolution products. The design of ultra-narrow bezels has reached a bottleneck due to insufficient design margin.

[0068] To address the aforementioned technical problems in related technologies, this disclosure provides an array substrate, as shown in Figures 1-3. Figure 1 is a partial top view of a portion of the film layers in the array substrate, Figure 2 is an enlarged view within the dashed box E in Figure 1, and Figure 3 is a cross-sectional view along the CC' direction in Figure 2. The array substrate includes:

[0069] The substrate 1 has a display area AA and a non-display area BB surrounding the display area AA. The non-display area BB includes a gate driving circuit area B1 (GOA) and a virtual pixel area B2 located between the gate driving circuit area B1 and the display area AA.

[0070] The first conductive layer 2 is located on the substrate 1. The first conductive layer 2 may be a gate layer. The first conductive layer 2 includes a gate line 21 and a gate 22 located in the display area. The gate line 21 extends to the virtual pixel area B2.

[0071] The second conductive layer 3 is located on the side of the first conductive layer 2 away from the substrate 1. The second conductive layer 3 can be a source / drain metal layer. The second conductive layer 3 includes a data line 31, a source 32, and a drain 33 located in the display area AA, and a dummy data line 31' located in the virtual pixel area B2. The data line 31 and the dummy data line 31' are both arranged to intersect with the gate line 21.

[0072] Semiconductor layer 4 is located between the second conductive layer 3 and the first conductive layer 2. Semiconductor layer 4 includes a first active layer 41 located in display area AA and a second active layer 41' located in virtual pixel area B2. At the intersection of adjacent data line 31, virtual data line 31' and gate line 21, the width of the first active layer 41 along the extension direction of gate line 21 is greater than the width of the second active layer 41' along the extension direction of gate line 21. The shapes of the first active layer 41 and the second active layer 41' are different.

[0073] The array substrate provided in this embodiment avoids uneven etching of the channels around the display area by setting a second active layer of the same material as the first active layer in the virtual pixel area, thus preventing channel opening problems around the display area. Furthermore, by setting only dummy data lines and a second active layer in the virtual pixel area without setting gate, source, and drain, and by setting the width of the second active layer smaller than the width of the first active layer in the display area, this disclosure uses a smaller dummy channel instead of dummy pixels in the related technology, compared to setting a column or half column of dummy pixels in the virtual pixel area. This greatly narrows the width of the virtual pixel area, providing more space for the peripheral wiring of the display area, thereby meeting the product design requirements of ultra-narrow bezels and high resolution.

[0074] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG1 and FIG2, since the gate 22, source 32 and drain 33 are not provided in the virtual pixel area B2, and the width of the second active layer 41' is smaller than the width of the first active layer 41 in the display area AA, the distance D1 between adjacent virtual data lines 31' and data lines 31 can be set to be smaller than the distance D2 between adjacent data lines 31, thereby narrowing the width of the virtual pixel area.

[0075] Optionally, as shown in Figures 1 and 2, the ratio of the distance D1 between adjacent dummy data lines 31' and data lines 31 to the distance D2 between adjacent data lines 31 is in the range of 0.2 to 0.5. For example, the ratio of D1 to D2 can be 0.2, 0.3, 0.4, 0.5, etc.

[0076] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG1 and FIG2, at the same position, the width ratio of the second active layer 41' to the width of the first active layer 41 along the extension direction (i.e., the lateral direction) of the gate line 21 is 0.2 to 0.5, thereby narrowing the width of the virtual pixel area; for example, the width ratio can be 0.2, 0.3, 0.4, 0.5, etc.

[0077] In some embodiments of the array substrate provided in this disclosure, as shown in FIG1 and FIG2, the width ratio of the second active layer 41' to the width of the first active layer 41 along the extension direction (i.e., longitudinal direction) of the data line 31 is 0.5 to 0.85; for example, the width ratio can be 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, etc.

[0078] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG1 and FIG2, the ratio of the projected area of ​​the second active layer 41' and the first active layer 41 on the substrate 1 is in the range of 0.15 to 0.45, thereby narrowing the width of the virtual pixel area. For example, the ratio range can be 0.15, 0.2, 0.3, 0.35, 0.4, 0.45, etc.

[0079] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG1 and FIG2, the dummy data line 31' and the data line 31 both have a widened portion 301 near the intersection point F with the gate line 21. The width of the widened portion 301 of the dummy data line 31' along the extension direction of the gate line 21 is smaller than the width of the widened portion 301 of the data line 31 along the extension direction of the gate line 21, which can narrow the width of the virtual pixel area B2.

[0080] In some embodiments, as shown in FIG1 and FIG2, in the array substrate provided in the present disclosure, the first active layer 41 includes a source contact 411, a drain contact 412 and a channel 413 disposed adjacent to the widened portion 301 of the data line 31; specifically, the channel 413 is generally a U-shaped structure, and the width of the data line 31 in the area where the widened portion 301 is located is greater than the width of the data line 31 in other positions, in order to create a U-shaped channel.

[0081] In some embodiments, in the array substrate provided in this disclosure, the material of the semiconductor layer may include at least one of polycrystalline silicon and metal oxide. Optionally, the metal oxide may be any one or more of indium gallium zinc oxide (IGZO), amorphous or polycrystalline zinc oxide (ZnO), indium zinc oxide (IZO), zinc tin oxide (ZTO), zinc tin oxide (IZTO), gallium zinc tin oxide (IGZTO), and indium gallium oxide (IGO).

[0082] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 1-3, an opening H is provided in the widened portion 301 of the dummy data line 31', and the area of ​​the second active layer 41' corresponding to the opening H is a dummy channel. In this disclosure, the dummy channel is set to correspond to the interior of the dummy data line 31'. In this way, compared with the normal U-shaped channel of the display area AA, the width of the dummy channel can be reduced, thereby narrowing the width of the virtual pixel area B2.

[0083] In some embodiments, in order to save on mask and reduce manufacturing costs, the semiconductor layer 4 and the second conductive layer 3 can be fabricated using a single mask process, i.e., using halftone mask (HTM) technology. Therefore, in the array substrate provided in the embodiments of this disclosure, as shown in FIG1 and FIG2, the pattern outline of the second conductive layer 3 and the pattern outline of the semiconductor layer 4 are approximately the same, i.e., the pattern of the semiconductor layer 4 is below the pattern of the second conductive layer 3.

[0084] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 1-3, the shape of the aperture H can be a strip structure, that is, the dummy channel is a strip structure, and the extension direction of the strip structure is the same as the extension direction of the dummy data line 31'. The dummy channel of the strip structure can further reduce the width of the widened portion 301 of the dummy data line 31', thereby further reducing the width of the virtual pixel area B2. Specifically, when using HTM technology to fabricate the semiconductor layer 4 and the second conductive layer 3, the width of the Half Tone area corresponding to the aperture H is the same as the width of the Half Tone area corresponding to the U-shaped channel of the display area AA, and the Mask value can be 3.5 μm. The minimum width d1 of the actually fabricated aperture H is 4.0 μm.

[0085] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG1-FIG3, the opening H is located in the middle region of the widened portion 301, which can minimize the width of the widened portion 301 of the dummy data line 31', so that the width of the virtual pixel area B2 reaches the minimum limit value.

[0086] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG3 and FIG4, FIG4 is an enlarged schematic diagram within the dashed frame G in FIG2, the minimum width W1 of the widened portion 301 of the dummy data line 31' along the extension direction of the gate line 21 is 8.5μm, and the widths d2 of the dummy data lines 31' on the left and right sides of the opening H are (8.5-4) / 2=2.25μm respectively. Compared with the width of the widened portion 301 corresponding to the U-shaped channel of the display area AA, it is greatly reduced, which is beneficial to narrowing the width of the virtual pixel area B2.

[0087] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 2-4, the gate line 21 extends through the virtual pixel area B2 and then extends along the extension direction of the data line 31. In order to avoid mutual interference caused by the formation of parasitic capacitance between the dummy data line 31' and the gate line 21 and the gate 22, the orthographic projection of the widened portion 301 of the dummy data line 31' on the substrate 1 does not overlap with the orthographic projection of the gate line 21 and the gate 22 extending along the extension direction of the data line 31 on the substrate 1. This can effectively reduce the parasitic capacitance between the dummy data line 31' and the gate line 21 and the gate 22, and ensure capacitance consistency.

[0088] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 2-4, the widened portion 301 of the dummy data line 31' includes a first edge C1 near the display area AA and a second edge C2 away from the display area AA. In order to ensure that the orthographic projection of the widened portion 301 of the dummy data line 31' on the substrate 1 does not overlap with the orthographic projections of the gate line 21 and the gate 22 extending along the data line 31 extension direction on the substrate 1, the minimum distance W2 between the first edge C1 and the adjacent gate 22 can be 2.5 μm, and the minimum distance W3 between the second edge C2 and the gate line 21 extending along the data line 31 extension direction can be 2.5 μm. With this design, when the space of the left and right bezels is insufficient, the virtual pixel area B2 only needs a limit width of 8.5 + 2.5 + 2.5 = 13.5 μm, which greatly saves the design space around the display area AA.

[0089] In some embodiments, due to the influence of manufacturing process precision, the actual values ​​of W2 and W3 can be larger than the limit values, for example, W2 = 8.0 μm and W3 = 6.3 μm. In this way, the width of the virtual pixel area B2 is 8.5 + 8.0 + 6.3 = 22.8 μm, which greatly reduces the width of the virtual pixel area B2 compared to the design of a half-column dummy pixel (82 μm) in related technologies.

[0090] Therefore, in the array substrate provided in this embodiment, the maximum width of the virtual pixel area B2 can only occupy 13.5 μm of space. This embodiment takes a width of 22.8 μm for the virtual pixel area B2 as an example.

[0091] In some embodiments, as shown in Figures 1-4, due to the influence of the HTM technology manufacturing process, the pattern width of the semiconductor layer 4 is greater than the pattern width of the second conductive layer 3. The width between adjacent edges of the semiconductor layer 4 and the second conductive layer 3 can be 1.5μm to 1.8μm, for example, 1.5μm, 1.6μm, 1.7μm, 1.8μm, etc.

[0092] Optionally, the material of the second conductive layer 3 can be a single layer or multiple layers formed of molybdenum, aluminum, titanium, copper, alloys, etc. For example, the second conductive layer 3 is a stacked structure composed of titanium / aluminum / titanium.

[0093] In some embodiments, in the array substrate provided in this disclosure, as shown in Figures 1 and 5-8, Figure 5 is a partially enlarged schematic diagram within the dashed box E in Figure 1, Figure 6 is a partially enlarged schematic diagram within the display area AA in Figure 1, Figure 7 is a cross-sectional schematic diagram of the data line 31 side within the display area AA in Figure 6, and Figure 8 is a cross-sectional schematic diagram of the gate line 21 side within the display area AA in Figure 6. Multiple data lines 31 and multiple gate lines 21 define multiple sub-pixels in the display area AA. Each sub-pixel includes a pixel electrode 5 located on the side of the second conductive layer 3 facing away from the substrate 1. The material of the pixel electrode 5 is generally ITO, and it is fabricated using photolithography. There is a large difference between the virtual pixel area B2, which has no ITO pattern, and the display area AA, which has a high density of ITO pattern. This can easily lead to poor uniformity of exposure and etching of the ITO pattern at the edge of the display area AA. In order to ensure the uniformity of etching of the ITO pattern at the edge of the display area AA, the virtual pixel area B2 of this disclosure includes a dummy pixel electrode 6, which is set in the same layer and material as the pixel electrode 5. This can improve the uniformity of exposure and etching of the pixel electrode at the edge of the display area AA.

[0094] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG1 and FIG5, since the distance D1 between adjacent dummy data lines 31' and data lines 31 is less than the distance D2 between adjacent data lines 31 in the present disclosure, the width of the dummy pixel electrode 6 is less than the width of the pixel electrode 5.

[0095] In some embodiments, in order to ensure the consistency of pixels in the display area and the virtual pixel area, in the array substrate provided in the embodiments of this disclosure, as shown in FIG1 and FIG5, the distances from adjacent virtual pixel electrodes 6 and pixel electrodes 5 to the data line 31 between them are the same.

[0096] In some embodiments, in the array substrate provided in this disclosure, as shown in Figures 1, 2, 5, and 9 (Figure 9 is a partially enlarged schematic diagram within the dashed box Q in Figure 1), the non-display area BB further includes a ring-shaped common signal line 7 located between the gate drive circuit area B1 and the virtual pixel area B2. The common signal line 7 is not shown in Figure 1. At least one end of the dummy data line 31' is electrically connected to the common signal line 7. Exemplarily, both ends of the dummy data line 31' extending in the direction of extension are electrically connected to the common signal line 7 to provide a common voltage for the dummy data line 31', preventing the floating of the dummy data line 31' made of metal material from affecting other signals.

[0097] In some embodiments, in the array substrate provided in this disclosure, as shown in FIG9, the common signal line 7 includes a first common signal line 71 disposed in the same layer and material as the gate line 21 and a second common signal line (not shown) disposed in the same layer and material as the pixel electrode 5. The second common signal line and the first common signal line 71 are electrically connected through via V1, and the dummy data line 31' and the second common signal line are electrically connected through via V2. Specifically, the first common signal line 71 is made of the same layer and material as the gate line 21, which can reduce the common resistance; the second common signal line is made of the same layer and material as the pixel electrode 5, which allows the dummy data line 31' to be electrically connected to the first common signal line 71 through the second common signal line, so that the dummy data line 31' can be connected to the common voltage.

[0098] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 5-8, further includes: a common electrode layer 8 located between the second conductive layer 3 and the pixel electrode 5, and a metal layer 9 located between the common electrode layer 8 and the pixel electrode 5 and directly contacting and electrically connecting with the common electrode layer 8. The metal layer 9 can reduce the common resistance. The metal layer 9 has a mesh structure, and the mesh holes of the mesh structure expose the sub-pixels, so that the metal layer 9 will not affect the transmittance. The metal layer 9 is electrically connected to the second common signal line through a via V3. Since the second common signal line and the first common signal line 71 are electrically connected, the common electrode layer 8 and the first common signal line 71 are electrically connected.

[0099] In some embodiments, in the array substrate provided in this disclosure, as shown in Figures 5 and 6, the orthographic projection of the first grid line 91 extending along the data line 31 in the grid structure onto the substrate 1 lies within the orthographic projection of the data line 31 onto the substrate 1, and the orthographic projection of the second grid line 92 extending along the gate line 21 in the grid structure onto the substrate 1 lies within the orthographic projection of the gate line 21 onto the substrate 1. This avoids the first grid line 91 and the second grid line 92 from occupying the pixel opening area, thereby avoiding affecting the transmittance.

[0100] In some embodiments, the common electrode layer 8 and the metal layer 9 can be fabricated using a single mask process, i.e., HTM technology, thereby further saving mask and reducing manufacturing costs.

[0101] In some embodiments, the array substrate provided in the present disclosure, as shown in FIG1 to FIG9, further includes a gate insulating layer 10 located between the first conductive layer 2 and the semiconductor layer 4, an organic insulating layer 11 located between the second conductive layer 3 and the common electrode layer 8, a passivation layer 12 located between the metal layer 9 and the pixel electrode 5, and so on.

[0102] In some embodiments, the array substrate provided in the present disclosure, as shown in FIG5 and FIG6, further includes a spacer PS, the orthographic projection of the spacer PS on the substrate 1 overlapping with the orthographic projection of at least a portion of the data line 31 and at least a portion of the channel of the first active layer 41 on the substrate 1.

[0103] The first grid line 91 corresponding to the spacer PS includes at least two disconnected first metal lines 901, with the spacer PS located between the two first metal lines 901. This is equivalent to locking the spacer PS between the two first metal lines 901, which can prevent the spacer PS from sliding up and down when the screen is pressed, thus improving DNU (Dark Non-Uniformity) defects.

[0104] In some embodiments, as shown in FIG5 and FIG6, in the array substrate provided in the present disclosure, one of the first metal lines 901 includes a first blocking portion 901' extending from the disconnected position to both sides in the extension direction of the gate line 21, and the first blocking portion 901' is a partial structure of the second grid line 92; the other first metal line 901 includes a second blocking portion 901' extending from the disconnected position to both sides in the extension direction of the gate line 21. This can prevent the spacer PS from sliding left and right when the screen is pressed, and further improve the DNU defect.

[0105] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG5 and FIG6, the distance from the first blocking portion 901' to the spacer PS is approximately the same as the distance from the second blocking portion 901" to the spacer PS. This effectively prevents excessive sliding distance when the spacer PS slides up and down.

[0106] Optionally, the array substrate provided in this embodiment is suitable for liquid crystal display products, in which case the pixel electrode is a slit electrode; the array substrate provided in this embodiment is also suitable for organic light-emitting display products, in which case the pixel electrode can be an anode, the common electrode layer is a cathode, and a light-emitting functional layer is disposed between the pixel electrode and the common electrode layer, so that the pixel electrode, the common electrode layer and the light-emitting functional layer together constitute a light-emitting device (e.g., an organic light-emitting device OLED), wherein the light-emitting functional layer includes, but is not limited to, a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting material layer, a hole blocking layer, an electron transport layer and an electron injection layer.

[0107] The following describes the method for fabricating the array substrate provided in the embodiments of this disclosure, which may specifically include the following steps:

[0108] (1) As shown in Figure 10A, a first conductive layer 2 is formed on the substrate 1 by a process of coating → exposure → development → wet etching. The material can be an NbMo / Cu / MTD stacked structure, where MTD can be a NiMOTi alloy to protect the Cu layer from corrosion. The first conductive layer 2 mainly includes a gate 21 and a gate line 22. Then, a gate insulating layer 10 is formed on the first conductive layer 2. The material can be at least one of SiN, SiO, and SiNO.

[0109] (2) As shown in Figure 10B, a semiconductor thin film 4' is deposited on the gate insulating layer 10, and a first metal material film 3' is deposited on the semiconductor thin film 4'. The metal material can be titanium / aluminum / titanium.

[0110] (3) As shown in Figure 10C, a photoresist layer is formed on the first metal material film layer 3'. The photoresist layer is patterned by halftone masking to form a first photoresist pattern 100 including a photoresist fully retained area 101, a photoresist partially retained area 102, and a photoresist completely removed area 103. The photoresist fully retained area 101 corresponds to the area where the source, drain, data line, dummy data line, and touch signal line are located. The photoresist partially retained area 102 corresponds to the area where the source and drain are not in contact with the first active layer and the second active layer. The photoresist completely removed area 103 is the area other than the photoresist fully retained area 101 and the photoresist partially retained area 102.

[0111] (4) As shown in Figure 10D, the metal material film layer 3' is etched using the first photoresist pattern 100 as a mask to form the second conductive layer 3 corresponding to the photoresist fully retained region 101 and the photoresist semi-retained region 102.

[0112] (5) As shown in Figure 10E, the semiconductor thin film 4' is etched using the second conductive layer 3 as a mask to form a semiconductor layer 4 corresponding to the photoresist fully retained region 101 and the photoresist semi-retained region 102.

[0113] (6) As shown in Figure 10F, the first photoresist pattern 100 is ashed to remove the photoresist in the semi-retained area 102 and thin the photoresist in the fully retained area 101 to form the second photoresist pattern 100'.

[0114] (7) As shown in Figure 10G, the first metal material film layer 3' corresponding to the photoresist semi-retained region 102 is etched using the second photoresist pattern 100' as a mask to form the source electrode 32, drain electrode 33, data line, dummy data line and touch signal line, etc.

[0115] (8) As shown in Figure 10H, remove the second photoresist pattern 100'.

[0116] It should be noted that this disclosure uses HTM technology to fabricate the semiconductor layer 4 and the second conductive layer 3, which can save one mask and reduce the manufacturing cost.

[0117] (9) As shown in Figure 10I, an organic material film is deposited on the second conductive layer 3. The material can be acrylic and the thickness can be about 25,000 angstroms. Then, the organic material film is etched by the exposure → development → etching process to form an organic insulating layer 11. The organic insulating layer 11 includes a connection via V4 corresponding to the pixel electrode 5 and the drain electrode 33.

[0118] (10) As shown in Figure 10J, a transparent conductive layer (e.g., ITO) is deposited on the organic insulating layer 11, and a second metal material film (e.g., Cu) is deposited on the transparent conductive layer. Then, the second metal material film and the transparent conductive layer are wet-etched for the first time using a halftone mask process to etch away the second metal material film and the transparent conductive layer corresponding to the positions such as the connecting via V4. Then, the second metal material film is wet-etched for the second time to etch away only the second metal material film corresponding to the pixel area, forming the common electrode layer 8 and the metal layer 9.

[0119] It should be noted that the present disclosure uses HTM technology to fabricate the common electrode layer 8 and the metal layer 9. The process can be similar to steps (3)-(8). In this way, the common electrode layer 8 and the metal layer 9 can be fabricated in one mask, reducing the manufacturing cost. Furthermore, the direct contact electrical connection between the metal layer 9 and the common electrode layer 8 can reduce the resistance of the common electrode.

[0120] (11) As shown in Figure 10K, an inorganic insulating material is deposited on the metal layer 9. The thickness can be 3500 angstroms and the material can be SiNx. The inorganic insulating material that is not needed, such as the connection via V4, is etched away by the exposure → development → etching process to form a passivation layer 12.

[0121] (12) As shown in Figure 10L, a pixel electrode 5 is formed on the passivation layer 12 by a process of coating → exposure → development → etching. The material can be ITO and the thickness can be 700 angstroms. The pixel electrode 5 is electrically connected to the drain electrode 33 through the via at the position of the connecting via V4.

[0122] The array substrate provided in this disclosure can be obtained by following the above steps (1)-(12).

[0123] Based on the same inventive concept, this disclosure also provides a display panel, including the array substrate described above. Since the principle by which this display panel solves the problem is similar to that of the array substrate, the implementation of the display panel provided in this disclosure can refer to the implementation of the array substrate described above, and repeated details will not be elaborated further.

[0124] In some embodiments, the display panel provided in this disclosure may be an organic light-emitting display panel or a liquid crystal display panel. The liquid crystal display panel further includes: a counter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the counter substrate. This disclosure uses the example of both pixel electrodes and a common electrode being disposed on the array substrate for illustration; in some embodiments, the common electrode may also be disposed on the counter substrate.

[0125] Based on the same inventive concept, this disclosure also provides a display device, including the display panel described above. Since the principle by which this display device solves the problem is similar to that of the display panel described above, the implementation of the display device provided in this disclosure can refer to the implementation of the display panel described above, and repeated details will not be elaborated further.

[0126] In specific implementations, the display device provided in the embodiments of this disclosure can be an organic light-emitting display device or a liquid crystal display device, and there is no limitation herein.

[0127] In specific implementation, the display device provided in the embodiments of this disclosure may be a full-screen display device or a flexible display device, etc., and is not limited thereto.

[0128] In specific implementations, the display device provided in this disclosure embodiment can be a full-screen mobile phone as shown in FIG11. Of course, the display device provided in this disclosure embodiment can also be any product or component with display function, such as a tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on the present invention. This display device includes, but is not limited to, components such as: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in this disclosure embodiment. In other words, the display device provided in this disclosure embodiment can include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0129] The array substrate, display panel, and display device provided in this disclosure have a second active layer with the same material and layer as the first active layer in the virtual pixel area. This avoids uneven etching of the channels around the display area, thus preventing channel opening problems around the display area. Furthermore, by only setting dummy data lines and the second active layer in the virtual pixel area without setting gate, source, and drain, and by setting the width of the second active layer smaller than the width of the first active layer in the display area, this disclosure uses a smaller dummy channel instead of dummy pixels in the related technology, compared to setting a column or half column of dummy pixels in the virtual pixel area. This significantly narrows the width of the virtual pixel area, providing more space for the peripheral wiring of the display area, thereby meeting the product design requirements of ultra-narrow bezels and high resolution.

[0130] Although preferred embodiments have been described in this disclosure, it should be understood that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, this disclosure is also intended to include such modifications and variations if they fall within the scope of the claims of this disclosure and their equivalents.

Claims

1. An array substrate, wherein, include: A substrate having a display area and a non-display area surrounding the display area, the non-display area including a gate driving circuit area and a virtual pixel area located between the gate driving circuit area and the display area; A first conductive layer is located on the substrate, and the first conductive layer includes a gate line and a gate located in the display area, the gate line extending to the virtual pixel area; The second conductive layer is located on the side of the first conductive layer away from the substrate. The second conductive layer includes multiple data lines, a source and a drain located in the display area, and a dummy data line located in the virtual pixel area. The data lines and the dummy data lines are all arranged to intersect with the gate line. A semiconductor layer is located between the second conductive layer and the first conductive layer. The semiconductor layer includes a first active layer located in the display area and a second active layer located in the virtual pixel area. At the intersection of the data line, the virtual data line and the gate line, the width of the first active layer along the extension direction of the gate line is greater than the width of the second active layer along the extension direction of the gate line. The shapes of the first active layer and the second active layer are different.

2. The array substrate as claimed in claim 1, wherein, The distance between adjacent dummy data lines and the data lines is less than the distance between adjacent data lines.

3. The array substrate as described in claim 2, wherein, The ratio of the distance between adjacent dummy data lines and the distance between adjacent data lines is in the range of 0.2 to 0.

5.

4. The array substrate according to any one of claims 1-3, wherein, At the same location, the ratio of the width of the second active layer to the width of the first active layer along the extension direction of the gate line is 0.2 to 0.5; The ratio of the width of the second active layer to the width of the first active layer along the data line extension direction is 0.5 to 0.

85.

5. The array substrate as claimed in claim 4, wherein, The ratio of the projected area of ​​the second active layer to that of the first active layer on the substrate ranges from 0.15 to 0.

45.

6. The array substrate according to any one of claims 1-5, wherein, Both the dummy data line and the data line have a widened portion near their intersection with the gate line. The width of the widened portion of the dummy data line along the extension direction of the gate line is smaller than the width of the widened portion of the data line along the extension direction of the gate line. The first active layer includes a source contact, a drain contact, and a channel disposed adjacent to the widened portion of the data line; The widened portion of the dummy data line has an opening, and the area of ​​the second active layer corresponding to the opening is a dummy channel.

7. The array substrate as claimed in claim 6, wherein, The opening is in the shape of a strip structure, and the extension direction of the strip structure is the same as the extension direction of the dummy data line.

8. The array substrate as claimed in claim 7, wherein, The opening is located in the middle region of the widened portion.

9. The array substrate as claimed in claim 8, wherein, The minimum width of the widened portion of the dummy data line along the extension direction of the gate line is 8.5 μm.

10. The array substrate according to any one of claims 6-9, wherein, The gate line extends through the virtual pixel area and then extends along the data line extension direction. The orthographic projection of the widened portion of the virtual data line on the substrate does not overlap with the orthographic projection of the gate line and the gate electrode extending along the data line extension direction on the substrate.

11. The array substrate as claimed in claim 10, wherein, The widened portion of the dummy data line includes a first edge near the display area and a second edge away from the display area; wherein... The minimum distance between the first edge and the adjacent gate is 2.5 μm, and the minimum distance between the second edge and the gate line extending along the data line extension direction is 2.5 μm.

12. The array substrate according to any one of claims 1-11, wherein, The pattern outline of the second conductive layer is approximately the same as that of the semiconductor layer.

13. The array substrate according to any one of claims 1-12, wherein, The multiple data lines and the multiple gate lines define multiple sub-pixels in the display area. Each sub-pixel includes a pixel electrode located on the side of the second conductive layer away from the substrate. The virtual pixel area includes a dummy pixel electrode disposed on the same layer and material as the pixel electrode.

14. The array substrate as claimed in claim 13, wherein, The width of the dummy pixel electrode is smaller than the width of the pixel electrode.

15. The array substrate as claimed in claim 14, wherein, The adjacent dummy pixel electrodes and the pixel electrodes are equidistant from the data line between them.

16. The array substrate according to any one of claims 13-15, wherein, The non-display area also includes a ring-shaped common signal line located between the gate driving circuit area and the virtual pixel area, and at least one end of the virtual data line is electrically connected to the common signal line.

17. The array substrate as claimed in claim 16, wherein, The common signal line includes a first common signal line disposed on the same layer and material as the gate line and a second common signal line disposed on the same layer and material as the pixel electrode. The second common signal line and the first common signal line are electrically connected through vias. The dummy data line and the second common signal line are electrically connected through vias.

18. The array substrate as claimed in claim 17, wherein, Also includes: A common electrode layer is located between the second conductive layer and the pixel electrode, and a metal layer is located between the common electrode layer and the pixel electrode and is in direct contact with and electrically connected to the common electrode layer; the metal layer has a mesh structure, the mesh openings of the mesh structure expose the sub-pixel, and the metal layer is electrically connected to the second common signal line through vias.

19. The array substrate as claimed in claim 18, wherein, The orthographic projection of the first grid line extending along the data line extension direction in the grid structure onto the substrate is located within the orthographic projection of the data line onto the substrate, and the orthographic projection of the second grid line extending along the gate line extension direction in the grid structure onto the substrate is located within the orthographic projection of the gate line onto the substrate.

20. The array substrate as claimed in claim 19, wherein, It also includes spacers, the orthographic projection of which on the substrate overlaps with the orthographic projection of at least a portion of the data line and at least a portion of the channel of the first active layer on the substrate. The first grid line corresponding to the spacer includes at least two disconnected first metal lines, and the spacer is located between the two first metal lines.

21. The array substrate as claimed in claim 20, wherein, One of the first metal wires includes a first blocking portion extending from the disconnected position to both sides in the direction of extension of the grid line, and the first blocking portion is a part of the structure of the second grid line; the other first metal wire includes a second blocking portion extending from the disconnected position to both sides in the direction of extension of the grid line.

22. The array substrate as claimed in claim 21, wherein, The distance from the first blocking part to the spacer is approximately the same as the distance from the second blocking part to the spacer.

23. The array substrate according to any one of claims 1-22, wherein, The semiconductor layer is made of at least one of polycrystalline silicon and metal oxide.

24. A display panel, wherein, Includes the array substrate as described in any one of claims 1-23.

25. The display panel as claimed in claim 24, wherein, Also includes: A counter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the counter substrate.

26. A display device, wherein, Includes the display panel as described in claim 24 or 25.

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