Array substrate, display panel, and display device

Abstract

Embodiments of the present disclosure provide an array substrate, a display panel, and a display device. The array substrate comprises: a base substrate; a first conductive layer located on one side of the base substrate, wherein the first conductive layer has a plurality of first hollowed-out portions; a plurality of first light-shielding patterns in direct contact with the first conductive layer, wherein the first light-shielding patterns comprise second hollowed-out portions extending in the direction of extension of the first light-shielding patterns, and the orthographic projections of the second hollowed-out portions on the base substrate overlap with the orthographic projections of the first hollowed-out portions on the base substrate; and a plurality of second light-shielding patterns located on a layer different from the first light-shielding patterns, wherein the orthographic projections of the second light-shielding patterns on the base substrate overlap with the orthographic projections of the second hollowed-out portions on the base substrate.

Description

Array substrate, display panel and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] With the development of virtual reality technology (VR) display technology, people's demand for liquid crystal display is getting higher and higher. In order to increase the amount of display information, high resolution products are one of the inevitable trends.

[0003] SUMMARY

[0004] The present application provides an array substrate, a display panel and a display device. The array substrate comprises:

[0005] a substrate;

[0006] a first conductive layer located on one side of the substrate, the first conductive layer having a plurality of first hollows;

[0007] a plurality of first light shielding patterns in direct contact with the first conductive layer; the first light shielding pattern comprises a second hollow extending along the extension direction of the first light shielding pattern; the second hollow in the orthographic projection of the substrate overlaps with the first hollow in the orthographic projection of the substrate;

[0008] a plurality of second light shielding patterns located at different layers from the first light shielding patterns, the second light shielding pattern in the orthographic projection of the substrate overlaps with the second hollow in the orthographic projection of the substrate.

[0009] In a possible implementation, the first light shielding pattern comprises a first bending portion, a first sub-light shielding portion located on one side of the first bending portion, and a second sub-light shielding portion located on the other side of the first bending portion;

[0010] The area between the edge of the first sub-light shielding portion close to the second sub-light shielding portion and the extension line of the edge of the second sub-light shielding portion away from the first sub-light shielding portion is a first sub-hollow portion;

[0011] The area between the edge of the second sub-light shielding portion close to the first sub-light shielding portion and the extension line of the edge of the first sub-light shielding portion away from the second sub-light shielding portion is a second sub-hollow portion.

[0012] In a possible implementation, the area between the outer edge of the first bending portion towards the first sub-light shielding portion and the extension line of the outer edge of the first sub-light shielding portion away from the first bending portion is the first sub-hollow portion;

[0013] The first bending portion is adjacent to the second sub-light shielding portion, and the second sub-light shielding portion is adjacent to the first sub-light shielding portion.

[0014] In a possible implementation, the first sub-hollow portion overlaps with the nth first hollow portion in the substrate in the orthographic projection, and the second sub-hollow portion overlaps with the (n+1)th first hollow portion in the substrate in the orthographic projection, where m is a positive integer, and n is a positive integer.

[0015] One end of the first hollow portion overlaps with the first sub-hollow portion in the orthographic projection of the substrate, and the other end of the first hollow portion overlaps with the second sub-hollow portion of the adjacent first light shielding pattern in the orthographic projection of the substrate.

[0016] In a possible implementation, the first hollow portion is a slit, and the first bending portion is an extension of the edge parallel to the extension direction and passes through the center region of the first hollow portion.

[0017] In a possible implementation, the edge parallel to the extension direction of the first sub-light shielding portion overlaps with the adjacent first hollow portion in the orthographic projection of the substrate, and / or the edge parallel to the extension direction of the second sub-light shielding portion overlaps with the other adjacent first hollow portion in the orthographic projection of the substrate.

[0018] In a possible implementation, the extension direction of the first bending portion is perpendicular to the extension direction of the first sub-light shielding portion and / or the second sub-light shielding portion.

[0019] In a possible implementation, the array substrate has a plurality of pixel light-transmitting region rows extending along a first direction and arranged along a second direction; the pixel light-transmitting region row includes a plurality of pixel light-transmitting regions arranged along the first direction; the pixel light-transmitting region includes a first outer boundary and a second outer boundary; the first outer boundary extends along the first direction, and the second outer boundary intersects the first outer boundary; and the second direction intersects the first direction.

[0020] The combination of the first light shielding pattern in the orthographic projection of the substrate and the second light shielding pattern in the orthographic projection of the substrate constitutes the second outer boundary of the pixel light-transmitting region.

[0021] In a possible implementation, the plurality of second light shielding patterns includes a plurality of third sub-light shielding portions and a plurality of fourth sub-light shielding portions; the third sub-light shielding portions and the fourth sub-light shielding portions are alternately arranged along the second direction.

[0022] The third sub-shading part overlaps the first sub-hollow part in the orthographic projection of the substrate; and the fourth sub-shading part overlaps the second sub-hollow part in the orthographic projection of the substrate.

[0023] In a possible implementation, the third sub-shading part coincides with the second sub-shading part and part of the first bending part in the outer edge parallel to the extending direction, and the combination of the third sub-shading part, the second sub-shading part and part of the first bending part constitutes the second outer boundary of the pixel light-transmitting area.

[0024] The fourth sub-shading part coincides with the first sub-shading part and part of the first bending part in the outer edge parallel to the extending direction, and the combination of the fourth sub-shading part, the first sub-shading part and part of the first bending part constitutes the second outer boundary of the pixel light-transmitting area.

[0025] In a possible implementation, the third sub-shading part and the fourth sub-shading part are distributed in a staggered manner in the second direction.

[0026] In a possible implementation, the third sub-shading part has a first overlapping area with the first sub-shading part in the orthographic projection of the substrate; and the fourth sub-shading part has a second overlapping area with the second sub-shading part in the orthographic projection of the substrate.

[0027] In a possible implementation, the width of the first overlapping area in the first direction is equal to the width of the second overlapping area in the first direction.

[0028] In a possible implementation, the third sub-shading part has a third overlapping area with the first bending part in the orthographic projection of the substrate; and the fourth sub-shading part has a fourth overlapping area with the first bending part in the orthographic projection of the substrate.

[0029] In a possible implementation, the width of the third overlapping area in the second direction is equal to the width of the fourth overlapping area in the second direction.

[0030] In a possible implementation, the array substrate further includes: a first active layer, and a plurality of first metal lines located on a side of the first active layer facing the substrate; the first active layer includes: a plurality of first active patterns; the second metal line covers at least part of the first active pattern in the orthographic projection of the substrate.

[0031] The third sub-shading part and the fourth sub-shading part are in the same layer as the first metal line and are connected to different sides of the first metal line respectively, and the extension direction of the second shading pattern intersects with the extension direction of the second metal line.

[0032] In a possible implementation, the third sub-shading part and the fourth sub-shading part have a first gap in the second direction between the two first metal lines adjacent in the second direction.

[0033] The first bending part overlaps the first gap in the orthographic projection of the substrate.

[0034] In a possible implementation, the array substrate further includes: a plurality of data lines; the data line includes: a first sub-metal part and a second sub-metal part arranged alternately along a second direction; the extension direction of the first sub-metal part is different from that of the second sub-metal part.

[0035] The first sub-metal part overlaps the area between the two first metal lines adjacent in the second direction in the orthographic projection of the substrate; and the second sub-metal part overlaps the first metal line in the orthographic projection of the substrate.

[0036] In a possible implementation, the array substrate further includes: a plurality of data lines; the data line is multiplexed as the second shading pattern.

[0037] The data line includes: the third sub-shading part and the fourth sub-shading part; the data line further includes: a second bending part extending along the first direction; the third sub-shading part is connected to one side of the second bending part, and the fourth sub-shading part is connected to the other side of the second bending part.

[0038] In a possible implementation, the second bending part has an overlapping area with the first bending part in the orthographic projection of the substrate, and the outer edge of the second bending part along the second direction coincides with the outer edge of the first bending part along the second direction.

[0039] In a possible implementation, the first sub-shading part extends along the second direction, and the second sub-shading part extends along the second direction.

[0040] The third sub-shading part extends along the second direction, and the fourth sub-shading part extends along the second direction, the second direction being perpendicular to the first direction.

[0041] In a possible implementation, the first sub-shading part extends along a third direction, and the second sub-shading part extends along the third direction.

[0042] The third sub-shading part extends along the third direction, and the fourth sub-shading part extends along the third direction; the third direction forms an angle with the first direction, the angle being greater than zero degrees and less than 90 degrees.

[0043] In a possible implementation, the first hollow part extends along a third direction.

[0044] The display panel provided in the embodiments of the present disclosure also includes the array substrate provided in the embodiments of the present disclosure; the display panel further includes a polaroid; an absorption axis of the polaroid is parallel or perpendicular to an outer edge of the first shading pattern.

[0045] The display device provided in the embodiments of the present disclosure also includes the display panel provided in the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0046] FIG. 1A is a schematic diagram of partial film layers of an array substrate provided in the embodiments of the present disclosure;

[0047] FIG. 1B is a schematic diagram of the partial film layers in FIG. 1A;

[0048] FIG. 1C is a schematic diagram of the partial film layers in FIG. 1A;

[0049] FIG. 1D is a schematic diagram of a single film layer of a second shading pattern in FIG. 1A;

[0050] FIG. 1E is a schematic diagram of a single film layer of a first conductive layer in FIG. 1A;

[0051] FIG. 1F is a schematic diagram of a single film layer of a first shading pattern in FIG. 1A;

[0052] FIG. 1G is a schematic diagram of a single film layer of another first shading pattern provided in the embodiments of the present disclosure;

[0053] FIG. 1H is a schematic diagram of a single film layer of another first conductive layer provided in the embodiments of the present disclosure;

[0054] FIG. 2A is a schematic diagram of partial film layers of an array substrate provided in the embodiments of the present disclosure;

[0055] FIG. 2B is a schematic diagram of the partial film layers in FIG. 2A;

[0056] FIG. 2C is a schematic view of a portion of the film layers in FIG. 2A;

[0057] FIG. 2D is a schematic view of a single film layer of the data lines in FIG. 2A;

[0058] FIG. 3A is a schematic view of a portion of the film layers of an array substrate according to an embodiment of the present disclosure;

[0059] FIG. 3B is a schematic view of a portion of the film layers in FIG. 3A;

[0060] FIG. 3C is a schematic view of a portion of the film layers in FIG. 3A;

[0061] FIG. 3D is a schematic view of a single film layer of the second light shielding pattern in FIG. 3A;

[0062] FIG. 3E is a schematic view of a stack of layers in which the data lines and the first metal lines are located according to an embodiment of the present disclosure;

[0063] FIG. 4A is a schematic view of an array substrate according to an embodiment of the present disclosure;

[0064] FIG. 4B is a schematic view of a single film layer of the layer in which the second light shielding pattern in FIG. 4A is located;

[0065] FIG. 4C is a schematic view of a single film layer of the first active layer in FIG. 4A;

[0066] FIG. 4D is a schematic view of a single film layer of the layer in which the gate lines in FIG. 4A are located;

[0067] FIG. 4E is a schematic view of a single film layer of the layer in which the data lines in FIG. 4A are located;

[0068] FIG. 4F is a schematic view of a single film layer of the layer in which the first sub-pixel electrode in FIG. 4A is located;

[0069] FIG. 4G is a schematic view of a single film layer of the layer in which the second sub-pixel electrode in FIG. 4A is located;

[0070] FIG. 4H is a schematic view of a single film layer of the layer in which the first conductive layer in FIG. 4A is located;

[0071] FIG. 4I is a schematic view of a single film layer of the layer in which the first light shielding pattern in FIG. 4A is located;

[0072] FIG. 5A is a schematic view of a cross-section along the line e1 in FIG. 4A;

[0073] FIG. 5B is a schematic view of a cross-section according to an embodiment of the present disclosure;

[0074] FIG. 6 is a schematic view of a common electrode layer and a light shielding layer of a pixel structure according to the related art;

[0075] FIG. 7 is a schematic view of a light efficiency of a pixel structure according to the related art;

[0076] FIG. 8 is a light efficiency diagram of a pixel structure according to an embodiment of the present disclosure;

[0077] FIG. 9 is a voltage-transmittance curve diagram of different pixel structures. DETAILED DESCRIPTION

[0078] Embodiments of the present disclosure will be described in detail below with reference to the drawings. The embodiments can be implemented in various forms. It should be readily understood by those skilled in the art that the embodiments and features thereof can be changed or replaced to one or more embodiments. Therefore, the present disclosure should not be interpreted as being limited to the embodiments described below. The embodiments and features in the present disclosure can be combined with each other if not contrary.

[0079] In the drawings, the size, the thickness or the region of one or more constituent elements can be exaggerated, and the like for clarity. Therefore, one embodiment of the present disclosure should not be interpreted as being limited to the drawings. The shapes and dimensions of the components shown in the drawings can be exaggerated, not to the accurate shape and dimension. In addition, the present disclosure is not limited to shapes or values shown in the drawings.

[0080] In the present specification, ordinal terms such as "first", "second", and "third" are used to avoid confusion among constituent elements, and are not used to constitute a limitation on the number thereof. In the present disclosure, "a plurality of" can include two or more.

[0081] In the present specification, for convenience of explanation, words indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the constituent elements with reference to the drawings, and are used only for convenience of the present specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0082] In the present specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "linking" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements. The above terms in the present disclosure can be understood according to the situation by those skilled in the art.

[0083] In this specification, "electrically connected" includes the case where elements are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as transmission of an electric signal between the elements to be connected is possible. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, another element having one or more functions, and the like.

[0084] In this specification, a transistor means an element including at least three terminals of a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain) and a source electrode (a source electrode terminal, a source region, or a source), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region means a region where current flows mainly.

[0085] In addition, the gate of the transistor can be referred to as a control electrode. The functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other in dependence on the direction in which current flows, the kind of transistor used, or the like. Thus, in this specification, the "source electrode" and the "drain electrode" are interchanged with each other in some cases.

[0086] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus can include a state where an angle formed between two straight lines is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus can include a state where an angle formed between two straight lines is greater than or equal to 85° and less than or equal to 95°.

[0087] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can be an approximately triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, can include some small deformation due to a tolerance, can include a rounded corner, a curved side, and deformation, and the like.

[0088] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0089] "About" and "approximately" in this specification mean that a limit is not strictly defined, and a range of process and measurement error is allowed. In this specification, "about the same" can mean that the difference between the values is within 10 %.

[0090] In the related pixel structure, as shown in FIG. 6, the shape of the opening C0 of the common electrode layer C is limited by the light shielding layer M, which causes the shape of the common electrode layer C to be changed passively, that is, the outer edge of the combined common electrode formed by the combination of the common electrode layer C and the light shielding layer M overlaps the opening C0 of the common electrode layer C, which causes the liquid crystal deflection at the end position of the opening C0 of the common electrode layer C to be disordered, a dark area appears, and the liquid crystal efficiency is low, as shown in FIG. 7.

[0091] Therefore, referring to FIGS. 1A-1F and FIG. 5A, FIG. 1A is a schematic diagram of part of the film layers of the array substrate provided in the embodiment of the present disclosure, FIG. 1B is a schematic diagram of part of the film layers in FIG. 1A, FIG. 1C is a schematic diagram of part of the film layers in FIG. 1A, FIG. 1D is a schematic diagram of a single film layer of the second light shielding pattern in FIG. 1A, FIG. 1E is a schematic diagram of a single film layer of the first conductive layer in FIG. 1A, FIG. 1F is a schematic diagram of a single film layer of the first light shielding pattern in FIG. 1A, and FIG. 5A is a schematic diagram of a cross section of the array substrate provided in the embodiment of the present disclosure, the embodiment of the present disclosure provides an array substrate, which comprises:

[0092] a substrate 1;

[0093] a first conductive layer D1 located on one side of the substrate 1, the first conductive layer D1 has a plurality of first hollows D10; optionally, the first conductive layer D1 can be a common electrode layer; optionally, the first conductive layer D1 can be a transparent electrode layer;

[0094] a plurality of first light shielding patterns M10 in direct contact with the first conductive layer D1; the first light shielding pattern M10 comprises a second hollow M100 extending along the extension direction of the first light shielding pattern M10; the shape of at least one of the plurality of first light shielding patterns M10 is a broken line shape; the orthogonal projection of the second hollow M100 on the substrate 1 overlaps the orthogonal projection of the first hollow D10 on the substrate; the orthogonal projection of the first light shielding pattern M10 on the substrate 1 does not overlap the orthogonal projection of the first hollow D10 on the substrate 1;

[0095] a plurality of second light shielding patterns M20 located at different layers from the first light shielding pattern M10, the orthogonal projection of the second light shielding pattern M20 on the substrate 1 overlaps the orthogonal projection of the second hollow M100 on the substrate 1.

[0096] In the embodiments of the present disclosure, the array substrate includes a plurality of first light shielding patterns M10 in direct contact with the first conductive layer D1. The first light shielding pattern M10 is in a broken line shape and is provided with a second hollow M100 to avoid overlapping with the first hollow D10 at the end position, thereby avoiding the influence of the first light shielding pattern M10 on the electric field distribution of the first conductive layer D1, avoiding liquid crystal deflection disorder at the end position of the first hollow D10, and the occurrence of a dark area, resulting in the problem of low liquid crystal efficiency. Moreover, the array substrate further includes a plurality of second light shielding patterns M20. The orthogonal projection of the second light shielding pattern M20 on the substrate 1 overlaps with the orthogonal projection of the second hollow M100 on the substrate 1, thereby achieving a compensating effect on the light shielding at the position of the second hollow M100 without affecting the electric field distribution of the first conductive layer D1.

[0097] In the embodiments of the present disclosure, the first light shielding pattern M10 is in direct contact with the first conductive layer D1 and can serve as a common electrode together to affect the electric field distribution.

[0098] In a possible implementation, in combination with FIG. 1E, the first hollow D10 can include a first opening D101, a second opening D102 located at one end of the first opening D101, and a third opening D103 located at the other end of the first opening D101. The extension directions of the first opening D101, the second opening D102, and the third opening D103 are all different. In a possible implementation, the extension direction of the first opening D101 can cross the first direction X and the second direction Y. In a possible implementation, the angle formed by the extension direction of the first opening D101 and the first direction X can range from greater than or equal to 20 degrees to less than or equal to 80 degrees. In a possible implementation, the angle formed by the extension direction of the first opening D101 and the first direction X can be 30 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, or 60 degrees.

[0099] In a possible implementation, the extension direction of the second opening D102 can cross the extension direction of the first opening D101. In a possible implementation, the angle formed by the extension direction of the second opening D102 and the extension direction of the first opening D101 can range from greater than or equal to 20 degrees to less than or equal to 80 degrees. In a possible implementation, the angle formed by the extension direction of the second opening D102 and the extension direction of the first opening D101 can be 30 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, or 60 degrees.

[0100] In a possible implementation, the extending direction of the third opening D103 can intersect the extending direction of the first opening D101; in a possible implementation, the extending direction of the third opening D103 can form an angle with the extending direction of the first opening D101, and the angle can range from greater than or equal to 110 degrees to less than or equal to 180 degrees. In a possible implementation, the extending direction of the third opening D103 can form an angle of 120 degrees, 130 degrees, 140 degrees, 145 degrees, 150 degrees, 155 degrees, or 160 degrees with the extending direction of the first opening D101.

[0101] In a possible implementation, the partial area of the third opening D103 and the partial area of the second opening D102 can be located on different sides of the extended area of the first opening D101, respectively, that is, for example, as shown in FIG. 1E, the partial area of the second opening D102 can be located on the right side of the extended area of the first opening D101, and the partial area of the third opening D103 can be located on the left side of the extended area of the first opening D101.

[0102] In a possible implementation, in combination with FIGS. 1A and 1E, the first hollow D10 can be a structure, and in a sub-pixel, the first hollow D10 has only one slit; in another possible implementation, in combination with FIG. 1H, the first hollow D10 can also be a combined structure including multiple slits S0, that is, in a sub-pixel, one first hollow D10 is provided, but the first hollow D10 is a combined structure including multiple slits S0.

[0103] In a possible implementation, the first light-shielding pattern M10 can shield light of an adjacent pixel to inhibit the occurrence of color mixing, and in addition, the first light-shielding pattern M10 can also be reused as an auxiliary electrode, and the resistance of the auxiliary electrode is lower than that of the first conductive layer D1; in a possible implementation, the material of the first light-shielding pattern M10 can be metal.

[0104] In a possible implementation, in combination with FIGS. 1A, 1B, and 1F, the first light-shielding pattern M10 includes a first bending portion M13, a first sub-light-shielding portion M11 located on one side of the first bending portion M13, and a second sub-light-shielding portion M12 located on the other side of the first bending portion M13.

[0105] The region between the edge of the first sub-shading portion M11 close to the second sub-shading portion M12 and the extension line S1 of the edge of the second sub-shading portion M12 away from the first sub-shading portion M11 is a first sub-hollow portion M101; the region between the edge of the second sub-shading portion M12 close to the first sub-shading portion M11 and the extension line S2 of the edge of the first sub-shading portion M11 away from the second sub-shading portion M12 is a second sub-hollow portion M102. That is, the region between the edge of the first sub-shading portion M11 close to the second sub-shading portion M12 and the extension line S1 of the edge of the second sub-shading portion M12 away from the first sub-shading portion M11 constitutes the region of the first sub-hollow portion M101 in the first direction X, wherein the edge of the first sub-shading portion M11 close to the second sub-shading portion M12 (such as the left edge of the first sub-shading portion M11 in FIG. 1A) and the extension line S1 of the edge of the second sub-shading portion M12 away from the first sub-shading portion M11 (such as the left edge of the second sub-shading portion M12 in FIG. 1A) can be regarded as the two side edges of the first sub-hollow portion M101 in the second direction Y; similarly, the region between the edge of the second sub-shading portion M12 close to the first sub-shading portion M11 and the extension line S2 of the edge of the first sub-shading portion M11 away from the second sub-shading portion M12 constitutes the region of the second sub-hollow portion M102 in the first direction X, wherein the edge of the second sub-shading portion M12 close to the first sub-shading portion M11 (such as the right edge of the second sub-shading portion M12 in FIG. 1A) and the extension line S2 of the edge of the first sub-shading portion M11 away from the second sub-shading portion M12 (such as the right edge of the first sub-shading portion M11 in FIG. 1A) can be regarded as the two side edges of the second sub-hollow portion M102 in the second direction Y; the second hollow M100 can include the first sub-hollow portion M101 and the second sub-hollow portion M102.

[0106] In a possible implementation, referring to FIG. 1F, the region between the outer edge of the first bending portion M13 toward the first sub-shading portion M11 and the extension line of the outer edge of the first sub-shading portion M11 away from the first bending portion M13 is the first sub-hollow portion M101; the region between the outer edge of the first bending portion M13 toward the second sub-shading portion M12 and the extension line of the outer edge of the second sub-shading portion M12 away from the first bending portion M13 is the second sub-hollow portion M102. That is, in combination with FIG. 1A and FIG. 1F, the region between the outer edge of the first bending portion M13 toward the first sub-shading portion M11 (such as the upper edge of the first bending portion M13 in FIG. 1A) and the extension line of the outer edge of the first sub-shading portion M11 away from the first bending portion M13 (such as the upper edge of the first sub-shading portion M11 in FIG. 1A) constitutes the region of the first sub-hollow portion M101 in the second direction Y, and the outer edge of the first bending portion M13 toward the first sub-shading portion M11 (such as the upper edge of the first bending portion M13 in FIG. 1A) and the extension line of the outer edge of the first sub-shading portion M11 away from the first bending portion M13 (such as the upper edge of the first sub-shading portion M11 in FIG. 1A) can serve as the two side edges of the first sub-hollow portion M101 in the first direction X; similarly, the region between the outer edge of the first bending portion M13 toward the second sub-shading portion M12 (such as the lower edge of the first bending portion M13 in FIG. 1A) and the extension line of the outer edge of the second sub-shading portion M12 away from the first bending portion M13 (such as the lower edge of the second sub-shading portion M12 in FIG. 1A) constitutes the region of the second sub-hollow portion M102 in the second direction Y, and the outer edge of the first bending portion M13 toward the second sub-shading portion M12 (such as the lower edge of the first bending portion M13 in FIG. 1A) and the extension line of the outer edge of the second sub-shading portion M12 away from the first bending portion M13 (such as the lower edge of the second sub-shading portion M12 in FIG. 1A) can serve as the two side edges of the second sub-hollow portion M102 in the first direction X.

[0107] In a possible implementation, as shown in FIG. 1A, FIG. 1B, and FIG. 1F, the first sub-hollow portion M101 overlaps the nth first hollow D10 in the mth row in the orthographic projection of the substrate 1, and the second sub-hollow portion M102 overlaps the (n+1)th first hollow D10 in the mth row in the orthographic projection of the substrate 1, where m is a positive integer, and n is a positive integer; the first hollow D10 is a slit, one end of the first hollow D10 overlaps the first sub-hollow portion M101 in the orthographic projection of the substrate 1, and the other end of the first hollow D10 overlaps the second sub-hollow portion M102 of the adjacent first light-shielding pattern M10 in the orthographic projection of the substrate 1. For example, as shown in FIG. 1A, for the first hollow D10 in the first row and the second column, the upper right end thereof overlaps the first sub-hollow portion M101 on the right side thereof, and the lower left end thereof overlaps the second sub-hollow portion M102 on the left side thereof.

[0108] In a possible implementation, as shown in FIG. 1A-FIG. 1F, the first light-shielding pattern M10 can be a structure extending along the second direction Y as a whole but having a bend locally; in a possible implementation, as shown in FIG. 1F, the same first light-shielding pattern M10 extending along the second direction Y can be a structure connected integrally; in another possible implementation, as shown in FIG. 1G, the same first light-shielding pattern M10 extending along the second direction Y can also be a structure disconnected from each other.

[0109] In a possible implementation, as shown in FIG. 1A, the first hollow D10 is a slit, and the first bend portion M13 passes through the center region O of the first hollow D10 in the extension direction. The extension E can be a virtual extension of the first bend portion M13 in the extension direction.

[0110] In a possible implementation, as shown in FIG. 1C, the first sub-light-shielding portion M11 overlaps the orthographic projection of the adjacent first hollow D10 in the orthographic projection of the substrate 1 in parallel to the edge extension line f1 in the extension direction, and / or the second sub-light-shielding portion M12 overlaps the orthographic projection of the other adjacent first hollow D10 in the orthographic projection of the substrate 1 in parallel to the edge extension line f2 in the extension direction. For example, as shown in FIG. 1C, in the first light-shielding pattern M10 in the second column, the first sub-light-shielding portion M11 overlaps the orthographic projection of the adjacent first hollow D10 on the right side thereof in the orthographic projection of the substrate 1 in parallel to the edge extension line f1 in the extension direction, and the second sub-light-shielding portion M12 overlaps the orthographic projection of the adjacent first hollow D10 on the left side thereof in the orthographic projection of the substrate 1 in parallel to the edge extension line f2 in the extension direction.

[0111] In a possible implementation, as shown in FIG. 1F, the extending direction of the first bending portion M13 is perpendicular to the extending direction of the first sub-shading portion M11 and / or the second sub-shading portion M12. In the embodiment of the present disclosure, the extending direction of the first bending portion M13 is perpendicular to the extending direction of the first sub-shading portion M11 and / or the second sub-shading portion M12, that is, the corner position of the first bending portion M13 and the first sub-shading portion M11 and / or the second sub-shading portion M12 should be designed as a right angle, which can reduce the influence of metal round corner de-biasing light leakage on the contrast of the display panel.

[0112] In a possible implementation, as shown in FIG. 1B, the array substrate has a plurality of pixel light-transmitting region rows P100 extending along a first direction X and arranged along a second direction Y; the pixel light-transmitting region row P100 includes a plurality of pixel light-transmitting regions P10 arranged along the first direction X; the pixel light-transmitting region P10 includes a first outer boundary w1 and a second outer boundary w2; the first outer boundary w1 extends along the first direction X, and the second outer boundary w2 intersects the first outer boundary w1; the second direction Y intersects the first direction X; the combination of the orthogonal projection of the first shading pattern M10 on the substrate 1 and the orthogonal projection of the second shading pattern M20 on the substrate 1 constitutes the second outer boundary w2 of the pixel light-transmitting region P100. In the embodiment of the present disclosure, the combination of the orthogonal projection of the first shading pattern M10 on the substrate 1 and the orthogonal projection of the second shading pattern M20 on the substrate 1 constitutes the second outer boundary w2 of the pixel light-transmitting region P100, thereby realizing shading at the pixel peripheral position.

[0113] In a possible implementation, as shown in FIGS. 1A-1D, the plurality of second shading patterns M20 includes a plurality of third sub-shading portions M21 and a plurality of fourth sub-shading portions M22; the third sub-shading portions M21 and the fourth sub-shading portions M22 are alternately arranged along the second direction Y; the orthogonal projection of the third sub-shading portion M21 on the substrate 1 overlaps the orthogonal projection of the first sub-hollow portion M101 on the substrate 1; the orthogonal projection of the fourth sub-shading portion M22 on the substrate 1 overlaps the orthogonal projection of the second sub-hollow portion M102 on the substrate 1. Optionally, the orthogonal projection of the third sub-shading portion M21 on the substrate 1 and the orthogonal projection of the first sub-shading portion M11 on the substrate 1 are located on the same side of the orthogonal projection of the first bending portion M13 on the substrate 1; the orthogonal projection of the fourth sub-shading portion M21 on the substrate 1 and the orthogonal projection of the second sub-shading portion M12 on the substrate 1 are located on the same side of the orthogonal projection of the first bending portion M13 on the substrate 1. For example, as shown in FIG. 1B, the third sub-shading portion M21 and the first sub-shading portion M11 are both located on the upper side of the first bending portion M13; the fourth sub-shading portion M21 and the second sub-shading portion M12 are both located on the lower side of the first bending portion M13.

[0114] In a possible implementation, as shown in FIGS. 1A-1D, the third light-shield part M21 coincides with the outer edge of the second light-shield part M12 parallel to the extending direction (for example, the outer edge of the second light-shield part M12 extending along the second direction Y) and the partial outer edge of the first bent part M13 (for example, the outer edge of the first bent part M13 extending along the second direction Y); the combination of the outer edge S3 of the third light-shield part M21 parallel to the extending direction, the outer edge of the second light-shield part M12 (for example, the outer edge of the second light-shield part M12 extending along the second direction Y), and the partial outer edge of the first bent part M13 (for example, the outer edge of the first bent part M13 extending along the second direction Y) constitutes a second outer boundary w2 of a pixel light-transmissive region P10.

[0115] The fourth light-shield part M22 coincides with the outer edge of the first light-shield part M11 parallel to the extending direction (for example, the outer edge of the first light-shield part M11 extending along the second direction Y) and the partial outer edge of the first bent part M13 (for example, the outer edge of the first bent part M13 extending along the second direction Y); the combination of the outer edge of the fourth light-shield part M22 parallel to the extending direction, the outer edge of the first light-shield part M11 (for example, the outer edge of the first light-shield part M11 extending along the second direction Y), and the partial outer edge of the first bent part M13 (for example, the outer edge of the first bent part M13 extending along the second direction Y) constitutes a second outer boundary w2 of another pixel light-transmissive region P10.

[0116] In a possible implementation, as shown in FIGS. 1A-1D, the third light-shield part M21, the fourth light-shield part M22 adjacent in the second direction Y are distributed in a staggered manner. In this way, the first light-shield pattern M10 is complemented with each other to achieve light shielding for the pixel peripheral position.

[0117] In a possible implementation, as shown in FIG. 1B, the third light-shield part M21 has a first overlapping area Z1 with the first light-shield part M11 in the orthographic projection of the substrate 1; the fourth light-shield part M22 has a second overlapping area Z2 with the second light-shield part M12 in the orthographic projection of the substrate 1.

[0118] In a possible implementation, as shown in FIG. 1B, the width of the first overlapping area Z1 in the first direction X is equal to the width of the second overlapping area Z2 in the first direction X. The width L3 of the first overlapping area Z1 in the first direction X satisfies the following relationship:

[0119] wherein OVL represents the alignment deviation between the layer where the first light-shield part M11 is located and the layer where the second light-shield part M12 is located, and Tol represents the tolerance of the alignment deviation.CM represents the process dimension deviation value of the pattern on the layer where the first sub-shading portion M11 is located. Thus, in the case of including process errors, it can still be guaranteed that the layer where the first sub-shading portion M11 is located and the layer where the second sub-shading portion M12 is located form a complementary shading effect. LS represents the process dimension deviation value of the pattern on the layer where the third sub-shading portion M21 is located. Thus, in the case of including process errors, it can still be guaranteed that the layer where the first sub-shading portion M11 is located and the layer where the second sub-shading portion M12 is located form a complementary shading effect.

[0120] In a possible implementation, as shown in FIG. 1B, the third sub-shading portion M21 has a third overlapping area Z3 with the first bending portion M13 in the orthographic projection of the substrate 1; and the fourth sub-shading portion M22 has a fourth overlapping area Z4 with the first bending portion M13 in the orthographic projection of the substrate 1.

[0121] In a possible implementation, as shown in FIG. 1B, the third overlapping area Z3 has a width in the second direction Y equal to the width of the fourth overlapping area Z4 in the second direction Y. The width L4 of the third overlapping area in the second direction satisfies the following relationship:

[0122] Thus, in the case of including process errors, it can still be guaranteed that the layer where the first sub-shading portion M11 is located and the layer where the second sub-shading portion M12 are located form a complementary shading effect.

[0123] In a specific implementation, the second light-shielding pattern M20 can be made using the existing film layers of the array substrate to simplify the manufacturing process of the display panel. For example, in one possible implementation, in combination with FIGS. 4A-4I and FIG. 5A, FIG. 4A is a top view of an array substrate according to an embodiment of the present disclosure, FIG. 4B is a schematic view of a single film layer of a layer on which the second light-shielding pattern is located in FIG. 4A, FIG. 4C is a schematic view of a single film layer of a layer on which the first active layer is located in FIG. 4A, FIG. 4D is a schematic view of a single film layer of a layer on which the gate line is located in FIG. 4A, FIG. 4E is a schematic view of a single film layer of a layer on which the data line is located in FIG. 4A, FIG. 4F is a schematic view of a single film layer of a layer on which the first sub-pixel electrode is located in FIG. 4A, FIG. 4G is a schematic view of a single film layer of a layer on which the second sub-pixel electrode is located in FIG. 4A, FIG. 4H is a schematic view of a single film layer of a layer on which the first conductive layer is located in FIG. 4A, and FIG. 4I is a schematic view of a single film layer of a layer on which the first light-shielding pattern is located in FIG. 4A. The array substrate further includes: a first active layer 2, and a plurality of first metal lines 3 located on a side of the first active layer 2 facing the substrate 1; the first active layer 2 includes: a plurality of first active patterns 20; a projection of the first metal lines 3 on the substrate 1 covers at least part of a projection of the first active patterns 20 on the substrate 1; the third sub-light-shielding portion M21 and the fourth sub-light-shielding portion M22 are in the same layer as the first metal lines 3 and are connected to different sides of the first metal lines 3, respectively; and an extension direction of the second light-shielding pattern M20 intersects an extension direction of the first metal lines 3. In the present embodiment, the third sub-light-shielding portion M21 and the fourth sub-light-shielding portion M22 are in the same layer and of the same material as the first metal lines 3 for shielding the first active patterns 20, so that the second light-shielding pattern M20 (including the third sub-light-shielding portion M21 and the fourth sub-light-shielding portion M22) complementary to the first light-shielding pattern M10 can be formed at the same time as the first metal lines 3 for shielding the first active patterns 20, thereby simplifying the manufacturing process of the display panel while achieving the light-shielding effect.

[0124] In one possible implementation, in combination with FIGS. 1B and 1D, the third sub-light-shielding portion M21 and the fourth sub-light-shielding portion M22 have a first gap J1 in the second direction Y between the regions between two adjacent first metal lines 3 in the second direction Y; and a projection of the first bending portion M13 on the substrate 1 overlaps a projection of the first gap J1 on the substrate 1.

[0125] In one possible implementation, in combination with FIGS. 1B and 1D, an outer boundary of the first metal lines 3 extending in the first direction X can constitute a first outer boundary w1 of the pixel region P10.

[0126] In a possible implementation, as shown in FIGS. 2A-2D, the array substrate further includes: a plurality of data lines 5; the data lines 5 are multiplexed as the second light-shielding pattern M20; the data lines 5 include: a third sub-light-shielding portion M21 and a fourth sub-light-shielding portion M22; the data lines 5 further include: a second bending portion 50 extending along the first direction X; the third sub-light-shielding portion M21 is connected to one side of the second bending portion 50, and the fourth sub-light-shielding portion M22 is connected to the other side of the second bending portion 50. In the embodiment, the data lines 5 are multiplexed as the second light-shielding pattern M20 (including the third sub-light-shielding portion M21 and the fourth sub-light-shielding portion M22), so that the second light-shielding pattern M20 (including the third sub-light-shielding portion M21 and the fourth sub-light-shielding portion M22) complementary to the first light-shielding pattern M10 is formed at the same time when the data lines 5 are formed, thereby simplifying the manufacturing process of the display panel while achieving the light-shielding effect. In addition, in the embodiment, the data lines 5 include the second bending portion 50 in addition to the third sub-light-shielding portion M21 and the fourth sub-light-shielding portion M22, so as to realize the connection of the data lines 5 in different pixel row regions.

[0127] In a possible implementation, as shown in FIGS. 2A-2D, the second bending portion 50 has an overlapping area with the first bending portion M13 in the orthographic projection of the substrate 1, and the outer edge of the second bending portion 50 along the second direction Y coincides with the outer edge of the first bending portion M13 along the second direction Y.

[0128] In a possible implementation, as shown in FIGS. 1A-1C and 2A-2D, the first sub-light-shielding portion M11 extends along the second direction Y, and the second sub-light-shielding portion M12 extends along the second direction Y; the third sub-light-shielding portion M21 extends along the second direction Y, and the fourth sub-light-shielding portion M22 extends along the second direction Y; the second direction Y is perpendicular to the first direction X.

[0129] In a possible implementation, as shown in FIGS. 3A-3D, FIG. 3A is a schematic view of a part of film layers of an array substrate according to an embodiment of the present disclosure, FIG. 3B is a schematic view of a part of the film layers in FIG. 3A, FIG. 3C is a schematic view of a part of the film layers in FIG. 3A, and FIG. 3D is a schematic view of a single film layer of a layer in which the second light shielding pattern is located in FIG. 3A. The first sub-light shielding portion M11 extends along the third direction Z, and the second sub-light shielding portion M12 extends along the third direction Z. The third sub-light shielding portion M21 extends along the third direction Z, and the fourth sub-light shielding portion M22 extends along the third direction Z. An included angle between the third direction Z and the first direction X is greater than 0 degrees and less than 90 degrees. In the embodiment of the present disclosure, the first light shielding pattern M10 and the second light shielding pattern M20 can also be arranged obliquely. Correspondingly, in the embodiment of the present disclosure, the first light shielding pattern M10 and the second light shielding pattern M20 can also be arranged to be obliquely complementary.

[0130] In a possible implementation, an included angle between the third direction Z and the first direction X is greater than or equal to 30 degrees and less than or equal to 60 degrees. In a possible implementation, the included angle between the third direction Z and the first direction X is 30 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, or 60 degrees.

[0131] In a possible implementation, as shown in FIGS. 3A-3E, the first hollow portion D10 extends along the third direction Z.

[0132] In a possible implementation, when the upper and lower pixel units are staggered by a certain interval in the first direction X, the data line will be bent accordingly, and then the second light shielding pattern M20 is inclined. That is, for the third sub-light shielding portion M21 extending along the third direction Z and the fourth sub-light shielding portion M22 extending along the third direction Z shown in FIGS. 3A-3D, as shown in FIG. 3E, the array substrate further includes: a plurality of data lines 5; the data line 5 includes: a first sub-metal portion M1a and a second sub-metal portion M1b arranged alternately along the second direction Y; the extension directions of the first sub-metal portion M1a and the second sub-metal portion M1b are different; the orthogonal projection of the first sub-metal portion M1a on the substrate 1 overlaps the area between the adjacent two first metal lines 3 in the orthogonal projection of the substrate 1 in the second direction Y; and the orthogonal projection of the second sub-metal portion M1b on the substrate 1 overlaps the orthogonal projection of the first metal line 3 on the substrate 1.

[0133] In a possible implementation, as shown in FIG. 3E, the orthogonal projection of the first sub-metal portion M1a on the substrate 1 overlaps the orthogonal projection of the third sub-light shielding portion M21 on the substrate 1 and the orthogonal projection of the fourth sub-light shielding portion M22 on the substrate 1.

[0134] In a possible implementation, as shown in FIG. 3E, the first sub-metal portion M1a can extend along a third direction Z; the second sub-metal portion M1b can extend along a fourth direction R; in a possible implementation, the fourth direction R forms an angle with the first direction X, and the angle is greater than or equal to 20 degrees and less than or equal to 80 degrees. In a possible implementation, the third direction Z forms an angle with the first direction X, and the angle is 30 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, or 60 degrees.

[0135] In a possible implementation, the distance between the two ends of the first sub-metal portion M1a in the first direction X can be equal to the distance between the two ends of the second sub-metal portion M1b in the first direction X; that is, the offset difference of the first sub-metal portion M1a in the first direction X can be equal to the offset difference of the second sub-metal portion M1b in the first direction X, so as to realize that the data line 5 as a whole extends along the second direction Y.

[0136] In a possible implementation, as shown in FIGS. 4A-4I and FIG. 5A, the array substrate can include: a gate line 4 located on the side of the first active layer 2 away from the substrate 1, a data line 5 located on the side of the gate line 4 away from the substrate 1, a first sub-pixel electrode 61 located on the side of the data line 5 away from the substrate 1, and a second sub-pixel electrode 62 located on the side of the first sub-pixel electrode 61 away from the substrate 1; a first conductive layer D1 can be located on the side of the second sub-pixel electrode 62 away from the substrate 1; the first sub-pixel electrode 61 and the second sub-pixel electrode 62 can be in direct contact and together serve as a pixel electrode; one end of the first active pattern 20 can be electrically connected to the data line 5 through a first via K1; the other end of the first active pattern 20 can be electrically connected to the first sub-pixel electrode 61 through a second via K2 and a third via K3.

[0137] In a possible implementation, as shown in FIGS. 4A-4I and FIG. 5A, the display panel can further include at least one of the following:

[0138] a buffer layer 91 located between the layer where the first metal line 3 is located and the first active layer 2;

[0139] a gate insulating layer 92 located between the first active layer 2 and the layer where the gate line 4 is located;

[0140] an interlayer dielectric layer 93 located between the layer where the gate line 4 is located and the layer where the data line 5 is located;

[0141] a first planarization layer 94 located between the data line 5 and the layer where the first sub-pixel electrode 61 is located;

[0142] a second planarization layer 96 located between the first sub-pixel electrode 61 and the second sub-pixel electrode 61;

[0143] The passivation layer 95 is located between the second sub-pixel electrode 61 and the first conductive layer D1.

[0144] The spacer 7 is located one layer away from the first conductive layer D1 in the direction of the first metal pattern M10.

[0145] In some examples, at least one of the buffer layer 91, the gate insulating layer 92, the interlayer dielectric layer 93, the first planarization layer 94, the second planarization layer 96, and the passivation layer 95 can be an inorganic insulating layer, for example, can adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer.

[0146] The first via K1 can pass through the gate insulating layer 92 and the interlayer dielectric layer 93; the second via K2 can pass through the gate insulating layer 92 and the interlayer dielectric layer 93; the third via K3 can pass through the first planarization layer 94; and the second planarization layer 96 can fill the second via K2 and the third via K3 between the first sub-pixel electrode 61 and the second sub-pixel electrode 62.

[0147] In a possible implementation, referring to FIG. 5B, the display panel can further include a transfer electrode 63 located between the layer where the data line 5 is located and the first sub-pixel electrode 61; optionally, the display panel can further include a third planarization layer 97 between the layer where the data line 5 is located and the transfer electrode 63; optionally, the transfer electrode 63 can be electrically connected to the first active pattern 20 through a fourth via K4 passing through the third planarization layer 97, the interlayer dielectric layer 93, and the gate insulating layer 92; and the first sub-pixel electrode 61 is electrically connected to the first active pattern 20 through the transfer electrode 63.

[0148] In a possible implementation, each first sub-pixel electrode 61 can correspond to one transfer electrode 63, the projection of the transfer electrode 63 on the substrate 1 can overlap the projection of the first sub-pixel electrode 61 on the substrate 1, and the projection of the transfer electrode 63 on the substrate 1 can overlap the projection of the first active pattern 20 on the substrate 1, so as to realize the perforated electrical connection at the overlapping position.

[0149] In a possible implementation, the projection of the transfer electrode 63 on the substrate 1 can overlap the projection of the first metal line 3 on the substrate 1; in a possible implementation, the projection of the transfer electrode 63 on the substrate 1 can be located in the region between the projections of adjacent two data lines 5 on the substrate 1.

[0150] In a possible implementation, the material of the transfer electrode 63 can include metal oxides (for example, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide.

[0151] In a possible implementation, the material of the transfer electrode 63 can be the same as that of the first sub-pixel electrode 61.

[0152] In a possible implementation, the material of the first active layer is a metal oxide semiconductor material, which can include any one or more of indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare earth element-doped metal oxide (RE-OS), where the rare earth element-doped metal oxide can include lanthanide-doped metal oxide (Ln-OS); and the crystalline state of the first active layer material can be amorphous, partially crystalline, or polycrystalline. In the embodiments of the present disclosure, the first active layer of the display area transistor can be an oxide active layer, and the thin film transistor of the oxide active layer has the advantage of low leakage current.

[0153] In a possible implementation, the material of the first conductive layer D1 can include a metal oxide (for example, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide.

[0154] In a possible implementation, the material of the first sub-pixel electrode 61 can include a metal oxide (for example, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide.

[0155] In a possible implementation, the material of the second sub-pixel electrode 62 can include a metal oxide (for example, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide.

[0156] In a possible implementation, the materials of at least two of the first conductive layer D1, the first sub-pixel electrode 61, and the second sub-pixel electrode 62 are the same. In a possible implementation, the materials of the first conductive layer D1, the second conductive layer D2, and the third conductive layer D3 can also be different from each other.

[0157] In a possible implementation, the material of at least one of the first metal line 3, the first light-shielding pattern M10, the second light-shielding pattern M20, the gate line 4, and the data line 5 can include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti.

[0158] In a possible implementation, materials of at least two of the first metal line 3, the first light-shielding pattern M10, the second light-shielding pattern M20, the gate line 4, and the data line 5 are the same. In a possible implementation, materials of the first metal line 3, the first light-shielding pattern M10, the second light-shielding pattern M20, the gate line 4, and the data line 5 can also be different from each other.

[0159] Based on the same inventive concept, the embodiment of the present disclosure further provides a display panel, which comprises the array substrate provided by the embodiment of the present disclosure.

[0160] In a possible implementation, the display panel further comprises a polarizer, and an absorption axis of the polarizer is parallel or perpendicular to an outer edge of the first light-shielding pattern. In this way, the influence of metal depolarization light leakage on the contrast of the display panel is reduced. As the resolution of the VR display product is higher and higher, the pixel is smaller and smaller, and the light efficiency and contrast are also declining. To solve the problem of contrast, the absorption axis of the polarizer is generally designed to be parallel or perpendicular to the outer edge of the first light-shielding pattern, and an angle is required between the first hollow D10 of the first conductive layer D1 and the first light-shielding pattern, which causes the opening shape of the first conductive layer D1 to be affected by the first light-shielding pattern, and the liquid crystal efficiency is low. However, in the embodiment of the present disclosure, the special-shaped second light-shielding pattern M20 and the special-shaped first light-shielding pattern M10 are complementary structures, which can ensure that the shape of the common electrode is consistent with the shape of the first conductive layer D1, and also ensure the light-shielding width.

[0161] In combination with FIG. 7, FIG. 8, and FIG. 9, wherein FIG. 7 is a light efficiency schematic diagram of a pixel structure of the related art, FIG. 8 is a light efficiency schematic diagram of a pixel structure provided by the embodiment of the present disclosure, and FIG. 9 is a voltage-transmittance curve schematic diagram of different pixel structures. In the embodiment of the present disclosure, the special-shaped second light-shielding pattern M20 and the special-shaped first light-shielding pattern M10 are complementary structures, which can ensure that the shape of the common electrode is consistent with the shape of the first conductive layer D1, and also ensure the light-shielding width. As can be known from FIG. 7 and FIG. 8, the pixel structure provided by the embodiment of the present disclosure has fewer pixel dark areas and higher liquid crystal efficiency in the liquid crystal driving state. The voltage-transmittance curves corresponding to the pixel structure of the related art and the pixel structure provided by the embodiment of the present disclosure are shown in FIG. 9, wherein in FIG. 9, S1 represents the voltage-transmittance curve corresponding to the pixel structure provided by the embodiment of the present disclosure, and S2 represents the voltage-transmittance curve corresponding to the pixel structure of the related art. As can be known from FIG. 9, in the case of the same aperture ratio, the transmittance of the pixel structure provided by the embodiment of the present disclosure is higher than the transmittance of the pixel structure of the related art.

[0162] Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, which comprises the display panel provided by the embodiment of the present disclosure.

[0163] While the preferred embodiments of the application have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they have the benefit of the present disclosure without departing from the spirit and scope of the application. Accordingly, it is intended that the appended claims include all such modifications and variations as fall within the scope of the present application.

[0164] It is apparent that those skilled in the art can make various changes and modifications to the embodiments of the application without departing from the spirit and scope of the application. Thus, it is intended that the present application include all such modifications and alterations insofar as they come within the scope of the appended claims and their equivalents.

Claims

1. An array substrate, wherein, include: Substrate; A first conductive layer is located on one side of the substrate, and the first conductive layer has a plurality of first cutouts; Multiple first light-shielding patterns are in direct contact with the first conductive layer; The first light-shielding pattern includes: a second cutout extending along the extension direction of the first light-shielding pattern; the orthographic projection of the second cutout on the substrate overlaps with the orthographic projection of the first cutout on the substrate; Multiple second light-shielding patterns are located on different layers from the first light-shielding pattern, and the orthographic projection of the second light-shielding pattern on the substrate overlaps with the orthographic projection of the second cutout on the substrate.

2. The array substrate as claimed in claim 1, wherein, The first light-shielding pattern includes: a first bend, a first sub-light-shielding portion located on one side of the first bend, and a second sub-light-shielding portion located on the other side of the first bend; The area between the edge of the first sub-shading part near the second sub-shading part and the extension line of the edge of the second sub-shading part away from the first sub-shading part is the first sub-hollowed-out part; The area between the edge of the second sub-shading part near the first sub-shading part and the extension line of the edge of the first sub-shading part away from the second sub-shading part is the second sub-hollowed-out part.

3. The array substrate as described in claim 2, wherein, The area between the outer edge of the first bent portion facing the first sub-shielding portion and the extended line of the outer edge of the first sub-shielding portion away from the first bent portion is the first sub-hollow portion; The area between the outer edge of the first bent portion facing the second sub-shading portion and the extended line of the outer edge of the second sub-shading portion away from the first bent portion is the second sub-hollowed-out portion.

4. The array substrate as described in claim 2 or 3, wherein, The orthographic projection of the first sub-cutout on the substrate overlaps with the orthographic projection of the nth first cutout in the mth row on the substrate; The orthographic projection of the second sub-cutout on the substrate overlaps with the orthographic projection of the (n+1)th first cutout in the m-th row on the substrate, where m is a positive integer and n is a positive integer; The orthographic projection of one end of the first cutout on the substrate overlaps with the orthographic projection of the first sub-cutout on the substrate; the orthographic projection of the other end of the first cutout on the substrate overlaps with the orthographic projection of the second sub-cutout of the adjacent first light-shielding pattern on the substrate.

5. The array substrate according to any one of claims 2-4, wherein, The first cutout is a slit; the extension of the first bent portion in the extending direction passes through the central region of the first cutout.

6. The array substrate according to any one of claims 2-5, wherein, The orthographic projection of the edge extension line of the first sub-shielding portion parallel to the extension direction on the substrate overlaps with the orthographic projection of an adjacent first cutout on the substrate, and / or, the orthographic projection of the edge extension line of the second sub-shielding portion parallel to the extension direction on the substrate overlaps with the orthographic projection of another adjacent first cutout on the substrate.

7. The array substrate as claimed in claim 5 or 6, wherein, The extension direction of the first bent portion is perpendicular to the extension direction of the first sub-shading portion and / or the second sub-shading portion.

8. The array substrate according to any one of claims 2-7, wherein, The array substrate has multiple rows of pixel light-transmitting areas extending along a first direction and arranged along a second direction; The row of light-transmitting pixel areas includes: a plurality of light-transmitting pixel areas arranged along the first direction; each light-transmitting pixel area includes: a first outer boundary and a second outer boundary; the first outer boundary extends along the first direction, and the second outer boundary intersects with the first outer boundary; the second direction intersects with the first direction; The orthographic projection of the first light-blocking pattern onto the substrate, and the combination of the orthographic projection of the second light-blocking pattern onto the substrate, constitute the second outer boundary of the pixel light-transmitting area.

9. The array substrate according to any one of claims 1-8, wherein, The plurality of second light-shielding patterns include: a plurality of third sub-light-shielding parts and a plurality of fourth sub-light-shielding parts; the third sub-light-shielding parts and the fourth sub-light-shielding parts are arranged alternately along the second direction; The orthographic projection of the third sub-shielding part on the substrate overlaps with the orthographic projection of the first sub-cutout part on the substrate; the orthographic projection of the fourth sub-shielding part on the substrate overlaps with the orthographic projection of the second sub-cutout part on the substrate.

10. The array substrate as claimed in claim 9, wherein, The outer edge extension line of the third light-shielding part parallel to the extension direction coincides with the outer edge of the second sub-light-shielding part parallel to the extension direction and a portion of the outer edge of the first bending part. The combination of the outer edge of the third light-shielding part parallel to the extension direction, the outer edge of the second sub-light-shielding part, and the portion of the outer edge of the first bending part constitutes the second outer boundary of the pixel light-transmitting area. The fourth light-shielding part extends parallel to the outer edge of the extending direction, coincides with the outer edge of the first sub-light-shielding part, and a portion of the outer edge of the first bending part. The combination of the outer edge of the fourth light-shielding part extending parallel to the extending direction, the outer edge of the first sub-light-shielding part, and a portion of the outer edge of the first bending part constitutes the second outer boundary of another pixel light-transmitting area.

11. The array substrate as claimed in claim 9 or 10, wherein, The third and fourth sub-shading parts adjacent to each other in the second direction are staggered.

12. The array substrate according to any one of claims 9-11, wherein, The orthographic projection of the third sub-shielding part onto the substrate has a first overlapping area with the orthographic projection of the first sub-shielding part onto the substrate. The orthographic projection of the fourth sub-shielding part onto the substrate has a second overlapping area with the orthographic projection of the second sub-shielding part onto the substrate.

13. The array substrate as claimed in claim 12, wherein, The width of the first overlapping region in the first direction is equal to the width of the second overlapping region in the first direction.

14. The array substrate according to any one of claims 9-13, wherein, The orthographic projection of the third sub-shielding part on the substrate has a third overlapping area with the orthographic projection of the first bending part on the substrate; the orthographic projection of the fourth sub-shielding part on the substrate has a fourth overlapping area with the orthographic projection of the first bending part on the substrate.

15. The array substrate as claimed in claim 14, wherein, The width of the third overlapping region in the second direction is equal to the width of the fourth overlapping region in the second direction.

16. The array substrate according to any one of claims 9-15, wherein, The array substrate further includes: a first active layer, and a plurality of first metal lines located on the side of the first active layer facing the substrate; the first active layer includes: a plurality of first active patterns; the orthographic projection of the second metal lines on the substrate covers at least a portion of the orthographic projection of the first active patterns on the substrate; The third sub-shielding part and the fourth sub-shielding part are on the same layer as the first metal line and are respectively connected to different sides of the first metal line. The extension direction of the second shielding pattern intersects with the extension direction of the second metal line.

17. The array substrate as claimed in claim 16, wherein, The region between two adjacent first metal lines in the second direction, wherein the third sub-shielding portion and the fourth sub-shielding portion have a first gap in the second direction; The orthographic projection of the first bent portion onto the substrate overlaps with the orthographic projection of the first gap onto the substrate.

18. The array substrate as claimed in claim 16 or 17, wherein, The array substrate further includes: multiple data lines; each data line includes: a first sub-metal portion and a second sub-metal portion arranged alternately along a second direction; the first sub-metal portion and the second sub-metal portion extend in different directions; The orthographic projection of the first sub-metal portion onto the substrate overlaps with the orthographic projection of the region between two adjacent first metal lines in the second direction onto the substrate; the orthographic projection of the second sub-metal portion onto the substrate overlaps with the orthographic projection of the first metal line onto the substrate.

19. The array substrate according to any one of claims 9-15, wherein, The array substrate further includes: multiple data lines; the data lines are multiplexed to form the second light-shielding pattern; The data cable includes: the third sub-shielding portion and the fourth sub-shielding portion; the data cable also includes: a second bend portion extending along the first direction; the third sub-shielding portion is connected to one side of the second bend portion, and the fourth sub-shielding portion is connected to the other side of the second bend portion.

20. The array substrate as claimed in claim 19, wherein, The orthographic projection of the second bent portion onto the substrate overlaps with the orthographic projection of the first bent portion onto the substrate, and the outer edge of the second bent portion along the second direction coincides with the outer edge of the first bent portion along the second direction.

21. The array substrate according to any one of claims 9-20, wherein, The first sub-shielding portion extends along the second direction, and the second sub-shielding portion extends along the second direction; The third sub-shading portion extends along the second direction, and the fourth sub-shading portion extends along the second direction. The direction extends, and the second direction is perpendicular to the first direction.

22. The array substrate according to any one of claims 9-20, wherein, The first sub-shielding portion extends along a third direction, and the second sub-shielding portion extends along the third direction; The third sub-shading part extends along the third direction, and the fourth sub-shading part extends along the third direction; the smaller of the angles formed by the third direction and the first direction is greater than zero degrees and less than 90 degrees.

23. The array substrate according to any one of claims 1-22, wherein, The first cutout extends in a third direction.

24. A display panel, wherein, Includes the array substrate as described in any one of claims 1-23; The display panel further includes: a polarizer; The absorption axis of the polarizer is parallel or perpendicular to the outer edge of the first light-shielding pattern.

25. A display device, wherein, Includes the display panel as described in claim 24.

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