Display panel and display apparatus

Abstract

The present application provides a display panel and a display apparatus. The display panel comprises a driving circuit layer, a resistance reduction layer, and a light-emitting device. The driving circuit layer comprises a plurality of transistors. The resistance reduction layer is provided with a first electrode, a second electrode, and a first power line. The first electrode and the first power line are both electrically connected to the transistors. A first terminal of the light-emitting device is bound to the first electrode, and a second terminal thereof is bound to the second electrode. Voltage uniformity on the first power line is greater than 85%.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, small-pitch light emitting diode (LED) direct display can bring excellent visual experience, and the market share is growing. For some special high-brightness scenes, it is necessary to develop LED backplanes with high brightness (such as >20000 nit) and high brightness uniformity. However, with the increase of display panel brightness and size, the influence of the voltage drop (IR drop) of the power line (such as VDD / VSS trace) on the brightness uniformity increases significantly. Therefore, how to reduce the voltage drop of the power line has become a problem that needs to be solved urgently. SUMMARY

[0003] The present application provides a display panel and a display device to reduce the voltage drop of the power line.

[0004] The technical solutions provided by the present application are as follows:

[0005] In a first aspect, the present application provides a display panel, comprising:

[0006] a substrate;

[0007] a drive circuit layer disposed on one side of the substrate, the drive circuit layer comprising a plurality of transistors;

[0008] a resistance reduction layer disposed on a side of the drive circuit layer away from the substrate, the resistance reduction layer being formed with a plurality of resistance reduction patterns, the plurality of resistance reduction patterns comprising a first electrode, a second electrode and a first power line, the first electrode and the first power line being electrically connected to the transistors;

[0009] a light emitting device disposed on a side of the resistance reduction layer away from the substrate, the light emitting device comprising a first pole and a second pole, the first pole being bound to the first electrode, and the second pole being bound to the second electrode;

[0010] wherein the voltage uniformity on the first power line is greater than 85%.

[0011] In a second aspect, the present application provides a display device comprising the display panel of the preceding embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only some of the embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0013] FIG. 1 is a schematic diagram of a film layer structure of a display panel in the related art.

[0014] FIG. 2 is a schematic diagram of a planar structure of a display panel according to an embodiment of the present application.

[0015] FIG. 3 is a schematic diagram of a partial detail structure of a display pixel in FIG. 2.

[0016] FIG. 4 is a schematic diagram of a cross-sectional structure along the direction of N-N' in FIG. 3.

[0017] FIG. 5 is a schematic diagram of a bonding structure of a light emitting device and a bonding electrode in the related art.

[0018] FIGS. 6a to 6e are schematic diagrams of a preparation process of a resistance reduction layer according to an embodiment of the present application.

[0019] FIG. 7 is a schematic diagram of another partial film layer structure of a display panel according to an embodiment of the present application.

[0020] FIG. 8 is a schematic diagram of still another partial film layer structure of a display panel according to an embodiment of the present application.

[0021] FIG. 9 is a schematic diagram of still another partial film layer structure of a display panel according to an embodiment of the present application.

[0022] FIG. 10 is a schematic diagram of an arrangement of a resistance reduction pattern in two adjacent display pixels according to an embodiment of the present application.

[0023] FIG. 11 is a schematic diagram of another planar structure of a display panel according to an embodiment of the present application.

[0024] FIG. 12 is a schematic diagram of a planar structure of a mother board according to an embodiment of the present application.

[0025] FIG. 13 is a schematic diagram of a cross-sectional structure of a display device according to an embodiment of the present application. Embodiments of the present application

[0026] The following description of the embodiments refers to the accompanying drawings, which are used to exemplify particular embodiments of the present application. Directional terms as used, e.g., [upper], [lower], [front], [back], [left], [right], [inner], [outer], [side] etc., are used with reference to the accompanying drawings. Consequently, the directional terms are used for illustration and understanding of the present application, and do not pertain to the application as such. In the drawings, similar elements of structure are denoted by like reference numbers. In the drawings, the thickness of some layers and regions are exaggerated for clarity and convenience of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited thereto.

[0027] In order to reduce the voltage drop of the power lines, it is common in the industry to set multiple metal layers in the display panel to form large-area power lines. Referring to FIG. 1, which is a schematic diagram of a film layer structure of a display panel in the related art, the display panel includes a substrate 10' and a driving circuit layer 20', a first metal layer M1', a second metal layer M2', and a third metal layer M3' arranged in sequence on the substrate 10'. The third metal layer M3' is used to form a first electrode 31' and a second electrode 32', the first metal layer M1' is used to form a large-area first power line 33', and the second metal layer M2' is used to form a large-area second power line 34'. By using multiple metal layers to form the large-area first power line 33' and the large-area second power line 34', the impedance of the first power line 33' and the second power line 34' can be reduced, and thus the voltage drop of the first power line 33' and the second power line 34' can be reduced.

[0028] However, the inventors of the present application found in research that: by setting multiple metal layers to form a large-area power line, although the voltage drop of the power line can be reduced, and the voltage uniformity of different areas on the power line can be improved, such as the voltage uniformity of different areas on the power line can be improved to 65%, but for higher requirements of voltage uniformity, such as to realize the voltage uniformity of different areas on the power line greater than 85%, it is difficult to realize by setting multiple metal layers to form a large-area power line. It should be noted that the voltage uniformity on the power line in the present application is used as an index to measure the voltage drop on the power line, the smaller the voltage drop on the power line, the better the voltage uniformity on the power line. Specifically, the voltage uniformity on the power line in the present application refers to the ratio of the voltage of different areas on the power line, for example, the ratio of the voltage at the far end of the power line to the voltage at the near end of the power line, the larger the ratio, the closer the voltage at the far end of the power line to the voltage at the near end, that is, the larger the ratio, the smaller the voltage drop on the power line, and accordingly, the better the voltage uniformity on the power line. Wherein, the near end of the power line refers to the area close to the integrated circuit (Integrated Circuit, IC) on the power line, and the far end of the power line refers to the area on the far side of the integrated circuit from the near end of the power line, the integrated circuit is connected to one end of the power line, and is used to provide a power voltage signal.

[0029] Therefore, the inventors of the present application have made continuous research and exploration, and proposed a display panel, a mother board and a display device to further reduce the voltage drop of the power line and realize higher requirements of voltage uniformity.

[0030] In an embodiment, the present application provides a display panel, comprising:

[0031] a substrate;

[0032] a drive circuit layer disposed on one side of the substrate, the drive circuit layer comprising a plurality of transistors;

[0033] a resistance reduction layer disposed on a side of the drive circuit layer away from the substrate, the resistance reduction layer being formed with a plurality of resistance reduction patterns, the plurality of resistance reduction patterns comprising a first electrode, a second electrode and a first power line, the first electrode and the first power line being electrically connected to the transistors; and

[0034] a light emitting device disposed on a side of the resistance reduction layer away from the substrate, the light emitting device comprising a first pole and a second pole, the first pole being bound to the first electrode, and the second pole being bound to the second electrode;

[0035] wherein the voltage uniformity on the first power line is greater than 85%.

[0036] In an embodiment, the resistance reduction pattern further comprises a second power line opposite and spaced apart from the first power line, a voltage uniformity on the second power line being greater than 85%; the second power line is integrally arranged with the second electrode.

[0037] In an embodiment, the material of the resistance reduction layer comprises copper, and a thickness of the resistance reduction layer ranges from 2 microns to 15 microns.

[0038] In an embodiment, the resistance reduction layer comprises a first copper layer and a second copper layer, the second copper layer is located on a side of the first copper layer away from the driving circuit layer, and a thickness of the second copper layer is greater than a thickness of the first copper layer.

[0039] In an embodiment, a boundary of the second copper layer exceeds a boundary of the first copper layer.

[0040] In an embodiment, the display panel further comprises a first flat layer between the driving circuit layer and the resistance reduction layer, the first flat layer is provided with a first via, and the first electrode is connected with the transistor through the first via on the first flat layer.

[0041] In an embodiment, the display panel further comprises:

[0042] a first flat layer between the driving circuit layer and the resistance reduction layer;

[0043] a first metal layer on a side of the first flat layer away from the resistance reduction layer, the first metal layer comprises an auxiliary electrode, and the first electrode is connected with the auxiliary electrode through a second via on the first flat layer;

[0044] a second flat layer on a side of the first metal layer away from the resistance reduction layer, and the auxiliary electrode is connected with the transistor through a third via on the second flat layer.

[0045] In an embodiment, a first gap is between adjacent resistance reduction patterns, and the display panel further comprises a filling structure arranged in the first gap, an absolute value of a difference between a thickness of the filling structure and a thickness of the resistance reduction pattern in a direction perpendicular to the substrate is less than or equal to 1.5 microns.

[0046] In an embodiment, the display panel further comprises:

[0047] a first filling layer comprising a first filling part arranged in the first gap;

[0048] A first anti-reflection layer is disposed on a side of the resistance-reducing layer distal to the driving circuit layer and has openings corresponding to positions of the first electrode and the second electrode; the first anti-reflection layer includes a first anti-reflection portion covering the resistance-reducing pattern and a second anti-reflection portion covering the first filling portion, and the second anti-reflection portion and the first filling portion jointly constitute the filling structure.

[0049] In an embodiment, the display panel further includes:

[0050] A second anti-reflection layer has openings corresponding to positions of the first electrode and the second electrode; the second anti-reflection layer includes a third anti-reflection portion and a fourth anti-reflection portion, the third anti-reflection portion covers the resistance-reducing pattern, and the fourth anti-reflection portion is located in the first gap.

[0051] A second filling layer includes a second filling portion disposed in the first gap, the second filling portion covers the fourth anti-reflection portion, and the fourth anti-reflection portion and the second filling portion jointly constitute the filling structure.

[0052] In an embodiment, the display panel further includes:

[0053] A second anti-reflection layer has openings corresponding to positions of the first electrode and the second electrode; the second anti-reflection layer includes a third anti-reflection portion and a fourth anti-reflection portion, the third anti-reflection portion covers the resistance-reducing pattern, and the fourth anti-reflection portion is located in the first gap.

[0054] A third anti-reflection layer includes a fifth anti-reflection portion disposed in the first gap, the fifth anti-reflection portion covers the fourth anti-reflection portion, and the fourth anti-reflection portion and the fifth anti-reflection portion jointly constitute the filling structure.

[0055] In an embodiment, the filling structure includes a protruding portion protruding from a plane in which a top surface of the resistance-reducing pattern is located; an included angle between a side surface of the protruding portion close to the first electrode and a top surface of the first electrode is less than 90 degrees; and / or, an included angle between a side surface of the protruding portion close to the second electrode and a top surface of the second electrode is less than 90 degrees.

[0056] In an embodiment, the display panel has a display area and a frame area outside the display area, and the display panel further includes a plurality of display pixels arranged in an array in the display area, a spacing between any two adjacent display pixels is the same, each display pixel includes at least three sub-pixels, each sub-pixel includes at least one transistor, one first electrode, one second electrode and one light emitting device, and a difference between area ratios of the resistance reduction pattern in adjacent display pixels is less than 20%.

[0057] In an embodiment, the frame area includes at least one binding area, the resistance reduction pattern further includes a binding terminal and / or fan-out wiring in the binding area, and a difference between the area ratio of the resistance reduction pattern in the unit area of the binding area and the area ratio of the resistance reduction pattern in each display pixel is less than 20%.

[0058] In an embodiment, the display panel further includes a plurality of virtual pixels in the frame area, and a difference between the area ratio of the resistance reduction pattern in the virtual pixels and the area ratio of the resistance reduction pattern in the display pixels is less than 20%.

[0059] In an embodiment, each display pixel further includes part of the first power supply line and part of the second power supply line, in each display pixel, the first power supply line is provided with a first notch on a side close to the second power supply line, the first electrode is located in the first notch, and the second power supply line is provided with a second notch on a side close to the first power supply line, and the second electrode is located in the second notch.

[0060] In an embodiment, the present application further provides a display device including the display panel of any one of the foregoing embodiments.

[0061] In the display panel and the display device provided in the application, the display panel comprises a substrate, a driving circuit layer, a resistance reduction layer and a light emitting device which are sequentially arranged on the substrate, the driving circuit layer comprises a plurality of transistors, the resistance reduction layer is formed with a plurality of resistance reduction patterns, the plurality of resistance reduction patterns comprise a first electrode, a second electrode and a first power supply line, the first electrode and the first power supply line are electrically connected with the transistors, the light emitting device comprises a first pole and a second pole, the first pole is bound with the first electrode, the voltage uniformity of the first power supply line is greater than 85%, and the second pole is bound with the second electrode; by adopting the resistance reduction layer to form the first electrode, the second electrode and the first power supply line, the voltage drop of the first power supply line can be reduced, the voltage uniformity of the first power supply line is greater than 85%, and the first electrode and the second electrode formed by the resistance reduction layer can be directly bound with the electrodes of the light emitting device without the need of arranging an adhesion layer or the like for increasing the adhesion of the upper and lower film layers between the bound electrodes and the electrodes of the light emitting device, so that the film layer structure of the bound electrodes can be simplified and the process can be simplified.

[0062] The display panel and the display device provided in the application will be described in detail below in combination with the drawings and specific embodiments.

[0063] Please refer to FIG. 2 to FIG. 4, FIG. 2 is a schematic diagram of a plane structure of a display panel provided in an embodiment of the application, FIG. 3 is a schematic diagram of a partial detail structure of a display pixel in FIG. 2, and FIG. 4 is a schematic diagram of a cross-sectional structure along the direction of N-N' in FIG. 3. Referring to FIG. 2, the display panel 100 comprises a display area AA and a frame area BA located outside the display area AA. The display area AA is used for displaying a picture, and the display area AA comprises a plurality of display pixels P arranged in an array. The frame area BA comprises at least one binding area PA, and a plurality of binding terminals BP are arranged in the binding area PA. An external circuit can be bound with the display panel 100 through the binding terminals BP. The external circuit can comprise a driving integrated circuit (IC), a flexible circuit board and the like.

[0064] Referring to FIG. 3, each display pixel P comprises at least three sub-pixels, for example, three sub-pixels are a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B respectively. The red sub-pixel R emits red light, the green sub-pixel G emits green light, and the blue sub-pixel B emits blue light, so as to realize color display of the display panel 100. Of course, the three sub-pixels can also emit light of the same color, for example, the three sub-pixels all emit blue light, and cooperate with a quantum dot film and a color filter to realize three primary colors.

[0065] With reference to FIG. 3 and FIG. 4, the display panel 100 further comprises a substrate 10, and a driving circuit layer 20, a resistance reduction layer 30, and a light emitting device 40 arranged in sequence on the substrate 10. The driving circuit layer 20 is arranged on one side of the substrate 10, and comprises a plurality of transistors 21. The resistance reduction layer 30 is arranged on a side of the driving circuit layer 20 away from the substrate 10, and is formed with a plurality of resistance reduction patterns, which comprise a first electrode 31, a second electrode 32, and a first power line 33, and the first electrode 31 and the first power line 33 are electrically connected to the transistors 21. The light emitting device 40 is arranged on a side of the resistance reduction layer 30 away from the substrate 10, and comprises a first pole 41 and a second pole 42, the first pole 41 is bound to the first electrode 31, and the second pole 42 is bound to the second electrode 32. The voltage uniformity on the first power line 33 is greater than 85%.

[0066] In the embodiment, by using the resistance reduction layer 30 to form the first electrode 31, the second electrode 32, and the first power line 33, the voltage drop of the first power line 33 can be reduced, and the voltage uniformity on the first power line 33 is greater than 85%. Moreover, the first electrode 31 and the second electrode 32 formed by the resistance reduction layer 30 can be directly bound to the electrodes of the light emitting device 40 as the binding electrodes, without the need to arrange an adhesion layer or the like for increasing the adhesion of the upper and lower film layers between the binding electrodes and the electrodes of the light emitting device 40, so that the film layer structure of the binding electrodes can be simplified, and the process can be simplified.

[0067] The film layer structure of the display panel 100 and the structure of the resistance reduction layer 30 will be described in detail below with reference to FIG. 3 and FIG. 4.

[0068] With reference to FIG. 4, the display panel 100 comprises a substrate 10, which can be a rigid substrate or a flexible substrate. When the substrate 10 is a rigid substrate, it can comprise a glass substrate or the like rigid substrate. When the substrate 10 is a flexible substrate, it can comprise a polyimide (PI) film, an ultra-thin glass film, or the like flexible substrate.

[0069] The driving circuit layer 20 is disposed on the substrate 10. The driving circuit layer 20 comprises at least one transistor 21, which can be a thin film transistor 21. The transistor 21 comprises an active layer 211, a gate 212, a source 213 and a drain 214. The active layer 211 comprises a channel region and source and drain regions on both sides of the channel region. The gate 212 is disposed on a side of the active layer 211 away from the substrate 10, and corresponds to the channel region of the active layer 211. The source 213 and the drain 214 are disposed on a side of the gate 212 away from the substrate 10, and the source 213 is connected to the source region of the active layer 211, and the drain 214 is connected to the drain region of the active layer 211. Of course, the structure of the transistor 21 of the present application is not limited to this, and the transistor 21 in this embodiment is only illustrative, and the transistor 21 of the present application can also adopt a bottom gate, double gate and other architectures.

[0070] Further, the driving circuit layer 20 further comprises an insulating layer disposed between each structure of the transistor 21, such as the driving circuit layer 20 further comprising a buffer layer 22 disposed between the transistor 21 and the substrate 10, a gate insulating layer 23 disposed between the gate 212 and the active layer 211, and a first interlayer insulating layer 24 disposed between the gate 212 and the source 213 and the drain 214. The source 213 and the drain 214 are connected to the source region and the drain region, respectively, through corresponding vias in the first interlayer insulating layer 24.

[0071] Optionally, the driving circuit layer 20 can further comprise a first capacitor C1. In order to form the first capacitor C1, the driving circuit layer 20 further comprises a conductive layer 25 and a second interlayer insulating layer 26 between the first interlayer insulating layer 24 and the gate 212. The conductive layer 25 is disposed on a side of the second interlayer insulating layer 26 away from the gate 212. The conductive layer 25 forms a first plate C11 of the first capacitor C1. A second plate C12 of the first capacitor C1 is disposed in the same layer as the gate 212.

[0072] The resistance reduction layer 30 is disposed on a side of the driving circuit layer 20 away from the substrate 10. The resistance reduction layer 30 is formed with a plurality of resistance reduction patterns. The resistance reduction patterns comprise a first electrode 31, a second electrode 32, a first power line 33 and a second power line 34. The first electrode 31 and the first power line 33 are both electrically connected to the transistor 21, such as the first electrode 31 being electrically connected to the drain 214 of the transistor 21, and the first power line 33 being electrically connected to the source 213 of the transistor 21.

[0073] The second power line 34 is opposite and spaced apart from the first power line 33, and the voltage uniformity on the second power line 34 is greater than 85%. The second electrode 32 is electrically connected to the second power line 34, and optionally, the second electrode 32 is integrally arranged with the second power line 34. The first electrode 31 and the second electrode 32 are insulated from each other. The first power line 33 and the second power line 34 are insulated from each other. The first electrode 31 and the second electrode 32 are located between the first power line 33 and the second power line 34. Optionally, the first power line 33 is provided with a first notch on one side close to the second power line 34, and the first electrode 31 is located in the first notch. The second power line 34 is provided with a second notch on one side close to the first power line 33, and the second electrode 32 is located in the second notch. The voltage on the first power line 33 is greater than the voltage on the second power line 34, for example, the first power line 33 is VDD, and the second power line 34 is VSS.

[0074] The material of the resistance reduction layer 30 includes copper, for example, the resistance reduction layer 30 is a thickness layer formed by a thick copper process, and the thickness of the resistance reduction layer 30 ranges from 2 microns to 15 microns. The resistance reduction layer 30 with a larger thickness has a lower impedance. In this way, the first power line 33 is formed by using the resistance reduction layer 30 with a larger thickness, which can reduce the impedance of the first power line 33, reduce the voltage drop on the first power line 33, and make the voltage uniformity on the first power line 33 greater than 85%, thereby improving the brightness uniformity of the display panel. Correspondingly, the second power line 34 is formed by using the resistance reduction layer 30 with a larger thickness, which can reduce the impedance of the second power line 34, reduce the voltage drop on the second power line 34, and make the voltage uniformity on the second power line 34 greater than 85%, thereby further improving the brightness uniformity of the display panel, and achieving a higher requirement for the brightness uniformity.

[0075] The light emitting device 40 is disposed on the side of the resistance reduction layer 30 away from the driving circuit layer 20. The light emitting device 40 includes a first electrode 41 and a second electrode 42 which are disposed in insulation. The first electrode 41 is bonded with the first electrode 31, and the second electrode 42 is bonded with the second electrode 32. Optionally, the display panel 100 further includes a solder layer 401 between the light emitting device 40 and the resistance reduction layer 30, the first electrode 41 and the second electrode 42 are bonded with the first electrode 31 and the second electrode 32 respectively through the corresponding solder layer 401, and the first electrode 31 and the second electrode 32 are both in contact with the corresponding solder layer 401. The solder of the solder layer 401 can be solder tin or eutectic solder composed of tin and indium. One of the first electrode 41 and the second electrode 42 is an anode, and the other is a cathode. The first electrode 41 includes a first signal terminal 411 and a first gold layer 412 covering the surface of the first signal terminal 411, and the second electrode 42 includes a second signal terminal 421 and a second gold layer 422 covering the surface of the second signal terminal 421.

[0076] By using the resistance reduction layer 30 to form the first electrode 31 and the second electrode 32, the impedance of the first electrode 31 and the second electrode 32 can be reduced, and the first electrode 31 and the second electrode 32 are directly bonded with the light emitting device 40, so that the contact impedance between the first electrode 31 and the second electrode 32 and the light emitting device 40 can be reduced, thereby further reducing the voltage drop and further improving the brightness uniformity of the display panel, so as to achieve higher requirements for the brightness uniformity. Moreover, by using the resistance reduction layer 30 to form the first electrode 31 and the second electrode 32 and directly bonding with the light emitting device 40, the film structure of the bonded electrode can be simplified, and the process can be simplified.

[0077] Specifically, referring to FIG. 5, which is a schematic diagram of a bonding structure of a light emitting device and a bonding electrode in the related art. The first electrode 41' of the light emitting device 40' is bonded with the first electrode 31' through a solder layer 401', and the second electrode 42' is also bonded with the second electrode 32' through the solder layer 401'. The first electrode 41' includes a first signal terminal 411' and a first gold layer 412' covering the surface of the first signal terminal 411', and the second electrode 42' includes a second signal terminal 421' and a second gold layer 422' covering the surface of the second signal terminal 421'. In order to improve the stability of the bonding between the first electrode 41' and the first electrode 31', and the second electrode 42' and the second electrode 32', the first electrode 31' and the second electrode 32' usually need to be provided as a stack of multiple metal layers, such as the first electrode 31' including a first terminal portion 311', a first adhesion layer 312', and a first auxiliary copper layer 313', and the second electrode 32' including a second terminal portion 321', a second adhesion layer 322', and a second auxiliary copper layer 323', wherein the material of the first terminal portion 311' and the second terminal portion 321' is a titanium-aluminum-titanium metal stack, the material of the first adhesion layer 312' and the second adhesion layer 322' is titanium, and the material of the first auxiliary copper layer 313' and the second auxiliary copper layer 323' is copper. In the present application, the first electrode 31 and the second electrode 32 are formed by the resistance reduction layer 30, and the first electrode 31 and the second electrode 32 are both in direct contact with the corresponding solder layer 401, and are bonded together with the first electrode 41 and the second electrode 42 of the light emitting device 40 through the corresponding solder layer 401, respectively, so that there is no need to provide an adhesion layer and an auxiliary copper layer for increasing the adhesion of the upper and lower film layers between the bonding electrode and the electrodes of the light emitting device 40, the film layer structure of the bonding electrode can be simplified, and the process can be simplified.

[0078] The first electrode 31 is electrically connected with the transistor 21 in the following specific implementation. Referring to FIG. 4, the display panel 100 further comprises a first metal layer M1 between the resistance reduction layer 30 and the driving circuit layer 20, and the first metal layer M1 comprises an auxiliary electrode 11 and a signal line 12, which can be various display signal lines for realizing the display function of the display panel 100. The first electrode 31 is electrically connected with the drain electrode 214 of the transistor 21 through the auxiliary electrode 11. Of course, the display panel 100 further comprises a plurality of insulating layers arranged between the first metal layer M1 and the resistance reduction layer 30 and the driving circuit layer 20. Specifically, the plurality of insulating layers comprise a first planar layer 51 and a first passivation layer 52 between the first metal layer M1 and the resistance reduction layer 30, and a second planar layer 53 and a second passivation layer 54 between the first metal layer M1 and the driving circuit layer 20. The first passivation layer 52 is located on the side of the first planar layer 51 away from the substrate 10, and the second passivation layer 54 is located on the side of the second planar layer 53 away from the substrate 10. The materials of the first planar layer 51 and the second planar layer 53 comprise organic materials such as organic photoresist, and the materials of the first passivation layer 52 and the second passivation layer 54 comprise inorganic materials such as silicon oxide and silicon nitride.

[0079] The first electrode 31 is connected with the auxiliary electrode 11 through a second via hole 512 on the first planar layer 51, and the auxiliary electrode 11 is connected with the drain electrode 214 of the transistor 21 through a third via hole 531 on the second planar layer 53, so as to realize the electrical connection between the first electrode 31 and the drain electrode 214 of the transistor 21.

[0080] In an embodiment, referring to FIG. 4, in order to improve the bonding yield of the light emitting device 40 with the first electrode 31 and the second electrode 32, it is necessary to improve the flatness of the film layer where the first electrode 31 and the second electrode 32 are located. However, the thickness of the resistance reduction layer 30 is large, so that the resistance reduction layer 30 forms deep pits with large depth between the plurality of resistance reduction patterns when forming the plurality of resistance reduction patterns, and the existence of the deep pits seriously affects the flatness of the film layer, and further seriously affects the bonding yield of the light emitting device 40 with the first electrode 31 and the second electrode 32. Therefore, the embodiment of the present application sets a filling structure 60 between adjacent resistance reduction patterns to improve the flatness of the film layer.

[0081] Specifically, the first gap is between the adjacent resistance-reducing patterns, and the display panel 100 further comprises a filling structure 60 arranged in the first gap. In a direction perpendicular to the substrate 10, the absolute value of the difference between the thickness of the filling structure 60 and the thickness of the resistance-reducing pattern is less than or equal to 1.5 microns, such as the absolute value of the difference between the thickness of the filling structure 60 and the thickness of the resistance-reducing pattern is 1.5 microns, 1.4 microns, 1.3 microns, 1.2 microns, 1.1 microns, 1 micron, 0.9 microns, 0.8 microns, 0.7 microns, 0.6 microns, 0.5 microns, 0.4 microns, 0.3 microns, 0.2 microns, 0.1 microns, 0 microns, etc.

[0082] Optionally, the display panel 100 further comprises a first filling layer 61 and the first anti-reflection layer 62. The first filling layer 61 comprises a first filling portion 611 arranged in the first gap. The first anti-reflection layer 62 is arranged on the side of the resistance-reducing layer 30 away from the driving circuit layer 20, and is provided with an opening at the position corresponding to the first electrode 31 and the second electrode 32. The first anti-reflection layer 62 comprises a first anti-reflection portion 621 covering the resistance-reducing pattern, and a second anti-reflection portion 622 covering the first filling portion 611, such as the first anti-reflection portion 621 covering the surfaces of the first power line 33 and the second power line 34. The second anti-reflection portion 622 and the first filling portion 611 jointly constitute the filling structure 60. The material of the first filling layer 61 comprises an organic photoresist such as OC, and the material of the first anti-reflection layer 62 comprises an organic photoresist such as BM or other materials with anti-reflection effect. The first anti-reflection layer 62 has the effect of reducing the reflectivity of the metal surface. Therefore, by arranging the first filling layer 61 and the first anti-reflection layer 62, the film layer flatness is improved, the binding yield is improved, and the surface reflectivity of the resistance-reducing layer 30 is reduced.

[0083] Optionally, the filling structure 60 comprises a protrusion, which protrudes from the plane where the top surface of the resistance-reducing pattern is located. In this embodiment, the second anti-reflective layer 622 is the protrusion. The angle between the side surface of the protrusion close to the first electrode 31 and the top surface of the first electrode 31 is less than 90 degrees, i.e. an undercut structure is formed between the protrusion and the first electrode 31; and / or the angle between the side surface of the protrusion close to the second electrode 32 and the top surface of the second electrode 32 is less than 90 degrees, i.e. an undercut structure is formed between the protrusion and the second electrode 32. By forming the protrusion on the filling structure 60, the height of the protrusion is less than 1.5 microns, so as to form a shallow pit above the first electrode 31 and the second electrode 32. In this way, the flow of the solder of the solder layer 401 can be blocked in the process of binding the light-emitting device 40 with the first electrode 31 and the second electrode 32, so as to avoid the short circuit of the first electrode 31 and the second electrode 32, thereby further improving the binding yield. Moreover, by forming the undercut structure between the protrusion and the first electrode 31 and / or the second electrode 32, the flow of the solder of the solder layer 401 can be further effectively blocked, so as to avoid the short circuit of the first electrode 31 and the second electrode 32, thereby further improving the binding yield. Optionally, in order to facilitate the formation of the undercut structure between the protrusion and the first electrode 31 and / or the second electrode 32, the material of the structure forming the protrusion can be selected as a negative photoresist.

[0084] Optionally, the display panel 100 further comprises a protective layer arranged on the side of the resistance-reducing layer 30 away from the driving circuit layer 20. Specifically, the protective layer is arranged on the side of the first anti-reflective layer 62 away from the resistance-reducing layer 30, and the protective layer covers the surface of the first anti-reflective layer 62. Of course, the protective layer is also provided with openings at positions corresponding to the first electrode 31 and the second electrode 32, so as to expose the first electrode 31 and the second electrode 32. The material of the protective layer comprises inorganic materials such as silicon oxide and silicon nitride, and the protective layer is used for blocking water and oxygen, so as to protect the metal traces in the display panel 100.

[0085] Next, how to form the resistance-reducing layer 30 will be specifically described.

[0086] Optionally, the resistance reduction layer 30 is prepared by electroplating thick copper process. The inventors of the present application have found in the continuous exploration and research that, in order to reduce the voltage drop of the power supply line, a metal with low resistivity and thick thickness needs to be used, and common process schemes include physical vapor deposition (PVD), electrofluid, screen printing, electroplating, chemical plating, evaporation, etc., and common metals include AL, Mo, Ag, Au, Cu, etc. However, considering the problems of stress-induced chipping, alignment accuracy, flow time, not supporting large size, too high cost, etc., the electroplating thick copper scheme is the optimal scheme.

[0087] Specifically, referring to FIGS. 6a-6e, FIGS. 6a-6e are schematic diagrams of a preparation process of the resistance reduction layer 30 provided in the embodiments of the present application, wherein FIG. 6a is a schematic diagram of preparing a first copper layer 301 and a photoresist layer 200 on a first passivation layer 52, FIG. 6b is a schematic diagram of forming a photoresist pattern 201 from the photoresist layer 200 in FIG. 6a, FIG. 6c is a schematic diagram of electroplating a copper layer to form a second copper layer 302 on the structure in FIG. 6b, FIG. 6d is a schematic diagram of peeling off the photoresist pattern 201 in FIG. 6c, and FIG. 6e is a schematic diagram of the first copper layer 301 after etching in FIG. 6d. Referring to FIG. 6a, a first copper layer 301 is deposited on the first passivation layer 52 as a seed copper layer by physical vapor deposition (PVD), and the material of the first copper layer 301 is copper. Then, a photoresist layer 200 is formed on the first copper layer 301. Referring to FIG. 6b, the photoresist layer 200 is exposed and developed to form a photoresist pattern 201, and the photoresist pattern 201 has a gap between adjacent photoresist patterns 201. Referring to FIG. 6c, thick copper is electroplated in the gap between adjacent photoresist patterns 201 by electroplating thick copper process to form a second copper layer 302, and the material of the second copper layer 302 is copper. Referring to FIG. 6d, the photoresist pattern 201 is peeled off to expose the first copper layer 301. Referring to FIG. 6e, the first copper layer 301 is etched to form a resistance reduction pattern of the resistance reduction layer 30, that is, the resistance reduction layer 30 includes the first copper layer 301 and the second copper layer 302, the second copper layer 302 is located on the side of the first copper layer 301 away from the driving circuit layer 20, and the thickness of the second copper layer 302 is greater than the thickness of the first copper layer 301. Since the second copper layer 302 is formed by electroplating resistance reduction process, the density of the second copper layer 302 is greater than the density of the first copper layer 301, and therefore the second copper layer 302 is not easily etched compared with the first copper layer 301. When the first copper layer 301 is etched, the boundary of the first copper layer 301 will be retracted compared with the boundary of the second copper layer 302 to form an undercut structure, that is, the boundary of the second copper layer 302 exceeds the boundary of the first copper layer 301.

[0088] In an embodiment, referring to FIGS. 2-7, FIG. 7 is a schematic diagram of another partial film layer structure of the display panel 100 provided in the embodiment. Referring to FIG. 7, different from the above-mentioned embodiments, the display panel 100 further includes a second anti-reflection layer 63 and a second filling layer 64. The second anti-reflection layer 63 is provided with openings at positions corresponding to the first electrode 31 and the second electrode 32, and includes a third anti-reflection part 631 and a fourth anti-reflection part 632. The third anti-reflection part 631 covers the resistance reduction pattern, for example, the third anti-reflection part 631 covers the surfaces of the first power line 33 and the second power line 34. The fourth anti-reflection part 632 is located in the first gap. The second filling layer 64 includes a second filling part 641 provided in the first gap, and the second filling part 641 covers the fourth anti-reflection part 632. The fourth anti-reflection part 632 and the second filling part 641 jointly constitute the filling structure 60. The material of the second filling layer 64 includes OC or other organic photoresist, and the material of the second anti-reflection layer 63 includes BM or other organic photoresist or other materials with anti-reflection effect. The second anti-reflection layer 63 has the effect of reducing the reflectivity of the metal surface. Therefore, by providing the second filling layer 64 and the second anti-reflection layer 63, the surface reflectivity of the resistance reduction layer 30 can be reduced while improving the film layer flatness and the binding yield.

[0089] Optionally, the filling structure 60 comprises a protruding portion protruding from the plane where the top surface of the resistance-reducing pattern is located, and in this embodiment, the second filling portion 641 protruding from the plane where the top surface of the resistance-reducing pattern is located is the protruding portion. The included angle between the side surface of the protruding portion close to the first electrode 31 and the top surface of the first electrode 31 is less than 90 degrees, that is, an undercut structure is formed between the protruding portion and the first electrode 31; and / or the included angle between the side surface of the protruding portion close to the second electrode 32 and the top surface of the second electrode 32 is less than 90 degrees, that is, an undercut structure is formed between the protruding portion and the second electrode 32. By making the filling structure 60 form the protruding portion, the height of the protruding portion is less than 1.5 microns, so as to form a shallow pit above the first electrode 31 and the second electrode 32, thus in the process of binding the light-emitting device 40 and the first electrode 31 and the second electrode 32, the flow of the solder of the soldering layer 401 can be blocked, and the first electrode 31 and the second electrode 32 can be prevented from short-circuiting, so as to further improve the binding yield; and furthermore, by making the undercut structure be formed between the protruding portion and the first electrode 31 and / or the second electrode 32, the flow of the solder of the soldering layer 401 can be further effectively blocked, and the first electrode 31 and the second electrode 32 can be prevented from short-circuiting, so as to further improve the binding yield. Optionally, in order to facilitate the undercut structure to be formed between the protruding portion and the first electrode 31 and / or the second electrode 32, the material of the structure forming the protruding portion can be selected as a negative photoresist. Other descriptions can refer to the above embodiments, which will not be repeated here.

[0090] In one embodiment, referring to FIGS. 2 to 8, FIG. 8 is a schematic diagram of another partial film layer structure of the display panel 100 provided in the embodiment. Referring to FIG. 8, different from the above embodiments, the display panel 100 further comprises a second anti-reflection layer 63 and a third anti-reflection layer 65. The second anti-reflection layer 63 is provided with an opening at a position corresponding to the first electrode 31 and the second electrode 32, and the second anti-reflection layer 63 comprises a third anti-reflection portion 631 and a fourth anti-reflection portion 632, the third anti-reflection portion 631 covers the resistance-reducing pattern, and the fourth anti-reflection portion 632 is located in the first gap. The third anti-reflection layer 65 comprises a fifth anti-reflection portion 651 located in the first gap, and the fifth anti-reflection portion 651 covers the fourth anti-reflection portion 632, and the fourth anti-reflection portion 632 and the fifth anti-reflection portion 651 jointly constitute the filling structure 60. The material of the third anti-reflection layer 65 comprises an organic photoresist such as BM or other materials with anti-reflection effect, and the third anti-reflection layer 65 has the effect of reducing the reflectivity of the metal surface. Other descriptions can refer to the above embodiments, which will not be repeated here.

[0091] In an embodiment, referring to FIGS. 2-9, FIG. 9 is a schematic view of another partial film layer structure of the display panel 100 provided in the embodiment. Referring to FIG. 9, different from the above embodiments, the display panel 100 further includes a first planar layer 51 between the driving circuit layer 20 and the resistance reduction layer 30, and the first electrode 31 is connected to the transistor 21 through a first via hole 511 in the first planar layer 51, that is, in the embodiment, the first electrode 31 is directly connected to the drain 214 of the transistor 21, so that the first metal layer M1 is not needed to be arranged, so as to further reduce the contact impedance of the first electrode 31, thereby further improving the brightness uniformity. In some other embodiments, the first passivation layer 52 can also be removed. Other descriptions can refer to the above embodiments, which are not repeated here.

[0092] In an embodiment, in order to improve the film thickness uniformity of the resistance reduction layer 30, the resistance reduction pattern on the electroplated resistance reduction area of the display panel 100 needs to be arranged compactly and uniformly. Specifically, referring to FIGS. 2-10, FIG. 10 is a schematic view of the arrangement of the resistance reduction pattern in two adjacent display pixels P provided in the embodiment. Referring to FIGS. 2 and 10, the display panel 100 has a display area AA and a frame area BA outside the display area AA, and the display panel 100 further includes a plurality of display pixels P arranged in an array in the display area AA, the spacing between any two adjacent display pixels P is the same, each display pixel P includes at least three sub-pixels, each sub-pixel includes at least one transistor 21, one first electrode 31, one second electrode 32, and one light emitting device 40. Each display pixel P further includes part of the first power supply line 33 and part of the second power supply line 34. In each display pixel P, the first power supply line 33 is provided with a first notch on the side close to the second power supply line 34, the first electrode 31 is located in the first notch, and the second power supply line 34 is provided with a second notch on the side close to the first power supply line 33, and the second electrode 32 is located in the second notch. In two adjacent display pixels P, the difference between the area ratios of the resistance reduction patterns is less than 20%, wherein in each display pixel P, the area of the resistance reduction pattern refers to the sum of the areas of three first electrodes 31, three second electrodes 32, part of the first power supply line 33, and part of the second power supply line 34. On the display panel 100, the resistance reduction pattern in each display pixel P is a repeating unit. Other descriptions can refer to the above embodiments, which are not repeated here.

[0093] In an embodiment, referring to FIG. 2, the bezel area BA includes at least one binding area PA, the resistance reduction pattern further includes a binding terminal BP and / or a fan-out wire located at the binding area PA, and a difference between an area ratio of the resistance reduction pattern in a unit area of the binding area PA and an area ratio of the resistance reduction pattern in each display pixel P is less than 20%. For details, refer to the above-mentioned embodiments, which will not be repeated here.

[0094] In an embodiment, referring to FIGS. 2 to 11, FIG. 11 is another schematic plan view of the display panel 100 provided by an embodiment of the present application. Referring to FIG. 11, the display panel 100 further includes a plurality of virtual pixels DP located at the bezel area BA, and a difference between an area ratio of the resistance reduction pattern in the virtual pixel DP and an area ratio of the resistance reduction pattern in the display pixel P is less than 20%. For details, refer to the above-mentioned embodiments, which will not be repeated here.

[0095] Based on the same inventive concept, an embodiment of the present application further provides a mother board 1000. Referring to FIGS. 2 to 12, FIG. 12 is a schematic plan view of the mother board 1000 provided by an embodiment of the present application. Referring to FIG. 12, the mother board 1000 includes a plurality of array-arranged display panels 100, and a spacing between adjacent display panels 100 is the same. The display panel 100 includes the display panel 100 of one of the above-mentioned embodiments.

[0096] Based on the same inventive concept, an embodiment of the present application further provides a display device. Referring to FIGS. 1 to 13, FIG. 13 is a schematic cross-sectional view of the display device provided by an embodiment of the present application. The display device includes a housing 300 and the display panel 100 of one of the above-mentioned embodiments. The housing 300 is formed with a receiving cavity 310, and the display panel 100 is arranged in the receiving cavity 310.

[0097] According to the above-mentioned embodiments, it can be known that:

[0098] The application provides a display panel, a mother board and a display device, the display panel comprises a substrate, a driving circuit layer, a resistance reduction layer and a light emitting device which are sequentially arranged on the substrate, the driving circuit layer comprises a plurality of transistors, the resistance reduction layer is formed with a plurality of resistance reduction patterns, the plurality of resistance reduction patterns comprise a first electrode, a second electrode and a first power line, the first electrode and the first power line are electrically connected with the transistors, the light emitting device comprises a first pole and a second pole, the first pole is bound with the first electrode, and the second pole is bound with the second electrode, and the voltage uniformity of the first power line is greater than 85%; the first electrode, the second electrode and the first power line are formed by adopting the resistance reduction layer, so that the voltage drop of the first power line is reduced, the voltage uniformity of the first power line is greater than 85%, and the first electrode and the second electrode formed by adopting the resistance reduction layer are directly bound with the electrodes of the light emitting device, without the need of arranging an adhesive layer or the like for increasing the adhesion of upper and lower film layers between the bound electrodes and the electrodes of the light emitting device, so that the film layer structure of the bound electrodes is simplified, and the process is simplified.

[0099] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0100] The above describes the embodiments of the application in detail, and the principle and implementation mode of the application are described by applying specific examples; the above embodiment is only used to help understand the technical scheme and core idea of the application; the person skilled in the art should understand that the technical scheme recorded in the above embodiments can be modified, or some technical features can be replaced by equivalents; and the modification or replacement does not make the essence of the corresponding technical scheme deviate from the scope of the technical scheme of the embodiments of the application.

Claims

1. A display panel comprising: Substrate; A driving circuit layer is disposed on one side of the substrate, and the driving circuit layer includes a plurality of transistors; A resistance-reducing layer is disposed on the side of the driving circuit layer away from the substrate. The resistance-reducing layer includes multiple resistance-reducing patterns, and the multiple resistance-reducing patterns include a first electrode, a second electrode, and a first power line. The first electrode and the first power line are both electrically connected to the transistor. as well as A light-emitting device is disposed on the side of the resistivity-reducing layer away from the substrate. The light-emitting device includes a first electrode and a second electrode, wherein the first electrode is bonded to the first electrode and the second electrode is bonded to the second electrode. The voltage uniformity on the first power line is greater than 85%.

2. The display panel according to claim 1, wherein, The resistance reduction pattern also includes a second power line that is opposite to and spaced apart from the first power line, and the voltage uniformity of the second power line is greater than 85%; the second power line is integrally formed with the second electrode.

3. The display panel according to claim 2, wherein, The material of the resistance-reducing layer includes copper, and the thickness of the resistance-reducing layer ranges from 2 micrometers to 15 micrometers.

4. The display panel according to claim 3, wherein, The resistance-reducing layer includes a first copper layer and a second copper layer, the second copper layer being located on the side of the first copper layer away from the driving circuit layer, and the thickness of the second copper layer being greater than the thickness of the first copper layer.

5. The display panel according to claim 4, wherein, The boundary of the second copper layer extends beyond the boundary of the first copper layer.

6. The display panel according to claim 1, wherein, The display panel further includes a first planarization layer located between the driving circuit layer and the resistance reduction layer; The first planarization layer has a first via, and the first electrode passes through the first via to connect to the transistor.

7. The display panel according to claim 1, wherein, The display panel also includes: A first planarization layer is disposed between the driving circuit layer and the resistance reduction layer; A first metal layer is disposed on the side of the first planarization layer away from the resistance-reducing layer. The first metal layer includes an auxiliary electrode, and the first electrode passes through a second via on the first planarization layer and is connected to the auxiliary electrode. A second planarization layer is disposed on the side of the first metal layer away from the resistance-reducing layer, and the auxiliary electrode is connected to the transistor through a third via on the second planarization layer.

8. The display panel according to claim 1, wherein, The display panel further includes a welding layer, wherein the first electrode and the second electrode are respectively bonded to the first electrode and the second electrode through the corresponding welding layer, and both the first electrode and the second electrode are in contact with the corresponding welding layer.

9. The display panel according to any one of claims 2 to 8, wherein, The adjacent resistivity-reducing patterns have a first gap, and the display panel further includes a filling structure disposed in the first gap. In a direction perpendicular to the substrate, the absolute value of the difference between the thickness of the filling structure and the thickness of the resistivity-reducing pattern is less than or equal to 1.5 micrometers.

10. The display panel according to claim 9, wherein, The display panel also includes: The first filling layer includes a first filling portion disposed within the first gap; A first anti-reflection layer is disposed on the side of the drag-reducing layer away from the driving circuit layer, and has an opening at the position corresponding to the first electrode and the second electrode; The first anti-reflective layer includes a first anti-reflective portion covering the drag-reducing pattern and a second anti-reflective portion covering the first filling portion, wherein the second anti-reflective portion and the first filling portion together constitute the filling structure.

11. The display panel according to claim 9, wherein, The display panel also includes: The second anti-reflective layer has an opening at a position corresponding to the first electrode and the second electrode. The second anti-reflective layer includes a third anti-reflective portion and a fourth anti-reflective portion. The third anti-reflective portion covers the drag-reducing pattern, and the fourth anti-reflective portion is located within the first gap. The second filling layer includes a second filling portion disposed within the first gap, the second filling portion covering the fourth anti-reflective portion, and the fourth anti-reflective portion and the second filling portion together constitute the filling structure.

12. The display panel according to claim 9, wherein, The display panel also includes: The second anti-reflective layer has an opening at a position corresponding to the first electrode and the second electrode. The second anti-reflective layer includes a third anti-reflective portion and a fourth anti-reflective portion. The third anti-reflective portion covers the drag-reducing pattern, and the fourth anti-reflective portion is located within the first gap. The third anti-reflective layer includes a fifth anti-reflective portion disposed within the first gap, the fifth anti-reflective portion covering the fourth anti-reflective portion, and the fourth and fifth anti-reflective portions together constituting the filling structure.

13. The display panel according to claim 9, wherein, The filling structure includes a protrusion that protrudes beyond the plane containing the top surface of the drag-reducing pattern; The angle between the side of the protrusion near the first electrode and the top surface of the first electrode is less than 90 degrees; and / or, the angle between the side of the protrusion near the second electrode and the top surface of the second electrode is less than 90 degrees.

14. The display panel according to claim 9, wherein, The display panel has a display area and a border area located outside the display area. The display panel also includes a plurality of display pixels arranged in an array in the display area. The spacing between any two adjacent display pixels is the same. Each display pixel includes at least three sub-pixels. Each sub-pixel includes at least one transistor, a first electrode, a second electrode, and a light-emitting device. In two adjacent display pixels, the difference in the area of ​​the drag-reducing pattern is less than 20%.

15. The display panel according to claim 14, wherein, The border area includes at least one bonding area, and the drag-reducing pattern also includes bonding terminals and / or fan-out traces located in the bonding area. The difference between the area ratio of the drag-reducing pattern per unit area in the bonding area and the area ratio of the drag-reducing pattern per display pixel is less than 20%.

16. The display panel according to claim 15, wherein, The display panel also includes a plurality of virtual pixels located in the border area, wherein the difference between the area ratio of the drag-reducing pattern in the virtual pixels and the area ratio of the drag-reducing pattern in the display pixels is less than 20%.

17. The display panel according to claim 14, wherein, Each of the display pixels further includes a portion of the first power line and a portion of the second power line. Within each display pixel, a first notch is provided on the side of the first power line near the second power line, and the first electrode is located within the first notch. A second notch is provided on the side of the second power line near the first power line, and the second electrode is located within the second notch.

18. A display device comprising a display panel as claimed in any one of claims 1 to 17.

Images