Display substrate and manufacturing method therefor

Abstract

A display substrate and a manufacturing method therefor. The display substrate comprises a base substrate (11), a driving circuit layer (12), a plurality of first electrodes (13), a pixel definition layer (PDL), a spacer layer and an insulating layer (17), wherein the driving circuit layer (12) is arranged on the base substrate (11); the plurality of first electrodes (13) are arranged on the side of the driving circuit layer (12) away from the base substrate (11); the pixel definition layer (PDL) is arranged on the side of the plurality of first electrodes away from the base substrate (11), and comprises a plurality of sub-pixel openings to respectively expose the plurality of first electrodes (13), the plurality of sub-pixel openings comprising a first sub-pixel opening (P1), a second sub-pixel opening (P2) and a third sub-pixel opening (P3); the spacer layer is arranged on the side of the pixel definition layer (PDL) away from the base substrate (11), and comprises spacers (16) that are arranged between adjacent sub-pixel openings of light-emitting material layers (14) having different colors; and the insulating layer (17) is arranged on the side of the spacer layer away from the base substrate (11), and at least part of the cross section of the edge portion of the insulating layer (17) close to the third sub-pixel opening (P3) has steps. The display substrate has a better display effect.

Description

Display substrate and method of manufacturing the same

[0001] This application claims priority to Chinese Patent Application No. 202410832028.5, filed on June 25, 2024, the disclosure of which is incorporated herein in its entirety as part of the present application. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to a display substrate and a method of manufacturing the same. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) display devices have a series of advantages such as self-emission, high contrast, high definition, wide viewing angle, low power consumption, fast response speed, and low manufacturing cost, and have become one of the key development directions of new generation display devices, and therefore have attracted more and more attention.

[0004] SUMMARY

[0005] At least one embodiment of the present disclosure provides a display substrate, which includes a substrate substrate, a driving circuit layer, a plurality of first electrodes, a pixel definition layer, a spacer column layer, and an insulating layer; the driving circuit layer is disposed on the substrate substrate, the plurality of first electrodes are disposed on a side of the driving circuit layer away from the substrate substrate, the pixel definition layer is disposed on a side of the plurality of first electrodes away from the substrate substrate, and includes a plurality of sub-pixel openings, wherein the plurality of sub-pixel openings respectively expose the plurality of first electrodes, the plurality of sub-pixel openings include a first sub-pixel opening, a second sub-pixel opening, and a third sub-pixel opening, the first sub-pixel opening, the second sub-pixel opening, and the third sub-pixel opening have different color light-emitting material layers, the spacer column layer is disposed on a side of the pixel definition layer away from the substrate substrate, and includes a spacer column, wherein the spacer column is disposed between adjacent sub-pixel openings having different color light-emitting material layers, and the insulating layer is disposed on a side of the spacer column layer away from the substrate substrate, wherein at least part of a cross section of an edge portion of the insulating layer close to the third sub-pixel opening has a step.

[0006] For example, in the display substrate provided by at least one embodiment of the present disclosure, the edge portion includes a first edge portion close to the third sub-pixel opening and a second edge portion located on a side of the first edge portion away from the third sub-pixel opening, and in a direction perpendicular to the substrate substrate, a thickness of the first edge portion is less than a thickness of the second edge portion.

[0007] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the light-emitting material layer includes a first light-emitting material layer, a second light-emitting material layer, and a third light-emitting material layer, the first light-emitting material layer is arranged in the first sub-pixel opening, the second light-emitting material layer is arranged in the second sub-pixel opening, the third light-emitting material layer is arranged in the third sub-pixel opening, the isolation column includes a first isolation column, the first isolation column is arranged between adjacent first sub-pixels and third sub-pixels, and the first isolation column has the material of the second light-emitting material layer thereon.

[0008] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, in a direction perpendicular to the substrate, the thickness of the material of the second light-emitting material layer on the first isolation column is less than the thickness of the second light-emitting material layer.

[0009] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the first light-emitting material layer and the third light-emitting material layer overlap on the first isolation column.

[0010] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, in the overlapping position, the third light-emitting material layer is located on the side of the first light-emitting material layer away from the substrate, so as to overlap the first light-emitting material layer in a direction perpendicular to the substrate, thereby achieving the overlap.

[0011] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the material of the second light-emitting material layer is on the side of the first light-emitting material layer close to the third light-emitting material layer.

[0012] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the isolation column includes a second isolation column, the second isolation column is arranged between adjacent first sub-pixels and second sub-pixels, and the first light-emitting material layer and the second light-emitting material layer overlap on the second isolation column. In the overlapping position, the second light-emitting material layer is located on the side of the first light-emitting material layer away from the substrate, so as to overlap the first light-emitting material layer in a direction perpendicular to the substrate, thereby achieving the overlap.

[0013] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the isolation column includes a third isolation column, the third isolation column is arranged between adjacent second sub-pixels and third sub-pixels, and the second light-emitting material layer and the third light-emitting material layer overlap on the third isolation column. In the overlapping position, the third light-emitting material layer is located on the side of the second light-emitting material layer away from the substrate, so as to overlap the second light-emitting material layer in a direction perpendicular to the substrate, thereby achieving the overlap.

[0014] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the light-emitting material layer includes a first light-emitting material layer, a second light-emitting material layer, and a third light-emitting material layer, the first light-emitting material layer is arranged in the first sub-pixel opening, the second light-emitting material layer is arranged in the second sub-pixel opening, the third light-emitting material layer is arranged in the third sub-pixel opening, the isolation column includes a first isolation column, the first isolation column is arranged between adjacent first sub-pixels and third sub-pixels, the first light-emitting material layer and the third light-emitting material layer have a first interval above the first isolation column, and the insulating layer on the first isolation column has a first groove at the first interval.

[0015] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the isolation column includes a second isolation column, the second isolation column is arranged between adjacent first sub-pixels and second sub-pixels, the first light-emitting material layer and the second light-emitting material layer have a second interval above the second isolation column, and the insulating layer on the second isolation column has a second groove at the second interval.

[0016] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the isolation column includes a third isolation column, the third isolation column is arranged between adjacent second sub-pixels and third sub-pixels, the second light-emitting material layer and the third light-emitting material layer have a third interval above the third isolation column, and the insulating layer on the third isolation column has a third groove at the third interval.

[0017] For example, in the display substrate provided by at least one of the embodiments of the present disclosure, the first light-emitting material layer, the second light-emitting material layer, and the third light-emitting material layer are one of a red light-emitting material layer, a green light-emitting material layer, and a blue light-emitting material layer.

[0018] The present disclosure also provides a preparation method of a display substrate, including: providing a substrate, forming a driving circuit layer on the substrate, forming a plurality of first electrodes on a side of the driving circuit layer away from the substrate, forming a pixel definition layer on a side of the plurality of first electrodes away from the substrate, wherein the pixel definition layer includes a plurality of sub-pixel openings, the plurality of sub-pixel openings respectively expose the plurality of first electrodes, the plurality of sub-pixel openings include a first sub-pixel opening, a second sub-pixel opening, and a third sub-pixel opening, the first sub-pixel opening, the second sub-pixel opening, and the third sub-pixel opening are respectively used to form light-emitting material layers of different colors, forming a first light-emitting material layer in at least the plurality of sub-pixel openings, and removing a part of the first light-emitting material layer located in the second sub-pixel opening, and retaining a part of the first light-emitting material layer located in the first sub-pixel opening and the third sub-pixel opening.

[0019] For example, the preparation method provided by at least one of the embodiments of the present disclosure further includes: forming a second light-emitting material layer in at least the plurality of sub-pixel openings, and removing portions of the first light-emitting material layer and the second light-emitting material layer located in the third sub-pixel opening, and retaining portions of the second light-emitting material layer located in the first sub-pixel opening and the second sub-pixel opening.

[0020] For example, the preparation method provided by at least one of the embodiments of the present disclosure further includes: forming a third light-emitting material layer in at least the plurality of sub-pixel openings, and removing portions of the third light-emitting material layer located in the first sub-pixel opening and the second sub-pixel opening, and retaining portions of the third light-emitting material layer located in the third sub-pixel opening.

[0021] For example, in the preparation method provided by at least one of the embodiments of the present disclosure, forming a first light-emitting material layer in at least the plurality of sub-pixel openings, and removing portions of the first light-emitting material layer located in the second sub-pixel opening, and retaining portions of the first light-emitting material layer located in the first sub-pixel opening and the third sub-pixel opening includes: sequentially forming a first light-emitting material layer and a first electrode material layer in at least the plurality of sub-pixel openings, and removing portions of the first light-emitting material layer and the first electrode material layer located in the second sub-pixel opening, and retaining portions of the first light-emitting material layer and the first electrode material layer located in the first sub-pixel opening and the third sub-pixel opening.

[0022] For example, the preparation method provided by at least one of the embodiments of the present disclosure further includes: sequentially forming a second light-emitting material layer and a second electrode material layer in at least the plurality of sub-pixel openings, and removing portions of the first light-emitting material layer, the first electrode material layer, the second light-emitting material layer, and the second electrode material layer located in the third sub-pixel opening, and retaining portions of the second light-emitting material layer and the second electrode material layer located in the first sub-pixel opening and the second sub-pixel opening.

[0023] For example, the preparation method provided by at least one of the embodiments of the present disclosure further includes: sequentially forming a third light-emitting material layer and a third electrode material layer in at least the plurality of sub-pixel openings, and removing portions of the third light-emitting material layer and the third electrode material layer located in the first sub-pixel opening and the second sub-pixel opening, and retaining portions of the third light-emitting material layer and the third electrode material layer located in the third sub-pixel opening.

[0024] For example, in the preparation method provided by at least one embodiment of the present disclosure, at least forming a first light-emitting material layer in the plurality of sub-pixel openings, and removing the part of the first light-emitting material layer located in the second sub-pixel opening, and retaining the part of the first light-emitting material layer located in the first sub-pixel opening and the third sub-pixel opening, comprises: sequentially forming a first light-emitting material layer, a first electrode material layer and a first sub-packaging layer in the plurality of sub-pixel openings, and removing the part of the first light-emitting material layer, the first electrode material layer and the first sub-packaging layer located in the second sub-pixel opening, and retaining the part of the first light-emitting material layer, the first electrode material layer and the first sub-packaging layer located in the first sub-pixel opening and the third sub-pixel opening.

[0025] For example, the preparation method provided by at least one embodiment of the present disclosure further comprises: sequentially forming a second light-emitting material layer, a second electrode material layer and a second sub-packaging layer in the plurality of sub-pixel openings, and removing the part of the first light-emitting material layer, the first electrode material layer, the first sub-packaging layer, the second light-emitting material layer, the second electrode material layer and the second sub-packaging layer located in the third sub-pixel opening, and retaining the part of the second light-emitting material layer, the second electrode material layer and the second sub-packaging layer located in the first sub-pixel opening and the second sub-pixel opening.

[0026] For example, the preparation method provided by at least one embodiment of the present disclosure further comprises: sequentially forming a third light-emitting material layer, a third electrode material layer and a third sub-packaging layer in the plurality of sub-pixel openings, and removing the part of the third light-emitting material layer, the third electrode material layer and the third sub-packaging layer located in the first sub-pixel opening and the second sub-pixel opening, and retaining the part of the third light-emitting material layer, the third electrode material layer and the third sub-packaging layer located in the third sub-pixel opening.

[0027] For example, in the preparation method provided by at least one embodiment of the present disclosure, the first light-emitting material layer retained in the first sub-pixel opening, the second light-emitting material layer retained in the second sub-pixel opening and the third light-emitting material layer retained in the third sub-pixel opening are one of a red light-emitting material layer, a green light-emitting material layer and a blue light-emitting material layer, respectively.

[0028] For example, in the preparation method provided by at least one embodiment of the present disclosure, before at least forming a first light-emitting material layer in the plurality of sub-pixel openings, the preparation method further comprises: forming an isolation column layer on the side of the pixel defining layer away from the substrate, the isolation column layer comprising at least one isolation column, wherein after at least forming a first light-emitting material layer in the plurality of sub-pixel openings, the first light-emitting material layer is disconnected at the at least one isolation column.

[0029] For example, in the preparation method provided by at least one of the embodiments of the present disclosure, the driving circuit layer comprises a plurality of conductive patterns, and the at least one isolation column is formed in electrical connection with at least one of the plurality of conductive patterns.

[0030] For example, in the preparation method provided by at least one of the embodiments of the present disclosure, the at least one isolation column is respectively formed between any two adjacent ones of the first light-emitting material layer, the second light-emitting material layer and the third light-emitting material layer, and the first light-emitting material layer, the second light-emitting material layer and the third light-emitting material layer are disconnected at the at least one isolation column.

[0031] For example, in the preparation method provided by at least one of the embodiments of the present disclosure, forming a driving circuit layer on the substrate includes: forming a transistor, a storage capacitor and a plurality of signal lines, wherein the transistor includes a gate and a source-drain electrode, the storage capacitor includes a first capacitor electrode and a second capacitor electrode, and the plurality of conductive patterns include the gate, the source-drain electrode, the first capacitor electrode, the second capacitor electrode and the plurality of signal lines. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some of the embodiments of the present disclosure, but not limit the present disclosure.

[0033] FIG. 1 is a cross-sectional schematic view of a display substrate;

[0034] FIG. 2 is a plan view of a pixel unit in a display substrate;

[0035] FIGS. 3A-5B are plan views of the display substrate in FIG. 2 during preparation;

[0036] FIG. 6 is a cross-sectional schematic view of another display substrate;

[0037] FIG. 7 is a cross-sectional schematic view of a first sub-pixel and a third sub-pixel in a display substrate provided by at least one of the embodiments of the present disclosure;

[0038] FIG. 8 is a cross-sectional schematic view of a first sub-pixel and a second sub-pixel in a display substrate provided by at least one of the embodiments of the present disclosure;

[0039] FIG. 9 is a cross-sectional schematic view of a second sub-pixel and a third sub-pixel in a display substrate provided by at least one of the embodiments of the present disclosure;

[0040] FIG. 10 is a cross-sectional schematic view of a first sub-pixel and a third sub-pixel in another display substrate provided by at least one of the embodiments of the present disclosure;

[0041] FIG. 11 is a cross-sectional view of a first sub-pixel and a second sub-pixel in another display substrate according to at least one embodiment of the present disclosure;

[0042] FIG. 12 is a cross-sectional view of a second sub-pixel and a third sub-pixel in another display substrate according to at least one embodiment of the present disclosure;

[0043] FIGS. 13A-13B are plan views of the display substrate of FIGS. 7-9 during fabrication;

[0044] FIGS. 14A-14C are cross-sectional views of the display substrate of FIGS. 7-9 during fabrication;

[0045] FIGS. 15A-15B are plan views of the display substrate of FIGS. 7-9 during fabrication;

[0046] FIGS. 16A-16C are cross-sectional views of the display substrate of FIGS. 7-9 during fabrication;

[0047] FIGS. 17A-17B are plan views of the display substrate of FIGS. 7-9 during fabrication;

[0048] FIGS. 18A-18B are plan views of the display substrate of FIGS. 10-12 during fabrication;

[0049] FIGS. 19A-19C are cross-sectional views of the display substrate of FIGS. 10-12 during fabrication;

[0050] FIGS. 20A-20B are plan views of the display substrate of FIGS. 10-12 during fabrication;

[0051] FIGS. 21A-21C are cross-sectional views of the display substrate of FIGS. 10-12 during fabrication;

[0052] FIGS. 22A-22B are plan views of the display substrate of FIGS. 10-12 during fabrication;

[0053] FIG. 23 is a cross-sectional view of yet another display substrate according to at least one embodiment of the present disclosure;

[0054] FIG. 24 is a circuit diagram of a pixel driving circuit of a display substrate according to at least one embodiment of the present disclosure; and

[0055] FIG. 25 is a timing diagram of a pixel driving circuit of a display substrate according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the drawings of the embodiments of the present disclosure to clearly and completely describe the technical solutions of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the protection scope of the present disclosure.

[0057] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the common meaning understood by a person of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second" and similar terms used in the present disclosure do not indicate any order, number or importance, but are only used to distinguish different components. The terms "include", "contain" and similar terms mean that the components or objects before the terms cover the components or objects listed after the terms and their equivalents, and do not exclude other components or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships may also be changed accordingly.

[0058] FIG. 1 shows a cross-sectional schematic view of a display substrate, as shown in FIG. 1, the display substrate has a plurality of sub-pixels for display, two adjacent sub-pixels, i.e. a first sub-pixel SP1 and a second sub-pixel SP2, are shown in FIG. 1 as an example, the display substrate further includes a substrate 11, a driving circuit layer 12, a light emitting device layer M, an isolation column layer, an encapsulation layer EN and the like functional layers.

[0059] For example, as shown in FIG. 1, the driving circuit layer 12 is disposed on the substrate 11 and includes pixel driving circuits for a plurality of sub-pixels, each pixel driving circuit includes a plurality of transistors and a storage capacitor and the like structures (to be described in detail later). The light emitting device layer M is disposed on the side of the driving circuit layer 12 away from the substrate 11 and includes light emitting devices for a plurality of sub-pixels. For example, each sub-pixel includes one pixel driving circuit of the driving circuit layer 12 and one light emitting device of the light emitting device layer M, and the pixel driving circuit is used to drive the light emitting device to emit light.

[0060] For example, as shown in FIG. 1, each light emitting device includes a first electrode 13, a light emitting material layer 14 and a second electrode 15, under the voltage driving of the first electrode 13 and the second electrode 15, the light emitting material layer 14 can emit light and realize the corresponding gray scale. For example, the first electrode 13 can be an anode and is electrically connected with the pixel driving circuit through a via hole for transmitting a high-level voltage; the second electrode 15 can be a cathode for transmitting a low-level voltage.

[0061] For example, in order to realize full-color display, a plurality of sub-pixels can emit light of different colors, such as red light, green light, and blue light, etc. In FIG. 1, the first sub-pixel SP1 and the second sub-pixel SP2 are used to emit light of different colors, and therefore the light-emitting material layer 14 of the first sub-pixel SP1 and the second sub-pixel SP2 is different, so that the light-emitting colors can be different. In order to isolate the light-emitting material layers 14 of adjacent sub-pixels with different colors, an isolation column layer can be provided on the display substrate, the isolation column layer comprising at least one isolation column 16, the isolation column 16 being provided at least between the sub-pixels with different light-emitting colors, the isolation column 16 having a structure with a concave side wall, so that the formed light-emitting material layer 14 can be sufficiently broken at the isolation column 16, thereby isolating the light-emitting material layers 14 of adjacent sub-pixels with different light-emitting colors.

[0062] For example, an encapsulation layer EN is provided above the light-emitting device to encapsulate the light-emitting device layer M. For example, the display substrate can further comprise more encapsulation layers or other structures provided on the side of the encapsulation layer EN away from the substrate 11, which will not be described here.

[0063] For example, the second electrode 15 and the encapsulation layer EN are also broken at the isolation column 16, and the second electrode 15 is in contact with the isolation column 16. In some embodiments, the isolation column 16 is a conductive isolation column, for example, formed of a conductive material, at this time, the isolation column 16 electrically connects the second electrodes 15 of adjacent sub-pixels, so that the isolation column 16 transmits the electrical signals of the second electrode 15, and the electrical signals transmitted by the second electrodes 15 of the plurality of sub-pixels are the same, which is conducive to display uniformity.

[0064] For example, as shown in FIG. 1, an insulating layer 17 can be provided on the isolation column 16 to shield the electrical signals transmitted in the isolation column 16, for example, to prevent the electrical signals transmitted in the isolation column 16 from affecting other electrical signals transmitted above it, such as touch signals, etc. For example, the insulating layer 17 can be formed of inorganic materials such as silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0065] For example, in some embodiments, during the preparation of the light-emitting material layer 14, the second electrode 15, and the encapsulation layer EN, the light-emitting material layer 14, the second electrode 15, and the encapsulation layer EN are formed on the plurality of first electrodes 13 in sequence, and then etched to retain the light-emitting material layer 14, the second electrode 15, and the encapsulation layer EN in the desired area. For example, if a pixel unit as shown in FIG. 2 is to be formed, the pixel unit comprising a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 with different light-emitting colors, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be used to emit red light, green light, and blue light, respectively, for example, and an exemplary preparation process is shown in FIGS. 3A-5B.

[0066] As shown in Fig. 3A, the luminescent material layer 14 of the first sub-pixel SP1, the second electrode 15 and the encapsulation layer EN are sequentially formed on the plurality of first electrodes 13, and then, as shown in Fig. 3B, the luminescent material layer 14, the second electrode 15 and the encapsulation layer EN of the first sub-pixel SP1 are etched to remain only in the region where the first sub-pixel SP1 is located.

[0067] Then, as shown in Fig. 4A, the luminescent material layer 14 of the second sub-pixel SP2, the second electrode 15 and the encapsulation layer EN are sequentially formed on the plurality of first electrodes 13, and then, as shown in Fig. 4B, the luminescent material layer 14, the second electrode 15 and the encapsulation layer EN of the second sub-pixel SP2 are etched to remain only in the region where the second sub-pixel SP2 is located.

[0068] Then, as shown in Fig. 5A, the luminescent material layer 14 of the third sub-pixel SP3, the second electrode 15 and the encapsulation layer EN are sequentially formed on the plurality of first electrodes 13, and then, as shown in Fig. 4B, the luminescent material layer 14, the second electrode 15 and the encapsulation layer EN of the third sub-pixel SP3 are etched to remain only in the region where the third sub-pixel SP3 is located.

[0069] In the above preparation process, the first electrode 13 of the third sub-pixel SP3 is etched by the luminescent material layer 14, the second electrode 15 and the encapsulation layer EN of the first sub-pixel SP1 and the second sub-pixel SP2 respectively, and in the etching process, in order to ensure complete etching, the first electrode 13 will be over-etched, at this time, the etching of the first sub-pixel SP1 and the second sub-pixel SP2 will cause the first electrode 13 of the third sub-pixel SP3 to be over-etched twice, so as to avoid the luminescent material layer 14 of the first sub-pixel SP1 and the second sub-pixel SP2 remaining on the first electrode 13 of the third sub-pixel SP3; similarly, the encapsulation layer EN of the first sub-pixel SP1 is etched by the luminescent material layer 14, the second electrode 15 and the encapsulation layer EN of the second sub-pixel SP2 and the third sub-pixel SP3 respectively, and in the etching process, in order to ensure complete etching, the encapsulation layer EN of the first sub-pixel SP1 will be over-etched twice, so as to avoid the luminescent material layer 14 of the second sub-pixel SP2 and the third sub-pixel SP3 remaining on the encapsulation layer EN of the first sub-pixel SP1; similarly, the encapsulation layer EN of the second sub-pixel SP2 is etched by the luminescent material layer 14, the second electrode 15 and the encapsulation layer EN of the third sub-pixel SP3, and in the etching process, in order to ensure complete etching, the encapsulation layer EN of the second sub-pixel SP2 will be over-etched once, so as to avoid the luminescent material layer 14 of the third sub-pixel SP3 remaining on the encapsulation layer EN of the second sub-pixel SP2.

[0070] Thus, the different structures of the sub-pixels of different colors are etched inconsistently. For example, the first electrode 13 of the first sub-pixel SP1 is over-etched twice, and electrode loss phenomenon is prone to occur, which seriously affects display; the encapsulation layers EN of the first sub-pixel SP1 and the encapsulation layers EN of the second sub-pixel SP2 are over-etched to different degrees, causing the luminescent material layer 14 and the second electrode 15 of the first sub-pixel SP1 and the second sub-pixel SP2 to be exposed and etched at the isolation column 16, as shown in FIG. 6, so that the second electrode 15 cannot be connected with the isolation column 16, and thus the second electrodes 15 of the plurality of sub-pixels are disconnected, the signal of the second electrode 15 cannot be transmitted as a whole, and display is affected.

[0071] The display substrate provided in at least one embodiment of the present disclosure includes a substrate, a driving circuit layer, a plurality of first electrodes, a pixel definition layer, an isolation column layer, and an insulating layer. The driving circuit layer is disposed on the substrate. The plurality of first electrodes are disposed on a side of the driving circuit layer away from the substrate. The pixel definition layer is disposed on a side of the plurality of first electrodes away from the substrate and includes a plurality of sub-pixel openings. The plurality of sub-pixel openings respectively expose the plurality of first electrodes. The plurality of sub-pixel openings include a first sub-pixel opening, a second sub-pixel opening, and a third sub-pixel opening. The first sub-pixel opening, the second sub-pixel opening, and the third sub-pixel opening have luminescent material layers of different colors. The isolation column layer is disposed on a side of the pixel definition layer away from the substrate and includes an isolation column. The isolation column is disposed between adjacent sub-pixel openings having luminescent material layers of different colors. The insulating layer is disposed on a side of the isolation column layer away from the substrate. At least part of an edge portion of the insulating layer near the third sub-pixel opening has a step.

[0072] The preparation method of the display substrate provided in at least one embodiment of the present disclosure includes the following steps. A substrate is provided. A driving circuit layer is formed on the substrate. A plurality of first electrodes are formed on a side of the driving circuit layer away from the substrate. A pixel definition layer is formed on a side of the plurality of first electrodes away from the substrate. The pixel definition layer includes a plurality of sub-pixel openings. The plurality of sub-pixel openings respectively expose the plurality of first electrodes. The plurality of sub-pixel openings include a first sub-pixel opening, a second sub-pixel opening, and a third sub-pixel opening. The first sub-pixel opening, the second sub-pixel opening, and the third sub-pixel opening are respectively used to form luminescent material layers of different colors. A first luminescent material layer is formed in at least the plurality of sub-pixel openings. Part of the first luminescent material layer located in the second sub-pixel opening is removed, and parts of the first luminescent material layer located in the first sub-pixel opening and the third sub-pixel opening are retained.

[0073] The display substrate provided by the display substrate preparation method provided in the embodiments of the present disclosure can be prepared. In the preparation process of the display substrate, the first light-emitting material layer remaining in the part of the third sub-pixel opening can serve as a sacrificial layer (protective layer) of the first electrode exposed by the third sub-pixel opening, so as to avoid the first electrode from being etched multiple times. Therefore, the etching times of the first electrode can be greatly reduced, the multiple first electrodes have high uniformity, and the display effect of the display substrate is improved.

[0074] The display substrate and the preparation method thereof provided in the embodiments of the present disclosure are described below through several specific examples.

[0075] The display substrate provided by at least one of the embodiments of the present disclosure is shown in different cross-sectional schematic diagrams in FIGS. 7-9. The display substrate has multiple sub-pixels, for example, taking the multiple sub-pixels including a first sub-pixel SP1, a second sub-pixel SP2 and a third sub-pixel SP3 as an example for description. For example, FIG. 7 shows a cross-sectional schematic diagram of adjacent first sub-pixels SP1 and third sub-pixels SP3. FIG. 8 shows a cross-sectional schematic diagram of adjacent first sub-pixels SP1 and second sub-pixels SP2. FIG. 9 shows a cross-sectional schematic diagram of adjacent second sub-pixels SP2 and third sub-pixels SP3.

[0076] As shown in FIG. 7, the display substrate includes a substrate 11, a driving circuit layer 12, a light-emitting device layer M (including multiple first electrodes 13 and a pixel definition layer PDL, etc.), a spacer layer, and an insulating layer 17.

[0077] The driving circuit layer 12 is disposed on the substrate 11 and includes multiple pixel driving circuits. The multiple first electrodes 13 are disposed on the side of the driving circuit layer 12 away from the substrate 11. The pixel definition layer PDL is disposed on the side of the multiple first electrodes 13 away from the substrate 11 and includes multiple sub-pixel openings. The multiple sub-pixel openings respectively expose the multiple first electrodes 13. The multiple sub-pixel openings include a first sub-pixel opening P1, a second sub-pixel opening P2 and a third sub-pixel opening P3, which are used to form the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3. The first sub-pixel opening P1, the second sub-pixel opening P2 and the third sub-pixel opening P3 have light-emitting material layers 14 of different colors, so that the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 can emit light of different colors.

[0078] The spacer layer is disposed on the side of the pixel definition layer PDL away from the substrate 11 and includes spacers 16. The spacers 16 are disposed at least between the adjacent sub-pixel openings having the light-emitting material layers 14 of different colors, so as to break the light-emitting material layers 14 and avoid color crosstalk between the adjacent sub-pixels.

[0079] The insulating layer 17 is disposed on the side of the isolation column layer away from the substrate 11, and can be made of inorganic materials such as silicon oxide, silicon nitride, or silicon oxynitride. At least part of the cross section of the edge portion of the insulating layer 17 near the third sub-pixel opening P3 has a step, as shown in the dashed-line frame in FIG. 7.

[0080] For example, as shown in FIG. 7, the edge portion of the insulating layer 17 near the third sub-pixel opening P3 includes a first edge portion 171 near the third sub-pixel opening P3 and a second edge portion 172 on the side of the first edge portion 171 away from the third sub-pixel opening P3. In the direction perpendicular to the substrate 11, the thickness of the first edge portion 171 is smaller than the thickness of the second edge portion 172.

[0081] For example, in some embodiments, at least part of the cross section of the edge portion of the insulating layer 17 near the third sub-pixel opening P3 can have multiple steps, and one step is shown as an example in FIG. 7. In the case where at least part of the cross section of the edge portion has multiple steps, the thickness of the multiple steps of the edge portion gradually increases in the direction from the edge portion to the middle portion of the insulating layer 17.

[0082] For example, the display substrate further includes a second electrode 15 disposed on the side of the light-emitting material layer 14 away from the substrate 11. For example, the first electrode 13, the light-emitting material layer 14, and the second electrode 15 within the range of each sub-pixel opening constitute a light-emitting device, and each sub-pixel includes one light-emitting device disposed in the light-emitting device layer M and one pixel driving circuit disposed in the driving circuit layer 12. For example, the first electrode 13 is the anode of the light-emitting device, used to transmit a high-level voltage signal, and the second electrode 15 is the cathode, used to transmit a low-level voltage signal. Under the voltage control of the first electrode 13 and the second electrode 15, the light-emitting material layer 14 can emit light.

[0083] For example, in some embodiments, the light-emitting material layer 14 and the second electrode 15 are both broken at the isolation column 16 and in contact with the isolation column 16. For example, the isolation column 16 is conductive, and can be made of metal materials such as copper, titanium, aluminum, nickel, or alloy materials. In this case, the second electrodes 15 of the light-emitting devices of multiple sub-pixels are electrically connected by the isolation column 16 to transmit the same low-level voltage signal.

[0084] For example, in some embodiments, as shown in FIGS. 7-9, the light-emitting material layer 14 includes a first light-emitting material layer 141, a second light-emitting material layer 142, and a third light-emitting material layer 143, the first light-emitting material layer 141 is disposed in the first sub-pixel opening P1, the second light-emitting material layer 142 is disposed in the second sub-pixel opening P2, and the third light-emitting material layer 143 is disposed in the third sub-pixel opening P3. As shown in FIG. 7, the isolation column 16 includes a first isolation column 161 disposed between the adjacent first sub-pixel SP1 and the third sub-pixel SP3, and the first isolation column 161 has the material L1 of the second light-emitting material layer 142 thereon.

[0085] For example, in some embodiments, as shown in FIG. 7, the first light-emitting material layer 141 and the third light-emitting material layer 143 overlap on the first isolation column 161, for example, above the material L1 of the second light-emitting material layer 142 on the first isolation column 161.

[0086] For example, at the overlapping position, the third light-emitting material layer 143 is located on the side of the first light-emitting material layer 141 away from the substrate 11, so as to overlap the first light-emitting material layer 141 in the direction perpendicular to the substrate 11, to achieve the overlapping.

[0087] For example, as shown in FIG. 7, the material L1 of the second light-emitting material layer 142 is on the side of the first light-emitting material layer 141 close to the third light-emitting material layer 143, i.e., on the sidewall of the first light-emitting material layer 141.

[0088] For example, in the direction perpendicular to the substrate 11, the thickness of the material of the second light-emitting material layer on the first isolation column 161 is less than the thickness of the second light-emitting material layer 142.

[0089] For example, in some embodiments, as shown in FIG. 8, the isolation column 16 includes a second isolation column 162 disposed between the adjacent first sub-pixel SP1 and the second sub-pixel SP2, and the first light-emitting material layer 141 in the first sub-pixel opening P1 and the second light-emitting material layer 142 in the second sub-pixel opening P2 overlap on the second isolation column 162.

[0090] For example, at the overlapping position, the second light-emitting material layer 142 is located on the side of the first light-emitting material layer 141 away from the substrate 11, so as to overlap the first light-emitting material layer 141 in the direction perpendicular to the substrate 11, to achieve the overlapping.

[0091] For example, in some embodiments, as shown in FIG. 9, at least part of the cross section of the edge portion of the insulating layer 17 close to the third sub-pixel opening P3 has a step, as shown in the portion circled by the dashed line in FIG. 9. The isolation column 16 includes a third isolation column 163, which is arranged between the adjacent second sub-pixel SP2 and the third sub-pixel SP3, and the light-emitting material layer 152 of the second sub-pixel SP2 and the light-emitting material layer 153 of the third sub-pixel SP3 overlap on the third isolation column 163.

[0092] For example, in the overlapping position, the third light-emitting material layer 143 is located on the side of the second light-emitting material layer 142 away from the substrate 11, so as to overlap with the second light-emitting material layer 142 in the direction perpendicular to the substrate 11, thereby achieving the overlapping.

[0093] For example, in some other embodiments, the light-emitting material layers 14 of the adjacent sub-pixels can also not overlap on the isolation column 16, but have a spacing.

[0094] For example, FIG. 10 shows a cross-sectional schematic view of the adjacent first sub-pixel SP1 and third sub-pixel SP3 in another display substrate provided by at least one embodiment of the present disclosure, FIG. 11 shows a cross-sectional schematic view of the adjacent first sub-pixel SP1 and second sub-pixel SP2 in another display substrate provided by at least one embodiment of the present disclosure, and FIG. 12 shows a cross-sectional schematic view of the adjacent second sub-pixel SP2 and third sub-pixel SP3 in another display substrate provided by at least one embodiment of the present disclosure.

[0095] As shown in FIGS. 10-12, the light-emitting material layer 14 includes a first light-emitting material layer 141, a second light-emitting material layer 142, and a third light-emitting material layer 143, the first light-emitting material layer 141 is arranged in the first sub-pixel SP1 opening P1, the second light-emitting material layer 142 is arranged in the second sub-pixel SP2 opening P2, and the third light-emitting material layer 143 is arranged in the third sub-pixel SP3 opening P3.

[0096] For example, as shown in FIG. 10, at least part of the cross section of the edge portion of the insulating layer 17 close to the third sub-pixel opening P3 has a step, as shown in the portion circled by the dashed line in FIG. 10. For example, the isolation column 16 includes a first isolation column 161, which is arranged between the adjacent first sub-pixel SP1 and third sub-pixel SP3, and the first light-emitting material layer 141 and the third light-emitting material layer 143 have a first spacing T1 above the first isolation column 161, and the insulating layer 17 on the first isolation column 161 has a first groove G1 at the first spacing T1.

[0097] For example, as shown in FIG. 11, the isolation column 16 includes a second isolation column 162, which is arranged between the adjacent first and second sub-pixels SP1 and SP2, and the first and second light-emitting material layers 141 and 142 have a second interval T2 above the second isolation column 162, and the insulating layer 17 on the second isolation column 162 has a second groove G2 at the second interval T2.

[0098] For example, as shown in FIG. 12, the isolation column 16 includes a third isolation column 163, which is arranged between the adjacent second and third sub-pixels SP2 and SP3, and the second and third light-emitting material layers 142 and 143 have a third interval T3 above the third isolation column 163, and the insulating layer 17 on the third isolation column 163 has a third groove G3 at the third interval T3.

[0099] For example, in some embodiments, the first, second and third light-emitting material layers 141, 142 and 143 are one of a red, green and blue light-emitting material layer, respectively. For example, in some examples, the first, second and third light-emitting material layers 141, 142 and 143 are a red, green and blue light-emitting material layer, respectively. Alternatively, in other examples, the first, second and third light-emitting material layers 141, 142 and 143 are a blue, green and red light-emitting material layer, respectively, or other combinations, and embodiments of the present disclosure are not limited in this regard.

[0100] For example, in other embodiments, referring to FIG. 23, the driving circuit layer 12 includes a plurality of conductive patterns (e.g., portions indicated by reference numerals 101-103, which will be described in detail later), and the isolation column 16 can be electrically connected to at least one (shown as a signal line 101 in the figure) of the plurality of conductive patterns through a via (e.g., V1 and V2, which will be described in detail later). Thus, the isolation column 16 can transmit the electrical signal of the conductive pattern connected thereto, instead of the signal line connected to the conductive pattern, to simplify the circuit arrangement, or the isolation column can reduce the electrical resistance of the conductive pattern (e.g., the signal line 101) connected thereto to improve the accuracy of signal transmission.

[0101] For example, in some embodiments, as shown in FIG. 23, the driving circuit layer 12 includes a transistor 102, a storage capacitor 103, and a plurality of signal lines 101, the transistor 102 includes an active layer 1021, a gate 1022, and a source / drain electrode 1023 / 1024, the storage capacitor 103 includes a first capacitor electrode 1031 and a second capacitor electrode 1032, and the plurality of signal lines 101 can include various signal lines that the display substrate has, such as various scan lines, data lines, reset voltage lines, power supply lines, and the like. For example, the above-mentioned plurality of conductive patterns include the gate 1022, the source / drain electrode 1023 / 1024, the first capacitor electrode 1031, the second capacitor electrode 1032, and the plurality of signal lines 101 of each transistor, at this time, the conductive pattern connected by the via of the isolation column 16 can be one or more of the above-mentioned various patterns, as long as signal crosstalk does not occur.

[0102] For example, as shown in FIG. 23, the driving circuit layer 12 has a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3 which are sequentially stacked in a direction away from the substrate base plate 11, the gate 1022 and the first capacitor electrode 1031 are disposed in the first conductive layer M1, the second capacitor electrode 1032 is disposed in the second conductive layer M2, and the source / drain electrode 1023 / 1024 is disposed in the third conductive layer M3, and the plurality of signal lines 101 are respectively disposed in at least one of the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3. In the cross-sectional view shown in FIG. 4, the signal line 101 is shown in the third conductive layer M3, and in other cross-sections, different signal lines 101 can be located in different conductive layers, which will not be described here.

[0103] For example, in some other embodiments, the driving circuit layer 12 can include more conductive layers, for example, the driving circuit layer 12 can further include a fourth conductive layer disposed on the side of the third conductive layer M3 away from the substrate base plate 11, and the like, at this time, the plurality of signal lines 101 are respectively disposed in at least one of the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4, and the like.

[0104] For example, as shown in FIG. 23, the display substrate can further include a barrier layer B1 and a buffer layer B2 disposed on the substrate base plate 11, the barrier layer B1 and the buffer layer B2 can prevent impurities in the substrate base plate 11 from entering the plurality of functional layers on the display substrate, thereby playing a protective role. For example, the barrier layer B1 and the buffer layer B2 can adopt one or more of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0105] For example, as illustrated in FIG. 23, the display substrate can further include a first gate insulating layer GI1 provided on the side of the active layer 1021 distal to the substrate 11, a second gate insulating layer GI2 provided on the side of the gate 1022 and the first capacitor electrode 1031 distal to the substrate 11, and an interlayer insulating layer IDL provided on the side of the second capacitor electrode 1032 distal to the substrate 11. For example, the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer IDL can employ one or more of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0106] For example, as illustrated in FIG. 23, the display substrate can further include a planarization layer PLN provided on the side of the source / drain electrodes 1023 / 1024 distal to the substrate 11, which can planarize the pixel driving circuit to form a relatively planar surface for providing the light emitting device layer M. For example, the pixel defining layer PDL can have a first via V1, and the planarization layer PLN can have a second via V2, and the spacer 16 can be electrically connected to at least one of the plurality of conductive patterns (illustrated as a signal line 101) through the first via V1 and the second via V2.

[0107] For example, in the case where the display substrate further includes a fourth conductive layer or more conductive layers, the display substrate can further include additional planarization layers to provide a planar surface. For example, each planarization layer can employ an organic insulating material such as polyimide or resin.

[0108] For example, the pixel defining layer PDL can employ one or more of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride; or in other embodiments, the pixel defining layer PDL can also employ one or more of organic insulating materials such as resin or polyimide.

[0109] For example, as illustrated in FIG. 23, the encapsulation layer EN can be an inorganic encapsulation layer, which can employ one or more of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. Further encapsulation layers such as an organic encapsulation layer and an inorganic encapsulation layer (not shown) can be formed on the encapsulation layer EN to form a composite encapsulation layer, in which the organic encapsulation layer can employ one or more of organic insulating materials such as resin or polyimide.

[0110] For example, in embodiments of the present disclosure, the substrate 11 can be a rigid substrate such as glass or quartz, or a flexible substrate such as polyimide or resin. The active layer 1021 of each transistor can be a semiconductor layer in various forms such as an amorphous silicon layer, a polysilicon layer, or a metal oxide semiconductor layer. For example, the polysilicon can be high-temperature polysilicon or low-temperature polysilicon, and the oxide semiconductor can be indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), or gallium zinc oxide (GZO).

[0111] For example, the gate electrode 1022 of each transistor can employ a metal material or an alloy material such as copper (Cu), aluminum (Al), titanium (Ti), or the like, for example, in a single-layer metal layer structure or a multi-layer metal layer structure, such as a multi-layer metal layer structure of titanium / aluminum / titanium or the like. The source / drain electrodes 1023 / 1024 of each transistor can employ a metal material or an alloy material such as copper (Cu), aluminum (Al), titanium (Ti), or the like, for example, in a single-layer metal layer structure or a multi-layer metal layer structure, such as a multi-layer metal layer structure of titanium / aluminum / titanium or the like.

[0112] For example, the material of the first electrode 13 can be a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), gallium zinc oxide (GZO), or the like, and the electrode material layer 15 can employ a metal material such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), or the like. Embodiments of the present disclosure do not make specific limitations on the materials of various structures.

[0113] At least one embodiment of the present disclosure further provides a preparation method of a display substrate, which can prepare the display substrate provided by embodiments of the present disclosure. For example, the preparation method is exemplarily introduced by taking the formation of a pixel unit as shown in FIG. 2, which includes a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 having different light-emitting colors.

[0114] For example, in some embodiments, with reference to FIGS. 7-12, the preparation method can include the following steps.

[0115] First, the substrate substrate 11 is provided, and then the driving circuit layer 12 is formed on the substrate substrate 11, for example, a plurality of pixel driving circuits of the driving circuit layer 12 can be formed on the substrate substrate 11 by using a patterning process. For example, a patterning process such as the formation of photoresist, exposure, development, and etching, etc. can be used, and specific details can be referred to related technologies, which will not be described here.

[0116] A plurality of first electrodes 13 can be formed on the side of the driving circuit layer 12 away from the substrate substrate 11 by using a patterning process, for example, the shapes and sizes of the first electrodes 13 corresponding to sub-pixels of different colors can be the same or different.

[0117] A pixel definition layer PDL can be formed on the side of the plurality of first electrodes 13 away from the substrate substrate 11 by using a patterning process, the pixel definition layer PDL includes a plurality of sub-pixel openings, the plurality of sub-pixel openings respectively expose the plurality of first electrodes 13, and the plurality of sub-pixel openings include a first sub-pixel opening P1, a second sub-pixel opening P2, and a third sub-pixel opening P3, the first sub-pixel opening P1, the second sub-pixel opening P2, and the third sub-pixel opening P3 are respectively used to form a light-emitting material layer 14 of different colors.

[0118] For example, in some embodiments, before forming the light-emitting material layer 14, a patterning process may be used to form an isolation pillar layer on the side of the pixel defining layer PDL away from the substrate 11. The isolation pillar layer includes at least one isolation pillar 16 for disconnecting the light-emitting material layer 14.

[0119] For example, a patterning process can be used to form an insulating layer 17 on the side of the isolation pillar 16 away from the substrate 11 for shielding signals, etc.

[0120] Subsequently, as shown in FIG13A, a first light-emitting material layer 141 is formed in at least a plurality of sub-pixel openings. For example, the first light-emitting material layer 141 is formed on the entire surface of the substrate 11. As shown in FIG13B, the portion of the first light-emitting material layer 141 located in the second sub-pixel opening P2 is removed, while the portions of the first light-emitting material layer 141 located in the first sub-pixel opening P1 and the third sub-pixel opening P3 are retained. At this time, the first light-emitting material layer 141 is formed in the first sub-pixel opening P1, and the material of the first light-emitting material layer 141 retained in the third sub-pixel opening P3 can serve as a sacrificial layer to prevent the first electrode 13 exposed in the third sub-pixel opening P3 from being unnecessarily etched in subsequent fabrication processes.

[0121] For example, in some other embodiments, in the steps of FIG13A and FIG13B, a first light-emitting material layer 141 and a first electrode material layer 151 (for forming the second electrode of the first sub-pixel SP1) can be sequentially formed in at least a plurality of sub-pixel openings (e.g., on the entire substrate 11). Then, the portions of the first light-emitting material layer 141 and the first electrode material layer 151 located in the second sub-pixel opening P2 are removed, while the portions of the first light-emitting material layer 141 and the first electrode material layer 151 located in the first sub-pixel opening P1 and the third sub-pixel opening P3 are retained. At this time, the material of the first light-emitting material layer 141 and the first electrode material layer 151 retained in the third sub-pixel opening P3 can serve as a sacrificial layer to prevent the first electrode 13 exposed in the third sub-pixel opening P3 from being unnecessarily etched in subsequent fabrication processes.

[0122] For example, in still other embodiments, in the steps of FIGS. 13A and 13B, the first light-emitting material layer 141, the first electrode material layer 151, and the first sub-encapsulation layer EN1 (for forming the encapsulation layer EN covering the first sub-pixel SP1) can be sequentially formed at least in the plurality of sub-pixel openings (e.g., on the entire substrate 11), and then, the portions of the first light-emitting material layer 141, the first electrode material layer 151, and the first sub-encapsulation layer EN1 located in the second sub-pixel opening P2 are removed, and the portions of the first light-emitting material layer 141, the first electrode material layer 151, and the first sub-encapsulation layer EN1 located in the first sub-pixel opening P1 and the third sub-pixel opening P3 are retained. At this time, the materials of the first light-emitting material layer 141, the first electrode material layer 151, and the first sub-encapsulation layer EN1 retained in the third sub-pixel opening P3 can act as a sacrificial layer to prevent the first electrode 13 exposed in the third sub-pixel opening P3 from being unnecessarily etched in subsequent preparation processes.

[0123] The cross section of the display substrate formed through the above steps is shown in FIGS. 14A-14C.

[0124] As shown in FIG. 14A, through the above steps, the materials of the first light-emitting material layer 141, the first electrode material layer 151, and the first sub-encapsulation layer EN1 are distributed in the regions of the first sub-pixel SP1 and the third sub-pixel SP3 as a whole, and are broken at the isolation column 16, and the isolation column 16 also has the materials of the first light-emitting material layer 141, the first electrode material layer 151, and the first sub-encapsulation layer EN1 thereon.

[0125] As shown in FIG. 14B, through the above steps, the first light-emitting material layer 141, the first electrode material layer 151, and the first sub-encapsulation layer EN1 located in the region of the second sub-pixel SP2 are removed, thereby exposing the first electrode 13 of the second sub-pixel SP2, at this time, the first electrode 13 of the second sub-pixel SP2 is over-etched once, and the portion of the isolation column 16 close to the first sub-pixel SP1 has the materials of the first light-emitting material layer 141, the first electrode material layer 151, and the first sub-encapsulation layer EN1 thereon.

[0126] As shown in FIG. 14C, through the above steps, the first light-emitting material layer 141, the first electrode material layer 151, and the first sub-encapsulation layer EN1 located in the region of the second sub-pixel SP2 are removed, and the portion of the isolation column 16 close to the third sub-pixel SP3 has the materials of the first light-emitting material layer 141, the first electrode material layer 151, and the first sub-encapsulation layer EN1 thereon.

[0127] For example, as shown in FIG. 15A, the second light-emitting material layer 142 is formed at least in the plurality of sub-pixel openings, for example, the second light-emitting material layer 142 is formed on the substrate 11 as a whole; as shown in FIG. 15B, the first light-emitting material layer 141 and the second light-emitting material layer 142 located in the third sub-pixel opening P3 are removed to expose the first electrode 13 of the second sub-pixel SP3, and the second light-emitting material layer 142 located in the first sub-pixel opening P1 and the second sub-pixel opening P2 is retained.

[0128] Thus, the second light-emitting material layer 142 is formed in the sub-pixel opening P2 of the second sub-pixel SP2, and the first light-emitting material layer 141 and the second light-emitting material layer 142 are sequentially stacked in the sub-pixel opening P1 of the first sub-pixel SP1, and the second light-emitting material layer 142 can prevent the first light-emitting material layer 141 of the first sub-pixel SP1 from being unnecessarily etched in the subsequent preparation process.

[0129] For example, in other embodiments, in the steps of FIGS. 15A and 15B, the second light-emitting material layer 142 and the second electrode material layer 152 (for forming the second electrode 15 of the second sub-pixel SP2) can be sequentially formed at least in the plurality of sub-pixel openings (for example, on the substrate 11 as a whole), and then the first light-emitting material layer 141, the first electrode material layer 151, the second light-emitting material layer 142 and the second electrode material layer 152 located in the third sub-pixel opening P3 are removed to expose the first electrode 13 of the second sub-pixel SP3, and the second light-emitting material layer 142 and the second electrode material layer 152 located in the first sub-pixel opening P1 and the second sub-pixel opening P2 are retained.

[0130] Thus, the second light-emitting material layer 142 and the second electrode 15 are formed in the sub-pixel opening P2 of the second sub-pixel SP2, and the first light-emitting material layer 141, the second electrode 15 of the first sub-pixel SP1, the second light-emitting material layer 142 and the second electrode material layer 152 are sequentially stacked in the sub-pixel opening P1 of the first sub-pixel SP1, and the second light-emitting material layer 142 and the second electrode material layer 152 can prevent the second electrode 15 of the first sub-pixel SP1 from being unnecessarily etched in the subsequent preparation process.

[0131] For example, in still other embodiments, in the steps of FIGS. 15A and 15B, the second light-emitting material layer 142, the second electrode material layer 152, and the second sub-encapsulation layer EN2 (an encapsulation layer EN for forming the second sub-pixel SP2) can be sequentially formed at least in the plurality of sub-pixel openings (e.g., on the entire substrate 11), and the portions of the first light-emitting material layer 141, the first electrode material layer 151, the first sub-encapsulation layer EN1, the second light-emitting material layer 142, the second electrode material layer 152, and the second sub-encapsulation layer EN2 located in the third sub-pixel opening P3 are removed to expose the first electrode 13 of the second sub-pixel SP3, and the portions of the second light-emitting material layer 142, the second electrode material layer 152, and the second sub-encapsulation layer EN2 located in the first sub-pixel opening P1 and the second sub-pixel opening P2 are retained.

[0132] Thus, the second light-emitting material layer 142, the second electrode 15, and the encapsulation layer EN are formed in the sub-pixel opening P2 of the second sub-pixel SP2, and the first light-emitting material layer 141, the second electrode 15 of the first sub-pixel SP1, and the encapsulation layer EN, the second light-emitting material layer 142, the second electrode material layer 152, and the second sub-encapsulation layer EN2 are sequentially stacked in the sub-pixel opening P1 of the first sub-pixel SP1, and the second light-emitting material layer 142, the second electrode material layer 152, and the second sub-encapsulation layer EN2 in the first sub-pixel opening P1 can prevent the encapsulation layer EN of the first sub-pixel SP1 from being unnecessarily etched in subsequent manufacturing processes.

[0133] The cross section of the display substrate formed by the above steps is shown in FIGS. 16A-16C.

[0134] As shown in FIG. 16A, since the first luminescent material layer 141, the first electrode material layer 151, the first sub-encapsulation layer EN1, the second luminescent material layer 142, the second electrode material layer 152 and the second sub-encapsulation layer EN2 in the third sub-pixel opening P3 need to be removed by one etching, the film layer number is relatively large, and thus the etching intensity is relatively high. At this time, the insulating layer 17 near the third sub-pixel opening P3 is etched, and thus a step is formed on the edge of the insulating layer 17 near the third sub-pixel opening P3, for example, a stepped shape is formed, as shown by the dashed line circle in FIG. 16A. In addition, since the first luminescent material layer 141, the first electrode material layer 151, the first sub-encapsulation layer EN1, the second luminescent material layer 142, the second electrode material layer 152 and the second sub-encapsulation layer EN2 are on the isolation column 16 near the first sub-pixel SP1, the film layer is relatively thick. At this time, the etching of the second luminescent material layer 142 on the side wall of the film layer may not be complete, and thus the material L1 of the second luminescent material layer 142 remains on the side wall. At this time, in the direction perpendicular to the substrate 11, the thickness of the material L1 of the second luminescent material layer remaining on the first isolation column 161 is less than the thickness of the second luminescent material layer 142. In the above process, the first electrode 13 of the third sub-pixel SP3 is etched once.

[0135] As shown in FIG. 16B, the region of the first sub-pixel SP1 forms the first luminescent material layer 141, the second electrode 15, the encapsulation layer EN, the second luminescent material layer 142, the second electrode material layer 152 and the second sub-encapsulation layer EN2 (for simplicity, the second luminescent material layer 142, the second electrode material layer 152 and the second sub-encapsulation layer EN2 are represented by one film layer in FIG. 16B), and the region of the second sub-pixel SP2 forms the second luminescent material layer 142, the second electrode 15 and the encapsulation layer EN. On the isolation column 16, the second luminescent material layer 142, the second electrode material layer 152 and the second sub-encapsulation layer EN2 cover the first luminescent material layer 141, the second electrode 15 and the encapsulation layer EN of the first sub-pixel SP1.

[0136] As shown in FIG. 16C, a stepped shape is formed on the edge of the insulating layer 17 near the third sub-pixel opening P3, as shown by the dashed line circle in FIG. 16C. On the isolation column 16, the second luminescent material layer 142, the second electrode 15 and the encapsulation layer EN are formed on the side near the second sub-pixel SP2.

[0137] For example, as shown in FIGS. 17A and 17B, at least the third light-emitting material layer 143 is formed in the plurality of sub-pixel openings, for example, the third light-emitting material layer 143 is formed on the entire substrate 11, and the portions of the third light-emitting material layer 143 located in the first sub-pixel opening P1 and the second sub-pixel opening P2 are removed, and the portions of the third light-emitting material layer 143 located in the third sub-pixel opening P3 are reserved. At this time, the first light-emitting material layer 141 of the first sub-pixel opening P1 and the second light-emitting material layer 142 of the second sub-pixel opening P2 are over-etched once.

[0138] For example, in other embodiments, in the steps of FIGS. 17A and 17B, the third light-emitting material layer 143 and the third electrode material layer 153 can be sequentially formed at least in the plurality of sub-pixel openings (for example, on the entire substrate 11), and the portions of the third light-emitting material layer 143 and the third electrode material layer 153 located in the first sub-pixel opening P1 and the second sub-pixel opening P2 are removed, and the portions of the third light-emitting material layer 143 and the third electrode material layer 153 located in the third sub-pixel opening P3 are reserved. At this time, the second electrode 15 of the first sub-pixel opening P1 and the second sub-pixel opening P2 is over-etched once.

[0139] For example, in still other embodiments, in the steps of FIGS. 17A and 17B, the third light-emitting material layer 143, the third electrode material layer 153, and the third sub-encapsulation layer EN3 can be sequentially formed at least in the plurality of sub-pixel openings (for example, on the entire substrate 11), and the portions of the third light-emitting material layer 143, the third electrode material layer 153, and the third sub-encapsulation layer EN3 located in the first sub-pixel opening P1 and the second sub-pixel opening P2 are removed, and the portions of the third light-emitting material layer 143, the third electrode material layer 153, and the third sub-encapsulation layer EN3 located in the third sub-pixel opening P3 are reserved. At this time, the encapsulation layer EN of the first sub-pixel opening P1 and the second sub-pixel opening P2 is over-etched once.

[0140] The cross section of the display substrate formed by the above steps is shown in FIGS. 7-9.

[0141] It can be seen that, in the above preparation process, the first electrode 13 of the second sub-pixel SP2 and the first electrode 13 of the third sub-pixel SP3 are both over-etched once, and the encapsulation layer EN of the first sub-pixel SP1 and the encapsulation layer EN of the second sub-pixel SP2 are both over-etched once. Compared with the traditional preparation process, the structures (for example, the first electrode 13 and the encapsulation layer EN) obtained by the preparation process are more uniform, and the phenomenon that a certain structure is over-etched multiple times is avoided, so that the above-mentioned electrode loss and the phenomenon that the second electrode 15 cannot be overlapped with the isolation column 16 can be solved.

[0142] For example, in other embodiments, corresponding to the embodiments of FIGS. 10-12, referring to FIGS. 18A and 18B, after the insulating layer 17 is formed, for example, the first light emitting material layer 141 is formed at least in the plurality of sub-pixel openings, for example, the first light emitting material layer 141 is formed on the entire substrate substrate 11, as shown in FIG. 18B, the portion of the first light emitting material layer 141 located in the second sub-pixel opening P2 is removed, and the portion of the first light emitting material layer 141 located in the first sub-pixel opening P1 and the third sub-pixel opening P3 is retained. At this time, the first light emitting material layer 141 is formed in the first sub-pixel opening P1, and the material of the first light emitting material layer 141 in the third sub-pixel opening P3 can act as a sacrificial layer to prevent the first electrode 13 exposed in the third sub-pixel opening P3 from being unnecessarily etched in the subsequent preparation process.

[0143] For example, in other embodiments, in the steps of FIGS. 18A and 18B, the first light emitting material layer 141 and the first electrode material layer 151 (used to form the second electrode of the first sub-pixel SP1) can be sequentially formed at least in the plurality of sub-pixel openings (for example, on the entire substrate substrate 11), and then the portion of the first light emitting material layer 141 and the first electrode material layer 151 located in the second sub-pixel opening P2 is removed, and the portion of the first light emitting material layer 141 and the first electrode material layer 151 located in the first sub-pixel opening P1 and the third sub-pixel opening P3 is retained. At this time, the first light emitting material layer 141 and the first electrode material layer 151 in the third sub-pixel opening P3 can act as a sacrificial layer to prevent the first electrode 13 exposed in the third sub-pixel opening P3 from being unnecessarily etched in the subsequent preparation process.

[0144] For example, in other embodiments, in the steps of FIGS. 18A and 18B, the first light emitting material layer 141, the first electrode material layer 151, and the first encapsulation layer EN1 (used to form the encapsulation layer EN covering the first sub-pixel SP1) can be sequentially formed at least in the plurality of sub-pixel openings (for example, on the entire substrate substrate 11), and then the portion of the first light emitting material layer 141, the first electrode material layer 151, and the first encapsulation layer EN1 located in the second sub-pixel opening P2 is removed, and the portion of the first light emitting material layer 141, the first electrode material layer 151, and the first encapsulation layer EN1 located in the first sub-pixel opening P1 and the third sub-pixel opening P3 is retained. At this time, the first light emitting material layer 141, the first electrode material layer 151, and the first encapsulation layer EN1 in the third sub-pixel opening P3 can act as a sacrificial layer to prevent the first electrode 13 exposed in the third sub-pixel opening P3 from being unnecessarily etched in the subsequent preparation process.

[0145] The cross section of the display substrate formed by the above steps is shown in FIGS. 19A-19C.

[0146] As shown in FIG. 19A, through the above steps, the materials of the first light-emitting material layer 141, the first electrode material layer 151 and the first sub-encapsulation layer EN1 are distributed in the regions of the first sub-pixel SP1 and the third sub-pixel SP3 as a whole, and are broken at the isolation column 16, and the isolation column 16 also has the materials of the first light-emitting material layer 141, the first electrode material layer 151 and the first sub-encapsulation layer EN1.

[0147] As shown in FIG. 19B, through the above steps, the first light-emitting material layer 141, the first electrode material layer 151 and the first sub-encapsulation layer EN1 located in the region of the second sub-pixel SP2 are removed, thereby exposing the first electrode 13 of the second sub-pixel SP2, at this time, the first electrode 13 of the second sub-pixel SP2 is over-etched once, and the part of the isolation column 16 close to the first sub-pixel SP1 has the materials of the first light-emitting material layer 141, the first electrode material layer 151 and the first sub-encapsulation layer EN1.

[0148] As shown in FIG. 19C, through the above steps, the first light-emitting material layer 141, the first electrode material layer 151 and the first sub-encapsulation layer EN1 located in the region of the second sub-pixel SP2 are removed, and the part of the isolation column 16 close to the third sub-pixel SP3 has the materials of the first light-emitting material layer 141, the first electrode material layer 151 and the first sub-encapsulation layer EN1.

[0149] For example, as shown in FIG. 20A, the second light-emitting material layer 142 is formed at least in the plurality of sub-pixel openings, for example, the second light-emitting material layer 142 is formed on the substrate 11 as a whole, as shown in FIG. 20B, the part of the first light-emitting material layer 141 and the second light-emitting material layer 142 located in the third sub-pixel opening P3 is removed to expose the first electrode 13 of the third sub-pixel SP3, and the part of the second light-emitting material layer 142 located in the first sub-pixel SP1 opening and the second sub-pixel SP2 opening is reserved.

[0150] Therefore, the second light-emitting material layer 142 is formed in the sub-pixel opening P2 of the second sub-pixel SP2, and the first light-emitting material layer 141 and the second light-emitting material layer 142 are sequentially superimposed in the sub-pixel opening P1 of the first sub-pixel SP1, and the second light-emitting material layer 142 can prevent the first light-emitting material layer 141 from being unnecessarily etched in the subsequent preparation process.

[0151] For example, in some other embodiments, in the steps of FIGS. 20A and 20B, the second light-emitting material layer 142 and the second electrode material layer 152 (for forming the second electrode 15 of the second sub-pixel SP2) can be sequentially formed at least in the plurality of sub-pixel openings (e.g., on the entire substrate 11), and the portions of the first light-emitting material layer 141, the first electrode material layer 151, the second light-emitting material layer 142, and the second electrode material layer 152 located in the third sub-pixel opening P3 are removed to expose the first electrode 13 of the third sub-pixel SP3, while the portions of the second light-emitting material layer 142 and the second electrode material layer 152 located in the first sub-pixel opening P1 and the second sub-pixel opening P2 are retained.

[0152] Thus, the second light-emitting material layer 142 and the second electrode 15 are formed in the sub-pixel opening P2 of the second sub-pixel SP2, and the first light-emitting material layer 141, the second electrode 15 of the first sub-pixel, the second light-emitting material layer 142, and the second electrode material layer 152 are sequentially stacked in the sub-pixel opening P1 of the first sub-pixel SP1. The second light-emitting material layer 142 and the second electrode material layer 152 can prevent the second electrode 15 of the first sub-pixel from being unnecessarily etched in subsequent manufacturing processes.

[0153] For example, in some other embodiments, in the steps of FIGS. 20A and 20B, the second light-emitting material layer 142, the second electrode material layer 152, and the second encapsulation layer EN2 (for forming the encapsulation layer EN of the second sub-pixel SP2) can be sequentially formed at least in the plurality of sub-pixel openings (e.g., on the entire substrate 11), and the portions of the first light-emitting material layer 141, the first electrode material layer 151, the first encapsulation layer EN1, the second light-emitting material layer 142, the second electrode material layer 152, and the second encapsulation layer EN2 located in the third sub-pixel opening P3 are removed to expose the first electrode 13 of the third sub-pixel SP3, while the portions of the second light-emitting material layer 142, the second electrode material layer 152, and the second encapsulation layer EN2 located in the first sub-pixel opening P1 and the second sub-pixel opening P2 are retained.

[0154] Thus, the second light-emitting material layer 142, the second electrode 15, and the encapsulation layer EN are formed in the sub-pixel opening P2 of the second sub-pixel SP2, and the first light-emitting material layer 141, the second electrode 15 of the first sub-pixel, and the encapsulation layer EN, the second light-emitting material layer 142, the second electrode material layer 152, and the second encapsulation layer EN2 are sequentially stacked in the sub-pixel opening P1 of the first sub-pixel SP1. The second light-emitting material layer 142, the second electrode material layer 152, and the second encapsulation layer EN2 can prevent the encapsulation layer EN of the first sub-pixel from being unnecessarily etched in subsequent manufacturing processes.

[0155] The cross section of the display substrate formed by the above steps is shown in FIGS. 21A-21C.

[0156] As shown in FIG. 21A, since the first light-emitting material layer 141, the first electrode material layer 151, the first sub-encapsulation layer EN1, the second light-emitting material layer 142, the second electrode material layer 152 and the second sub-encapsulation layer EN2 in the third sub-pixel opening P3 need to be removed by one etching, the film layer number is relatively large, and thus the etching intensity is relatively high. At this time, the insulating layer 17 near the third sub-pixel opening P3 is etched, and thus a step is formed at the edge of the insulating layer 17 near the third sub-pixel opening P3, as shown by the dashed line circle in FIG. 21A. In addition, since the first light-emitting material layer 141, the first electrode material layer 151, the first sub-encapsulation layer EN1, the second light-emitting material layer 142, the second electrode material layer 152 and the second sub-encapsulation layer EN2 are on the isolation column 16 near the first sub-pixel SP1, the film layer is relatively thick. At this time, the etching of the second light-emitting material layer 142 on the sidewall of the film layer may not be complete, and thus the material L1 of the second light-emitting material layer 142 remains on the sidewall. In the above process, the first electrode of the third sub-pixel SP3 is etched once.

[0157] As shown in FIG. 21B, the region of the first sub-pixel SP1 forms the first light-emitting material layer 141, the second electrode 15, the encapsulation layer EN, the second light-emitting material layer 142, the second electrode material layer 152 and the second sub-encapsulation layer EN2 (for simplicity, the second light-emitting material layer 142, the second electrode material layer 152 and the second sub-encapsulation layer EN2 are represented by one film layer in FIG. 16B), and the region of the second sub-pixel SP2 forms the second light-emitting material layer 142, the second electrode 15 and the encapsulation layer EN. On the isolation column 16, the second light-emitting material layer 142, the second electrode material layer 152 and the second sub-encapsulation layer EN2 cover the first light-emitting material layer 141, the second electrode 15 and the encapsulation layer EN of the first sub-pixel SP1.

[0158] As shown in FIG. 21C, a step is formed at the edge of the insulating layer 17 near the third sub-pixel opening P3, as shown by the dashed line circle in FIG. 21C. On the isolation column 16, the second light-emitting material layer 142, the second electrode 15 and the encapsulation layer EN are formed near the second sub-pixel SP2.

[0159] For example, as shown in FIGS. 22A and 22B, the third light-emitting material layer 143 is formed in at least a plurality of sub-pixel openings, for example, the third light-emitting material layer 143 is formed on the substrate 11, and the portions of the third light-emitting material layer 143 located in the first sub-pixel opening P1 and the second sub-pixel opening P2 are removed, and the portion of the third light-emitting material layer 143 located in the third sub-pixel opening P3 is retained.

[0160] For example, in some other embodiments, in the steps of FIGS. 22A and 22B, the third light-emitting material layer 143 and the third electrode material layer 153 can be sequentially formed at least in the plurality of sub-pixel openings (e.g., on the entire substrate 11), and the portions of the third light-emitting material layer 143 and the third electrode material layer 153 located at the first sub-pixel opening P1 and the second sub-pixel opening P2 are removed, and the portions of the third light-emitting material layer 143 and the third electrode material layer 153 located at the third sub-pixel opening P3 are retained.

[0161] For example, in some other embodiments, in the steps of FIGS. 22A and 22B, the third light-emitting material layer 143 and the third electrode material layer 153 can be sequentially formed at least in the plurality of sub-pixel openings (e.g., on the entire substrate 11), and the portions of the third light-emitting material layer 143 and the third electrode material layer 153 located at the first sub-pixel opening P1 and the second sub-pixel opening P2 are removed, and the portions of the third light-emitting material layer 143 and the third electrode material layer 153 located at the third sub-pixel opening P3 are retained.

[0162] For example, the cross section of the display substrate formed by the above steps is shown in FIGS. 10-12.

[0163] As shown in FIG. 10, since the whole of the third light-emitting material layer 143, the second electrode 15 and the encapsulation layer EN formed on the isolation column 16 has the first interval T1 with the whole of the first light-emitting material layer 141, the second electrode 15 and the encapsulation layer EN, when etching, the material L1 remaining on the sidewall of the first light-emitting material layer 141 and the upper surface of the insulating layer 17 are etched, so that the insulating layer 17 forms the first groove G1 at the first interval T1.

[0164] As shown in FIG. 11, since the whole of the first light-emitting material layer 141, the second electrode 15 and the encapsulation layer EN formed on the isolation column 16 has the second interval T2 with the whole of the second light-emitting material layer 142, the second electrode 15 and the encapsulation layer EN, when etching, the upper surface of the insulating layer 17 is etched, so that the insulating layer 17 forms the second groove G2 at the second interval T2.

[0165] As shown in FIG. 12, since the whole of the third light-emitting material layer 143, the second electrode 15 and the encapsulation layer EN formed on the isolation column 16 has the third interval T3 with the whole of the second light-emitting material layer 142, the second electrode 15 and the encapsulation layer EN, when etching, the upper surface of the insulating layer 17 is etched, so that the insulating layer 17 forms the third groove G3 at the third interval T3.

[0166] Similarly, in the above preparation process, the first electrode 13 of the second sub-pixel SP2 and the first electrode 13 of the third sub-pixel SP3 are each over-etched once, and the encapsulation layer EN of the first sub-pixel SP1 and the encapsulation layer EN of the second sub-pixel SP2 are each over-etched once. Compared with the conventional preparation process, the structures (such as the first electrode 13 and the encapsulation layer EN) obtained by the preparation process are more uniform, and the phenomenon that a certain structure is over-etched multiple times is avoided, so that the above-mentioned electrode loss and the phenomenon that the second electrode 15 cannot be overlapped with the isolation column 16 can be solved.

[0167] For example, in some embodiments, the first light-emitting material layer 141 reserved in the first sub-pixel SP1 opening, the second light-emitting material layer 142 reserved in the second sub-pixel SP2 opening, and the third light-emitting material layer 143 reserved in the third sub-pixel SP3 opening are respectively one of a red light-emitting material layer, a green light-emitting material layer, and a blue light-emitting material layer. For example, in some embodiments, the first light-emitting material layer 141 reserved in the first sub-pixel SP1 opening, the second light-emitting material layer 142 reserved in the second sub-pixel SP2 opening, and the third light-emitting material layer 143 reserved in the third sub-pixel SP3 opening are respectively a red light-emitting material layer, a green light-emitting material layer, and a blue light-emitting material layer; in other embodiments, the first light-emitting material layer 141 reserved in the first sub-pixel SP1 opening, the second light-emitting material layer 142 reserved in the second sub-pixel SP2 opening, and the third light-emitting material layer 143 reserved in the third sub-pixel SP3 opening are respectively a blue light-emitting material layer, a green light-emitting material layer, and a red light-emitting material layer, or other combinations, and the embodiments of the present disclosure are not limited thereto.

[0168] For example, in the above embodiments, the isolation column 16 is formed between any two adjacent ones of the first light-emitting material layer 141, the second light-emitting material layer 142, and the third light-emitting material layer 143, and the first light-emitting material layer 141, the second light-emitting material layer 142, and the third light-emitting material layer 143 are disconnected at at least one isolation column 16 to prevent color crosstalk between sub-pixels of different colors.

[0169] For example, in other embodiments, referring to FIG. 23, the driving circuit layer 12 includes a plurality of conductive patterns (such as the portions indicated by reference numerals 101-103, which will be described in detail later), and at least one isolation column 16 is formed to be electrically connected with at least one of the plurality of conductive patterns.

[0170] For example, forming the driving circuit layer 12 on the substrate 11 includes forming a transistor 102, a storage capacitor 103, and a plurality of signal lines 101, wherein the transistor 102 includes a gate 1021 and a source / drain electrode 1023 / 1024, the storage capacitor 103 includes a first capacitor electrode 1031 and a second capacitor electrode 1032, and the plurality of conductive patterns include the gate 1021, the source / drain electrode 1023 / 1024, the first capacitor electrode 1031, the second capacitor electrode 1032, and the plurality of signal lines 101.

[0171] For example, the plurality of conductive patterns of the driving circuit layer 12 form a pixel driving circuit of a plurality of sub-pixels. For example, FIG. 24 is a schematic circuit structure diagram of a pixel driving circuit provided by at least one embodiment of the present disclosure, as shown in FIG. 24, the pixel driving circuit includes a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C, at this time, the pixel driving circuit is formed as a 7T1C structure.

[0172] For example, as shown in FIG. 24, the first transistor T1 can be a first reset transistor T1, the second transistor T2 can be a threshold compensation transistor T2, the third transistor T3 can be a driving transistor T3, the fourth transistor T4 can be a data writing transistor T4, the fifth transistor T5 can be a second light-emitting control transistor T5, the sixth transistor T6 can be a first light-emitting control transistor T6, and the seventh transistor T7 can be a second reset control transistor T7.

[0173] For example, the first electrode of the first transistor T1 is connected to the N1 node, that is, electrically connected to the gate of the driving transistor T3, the second electrode of the first transistor T1 is connected to the first initial signal end Vinit1, that is, electrically connected to the first reset voltage line to receive a reset voltage, and the gate of the first transistor T1 is connected to the first reset signal end Re1, that is, electrically connected to the reset control signal line to receive a reset control signal.

[0174] The first electrode of the second transistor T2, that is, the threshold compensation transistor, is connected to the N1 node, that is, electrically connected to the gate of the driving transistor T3, the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, and the gate of the second transistor T2 is connected to the first gate driving signal end G1 to receive a compensation control signal.

[0175] The gate of the driving transistor T3 is connected to the N1 node, so as to be connected to the first capacitor electrode of the storage capacitor C, the first electrode of the first transistor T1, and the first electrode of the second transistor T2.

[0176] The first electrode of the fourth transistor T4, i.e. a data writing transistor, is connected to a data signal terminal Data to receive a data signal, the second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T3, and the gate electrode of the fourth transistor T4 is connected to a second gate driving signal terminal G2 to receive a scanning signal.

[0177] The first electrode of the fifth transistor T5, i.e. a second light emitting control transistor, is connected to a first power supply terminal VDD to receive a first power supply signal, the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and the gate electrode of the fifth transistor T5 is connected to a light emitting control signal terminal EM to receive a light emitting control signal.

[0178] The first electrode of the sixth transistor T6, i.e. a first light emitting control transistor, is connected to the second electrode of the driving transistor T3, the second electrode of the sixth transistor T6 is connected to the first electrode of the seventh transistor T7, and the gate electrode of the sixth transistor T6 is connected to the light emitting control signal terminal EM to receive the light emitting control signal.

[0179] The second electrode of the seventh transistor T7 is connected to a second initial signal terminal Vinit2, i.e. electrically connected to a second reset voltage signal line to receive a reset voltage, and the gate electrode of the seventh transistor T7 is connected to a second reset signal terminal Re2, i.e. electrically connected to a reset control signal line to receive a reset control signal.

[0180] The first capacitor electrode of the storage capacitor C is connected to the N1 node and electrically connected to the gate electrode of the driving transistor T3, and the second capacitor electrode of the storage capacitor C is connected to the first power supply terminal VDD, i.e. connected to the first power supply signal line.

[0181] The pixel driving circuit can be connected to a light emitting device, which can be an organic light emitting diode (OLED), and the pixel driving circuit is used to drive the light emitting device to emit light. The light emitting device can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS, for example, the anode of the light emitting device is connected to the second electrode of the sixth transistor T6, and the cathode of the light emitting device is connected to the second power supply terminal VSS, i.e. connected to the second power supply signal line.

[0182] For example, the first power supply signal line mentioned above refers to a signal line outputting a voltage signal VDD, which can be connected to a voltage source to output a constant voltage signal, such as a high level voltage signal. The second power supply signal line mentioned above refers to a signal line outputting a voltage signal VSS, which can be connected to a voltage source to output a constant voltage signal, such as a low level voltage signal.

[0183] For example, the scanning signal and the compensation control signal can be the same, i.e., the gate of the data writing transistor T4 and the gate of the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, so as to reduce the number of signal lines. For example, the gate of the data writing transistor T4 and the gate of the threshold compensation transistor T2 can also be electrically connected to different signal lines, i.e., the gate of the data writing transistor T4 is electrically connected to a second scanning signal line (second gate line), and the gate of the threshold compensation transistor T2 is electrically connected to a first scanning signal line (first gate line), and the signals transmitted by the first scanning signal line and the second scanning signal line can be the same or different, so that the gate of the data writing transistor T4 and the gate of the threshold compensation transistor T2 can be controlled separately, thereby increasing the flexibility of controlling the pixel driving circuit.

[0184] For example, the first light emitting control transistor T6 and the second light emitting control transistor T5 can input the same light emitting control signal, i.e., the gate of the first light emitting control transistor T6 and the gate of the second light emitting control transistor T5 can be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gate of the first light emitting control transistor T6 and the gate of the second light emitting control transistor T5 can also be electrically connected to different light emitting control signal lines, and the signals transmitted by the different light emitting control signal lines can be the same or different.

[0185] For example, the second reset transistor T7 and the first reset transistor T1 can input the same reset control signal, i.e., the gate of the second reset transistor T7 and the gate of the first reset transistor T1 can be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gate of the second reset transistor T7 and the gate of the first reset transistor T1 can also be electrically connected to different reset control signal lines, and the signals on the different reset control signal lines can be the same or different.

[0186] For example, the first transistor T1 and the second transistor T2 can be N-type transistors. For example, the first transistor T1 and the second transistor T2 can be N-type metal oxide transistors, which have a small leakage current, thereby avoiding the leakage of the N1 node through the first transistor T1 and the second transistor T2 in the light-emitting stage. Meanwhile, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors, for example, P-type low-temperature polysilicon transistors, which have a high carrier mobility, thereby facilitating the realization of a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal Vinit1 and the second initial signal terminal Vinit2 can output the same or different voltage signals according to actual conditions.

[0187] For example, the first transistor T1 to the seventh transistor T7 can be thin film transistors, field effect transistors, or various forms of transistors, and embodiments of the present disclosure do not make specific limitations thereon. For example, the first pole and the second pole of each transistor are the source-drain electrodes of the transistor, which are not structurally different and can be interchangeable.

[0188] For example, FIG. 25 is a timing diagram of the driving method of the pixel driving circuit in FIG. 24. For example, in FIG. 25, G1 represents the timing of the first gate driving signal terminal G1, G2 represents the timing of the second gate driving signal terminal G2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the light-emitting control signal terminal EM, and Data represents the timing of the data signal terminal Data.

[0189] For example, the driving method of the pixel driving circuit can include a first reset stage t1, a compensation stage t2, a second reset stage t3, and a light-emitting stage t4.

[0190] In the first reset stage t1, the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N1.

[0191] In the compensation stage t2, the first gate driving signal terminal G1 outputs a high-level signal, the second gate driving signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Data outputs a driving signal to write a voltage Vdata+Vth (i.e., the sum of the voltage Vdata and Vth) to the node N1, where Vdata is the voltage of the driving signal, and Vth is the threshold voltage of the driving transistor T3.

[0192] In the second reset stage t3: the second reset signal end Re2 outputs a low level signal, the seventh transistor T7 is turned on, and the second initial signal end Vinit2 inputs an initial signal to the second electrode of the sixth transistor T6.

[0193] In the light emitting stage t4: the light emitting control signal end EM outputs a low level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the storage capacitor C.

[0194] It should be noted that in the embodiments of the present disclosure, each pixel driving circuit can be a structure including other number of transistors, such as 7T2C structure, 6T1C structure, 6T2C structure, 8T1C structure or 9T2C structure, in addition to the 7T1C (i.e. seven transistors and one capacitor) structure shown in FIG. 2, and the embodiments of the present disclosure do not limit this.

[0195] For example, in some embodiments, the conductive pattern electrically connected with the isolation column 16 can be an initial signal end in the above-mentioned circuit, such as Vinit1 and Vinit2 in FIG. 24, at this time, the isolation column 16 can be connected with the second electrode (source-drain electrode) of the first transistor T1 and the second electrode (source-drain electrode) of the seventh transistor T7, thereby the isolation column 16 can serve as a reset voltage line; for example, in another embodiment, the conductive pattern electrically connected with the isolation column 16 can be a first power supply end in the above-mentioned circuit, for example, the isolation column 16 can be connected with the first electrode of the fifth transistor T5 and the second capacitor electrode of the storage capacitor C, for transmitting the first power supply signal VDD, thereby the isolation column 16 can serve as a first voltage line.

[0196] For example, in the case that the isolation column 16 serves as a reset voltage line, the electrical signal of the initial signal end is the same as the electrical signal of the second electrode 15 of the plurality of sub-pixels; in the case that the isolation column 16 serves as a first voltage line, the second electrode 15 of the plurality of sub-pixels needs to be disconnected at the isolation column 16, so that the isolation column 16 can only transmit the first power supply signal VDD, to prevent signal crosstalk.

[0197] Through the above-mentioned setting, the original reset voltage line or the first voltage line in the display substrate can be saved, the arrangement space of the original reset voltage line or the first voltage line is saved, and the arrangement of the conductive pattern in the pixel driving circuit layer is simpler.

[0198] For example, in still another embodiment, the conductive pattern electrically connected with the isolation column 16 can also be various signal lines in the above-mentioned pixel driving circuit, such as each scanning line, data line, etc., to reduce the signal transmission resistance thereof.

[0199] In summary, the preparation method provided by the embodiments of the present disclosure can be used to prepare the display substrate provided by the embodiments of the present disclosure. In the preparation process of the display substrate, the first electrode of at least part of the sub-pixels and the encapsulation layer are protected by the sacrificial layer, so as not to be over-etched for multiple times. The display substrate formed thereby has high uniformity, so as to improve the display effect of the display substrate. In addition, the isolation column 16 can have the functions of isolation and signal transmission at the same time, and can be reused as a signal line in some cases, so as to simplify the circuit arrangement of the display substrate.

[0200] The following points also need to be explained:

[0201] (1) The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0202] (2) In order to be clear, the thickness of the layer or area is enlarged or reduced in the drawings used to describe the embodiments of the present disclosure, that is, the drawings are not drawn according to the actual proportion. It can be understood that when an element such as a layer, a film, an area or a substrate is referred to as being located “on” or “under” another element, the element can be “directly” located on or under another element or there can be an intermediate element.

[0203] (3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0204] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate, comprising: a substrate substrate, a driving circuit layer disposed on the substrate substrate, a plurality of first electrodes disposed on a side of the driving circuit layer distal to the substrate substrate, a pixel defining layer disposed on a side of the plurality of first electrodes distal to the substrate substrate, comprising a plurality of sub-pixel openings, wherein the plurality of sub-pixel openings respectively expose the plurality of first electrodes, the plurality of sub-pixel openings comprise a first sub-pixel opening, a second sub-pixel opening and a third sub-pixel opening, the first sub-pixel opening, the second sub-pixel opening and the third sub-pixel opening have layers of light-emitting materials of different colors, a spacer column layer disposed on a side of the pixel defining layer distal to the substrate substrate, comprising a spacer column, wherein the spacer column is disposed between adjacent sub-pixel openings having layers of light-emitting materials of different colors, and an insulating layer disposed on a side of the spacer column layer distal to the substrate substrate, wherein at least part of a cross section of an edge portion of the insulating layer proximate to the third sub-pixel opening has a step. 2.The display substrate of claim 1, wherein, the edge portion comprises a first edge portion proximate to the third sub-pixel opening and a second edge portion located on a side of the first edge portion distal to the third sub-pixel opening, in a direction perpendicular to the substrate substrate, a thickness of the first edge portion is less than a thickness of the second edge portion. 3.The display substrate according to claim 1 or 2, wherein, the layers of light-emitting materials comprise a first layer of light-emitting materials, a second layer of light-emitting materials and a third layer of light-emitting materials, the first layer of light-emitting materials is disposed in the first sub-pixel opening, the second layer of light-emitting materials is disposed in the second sub-pixel opening, and the third layer of light-emitting materials is disposed in the third sub-pixel opening, the spacer column comprises a first spacer column disposed between adjacent first sub-pixels and third sub-pixels, the first spacer column has a material of the second layer of light-emitting materials thereon. 4.The display substrate of claim 3, wherein, in a direction perpendicular to the substrate substrate, a thickness of the material of the second layer of light-emitting materials on the first spacer column is less than a thickness of the second layer of light-emitting materials. 5.The display substrate according to claim 3 or 4, wherein, the first layer of light-emitting materials and the third layer of light-emitting materials overlap over the first spacer column. 6.The display substrate of claim 5, wherein, in an overlapping position, the third layer of light-emitting materials is located on a side of the first layer of light-emitting materials distal to the substrate substrate to overlap with the first layer of light-emitting materials in a direction perpendicular to the substrate substrate, achieving overlap. 7.The display substrate according to any one of claims 3-6, wherein, the material of the second layer of light-emitting materials is on a side of the first layer of light-emitting materials proximate to the third layer of light-emitting materials. 8.The display substrate according to any one of claims 3-7, wherein, the spacer column comprises a second spacer column disposed between adjacent first sub-pixels and second sub-pixels, the first layer of light-emitting materials and the second layer of light-emitting materials overlap over the second spacer column, in an overlapping position, the second layer of light-emitting materials is located on a side of the first layer of light-emitting materials distal to the substrate substrate to overlap with the first layer of light-emitting materials in a direction perpendicular to the substrate substrate, achieving overlap. 9.The display substrate of claim 8, wherein, The isolation column includes a third isolation column disposed between the adjacent second and third sub-pixels, the second and third light-emitting material layers overlap each other over the third isolation column, In the overlap position, the third light-emitting material layer is located on the side of the second light-emitting material layer away from the substrate, so as to overlap the second light-emitting material layer in the direction perpendicular to the substrate, thereby achieving the overlap. 10.The display substrate of claim 1, wherein, The light-emitting material layer includes a first light-emitting material layer, a second light-emitting material layer, and a third light-emitting material layer, The first light-emitting material layer is disposed in the first sub-pixel opening, the second light-emitting material layer is disposed in the second sub-pixel opening, and the third light-emitting material layer is disposed in the third sub-pixel opening, The isolation column includes a first isolation column disposed between the adjacent first and third sub-pixels, the first and third light-emitting material layers have a first interval over the first isolation column, The insulating layer on the first isolation column has a first groove at the first interval. 11.The display substrate of claim 10, wherein, The isolation column includes a second isolation column disposed between the adjacent first and second sub-pixels, the first and second light-emitting material layers have a second interval over the second isolation column, The insulating layer on the second isolation column has a second groove at the second interval. 12.The display substrate of claim 11, wherein, The isolation column includes a third isolation column disposed between the adjacent second and third sub-pixels, the second and third light-emitting material layers have a third interval over the third isolation column, The insulating layer on the third isolation column has a third groove at the third interval.

13. The display substrate according to any one of claims 1-12, wherein, The first, second, and third light-emitting material layers are one of a red light-emitting material layer, a green light-emitting material layer, and a blue light-emitting material layer, respectively.

14. A method for manufacturing a display substrate, comprising: providing a substrate, forming a driving circuit layer on the substrate, forming a plurality of first electrodes on a side of the driving circuit layer away from the substrate, forming a pixel defining layer on a side of the plurality of first electrodes away from the substrate, wherein the pixel defining layer includes a plurality of sub-pixel openings, the plurality of sub-pixel openings respectively expose the plurality of first electrodes, the plurality of sub-pixel openings include a first sub-pixel opening, a second sub-pixel opening, and a third sub-pixel opening, the first, second, and third sub-pixel openings are respectively used to form light-emitting material layers of different colors, and forming a first light-emitting material layer in at least the plurality of sub-pixel openings, and removing a portion of the first light-emitting material layer located in the second sub-pixel opening, and retaining portions of the first light-emitting material layer located in the first and third sub-pixel openings.

15. The method of claim 14, further comprising: forming a second light-emitting material layer in at least the plurality of sub-pixel openings, and removing portions of the first and second light-emitting material layers located in the third sub-pixel opening, leaving portions of the second light-emitting material layer located in the first and second sub-pixel openings.

16. The method of manufacturing of claim 15, further comprising: forming a third light-emitting material layer in at least the plurality of sub-pixel openings, and removing portions of the third light-emitting material layer located in the first and second sub-pixel openings, leaving portions of the third light-emitting material layer located in the third sub-pixel opening.

17. The method of making according to claim 14, wherein, forming a first light-emitting material layer in at least the plurality of sub-pixel openings, and removing portions of the first light-emitting material layer located in the second sub-pixel opening, leaving portions of the first light-emitting material layer located in the first and third sub-pixel openings, comprising: forming a first light-emitting material layer and a first electrode material layer in at least the plurality of sub-pixel openings in sequence, and removing portions of the first light-emitting material layer and the first electrode material layer located in the second sub-pixel opening, leaving portions of the first light-emitting material layer and the first electrode material layer located in the first and third sub-pixel openings.

18. The method of manufacturing of claim 17, further comprising: forming a second light-emitting material layer and a second electrode material layer in at least the plurality of sub-pixel openings in sequence, and removing portions of the first light-emitting material layer, the first electrode material layer, the second light-emitting material layer, and the second electrode material layer located in the third sub-pixel opening, leaving portions of the second light-emitting material layer and the second electrode material layer located in the first and second sub-pixel openings.

19. The method of manufacturing of claim 18, further comprising: forming a third light-emitting material layer and a third electrode material layer in at least the plurality of sub-pixel openings in sequence, and removing portions of the third light-emitting material layer and the third electrode material layer located in the first and second sub-pixel openings, leaving portions of the third light-emitting material layer and the third electrode material layer located in the third sub-pixel opening.

20. The method of making according to claim 14, wherein, forming a first light-emitting material layer in at least the plurality of sub-pixel openings, and removing portions of the first light-emitting material layer located in the second sub-pixel opening, leaving portions of the first light-emitting material layer located in the first and third sub-pixel openings, comprising: forming a first light-emitting material layer, a first electrode material layer, and a first sub-encapsulation layer in at least the plurality of sub-pixel openings in sequence, and removing portions of the first light-emitting material layer, the first electrode material layer, and the first sub-encapsulation layer located in the second sub-pixel opening, leaving portions of the first light-emitting material layer, the first electrode material layer, and the first sub-encapsulation layer located in the first and third sub-pixel openings.

21. The method of manufacturing of claim 20, further comprising: forming, in the plurality of sub-pixel openings, a second light-emitting material layer, a second electrode material layer and a second sub-packaging layer in sequence, and removing portions of the first light-emitting material layer, the first electrode material layer, the first sub-packaging layer, the second light-emitting material layer, the second electrode material layer and the second sub-packaging layer located in the third sub-pixel opening, while retaining portions of the second light-emitting material layer, the second electrode material layer and the second sub-packaging layer located in the first sub-pixel opening and the second sub-pixel opening.

22. The manufacturing method of claim 21, further comprising: forming, in the plurality of sub-pixel openings, a third light-emitting material layer, a third electrode material layer and a third sub-packaging layer in sequence, and removing portions of the third light-emitting material layer, the third electrode material layer and the third sub-packaging layer located in the first sub-pixel opening and the second sub-pixel opening, while retaining portions of the third light-emitting material layer, the third electrode material layer and the third sub-packaging layer located in the third sub-pixel opening. The first light-emitting material layer retained in the first sub-pixel opening, the second light-emitting material layer retained in the second sub-pixel opening and the third light-emitting material layer retained in the third sub-pixel opening are one of a red light-emitting material layer, a green light-emitting material layer and a blue light-emitting material layer, respectively.

23. The method of making according to claim 16, 20, or 22, wherein, Before forming the first light-emitting material layer in the plurality of sub-pixel openings, the manufacturing method further comprises:

24. The method of manufacturing according to claim 14, wherein, forming, on a side of the pixel defining layer distal to the substrate, an isolation column layer comprising at least one isolation column, wherein, after forming the first light-emitting material layer in the plurality of sub-pixel openings, the first light-emitting material layer is broken at the at least one isolation column. The drive circuit layer comprises a plurality of conductive patterns, and the at least one isolation column is formed to electrically connect with at least one of the plurality of conductive patterns.

25. The method of manufacturing according to claim 24, wherein, The at least one isolation column is formed between any two adjacent ones of the first light-emitting material layer, the second light-emitting material layer and the third light-emitting material layer, respectively, and the first light-emitting material layer, the second light-emitting material layer and the third light-emitting material layer are broken at the at least one isolation column.

26. The method of manufacturing according to claim 24, wherein, forming, on the substrate, a drive circuit layer comprising a transistor, a storage capacitor and a plurality of signal lines, wherein the transistor comprises a gate and a source-drain electrode, and the storage capacitor comprises a first capacitor electrode and a second capacitor electrode, 27. The method of making according to claim 25, wherein, The plurality of conductive patterns comprises the gate, the source-drain electrode, the first capacitor electrode, the second capacitor electrode and the plurality of signal lines. ​

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