Low-power-consumption self-biased slew-rate-enhanced circuit and integrator

Abstract

The present application discloses a low-power-consumption self-biased slew-rate-enhanced circuit and an integrator. The enhanced circuit comprises: a self-biased control circuit used for outputting a bias voltage on the basis of an output voltage of an input voltage measurement circuit; the input voltage measurement circuit connected to the self-biased control circuit and used for measuring the magnitude of a differential input voltage; and a slew rate control circuit used for providing, when the voltage of a differential input voltage end exceeds a starting voltage, a sourcing current or a sinking current for an output end of an operational amplifier, and when the voltage of the differential input voltage end does not exceed the starting voltage, not generating an additional current or not generating a slew rate enhancement effect. In the present invention, an additional bias voltage or bias current does not need to be input, a static current is not consumed when the function of the slew-rate-enhanced circuit is not enabled, and a static bias current of an operational amplifier does not need to be increased when the slew-rate-enhanced circuit is started, so that fast charging and discharging of a large capacitance load can be achieved without affecting a small signal frequency domain characteristic of the operational amplifier, and a bidirectional slew rate of the operational amplifier is enhanced, thereby meeting low-power consumption and high-speed design requirements of an integrated circuit.

Description

Low-power self-biased slew rate enhancement circuit and integrator TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and in particular, to a low-power self-biased slew rate enhancement circuit and integrator. BACKGROUND

[0002] Slew rate and the slew rate of the output voltage of the operational amplifier are important parameters for measuring the speed of the operational amplifier when a large amplitude signal is applied, which is defined as the slope of the linear stage of the output change of the operational amplifier when a large amplitude step signal is input, and is related to the static working current and the load capacitance, as follows

[0003] The operational amplifier is a key circuit unit of the switched capacitor circuit, for example, the switched capacitor circuit in the Sigma-Delta integrator is composed of an operational amplifier and a switched capacitor circuit, wherein the sampling capacitor and the integration capacitor both contribute to the load capacitance, and therefore the operational amplifier is required to have a large enough slew rate to realize the rapid transfer of charges between the capacitors.

[0004] The existing slew rate enhancement technology is realized by increasing the static working current of the operational amplifier, which increases the power consumption, and at the same time, since the current acts on the devices of the entire amplifier, there are certain requirements for the length and width of the devices, which not only increases the chip area but also limits the realization of other important indicators. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a low-power self-biased slew rate enhancement circuit and integrator, which is used to solve at least one problem existing in the prior art.

[0006] To achieve the above-mentioned purposes and other related purposes, the present application provides a low-power self-biased slew rate enhancement circuit, which comprises a differential input voltage end Vin+ and Vin-, a differential output voltage end Vout+ and Vout-, a self-biasing control circuit, an input voltage detection circuit and a slew rate control circuit, wherein the differential input voltage end Vin+ and Vin- are used to connect the differential input voltage end of the operational amplifier, and the differential output voltage end Vout+ and Vout- are used to connect the differential output voltage end of the operational amplifier.

[0007] The self-biasing control circuit has an input end connected to the output end of the input voltage detection circuit, and outputs a bias voltage based on the output voltage of the input voltage detection circuit.

[0008] The input voltage detection circuit is connected with the output end of the self-bias control circuit and the differential input voltage end respectively; the output end of the input voltage detection circuit is connected with the input end of the self-bias control circuit and the input end of the slew rate control circuit respectively;

[0009] The slew rate control circuit is connected with the differential output voltage end Vout+ and Vout-, and is used for providing pull current or fill current for the output end of the operational amplifier when the output voltage of the differential input voltage end Vin+ and Vin- exceeds the opening voltage, so as to enhance the rising edge slew rate or the falling edge slew rate, and otherwise no additional current is generated, and no slew rate enhancement effect is generated.

[0010] In an embodiment of the present application, the self-bias control circuit first bias circuit and second bias circuit, the input voltage detection circuit includes first detection circuit and second detection circuit;

[0011] The first bias circuit receives the output of the first detection circuit, and generates a first bias voltage connected to the first detection circuit, so as to provide bias current for the first detection circuit;

[0012] The second bias circuit receives the output of the second detection circuit, and generates a second bias voltage connected to the second detection circuit, so as to provide bias current for the second detection circuit;

[0013] The first detection circuit includes a first input end and a second input end connected with the differential input voltage end Vin+ and Vin- respectively;

[0014] The second detection circuit includes a third input end and a fourth input end connected with the differential input voltage end Vin- and Vin+ respectively;

[0015] In an embodiment of the present application, the slew rate control circuit includes a first control circuit and a second control circuit, the first input end of the first control circuit is connected with the output end of the first detection circuit, the second input end of the first control circuit is connected with the output end of the second detection circuit, the first input end of the second control circuit is connected with the first output end of the second detection circuit, and the second input end of the second control circuit is connected with the second output end of the first detection circuit.

[0016] In an embodiment of the present application, the first bias circuit comprises a first PMOS transistor M7a and a first NMOS transistor M6a, the gate of the first PMOS transistor M7a is connected to the output terminal of the first detection circuit, the source of the first PMOS transistor M7a is connected to a power supply voltage, the drain of the first PMOS transistor M7a is connected to the drain of the first NMOS transistor M6a, the source of the first NMOS transistor M6a is connected to ground, the first NMOS transistor M6a is in diode connection, the gate of the first NMOS transistor M6a is connected to the first detection circuit to provide bias current for the first detection circuit; the second bias circuit comprises a second PMOS transistor M7b and a second NMOS transistor M6b, the gate of the second PMOS transistor M7b is connected to the output terminal of the second detection circuit, the source of the second PMOS transistor M7b is connected to a power supply voltage, the drain of the second PMOS transistor M7b is connected to the drain of the second NMOS transistor M6b, the source of the second NMOS transistor M6b is connected to ground, the second NMOS transistor M6b is in diode connection, the gate of the second NMOS transistor M6b is connected to the second detection circuit to provide bias current for the second detection circuit.

[0017] In an embodiment of the present application, the first detection circuit comprises a third NMOS transistor M5a, a fourth NMOS transistor M1a, a fifth NMOS transistor M2a, a third PMOS transistor M3a, and a fourth PMOS transistor M4a; the gate of the third NMOS transistor M5a is connected to the gate of the first NMOS transistor, the source of the third NMOS transistor M5a is grounded, the drain of the third NMOS transistor M5a is connected to the source of the fourth NMOS transistor and the source of the fifth NMOS transistor M2a respectively, the gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor M2a are connected to the differential input voltage terminal Vin+ and Vin- respectively, the drain of the fourth NMOS transistor is connected to the drain of the third PMOS transistor M3a, the third PMOS transistor M3a is connected in diode mode, the source of the third PMOS transistor M3a is connected to the power supply voltage, the drain of the fifth NMOS transistor M2a is connected to the drain of the fourth PMOS transistor M4a and forms the output terminal of the first detection circuit, the gate of the fourth PMOS transistor M4a is connected to the gate of the third NMOS transistor M5a, and the source of the fourth PMOS transistor M4a is connected to the power supply voltage; the second detection circuit comprises a sixth NMOS transistor M5b, a seventh NMOS transistor M1b, an eighth NMOS transistor M2b, a fifth PMOS transistor M3b, and a sixth PMOS transistor M4b; the gate of the sixth NMOS transistor M5b is connected to the gate of the second NMOS transistor, the source of the sixth NMOS transistor M5b is grounded, the drain of the sixth NMOS transistor M5b is connected to the source of the seventh NMOS transistor M1b and the source of the eighth NMOS transistor M2b respectively, the gate of the seventh NMOS transistor M1b and the gate of the eighth NMOS transistor M2b are connected to the differential input voltage terminal Vin+ and Vin- respectively, the drain of the seventh NMOS transistor M1b is connected to the drain of the fifth PMOS transistor M3b, the fifth PMOS transistor M3b is connected in diode mode, the source of the fifth PMOS transistor M3b is connected to the power supply voltage, the drain of the eighth NMOS transistor M2b is connected to the drain of the sixth PMOS transistor M4b and forms the second output terminal of the second detection circuit, the gate of the fifth PMOS transistor M3b is connected to the gate of the sixth PMOS transistor M4b, and the source of the sixth PMOS transistor M4b is connected to the power supply voltage.

[0018] In an embodiment of the present application, the first control circuit comprises a ninth NMOS transistor M1n, a tenth NMOS transistor M4n, a seventh PMOS transistor M1p and an eighth PMOS transistor M4p, the source of the seventh PMOS transistor M1p is connected to a power supply voltage, the gate of the seventh PMOS transistor M1p is connected to the output terminal of the first detection circuit, the drain of the seventh PMOS transistor M1p is connected to the drain of the ninth NMOS transistor M1n, the source of the ninth NMOS transistor M1n is connected to ground, the ninth NMOS transistor M1n is in diode connection, the source of the eighth PMOS transistor M4p is connected to the power supply voltage, the gate of the eighth PMOS transistor M4p is connected to the output terminal of the second detection circuit, the drain of the eighth PMOS transistor M4p is connected to the drain of the tenth NMOS transistor M4n and the differential output voltage terminal Vout+, the source of the tenth NMOS transistor M4n is connected to ground, and the gate of the tenth NMOS transistor M4n is connected to the drain of the ninth NMOS transistor M1n; the second control circuit comprises an eleventh NMOS transistor M2n, a twelfth NMOS transistor M3n, a ninth PMOS transistor M2p and a tenth PMOS transistor M3p, the source of the ninth PMOS transistor M2p is connected to the power supply voltage, the gate of the ninth PMOS transistor M2p is connected to the output terminal of the second detection circuit, the drain of the ninth NMOS transistor M1n is connected to the drain of the eleventh NMOS transistor M2n, the source of the eleventh NMOS transistor M2n is connected to ground, the eleventh NMOS transistor M2n is in diode connection, the source of the tenth PMOS transistor M3p is connected to the power supply voltage, the gate of the tenth PMOS transistor M3p is connected to the output terminal of the first detection circuit, the drain of the tenth PMOS transistor M3p is connected to the drain of the twelfth NMOS transistor M3n and the differential output voltage terminal Vout-, the source of the twelfth NMOS transistor M3n is connected to ground, and the gate of the twelfth NMOS transistor M3n is connected to the drain of the eleventh NMOS transistor M2n.

[0019] In an embodiment of the present application, the first bias circuit comprises a first PMOS transistor M6a and a first NMOS transistor M7a, the first PMOS transistor M6a is in diode connection, the source of the first PMOS transistor M6a is connected to a power supply voltage, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor M7a, the source of the first NMOS transistor M7a is connected to ground, the gate of the first NMOS transistor M7a is connected to the output terminal of the first detection circuit, and the gate of the first PMOS transistor M6a is connected to the first detection circuit to provide a bias current for the first detection circuit.

[0020] The second bias circuit comprises a second PMOS tube M6b and a second NMOS tube M7b, the second PMOS tube M6b is connected in a diode mode, the source of the second PMOS tube M6b is connected to a power supply voltage, the drain of the second PMOS tube is connected to the drain of the second NMOS tube M7b, the source of the second NMOS tube M7b is connected to ground, the gate of the second NMOS tube M7b is connected to the output terminal of the first detection circuit, and the gate of the second PMOS tube is connected to the first detection circuit to provide a bias current for the first detection circuit.

[0021] In an embodiment of the present application, the first detection circuit comprises a third NMOS tube M3a, a fourth NMOS tube M4a, a third PMOS tube M5a, a fourth PMOS tube M1a and a fifth PMOS tube M2a, the source of the third PMOS tube M5a is connected to a power supply voltage, the gate of the third PMOS tube M5a is connected to the gate of the first PMOS tube M6a, the drain of the third PMOS tube M5a is connected to the source of the fourth PMOS tube M1a and the source of the fifth PMOS tube M2a respectively, the gate of the fourth PMOS tube M1a and the gate of the fifth PMOS tube M2a are connected to a differential input voltage terminal Vin+ and Vin- respectively, the drain of the fourth PMOS tube M1a is connected to the drain of the third NMOS tube M3a, the source of the third NMOS tube M3a is connected to ground, the third NMOS tube M3a is connected in a diode mode, the drain of the fifth PMOS tube M2a is connected to the drain of the fourth NMOS tube M4a, the gate of the fourth NMOS tube M4a is connected to the gate of the third NMOS tube M3a, and the source of the fourth NMOS tube M4a is connected to ground.

[0022] The second detection circuit comprises a fifth NMOS tube M3b, a sixth NMOS tube M4b, a sixth PMOS tube M5b, a seventh PMOS tube M1b and an eighth PMOS tube M2b, the source of the sixth PMOS tube M5b is connected to a power supply voltage, the gate of the sixth PMOS tube M5b is connected to the gate of the second PMOS tube M6b, the drain of the sixth PMOS tube M5b is connected to the source of the seventh PMOS tube M1b and the source of the eighth PMOS tube M2b respectively, the gate of the seventh PMOS tube M1b and the gate of the eighth PMOS tube M2b are connected to a differential input voltage terminal Vin+ and Vin- respectively, the drain of the seventh PMOS tube M1b is connected to the drain of the fifth NMOS tube M3b, the source of the fifth NMOS tube M3b is connected to ground, the fifth NMOS tube M3b is connected in a diode mode, the drain of the eighth PMOS tube M2b is connected to the drain of the sixth NMOS tube M4b, the gate of the sixth NMOS tube M4b is connected to the gate of the fifth NMOS tube M3b, and the source of the sixth NMOS tube M4b is connected to ground.

[0023] In an embodiment of the present application, the first control circuit comprises a ninth PMOS transistor M1p, a tenth PMOS transistor M4p, a seventh NMOS transistor M1n and an eighth NMOS transistor M4n, the ninth PMOS transistor M1p is in diode connection, the source of the ninth PMOS transistor M1p is connected to a power supply voltage, the drain of the ninth PMOS transistor M1p is connected to the drain of the seventh NMOS transistor M1n, the source of the seventh NMOS transistor M1n is connected to ground, the gate of the seventh NMOS transistor M1n is connected to the output of the first detection circuit, the source of the tenth PMOS transistor M4p is connected to the power supply voltage, the gate of the tenth PMOS transistor M4p is connected to the drain of the ninth PMOS transistor M1p, the drain of the tenth PMOS transistor M4p is connected to the drain of the eighth NMOS transistor M4n and the differential output voltage terminal Vout+, and the gate of the eighth NMOS transistor M4n is connected to the output of the second detection circuit, and the source of the eighth NMOS transistor M4n is connected to ground.

[0024] The first control circuit comprises an eleventh PMOS transistor M2p, a twelfth PMOS transistor M3p, a ninth NMOS transistor M2n and a tenth NMOS transistor M3n, the eleventh PMOS transistor M2p is in diode connection, the source of the eleventh PMOS transistor M2p is connected to a power supply voltage, the drain of the eleventh PMOS transistor M2p is connected to the drain of the ninth NMOS transistor M2n, the source of the ninth NMOS transistor M2n is connected to ground, the gate of the ninth NMOS transistor M2n is connected to the second output of the first detection circuit, the source of the twelfth PMOS transistor M3p is connected to a power supply voltage, the gate of the twelfth PMOS transistor M3p is connected to the drain of the eleventh PMOS transistor M2p, the drain of the twelfth PMOS transistor M3p is connected to the drain of the tenth NMOS transistor M3n and the differential output voltage terminal Vout-, the gate of the tenth NMOS transistor M3n is connected to the first output of the second detection circuit, and the source of the tenth NMOS transistor M3n is connected to ground.

[0025] To achieve the above object and other related objects, the present application provides an integrator comprising the low-power self-biased slew rate enhancement circuit, an operational amplifier and a switched capacitor; the switched capacitor is differential, and its single end comprises first to fourth switches S1-S4, a sampling capacitor Cs and an integration capacitor C1.

[0026] The first switch S1 and the second switch S2 are controlled by a sampling phase timing Φ1, the third switch S3 and the fourth switch S4 are controlled by an integration phase timing Φ2, one end of the first switch S1 is connected with an integrator input voltage VP, the other end of the first switch S1 is connected with a lower plate of a sampling capacitor Cs, two ends of the second switch S2 are connected with an upper plate of the sampling capacitor Cs and a common-mode voltage Vcm respectively, two ends of the third switch S3 are connected with the lower plate of the sampling capacitor Cs and the common-mode voltage Vcm respectively, two ends of the fourth switch S4 are connected with the upper plate of the sampling capacitor Cs and an input end Vin+ of an operational amplifier respectively, and an integration capacitor C1 is connected between the input end Vin+ and an output end Vout- of the operational amplifier; the low-power self-bias slew rate enhancement circuit is differential, differential input voltage ends Vin+ and Vin- are connected with differential input voltage ends Vin+ and Vin- of the operational amplifier respectively, and differential output voltage ends Vin+ and Vin- are connected with differential output voltage ends Vout- and Vout+ of the operational amplifier respectively.

[0027] As described above, the low-power self-bias slew rate enhancement circuit has the following beneficial effects:

[0028] The low-power self-bias slew rate enhancement circuit comprises differential input voltage ends Vin+ and Vin-, differential output voltage ends Vout+ and Vout-, a self-bias control circuit, an input voltage detection circuit and a slew rate control circuit, the differential input voltage ends Vin+ and Vin- are used for connecting differential input voltage ends of an operational amplifier, and the differential output voltage ends Vout+ and Vout- are used for connecting differential output voltage ends of the operational amplifier; the input end of the self-bias control circuit is connected with an output end of the input voltage detection circuit, and a bias voltage is output based on an output voltage of the input voltage detection circuit; the input end of the input voltage detection circuit is connected with an output end of the self-bias control circuit and the differential input voltage ends respectively; the output end of the input voltage detection circuit is connected with the input end of the self-bias control circuit and an input end of the slew rate control circuit respectively; the slew rate control circuit is connected with the differential output voltage ends Vout+ and Vout-, and is used for providing pull current or fill current for output ends of the operational amplifier when output voltages of the differential input voltage ends Vin+ and Vin- exceed an opening voltage, so as to enhance rising edge slew rate or falling edge slew rate, and otherwise no additional current is generated and no slew rate enhancement effect is generated. The present application does not need additional bias voltage or bias current input, does not consume static current when the slew rate enhancement circuit function is not opened, and does not need to increase static bias current of the operational amplifier when the slew rate enhancement circuit is opened, so that fast charge and discharge of a large-capacitance load can be realized without affecting small signal frequency domain characteristics of the operational amplifier, bidirectional slew rate of the operational amplifier is enhanced, and the design requirements of low power and high speed of an integrated circuit are met.

[0029] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0031] FIG. 1 is a low-power self-bias swing enhancement circuit architecture block diagram of an embodiment of the present application;

[0032] FIG. 2 is a low-power self-bias swing enhancement circuit schematic diagram of an NMOS input pair of an embodiment of the present application;

[0033] FIG. 3 is a low-power self-bias swing enhancement circuit schematic diagram of a PMOS input pair of an embodiment of the present application.

[0034] FIG. 4 is an application example of a self-bias swing enhancement circuit in a Sigma-Delta switched-capacitor integrator of an embodiment of the present application; DETAILED DESCRIPTION

[0035] The specific embodiments of the present application will be described below with reference to the drawings, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the specification. The present application can also be implemented or applied by different specific embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0036] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner, and the diagrams only show the components related to the present application, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be arbitrarily changed in type, number and proportion, and the layout pattern of the components may also be more complex.

[0037] Although the terms "first", "second", "A", and "B" and the like can be used herein to describe various elements, these elements should not be limited by these terms, and are only used to distinguish one element from another element. For example, without departing from the scope of the technology described below, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element. The term "and / or" includes a combination of related items or any of the related items.

[0038] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be understood that the term "comprises" means "comprising," "includes," "containing," "having" and the like, but excludes "consisting only of." It will be further understood that terms, such as, for example, "element", "component", "member", "device", "means", "step", "operation", "feature", "element" and the like, utilized throughout this disclosure, refer to a singular structure or substance, or multiple structures or substances that can used separately or in combination with one another, unless the context clearly indicates otherwise. In addition, as used herein, the term "if" can be construed to mean "when" or "when a condition is met" except where the context clearly indicates otherwise.

[0039] Before the detailed description of the drawings, it is intended that the division of components in the present specification is divided only by the main function of each component. That is, two or more components to be described below can be combined into one component, or can be divided into two or more components according to a more detailed function. In addition to the main function of the component, each component to be described below can additionally perform some or all of the functions of other components, and some of the main functions of each component can be performed exclusively by other components.

[0040] FIG. 1 is a schematic diagram of an architecture of a low-power self-biased slew rate enhancement circuit according to an embodiment of the present application, which can be used in an integrator including an operational amplifier, the low-power self-biased slew rate enhancement circuit including differential input voltage terminals Vin+ and Vin-, differential output voltage terminals Vout+ and Vout-, a self-bias control circuit 21, an input voltage detection circuit 22, and a slew rate control circuit 23; the differential input voltage terminals Vin+ and Vin- are used to connect differential input voltage terminals of the operational amplifier, and the differential output voltage terminals Vout+ and Vout- are used to connect differential output voltage terminals of the operational amplifier;

[0041] The self-bias control circuit 21 includes a first bias circuit 211 and a second bias circuit 212, and is used to provide current of the low-power self-biased slew rate enhancement circuit and to control according to an output of the voltage detection circuit; when the differential input voltage terminals Vin+ and Vin- do not exceed an on voltage, the low-power self-biased slew rate enhancement circuit has no current consumption, and otherwise, the low-power self-biased slew rate enhancement circuit consumes current;

[0042] The input voltage detection circuit 22 includes a first detection circuit 221 and a second detection circuit 222, and is connected to the differential input voltage terminals Vin+ and Vin- to detect whether a difference between the Vin+ and Vin- exceeds an on voltage, and an output voltage is connected to the self-bias circuit and the slew rate control circuit;

[0043] The slew rate control circuit 23 comprises a first control circuit 231 and a second control circuit 232; the slew rate control circuit is connected with the differential output voltage terminals Vout+ and Vout-; when the differential input voltage terminals Vin+ and Vin- exceed the start voltage, the first control circuit 231 and the second control circuit 232 provide extra pull current or sink current to the main operational amplifier output terminal, so as to enhance the rising edge slew rate or the falling edge slew rate, and vice versa, no extra current is provided, and no slew rate enhancement effect is generated.

[0044] The first input terminal and the second input terminal of the first detection circuit 221 are respectively connected with the differential input signals Vin+ and Vin- of the operational amplifier, the third input terminal is connected with the output V BIAS1 of the first bias circuit 211, A the output is VB, which is input to the first bias circuit 211, and is simultaneously connected to the first input terminal of the first control circuit 231 and the second input terminal of the second control circuit 232.

[0045] The first input terminal and the second input terminal of the second detection circuit 222 are respectively connected with the differential input signals Vin- and Vin+ of the operational amplifier, the third input terminal is connected with the output V BIAS2 of the second bias circuit 212, + the output is VB, which is input to the second bias circuit 212, and is simultaneously connected to the second input terminal of the first control circuit 231 and the first input terminal of the second control circuit 232. The outputs of the first control circuit 231 and the second control circuit 232 are connected with the differential output signals Vout+ and Vout- of the operational amplifier.

[0046] When the input differential signal |Vin P | < V A , the output V BIAS1 of the first detection circuit 221 makes the first bias circuit 211 not generate current, and the generated bias voltage V B makes the first detection circuit 221 not have current, the output V BIAS2 of the second detection circuit 222 makes the second bias circuit 212 not generate current, and the generated bias voltage V A makes the second detection circuit 222 not have current, and V B and V in+ control the first control circuit 231 and the second control circuit 232, so that the first control circuit 231 and the second control circuit 232 do not generate current, and cannot directly provide extra current of the output voltage terminals Vout+ and Vout- to the output node of the operational amplifier, the self-bias slew rate enhancement amplifier circuit does not work, and does not consume current.

[0047] When the input differential signal V in- -V PWhen the input differential signal V

[0048] When the input differential signal V in- -V in+ >V P When the input differential signal V

[0049] Figure 2 is a low-power self-biasing slew rate enhancement amplifier circuit of an embodiment of the present application, comprising a self-biasing control circuit 31, an input voltage detection circuit 32 and a slew rate control circuit 33.

[0050] The self-bias control circuit 31 comprises a first bias circuit 311 and a second bias circuit 312 with the same architecture and parameters, the input voltage detection circuit 32 comprises a first detection circuit 321 and a second detection circuit 322 with the same architecture and parameters, the slew rate control circuit 33 comprises a first control circuit 331 and a second control circuit 332 with the same architecture and parameters; the first detection circuit 321 is connected with the first bias circuit 311 and the first control circuit 331 and the second control circuit 332, the second detection circuit 322 is connected with the second bias circuit 312 and the second control circuit 332 and the first control circuit 331; the first input end and the second input end of the first detection circuit 321 are respectively used for connecting the differential input voltage ends Vin+ and Vin- of an operational amplifier, the first input end and the second input end of the second detection circuit 322 are respectively used for connecting the differential input voltage ends Vin+ and Vin- of an operational amplifier; the output ends of the first detection circuit 331 and the second detection circuit 332 are respectively connected with the differential output voltage ends Vout+ and Vout- of an operational amplifier.

[0051] In an embodiment, the first bias circuit comprises a first PMOS tube M7a and a first NMOS tube M6a, the gate of the first PMOS tube M7a is connected with the output end of the first detection circuit, the source of the first PMOS tube M7a is connected with a power supply voltage, the drain of the first PMOS tube M7a is connected with the drain of the first NMOS tube M6a, the source of the first NMOS tube M6a is connected with the ground, the first NMOS tube M6a adopts a diode connection form, the gate of the first NMOS tube M6a is connected with the first detection circuit to provide a bias current for the first detection circuit; the second bias circuit comprises a second PMOS tube M7b and a second NMOS tube M6b, the gate of the second PMOS tube M7b is connected with the output end of the second detection circuit, the source of the second PMOS tube M7b is connected with a power supply voltage, the drain of the second PMOS tube M7b is connected with the drain of the second NMOS tube M6b, the source of the second NMOS tube M6b is connected with the ground, the second NMOS tube M6b adopts a diode connection form, the gate of the second NMOS tube M6b is connected with the second detection circuit to provide a bias current for the second detection circuit.

[0052] In an embodiment, the first detection circuit comprises a third NMOS transistor M5a, a fourth NMOS transistor M1a, a fifth NMOS transistor M2a, a third PMOS transistor M3a, and a fourth PMOS transistor M4a; the gate of the third NMOS transistor M5a is connected with the gate of a first NMOS transistor M6a, the source of the third NMOS transistor M5a is grounded, the drain of the third NMOS transistor M5a is connected with the source of the fourth NMOS transistor M1a and the source of the fifth NMOS transistor M2a respectively, the gate of the fourth NMOS transistor M1a and the gate of the fifth NMOS transistor M2a are connected with a differential input voltage terminal Vin+ and Vin- respectively, the drain of the fourth NMOS transistor M1a is connected with the drain of the third PMOS transistor M3a, the third PMOS transistor M3a is in a diode connection form, the source of the third PMOS transistor M3a is connected with a power supply voltage, the drain of the fifth NMOS transistor M2a is connected with the drain of the fourth PMOS transistor M4a and forms an output terminal of the first detection circuit, the gate of the fourth PMOS transistor M4a is connected with the gate of the third NMOS transistor M5a, and the source of the fourth PMOS transistor M4a is connected with the power supply voltage; the second detection circuit comprises a sixth NMOS transistor M5b, a seventh NMOS transistor M1b, an eighth NMOS transistor M2b, a fifth PMOS transistor M3b, and a sixth PMOS transistor M4b; the gate of the sixth NMOS transistor M5b is connected with the gate of a second NMOS transistor, the source of the sixth NMOS transistor M5b is grounded, the drain of the sixth NMOS transistor M5b is connected with the source of the seventh NMOS transistor M1b and the source of the eighth NMOS transistor M2b respectively, the gate of the seventh NMOS transistor M1b and the gate of the eighth NMOS transistor M2b are connected with the differential input voltage terminal Vin+ and Vin- respectively, the drain of the seventh NMOS transistor M1b is connected with the drain of the fifth PMOS transistor M3b, the fifth PMOS transistor M3b is in a diode connection form, the source of the fifth PMOS transistor M3b is connected with the power supply voltage, the drain of the eighth NMOS transistor M2b is connected with the drain of the sixth PMOS transistor M4b and forms a second output terminal of the second detection circuit, the gate of the fifth PMOS transistor M3b is connected with the gate of the sixth PMOS transistor M4b, and the source of the sixth PMOS transistor M4b is connected with the power supply voltage.

[0053] It should be noted that, in the first detection circuit, the fourth NMOS transistor M1a and the fifth NMOS transistor M2a constitute input NMOS transistors, the third NMOS transistor M5a is a tail current transistor, and the third PMOS transistor M3a and the fourth PMOS transistor M4a are load transistors. The width-length ratio of the fourth NMOS transistor M1a and the fifth NMOS transistor M2a is m:1, and m is greater than 1. The third NMOS transistor M5a and the first NMOS transistor M6a form a current mirror to obtain a current for providing the first detection circuit 321 to work. The width-length ratio of the third PMOS transistor M3a and the fourth PMOS transistor M4a is 1:1.

[0054] It should be noted that in the second detection circuit, the seventh NMOS transistor M1b and the eighth NMOS transistor M2b constitute input transistors, the sixth NMOS transistor M5b is a tail current transistor, and the fifth PMOS transistor M3b and the sixth PMOS transistor M4b are load transistors. The ratio of the width-length ratio of the seventh NMOS transistor M1b and the eighth NMOS transistor M2b is m:1, the gate of the sixth NMOS transistor M5b is connected to the drain of the second NMOS transistor M6b in the second bias circuit 312, and a current mirror is formed with the second NMOS transistor M6b to obtain a current to provide the second detection circuit 322 to work. The width-length ratio of the fifth PMOS transistor M3b and the sixth PMOS transistor M4b is 1:1.

[0055] The first control circuit includes a ninth NMOS transistor M1n, a tenth NMOS transistor M4n, a seventh PMOS transistor M1p, and an eighth PMOS transistor M4p. The source of the seventh PMOS transistor M1p is connected to a power supply voltage, the gate of the seventh PMOS transistor M1p is connected to the output end of the first detection circuit, the drain of the seventh PMOS transistor M1p is connected to the drain of the ninth NMOS transistor M1n, the source of the ninth NMOS transistor M1n is connected to ground, the ninth NMOS transistor M1n is in a diode connection form, the source of the eighth PMOS transistor M4p is connected to a power supply voltage, the gate of the eighth PMOS transistor M4p is connected to the output end of the second detection circuit, the drain of the eighth PMOS transistor M4p is connected to the drain of the tenth NMOS transistor M4n and the differential output voltage end Vout+, the source of the tenth NMOS transistor M4n is connected to ground, and the gate of the tenth NMOS transistor M4n is connected to the drain of the ninth NMOS transistor M1n. The second control circuit includes an eleventh NMOS transistor M2n, a twelfth NMOS transistor M3n, a ninth PMOS transistor M2p, and a tenth PMOS transistor M3p. The source of the ninth PMOS transistor M2p is connected to a power supply voltage, the gate of the ninth PMOS transistor M2p is connected to the output end of the second detection circuit, the drain of the ninth NMOS transistor M1n is connected to the drain of the eleventh NMOS transistor M2n, the source of the eleventh NMOS transistor M2n is connected to ground, the eleventh NMOS transistor M2n is in a diode connection form, the source of the tenth PMOS transistor M3p is connected to a power supply voltage, the gate of the tenth PMOS transistor M3p is connected to the output end of the first detection circuit, the drain of the tenth PMOS transistor M3p is connected to the drain of the twelfth NMOS transistor M3n and the differential output voltage end Vout-, the source of the twelfth NMOS transistor M3n is connected to ground, and the gate of the twelfth NMOS transistor M3n is connected to the drain of the eleventh NMOS transistor M2n.

[0056] It should be noted that in the input voltage detection circuit 32, the fourth NMOS transistor M1a, the fifth NMOS transistor M2a, the seventh NMOS transistor M1b, and the eighth NMOS transistor M2b constitute input transistors, and the width-length ratio of the input transistors is m:1, which determines the turn-on voltage V P. Taking the first detection circuit 321 as an example, when the branch currents I1a and I1b flowing through the two branches of the detection circuit are equal, according to the saturation region current formula, the gate-source voltages V GS1a and V GS2a of the fourth NMOS transistor M1a and the fifth NMOS transistor M2a are respectively

[0057] obtained as

[0058] When the input differential signal |Vin+ - Vin| < VP, since the width-to-length ratio of the fourth NMOS transistor M1a in the first detection circuit 321 is greater than that of the fifth NMOS transistor M2a, the current flowing through the fourth NMOS transistor M1a is greater than the current flowing through the fifth NMOS transistor M2a. Since the third PMOS transistor M3a and the fourth PMOS transistor M4a form a 1:1 current mirror, the current flowing through the fourth PMOS transistor M4a is greater than the current flowing through the fifth NMOS transistor M2a, making VA a high level. VA controls the first PMOS transistor M7a in the first bias circuit 311, causing the first PMOS transistor M7a to turn off and no current to flow through the first NMOS transistor M6a. The first NMOS transistor M6a and the third NMOS transistor M5a form a current mirror, so no current flows through the third NMOS transistor M5a, making the first detection circuit 321 have no current and not work. At the same time, VA controls the seventh PMOS transistor M1p and the tenth PMOS transistor M3p in the slew rate control circuit 33 to turn them off, so the node V3a is at a low level, which serves as the gate voltage of the tenth NMOS transistor M4n, causing the tenth NMOS transistor M4n to also turn off. Similarly, the output voltage VB of the second detection circuit 322 is also at a high level, which will turn off the second bias circuit 312 and the second control circuit 332. Therefore, when the input differential signal |Vin+ - Vin| < VP, the low-power self-biased slew rate enhanced amplifier circuit of the NMOS input pair does not work and does not consume current.

[0059] When the input differential signal V in+ - V in- > V PWhen the output VB of the second detection circuit 322 is low, the second PMOS transistor M7b in the second bias circuit 312 is turned on, generating current that is mirrored to the sixth NMOS transistor M5b, providing current to the second detection circuit 322 and maintaining VB at a low level. Simultaneously, the output VA of the first detection circuit 321 is high, turning off the first bias circuit 311. In the first control circuit 331, the gate terminal of the seventh PMOS transistor M1p is connected to VA at a high level, so node V3a is low, the tenth PMOS transistor M4n is turned off, and the gate terminal of the eighth NMOS transistor M4p is connected to VB, so the eighth NMOS transistor M4p is turned on. Therefore, a current is drawn into the output voltage terminal Vout+ of the operational amplifier. In the second control circuit 332, the gate terminal of the ninth PMOS transistor M2p is connected to VB, making it low. This turns on the ninth PMOS transistor M2p, causing node V3b to go high. The twelfth NMOS transistor M3n is also turned on, while the gate terminal of the tenth PMOS transistor M3p is turned off due to its connection to VA. Therefore, a current is drawn from the output voltage terminal Vout- of the operational amplifier. Thus, when the input differential signal V... in+ -V in- >V P When the low-power self-biased slew rate enhancement circuit of the present invention is working, it directly provides additional sink current for the output voltage terminal Vout+ and draw current for Vout- to the output node of the operational amplifier, thereby increasing the rising edge slew rate of Vout+ and the falling edge slew rate of Vout-, and thus increasing the rising edge slew rate of the differential output voltage.

[0060] When the input differential signal V in- -V in+ >V P The principle is similar to the above. The output VA of the first detection circuit 321 is low, and the output VB of the second detection circuit 322 is high. The first bias circuit 311 provides current, the second bias circuit 312 is turned off, the first control circuit 331 forms a drawdown current to the output voltage terminal Vout+, and the second control circuit 332 forms a sink current to the output voltage terminal Vout-. Therefore, when the input differential signal V... in- -V in+ >V P When the low-power self-biased slew rate enhancement circuit of the present invention is working, it directly provides additional output voltage terminal Vout+ with additional draw-current and Vout- with additional sink-current to the operational amplifier output node, thereby increasing the falling edge slew rate of Vout+ and the rising edge slew rate of Vout-, and thus increasing the falling edge slew rate of the differential output voltage.

[0061] Figure 3 is a low-power self-biased slew rate enhancement amplifier circuit of a PMOS input pair according to an embodiment of the present application, comprising a self-bias control circuit 41, an input voltage detection circuit 42 and a slew rate control circuit 43. The self-bias control circuit 41 comprises a first bias circuit 411 and a second bias circuit 412 which have the same architecture and parameters, the input voltage detection circuit 42 comprises a first detection circuit 421 and a second detection circuit 422 which have the same architecture and parameters and the input pair is PMOS, and the slew rate control circuit 43 comprises a first control circuit 431 and a second control circuit 432 which have the same architecture and parameters. The first detection circuit 421 is connected to the first bias circuit 411 and the first control circuit 431 and the second control circuit 432, and the second detection circuit 422 is connected to the second bias circuit 412 and the second control circuit 432 and the second control circuit 431. The first input terminal and the second input terminal of the first detection circuit 421 are connected to the differential input voltage terminals Vin+ and Vin- of an operational amplifier respectively, and the first input terminal and the second input terminal of the second detection circuit 422 are connected to Vin- and Vin+ respectively. The output terminals of the first detection circuit 431 and the second detection circuit 432 are connected to the differential output voltage terminals Vout+ and Vout- of the operational amplifier respectively.

[0062] In an embodiment, the first bias circuit comprises a first PMOS transistor M6a and a first NMOS transistor M7a, the first PMOS transistor M6a is connected in diode mode, the source of the first PMOS transistor M6a is connected to a power supply voltage, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor M7a, the source of the first NMOS transistor M7a is connected to ground, the gate of the first NMOS transistor M7a is connected to the output terminal of the first detection circuit, and the gate of the first PMOS transistor M6a is connected to the first detection circuit to provide bias current for the first detection circuit; and the second bias circuit comprises a second PMOS transistor M6b and a second NMOS transistor M7b, the second PMOS transistor M6b is connected in diode mode, the source of the second PMOS transistor M6b is connected to a power supply voltage, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor M7b, the source of the second NMOS transistor M7b is connected to ground, the gate of the second NMOS transistor M7b is connected to the output terminal of the first detection circuit, and the gate of the second PMOS transistor is connected to the first detection circuit to provide bias current for the first detection circuit.

[0063] In an embodiment, the first detection circuit comprises: a third NMOS transistor M3a, a fourth NMOS transistor M4a, a third PMOS transistor M5a, a fourth PMOS transistor M1a, and a fifth PMOS transistor M2a; the source of the third PMOS transistor M5a is connected to a power supply voltage, the gate of the third PMOS transistor M5a is connected to the gate of a first PMOS transistor M6a, the drain of the third PMOS transistor M5a is connected to the source of the fourth PMOS transistor M1a and the source of the fifth PMOS transistor M2a respectively, the gate of the fourth PMOS transistor M1a and the gate of the fifth PMOS transistor M2a are connected to a differential input voltage terminal Vin+ and Vin- respectively, the drain of the fourth PMOS transistor M1a is connected to the drain of the third NMOS transistor M3a, the source of the third NMOS transistor M3a is connected to ground, the third NMOS transistor M3a is connected in a diode form, the drain of the fifth PMOS transistor M2a is connected to the drain of the fourth NMOS transistor M4a, the gate of the fourth NMOS transistor M4a is connected to the gate of the third NMOS transistor M3a, and the source of the fourth NMOS transistor M4a is connected to ground; the second detection circuit comprises: a fifth NMOS transistor M3b, a sixth NMOS transistor M4b, a sixth PMOS transistor M5b, a seventh PMOS transistor M1b, and an eighth PMOS transistor M2b; the source of the sixth PMOS transistor M5b is connected to a power supply voltage, the gate of the sixth PMOS transistor M5b is connected to the gate of a second PMOS transistor M6b, the drain of the sixth PMOS transistor M5b is connected to the source of the seventh PMOS transistor M1b and the source of the eighth PMOS transistor M2b respectively, the gate of the seventh PMOS transistor M1b and the gate of the eighth PMOS transistor M2b are connected to a differential input voltage terminal Vin+ and Vin- respectively, the drain of the seventh PMOS transistor M1b is connected to the drain of the fifth NMOS transistor M3b, the source of the fifth NMOS transistor M3b is connected to ground, the fifth NMOS transistor M3b is connected in a diode form, the drain of the eighth PMOS transistor M2b is connected to the drain of the sixth NMOS transistor M4b, the gate of the sixth NMOS transistor M4b is connected to the gate of the fifth NMOS transistor M3b, and the source of the sixth NMOS transistor M4b is connected to ground.

[0064] In an embodiment, the first control circuit comprises a ninth PMOS transistor M1p, a tenth PMOS transistor M4p, a seventh NMOS transistor M1n, and an eighth NMOS transistor M4n, the ninth PMOS transistor M1p is in diode connection, the source of the ninth PMOS transistor M1p is connected to a power supply voltage, the drain of the ninth PMOS transistor M1p is connected to the drain of the seventh NMOS transistor M1n, the source of the seventh NMOS transistor M1n is connected to ground, the gate of the seventh NMOS transistor M1n is connected to the output of the first detection circuit, the source of the tenth PMOS transistor M4p is connected to the power supply voltage, the gate of the tenth PMOS transistor M4p is connected to the drain of the ninth PMOS transistor M1p, the drain of the tenth PMOS transistor M4p is connected to the drain of the eighth NMOS transistor M4n and to the differential output voltage terminal Vout+, the gate of the eighth NMOS transistor M4n is connected to the output of the second detection circuit, and the source of the eighth NMOS transistor M4n is connected to ground; the first control circuit comprises an eleventh PMOS transistor M2p, a twelfth PMOS transistor M3p, a ninth NMOS transistor M2n, and a tenth NMOS transistor M3n, the eleventh PMOS transistor M2p is in diode connection, the source of the eleventh PMOS transistor M2p is connected to the power supply voltage, the drain of the eleventh PMOS transistor M2p is connected to the drain of the seventh NMOS transistor M2n, the source of the ninth NMOS transistor M2n is connected to ground, the gate of the ninth NMOS transistor M2n is connected to the second output of the first detection circuit, the source of the twelfth PMOS transistor M3p is connected to the power supply voltage, the gate of the twelfth PMOS transistor M3p is connected to the drain of the eleventh PMOS transistor M2p, the drain of the twelfth PMOS transistor M3p is connected to the drain of the tenth NMOS transistor M3n and to the differential output voltage terminal Vout-, the gate of the tenth NMOS transistor M3n is connected to the first output of the second detection circuit, and the source of the tenth NMOS transistor M3n is connected to ground.

[0065] In the first detection circuit, the ratio of the width-length ratio of the third NMOS transistor M3a and the fourth NMOS transistor M4a is 1:1; in the second detection circuit, the ratio of the width-length ratio of the seventh PMOS transistor M1b and the eighth PMOS transistor M2b is m:1, the sixth PMOS transistor M5b and the second PMOS transistor M6b form a current mirror to obtain a current to provide for the operation of the second detection circuit 422. The ratio of the width-length ratio of the fifth NMOS transistor M3b and the sixth NMOS transistor M4b is 1:1.

[0066] The first control circuit 431 includes a seventh NMOS transistor M1n and an eighth NMOS transistor M4n connected to the output ends VA and VB of the first detection circuit 421 and the second detection circuit 422 respectively, a ninth PMOS transistor M1p, a tenth PMOS transistor M4p, an eleventh PMOS transistor M2p connected in diode mode as a load of the seventh NMOS transistor M1n, an output voltage V3a, and a gate of the tenth PMOS transistor M4p connected to the output voltage end Vout+. The tenth PMOS transistor M4p is a load transistor of the eighth NMOS transistor M4n, and the eighth NMOS transistor M4n is connected to the drain of the tenth PMOS transistor M4p to form the output voltage end Vout+. The second control circuit 432 has the same structure as the first control circuit 431 and includes a ninth NMOS transistor M2n and a tenth NMOS transistor M3n connected to the output ends VB and VA of the second detection circuit 422 and the first detection circuit 421 respectively, and an output voltage end Vout-.

[0067] Similarly, the turn-on voltage

[0068] When the input differential signal |Vin+-Vin|<VP, the width-length ratio of the fourth PMOS transistor M1a in the first detection circuit 421 is greater than that of the fifth PMOS transistor M2a, so the current flowing through the fourth PMOS transistor M1a is greater than that flowing through the fifth PMOS transistor M2a. Since the third NMOS transistor M3a and the fourth NMOS transistor M4a form a 1:1 current boundary, the current flowing through the fourth NMOS transistor M4a is greater than that flowing through the fifth PMOS transistor M2a, so that VA becomes low. VA controls the first NMOS transistor M7a in the first bias circuit 411, so that the first NMOS transistor M7a is turned off and no current flows through the first PMOS transistor M6a. The first PMOS transistor M6a and the third PMOS transistor M5a form a current boundary, so no current flows through the third PMOS transistor M5a, and the first detection circuit 421 has no current and is not working. Similarly, the output voltage VB of the second detection circuit 422 is also low, which turns off the second bias circuit 412. VA and VB simultaneously control the NMOS transistors M1n and M3n in the slew rate control circuit 43, and the ninth NMOS transistor M2n and the eighth NMOS transistor M4n, so that they are all turned off. Therefore, the nodes V3a and V3b are high, which are the gate voltages of the tenth PMOS transistor M4p and the twelfth PMOS transistor M3p, so that the tenth PMOS transistor M4p and the twelfth PMOS transistor M3p are also turned off. Therefore, when the input differential signal |Vin+-Vin|<VP, the low-power self-biased slew rate enhancement amplifier circuit of the PMOS input pair is not working and does not consume current.

[0069] When the input differential signal V in+ -V in->V P When the output VA of the first detection circuit 421 is high, the first NMOS transistor M7a in the first bias circuit 411 is turned on, generating current that is mirrored to the third PMOS transistor M5a, providing current to the first detection circuit 421 and maintaining VA at a high level. Simultaneously, the output VB of the second detection circuit 422 is low, turning off the second bias circuit 412. In the first control circuit 431, the gate terminal of the seventh NMOS transistor M1n is connected to VA at a high level, therefore node V3a is low, the tenth PMOS transistor M4p is turned on, and the gate terminal of the eighth NMOS transistor M4n is turned off due to connection to VB. Therefore, a current is drawn into the output voltage terminal Vout+ of the operational amplifier. In the second control circuit 432, the gate terminal of the ninth NMOS transistor M2n is connected to VB and is at a low level, so the ninth NMOS transistor M2n is turned off, making node V3b high. The twelfth PMOS transistor M3p is turned off, while the gate terminal of the tenth NMOS transistor M3n is turned on because it is connected to VA. Therefore, a current is drawn to the output voltage terminal Vout- of the operational amplifier. Therefore, when the input differential signal V... in+ -V in- >V P When the low-power self-biased slew rate enhancement circuit of the present invention is working, it directly provides additional sink current for the output voltage terminal Vout+ and draw current for Vout- to the output node of the operational amplifier, thereby increasing the rising edge slew rate of Vout+ and the falling edge slew rate of Vout-, and thus increasing the rising edge slew rate of the differential output voltage.

[0070] When the input differential signal V in- -V in+ >V P The principle is similar to the above. The output VA of the first detection circuit 421 is low, and the output VB of the second detection circuit 422 is high. The first bias circuit 411 is turned off, and the second bias circuit 412 provides current. The first control circuit 431 forms a drawdown current to the output voltage terminal Vout+, and the second control circuit 432 forms a sink current to the output voltage terminal Vout-. Therefore, when the input differential signal V... in- -V in+ >V P When the low-power self-biased slew rate enhancement circuit of the present invention is working, it directly provides additional output voltage terminal Vout+ with additional draw-current and Vout- with additional sink-current to the operational amplifier output node, thereby increasing the falling edge slew rate of Vout+ and the rising edge slew rate of Vout-, and thus increasing the falling edge slew rate of the differential output voltage.

[0071] Figure 4 is an application example of the self-biased slew rate enhancement circuit of the present application in a Sigma-Delta switched capacitor integrator, which is a switched capacitor integrator, input signals are VP and VN, output signals are Vout+ and Vout-, which comprises an operational amplifier, a switched capacitor, and a self-biased slew rate enhancement circuit. The switched capacitor is differential, and its single end comprises first to fourth switches S1-S4, a sampling capacitor Cs, and an integration capacitor CI. The first and second switches S1 and S2 are controlled by a sampling phase timing Φ1, and the third and fourth switches S3 and S4 are controlled by an integration phase timing Φ2. The first switch S1 is connected to the lower plate of the sampling capacitor Cs and the positive input signal V P of the integrator, respectively, the second switch S2 is connected to the upper plate of the sampling capacitor Cs and the common mode voltage Vcm, respectively, the third switch S3 is connected to the lower plate of the sampling capacitor Cs and the common mode voltage Vcm, respectively, the fourth switch S4 is connected to the upper plate of the sampling capacitor Cs and the input terminal Vin+ of the operational amplifier, respectively, and the integration capacitor CI is connected across the input terminal Vin+ and the output terminal Vout- of the operational amplifier. The low-power self-biased slew rate enhancement circuit is differential, and its input terminals Vin+ and Vin- are connected to the input terminals Vin+ and Vin- of the operational amplifier, respectively, and its output terminals Vout+ and Vout- are connected to the output terminals Vout- and Vout+ of the operational amplifier, respectively. When the input differential voltage Vin+-Vin- of the operational amplifier is less than the start voltage Vp, the slew rate enhancement circuit does not work and does not consume current; when the input differential voltage Vin+-Vin- of the operational amplifier is greater than the start voltage Vp, the slew rate enhancement circuit directly provides the output node of the operational amplifier with additional extraction current of the output voltage terminal Vout+ and filling current of Vout-, thereby improving the falling edge slew rate of the differential output voltage; and when the input differential voltage Vin+-Vin- of the operational amplifier is greater than the start voltage Vp, the slew rate enhancement circuit directly provides the output node of the operational amplifier with additional filling current of the output voltage terminal Vout+ and extraction current of Vout-, thereby improving the rising edge slew rate of the differential output voltage. The self-biased slew rate enhancement circuit realizes fast transfer of charges between Cs and CI, can increase the slew rate by 4 times or more, and meets the requirements of low power consumption and high speed of the Sigma-Delta integrator. in- in+ When the input differential voltage Vin+-Vin- of the operational amplifier is greater than the start voltage Vp, the slew rate enhancement circuit directly provides the output node of the operational amplifier with additional filling current of the output voltage terminal Vout+ and extraction current of Vout-, thereby improving the rising edge slew rate of the differential output voltage. The self-biased slew rate enhancement circuit realizes fast transfer of charges between Cs and CI, can increase the slew rate by 4 times or more, and meets the requirements of low power consumption and high speed of the Sigma-Delta integrator.

[0072] In summary, the present application does not require additional bias voltage or bias current input, does not consume static current when the slew rate enhancement circuit is not turned on, and does not need to increase the static bias current of the operational amplifier when the slew rate enhancement circuit is turned on, can realize fast charging and discharging of large-capacitance load without affecting the small-signal frequency domain characteristics of the operational amplifier, enhances the bidirectional slew rate of the operational amplifier, and meets the design requirements of low power consumption and high speed of integrated circuits.

[0073] ​It should be noted that in the embodiments of the present application, the low-power self-bias rate enhancement circuit can be used in other circuits besides the integrator. The foregoing description is merely illustrative of the integrator circuit.

[0074] The above embodiments only illustrate the principles and effects of the present application, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A low-power self-biased slew rate enhancement circuit, characterized in that, The low-power self-biased slew rate enhancement circuit includes differential input voltage terminals Vin+ and Vin-, differential output voltage terminals Vout+ and Vout-, a self-biasing control circuit, an input voltage detection circuit, and a slew rate control circuit. The differential input voltage terminals Vin+ and Vin- are used to connect to the differential input voltage terminals of the operational amplifier, and the differential output voltage terminals Vout+ and Vout- are used to connect to the differential output voltage terminals of the operational amplifier. The self-biasing control circuit has its input terminal connected to the output terminal of the input voltage detection circuit, and outputs a bias voltage based on the output voltage of the input voltage detection circuit. The input voltage detection circuit has its input terminals connected to the output terminal of the self-biasing control circuit and the differential input voltage terminal, respectively; the output terminal of the input voltage detection circuit is connected to the input terminal of the self-biasing control circuit and the input terminal of the slew rate control circuit, respectively. The slew rate control circuit is connected to the differential output voltage terminals Vout+ and Vout-. When the output voltages of the differential input voltage terminals Vin+ and Vin- exceed the turn-on voltage, it provides a pull-up current or a sink current to the output terminal of the operational amplifier to enhance the rising edge slew rate or the falling edge slew rate. Conversely, it does not generate additional current or enhance the slew rate when the output voltages exceed the turn-on voltage.

2. The low-power self-biased slew rate enhancement circuit according to claim 1, characterized in that, The self-biasing control circuit includes a first bias circuit and a second bias circuit, and the input voltage detection circuit includes a first detection circuit and a second detection circuit. The first bias circuit receives the output of the first detection circuit and generates a first bias voltage, which is connected to the first detection circuit to provide bias current to the first detection circuit. The second bias circuit receives the output of the second detection circuit and generates a second bias voltage, which is connected to the second detection circuit to provide bias current for the second detection circuit. The first detection circuit includes a first input terminal and a second input terminal, which are respectively connected to the differential input voltage terminals Vin+ and Vin-; The second detection circuit includes a third input terminal and a fourth input terminal, which are respectively connected to the differential input voltage terminals Vin- and Vin+.

3. The low-power self-biased slew rate enhancement circuit according to claim 2, characterized in that, The slew rate control circuit includes a first control circuit and a second control circuit. The first input terminal of the first control circuit is connected to the output terminal of the first detection circuit, the second input terminal of the first control circuit is connected to the output terminal of the second detection circuit, the first input terminal of the second control circuit is connected to the first output terminal of the second detection circuit, and the second input terminal of the second control circuit is connected to the second output terminal of the first detection circuit.

4. The low-power self-biased slew rate enhancement circuit according to claim 3, characterized in that, The first bias circuit includes a first PMOS transistor M7a and a first NMOS transistor M6a. The gate of the first PMOS transistor M7a is connected to the output terminal of the first detection circuit. The source of the first PMOS transistor M7a is connected to a power supply voltage. The drain of the first PMOS transistor M7a is connected to the drain of the first NMOS transistor M6a. The source of the first NMOS transistor M6a is grounded. The first NMOS transistor M6a is connected in a diode configuration. The gate of the first NMOS transistor M6a is connected to the first detection circuit to provide bias current for the first detection circuit. The second bias circuit includes a second PMOS transistor M7b and a second NMOS transistor M6b. The gate of the second PMOS transistor M7b is connected to the output terminal of the second detection circuit. The source of the second PMOS transistor M7b is connected to a power supply voltage. The drain of the second PMOS transistor M7b is connected to the drain of the second NMOS transistor M6b. The source of the second NMOS transistor M6b is grounded. The second NMOS transistor M6b is connected in a diode configuration. The gate of the second NMOS transistor M6b is connected to the second detection circuit to provide bias current for the second detection circuit.

5. A low-power self-biased slew rate enhancement circuit according to claim 3, characterized in that, The first detection circuit includes a third NMOS transistor M5a, a fourth NMOS transistor M1a, a fifth NMOS transistor M2a, a third PMOS transistor M3a, and a fourth PMOS transistor M4a. The gate of the third NMOS transistor M5a is connected to the gate of the first NMOS transistor, the source of the third NMOS transistor M5a is grounded, and the drain of the third NMOS transistor M5a is connected to the source of the fourth NMOS transistor and the source of the fifth NMOS transistor M2a, respectively. The gates of the fourth NMOS transistor and the fifth NMOS transistor M2a are respectively... The differential input voltage terminals Vin+ and Vin- are connected. The drain of the fourth NMOS transistor is connected to the drain of the third PMOS transistor M3a, which is connected in a diode configuration. The source of the third PMOS transistor M3a is connected to the power supply voltage. The drain of the fifth NMOS transistor M2a is connected to the drain of the fourth PMOS transistor M4a to form the output terminal of the first detection circuit. The gate of the fourth PMOS transistor M4a is connected to the gate of the third NMOS transistor M5a, and the source of the fourth PMOS transistor M4a is connected to the power supply voltage. The second... The detection circuit includes a sixth NMOS transistor M5b, a seventh NMOS transistor M1b, an eighth NMOS transistor M2b, a fifth PMOS transistor M3b, and a sixth PMOS transistor M4b. The gate of the sixth NMOS transistor M5b is connected to the gate of the second NMOS transistor, the source of the sixth NMOS transistor M5b is grounded, and the drain of the sixth NMOS transistor M5b is connected to the source of the seventh NMOS transistor M1b and the source of the eighth NMOS transistor M2b, respectively. The gates of the seventh NMOS transistor M1b and the eighth NMOS transistor M2b are also connected to each other. The differential input voltage terminals Vin+ and Vin- are connected respectively. The drain of the seventh NMOS transistor M1b is connected to the drain of the fifth PMOS transistor M3b. The fifth PMOS transistor M3b is connected in a diode configuration. The source of the fifth PMOS transistor M3b is connected to the power supply voltage. The drain of the eighth NMOS transistor M2b is connected to the drain of the sixth PMOS transistor M4b to form the second output terminal of the second detection voltage. The gate of the fifth PMOS transistor M3b is connected to the gate of the sixth PMOS transistor M4b. The source of the sixth PMOS transistor M4b is connected to the power supply voltage.

6. A low-power self-biased slew rate enhancement circuit according to claim 3, characterized in that, The first control circuit includes a ninth NMOS transistor M1n, a tenth NMOS transistor M4n, a seventh PMOS transistor M1p, and an eighth PMOS transistor M4p. The source of the seventh PMOS transistor M1p is connected to the power supply voltage, the gate of the seventh PMOS transistor M1p is connected to the output terminal of the first detection circuit, the drain of the seventh PMOS transistor M1p is connected to the drain of the ninth NMOS transistor M1n, the source of the ninth NMOS transistor M1n is grounded, and the ninth NMOS transistor M1n is connected in a diode configuration. The source of the eighth PMOS transistor M4p is connected to the power supply voltage, the gate of the eighth PMOS transistor M4p is connected to the output terminal of the second detection circuit, the drain of the eighth PMOS transistor M4p is connected to the drain of the tenth NMOS transistor M4n and connected to the differential output voltage terminal Vout+, the source of the tenth NMOS transistor M4n is grounded, and the gate of the tenth NMOS transistor M4n is connected to the drain of the ninth NMOS transistor M1n. The second control circuit includes an eleventh NMOS transistor M2n, a twelfth NMOS transistor M3n, a ninth PMOS transistor M2p, and a tenth PMOS transistor M3p. The source of the ninth PMOS transistor M2p is connected to the power supply voltage, and the gate of the ninth PMOS transistor M2p is connected to the output terminal of the second detection circuit. The drain of the ninth NMOS transistor M1n is connected to the drain of the eleventh NMOS transistor M2n, and the source of the eleventh NMOS transistor M2n is grounded. The eleventh NMOS transistor M2n is connected in a diode configuration. The source of the tenth PMOS transistor M3p is connected to the power supply voltage, and the gate of the tenth PMOS transistor M3p is connected to the output terminal of the first detection circuit. The drain of the tenth PMOS transistor M3p is connected to the drain of the twelfth NMOS transistor M3n and connected to the differential output voltage terminal Vout-. The source of the twelfth NMOS transistor M3n is grounded, and the gate of the twelfth NMOS transistor M3n is connected to the drain of the eleventh NMOS transistor M2n.

7. A low-power self-biased slew rate enhancement circuit according to claim 3, characterized in that, The first bias circuit includes: a first PMOS transistor M6a and a first NMOS transistor M7a. The first PMOS transistor M6a is connected in a diode manner. The source of the first PMOS transistor M6a is connected to the power supply voltage. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor M7a. The source of the first NMOS transistor M7a is grounded. The gate of the first NMOS transistor M7a is connected to the output terminal of the first detection circuit. The gate of the first PMOS transistor M6a is connected to the first detection circuit to provide bias current for the first detection circuit. The second bias circuit includes a second PMOS transistor M6b and a second NMOS transistor M7b. The second PMOS transistor M6b is connected in a diode configuration. The source of the second PMOS transistor M6b is connected to the power supply voltage, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor M7b, the source of the second NMOS transistor M7b is grounded, and the gate of the second NMOS transistor M7b is connected to the output terminal of the first detection circuit. The gate of the second PMOS transistor is connected to the first detection circuit to provide bias current for the first detection circuit.

8. A low-power self-biased slew rate enhancement circuit according to claim 7, characterized in that, The first detection circuit includes: a third NMOS transistor M3a, a fourth NMOS transistor M4a, a third PMOS transistor M5a, a fourth PMOS transistor M1a, and a fifth PMOS transistor M2a; the source of the third PMOS transistor M5a is connected to the power supply voltage, the gate of the third PMOS transistor M5a is connected to the gate of the first PMOS transistor M6a, the drain of the third PMOS transistor M5a is connected to the source of the fourth PMOS transistor M1a and the source of the fifth PMOS transistor M2a, respectively, and the gate of the fourth PMOS transistor M1a... The gates of the fifth PMOS transistor M2a are connected to the differential input voltage terminals Vin+ and Vin-, respectively. The drain of the fourth PMOS transistor M1a is connected to the drain of the third NMOS transistor M3a. The source of the third NMOS transistor M3a is grounded. The third NMOS transistor M3a is connected in the form of a diode. The drain of the fifth PMOS transistor M2a is connected to the drain of the fourth NMOS transistor M4a. The gate of the fourth NMOS transistor M4a is connected to the gate of the third NMOS transistor M3a. The source of the fourth NMOS transistor M4a is grounded. The second detection circuit includes: a fifth NMOS transistor M3b, a sixth NMOS transistor M4b, a sixth PMOS transistor M5b, a seventh PMOS transistor M1b, and an eighth PMOS transistor M2b; the source of the sixth PMOS transistor M5b is connected to the power supply voltage, the gate of the sixth PMOS transistor M5b is connected to the gate of the second PMOS transistor M6b, the drain of the sixth PMOS transistor M5b is connected to the source of the seventh PMOS transistor M1b and the source of the eighth PMOS transistor M2b, respectively, and the gate of the seventh PMOS transistor M1b... The gates of the eighth PMOS transistor M2b are connected to the differential input voltage terminals Vin+ and Vin-, respectively. The drain of the seventh PMOS transistor M1b is connected to the drain of the fifth NMOS transistor M3b. The source of the fifth NMOS transistor M3b is grounded. The fifth NMOS transistor M3b is connected in the form of a diode. The drain of the eighth PMOS transistor M2b is connected to the drain of the sixth NMOS transistor M4b. The gate of the sixth NMOS transistor M4b is connected to the gate of the fifth NMOS transistor M3b. The source of the sixth NMOS transistor M4b is grounded.

9. A low-power self-biased slew rate enhancement circuit according to claim 8, characterized in that, The first control circuit includes a ninth PMOS transistor M1p, a tenth PMOS transistor M4p, a seventh NMOS transistor M1n, and an eighth NMOS transistor M4n. The ninth PMOS transistor M1p is connected in a diode configuration. The source of the ninth PMOS transistor M1p is connected to the power supply voltage. The drain of the ninth PMOS transistor M1p is connected to the drain of the seventh NMOS transistor M1n. The source of the seventh NMOS transistor M1n is grounded. The gate of the seventh NMOS transistor M1n is connected to the output terminal of the first detection circuit. The source of the tenth PMOS transistor M4p is connected to the power supply voltage. The gate of the tenth PMOS transistor M4p is connected to the drain of the ninth PMOS transistor M1p. The drain of the tenth PMOS transistor M4p is connected to the drain of the eighth NMOS transistor M4n and connected to the differential output voltage terminal Vout+. The gate of the eighth NMOS transistor M4n is connected to the output terminal of the second detection circuit. The source of the eighth NMOS transistor M4n is grounded. The first control circuit includes an eleventh PMOS transistor M2p, a twelfth PMOS transistor M3p, a ninth NMOS transistor M2n, and a tenth NMOS transistor M3n. The eleventh PMOS transistor M2p is connected in a diode configuration. The source of the eleventh PMOS transistor M2p is connected to the power supply voltage, and the drain of the eleventh PMOS transistor M2p is connected to the drain of the seventh NMOS transistor M2n. The source of the ninth NMOS transistor M2n is grounded, and the gate of the ninth NMOS transistor M2n is connected to the second output terminal of the first detection circuit. The source of the twelfth PMOS transistor M3p is connected to the power supply voltage, and the gate of the twelfth PMOS transistor M3p is connected to the drain of the eleventh PMOS transistor M2p. The drain of the twelfth PMOS transistor M3p is connected to the drain of the tenth NMOS transistor M3n and connected to the differential output voltage terminal Vout-. The gate of the tenth NMOS transistor M3n is connected to the first output terminal of the second detection circuit, and the source of the tenth NMOS transistor M3n is grounded.

10. An integrator, characterized in that, It includes a low-power self-biased slew rate enhancement circuit as described in any one of claims 1-9, as well as an operational amplifier and a switched capacitor; the switched capacitor is differential, and its single end includes a first switch S1 to a fourth switch S4, a sampling capacitor Cs and an integrating capacitor C1. The first switch S1 and the second switch S2 are controlled by the sampling phase timing Φ1, and the third switch S3 and the fourth switch S4 are controlled by the integrating phase timing Φ2. One end of the first switch S1 is connected to the integrator input voltage V. P The other end of the first switch S1 is connected to the lower plate of the sampling capacitor Cs. The two ends of the second switch S2 are connected to the upper plate of the sampling capacitor Cs and the common-mode voltage Vcm, respectively. The two ends of the third switch S3 are connected to the lower plate of the sampling capacitor Cs and the common-mode voltage Vcm, respectively. The two ends of the fourth switch S4 are connected to the upper plate of the sampling capacitor Cs and the input terminal Vin+ of the operational amplifier, respectively. The integrating capacitor C1 is connected across the input terminal Vin+ and the output terminal Vout- of the operational amplifier. The low-power self-biased slew rate enhancement circuit is differential. Its differential input voltage terminals Vin+ and Vin- are connected to the differential input voltage terminals Vin+ and Vin- of the operational amplifier, respectively. Its differential output voltage terminals Vin+ and Vin- are connected to the differential output voltage terminals Vout- and Vout+ of the operational amplifier, respectively.

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