Chip packaging assembly, preparation method and electronic device

Abstract

Provided in the present application are a chip packaging assembly, a preparation method and an electronic device. The chip packaging assembly comprises a substrate, an interposer, a first chip, and a second chip, wherein the first chip comprises a first surface and a second surface that are opposite each other, the first surface being electrically connected to a first pad disposed on the substrate, and the second surface being electrically connected to the interposer; and the second chip is located on the side of the substrate where the first pad is disposed, the second surface being electrically connected to the second chip by means of the interposer. The thickness of the chip packaging assembly is the stacked thickness of the substrate, the first chip and the interposer, and the thickness of the interposer is smaller than that of the second chip. Compared with a chip packaging assembly prepared by stacking a substrate, a first chip, and a second chip together by means of existing POP technology, the chip packaging assembly of the present application has a smaller thickness.

Description

Chip package assembly, preparation method and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202410825819.5, filed on June 24, 2024, entitled "Chip package assembly, preparation method and electronic device", and the Chinese patent application No. 202510194898.9, filed on February 20, 2025, entitled "Chip package assembly, preparation method and electronic device", the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] The present application relates to the field of electronic technology, and in particular, to a chip package assembly, a preparation method and an electronic device. BACKGROUND

[0003] The integrated circuit packaging technology is a key technology for the development of electronic devices such as mobile phones and tablet computers towards high integration and miniaturization. Through the integrated circuit packaging technology, chips with different functions can be packaged and installed in electronic devices, thereby improving the integration of electronic devices. Among them, the package on package (POP) technology has been widely used in the field of chip packaging due to its high flexibility, small space occupation, high data transmission rate and low power consumption.

[0004] The existing POP technology mainly stacks multiple chips on a circuit board in sequence through a soldering process. The stacking of multiple chips in the height direction leads to a large thickness of the chip package assembly, which cannot meet the ultra-thin demand of electronic devices. SUMMARY

[0005] The present application provides a chip package assembly, a preparation method and an electronic device, which can solve the technical problem of a large thickness of the chip package assembly caused by the stacking of multiple chips in the height direction.

[0006] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0007] In a first aspect, the present application provides a chip package assembly, which comprises a substrate, an adapter plate, a first chip and a second chip. The substrate is provided with a first pad. The first chip comprises a first surface and a second surface arranged oppositely. The first pad of the substrate is electrically connected to the first surface, and the adapter plate is electrically connected to the second surface. The second chip is located on one side of the substrate provided with the first pad. The second surface of the second chip is electrically connected to the second chip through the adapter plate. The thickness of the stack of the substrate, the first chip and the adapter plate is smaller than the thickness of the stack of the substrate, the first chip and the second chip.

[0008] The substrate can be a printed circuit board (PCB). The first chip can be a system on chip (SoC) or the like, which has pads or pins on both opposite surfaces. The second chip can be a double data rate (DDR) memory, a read only memory (ROM) or the like, which has pads or pins on only one surface. There can be one or more second chips in the chip package assembly. When there are multiple second chips, the first chip can be electrically connected to each of the second chips through the adapter board. The electrical connection between the components in the embodiments of the present application can realize the transmission of electrical signals.

[0009] In the chip package assembly provided in the present application, the first chip and the at least one second chip are located on the same side of the substrate, and the first chip is arranged between the substrate and the adapter board. The first chip can be electrically connected to the substrate through the pads on the first surface, and electrically connected to the second chip through the pads on the second surface and the adapter board. The thickness of the chip package assembly is the thickness of the stack of the substrate, the first chip and the adapter board, and the thickness of the adapter board is less than the thickness of the second chip. Compared with the existing chip package assembly obtained by stacking the substrate, the first chip and the second chip in sequence through the POP technology, the chip package assembly provided in the present application has a smaller thickness and occupies a smaller thickness space, and can meet the requirements of high integration and ultra-thin of electronic devices.

[0010] In a possible design, the second chip includes a third surface and a fourth surface arranged oppositely. The third surface is provided with pads or pins, and the pads on the third surface can be electrically connected to the adapter board. The fourth surface is opposite to the substrate, and there is a gap between the fourth surface and the substrate. Based on this possible design, even if multiple second chips are arranged in the chip package assembly, the thickness of the chip package assembly is still the sum of the thickness of the substrate, the thickness of the first chip and the thickness of the adapter board.

[0011] In a possible design, a support is arranged between the substrate and the adapter board. When the adapter board provided with the second chip is arranged on the second surface of the second chip, the gravity of the second chip can cause the center of gravity of the adapter board to be unstable. The support arranged between the substrate and the adapter board can be used to support the adapter board and keep the adapter board balanced.

[0012] For example, the support can be a high-temperature-resistant plastic part or a hardware part that plays a supporting role.

[0013] In a possible design, the support can be replaced by a counterweight, and the counterweight can be arranged on the adapter plate. The counterweight can be used to balance the weight of the second chip, so that the center of gravity of the adapter plate remains stable. The size, shape and number of the counterweights can be flexibly adjusted according to the shape of the adapter plate and the wiring design requirements.

[0014] Optionally, the counterweight can be arranged on one side of the adapter plate facing the substrate or one side of the adapter plate away from the substrate.

[0015] In a possible design, the substrate is provided with a first avoiding slot, and the fourth surface is located in the first avoiding slot.

[0016] In a possible design, the adapter plate is provided with a second avoiding slot, and the third surface is electrically connected with the bottom wall of the second avoiding slot. Based on the above possible design, when the thickness of the second chip is greater than the distance between the adapter plate and the substrate, a first avoiding slot can be formed on the substrate at a position opposite to the fourth surface of the second chip, or a second avoiding slot can be formed on the adapter plate at a position where the second chip is mounted, so as to avoid interference between the second chip and the substrate. In addition, the wiring on the substrate is more complex than the wiring on the adapter plate. Compared with the way of forming the first avoiding slot on the substrate, the way of forming the second avoiding slot on the adapter plate can make the wiring on the substrate more flexible, avoid hollowing of the substrate, and thus reduce the wiring difficulty of the substrate.

[0017] In a possible design, the first surface is electrically connected with the first pad of the substrate through a first conductive connecting agent, the second surface is electrically connected with the first pad of the substrate through a second conductive connecting agent, and the third surface is electrically connected with the adapter plate through a third conductive connecting agent. The melting point of the first conductive connecting agent, the melting point of the second conductive connecting agent and the melting point of the third conductive connecting agent are the same, or the melting point of the first conductive connecting agent and the melting point of the third conductive connecting agent are both greater than the melting point of the second conductive connecting agent.

[0018] In a possible design, the second chip includes a third surface provided with a pad; the third surface is electrically connected with the first pad of the substrate, the first region of the adapter plate is electrically connected with the second surface, and the second region of the adapter plate is electrically connected with the first pad of the substrate. The second chip is electrically connected with the second surface through the substrate and the adapter plate.

[0019] In a possible design, the adapter plate includes a bottom plate and a side plate arranged on a fifth surface of the bottom plate, the first region is the fifth surface, the second region is a side of the side plate away from the bottom plate, and the first chip is located in a receiving cavity formed between the fifth surface, the side plate and the substrate.

[0020] Based on the possible design, the thickness of the substrate, the first chip and the adapter plate stack is the sum of the thickness of the substrate, the thickness of the bottom plate, the thickness of the first chip and the thickness of the conductive connecting agent between the side plate and the substrate. Even if multiple second chips are arranged in the chip packaging assembly, the thickness of the chip packaging assembly is the sum of the thickness of the substrate, the thickness of the first chip, the thickness of the bottom plate of the adapter plate and the thickness of the conductive connecting agent between the side plate of the adapter plate and the substrate, and the thickness of the adapter plate is less than the thickness of the second chip, which is thinner than the existing chip packaging assembly made by stacking all the chips on the circuit board through the POP technology, and can meet the needs of high integration and ultra-thin of electronic equipment at the same time.

[0021] In a possible design, the adapter plate is not bendable, for example, the adapter plate is a grid array packaging circuit board.

[0022] In a possible design, the adapter plate is a bendable circuit board, for example, the adapter plate is a flexible printed circuit board or a rigid-flexible combined board, and the first region and the second region are located on the same side of the adapter plate.

[0023] In a possible design, the second region is electrically connected to the first pad of the substrate through an electrical connecting piece. For example, the electrical connecting piece can be a board-to-board connector.

[0024] In a possible design, the third surface of the second chip is filled with a first heat-conducting material between the second chip and the adapter plate when the second chip is electrically connected to the adapter plate. The first heat-conducting material can be an underfill adhesive, for example, an epoxy adhesive, a mixed adhesive of epoxy and silicon dioxide or a mixed adhesive of epoxy and aluminum trioxide. The first heat-conducting material has a certain fluidity, and after the first heat-conducting material is solidified, the gap between the second chip and the adapter plate can be filled. The heat generated by the second chip during use can be sequentially conducted through the first heat-conducting material and the adapter plate to the display screen connected to the adapter plate for heat dissipation, or to the heat-conducting plate (vapor chamber), copper pipe or other heat dissipation devices connected to the outside of the adapter plate for heat dissipation.

[0025] In a possible design, the third surface of the second chip is filled with the first thermal conductive material between the first surface of the second chip and the first region, and / or the fourth surface of the second chip is provided with the second thermal conductive material, and the third surface and the fourth surface are oppositely arranged. For example, the second thermal conductive material can be the same as the first thermal conductive material, or can be a thermal conductive gel or other paste-shaped and non-solidified thermal conductive glue. The heat generated by the second chip can be conducted to the substrate through the first thermal conductive material, and then conducted to the shell of the electronic device connected with the substrate for heat dissipation. The heat generated by the second chip can also be conducted to a vapor chamber (VC), a copper pipe or other heat dissipation devices in the electronic device through the second thermal conductive material, and the heat dissipation devices can conduct the heat to the display screen of the electronic device for heat dissipation.

[0026] In a possible design, the first surface of the first chip is filled with the first thermal conductive material between the first surface of the first chip and the substrate, and / or the second surface of the first chip is filled with the first thermal conductive material between the second surface of the first chip and the adapter plate. Based on this design, the first thermal conductive material can improve the heat conduction efficiency of the first chip, so that the heat generated by the first chip can be dissipated through the substrate and the adapter plate arranged on the two surfaces respectively, and the heat dissipation effect of the first chip is improved.

[0027] In a possible design, the third thermal conductive material is arranged on the side of the substrate away from the first chip, and / or the fourth thermal conductive material is arranged on the side of the adapter plate away from the first chip; along the thickness direction of the adapter plate, the third thermal conductive material on the substrate and the first chip overlap each other, and the fourth thermal conductive material on the adapter plate and the first chip overlap each other. Based on this design, the heat conduction efficiency between the adapter plate and the heat dissipation devices such as a vapor chamber, a copper pipe or a display screen connected externally, or the heat conduction efficiency between the substrate and the shell of the electronic device connected externally can be improved, so that the heat dissipation effect of the first chip can be further improved.

[0028] In a possible design, the adapter plate is provided with a through hole, and the through hole is located in the projection area of the first chip in the thickness direction of the adapter plate.

[0029] Optionally, the fifth thermal conductive material is filled in the through hole of the adapter plate. Based on this design, the fifth thermal conductive material can be in direct contact with the second surface of the first chip, and the heat generated by the first chip can be directly dissipated through the fifth thermal conductive material, so that the heat dissipation path and thermal resistance of the first chip are reduced, and the heat dissipation performance of the first chip is further improved.

[0030] Optionally, the chip packaging assembly further comprises a heat-conducting metal block. One end of the heat-conducting metal block is connected with the heat dissipation device, and the other end of the heat-conducting metal block is inserted into the through hole. The heat-conducting metal block is filled with the fifth heat-conducting material between the heat-conducting metal block and the adapter plate and between the heat-conducting metal block and the first chip. The heat dissipation device is located on the side of the adapter plate away from the substrate. The heat-conducting efficiency of the metal block is higher than that of the fifth heat-conducting material such as heat-conducting glue. Therefore, the heat dissipation performance of the first chip can be further improved by the heat-conducting metal block.

[0031] In a second aspect, the present application provides a preparation method of a chip packaging assembly. The method comprises: electrically connecting a first surface of a first chip with a first pad of a substrate; electrically connecting an adapter plate with a second surface of the first chip, and electrically connecting the second surface with a second chip through the adapter plate; wherein the first surface and the second surface are oppositely arranged, and the second chip is located on the side of the substrate where the first pad is arranged.

[0032] In a possible implementation manner of the second aspect, the second chip comprises a third surface provided with a pad or a pin and a fourth surface oppositely arranged with the third surface; the third surface can be attached to the adapter plate through a third conductive connecting agent; the adapter plate and the second chip are reflow soldered; the adapter plate is electrically connected with the second surface, wherein the fourth surface is opposite to the first pad and has a gap between the fourth surface and the first pad.

[0033] The second chip can be attached to the adapter plate based on a ball mounting process or a tin spraying process. The adapter plate is more thin and more susceptible to warping caused by external force or temperature, etc. The third conductive connecting agent can make the second chip and the adapter plate large-area attached together after melting and solidification in the reflow soldering process, thereby improving the warping tolerance of the adapter plate.

[0034] In a possible implementation manner of the second aspect, a first avoiding slot can be arranged on the first pad before the adapter plate is electrically connected with the second surface, and the fourth surface is located in the first avoiding slot.

[0035] In a possible implementation manner of the second aspect, a second avoiding slot can be arranged on the adapter plate; and the third surface is attached to the bottom wall of the second avoiding slot through the third conductive connecting agent.

[0036] In a possible implementation manner of the second aspect, at least one supporting piece is arranged between the adapter plate and the substrate.

[0037] Optionally, a counterweight is arranged on the adapter plate. The counterweight can replace the supporting piece and balance the weight of the second chip to keep the adapter plate balanced.

[0038] In a possible implementation manner of the second aspect, the first surface can be attached to the substrate by the first conductive connecting agent; the adapter board can be attached to the second surface by the second conductive connecting agent; and the adapter board, the second chip, the substrate and the first chip can be reflow soldered.

[0039] In a possible implementation manner of the second aspect, the melting point of the first conductive connecting agent and the melting point of the third conductive connecting agent are both greater than the melting point of the second conductive connecting agent; after the first surface is attached to the substrate by the first conductive connecting agent, the substrate and the first chip can be reflow soldered.

[0040] In a possible implementation manner of the second aspect, the melting point of the first conductive connecting agent, the melting point of the second conductive connecting agent and the melting point of the third conductive connecting agent are the same.

[0041] In a possible implementation manner of the second aspect, a pressing plate can be arranged on the side of the adapter board away from the second chip; the pressing plate, the adapter board, the second chip, the substrate and the first chip can be reflow soldered.

[0042] Based on the possible implementation manner, the gravity of the pressing plate can balance the stress of the substrate and the buoyancy generated between the adapter board and the first chip and the substrate during the reflow soldering process, so that the pressing plate and the first chip are more closely attached to each other, and the pressing plate and the substrate are more closely attached to each other. Meanwhile, the pressing plate can also correct the warping of the adapter board generated during the high-temperature heating process by the gravity of the pressing plate.

[0043] In a possible implementation manner of the second aspect, the second chip includes a third surface provided with a pad or a pin; the first region of the adapter board can be electrically connected to the second surface of the first chip; the second region of the adapter board can be electrically connected to the first pad of the substrate; and the third surface can be electrically connected to the first pad of the substrate.

[0044] In a possible implementation manner of the second aspect, the adapter board includes a bottom plate and a side plate arranged on a fifth surface of the bottom plate, the first region is the fifth surface, the second region is the side plate away from the bottom plate, and the first chip is located in a receiving cavity formed between the fifth surface, the side plate and the substrate. The thickness of the chip packaging assembly is the sum of the thickness of the substrate, the thickness of the first chip and the thickness of the bottom plate.

[0045] In a possible implementation manner of the second aspect, the adapter board is a grid array packaging circuit board.

[0046] In a possible implementation manner of the second aspect, the adapter board is a flexible printed circuit board or a rigid-flexible combined board, and the first region and the second region are located on the same side of the adapter board.

[0047] In a possible implementation manner of the second aspect, the second region of the adapter plate can be electrically connected with the substrate through the electrical connection.

[0048] In a possible implementation manner of the second aspect, in the case that the second chip is electrically connected with the adapter plate, the method further includes: filling the first thermal conductive material in the gap between the third surface of the second chip and the adapter plate, so as to improve the heat dissipation performance of the second chip and the connection strength between the second chip and the adapter plate.

[0049] In a possible implementation manner of the second aspect, in the case that the second chip is electrically connected with the substrate, the method further includes: filling the first thermal conductive material in the gap between the third surface of the second chip and the first region of the adapter plate, and / or disposing the second thermal conductive material on the fourth surface of the second chip, the third surface and the fourth surface being oppositely arranged, so that the second chip conducts heat outward through the two surfaces, and the heat dissipation performance of the second chip and the connection strength between the second chip and the adapter plate and the substrate are improved.

[0050] In a possible implementation manner of the second aspect, the method further includes: filling the first thermal conductive material in the gap between the first surface of the first chip and the substrate, and / or filling the first thermal conductive material in the gap between the second surface of the first chip and the adapter plate.

[0051] In a possible implementation manner of the second aspect, the method further includes: disposing the third thermal conductive material on the side of the substrate away from the first chip, and / or disposing the fourth thermal conductive material on the side of the adapter plate away from the first chip; along the thickness direction of the adapter plate, the third thermal conductive material on the substrate and the first chip overlap each other, and the fourth thermal conductive material on the adapter plate and the first chip overlap each other.

[0052] In a possible implementation manner of the second aspect, the adapter plate is provided with a through hole, and the through hole is located in the orthographic projection of the first chip on the adapter plate; the method further includes: filling the fifth thermal conductive material in the through hole.

[0053] In a third aspect, the present application provides an electronic device, including the chip packaging assembly in any possible implementation manner of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0054] FIG. 1 is a cross-sectional view of a chip packaging assembly provided by an embodiment of the present application.

[0055] FIG. 2 is a cross-sectional view of another chip packaging assembly provided by an embodiment of the present application.

[0056] FIG. 3 is a cross-sectional view of still another chip packaging assembly provided by an embodiment of the present application.

[0057] FIG. 4 is a cross-sectional view of still another chip packaging assembly provided by an embodiment of the present application.

[0058] FIG. 5 is a schematic diagram of an overall structure of a chip package assembly according to an embodiment of the present application.

[0059] FIG. 6 is a sectional view of the chip package assembly shown in FIG. 5.

[0060] FIG. 7 is another sectional view of the chip package assembly shown in FIG. 5.

[0061] FIG. 8 is a schematic diagram of a structure of a chip package assembly and a heat dissipation device according to an embodiment of the present application.

[0062] FIG. 9 is a plan view of a substrate according to an embodiment of the present application.

[0063] FIG. 10 is a plan view of a conversion board according to an embodiment of the present application.

[0064] FIG. 11 is a flowchart of a method of manufacturing a chip package assembly according to an embodiment of the present application.

[0065] FIGS. 12a to 12g are schematic diagrams of a manufacturing process of a chip package assembly according to an embodiment of the present application.

[0066] FIGS. 13a to 13h are schematic diagrams of another manufacturing process of a chip package assembly according to an embodiment of the present application.

[0067] FIG. 14 is a sectional view of still another chip package assembly according to an embodiment of the present application.

[0068] FIG. 15 is a schematic diagram of a structure of still another chip package assembly and a heat dissipation device according to an embodiment of the present application.

[0069] FIG. 16 is a plan view of another conversion board according to an embodiment of the present application.

[0070] FIG. 17 is a sectional view in the A-A direction of FIG. 16.

[0071] FIGS. 18a to 18d are schematic diagrams of still another manufacturing process of a chip package assembly according to an embodiment of the present application.

[0072] FIG. 19 is a sectional view of another chip package assembly according to an embodiment of the present application.

[0073] FIG. 20 is a schematic diagram of a structure of another chip package assembly and a heat dissipation device according to an embodiment of the present application.

[0074] FIGS. 21a to 21e are schematic diagrams of still another manufacturing process of a chip package assembly according to an embodiment of the present application.

[0075] 10, chip package assembly; 101, substrate; 1011, first pad; 1012, first avoiding slot; 102, adapter plate; 1021, second avoiding slot; 1022, bottom plate; 10221, fifth surface; 10222, sixth surface; 1023, side plate; 1024, second pad; 1025, through hole; 103, first chip; 1031, first surface; 1032, second surface; 104, second chip; 1041, third surface; 1042, fourth surface; 105, support; 106, first conductive connecting agent; 107, second conductive connecting agent; 108, third conductive connecting agent; 109, electrical connecting piece; 110, accommodating cavity; 111, counterweight; 112, heat-conducting metal block; 113, third heat-conductive material; 114, fourth heat-conductive material; 115, fifth heat-conductive material; 20, pressing plate; 30, heat dissipation device. DETAILED DESCRIPTION

[0076] Embodiments of the present application are described below in detail with reference to the accompanying drawings, wherein the same or similar components are denoted by the same or similar reference numerals throughout. The embodiments described below by reference to the accompanying drawings are exemplary and are for the purpose of explanation only, and are not to be understood as limiting the present application.

[0077] In the description of embodiments of the present application, the terms used in the following embodiments are only for the purpose of describing the specific embodiments, and are not intended to be limiting to the present application. As used in the specification and the appended claims of the present application, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", as used herein, specify the presence of the stated features, integers, steps, operations, objects, and / or the like, but do not preclude the presence or addition of one or more other features, integers, steps, operations, objects, and / or the like.

[0078] In the description of the present application, it is to be understood that the terms "first", "second", and the like, are used only for descriptive purposes, and are not to be construed as indicating or implying relative importance or a specific number of the indicated technical features. Thus, features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0079] In the description of the application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection" should be understood broadly, for example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0080] In the description of the application, it should be understood that the terms "upper", "lower", "side", "front", "back" and the like indicate the orientation or positional relationship based on the installation, and are only for the convenience of describing the application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the application.

[0081] It should also be noted that the same reference signs in the embodiments of the application represent the same component or the same part, and for the same parts in the embodiments of the application, only one part or component may be labeled with a reference sign in the drawing, and it should be understood that the reference sign is also applicable to other identical parts or components.

[0082] The package on package (POP) technology is a widely used chip multilayer stacking packaging technology. By using the POP technology, multiple chips with different functions are sequentially stacked on a circuit board and packaged, and then installed in an electronic device, which can improve the integration of the electronic device. However, with the continuous improvement of the multifunctionality and integration of electronic devices, the number of chips stacked on the circuit board is also increasing, and the stacking of chips in the height direction increases the thickness of the chip packaging assembly, thereby occupying a large thickness space, which cannot meet the user's demand for ultra-thin electronic devices. In addition, a large amount of heat will be generated during the use of the chip, and the layering of multiple chips will reduce the heat dissipation performance of the chips located in the middle and bottom layers.

[0083] To solve the above technical problems, the chip packaging assembly, the preparation method and the electronic device are provided. The first chip 103 and the second chip 104 in the chip packaging assembly 10 are horizontally distributed on one side of the substrate 101 provided with the first pad 1011, and the first chip 103 is arranged between the substrate 101 and the adapter plate 102. The first chip 103 can be electrically connected to the second chip 104 through the adapter plate 102. The thickness of the chip packaging assembly 10 is the sum of the thicknesses of the substrate 101, the first chip 103 and the adapter plate 102, and the thickness of the adapter plate 102 is less than the thickness of the second chip 104. Compared with the existing chip packaging assembly made by stacking the substrate 101, the first chip 103 and the second chip 104 together through the POP technology, the thickness is thinner, and the heat dissipation path and the thermal resistance of the first chip 103 and the second chip 104 can be reduced.

[0084] The chip packaging assembly 10 provided by the embodiments of the present application is applied to electronic devices with ultra-thin requirements. For example, a printed circuit board (PCB) support can be arranged in the electronic device, and the side of the substrate 101 in the chip packaging assembly 10 away from the first chip 103 can be fixed on the PCB support or the shell. The shell can include the middle frame and the rear shell of the electronic device, so that the stacking direction of the first chip 103, the adapter plate 102 and the substrate 101 is the same as the thickness direction of the electronic device. The side of the adapter plate 102 in the chip packaging assembly 10 away from the first chip 103 can be connected with a heat dissipation device such as a heat conduction plate or a steel pipe, or can be connected with a display screen of the electronic device, or connected with the display screen through the heat dissipation device. For example, the electronic device can be a terminal device such as a mobile phone, a tablet computer, an electronic reader, a notebook computer, a wearable device, etc. The wearable device can be a smart bracelet, a smart watch, smart glasses, etc. The embodiments of the present application do not specially limit the specific form of the above electronic device.

[0085] The chip packaging assembly 10 provided by the embodiments of the present application will be described below in combination with the corresponding drawings and specific embodiments.

[0086] Referring to the cross-sectional view of the chip packaging assembly 10 shown in FIGS. 1-4, 6, 7, 14 and 19, the chip packaging assembly 10 provided by the embodiments of the present application includes a substrate 101, an adapter plate 102, a first chip 103 and a second chip 104. The substrate 101 can be a single-sided circuit board (for example, a single-sided printed circuit board) provided with pads on only one side, or a double-sided circuit board (for example, a double-sided printed circuit board) provided with pads on both sides.

[0087] The first chip 103 includes a first surface 1031 and a second surface 1032 oppositely arranged, and the first surface 1031 and the second surface 1032 are both provided with a plurality of pads or pins. For example, the first chip 103 can be a system on chip (SoC). The first surface 1031 and the second surface 1032 of the first chip 103 can be fully arranged with pads or pins, or a part of the area is provided with pads or pins, and the other part of the area is not provided with pads or pins.

[0088] The second chip 104 is a chip provided with a plurality of pads or pins on a third surface 1041, and a fourth surface 1042 opposite to the third surface 1041 is not provided with pads or pins. For example, the second chip 104 can be a double data rate (DDR) memory, a read only memory (ROM) or the like. The third surface 1041 of the second chip 104 can be fully arranged with pads or pins, or a part of the area of the third surface 1041 is provided with pads or pins, and the other part of the area is not provided with pads or pins.

[0089] Optionally, the adapter board 102 can be a non-bendable circuit board, for example, a land grid array (LGA) circuit board. Alternatively, the adapter board 102 can be a bendable circuit board, for example, a flexible printed circuit board (FPCB) or a rigid-flex printed circuit board. The thickness of the adapter board 102 is less than the thickness of the second chip 104.

[0090] The first chip 103 in the chip packaging assembly 10 provided by the present application is arranged between the substrate 101 and the adapter board 102, and the first chip 103 and the second chip 104 are both located on the same side of the substrate 101. Referring to a top view of a substrate 101 shown in FIG. 9, a plurality of first pads 1011 arranged in an array are arranged on the side of the substrate 101 facing the first chip 103. The shape of the first pad 1011 can be a circle as shown in FIG. 8, or a square, an ellipse or other shapes.

[0091] In the chip packaging assembly 10 provided in the present application, the first pads 1011 of the substrate 101 are electrically connected with the pads arranged on the first surface 1031 of the first chip 103, and the adapter plate 102 is electrically connected with the pads arranged on the second surface 1032 of the first chip 103. The second chip 104 is located on the side of the substrate 101 where the first pads 1011 are arranged, and the third surface 1041 of the second chip 104 provided with pads can be electrically connected with the pads arranged on the second surface 1032 of the first chip 103 through the adapter plate 102, so that the second chip 104 can communicate with the first chip 103 through the adapter plate 102. The thickness of the chip packaging assembly 10 is the thickness of the stack of the substrate 101, the first chip 103 and the adapter plate 102, and the thickness of the adapter plate 102 is less than the thickness of the second chip 104. Compared with the chip packaging assembly made by sequentially stacking the substrate 101, the first chip 103 and the second chip 104 through the POP technology, the chip packaging assembly 10 provided in the present application is thinner, occupies less space in the electronic device, can meet the requirements of high integration and ultra-thin of the electronic device, and can improve the heat dissipation performance of the first chip 103 and the second chip 104.

[0092] It should be noted that the electrical connection between the components in the chip packaging assembly 10 provided in the present application can realize the transmission of electrical signals, and the electrical signals can be used to indicate data, instructions or other types of information.

[0093] Based on the chip packaging assembly 10 provided in the present application, the present application further provides a preparation method of the chip packaging assembly 10. FIG. 11 is a flowchart of a preparation method of a chip packaging assembly 10 provided in the present application. As shown in FIG. 11, the preparation method includes the following steps:

[0094] S1110, electrically connecting the first surface 1031 of the first chip 103 with the substrate 101.

[0095] For example, the pads on the first surface 1031 can be electrically connected with the first pads 1011 through a welding process. The welding process can be a ball mounting welding process or a solder paste welding process.

[0096] S1120, electrically connecting the adapter plate 102 with the second surface 1032 of the first chip 103, and electrically connecting the second surface 1032 with the third surface 1041 of the second chip 104 through the adapter plate 102.

[0097] In the embodiments of the present application, the second chip 104 can be arranged on one side of the substrate 101 in different manners, and the pads arranged on the second surface 1032 of the first chip 103 are electrically connected to the pads arranged on the third surface 1041 of the second chip 104 through the non-bendable adapter plate 102 or the bendable adapter plate 102, so as to obtain different chip packaging assemblies 10. The chip packaging assemblies 10 and the preparation methods thereof provided in the present application are specifically described below through different embodiments.

[0098] Embodiment one

[0099] Referring to the cross-sectional views of the chip packaging assemblies 10 shown in FIGS. 1 to 4, the adapter plate 102 in the chip packaging assemblies 10 is a non-bendable flat plate structure (for example, it can be a grid array packaging circuit board), and the first chip 103 and the second chip 104 are both located between the adapter plate 102 and the substrate 101. As shown in FIG. 9, the side of the substrate 101 facing the first chip 103 and the second chip 104 is provided with a plurality of first pads 1011. As shown in FIG. 10, the side of the adapter plate 102 facing the first chip 103 and the second chip 104 is provided with a plurality of second pads 1024. For example, the shape of the second pads 1024 can be circular as shown in FIG. 10, or can be square, oval or other shapes.

[0100] As shown in FIG. 1, in the chip packaging assembly 10 provided in the first embodiment of the present application, the pads arranged on the third surface 1041 of the second chip 104 are electrically connected to the second pads 1024 of the adapter plate 102, the fourth surface 1042 of the second chip 104 is opposite to the first pads 1011 of the substrate 101, and there is a gap between the fourth surface 1042 and the first pads 1011. The pads arranged on the first surface 1031 of the first chip 103 are electrically connected to the first pads 1011 of the substrate 101, and the pads arranged on the second surface 1032 of the first chip 103 are electrically connected to the second pads 1024 of the adapter plate 102, so that the pads on the second surface 1032 of the first chip 103 can be electrically connected to the pads on the third surface 1041 of the second chip 104 through the second pads 1024 of the adapter plate 102. In this embodiment, the first chip 103 can communicate with the second chip 104 through the pads on the second surface 1032 and the adapter plate 102 in sequence, or can communicate with the substrate 101 through the pads on the first surface 1031.

[0101] In the chip packaging assembly 10 provided in the embodiment, the thickness of the stack of the adapter plate 102, the first chip 103 and the substrate 101 is the sum of the thickness of the adapter plate 102, the thickness of the first chip 103 and the thickness of the substrate 101, wherein the thickness of the adapter plate 102 is less than the thickness of the second chip 104, so compared with the existing POP chip packaging assembly in which the first chip 103 and the second chip 104 are sequentially stacked on the substrate 101 in the thickness direction, the thickness of the chip packaging assembly 10 provided in the embodiment is thinner, and the heat of the second chip 104 can be conducted to the outside through the substrate 101 and the adapter plate 102 respectively, so the heat dissipation path of the second chip 104 is shortened and the thermal resistance of the second chip 104 is reduced, and the heat dissipation efficiency of the second chip 104 is improved.

[0102] It should be noted that one second chip 104 can be provided in the chip packaging assembly 10 provided in the embodiment, or a plurality of second chips 104 can be provided. In the case where a plurality of second chips 104 are provided in the chip packaging assembly 10, the pads on the third surface 1041 of each second chip 104 are electrically connected to the second pads 1024 of the adapter plate 102, and the fourth surface 1042 of each second chip 104 which is oppositely arranged to the third surface 1041 is opposite to the first pads 1011 of the substrate 101 and there is a gap between the fourth surface 1042 and the first pads 1011. In this way, the first chip 103 can communicate with each second chip 104 through the adapter plate 102, and the thickness of the chip packaging assembly 10 is still the thickness of the stack of the adapter plate 102, the first chip 103 and the substrate 101, which is thinner than the thickness of the chip packaging assembly obtained by sequentially stacking the first chip 103 and a plurality of second chips 104 on the substrate 101 by the POP technology.

[0103] In addition, in the first embodiment, if a plurality of second chips 104 are provided in the chip packaging assembly 10, the plurality of second chips 104 can be distributed around the first chip 103 and keep the adapter plate 102 balanced. For example, if two second chips 104 and one first chip 103 are provided on the adapter plate 102, and the sizes of the two second chips 104 are the same, the first chip 103 can be arranged in the central region of the adapter plate 102, and the two second chips 104 can be respectively arranged on the left and right sides of the first chip 103, and the distance between the two second chips 104 and the first chip 103 is equal.

[0104] Optionally, the electrical connection between the first pad 1011 and the pad arranged on the first surface 1031, between the adapter plate 102 and the pad on the second surface 1032, and between the adapter plate 102 and the pad arranged on the third surface 1041 can be achieved by a soldering process. Specifically, based on the soldering process, the pad arranged on the first surface 1031 can be electrically connected to the first pad 1011 of the substrate 101 through the first conductive connecting agent 106, the pad arranged on the second surface 1032 can be electrically connected to the second pad 1024 of the adapter plate 102 through the second conductive connecting agent 107, and the pad arranged on the third surface 1041 can be electrically connected to the second pad 1024 of the adapter plate 102 through the third conductive connecting agent 108.

[0105] In the above embodiment, the melting point of the first conductive connecting agent 106, the melting point of the second conductive connecting agent 107, and the melting point of the third conductive connecting agent 108 are the same, for example, the first conductive connecting agent 106, the second conductive connecting agent 107, and the third conductive connecting agent 108 can all be high-temperature solder paste, low-temperature solder paste, high-temperature solder ball, or low-temperature solder ball. Alternatively, the melting point of the first conductive connecting agent 106 and the melting point of the third conductive connecting agent 108 are both greater than the melting point of the second conductive connecting agent 107, for example, the first conductive connecting agent 106 and the third conductive connecting agent 108 are both high-temperature solder paste or high-temperature solder ball, and the melting point of the second conductive connecting agent 107 is low-temperature solder paste or low-temperature solder ball.

[0106] Further, when the adapter plate 102 is arranged on the second surface 1032 of the first chip 103, if the relative distance between the adapter plate 102 and the first pad 1011 of the substrate 101 is less than or equal to the thickness of the second chip 104, a clearance groove can be arranged on the adapter plate 102 or at a position corresponding to the second chip 104 on the substrate 101 to avoid interference between the second chip 104 and the substrate 101. The thickness of the second chip 104 is the distance between the third surface 1041 and the fourth surface 1042 of the second chip 104.

[0107] In one example, referring to the schematic diagram of the chip package assembly 10 shown in FIGS. 2 and 4-6, a first clearance groove 1012 can be arranged on the side of the substrate 101 facing the second chip 104, the pad arranged on the third surface 1041 of the second chip 104 is electrically connected to the second pad 1024 of the adapter plate 102 through the third conductive connecting agent 108, and the fourth surface 1042 of the second chip 104 is located in the first clearance groove 1012 and has a gap with the bottom wall and the side wall of the first clearance groove 1012. The area of the first pad 1011 opposite to the second chip 104 is locally thinned, which can avoid interference between the second chip 104 and the substrate 101.

[0108] Optionally, the first avoiding groove 1012 can be an arc-shaped groove or a square groove.

[0109] In another example, referring to the cross-sectional view of another chip package assembly 10 shown in FIG. 3, FIG. 7 and FIG. 8, a second avoiding groove 1021 can be arranged on the side of the adapter plate 102 facing the second chip 104, and the third surface 1041 of the second chip 104 is electrically connected to the pads arranged on the bottom wall of the second avoiding groove 1021 through the third conductive connecting agent 108, and the fourth surface 1042 of the second chip 104 is opposite to the first pad 1011 of the substrate 101 and has a gap with the first pad 1011. The area of the adapter plate 102 where the second chip 104 is arranged is partially thinned, which can avoid the interference between the second chip 104 and the substrate 101. In addition, the wiring in the substrate 101 is more complex than that in the adapter plate 102, and compared with the way of arranging the first avoiding groove 1012 on the substrate 101, the way of arranging the second avoiding groove 1021 on the adapter plate 102 can make the wiring on the substrate 101 more flexible, avoiding the difficulty in wiring after the substrate 101 is hollowed out.

[0110] Optionally, the second avoiding groove 1021 can be an arc-shaped groove or a square groove. The shape of the first avoiding groove 1012 and the second avoiding groove 1021 is not limited in the embodiments of the present application.

[0111] Optionally, the pads of the first surface 1031 of the first chip 103 are electrically connected to the first pad 1011 on the substrate 101, and there can be a gap between each pad on the first surface 1031, and based on this, there can also be a gap between the first surface 1031 and the substrate 101. After the pads of the second surface 1032 of the first chip 103 are electrically connected to the second pad 1024 of the adapter plate 102, there can also be a gap between each pad on the second surface 1032, and based on this, there can also be a gap between the second surface 1032 and the adapter plate 102. The gap between the first surface 1031 and the substrate 101 can be filled with a first heat-conductive material, and / or the gap between the second surface 1032 and the adapter plate 102 can be filled with a first heat-conductive material. The first heat-conductive material on the first surface 1031 can quickly conduct the heat generated by the first chip 103 to the substrate 101, so as to conduct the heat to the shell in the electronic device for heat dissipation through the substrate 101, improving the heat transfer efficiency between the first chip 103 and the substrate 101. The first heat-conductive material on the second surface 1032 can conduct the heat generated by the first chip 103 to the adapter plate 102, so as to conduct the heat to other heat dissipation devices or display screens in the electronic device for heat dissipation through the adapter plate 102, improving the heat transfer efficiency between the first chip 103 and the adapter plate 102 and improving the heat dissipation effect of the first chip 103.

[0112] For example, the first heat-conductive material can be an underfill adhesive with high heat-conducting function, such as an epoxy adhesive, a mixture of epoxy and silicon dioxide, or a mixture of epoxy and aluminum trioxide. The first heat-conductive material filled on the first surface 1031 and the second surface 1032 of the first chip 103 can have fluidity, and the first heat-conductive material can be fully filled in each gap through an underfill process. After solidification, the first heat-conductive material not only has high heat conductivity, but also can improve the connection strength between the first chip 103 and the substrate 101 and between the first chip 103 and the adapter plate 102.

[0113] Optionally, after the pads on the third surface 1041 of the second chip 104 are electrically connected with the second pads 1024 on the adapter plate 102, there are gaps between the pads on the third surface 1041 and the adapter plate 102. Based on this, the first heat-conductive material can be filled in the gaps between the third surface 1041 and the adapter plate 102. After solidification, the first heat-conductive material can quickly conduct the heat generated by the second chip 104 to the adapter plate 102, and then conduct the heat to a heat dissipation device such as a VC in the electronic device and a display screen for heat dissipation, thereby improving the heat conduction efficiency between the second chip 104 and the adapter plate 102. For example, the first heat-conductive material can be an underfill adhesive with high heat-conducting function, such as an epoxy adhesive, a mixture of epoxy and silicon dioxide, or a mixture of epoxy and aluminum trioxide.

[0114] Optionally, generally, the heat generated by the first chip 103 during use is greater than the heat generated by the second chip 104 during use. As shown in FIGS. 4 and 5, in order to further improve the heat dissipation performance of the first chip 103, a through hole 1025 can also be arranged on the adapter plate 102. The through hole 1025 is located in the orthographic projection of the first chip 103 on the adapter plate 102, so that the heat generated by the first chip 103 can be directly dissipated through the through hole 1025.

[0115] Further, as shown in FIGS. 6 to 8, the fifth heat-conductive material 115 can also be filled in the through hole 1025. The fifth heat-conductive material 115 in the through hole 1025 can directly contact the second surface 1032 of the first chip 103 and contact a heat dissipation device 30 such as a VC in the electronic device, so that the heat generated by the first chip 103 can be directly conducted to the heat dissipation device 30 such as a VC in the electronic device and a display screen through the fifth heat-conductive material 115 in the through hole 1025 for heat dissipation, thereby shortening the heat dissipation path of the first chip 103 and improving the heat dissipation performance of the first chip 103.

[0116] Preferably, the through hole 1025 can be located in the region without pads in the second surface 1032 of the first chip 103 within the orthographic projection of the adapter board 102, and the orthographic projection of the through hole 1025 on the second surface 1032 is located in the region without pads in the second surface 1032, which can avoid the filled fifth thermal conductive material covering the pads on the second surface 1032. Exemplarily, the shape of the orthographic projection of the through hole 1025 on the second surface 1032 can be rectangular, circular, elliptical or other shapes.

[0117] Exemplarily, the fifth thermal conductive material 115 can be the same as the first thermal conductive material. Alternatively, the fifth thermal conductive material 115 can be different from the first thermal conductive material, for example, the fifth thermal conductive material 115 can be a thermal conductive gel or other paste-shaped and does not need to be cured thermal conductive glue.

[0118] Optionally, a thermal conductive metal block 112 can also be arranged in the through hole 1025 opposite to the first chip 103, and the material of the thermal conductive metal block 112 can be copper, gold, silver or other metal materials with high thermal conductivity. Referring to the structural schematic diagram of the chip packaging assembly 10 and the heat dissipation device 30 shown in FIG. 8, one end of the thermal conductive metal block 112 can be fixedly connected to the side of the VC or other heat dissipation device 30 in the electronic device facing the adapter board 102, the other end of the thermal conductive metal block 112 can be inserted into the through hole 1025, and the fifth thermal conductive material 115 is also filled between the thermal conductive metal block 112 and the adapter board 102 and the first chip 103. The side of the heat dissipation device 30 away from the adapter board 102 is generally provided with a display screen of the electronic device. Since the thermal conductivity of the thermal conductive metal block 112 is higher than that of the thermal conductive glue, the heat conduction efficiency between the first chip 103 and the VC or other heat dissipation device 30 can be further improved through the fifth thermal conductive material 115 and the thermal conductive metal block 112.

[0119] It should be noted that in the embodiments of the present application, the heat dissipation device 30 in the electronic device can be fixedly connected to the substrate 101 through a metal frame with high thermal conductivity, and the adapter board 102, the first chip 103 and the second chip 104 can be located in the accommodation space enclosed by the metal frame, the substrate 101 and the heat dissipation device 30. Optionally, the thermal conductive glue can be filled in the accommodation space, and the heat generated by the first chip 103 and the second chip 104 is sequentially transmitted to the heat dissipation device 30 through the thermal conductive glue and the metal frame for heat dissipation. The material of the metal frame can be copper, silver or other metal materials with high thermal conductivity.

[0120] Optionally, in this embodiment, a via hole can also be arranged on the adapter plate 102 corresponding to the second chip 104, and the orthographic projection of the via hole corresponding to the second chip 104 on the third surface 1041 of the second chip 104 is located in the area of the third surface 1041 where no pad is arranged. On this basis, the sixth heat-conductive material can be filled in the via hole, and the sixth heat-conductive material can be in direct contact with the third surface 1041, so that the heat generated by the second chip 104 can be conducted to the VC and other heat dissipation devices in the electronic device and the display screen through the sixth heat-conductive material in the via hole 1025, shortening the heat dissipation path of the second chip 104 and improving the heat dissipation performance of the second chip 104. For example, the sixth heat-conductive material can be the same as the fifth heat-conductive material.

[0121] Optionally, a heat-conductive metal block can also be arranged in the via hole opposite to the second chip 104, one end of the heat-conductive metal block is fixedly connected with the VC and other heat dissipation devices in the electronic device, and the other end is inserted into the via hole. The sixth heat-conductive material can be filled between the heat-conductive metal block and the adapter plate 102 and the second chip 104, so that the heat generated by the second chip 104 can be quickly conducted to the heat dissipation device through the sixth heat-conductive material and the heat-conductive metal block.

[0122] Optionally, as shown in FIGS. 6 to 8, the third heat-conductive material 113 can be arranged on the side of the substrate 101 away from the first chip 103, and / or the fourth heat-conductive material 114 can be arranged on the side of the adapter plate 102 away from the first chip 103. Along the thickness direction of the adapter plate 102, the third heat-conductive material 113 arranged on the side of the substrate 101 away from the first chip 103 overlaps with the first chip 103. The fourth heat-conductive material 114 arranged on the side of the adapter plate 102 away from the first chip 103 overlaps with the first chip 103 and / or overlaps with the second chip 104. Based on this design, as shown in FIG. 8, the fourth heat-conductive material 114 is filled between the adapter plate 102 and the heat dissipation device 30, and the heat transfer efficiency between the adapter plate 102 and the VC, copper pipe and other heat dissipation devices 30 connected externally can be improved through the fourth heat-conductive material 114. The third heat-conductive material 113 is filled between the substrate 101 and the shell of the electronic device, and the heat transfer efficiency between the substrate 101 and the shell of the electronic device can be improved through the third heat-conductive material 113, thereby further improving the heat dissipation effect of the first chip 103 and the second chip 104.

[0123] Optionally, the third heat-conductive material 113 can include a heat-conductive glue or a metal layer, wherein the heat-conductive glue can be a glue such as epoxy glue that needs to be cured, or a paste-shaped heat-conductive glue such as heat-conductive gel that does not need to be cured, and the metal layer can be a copper foil or a silver foil. Alternatively, the third heat-conductive material 113 can include a metal layer and a heat-conductive glue that are arranged in a stacked manner, the metal layer can be arranged on the side of the adapter plate 102 that faces away from the first chip 103, and the heat-conductive glue is located between the metal layer and the heat-dissipating device. The fourth heat-conductive material 114 is a heat-conductive glue such as epoxy glue that needs to be cured, or a paste-shaped heat-conductive glue such as heat-conductive gel that does not need to be cured.

[0124] Further, as shown in FIGS. 1-3, the chip package assembly 10 provided by the embodiments of the present application further includes a plurality of support members 105 arranged between the adapter plate 102 and the substrate 101, and the support members 105 are not electrically connected with the adapter plate 102 and the substrate 101. The plurality of support members 105 can be used to support the adapter plate 102 and keep the adapter plate 102 balanced, and can also prevent the adapter plate 102 from being deformed due to the gravity of the second chip 104.

[0125] In one example, one end of each support member 105 can be fixedly connected with the side of the adapter plate 102 that faces the second chip 104, the other end of each support member 105 can be fixedly connected with the side of the substrate 101 that faces the second chip 104, and the connection between the support member 105 and the substrate 101 is not provided with the first bonding pad 1011, and the connection between the support member 105 and the adapter plate 102 is not provided with the second bonding pad 1024.

[0126] In another example, the adapter plate 102 is provided with a plurality of first blind holes, and the substrate 101 is provided with a plurality of second blind holes corresponding to the plurality of first blind holes, one end of each support member 105 can be fixedly arranged in a first blind hole, and the other end can be fixedly arranged in a second blind hole corresponding to the first blind hole. The support member 105 is fixed between the adapter plate 102 and the substrate 101 by means of hole connection, which can enhance the reliability of the connection points between the support member 105 and the adapter plate 102 and between the support member 105 and the substrate 101, and further increase the stability of the adapter plate 102.

[0127] Optionally, the support member 105 can be a high-temperature-resistant plastic member or a hardware member that plays a supporting role. The two ends of the support member 105 can be fixedly connected with the adapter plate 102 and the substrate 101 by means of welding or bonding. The height difference between any two support members 105 can be less than or equal to 50 microns, so as to ensure the stability of the adapter plate 102 when it is attached to the second surface 1032 of the first chip 103.

[0128] Optionally, in the case that the weight of the at least one first chip 103 and the at least one second chip 104 arranged on the adapter plate 102 is unbalanced, the center of gravity of the adapter plate 102 can be inclined, and based on this, the support 105 in the chip package assembly 10 can be replaced by a counterweight 111, which balances the weight of the second chip 104 and keeps the center of gravity of the adapter plate 102 stable. Specifically, at least one counterweight 111 (only one counterweight 111 is shown in FIGS. 5 to 8, but not limited to one counterweight 111) can be arranged on the adapter plate 102, and the counterweight 111 and the second chip 104 are respectively located on the two sides of the first chip 103. As shown in FIGS. 5, 6 and 8, the counterweight 111 can be arranged on the side of the adapter plate 102 facing the substrate 101; or as shown in FIG. 7, the counterweight 111 can be arranged on the side of the adapter plate 102 away from the substrate 101. Compared with the support 105, the arrangement position of the counterweight 111 is more flexible, and can meet the design constraints of the shape, wiring, etc. of the adapter plate 102.

[0129] For example, the counterweight 111 can be welded or bonded with the adapter plate 102. The shape of the counterweight 111 is a cylinder, a cuboid or a square. The number, size, shape and distribution position of the counterweight 111 on the adapter plate are not limited in the embodiments of the present application.

[0130] It should be noted that in the case that the weight of the at least one first chip 103 and the at least one second chip 104 arranged on the adapter plate 102 is balanced, so that the adapter plate 102 can keep balance, the counterweight 111 can not be arranged on the adapter plate 102 in the embodiment one.

[0131] Based on the chip package assembly 10 provided in the embodiment one, the present application further provides a preparation method of the chip package assembly 10. In the process of preparing the chip package assembly 10, the second chip 104 and the support 105 can be first welded on the adapter plate 102, then the first chip 103 is attached to the substrate 101, and the adapter plate 102 is attached to the first chip 103, and finally the first chip 103, the second chip 104, the support 105, the adapter plate 102 and the substrate 101 are subjected to one reflow soldering. Alternatively, the second chip 104 and the support 105 can be first welded on the adapter plate 102, then the first chip 103 is attached to the substrate 101 and subjected to one reflow soldering, and finally the adapter plate 102 is attached to the first chip 103, and the first chip 103, the second chip 104, the support 105, the adapter plate 102 and the substrate 101 are subjected to one reflow soldering.

[0132] The process of preparing the chip package assembly 10 shown in FIG. 6 based on the first and second manners will be described below according to the preparation flowchart shown in FIGS. 12a-12f and the preparation flowchart shown in FIGS. 13a-13g.

[0133] The first manner

[0134] As shown in FIGS. 12a-12f, the preparation process includes the following steps:

[0135] Step one, as shown in FIG. 12a, the third surface 1041 of the second chip 104 is attached to the adapter board 102 by the third conductive connecting agent 108, and one end of the support 105 is arranged on the adapter board 102.

[0136] Specifically, in the case where the first avoiding slot 1012 is arranged on the substrate 101 in the chip package assembly 10, the third surface 1041 of the second chip 104 can be directly attached to the side of the adapter board 102 where the second pads 1024 are arranged by the third conductive connecting agent 108.

[0137] Optionally, the third conductive connecting agent 108 can be a high-temperature solder ball or a low-temperature solder ball, and the material of the solder ball can be tin-lead, tin-silver, or tin-silver-copper. Correspondingly, the method of attaching the third surface 1041 of the second chip 104 to the adapter board 102 by the third conductive connecting agent 108 can include: first, pasting a solder ball on the second pad 1024 of the adapter board 102 by a ball placement process; then, printing flux on the third surface 1041 of the second chip 104; and finally, pasting the third surface 1041 printed with flux on the solder ball of the second pad 1024.

[0138] Optionally, the third conductive connecting agent 108 can be a high-temperature solder paste or a low-temperature solder paste. Correspondingly, the method of attaching the third surface 1041 of the second chip 104 to the adapter board 102 by the third conductive connecting agent 108 can include: first, generating solder paste on the second pad 1024 of the adapter board 102 and / or the pads of the third surface 1041 of the second chip 104 by a solder spraying process or a solder paste printing process; and then, bonding the third surface 1041 of the second chip 104 to the second pad 1024.

[0139] Further, a plurality of first blind holes corresponding to the plurality of supports 105 can be arranged on the adapter board 102, and one end of each support 105 can be fixed in the corresponding first blind hole by solder paste.

[0140] Step two, as shown in FIG. 12b, the support 105, the adapter board 102, and the second chip 104 are reflow soldered.

[0141] The temperature required for reflow soldering matches the melting point of the third conductive connecting agent 108. That is, when the third conductive connecting agent 108 is a high-temperature soldering ball or a high-temperature soldering paste, high-temperature reflow soldering can be performed on the support 105, the adapter plate 102, and the second chip 104. When the third conductive connecting agent 108 is a low-temperature soldering ball or a low-temperature soldering paste, low-temperature reflow soldering can be performed on the support 105, the adapter plate 102, and the second chip 104. Through reflow soldering, the support 105 can be soldered in the first blind hole on the adapter plate 102, and the second chip 104 can be soldered on the second pad 1024 of the adapter plate 102, so that the third surface 1041 of the second chip 104 is electrically connected to the adapter plate 102. By pre-fixing the support 105 and the second chip 104 on the adapter plate 102 through reflow soldering, it can be avoided that the support 105 and the second chip 104 fall off from the adapter plate 102 when the adapter plate 102 provided with the support 105 and the second chip 104 is arranged on the second surface 1032 of the first chip 103.

[0142] Alternatively, the support 105 in steps one and two can be replaced by a counterweight 111, so as to solder or bond the counterweight 111 on the side of the adapter plate 102 provided with the second chip 104, or solder or bond the counterweight 111 on the side of the adapter plate 102 away from the second chip 104.

[0143] Step three, as shown in FIG. 12c, the first surface 1031 of the first chip 103 is attached to the first pad 1011 of the substrate 101 through the first conductive connecting agent 106.

[0144] For example, the first conductive connecting agent 106 can be a high-temperature soldering ball, a low-temperature soldering ball, a high-temperature soldering paste, or a low-temperature soldering paste, and the melting point of the first conductive connecting agent 106 is the same as that of the third conductive connecting agent 108. The material of the soldering ball can be tin-lead, tin-silver, or tin-silver-copper.

[0145] The method of attaching the first surface 1031 of the first chip 103 to the first pad 1011 of the substrate 101 through a high-temperature soldering ball or a low-temperature soldering ball, and the method of attaching the first surface 1031 of the first chip 103 to the first pad 1011 of the substrate 101 through a high-temperature soldering paste or a low-temperature soldering paste can refer to the process of attaching the third surface 1041 of the second chip 104 to the adapter plate 102 described in step one above, which will not be described here.

[0146] Optionally, as shown in FIG. 12c, a first avoiding slot 1012 can be formed on the side of the substrate 101 provided with the first chip 103.

[0147] Step four, as shown in FIG. 12d, a second conductive connecting agent 107 is formed on the second surface 1032 of the first chip 103.

[0148] Exemplarily, the second conductive connecting agent 107 can be disposed on the second surface 1032 by a soldering process or a solder paste printing process. The second conductive connecting agent 107 can be disposed in a region of the second surface 1032 where no pad is disposed.

[0149] The melting point of the second conductive connecting agent 107 is the same as that of the first conductive connecting agent 106 and the third conductive connecting agent 108. For example, the first conductive connecting agent 106 and the third conductive connecting agent 108 are both high-temperature solder balls, and the second conductive connecting agent 107 is high-temperature solder paste. For another example, the first conductive connecting agent 106 and the third conductive connecting agent 108 are both low-temperature solder balls, and the second conductive connecting agent 107 is low-temperature solder paste.

[0150] Step five, the adapter board 102 is attached to the second surface 1032 of the first chip 103 through the second conductive connecting agent 107.

[0151] As shown in FIG. 12e, in the case where the support 105 is disposed on the adapter board 102, a plurality of second blind holes corresponding to the plurality of supports 105 can be disposed on the substrate 101; the adapter board 102 on which the support 105 and the second chip 104 are fixed is attached to the second surface 1032 of the first chip 103, and the other end of each support 105 is fixed in the corresponding second blind hole through solder paste.

[0152] In the case where the counterweight 111 is disposed on the adapter board 102, when the adapter board 102 on which the counterweight 111 and the second chip 104 are disposed is attached to the first chip 103 with the second chip 104 as a fulcrum, the counterweight 111 can balance the weight of the second chip 104, so that the adapter board 102 remains balanced.

[0153] In addition, when the adapter board 102 is attached to the second surface 1032 of the first chip 103, the through hole 1025 disposed on the adapter board 102 communicates with a region of the second surface 1032 where no second conductive connecting agent 107 is disposed.

[0154] Step six, as shown in FIG. 12f, a pressing plate 20 is disposed on the side of the adapter board 102 away from the second chip 104, and the pressing plate 20, the adapter board 102, the second chip 104, the substrate 101 and the first chip 103 are reflow soldered.

[0155] Based on the step, the pads on the first surface 1031 of the first chip 103 can be electrically connected with the first pads 1011 of the substrate 101, and the pads on the second surface 1032 of the first chip 103 can be electrically connected with the second pads 1024 of the adapter board 102, so that the first chip 103 can communicate with the substrate 101 through the pads on the first surface 1031, and communicate with the second chip 104 through the pads on the second surface 1032 and the adapter board 102. Further, after reflow soldering of the pressing plate 20, the adapter board 102, the second chip 104, the substrate 101 and the first chip 103, the pressing plate 20 can be removed.

[0156] Compared with the substrate 101, the adapter board 102 is lighter and thinner, and is more susceptible to temperature and / or external force to cause warping, so that through the ball mounting process or the tin spraying process, the adapter board 102 can be bonded with the first chip 103 through the second conductive connecting agent 107 in a large area, and bonded with the second chip 104 through the third conductive connecting agent 108 in a large area, so as to improve the warping tolerance of the adapter board 102 caused by high temperature in the reflow soldering. In addition, during the reflow soldering shown in step six, the pressing plate 20 arranged on the top of the adapter board 102 can apply pressure to the adapter board 102, so that the adapter board 102 is more fitted with the first chip 103. At the same time, the pressing plate 20 can also correct the warping of the adapter board 102 caused by high temperature heating.

[0157] Step seven, fill the first thermally conductive material in the gap between the first surface 1031 of the first chip 103 and the substrate 101, and / or fill the first thermally conductive material in the gap between the second surface 1032 of the first chip 103 and the adapter board 102, and / or fill the first thermally conductive material in the gap between the third surface 1041 of the second chip 104 and the adapter board 102.

[0158] After the reflow soldering of the pressing plate 20, the adapter plate 102, the second chip 104, the substrate 101 and the first chip 103, the first conductive connecting agent 106 can not completely cover the gap between the first chip 103 and the substrate 101, the second conductive connecting agent 107 can not completely cover the gap between the first chip 103 and the adapter plate 102, and the third conductive connecting agent 108 can also not completely cover the gap between the second chip 104 and the adapter plate 102. Therefore, in this step, the gap between the first chip 103 and the substrate 101, the gap between the first chip 103 and the adapter plate 102, and the gap between the second chip 104 and the adapter plate 102 can be respectively filled with a first thermal conductive material through an underfill process, and the first thermal conductive material is solidified. Not only can the thermal conductivity of the first chip 103 and the second chip 104 be improved, but also the connection strength between the adapter plate 102 and the first chip 103 and the second chip 104 and the connection strength between the first chip 103 and the substrate 101 can be improved, thereby improving the reliability of the chip packaging assembly 10.

[0159] Step eight, as shown in FIG. 12g, the fifth thermal conductive material 115 can be filled in the through hole 1025 of the adapter plate 102.

[0160] Optionally, after step eight, a third thermal conductive material can be arranged on the side of the substrate 101 away from the first chip 103, and / or a fourth thermal conductive material can be arranged on the side of the adapter plate 102 away from the first chip 103, and along the thickness direction of the adapter plate 102, the third thermal conductive material on the substrate 101 and the first chip 103 overlap each other, and the fourth thermal conductive material on the adapter plate 102 and the first chip 103 and / or the second chip 104 overlap each other.

[0161] Method two

[0162] As shown in FIGS. 13a-13g, the preparation process includes the following steps:

[0163] Step one, as shown in FIG. 13a, the third surface 1041 of the second chip 104 is attached to the adapter plate 102 through the third conductive connecting agent 108, and one end of the support 105 is arranged on the adapter plate 102.

[0164] For example, the third conductive connecting agent 108 can be a high-temperature solder ball or a high-temperature solder paste. The material of the solder ball can be tin-lead, tin-silver or tin-silver-copper.

[0165] The method of attaching the third surface 1041 of the second chip 104 to the adapter plate 102 through the third conductive connecting agent 108 and the method of arranging the support 105 on the adapter plate 102 can refer to the related description in step one of method one described above, which will not be repeated here.

[0166] Step two, as shown in FIG. 13b, high-temperature reflow soldering is performed on the support 105, the adapter plate 102 and the second chip 104, so as to realize the electrical connection between the second chip 104 and the adapter plate 102, and fix one end of the support 105 in the first blind hole provided on the adapter plate 102.

[0167] Optionally, the support 105 in the above-mentioned step one and step two can be replaced by a counterweight 111, and the counterweight 111 is welded or bonded on the side of the adapter plate 102 provided with the second chip 104, or the counterweight 111 is welded or bonded on the side of the adapter plate 102 away from the second chip 104.

[0168] Step three, as shown in FIG. 13c, the first surface 1031 of the first chip 103 is attached to the side of the substrate 101 provided with the first pad 1011 by the first conductive connecting agent 106.

[0169] For example, the first conductive connecting agent 106 is a high-temperature solder ball or a high-temperature solder paste. The material of the solder ball can be tin-lead, tin-silver or tin-silver-copper.

[0170] Optionally, the first avoiding groove 1012 can be provided on the first pad 1011.

[0171] Step four, as shown in FIG. 13d, high-temperature reflow soldering is performed on the substrate 101 and the first chip 103, so as to realize the electrical connection between the pad on the first surface 1031 of the first chip 103 and the first pad 1011 of the substrate 101.

[0172] Step five, as shown in FIG. 13e, the second conductive connecting agent 107 is formed on the second surface 1032 of the first chip 103 by a tin spraying process.

[0173] The melting point of the second conductive connecting agent 107 is lower than that of the first conductive connecting agent 106 and the third conductive connecting agent 108. For example, the second conductive connecting agent 107 can be a low-temperature solder paste. The setting position of the second conductive connecting agent 107 can avoid the area provided with the pad on the second surface 1032.

[0174] Step six, as shown in FIG. 13f, in the case that the support 105 is provided on the adapter plate 102, the adapter plate 102 can be attached to the second surface 1032 of the first chip 103 by the second conductive connecting agent 107, and the other end of the support 105 is arranged on the substrate 101. At this time, the through hole 1025 provided on the adapter plate 102 is in communication with the area of the second surface 1032 which is not provided with the second conductive connecting agent 107. The specific implementation process of this step can refer to the related description in step five of the above-mentioned mode one, which will not be described here again.

[0175] Optionally, in step six, when the weight block 111 is provided on the adapter plate 102, the adapter plate 102 provided with the weight block 111 and the second chip 104 can be attached to the first chip 103 through the second conductive connecting agent 107, at this time, the weight block 111 can balance the weight of the second chip 104 with the second chip 104 as the fulcrum, so that the adapter plate 102 remains balanced.

[0176] In addition, when the adapter plate 102 is attached to the second surface 1032 of the first chip 103, the through hole 1025 provided on the adapter plate 102 is in communication with the area of the second surface 1032 where the second conductive connecting agent 107 is not provided.

[0177] Step seven, as shown in FIG. 13g, a pressing plate 20 is provided on the side of the adapter plate 102 facing away from the second chip 104, and low-temperature reflow soldering is performed on the pressing plate 20, the adapter plate 102, the second chip 104, the substrate 101 and the first chip 103 to obtain the chip packaging assembly 10.

[0178] Based on this step, the electrical connection between the pads on the second surface 1032 of the first chip 103 and the second pads 1024 of the adapter plate 102, and the electrical connection between the pads on the second surface 1032 and the pads on the third surface 1041 of the second chip 104 through the second pads 1024 of the adapter plate 102 can be realized, so that the first chip 103 communicates with the second chip 104 through the adapter plate 102. In addition, low-temperature soldering is performed on the second surface 1032 of the first chip 103, which can prevent the first chip 103 from being severely deformed due to high-temperature heating.

[0179] Further, after low-temperature reflow soldering is performed on the pressing plate 20, the adapter plate 102, the second chip 104, the substrate 101 and the first chip 103, the pressing plate 20 can be removed.

[0180] Optionally, as shown in FIG. 13h, after step seven, the fifth thermal conductive material 115 can be filled in the through hole 1025 of the adapter plate 102.

[0181] Optionally, a third thermal conductive material can also be provided on the side of the substrate 101 facing away from the first chip 103, and / or a fourth thermal conductive material can be provided on the side of the adapter plate 102 facing away from the first chip 103, and along the thickness direction of the adapter plate 102, the third thermal conductive material on the substrate 101 and the first chip 103 overlap each other, and the fourth thermal conductive material on the adapter plate 102 and the first chip 103 and / or the second chip 104 overlap each other.

[0182] Optionally, the gap between the first chip 103 and the adapter plate 102 and the gap between the second chip 104 and the adapter plate 102 can also be filled by a bottom filling process to improve the connection strength between the components and the heat dissipation performance of the first chip 103 and the second chip 104.

[0183] The process of preparing the chip packaging assembly 10 by the second method has one more step of reflow soldering the substrate 101 and the first chip 103 than the process of preparing the chip packaging assembly 10 by the first method, and the temperature of reflow soldering the substrate 101 and the first chip 103 is higher than the temperature of reflow soldering the pressing plate 20, the adapter plate 102, the second chip 104, the substrate 101 and the first chip 103 in step seven, because the melting point of the first conductive connecting agent 106 between the first surface 1031 of the first chip 103 and the substrate 101 is higher than the melting point of the second conductive connecting agent 107 between the second surface 1032 of the first chip 103 and the adapter plate 102, if only one high-temperature reflow soldering is performed on the pressing plate 20, the adapter plate 102, the second chip 104, the substrate 101 and the first chip 103 together, the high temperature will not only cause the oxidation reaction or inactivation of the second conductive connecting agent 107, such as burning, voiding and other problems, thereby affecting the quality of the welding, but also cause the first chip 103 to deform due to high temperature; if only one low-temperature reflow soldering is performed on the pressing plate 20, the adapter plate 102, the second chip 104, the substrate 101 and the first chip 103 together, the low temperature will affect the flowability and adhesion of the first conductive connecting agent 106, and reduce the connection strength between the first chip 103 and the substrate 101. Therefore, the high-temperature reflow soldering of the substrate 101 and the first chip 103 is performed first, and then the low-temperature reflow soldering of the pressing plate 20, the adapter plate 102, the second chip 104, the substrate 101 and the first chip 103 is performed together, which can weld the first chip 103 and the adapter plate 102 without affecting the welding performance between the substrate 101 and the first chip 103.

[0184] Embodiment two

[0185] FIG. 14 is a sectional view of a chip packaging assembly 10, FIG. 15 is a structural schematic view of a chip packaging assembly 10 and a heat dissipation device 30 in an electronic device, and FIG. 16 is a top view of an adapter plate 102 provided in an embodiment of the present application, and FIG. 17 is a sectional view of A-A of FIG. 16.

[0186] As shown in FIGS. 14 and 15, the first chip 103 and the second chip 104 in the chip package assembly 10 provided by the second embodiment of the present application are both arranged on the substrate 101, and the second chip 104 is arranged between the adapter board 102 and the substrate 101, and the first chip 103 can communicate with the second chip 104 through the adapter board 102 and the substrate 101. The adapter board 102 is a circuit board which is not bendable and has a cavity.

[0187] Specifically, as shown in FIGS. 16 and 17, the adapter board 102 in the chip package assembly 10 includes a bottom plate 1022 and a side plate 1023 arranged on the fifth surface 10221 of the bottom plate 1022, and the adapter board 102 is an integrally formed structure. The fifth surface 10221 of the bottom plate 1022 and the side plate 1023 away from the bottom plate 1022 are both provided with a plurality of pads (the pads on the adapter board 102 are indicated by circles in FIG. 16), and the bottom plate 1022 and the side plate 1023 enclose the cavity of the adapter board 102, which can be a square cavity or an arc-shaped cavity.

[0188] Referring to FIG. 17, in this embodiment, the thickness of the adapter board 102 refers to the thickness of the bottom plate 1022 in the adapter board 102, and the thickness of the bottom plate 1022 is less than the thickness of the second chip 104. The thickness L1 of the bottom plate 1022 is less than the thickness of the second chip 104, the width L2 of the cavity of the adapter board 102 in the A-A direction is greater than the width of the first chip 103, and the depth L3 of the cavity is greater than the thickness of the first chip 103, so that there is sufficient space in the accommodating cavity 110 to accommodate the first chip 103. The depth of the cavity is the relative distance between the fifth surface 10221 of the bottom plate 1022 and the side plate 1023 away from the bottom plate 1022, and the width of the cavity is the relative distance between the inner side walls of the two bottom plates 1022 arranged oppositely. For example, generally the width of the first chip 103 is 10 mm, the thickness is 0.25 mm, the thickness of the second chip 104 is 0.5 mm, the width L2 of the square cavity in the adapter board 102 in the A-A direction can be 16.2 mm, the depth L3 of the square cavity can be 0.55 mm, and the thickness L1 of the bottom plate 1022 can be 0.3 mm.

[0189] Optionally, the side plate 1023 in the adapter board 102 provided by the present application can be provided with one, for example, the side plate 1023 shown in FIG. 15 is a surrounding edge arranged at the edge of the bottom plate 1022.

[0190] Optionally, the side plate 1023 in the adapter board 102 can be provided with a plurality of side plates 1023, which can be spaced and uniformly distributed at the edges of the bottom plate 1022, so that when the adapter board 102 is arranged on the first chip 103, the plurality of side plates 1023 can support the adapter board 102 and keep the adapter board 102 balanced.

[0191] In the chip package assembly 10 shown in FIG. 14 and FIG. 15, the part of the adapter plate 102 facing the substrate 101 has a first area and a second area, and the first area and the second area are located at different surfaces of the adapter plate 102, wherein the first area is the fifth surface 10221 of the bottom plate 1022, and the second area is the surface of the side plate 1023 away from the bottom plate 1022. The substrate 101 is provided with a surface of the first pad 1011, which can be enclosed with the recess formed by the bottom plate 1022 and the side plate 1023 of the adapter plate 102 to form a containing cavity 110, and the first chip 103 is located in the containing cavity 110. Specifically, the pads provided on the first surface 1031 of the first chip 103 can be electrically connected with the first pad 1011 of the substrate 101, the pads provided on the third surface 1041 of the second chip 104 are electrically connected with the first pad 1011 of the substrate 101, the pads provided on the first area of the adapter plate 102 are electrically connected with the pads provided on the second surface 1032 of the first chip 103, and the pads provided on the second area of the adapter plate 102 are electrically connected with the first pad 1011 of the substrate 101, so that the pads on the second surface 1032 of the first chip 103 can be electrically connected with the pads on the third surface 1041 of the second chip 104 through the pads on the fifth surface 10221 of the bottom plate 1022, the pads on the surface of the side plate 1023 away from the bottom plate 1022, and the first pad 1011 of the substrate 101. That is, in this chip package assembly 10, the first chip 103 can realize the communication function between the second chip 104 through the pads provided on the second surface 1032, the bottom plate 1022 of the adapter plate 102, the side plate 1023 of the adapter plate 102, and the substrate 101 in turn.

[0192] In addition, as known from the foregoing, the pads provided on the first surface 1031 of the first chip 103 can be electrically connected with the pads provided on the third surface 1041 of the second chip 104 through the first pad 1011 of the substrate 101. In this case, the function of the pads on the first surface 1031 of the first chip 103 can be different from the function of the pads on the second surface 1032, and in this case, the first chip 103 can also realize other communication functions between the second chip 104 through the pads provided on the first surface 1031 and the substrate 101.

[0193] Based on the chip package assembly 10 provided in Embodiment Two, the first chip 103 and the second chip 104 are arranged in a tiled manner on the substrate 101, and the pads on the second surface 1032 of the second chip 104 are connected to the substrate 101 through the pads on the bottom plate 1022 and the side plate 1023 of the adapter plate 102, so that the pads on the second surface 1032 can be electrically connected with the substrate 101 through the adapter plate 102, and be electrically connected with the second chip 104 through the adapter plate 102 and the substrate 101 in turn.

[0194] Optionally, the electrical connection between the bottom plate 1022 and the first chip 103, the electrical connection between the side plate 1023 and the substrate 101, the electrical connection between the first chip 103 and the substrate 101, and the electrical connection between the second chip 104 and the substrate 101 can be realized through a tin paste welding process or a ball mounting welding process.

[0195] Optionally, there can be gaps between the welding points between the first surface 1031 of the first chip 103 and the substrate 101, and between the welding points between the second surface 1032 of the first chip 103 and the fifth surface 10221 of the bottom plate 1022. Based on this, the gap between the first surface 1031 and the substrate 101 can be filled with the first heat-conductive material, and / or the gap between the second surface 1032 and the fifth surface 10221 of the bottom plate 1022 can be filled with the first heat-conductive material. The first heat-conductive material filled on the first surface 1031 can quickly conduct the heat generated by the first chip 103 to the substrate 101, so as to conduct the heat to the shell in the electronic device through the substrate 101 for heat dissipation, thereby improving the heat transfer efficiency between the first chip 103 and the substrate 101. The first heat-conductive material after solidification not only has high heat conductivity, but also can improve the connection strength between the first chip 103 and the substrate 101 and the adapter plate 102.

[0196] Optionally, after the pads on the third surface 1041 of the second chip 104 are electrically connected with the first pads 1011 on the substrate 101, there are gaps between the welding points between the third surface 1041 and the substrate 101. Based on this, the gap between the third surface 1041 and the substrate 101 can be filled with the first heat-conductive material. The first heat-conductive material after solidification can quickly conduct the heat generated by the second chip 104 to the substrate 101, so as to conduct the heat to the shell in the electronic device through the substrate 101 for heat dissipation, thereby improving the heat transfer efficiency between the second chip 104 and the substrate 101.

[0197] Further, the fourth surface 1042 of the second chip 104 can also be provided with the second heat-conductive material. As shown in FIG. 14 and FIG. 15, the second heat-conductive material can fill the gap between the fourth surface 1042 of the second chip 104 and the heat dissipation device 30 in the electronic device, so that the heat generated by the second chip 104 is conducted to the heat dissipation device 30 and the display screen in the electronic device through the second heat-conductive material for heat dissipation.

[0198] For example, the second thermally conductive material can be the same as the first thermally conductive material. Alternatively, the second thermally conductive material can be different from the first thermally conductive material, for example, the second thermally conductive material can be a thermally conductive gel or other paste-like and does not need to be cured thermally conductive glue.

[0199] Optionally, generally, the heat generated by the first chip 103 during use is greater than the heat generated by the second chip 104 during use, as shown in FIGS. 14-17, in order to further improve the heat dissipation performance of the first chip 103, a through hole 1025 can also be provided on the bottom plate 1022 of the adapter plate 102, the through hole 1025 is located in the orthographic projection of the first chip 103 on the bottom plate 1022, so that the first chip 103 can dissipate heat through the through hole 1025.

[0200] Further, the fifth thermally conductive material can be filled in the through hole 1025. The fifth thermally conductive material in the through hole 1025 can be in direct contact with the second surface 1032 of the first chip 103 and in contact with the VC or other heat dissipation device or display screen in the electronic device, so that the heat generated by the first chip 103 can be directly conducted to the VC or other heat dissipation device or display screen through the fifth thermally conductive material in the through hole 1025 for heat dissipation, shortening the heat dissipation path of the first chip 103 and improving the heat dissipation performance of the first chip 103. The type of the fifth thermally conductive material can refer to the related description in Embodiment One, which will not be described here.

[0201] Preferably, the through hole 1025 can be located in the orthographic projection of the area on the second surface 1032 of the first chip 103 where no pads are provided on the bottom plate 1022, and the orthographic projection of the through hole 1025 on the second surface 1032 is located in the area on the second surface 1032 where no pads are provided, which can avoid the filled fifth thermally conductive material covering the pads on the second surface 1032 of the first chip 103.

[0202] Further, as shown in FIG. 15, a thermally conductive metal block 112 can also be provided in the through hole 1025, one end of the thermally conductive metal block 112 is fixedly connected with the heat dissipation device 30 of the electronic device, the other end of the thermally conductive metal block 112 is inserted into the through hole 1025, and the fifth thermally conductive material 115 is filled between the thermally conductive metal block 112 and the adapter plate 102 and between the thermally conductive metal block 112 and the second surface 1032 of the first chip 103.

[0203] Optionally, the side of the substrate 101 opposite to the first chip 103 can be provided with a third thermally conductive material 113, and / or the side of the adapter plate 102 opposite to the first chip 103 is provided with a fourth thermally conductive material 114, and along the thickness direction of the adapter plate 102, the third thermally conductive material 113 provided on the substrate 101 can overlap with the first chip 103 and / or overlap with the second chip 104, and the fourth thermally conductive material 114 provided on the adapter plate 102 can overlap with the first chip 103. Based on this design, the heat transfer efficiency between the adapter plate 102 and the external connected VC, copper pipe and other heat dissipation devices 30 can be improved by the thermally conductive material, and the heat transfer efficiency between the substrate 101 and the shell of the electronic device can also be improved, so that the heat dissipation effect of the first chip 103 and the second chip 104 can be further improved. The implementation of the third thermally conductive material 113 and the fourth thermally conductive material 114 can refer to the related description in Embodiment One, which will not be repeated here.

[0204] It should be noted that one second chip 104 or multiple second chips 104 can be provided in the chip packaging assembly 10 provided by the embodiments of the present application. In the case of providing multiple second chips 104 in the chip packaging assembly 10, the multiple second chips 104 can be provided on the substrate 101, and the third surface 1041 of each second chip 104 is provided with a pad electrically connected to the first pad 1011 of the substrate 101. Therefore, even in the case of providing multiple second chips 104 in the chip packaging assembly 10, the thickness of the chip packaging assembly 10 (i.e. the thickness of the stack of the substrate 101, the first chip 103 and the adapter plate 102) is still the sum of the thickness of the substrate 101, the thickness of the first chip 103, the thickness of the bottom plate 1022 of the adapter plate 102 and the thickness of the conductive connecting agent between the side plate 1023 of the adapter plate 102 and the substrate 101, and the thickness of the bottom plate 1022 is less than the thickness of the second chip 104. Compared with the chip packaging assembly prepared based on the existing POP technology, the occupied thickness space can be greatly reduced, and the high integration and ultra-thin requirements of the electronic device can be met at the same time.

[0205] Based on the chip packaging assembly 10 provided by Embodiment Two, the present application further provides a preparation method of the chip packaging assembly 10. Referring to the preparation flowchart of the chip packaging assembly 10 shown in FIGS. 18a-18c, the preparation method comprises the following steps:

[0206] Step one, as shown in FIG. 18a, the first surface 1031 of the first chip 103 and the third surface 1041 of the second chip 104 are respectively attached to the side of the substrate 101 provided with the first pad 1011.

[0207] Specifically, the first surface 1031 of the first chip 103 can be attached to the substrate 101 by a conductive connecting agent, and the third surface 1041 of the second chip 104 can be attached to the substrate 101 by a conductive connecting agent. The conductive connecting agent can be solder balls or solder paste.

[0208] In one example, solder balls can be first attached to the first pads 1011 of the substrate 101 by a ball mounting process; then flux can be printed on the first surface 1031 of the first chip 103 and on the third surface 1041 of the second chip 104; finally, the first surface 1031 printed with flux can be attached to the solder balls of the substrate 101, and the third surface 1041 printed with flux can be attached to the solder balls of the substrate 101.

[0209] In another example, solder paste can be first deposited on the first surface 1031 of the first chip 103 by a solder spraying process, and the first surface 1031 with solder paste deposited thereon can be attached to the side of the substrate 101 provided with the first pads 1011; then solder paste can be deposited on the third surface 1041 of the second chip 104 by a solder spraying process, and the third surface 1041 with solder paste deposited thereon can be attached to the side of the substrate 101 provided with the first pads 1011.

[0210] Step two, as shown in FIG. 18b, the fifth surface 10221 of the bottom plate 1022 is attached to the second surface 1032 of the first chip 103, and the side plate 1023 away from the bottom plate 1022 is attached to the side of the substrate 101 provided with the first pads 1011.

[0211] Specifically, the fifth surface 10221 of the bottom plate 1022 can be attached to the second surface 1032 of the first chip 103 by a conductive connecting agent, and the side plate 1023 away from the bottom plate 1022 can be attached to the substrate 101 by a conductive connecting agent. The conductive connecting agent can be solder paste.

[0212] In one example, solder can be first sprayed on the fifth surface 10221 of the bottom plate 1022 of the adapter plate 102, and solder can be sprayed on the side of the side plate 1023 away from the bottom plate 1022; then the adapter plate 102 after spraying is set on the first chip 103, so that the fifth surface 10221 of the bottom plate 1022 can be attached to the second surface 1032 of the first chip 103, and the side of the side plate 1023 away from the bottom plate 1022 can be attached to the side of the substrate 101 provided with the first pads 1011.

[0213] In another example, the area of the second surface 1032 of the first chip 103 where the pads are arranged can be tin-plated, and the substrate 101 where the first pads 1011 are arranged can be tin-plated according to the arrangement position of the side plate 1023 on the substrate 101; then the fifth surface 10221 of the bottom plate 1022 of the adapter plate 102 is pasted on the second surface 1032 of the first chip 103 after tin-plating, and the side plate 1023 is pasted on the side of the substrate 101 where the first pads 1011 are arranged. As shown in FIG. 18b, when the bottom plate 1022 is pasted on the second surface 1032 of the first chip 103, the through hole 1025 arranged on the bottom plate 1022 is in communication with the area of the first chip 103 where no conductive connecting agent is arranged.

[0214] In other examples, the fifth surface 10221 of the bottom plate 1022 of the adapter plate 102, the side plate 1023 away from the bottom plate 1022, and the area of the second surface 1032 of the first chip 103 where the pads are arranged can be tin-plated respectively, and the substrate 101 where the first pads 1011 are arranged can be tin-plated according to the arrangement position of the side plate 1023 on the substrate 101; then the fifth surface 10221 of the bottom plate 1022 is pasted on the second surface 1032 of the first chip 103, and the side plate 1023 away from the bottom plate 1022 is pasted on the side of the substrate 101 where the first pads 1011 are arranged. The tin-plating operation is performed on the bottom plate 1022, the second chip 104, the side plate 1023, and the substrate 101, which can enhance the pasting strength between the adapter plate 102 and the first chip 103 and between the adapter plate 102 and the substrate 101.

[0215] Step three, as shown in FIG. 18c, the pressing plate 20 is arranged on the sixth surface 10222 of the bottom plate 1022, and the pressing plate 20, the adapter plate 102, the first chip 103, the second chip 104, and the substrate 101 are subjected to reflow soldering, and the sixth surface 10222 is arranged opposite to the fifth surface 10221 of the bottom plate 1022.

[0216] Specifically, the conductive connecting agent between the first chip 103 and the substrate 101, the conductive connecting agent between the second chip 104 and the substrate 101, the conductive connecting agent between the bottom plate 1022 and the first chip 103, and the conductive connecting agent between the side plate 1023 and the substrate 101 can all be melted and solidified in the process of reflow soldering, so that the pads on the first surface 1031 of the first chip 103 can be electrically connected with the first pads 1011 of the substrate 101, the pads on the second surface 1032 of the first chip 103 can be electrically connected with the pads on the fifth surface 10221 of the bottom plate 1022, the pads on the side of the side plate 1023 away from the bottom plate 1022 can be electrically connected with the first pads 1011 of the substrate 101, and the pads on the third surface 1041 of the second chip 104 can be electrically connected with the first pads 1011 of the substrate 101, so that the first chip 103 communicates with the second chip 104 through the pads on the first surface 1031, the adapter plate 102 and the substrate 101, and communicates with the substrate 101 through the pads on the second surface 1032.

[0217] In this step, the gravity of the pressing plate 20 arranged on the top of the adapter plate 102 can balance with the stress of the substrate 101 and the buoyancy generated by the solder joints between the adapter plate 102 and the first chip 103 and the substrate 101 in the process of reflow soldering, so that the bottom plate 1022 and the first chip 103 and the side plate 1023 and the substrate 101 are more closely attached. At the same time, the pressing plate 20 can also correct the warping of the adapter plate 102 generated in the process of high-temperature heating by its own gravity. Further, after reflow soldering of the pressing plate 20, the adapter plate 102, the second chip 104, the substrate 101 and the first chip 103, the pressing plate 20 can be removed.

[0218] Step four, as shown in FIG. 18d, the fifth heat-conducting material 115 is filled in the through hole 1025 arranged on the bottom plate 1022.

[0219] Optionally, after step four, the gap between the second chip 104 and the substrate 101 can be filled with the first thermal conductive material through a bottom filling process, and the solidified first thermal conductive material can not only conduct the heat generated by the second chip 104 to the shell of the electronic device through the substrate 101 to dissipate quickly, thereby improving the heat dissipation performance of the second chip 104, but also can improve the connection strength between the substrate 101 and the second chip 104. Further, the second thermal conductive material can be arranged on the fourth surface 1042 of the second chip 104, and the second thermal conductive material can conduct the heat generated by the second chip 104 to the VC and other heat dissipation devices in the electronic device for heat dissipation. Based on this method, the second chip 104 can dissipate heat through the upper and lower surfaces at the same time, and the heat dissipation performance of the second chip 104 can be further improved. The types of the first thermal conductive material and the second thermal conductive material can refer to the related description in the above-mentioned other embodiments, which will not be described here.

[0220] Optionally, after step four, the gap between the first surface 1031 of the first chip 103 and the substrate 101 can be filled with the first thermal conductive material through a bottom filling process, and / or the gap between the second surface 1032 of the first chip 103 and the fifth surface 10221 of the bottom plate 1022 can be filled with the first thermal conductive material, and the first thermal conductive material can be solidified. The solidified first thermal conductive material can not only improve the heat transfer efficiency between the first chip 103 and the substrate 101, the adapter plate 102, but also can improve the connection strength between the first chip 103 and the substrate 101, the adapter plate 102.

[0221] Optionally, the fourth thermal conductive material 114 can be arranged on the sixth surface 10222 of the bottom plate 1022, and / or the third thermal conductive material 113 can be arranged on the side of the substrate 101 away from the first chip 103, and along the thickness direction of the bottom plate 1022, the third thermal conductive material 113 arranged on the substrate 101 can overlap with the first chip 103 and / or overlap with the second chip 104, and the fourth thermal conductive material 114 on the bottom plate 1022 can overlap with the first chip 103. Based on this method, the heat dissipation performance of the first chip 103 and the second chip 104 can be further improved.

[0222] Optionally, the gap between the side plate 1023 and the substrate 101 can be filled with a thermal conductive material, so that the heat of the adapter plate 102 can be conducted to the substrate 101 through the side plate 1023, and the heat dissipation performance of the adapter plate 102 and the connection strength between the adapter plate 102 and the substrate 101 can be improved.

[0223] Embodiment three

[0224] FIG. 19 is a sectional view of the chip package assembly 10 provided by the embodiment of the present application, and FIG. 19 is a sectional view of the chip package assembly 10 provided by the embodiment of the present application and the heat dissipation device 30 in the electronic device, the first chip 103 and the second chip 104 in the chip package assembly 10 are disposed on the substrate 101, and the second chip 104 is disposed between the substrate 101 and the adapter board 102. Wherein, the adapter board 102 is a flexible circuit board, and the adapter board 102 has a first area and a second area on the side facing the substrate 101, and the first area and the second area are both provided with a plurality of pads.

[0225] Specifically, in the chip package assembly 10 shown in FIG. 19 and FIG. 20, the pads provided on the first surface 1031 of the first chip 103 can be electrically connected with the first pads 1011 of the substrate 101, and the pads provided on the third surface 1041 of the second chip 104 are electrically connected with the first pads 1011 of the substrate 101, and after the adapter board 102 is bent, the pads in the first area of the adapter board 102 can be electrically connected with the pads provided on the second surface 1032 of the first chip 103, and the pads in the second area of the adapter board 102 can be electrically connected with the first pads 1011 of the substrate 101, so that the pads on the second surface 1032 of the first chip 103 can be electrically connected with the pads on the third surface 1041 of the second chip 104 through the pads in the first area of the adapter board 102, the pads in the second area of the adapter board 102 and the first pads 1011 of the substrate 101 in sequence. That is, in the chip package assembly 10, the first chip 103 can realize certain communication functions between the second chip 104 through the pads on the second surface 1032, the adapter board 102 and the substrate 101 in sequence.

[0226] In addition, as known from the foregoing, the pads provided on the first surface 1031 of the first chip 103 can be electrically connected with the pads provided on the third surface 1041 of the second chip 104 through the first pads 1011 of the substrate 101, wherein the function of the pads on the first surface 1031 of the first chip 103 can be different from the function of the pads on the second surface 1032, in this case, the first chip 103 can also realize other communication functions between the second chip 104 through the pads on the first surface 1031, the substrate 101 and the second chip 104 in sequence.

[0227] For example, the adapter board 102 shown in FIG. 19 and FIG. 20 can be a flexible printed circuit board or a rigid-flexible combined board.

[0228] Optionally, the electrical connection between the pads on the first surface 1031 of the first chip 103 and the first pads 1011 of the substrate 101, the electrical connection between the pads on the second surface 1032 of the first chip 103 and the pads in the first area of the adapter board 102, and the electrical connection between the pads on the third surface 1041 of the second chip 104 and the first pads 1011 of the substrate 101 can be achieved by a soldering process. The electrical connection between the pads in the second area of the adapter board 102 and the first pads 1011 of the substrate 101 can be achieved by a soldering process or the electrical connector 109.

[0229] For example, the soldering process can be a ball grid array (BGA) soldering process or a solder paste soldering process. The electrical connector 109 can be a board-to-board connector including a male seat and a female seat buckling with the male seat, the male seat being electrically connected with the first pads 1011, and the female seat being electrically connected with the pads in the second area of the adapter board 102, so that the adapter board 102 can be electrically connected with the substrate 101 through the board-to-board connector to transmit electrical signals.

[0230] Optionally, there can be gaps between the solder joints between the first surface 1031 of the first chip 103 and the substrate 101, and there can be gaps between the solder joints between the second surface 1032 of the first chip 103 and the first area of the adapter board 102. Based on this, a thermally conductive material can be filled in the gaps between the first surface 1031 and the substrate 101, and / or a thermally conductive material can be filled in the gaps between the second surface 1032 and the first area of the adapter board 102. The first thermally conductive material filled on the first surface 1031 can quickly conduct the heat generated by the first chip 103 to the substrate 101, so as to conduct the heat to the shell in the electronic device through the substrate 101 for heat dissipation, thereby improving the heat transfer efficiency between the first chip 103 and the substrate 101. The first thermally conductive material filled on the second surface 1032 can conduct the heat generated by the first chip 103 to the first area of the adapter board 102, so as to conduct the heat to other heat dissipation devices or the display screen in the electronic device through the bottom plate 1022 for heat dissipation. The first thermally conductive material filled on the first surface 1031 and the first thermally conductive material filled on the second surface 1032 can not only respectively improve the heat transfer efficiency between the first chip 103 and the adapter board 102 and the heat dissipation effect of the first chip 103, but also improve the connection strength between the first chip 103 and the substrate 101 and the first area of the adapter board 102.

[0231] Optionally, after the pads on the third surface 1041 of the second chip 104 are electrically connected with the first pads 1011 on the substrate 101, there is a gap between each solder joint between the third surface 1041 and the substrate 101, and based on this, the first heat-conductive material can be filled in the gap between the third surface 1041 and the substrate 101. The solidified first heat-conductive material can quickly conduct the heat generated by the second chip 104 to the substrate 101, and conduct the heat to the shell in the electronic device through the substrate 101 for heat dissipation, thereby improving the heat transfer efficiency between the second chip 104 and the substrate 101.

[0232] Further, the fourth surface 1042 of the second chip 104 can also be provided with the second heat-conductive material. As shown in FIG. 20, the fourth surface 1042 of the second chip 104 has a gap with the heat dissipation device 30 in the electronic device, and the second heat-conductive material can fill the gap and conduct the heat generated by the second chip 104 to the heat dissipation device 30 in the electronic device, and through the simultaneous heat dissipation of the upper and lower surfaces, the heat dissipation performance of the second chip 104 can be further improved.

[0233] Optionally, generally, the heat generated by the first chip 103 during use is greater than the heat generated by the second chip 104 during use, and as shown in FIG. 19, in order to further improve the heat dissipation performance of the first chip 103, a through hole 1025 can also be arranged in the first region of the adapter plate 102, and the through hole 1025 is located in the orthographic projection of the first chip 103 on the first region of the adapter plate 102, so that the heat generated by the first chip 103 can be dissipated from the through hole 1025.

[0234] Further, the fifth heat-conductive material 115 can be filled in the through hole 1025. The fifth heat-conductive material 115 in the through hole 1025 can directly contact the second surface 1032 of the first chip 103, so that the heat generated by the first chip 103 can be directly conducted to the VC and other heat dissipation devices 30 in the electronic device through the second heat-conductive material in the through hole 1025, thereby shortening the heat dissipation path of the first chip 103 and improving the heat dissipation performance of the first chip 103.

[0235] Preferably, the orthographic projection of the through hole 1025 on the second surface 1032 is located in the region of the second surface 1032 where no pad is arranged, so as to avoid the fifth heat-conductive material 115 filled in the through hole 1025 covering the pads on the second surface 1032 of the first chip 103.

[0236] Optionally, as shown in FIG. 20, a thermally conductive metal block 112 is further arranged in the through hole 1025, one end of the thermally conductive metal block 112 is fixedly connected with the heat dissipation device 30 of the electronic device, the other end of the thermally conductive metal block 112 is inserted into the through hole 1025, and the thermally conductive metal block 112 is filled with the fifth thermally conductive material 115 between the thermally conductive metal block 112 and the adapter plate 102 and between the thermally conductive metal block 112 and the second surface 1032 of the first chip 103.

[0237] Optionally, as shown in FIG. 20, the third thermally conductive material 113 can also be arranged on the side of the substrate 101 away from the first chip 103, and / or the fourth thermally conductive material 114 can be arranged on the side of the adapter plate 102 away from the first chip 103. The third thermally conductive material 113 arranged on the substrate 101 can overlap with the first chip 103 and / or overlap with the second chip 104 along the thickness direction of the adapter plate 102. The fourth thermally conductive material 114 arranged on the adapter plate 102 overlaps with the first chip 103. Based on this design, the fourth thermally conductive material 114 can improve the heat transfer efficiency between the adapter plate 102 and the heat dissipation device 30 such as VC, copper pipe, etc. connected externally, and the third thermally conductive material 113 can improve the heat transfer efficiency between the substrate 101 and the shell of the electronic device, thereby further improving the heat dissipation effect of the first chip 103 and the second chip 104. The specific implementation of the first thermally conductive material, the second thermally conductive material, the third thermally conductive material 113, the fourth thermally conductive material 114 and the fifth thermally conductive material 115 in the embodiments of the application can refer to the related description in Embodiment One, which will not be repeated here.

[0238] Optionally, the chip packaging assembly 10 provided in Embodiment Three can include one second chip 104 or multiple second chips 104. The thickness of the chip packaging assembly 10 is always the sum of the thickness of the substrate 101, the thickness of the first chip 103 and the thickness of the adapter plate 102 (i.e. the thickness of the stack of the substrate 101, the first chip 103 and the adapter plate 102), and the thickness of the adapter plate 102 is less than the thickness of the second chip 104, which is thinner than the chip packaging assembly made by stacking the substrate 101, the first chip 103 and multiple second chips 104 in the thickness direction through the existing POP technology.

[0239] Based on the chip packaging assembly 10 provided in Embodiment Three of the application, the application further provides a preparation method of the chip packaging assembly 10. Referring to the preparation flowchart of the chip packaging assembly 10 shown in FIGS. 21a-21d, it is assumed that the preparation method includes the following steps:

[0240] Step one, as shown in FIG. 21a, the first surface 1031 of the first chip 103 and the third surface 1041 of the second chip 104 are respectively attached on the side of the substrate 101 provided with the first pads 1011. The specific implementation method of this step can refer to the related description of FIG. 21a in Embodiment Two, which will not be repeated here.

[0241] Step two, as shown in FIG. 21b, the electrical connector 109 is arranged on the substrate 101.

[0242] As an example but not limitation, in the case of the electrical connector 109 being a board-to-board connector, the male seat of the board-to-board connector can be fixed on the side of the substrate 101 provided with the first pads 1011 through a welding process, so that the board-to-board connector can be electrically connected with the first pads 1011.

[0243] Step three, as shown in FIG. 21c, the first area of the adapter plate 102 is attached to the second surface 1032 of the first chip 103, and the second area of the adapter plate 102 is fixedly connected with the electrical connector 109.

[0244] In one example, the surface of the first area of the adapter plate 102 and the surface of the second area can be tin sprayed and / or the area of the second surface 1032 of the first chip 103 provided with pads can be tin sprayed; then the first area of the adapter plate 102 is attached to the second surface 1032 of the first chip 103, and the second area of the adapter plate 102 is attached to the female seat of the board-to-board connector, so that the pads in the second area of the adapter plate 102 can be electrically connected with the first pads 1011 of the substrate 101 through the board-to-board connector. When the adapter plate 102 is attached to the first chip 103, the through hole 1025 provided in the first area of the adapter plate 102 corresponds to the area of the second surface 1032 of the first chip 103 provided with pads.

[0245] Step four, as shown in FIG. 21d, the pressing plate 20 is arranged on the top surface of the adapter plate 102, and the pressing plate 20, the adapter plate 102, the first chip 103, the second chip 104 and the substrate 101 are reflow soldered.

[0246] Specifically, the conductive connecting agent between the first chip 103 and the substrate 101, the conductive connecting agent between the second chip 104 and the substrate 101, and the conductive connecting agent between the adapter plate 102 and the first chip 103 can all be melted and solidified in the process of reflow soldering, so that the pads arranged on the first surface 1031 of the first chip 103 are electrically connected with the first pads 1011 of the substrate 101, the pads arranged on the second surface 1032 of the first chip 103 are electrically connected with the pads in the first area of the adapter plate 102, and the pads arranged on the third surface 1041 of the second chip 104 are electrically connected with the first pads 1011 of the substrate 101. The first chip 103 can communicate with the substrate 101 through the pads on the first surface 1031, and sequentially realize the communication function between the second chip 104 through the pads on the second surface 1032, the adapter plate 102, the electrical connecting piece 109, and the substrate 101.

[0247] In addition, as known from the foregoing, the pads arranged on the first surface 1031 of the first chip 103 can be electrically connected with the pads arranged on the third surface 1041 of the second chip 104 through the first pads 1011 of the substrate 101, wherein the function of the pads on the first surface 1031 of the first chip 103 can be different from the function of the pads on the second surface 1032, in which case the first chip 103 can also realize other communication functions between the second chip 104 through the pads on the first surface 1031 and the substrate 101.

[0248] In the process of reflow soldering in step four, the pressing plate 20 arranged on the top surface of the adapter plate 102 can apply pressure to the adapter plate 102, so that the adapter plate 102 is more closely attached to the first chip 103, and the pressing plate 20 can also correct the warping of the adapter plate 102 in the process of high-temperature heating. Further, after reflow soldering of the pressing plate 20, the adapter plate 102, the second chip 104, the substrate 101, and the first chip 103, the pressing plate 20 can be removed.

[0249] Step five, as shown in FIG. 21e, the fifth heat-conducting material 115 is filled in the through hole 1025 arranged on the first area of the adapter plate 102.

[0250] Optionally, after step five, the first heat-conducting material can also be filled in the gap between the first chip 103 and the substrate 101, the gap between the second chip 104 and the substrate 101, and the gap between the first area of the adapter plate 102 and the first chip 103 through the underfill process, and the first heat-conducting material is solidified, so as to improve the heat dissipation efficiency of the first chip 103 and the second chip 104, and improve the connection strength between the substrate 101 and the first chip 103 and the second chip 104, and the connection strength between the first chip 103 and the adapter plate 102, and improve the reliability of the chip packaging assembly 10.

[0251] Optionally, the fourth heat-conductive material 114 can also be arranged on the side of the adapter plate 102 opposite to the first chip 103, and / or the third heat-conductive material 113 can be arranged on the side of the substrate 101 opposite to the first chip 103, and along the thickness direction of the bottom plate 1022, the third heat-conductive material 113 arranged on the side of the substrate 101 opposite to the first chip 103 can overlap with the first chip 103 and / or overlap with the second chip 104, and the fourth heat-conductive material 114 arranged on the side of the adapter plate 102 opposite to the first chip 103 can overlap with the first chip 103, based on this method, the heat dissipation performance of the first chip 103 and the second chip 104 can be further improved.

[0252] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited to this, any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip packaging component, characterized in that, The application relates to a chip structure. The chip structure comprises a substrate (101), a transition plate (102), a first chip (103) and a second chip (104). The substrate (101) is provided with a first pad (1011), the first chip (103) comprises oppositely arranged first and second surfaces (1031 and 1032), the first pad (1011) is electrically connected with the first surface (1031), and the transition plate (102) is electrically connected with the second surface (1032). The second chip (104) is located on the side of the substrate (101) provided with the first pad (1011), and the second surface (1032) is electrically connected with the second chip (104) through the transition plate (102). The thickness of the transition plate (102) is smaller than the thickness of the second chip (104).

2. The chip package assembly of claim 1, wherein, The second chip (104) comprises oppositely arranged third and fourth surfaces (1041 and 1042). The third surface (1041) is electrically connected with the transition plate (102), the fourth surface (1042) is opposite to the substrate (101), and a gap is formed between the fourth surface (1042) and the substrate (101).

3. The chip package assembly of claim 2, wherein, A support (105) is arranged between the substrate (101) and the transition plate (102).

4. The chip package assembly of claim 2, wherein, A counterweight (111) is arranged on the transition plate (102) and used for balancing the weight of the second chip (104).

5. The chip package assembly of claim 4, wherein, The counterweight (111) is arranged on one side of the transition plate (102) facing the substrate (101) or on one side of the transition plate (102) away from the substrate (101).

6. The chip package assembly of any one of claims 2 to 5, wherein, A first avoiding groove (1012) is arranged on the substrate (101), and the fourth surface (1042) is located in the first avoiding groove (1012).

7. The chip package assembly of any one of claims 2-5, wherein, A second avoiding groove (1021) is arranged on the transition plate (102), and the third surface (1041) is electrically connected with the bottom wall of the second avoiding groove (1021).

8. The chip package assembly of any one of claims 2-7, wherein, The first surface (1031) is electrically connected with the substrate (101) through a first conductive connecting agent (106), the second surface (1032) is electrically connected with the transition plate (102) through a second conductive connecting agent (107), and the third surface (1041) is electrically connected with the transition plate (102) through a third conductive connecting agent (108). The melting points of the first, second and third conductive connecting agents (106, 107 and 108) are the same, or the melting points of the first and third conductive connecting agents (106 and 108) are both greater than the melting point of the second conductive connecting agent (107).

9. The chip package assembly of claim 1, wherein, The second chip (104) comprises a third surface (1041). The third surface (1041) is electrically connected with the substrate (101), a first area of the adapter board (102) is electrically connected with the second surface (1032), a second area of the adapter board (102) is electrically connected with the substrate (101), and the second chip (104) is electrically connected with the second surface (1032) through the substrate (101) and the adapter board (102).

10. The chip package assembly of claim 9, wherein, The adapter board (102) comprises a bottom plate (1022) and a side plate (1023) arranged on a fifth surface (10221) of the bottom plate (1022), the first area is the fifth surface (10221), the second area is a side of the side plate (1023) away from the bottom plate (1022), and the first chip (103) is located in a receiving cavity (110) formed between the fifth surface (10221), the side plate (1023) and the substrate (101).

11. The chip package assembly of any one of claims 1 to 10, wherein, The adapter board (102) is a grid array packaging circuit board.

12. The chip package assembly of claim 9, wherein, The adapter board (102) is a flexible printed circuit board or a rigid-flex printed circuit board, and the first area and the second area are located on the same side of the adapter board (102).

13. The chip package assembly of claim 12, wherein, The second area is electrically connected with the substrate (101) through an electrical connector (109).

14. The chip package assembly of any one of claims 1 to 8, wherein, A first heat-conducting material is filled between the second chip (104) and the adapter board (102).

15. The chip package assembly of any one of claims 9, 10, 12, and 13, wherein, A first heat-conducting material is filled between the third surface (1041) and the first area, and / or a fourth surface (1042) of the second chip (104) is provided with a second heat-conducting material, and the third surface (1041) and the fourth surface (1042) are oppositely arranged.

16. The chip package assembly of any one of claims 1 to 15, wherein, A first heat-conducting material is filled between the first surface (1031) and the substrate (101), and / or the first heat-conducting material is filled between the second surface (1032) and the adapter board (102).

17. The chip package assembly of any one of claims 1 to 16, wherein, A third heat-conducting material (113) is arranged on a side of the substrate (101) away from the first chip (103), and / or a fourth heat-conducting material (114) is arranged on a side of the adapter board (102) away from the first chip (103); Along the thickness direction of the adapter board (102), the third heat-conducting material (113) and the first chip (103) overlap each other, and the fourth heat-conducting material (114) and the first chip (103) overlap each other.

18. The chip package assembly of any one of claims 1 to 17, wherein, A through hole (1025) is arranged on the adapter board (102), and the through hole (1025) is located in the orthographic projection of the first chip (103) on the adapter board (102).

19. The chip package assembly of claim 18, wherein, A fifth heat-conducting material (115) is filled in the through hole (1025).

20. The chip package assembly of claim 18, wherein, The chip packaging assembly further comprises a heat-conducting metal block (112). One end of the heat-conducting metal block (112) is connected with a heat dissipation device (30), the other end of the heat-conducting metal block (112) is inserted into the through hole (1025), the heat-conducting metal block (112) and the adapter plate (102) are filled with a fifth heat-conducting material (115), and the heat dissipation device (30) is located on a side of the adapter plate (102) away from the substrate (101).

21. A method of fabricating a chip package assembly, comprising: The method comprises: electrically connecting a first surface (1031) of a first chip (103) with a first pad (1011) of a substrate (101); electrically connecting an adapter plate (102) with a second surface (1032) of the first chip (103) and electrically connecting the second surface (1032) with a second chip (104) through the adapter plate (102); wherein the first surface (1031) and the second surface (1032) are oppositely arranged, the second chip (104) is located on a side of the substrate (101) provided with the first pad (1011), and a thickness of the adapter plate (102) is less than a thickness of the second chip (104).

22. The method of claim 21, wherein, The second chip (104) comprises a third surface (1041) and a fourth surface (1042) arranged oppositely; electrically connecting the adapter plate (102) with the second surface (1032) of the first chip (103) and electrically connecting the second surface (1032) with the second chip (104) through the adapter plate (102) comprises: attaching the third surface (1041) on the adapter plate (102) through a third conductive connecting agent (108); reflow soldering the adapter plate (102) and the second chip (104); electrically connecting the adapter plate (102) with the second surface (1032), wherein the fourth surface (1042) is opposite to the substrate (101) and has a gap between the fourth surface (1042) and the substrate (101).

23. The method of claim 22, wherein, Before electrically connecting the adapter plate (102) with the second surface (1032), the method further comprises: providing a first avoiding slot (1012) on the substrate (101), and the fourth surface (1042) is located in the first avoiding slot (1012).

24. The method of claim 22, wherein, attaching the third surface (1041) on the adapter plate (102) through a third conductive connecting agent (108) comprises: providing a second avoiding slot (1021) on the adapter plate (102); attaching the third surface (1041) on a bottom wall of the second avoiding slot (1021) through a third conductive connecting agent (108).

25. The method of any one of claims 22-24, wherein, The method further comprises: providing a supporting piece (105) between the adapter plate (102) and the substrate (101).

26. The method of any one of claims 22-24, wherein, The method further comprises: providing a counterweight (111) on the adapter plate (102), and the counterweight (111) is used for balancing the weight of the second chip (104).

27. The method of any one of claims 22-26, wherein, The first surface (1031) of the first chip (103) is electrically connected with the first pad (1011) of the substrate (101) by a first conductive connecting agent (106). The first surface (1031) is attached to the first pad (1011) of the substrate (101) by the first conductive connecting agent (106). The adapter board (102) is electrically connected with the second surface (1032) by a second conductive connecting agent (107). The adapter board (102) is attached to the second surface (1032) by the second conductive connecting agent (107). The adapter board (102), the second chip (104), the substrate (101) and the first chip (103) are reflow soldered.

28. The method of claim 27, wherein, The melting point of the first conductive connecting agent (106) and the melting point of the third conductive connecting agent (108) are both greater than the melting point of the second conductive connecting agent (107). After the first surface (1031) is attached to the substrate (101) by the first conductive connecting agent (106), the method further comprises: The substrate (101) and the first chip (103) are reflow soldered.

29. The method of claim 27, wherein, The melting point of the first conductive connecting agent (106), the melting point of the second conductive connecting agent (107) and the melting point of the third conductive connecting agent (108) are the same.

30. The method of any one of claims 27-29, wherein, The reflow soldering of the adapter board (102), the second chip (104), the substrate (101) and the first chip (103) comprises: A pressing plate (20) is arranged on the side of the adapter board (102) away from the second chip (104); The pressing plate (20), the adapter board (102), the second chip (104), the substrate (101) and the first chip (103) are reflow soldered.

31. The method of claim 21, wherein, The second chip (104) comprises a third surface (1041). The adapter board (102) is electrically connected with the second surface (1032) of the first chip (103), and the second surface (1032) is electrically connected with the second chip (104) through the adapter board (102), which comprises: A first area of the adapter board (102) is electrically connected with the second surface (1032); A second area of the adapter board (102) is electrically connected with the substrate (101); The third surface (1041) is electrically connected with the substrate (101).

32. The method of claim 31, wherein, The adapter board (102) comprises a bottom plate (1022) and a side plate (1023) arranged on a fifth surface (10221) of the bottom plate (1022), the first area is the fifth surface (10221), the second area is the side of the side plate (1023) away from the bottom plate (1022), and the first chip (103) is located in a receiving cavity (110) formed between the fifth surface (10221), the side plate (1023) and the substrate (101).

33. The method of any one of claims 21-32, wherein, The adapter board (102) is a grid array package circuit board.

34. The method of claim 31, wherein, The adapter plate (102) is a flexible printed circuit board or a rigid-flex printed circuit board, and the first region and the second region are located on the same surface of the adapter plate (102).

35. The method of claim 34, wherein, The second region of the adapter plate (102) is electrically connected to the substrate (101) by an electrical connector (109).

36. The method of any one of claims 21-30, wherein, The method further comprises: A first thermal conductive material is filled in a gap between the second chip (104) and the adapter plate (102).

37. The method of any one of claims 31, 32, 34, and 35, wherein, The method further comprises: A first thermal conductive material is filled in a gap between the third surface (1041) and the first region, and / or a second thermal conductive material is arranged on a fourth surface (1042) of the second chip (104), the third surface (1041) and the fourth surface (1042) being oppositely arranged.

38. The method of any one of claims 21-37, wherein, The method further comprises: A first thermal conductive material is filled in a gap between the first surface (1031) and the substrate (101), and / or the first thermal conductive material is filled in a gap between the second surface (1032) and the adapter plate (102).

39. The method of any one of claims 21-38, wherein, The method further comprises: A third thermal conductive material is arranged on a surface of the substrate (101) away from the first chip (103), and / or a fourth thermal conductive material is arranged on a surface of the adapter plate (102) away from the first chip (103); Along the thickness direction of the adapter plate (102), the third thermal conductive material and the first chip (103) overlap each other, and the fourth thermal conductive material and the first chip (103) overlap each other.

40. The method of any one of claims 21-39, wherein, A through hole (1025) is arranged on the adapter plate (102), and the through hole (1025) is located in the orthographic projection of the first chip (103) on the adapter plate (102). The method further comprises: A fifth thermal conductive material is filled in the through hole (1025).

41. An electronic device, comprising: The chip package assembly (10) according to any one of claims 1 to 20.

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