Memory chip control method, memory controller and memory system

Abstract

A memory chip control method, a memory controller, and a memory system. The control method comprises: applying a read voltage to multiple first memory cells corresponding to a first address; in response to a failure rate of the multiple first memory cells being greater than a first threshold, refreshing the data stored in multiple second memory cells, the first threshold being less than a second threshold that triggers the memory chip UCE, the multiple second memory cells being memory cells affected by read interference or write interference, and the multiple second memory cells being multiple first memory cells, or the multiple second memory cells being multiple first memory cells and memory cells adjacent to the multiple first memory cells. The present control method can improve the stability of data stored in a memory chip.

Description

Control method of storage chip, storage controller and storage system

[0001] The present application claims priority to the Chinese patent application No. 202410851268.X, filed on June 27, 2024, and entitled "Control method of storage chip, storage controller and storage system", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of storage, in particular to a control method of storage chip, a storage controller and a storage system. BACKGROUND

[0003] With the development of storage technology, the storage performance of storage chips is also getting higher and higher, and the stability of the data stored by the storage chips is also becoming more and more important.

[0004] Read interference and write interference are important factors affecting the stability of the data stored by the storage chip. Read interference refers to the influence of the conduction current inside the storage unit on the storage state of the storage unit when the read operation is frequently performed on the storage unit. Write interference refers to the influence of the temperature rise of the storage unit itself on the storage state of the storage unit itself and the surrounding storage units when the write operation is frequently performed on the storage unit. Among them, read interference mainly disturbs the storage unit from low resistance state to high resistance state, and write interference mainly disturbs the storage unit from high resistance state to low resistance state.

[0005] Currently, there is no optimization scheme for read interference and write interference in the storage chip, resulting in low stability of the data stored by the storage chip. SUMMARY

[0006] The embodiments of the present application provide a control method of storage chip, a storage controller and a storage system, which can improve the stability of the data stored by the storage chip. The corresponding technical solutions are as follows:

[0007] In a first aspect, a control method of storage chip is provided, comprising: applying a read voltage to a plurality of first storage units corresponding to a first address. In response to the failure rate of the plurality of first storage units being greater than a first threshold value, refreshing the data stored in a plurality of second storage units, wherein the first threshold value is less than a second threshold value triggering UCE of the storage chip, the plurality of second storage units are storage units affected by read interference or write interference, and the plurality of second storage units are the plurality of first storage units, or the second storage unit is the plurality of first storage units and the storage units adjacent to the plurality of first storage units.

[0008] In the scheme shown in the present application, after performing the read operation on the plurality of first storage units of the first address, if it is determined that the failure rate of the read result of the first storage unit is greater than the first threshold value, it is considered that the first storage unit may be affected by read interference or write interference. Then the data stored in the plurality of second storage units (the plurality of second storage units include the first storage unit) which may be affected by read interference or write interference can be refreshed to restore the threshold voltage of the storage unit affected by read interference or write interference to the state not affected by read interference or write interference. Since the first threshold value is smaller than the second threshold value triggering the UCE of the storage chip, the scheme shown in the present application can eliminate the influence of read interference or write interference on the storage unit before triggering the UCE of the storage chip, thereby improving the stability of the data stored in the storage chip and reducing the probability of triggering the UCE of the storage chip.

[0009] In an implementable manner, in response to the failure rate of the plurality of first storage units being greater than the first threshold value, refreshing the data stored in the plurality of second storage units includes: in response to the failure rate of the plurality of first storage units being greater than the first threshold value, determining the interference type corresponding to the plurality of first storage units, the interference type being read interference or write interference. In the case where it is determined that the interference type is read interference, it is determined that the plurality of first storage units are the plurality of second storage units, and the data stored in the second storage units is refreshed. In the case where it is determined that the interference type is read interference, it is determined that the plurality of first storage units and the storage units adjacent to the plurality of first storage units are the second storage units, and the data stored in the second storage units is refreshed.

[0010] In the scheme shown in the present application, it can be determined whether the first storage unit is mainly affected by read interference or write interference, and the storage unit can be selectively refreshed according to the different interference types of the first storage unit. In the case where the first storage unit is affected by read interference, only the data of the first storage unit is refreshed to reduce the number of storage units to be refreshed and reduce the power consumption of the storage chip. In the case where the first storage unit is affected by write interference, the data of the first storage unit and the storage units adjacent to the first storage unit can be refreshed to ensure that the data refresh is performed on the storage units affected by write interference, thereby improving the stability of the data stored in the storage chip.

[0011] In an implementable manner, determining the interference type corresponding to the plurality of first storage units includes: in the plurality of first storage units, determining the proportion of the number of failed low-resistance state first storage units in the total number of failed first storage units. In the case where the proportion is greater than a third threshold value, it is determined that the interference type is read interference, and in the case where the proportion is less than or equal to the third threshold value, it is determined that the interference type is write interference.

[0012] In the scheme shown in the present application, the interference type corresponding to the plurality of first storage units can be determined according to the number of failed low-resistance-state first storage units, or the proportion of the number of failed high-resistance-state first storage units in the total number of failures. In this way, by distinguishing the interference type corresponding to the first storage unit, the range of the second storage unit subjected to read interference or write interference can be accurately determined, avoiding the missed brushing of the storage unit subjected to interference, or the mistaken brushing of the storage unit not subjected to interference, thereby reducing the power consumption of the storage chip and improving the stability of the storage chip in storing data.

[0013] In an implementable manner, the step of applying a read voltage to the plurality of first storage units corresponding to the first address includes: applying a plurality of gear read voltages to the plurality of first storage units corresponding to the first address, the plurality of gear read voltages increasing in turn. The step of refreshing the data stored in the plurality of second storage units in response to the failure rate of the plurality of first storage units being greater than the first threshold includes: refreshing the data stored in the plurality of second storage units in response to the failure rate obtained by applying each gear read voltage to the plurality of first storage units being greater than the first threshold.

[0014] In the scheme shown in the present application, when the failure rate obtained by applying a plurality of gear read voltages to the first storage unit is greater than the first threshold, refreshing the data stored in the storage unit is triggered. In this way, the influence of read interference or write interference on the first storage unit can be eliminated before the first storage unit fails to read, thereby reducing the number of refreshes of the storage unit under the premise of ensuring the stability of the storage chip in storing data, and reducing the power consumption of the storage chip.

[0015] In an implementable manner, after the step of applying a plurality of gear read voltages to the plurality of first storage units corresponding to the first address, the method further includes: performing error correction processing on the target read data to obtain read data after error correction processing, the target read data being a group of read data corresponding to the lowest failure rate in a plurality of groups of read data obtained by applying a plurality of gear read voltages respectively. The step of refreshing the data stored in the plurality of second storage units includes: writing the read data after error correction processing into the first storage unit included in the plurality of second storage units.

[0016] In the scheme shown in the present application, when refreshing the data of the first storage unit, the target read data corresponding to the lowest failure rate can be selected for error correction, and the data after error correction can be re-written into the first storage unit. In this way, the target read data with the lowest failure rate is subjected to error correction, which can improve the accuracy of error correction on the target read data, and thereby improve the accuracy of the data stored in the first storage unit after refreshing.

[0017] In an implementable manner, the storage unit adjacent to the plurality of first storage units comprises a third storage unit adjacent to the plurality of first storage units on the same bit line or word line, and the method further comprises: determining a fourth storage unit adjacent to the third storage unit on the same bit line or word line as the second storage unit. In this way, the range of the second storage unit is expanded, and it can be ensured that the storage units affected by the write disturbance are refreshed, thereby improving the stability of the storage data of the storage chip.

[0018] In an implementable manner, it can be obtained through experimental data that the third threshold value is between one-half and four-fifths, and the accuracy of distinguishing the read disturbance and the write disturbance is higher.

[0019] In an implementable manner, the storage chip is a phase change storage chip, and the storage unit included in the phase change storage chip is a phase change storage unit.

[0020] In a second aspect, a storage controller is provided, which is connected with a storage chip, and the storage controller is configured to:

[0021] applying a read voltage to a plurality of first storage units corresponding to a first address in the storage chip; and in response to a failure rate of the plurality of first storage units being greater than a first threshold value, refreshing data stored in a plurality of second storage units, wherein the first threshold value is less than a second threshold value triggering uncorrectable error (UCE) of the storage chip, the plurality of second storage units are storage units affected by read disturbance or write disturbance, and the plurality of second storage units are the plurality of first storage units, or the second storage units are the plurality of first storage units and storage units adjacent to the plurality of first storage units.

[0022] In an implementable manner, the storage controller is configured to: in response to the failure rate of the plurality of first storage units being greater than the first threshold value, determine a disturbance type corresponding to the plurality of first storage units, the disturbance type being read disturbance or write disturbance; in a case where the disturbance type is determined to be read disturbance, determine that the plurality of first storage units are the plurality of second storage units, and refresh data stored in the second storage units; and in a case where the disturbance type is determined to be read disturbance, determine that the plurality of first storage units and the storage units adjacent to the plurality of first storage units are the second storage units, and refresh data stored in the second storage units.

[0023] In an implementable manner, the storage controller is configured to: in the plurality of first storage units, determine a proportion of a number of failed low-resistance-state first storage units in a total number of failed first storage units. In a case where the proportion is greater than a third threshold value, the disturbance type is determined to be read disturbance, and in a case where the proportion is less than or equal to the third threshold value, the disturbance type is determined to be write disturbance.

[0024] In an implementable manner, the storage controller is configured to: apply read voltages of multiple levels to the multiple first storage units corresponding to the first address, the read voltages of the multiple levels being sequentially increased. In response to the failure rate obtained by applying the read voltage of each level to the multiple first storage units being greater than a first threshold, the storage controller is configured to perform refresh on the data stored in the multiple second storage units.

[0025] In an implementable manner, the storage controller is further configured to: perform error correction processing on the target read data to obtain read data after error correction processing, the target read data being a group of read data corresponding to the lowest failure rate in multiple groups of read data obtained by applying the read voltages of the multiple levels, respectively. The storage controller is configured to write the read data after error correction processing into the first storage unit included in the multiple second storage units.

[0026] In an implementable manner, the storage unit adjacent to the multiple first storage units includes a third storage unit adjacent to the multiple first storage units on the same bit line or word line. The storage controller is further configured to: determine a fourth storage unit adjacent to the third storage unit on the same bit line or word line as the second storage unit.

[0027] In an implementable manner, the third threshold is between one-half and four-fifths.

[0028] In an implementable manner, the first storage unit is a phase change storage unit.

[0029] In a third aspect, a storage system is provided. The storage system includes the storage controller according to the second aspect, and at least one storage chip connected to the storage controller.

[0030] In a fourth aspect, an electronic device is provided. The electronic device includes a processor and the storage system according to the third aspect. The processor is configured to send a read-write instruction to the storage system to enable the storage system to perform a read-write operation. BRIEF DESCRIPTION OF DRAWINGS

[0031] FIG. 1 is a structural schematic diagram of a storage chip according to an embodiment of the present application;

[0032] FIG. 2 is a structural schematic diagram of a control circuit according to an embodiment of the present application;

[0033] FIG. 3 is a structural schematic diagram of a storage system according to an embodiment of the present application;

[0034] FIG. 4 is a threshold voltage distribution diagram of a storage unit according to an embodiment of the present application;

[0035] FIG. 5 is a schematic diagram of a storage unit affected by write disturbance and read disturbance according to an embodiment of the present application;

[0036] FIG. 6 is a flowchart of a control method of a memory chip according to an embodiment of the present application;

[0037] FIG. 7 is a threshold voltage distribution diagram of a memory cell according to an embodiment of the present application;

[0038] FIG. 8 is a flowchart of a control method of a memory chip according to an embodiment of the present application;

[0039] FIG. 9 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] For the purpose of making the purpose, technical scheme and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0041] Some terms involved in the embodiments of the present application will be explained below:

[0042] Resistive memory: data is stored or read by using the change of resistance. For example, resistive memory can realize the storage of "0" in a high configuration and the storage of "1" in a low configuration.

[0043] Phase change memory (PCM): a new type of non-volatile semiconductor memory based on chalcogenide compounds, which belongs to a type of resistive memory. The resistive memory can realize the storage of "0" and "1" by using the different resistances of the crystalline and amorphous states of the phase change material. When the phase change material is in the amorphous state, the phase change material is in a high resistance state, i.e., has a high resistance value, and is defined as a RESET (0) state. When the phase change material is in the crystalline state, the phase change material is in a low resistance state, i.e., has a low resistance value, and is defined as a SET (1) state.

[0044] Ovonic threshold switch (OTS): a new type of bidirectional gating device based on chalcogenide compounds. When an electric pulse with an arbitrary positive or negative direction and lower than the threshold voltage corresponding to the ovonic threshold switch is applied to the ovonic threshold switch, the response current on the ovonic threshold switch is small, and the ovonic threshold switch presents a high resistance non-conducting state. When an electric pulse with an arbitrary positive or negative direction and higher than the threshold voltage corresponding to the ovonic threshold switch is applied to the ovonic threshold switch, the response current on the ovonic threshold switch is large, and the ovonic threshold switch presents a low resistance conducting state.

[0045] 1S1R memory cell: a memory cell consisting of one OTS and one PCM. In one implementation, when the PCM in the 1S1R memory cell is in RESET (0) state, the 1S1R memory cell stores "0", and the 1S1R memory cell has a higher threshold voltage Vthr. When the PCM in the 1S1R memory cell is in SET (1) state, the 1S1R memory cell stores "1", and the 1S1R memory cell has a lower threshold voltage Vths. Wherein, Vthr is equal to the threshold voltage of the OTS plus the threshold voltage corresponding to the PCM in RESET (0) state, and Vths is equal to the threshold voltage of the OTS plus the threshold voltage corresponding to the PCM in SET (1) state.

[0046] Based on the above characteristics, when the 1S1R memory cell stores "0", the 1S1R device cell has a smaller response current under a certain read voltage Vread (greater than Vths and less than Vthr); when the 1S1R memory cell stores "1", the 1S1R device cell has a larger response current under a certain read voltage Vread. In this way, the data stored in the 1S1R memory cell can be read by applying a read voltage Vread.

[0047] Erasing operation: achieved by applying a high-amplitude narrow-width electrical pulse to the 1S1R memory cell. The amplitude of the electrical pulse is higher than the threshold voltage of the OTS, and under the action of the electrical pulse, the temperature of the PCM in the 1S1R memory cell is rapidly raised above the melting temperature and then quenched. Since the micro atoms do not have sufficient time to crystallize, they remain in a high-resistance amorphous state, i.e. "0" is stored.

[0048] Write operation: achieved by applying an electrical pulse with a relatively low amplitude but a relatively long duration to the 1S1R memory cell. The amplitude of the electrical pulse is higher than the threshold voltage of the OTS, and under the action of the electrical pulse, the temperature of the PCM in the 1S1R memory cell is raised above the crystallization temperature and below the melting temperature. The PCM can be converted to a low-resistance state through a thermal crystallization process, i.e. "1" is stored.

[0049] Read operation: the data stored in the 1S1R memory cell can be read by applying a fixed read voltage Vread across the 1S1R memory cell and according to the response current of the 1S1R memory cell.

[0050] Word line: a signal line required to select a row of 1S1R memory cells in the memory array. Together with the bit line, it can complete the selection of a 1S1R memory cell.

[0051] Bit line: the signal line required for selecting a column in the storage array, which can select a 1S1R memory cell together with the word line. By applying corresponding electrical pulses to the word line and the bit line, the above-mentioned write operation, erase operation or read operation can be performed on the selected 1S1R memory cell.

[0052] Figure 1 is a structural schematic diagram of a storage chip according to an embodiment of the present application. As shown in Figure 1, the storage chip 100 includes a control circuit 110 and at least one storage bank 120 (Bank 120), and each Bank 120 includes a plurality of storage arrays 121. The plurality of storage arrays 121 included in the plurality of Banks 120 can generally be tiled on the same plane or can be stacked in three-dimensional space. Each storage array 121 includes storage cells arranged in rows and columns, and when performing read / write operations on the storage cells of the storage chip 100, a storage cell can be selected in each storage array 121 to perform read / write operations on the selected storage cells. In this way, the storage capacity and storage performance of the storage chip can be improved without increasing the area occupied by the storage chip.

[0053] Figure 2 is a schematic diagram of a control circuit according to an embodiment of the present application. As shown in Figure 2, the control circuit 110 includes a logic control circuit 1101, an address register 1102, a Bank selection circuit 1103, a row address multiplexing circuit 1104, a column address multiplexing circuit 1105, and a row decoder 1106, a column decoder 1107, a driving circuit 1108 and a sensing circuit (SA) 1109 corresponding to each storage array, wherein:

[0054] The logic control circuit 1101 can be used to receive read / write operation requests sent by an external device, control the timing of performing read / write operations, etc. For example, the address of the storage cell to be executed for read / write operation is sent to the address register 1102, and the type of operation to be performed, such as write operation, read operation, etc., is sent to the driving circuit.

[0055] The address register 1102 can receive and store the address of the storage cell to be executed for read / write operation sent by the logic control circuit 1101. The address includes the row address, column address and Bank address of the storage cell.

[0056] The Bank selection circuit 1103 can select the Bank where the storage cell to be executed for read / write operation is located from the plurality of Banks according to the Bank address of the storage cell to be executed for read / write operation.

[0057] The row address multiplexing circuit 1104 can send the row address corresponding to the storage unit to be executed read, write, etc. operation to the row decoder 1106 corresponding to each storage array 121 included in the selected Bank. The column address multiplexing circuit 1105 can send the column address corresponding to the storage unit to be executed read, write, etc. operation to the column decoder 1107 corresponding to each storage array 121 included in the selected Bank.

[0058] For each row decoder 1106 receiving the row address, each row decoder 1106 can decode the row address to select the row where the storage unit to be executed read, write, etc. operation is located. For each column decoder 1107 receiving the column address, each column decoder 1107 can decode the column address to select the column where the storage unit to be executed read, write, etc. operation is located. The storage unit selected by the row decoder 1106 and the column decoder 1107 at the same time is the storage unit to be executed read, write, etc. operation.

[0059] For each drive circuit 1108 included in the selected Bank, each drive circuit 1108 can apply an operation voltage to the selected storage unit in the corresponding storage array 121 according to the received operation type, to complete the corresponding operation.

[0060] For each sensing circuit 1109 included in the selected Bank, each sensing circuit 1109 can determine the data stored in the storage unit by detecting the current size or voltage size after the drive circuit 1108 completes the read operation voltage applied to the storage unit.

[0061] FIG. 3 is a schematic diagram of a storage system according to an embodiment of the present application. As shown in FIG. 3, the storage system 300 includes a storage controller 200 and one or more storage chips 100 as shown in FIG. 1. Wherein:

[0062] The storage controller 200 is a hardware device for controlling the storage chip 100 to perform read, write, etc. operation. The storage controller 200 can send the storage chip 100 an operation request corresponding to a read operation, a write operation or an erase operation, so that the control circuit 110 in the storage chip 100 selects the storage unit through the word line and the bit line, and applies a read voltage, a write voltage or an erase voltage to the selected storage unit, thereby realizing the execution of the read operation, the write operation or the erase operation. In order to cope with the read error of the storage unit, the storage controller 200 is also provided with an error correction algorithm, such as Error Correction Code (ECC). The error correction algorithm can check and correct the read result of the storage chip to avoid or reduce the read error data.

[0063] 1S1R memory cell can be disturbed by some factors during the write or read operation, which changes the physical state of the 1S1R memory cell as a whole, and then causes the change of Vth, thereby causing the read abnormality of the cell. These disturbance factors include read disturbance, write disturbance, threshold voltage drift caused by long-term storage, etc.

[0064] Threshold voltage drift of OTS: the threshold voltage of OTS changes over time due to the voltage applied to OTS, ambient temperature, etc., which is called threshold voltage drift of OTS.

[0065] OTS has a large current conduction capability under the voltage greater than the threshold voltage, which is caused by the transition of the balanced non-conductive electrons in the low-energy state to the unbalanced conductive state in the high-energy state under the action of high voltage. When the voltage applied to the OTS is removed, the high-energy unbalanced carriers in the OTS do not return to the balanced state at once, but gradually return to the low-energy balanced non-conductive state according to a certain probability. Therefore, after each operation of the 1S1R memory cell, the threshold voltage of the OTS in the 1S1R memory cell will suddenly decrease, and then gradually increase over time. The greater the voltage applied to the OTS, the more the threshold voltage of the OTS decreases, and the higher the ambient temperature of the OTS, the faster the threshold voltage drifts upward. In addition, when the OTS is placed for a long time, its threshold voltage will also drift to a higher state.

[0066] Figure 4 is a threshold voltage distribution diagram provided by the embodiment of the present application. As shown in Figure 4, unlike the threshold voltage drift of OTS, the threshold voltage drift mainly causes the threshold voltage to increase, and the curve shape of the threshold voltage distribution remains basically unchanged. Read disturbance and write disturbance are mainly caused by the electrical and thermal interference of the memory cell, which affects the OTS and PCM as a whole. On the one hand, it makes the threshold voltage increase, and on the other hand, it makes the curve of the threshold voltage distribution widen, thereby causing the distribution curves of the memory cell "0" and "1" to overlap.

[0067] In an example, write disturbance refers to the disturbance (mainly thermal disturbance) of the memory cell of a certain address to the adjacent, next adjacent, and next next adjacent memory cells when frequently writing, which causes the thermal crystallization of the high-resistance "0" state of the adjacent cell to the low-resistance "1" state. The memory cell that may be affected is also called PV (potential-victim), and the closer the distance, the greater the impact. As shown in Figure 4, write disturbance mainly widens the curve shape of the threshold voltage of the high-resistance "0" state, so that part of the threshold voltage of the high-resistance "0" state overlaps with the threshold voltage of the low-resistance "1" state.

[0068] In an example, the read disturbance is because the storage unit at a certain address can be affected by the cumulative effect of the current floating during the frequent read-on of the self-reading, etc. (mainly current disturbance), resulting in the self-stored low-resistance "1" state being misjudged as a "0" state. As shown in FIG. 4, the write disturbance is mainly to widen the curve shape of the threshold voltage of the low-resistance "1" state, so that part of the threshold voltage of the low-resistance "1" state overlaps with the threshold voltage of the high-resistance "0" state.

[0069] FIG. 5 is a schematic diagram of a storage unit affected by write disturbance and read disturbance respectively according to an embodiment of the present application. As shown in FIG. 5, when a write operation is frequently performed on a target storage unit a, the target storage unit a and the plurality of storage units (PV) adjacent to the target storage unit a can all be affected by the high temperature of the target storage unit, resulting in a change in the storage state, and among them, the storage unit storing the high-resistance state "0" is disturbed to the storage unit storing the low-resistance state "1". The plurality of storage units adjacent to the target storage unit a can include storage units b, c, d, e, etc. When a read operation is frequently performed on a target storage unit n, the target storage unit n will be frequently turned on, and the conduction current will continuously affect the storage state of the target storage unit n, thereby causing a change in the storage state, and among them, the storage unit storing the low-resistance state "1" is disturbed to the storage unit storing the high-resistance state "0".

[0070] The embodiment of the present application provides a control method of a storage chip. In the process of normal reading of the storage chip, if it is determined that the failure rate of the storage unit at a certain address is greater than the set failure rate threshold, the reason for the high failure rate of the storage unit at the address can be further determined, including whether it is affected by write disturbance or read disturbance. According to the different reasons for the high failure rate of the storage unit and the characteristics of the disturbance of the read and write operations on the storage unit in the storage chip, a refresh operation is performed on the corresponding storage unit to refresh the storage state in the storage unit to the storage state before being disturbed, thereby improving the stability of the storage data of the storage chip and avoiding the uncorrectable problem caused by the write disturbance or the read disturbance of the storage chip.

[0071] FIG. 6 is a flowchart of a control method of a storage chip according to an embodiment of the present application, which can be executed by the storage controller described above. Referring to FIG. 6, the method comprises:

[0072] In step 601, the storage controller applies a read voltage to a plurality of first storage units corresponding to a first address.

[0073] In implementation, the storage controller can receive a read request sent by the host. After receiving the read request, the storage controller can send a first address corresponding to the read request to a control circuit in the storage chip, and then the control circuit of the storage chip applies a read voltage to a plurality of first storage units corresponding to the first address to perform a read operation on the plurality of first storage units. The process of the control circuit applying the read voltage to the plurality of first storage units can refer to the above-mentioned embodiment content corresponding to FIG. 2, which will not be described here. In the embodiments of the present application, the storage chip can be a phase change storage chip, and the storage unit included therein can be a phase change storage unit, such as a 1S1R storage unit.

[0074] In step 602, in response to the failure rate of the plurality of first storage units being greater than a first threshold, the data stored in the plurality of second storage units is refreshed. The first threshold is less than a second threshold that triggers an Uncorrectable Error (UCE) of the storage chip. The plurality of second storage units are storage units affected by read interference or write interference. The plurality of second storage units are the plurality of first storage units, or the second storage units are the plurality of first storage units and the storage units adjacent to the plurality of first storage units.

[0075] After performing the read operation on the plurality of first storage units, the sensing circuit included in the control circuit can obtain the read results corresponding to the plurality of first storage units, and the read results of each first storage unit can be stored in the register included in the control circuit. The first storage unit read result is "1" or "0". In an example, when the read result is "1", it can indicate that the storage state of the first storage unit is in a low resistance state, and when the read result is "0", it can indicate that the storage state of the first storage unit is in a high resistance state.

[0076] The storage controller can read the read results stored in the register, and then determine the failure rate corresponding to the read results by using an error correction algorithm, such as an Error Correction Code (ECC). The failure rate can be represented by the number of storage units with data failure in the plurality of first storage units, such as the Fail bit count (FBC), or the proportion of the number of storage units with data failure in the plurality of first storage units.

[0077] The second storage unit is a storage unit that may be affected by read interference or write interference, i.e., a PV. When the failure rate of the plurality of first storage units is greater than a first threshold, it indicates that the plurality of first storage units may be affected by read interference or write interference, resulting in a high failure rate. Therefore, the plurality of first storage units can be determined as at least the second storage unit to be subjected to data refresh, and the data stored in the plurality of second storage units is refreshed to eliminate the influence of read interference or write interference on the storage state of the storage unit, thereby ensuring the accuracy of the data stored in the storage unit. The first threshold is less than the second threshold that triggers the UCE of the storage chip, so that after the failure rate of the plurality of first storage units is determined to be greater than the first threshold, the error correction algorithm can correct the read results of the plurality of first storage units, and then refresh the data stored in the first storage unit. In an example, the first threshold is between 0.5 and 0.99 times the second threshold.

[0078] Since the first storage unit is affected by write interference, the storage units around the first storage unit may also be affected by write interference. As shown in FIG. 5, when the write operation is frequently performed on the storage unit a, in addition to the storage unit a being affected by write interference, the high temperature generated by the storage unit a is also transmitted to the storage units b, c, d, and e through some medium, so that the storage units b, c, d, and e may also be affected by write interference. Therefore, when it is determined that the first storage unit may be affected by write interference, even if it cannot be directly determined whether the first storage unit is a storage unit that frequently performs a write operation, it can be determined that the storage unit adjacent to the first storage unit may also be affected by write interference. Therefore, in the embodiments of the present application, in order to further eliminate the influence of write interference on the storage state of the storage unit, when it is determined that the first storage unit is affected by write interference, the first storage unit and the storage unit adjacent to the first storage unit can be determined as the second storage unit to be subjected to data refresh, and the data stored in the plurality of second storage units is refreshed to eliminate the influence of read interference or write interference on the storage state of the storage unit, thereby ensuring the accuracy of the data stored in the storage unit.

[0079] In the embodiments of the present application, refreshing the data stored in the second storage unit is to perform error correction processing on the read results corresponding to the second storage unit, and then write the data after error correction processing into the second storage unit again. In this way, since the data written into the second storage unit again is the data after error correction processing, the accuracy of the data stored in the second storage unit can be ensured, and after the data is written into the second storage unit again, the threshold voltage of the second storage unit is refreshed to the threshold voltage before being affected by read interference, write interference, threshold voltage drift, and the like, thereby avoiding the problem that the read voltage cannot distinguish the storage state of the storage unit, and the accuracy of the data stored in the storage unit can be improved.

[0080] Figure 7 is a threshold voltage distribution diagram provided by an embodiment of the present application. As shown in Figure 7, after the plurality of second storage units are subjected to read disturbance or write disturbance, the threshold voltage distribution curve of the first storage unit storing "1" and the threshold voltage distribution curve of the second storage unit storing "0" can overlap, causing the read voltage (Vread) to be unable to distinguish the storage state of some second storage units. Continuing to refer to Figure 7, after the data stored in the second storage unit is refreshed, the threshold voltage of the second storage unit is refreshed, and the threshold voltage distribution curve of the first storage unit storing "1" and the threshold voltage distribution curve of the second storage unit storing "0" are both "narrowed", and the read voltage (Vread) can accurately distinguish the storage state of the second storage unit.

[0081] In an example, after determining that the failure rate of the plurality of first storage units is greater than the first threshold value, it can be determined whether the type of disturbance suffered by the plurality of first storage units is read disturbance or write disturbance. Then, according to the type of disturbance suffered by the first storage unit, the range of storage units for which data refresh is performed can be selected. The way to determine the type of disturbance suffered by the first storage unit is described below:

[0082] Read disturbance mainly disturbs the storage unit from a low resistance state to a high resistance state, that is, mainly disturbs the storage unit storing "1" to the storage unit storing "0". Write disturbance mainly disturbs the storage unit from a high resistance state to a low resistance state, that is, mainly disturbs the storage unit storing "0" to the storage unit storing "1". Therefore, in the embodiment of the present application, according to the number of failed storage units in a low resistance state and the number of failed storage units in a high resistance state in the plurality of storage units, it can be determined whether the storage unit is mainly affected by read disturbance or write disturbance.

[0083] In implementation, the storage controller can determine the number of failed first storage units in the plurality of first storage units by error correction algorithm, and can also determine the first number of first storage units that fail from storing "1" to storing "0" and the second number of first storage units that fail from storing "0" to storing "1" in the failed first storage units. The sum of the first number and the second number is the total number of failed storage units in the plurality of first storage units.

[0084] In an example, when the first quantity is greater than the second quantity, that is, the first proportion of the first storage cells that fail from storing "1" to storing "0" in the total failed first storage cells is greater than 50% (or the second proportion of the first storage cells that fail from storing "0" to storing "1" in the total failed first storage cells is less than 50%), it can be determined that the plurality of first storage cells corresponding to the first address are mainly affected by read disturbance. When the first quantity is less than the second quantity, that is, the second proportion of the first storage cells that fail from storing "0" to storing "1" in the total failed first storage cells is greater than 50% (or the first proportion of the first storage cells that fail from storing "1" to storing "0" in the total failed first storage cells is less than 50%), it can be determined that the plurality of first storage cells corresponding to the first address are mainly affected by write disturbance.

[0085] In another example, a threshold (third threshold) can be set for the first proportion or the second proportion, and according to the relationship between the first proportion or the second proportion and the set third threshold, it can be determined whether the storage cells are mainly affected by read disturbance or write disturbance. For example, when the first proportion is greater than the third threshold (or the second proportion is less than the third threshold), it can be determined that the plurality of first storage cells corresponding to the first address are mainly affected by read disturbance. When the first proportion is greater than the third threshold (or the second proportion is less than the third threshold), it can be determined that the plurality of first storage cells corresponding to the first address are mainly affected by write disturbance. The specific value of the third threshold can be set by the technician in advance. According to experimental data, when the third threshold is set to between one-half and four-fifths, the accuracy for read disturbance and write disturbance is the highest.

[0086] In the embodiments of the present application, when it is determined that the plurality of first storage cells are affected by read disturbance, the data stored in the determined first storage cells can be refreshed, thereby avoiding the influence of read disturbance on the storage cells. When it is determined that the plurality of first storage cells are affected by write disturbance, the plurality of first storage cells and the storage cells adjacent to the plurality of first storage cells can be determined as second storage cells, and the data stored in the determined second storage cells can be refreshed. In this way, the influence of write disturbance on the first storage cells and the storage cells around the first storage cells can be avoided.

[0087] In an example, when it is determined that the type of interference suffered by the plurality of first storage units is write interference, the second storage units to be subjected to data refresh can include, in addition to the first storage units, third storage units adjacent to the first storage units in the same word line and third storage units adjacent to the first storage units in the same bit line. As shown in FIG. 5, the first storage units are a, the third storage units adjacent to the first storage units in the same word line include storage units b, c, d, and e. In addition, the high temperature of the third storage units can also be transmitted to fourth storage units adjacent to the third storage units through the word line and the bit line, so that the fourth storage units are also affected by write interference. Therefore, in order to ensure the accuracy of the data stored by the storage units, data refresh can also be performed on the fourth storage units adjacent to the third storage units in the same bit line or the same word line. As shown in FIG. 5, the third storage units include storage units b, c, d, and e, and the corresponding fourth storage units include storage units f, g, h, i, j, k, l, and m. In implementation, the address correspondence between each first storage unit and the third storage unit and the fourth storage unit can be stored in advance, and after it is determined that the first storage unit is subjected to write interference, the data stored by the third storage unit and the fourth storage unit can be refreshed according to the address correspondence.

[0088] It should be noted that, in the embodiments of the present application, when it is determined that the type of interference suffered by the plurality of first storage units is read interference, it means that the reason for the failure of the plurality of first storage units is mainly affected by read interference, and the first storage units are not excluded from being affected by write interference. Similarly, when it is determined that the type of interference suffered by the plurality of first storage units is write interference, it means that the reason for the failure of the plurality of first storage units is mainly affected by write interference, and the first storage units are not excluded from being affected by read interference. However, whether the type of interference suffered by the plurality of first storage units is read interference or write interference, the second storage units subjected to data refresh include the first storage units, which can avoid read interference or write interference suffered by the first storage units, can solve the problem of high failure rate of the first storage units, and can improve the accuracy of data stored by the storage chip.

[0089] In an implementable manner, the read voltage applied in step 601 is a plurality of read voltages, and the plurality of read voltages are sequentially increased. In some embodiments, the read voltage applied to the first storage unit includes a plurality of read voltages, and the plurality of read voltages are sequentially increased. When the read operation needs to be performed on the plurality of first storage units, the lowest read voltage can be applied to the plurality of first storage units first. If the failure rate of the read result does not trigger the UCE of the storage chip, the read result is corrected by the error correction algorithm to obtain an accurate read result. If the failure rate of the read result triggers the UCE of the storage chip, the read voltage level can be increased, and the higher read voltage is applied to the plurality of first storage units to obtain a new read result. Then, it is judged again whether the failure rate corresponding to the read result triggers the UCE of the storage chip, and the same operation is performed until the corrected read result is obtained. If the plurality of read voltages applied to the first storage unit respectively trigger the UCE, the read fails. In this way, the influence of the threshold voltage drift on the threshold voltage of the storage unit can be solved by applying read voltages of different levels.

[0090] In the embodiments provided in the embodiments of the present application, a first threshold value smaller than the second threshold value triggering the UCE of the storage chip is set. After the read voltage is applied to the plurality of first storage units, if the failure rate of the read result is greater than the first threshold value, the higher read voltage can be applied to the plurality of first storage units again. If the read result corresponding to the plurality of read voltages applied has a failure rate smaller than the first threshold value, the read result can be corrected by the error correction algorithm to obtain a corrected read result. If the failure rate of the read result corresponding to the plurality of read voltages applied is greater than the first threshold value, it indicates that the plurality of first storage units are seriously affected by the read disturbance or the write disturbance, and the UCE of the storage chip can be triggered. Therefore, the data stored in the plurality of second storage units is refreshed in step 602 to ensure the accuracy of the data. In this way, the failure rate of the read result obtained by the plurality of read voltages is verified, the number of data refresh operations performed on the first storage unit is reduced, and the data refresh operation is performed on the storage unit affected by the read disturbance or the write disturbance before the read failure of the first storage unit (that is, the serious influence of the read disturbance or the write disturbance), so that the power consumption of the storage chip is reduced, and the accuracy of the data stored in the storage chip is improved.

[0091] In an example, in the examples of the present application, if it is needed to refresh the second storage unit after applying the read voltage of multiple gears, for the first storage unit included in the second storage unit, the target read data can be obtained by performing error correction processing on the target read data, and then the read data after error correction processing is written into the first storage unit to realize data refresh of the first storage unit. Wherein, the target read data is the read data corresponding to the lowest failure rate in the multiple groups of read data obtained by applying the read voltage of multiple gears to multiple first storage units. In this way, by performing error correction on the read data with the lowest failure rate, the accuracy of error correction on the read data can be reduced, and the accuracy of the data of the first storage unit after refresh can be ensured.

[0092] FIG. 8 is a flow chart of a control method of a storage chip provided by an embodiment of the present application. As shown in FIG. 8, the method comprises:

[0093] Step 801, start the read flow.

[0094] Apply the read voltage of the lowest gear to the multiple first storage units corresponding to the first address to obtain the read result.

[0095] Step 802, determine whether the FBC corresponding to the read result is greater than the set FBC threshold.

[0096] If it is determined that the FBC is greater than the set FBC threshold, step 803 is executed. If it is determined that the FBC is not greater than the set FBC threshold, the read result is normally error corrected and the read result after error correction is returned. Wherein, the set FBC threshold is less than the FBC threshold triggering the UCE of the storage chip.

[0097] Step 803, perform read retry using different gear read voltages to find the lowest FBC.

[0098] Step 804, determine whether the lowest FBC is greater than the set FBC threshold.

[0099] If it is determined that the FBC is greater than the set FBC threshold, step 805 is executed. If it is determined that the FBC is not greater than the set FBC threshold, the read result is normally error corrected and the read result after error correction is returned.

[0100] Step 805, determine whether the “0→1” failure ratio exceeds 50%.

[0101] If the proportion of the storage cells with "0→1" failure exceeds 50%, it indicates that the first storage cells are mainly affected by write disturb, and step 806 can be performed. If the proportion of the storage cells with "0→1" failure does not exceed 50%, it indicates that the storage cells are mainly affected by read disturb, and step 807 can be performed.

[0102] Step 806: performing refresh processing on the current storage cell and the storage cells adjacent to the current storage cell.

[0103] Step 807: performing refresh processing on the current storage cell.

[0104] In this way, in the embodiments of the present application, the read disturb and the write disturb affecting the storage cells can be distinguished, and different refresh processing can be performed for the read disturb and the write disturb, so that the stability of the storage data of the storage chip can be improved, and the power consumption of the refresh processing can be reduced.

[0105] FIG. 9 is a schematic diagram of an electronic device provided in an embodiment of the present application. The storage system includes a host, a storage controller, and a storage chip. The host, the storage controller, and the storage chip can be connected through an interface. The storage controller is provided with an algorithm module, which includes a Disturb solution module, an ECC module, and a Read retry module. The Disturb solution module, the ECC module, and the Read retry module can be used to implement the control method provided in the embodiments of the present application, so as to improve the stability of the storage data of the storage chip. In particular:

[0106] The ECC module can send the FBC corresponding to the read result of each of the plurality of first storage cells to the Disturb solution module.

[0107] After the Disturb solution module receives the FBC corresponding to the read result, it determines whether it is necessary to perform read retry (i.e., performing read operation on the first storage cell through a plurality of higher gear read voltages) on the plurality of first storage cells. If the Disturb solution module determines that read retry is necessary, it can send a read retry instruction to the Read retry module.

[0108] After the Read retry module receives the read retry instruction, it can perform read operation on the plurality of first storage cells through a plurality of higher gear read voltages in sequence, and send the read result obtained each time to the ECC module.

[0109] The ECC module can determine the FBC corresponding to the read result corresponding to the read voltage of the higher gear after receiving the read result corresponding to the read voltage of the higher gear, and send the corresponding FBC to the Disturb solution module.

[0110] The Disturb solution module can determine whether data refresh needs to be performed according to the FBC corresponding to the read result corresponding to the read voltage of the higher gear, and determine the disturb type in the case where data refresh needs to be performed.

[0111] In the case where the disturb type is read disturb, the Disturb solution module can obtain the error-corrected data corresponding to the plurality of first storage units from the ECC module, and write the error-corrected data into the plurality of first storage units to refresh the data of the first storage units, thereby solving the influence of read disturb on the storage units.

[0112] In the case where the disturb type is read disturb, the Disturb solution module can send the addresses of the third storage unit and the fourth storage unit that need to be read to the Read retry module. The Read retry module can read the read results of the third storage unit and the fourth storage unit according to the addresses of the third storage unit and the fourth storage unit, and provide the read results to the ECC module for error correction. The Disturb solution module can obtain the error-corrected data corresponding to the plurality of first storage units, the third storage unit and the fourth storage unit from the ECC module, and write the error-corrected data into the plurality of first storage units, the third storage unit and the fourth storage unit, thereby solving the influence of write disturb on the storage units.

[0113] In the embodiments of the present application, when it is determined that the storage units at the first address have a high failure rate, the main disturb suffered by the storage units can be distinguished according to the specific failure of the storage units. When the first number of storage units at the low resistance state that fail is greater than the second number of storage units at the high resistance state that fail, it indicates that the storage units at the first address are mainly affected by read disturb, and therefore the storage units at the first address can be written and refreshed to ensure the stability of the data stored in the storage units at the first address. When the second number of storage units at the high resistance state that fail is greater than the first number of storage units at the low resistance state that fail, it indicates that the storage units at the first address are mainly affected by write disturb, and therefore the storage units at the first address and the storage units around the storage units at the first address can be written and refreshed to ensure the stability of the data stored in the storage units at the first address and the storage units around the storage units at the first address. It can be seen that in the present application, the influence of read disturb and write disturb on the storage units can be distinguished, and different write refresh methods are provided for read disturb and write disturb respectively, which can improve the stability of the data stored in the storage chip.

[0114] Based on the same inventive concept, the embodiments of the present application further provide a storage controller, which is included in the storage system shown in Fig. 3. In the process of performing a read operation on the storage chip, the storage controller can implement the control method of the storage chip provided by the above embodiments to determine whether there is read interference or write interference according to the failure rate of the plurality of first storage units corresponding to the first address in the storage chip, and perform data refresh on the second storage units affected by the read interference or the write interference to eliminate the influence of the read interference or the write interference. The process in which the storage controller implements the control method of the storage chip can refer to the above method embodiments, and will not be described here.

[0115] Based on the same inventive concept, the embodiments of the present application further provide a storage system, which is the storage system shown in Fig. 3, and includes a storage controller and one or more storage chips. In the process of performing a read operation on the storage chip, the storage controller can implement the control method of the storage chip provided by the above embodiments to determine whether there is read interference or write interference according to the failure rate of the plurality of first storage units corresponding to the first address in the storage chip, and perform data refresh on the second storage units affected by the read interference or the write interference to eliminate the influence of the read interference or the write interference. The process in which the storage controller implements the control method of the storage chip can refer to the above method embodiments, and will not be described here.

[0116] In the present application, the terms "first", "second", and the like are used to distinguish between the same or similar items or elements having substantially the same function and should be understood not to have a logical or chronological dependency between them, nor to limit the number and execution order. It should also be understood that although the following description uses the terms first, second, and the like to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. In the present application, the term "at least one" means one or more, and the term "a plurality of" means two or more.

[0117] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any skilled person in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A control method for a memory chip, characterized in that, The method includes: Apply a read voltage to the multiple first memory cells corresponding to the first address; In response to the failure rate of the plurality of first storage cells being greater than a first threshold, the data stored in the plurality of second storage cells is refreshed, wherein the first threshold is less than a second threshold that triggers the uncorrectable error (UCE) of the storage chip, the plurality of second storage cells are storage cells affected by read interference or write interference, the plurality of second storage cells are the plurality of first storage cells, or the second storage cells are the plurality of first storage cells and the storage cells adjacent to the plurality of first storage cells.

2. The method according to claim 1, characterized in that, The step of refreshing the data stored in the plurality of second storage units in response to the failure rate of the plurality of first storage units being greater than a first threshold includes: In response to the failure rate of the plurality of first storage cells being greater than a first threshold, the interference type corresponding to the plurality of first storage cells is determined, wherein the interference type is read interference or write interference; If the interference type is determined to be read interference, the plurality of first storage units are determined to be a plurality of second storage units, and the data stored in the second storage units is refreshed; If the interference type is determined to be read interference, the plurality of first storage units and the storage units adjacent to the plurality of first storage units are determined to be second storage units, and the data stored in the second storage units is refreshed.

3. The method according to claim 2, characterized in that, Determining the interference type corresponding to the plurality of first storage units includes: Among the plurality of first memory cells, determine the percentage of the number of failed low-resistivity first memory cells in the total number of failed first memory cells; If the percentage is greater than the third threshold, the interference type is determined to be read interference; if the percentage is less than or equal to the third threshold, the interference type is determined to be write interference.

4. The method according to any one of claims 1 to 3, characterized in that, Applying a read voltage to the plurality of first memory cells corresponding to the first address includes: Multiple read voltage levels are applied to multiple first memory cells corresponding to the first address, and the multiple read voltage levels increase sequentially. The step of refreshing the data stored in the plurality of second storage units in response to the failure rate of the plurality of first storage units being greater than a first threshold includes: In response to the failure rate obtained by applying a read voltage of each level to the plurality of first storage cells being greater than the first threshold, the data stored in the plurality of second storage cells is refreshed.

5. The method according to claim 4, characterized in that, After applying multiple levels of read voltage to the multiple first memory cells corresponding to the first address, the method further includes: Error correction processing is performed on the target read data to obtain the error-corrected read data. The target read data is the set of read data with the lowest failure rate among multiple sets of read data obtained by applying multiple levels of read voltage. The step of refreshing the data stored in the plurality of second storage units includes: The read data after error correction is written into the first storage unit included in the plurality of second storage units.

6. The method according to claim 2, characterized in that, The memory cells adjacent to the plurality of first memory cells include a third memory cell that is on the same bit line or word line and adjacent to the plurality of first memory cells. The method further includes: The fourth storage cell, which is on the same bit line or word line and adjacent to the third storage cell, is identified as the second storage cell.

7. The method according to claim 3, characterized in that, The third threshold is between one-half and four-fifths.

8. The method according to any one of claims 1 to 7, characterized in that, The first storage unit is a phase-change storage unit.

9. A storage controller, characterized in that, The storage controller is connected to the storage chip, and the storage controller is used for: A read voltage is applied to the plurality of first memory cells corresponding to the first address in the memory chip; In response to the failure rate of the plurality of first storage cells being greater than a first threshold, the data stored in the plurality of second storage cells is refreshed, wherein the first threshold is less than a second threshold that triggers the uncorrectable error (UCE) of the storage chip, the plurality of second storage cells are storage cells affected by read interference or write interference, the plurality of second storage cells are the plurality of first storage cells, or the second storage cells are the plurality of first storage cells and the storage cells adjacent to the plurality of first storage cells.

10. The storage controller according to claim 9, characterized in that, The storage controller is used for: In response to the failure rate of the plurality of first storage cells being greater than a first threshold, the interference type corresponding to the plurality of first storage cells is determined, wherein the interference type is read interference or write interference; If the interference type is determined to be read interference, the plurality of first storage units are determined to be a plurality of second storage units, and the data stored in the second storage units is refreshed; If the interference type is determined to be read interference, the plurality of first storage units and the storage units adjacent to the plurality of first storage units are determined to be second storage units, and the data stored in the second storage units is refreshed.

11. The storage controller according to claim 10, characterized in that, The storage controller is used for: Among the plurality of first memory cells, determine the percentage of the number of failed low-resistivity first memory cells in the total number of failed first memory cells; If the percentage is greater than the third threshold, the interference type is determined to be read interference; if the percentage is less than or equal to the third threshold, the interference type is determined to be write interference.

12. The storage controller according to any one of claims 9 to 11, characterized in that, The storage controller is used for: Multiple read voltage levels are applied to multiple first memory cells corresponding to the first address, and the multiple read voltage levels increase sequentially. In response to the failure rate obtained by applying a read voltage of each level to the plurality of first storage cells being greater than the first threshold, the data stored in the plurality of second storage cells is refreshed.

13. The storage controller according to claim 12, characterized in that, The storage controller is further configured to: Error correction processing is performed on the target read data to obtain the error-corrected read data. The target read data is the set of read data with the lowest failure rate among multiple sets of read data obtained by applying multiple levels of read voltage. The read data after error correction is written into the first storage unit included in the plurality of second storage units.

14. The storage controller according to claim 10, characterized in that, The memory cells adjacent to the plurality of first memory cells include a third memory cell that is on the same bit line or word line and adjacent to the plurality of first memory cells. The memory controller is further configured to: The fourth storage cell, which is on the same bit line or word line and adjacent to the third storage cell, is identified as the second storage cell.

15. The storage controller according to claim 11, characterized in that, The third threshold is between one-half and four-fifths.

16. The storage controller according to any one of claims 9 to 15, characterized in that, The first storage unit is a phase-change storage unit.

17. A storage system, characterized in that, The storage system includes a storage controller as described in any one of claims 9 to 16, and at least one storage chip connected to the storage controller.

18. An electronic device, characterized in that, The electronic device includes a processor and the storage system as described in claim 17; The processor is used to send read and write instructions to the storage system so that the storage system can perform read and write operations.

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