Array substrate, manufacturing method and display device

Abstract

Provided in the embodiments of the present disclosure are an array substrate, a manufacturing method and a display device. The array substrate comprises a base substrate and a pixel circuit located on the base substrate. The pixel circuit comprises a plurality of switching transistors and at least one driving transistor, wherein an active layer of at least one of the plurality of switching transistors further comprises a lightly-doped region, and the lightly-doped region is located between a channel region and at least one of a source region and a drain region. Each switching transistor comprises a first transistor, wherein lightly-doped regions of the first transistor are located between the source region and the channel region and between the drain region and the channel region; and a gate electrode of the first transistor is coupled to a reset signal terminal, a first electrode of the first transistor is coupled to a gate electrode of the driving transistor, and a second electrode of the first transistor is coupled to an initialization signal terminal. A leakage current in the pixel circuit can be reduced while improving the current output capability of the pixel circuit, thereby reducing the power consumption of the display device, improving the performance of the pixel circuit, and improving the display effects.

Description

Array substrate, manufacturing method and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410823959.9, filed on June 25, 2024, entitled "Array Substrate, Manufacturing Method and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to array substrates, manufacturing methods, and display devices. Background Technology

[0004] Organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) are currently a hot research topic in the field of array substrate applications due to their advantages such as self-illumination and low energy consumption. Pixel circuits are generally used to drive the light-emitting devices. The thin-film transistors (TFTs) in the pixel circuits typically include amorphous silicon (α-Si, a-Si) transistors, low-temperature polycrystalline silicon (LTPS) transistors, and oxide thin-film transistors.

[0005] Low-temperature polysilicon (LTPS) transistors are widely used due to their high mobility and good stability. However, with the improvement of display product performance and the increase in integration, the demand for mobility is increasing. The mobility of the array substrate formed by combining LPS transistors is limited by the materials, and higher mobility cannot be achieved. Furthermore, the large leakage current leads to higher power consumption in the display device. Summary of the Invention

[0006] The array substrate provided in this embodiment includes: a substrate and pixel circuits located on the substrate;

[0007] The pixel circuit includes: a plurality of switching transistors and at least one driving transistor; the active layer of each switching transistor includes a source region, a drain region and a channel region located between the source region and the drain region, wherein the source region and the drain region are both heavily doped regions;

[0008] The active layer of at least one of the plurality of switching transistors further includes a lightly doped region, the lightly doped region being located between at least one of the source region and the drain region and the channel region;

[0009] The switching transistor includes: a first transistor; a lightly doped region of the first transistor located between the source region and the channel region and between the drain region and the channel region; the gate of the first transistor is coupled to a reset signal terminal, the first electrode of the first transistor is coupled to the gate of the driving transistor, and the second electrode of the first transistor is coupled to an initialization signal terminal.

[0010] In some embodiments of this disclosure, the switching transistor further includes: a second transistor; the lightly doped region of the second transistor is located between the source region and the channel region and between the drain region and the channel region;

[0011] The gate of the second transistor is coupled to the first scan signal terminal, the first terminal of the second transistor is coupled to the gate of the driving transistor, and the second terminal of the second transistor is coupled to the drain of the driving transistor.

[0012] In some embodiments of this disclosure, the switching transistor further includes: a third transistor; the lightly doped region of the third transistor is located between the source region and the channel region or between the drain region and the channel region;

[0013] The gate of the third transistor is coupled to the second scan signal terminal, the first terminal of the third transistor is coupled to the source of the driving transistor, and the second terminal of the third transistor is coupled to the data signal terminal.

[0014] In some embodiments of this disclosure, the pixel circuit further includes: a light-emitting device; the switching transistor further includes: a fourth transistor; the lightly doped region of the fourth transistor is located between the source region and the channel region or between the drain region and the channel region;

[0015] The gate of the fourth transistor is coupled to the third scan signal terminal, the first terminal of the fourth transistor is coupled to the light-emitting device, and the second terminal of the fourth transistor is coupled to the initialization signal terminal.

[0016] In some embodiments of this disclosure, the pixel circuit further includes: a first light-emitting transistor and a second light-emitting transistor;

[0017] The gate of the first light-emitting transistor is coupled to the first light-emitting control signal terminal, the first electrode of the first light-emitting transistor is coupled to the first power supply terminal, and the second electrode of the first light-emitting transistor is coupled to the source of the driving transistor.

[0018] The gate of the second light-emitting transistor is coupled to the second light-emitting control signal terminal, the first terminal of the second light-emitting transistor is coupled to the drain of the driving transistor, and the second terminal of the second light-emitting transistor is coupled to the light-emitting device.

[0019] In some embodiments of this disclosure, the spacing between the source region and the channel region is 0.1 μm to 1.5 μm, and the spacing between the drain region and the channel region is 0.1 μm to 1.5 μm.

[0020] In some embodiments of this disclosure, the gate of the driving transistor includes a first gate and a second gate, wherein the first gate and the second gate are located in different film layers;

[0021] The source of the driving transistor is electrically connected to the first gate of the driving transistor.

[0022] In some embodiments of this disclosure, the driving transistor further includes an active layer; the first gate of the driving transistor, the active layer of the driving transistor, and the second gate of the driving transistor are sequentially stacked.

[0023] The active layer of the driving transistor includes a source region, a drain region, and a channel region located between the source region and the drain region. The source region of the driving transistor is electrically connected to the first gate of the driving transistor through a first via. The first via penetrates the insulating layer between the active layer of the driving transistor and the first gate.

[0024] Alternatively, the source of the driving transistor is electrically connected to the first gate of the driving transistor through a second via; the orthographic projection of the second via on the substrate does not overlap with the active layer of the driving transistor; the second via penetrates the insulating layer between the source and the first gate of the driving transistor.

[0025] Alternatively, the source of the driving transistor is electrically connected to the first gate via a transition structure, and the transition structure and the second gate are located on the same layer.

[0026] The array substrate, fabrication method, and display device provided in this disclosure include: a substrate and a pixel circuit located on the substrate; the pixel circuit includes a plurality of switching transistors, each switching transistor having an active layer including a source region, a drain region, and a channel region located between the source region and the drain region, both the source region and the drain region being heavily doped regions; at least one of the multiple switching transistors also includes a lightly doped region in its active layer, the lightly doped region being located between at least one of the source and drain regions and the channel region. This improves the output current capability of the pixel circuit while reducing leakage current in the pixel circuit, thereby reducing the power consumption of the display device and improving the performance of the pixel circuit, thus enhancing the display effect.

[0027] The display device provided in this disclosure includes the array substrate described above.

[0028] The method for fabricating an array substrate provided in this disclosure includes: forming a plurality of switching transistors in a pixel circuit on a substrate.

[0029] The active layer forming at least one of the plurality of switching transistors includes:

[0030] Ion implantation is performed on the active layer, and the concentration of implanted ions is greater than or equal to a first set concentration to form heavily doped regions on both sides of the channel region.

[0031] Ion implantation is performed on at least one region between the channel region and the heavily doped region of the active layer, and the concentration of the implanted ions is less than or equal to a second set concentration to form a lightly doped region, wherein the second set concentration is less than the first set concentration.

[0032] In some embodiments of this disclosure, the step of ion implantation into the active layer, wherein the concentration of the implanted ions is greater than or equal to a first predetermined concentration, to form heavily doped regions on both sides of the channel region, includes:

[0033] A semiconductor layer is deposited on the substrate and the semiconductor layer is patterned to form an initial active layer;

[0034] A gate insulating layer is deposited on the initial active layer;

[0035] A second conductive layer is deposited on the gate insulating layer;

[0036] A photoresist layer is deposited on the second conductive layer and the photoresist layer is patterned such that the orthographic projection of the remaining photoresist on the substrate covers the orthographic projection of the first region of the initial active layer on the substrate, and the orthographic projection of the remaining photoresist on the substrate does not overlap with the orthographic projection of the second region of the initial active layer on the substrate, wherein the second region is located on both sides of the first region.

[0037] Ion implantation is performed on the second region, and the concentration of implanted ions is greater than or equal to a first set concentration to form a heavily doped region;

[0038] The step of ion implantation into at least one region between the channel region and the heavily doped region of the active layer, wherein the concentration of the implanted ions is less than or equal to a second predetermined concentration, to form a lightly doped region, includes:

[0039] The remaining photoresist is patterned again using an ashing and etching process, so that the orthographic projection of the remaining photoresist on the substrate after repatterning covers the third region of the initial active layer, and the orthographic projection of the remaining photoresist on the substrate after repatterning does not overlap with the orthographic projection of the fourth region of the initial active layer on the substrate. The first region includes the third region and the fourth region, and the fourth region is located between the third region and the second region.

[0040] Ion implantation is performed on the second region, and the concentration of implanted ions is less than or equal to a second set concentration to form a lightly doped region, wherein the second set concentration is less than the first set concentration. Attached Figure Description

[0041] Figure 1 shows some simulation curves provided in the embodiments of this disclosure;

[0042] Figure 2 shows some other simulation curves provided in the embodiments of this disclosure;

[0043] Figure 3 is a schematic diagram of some structures of the array substrate provided in the embodiments of this disclosure;

[0044] Figure 4 is a schematic diagram of some structures of the pixel circuit provided in the embodiments of this disclosure;

[0045] Figure 5 shows some more simulation curves provided in the embodiments of this disclosure;

[0046] Figure 6 shows some more simulation curves provided in the embodiments of this disclosure;

[0047] Figure 7 shows some more simulation curves provided in the embodiments of this disclosure;

[0048] Figure 8 shows some more simulation curves provided in the embodiments of this disclosure;

[0049] Figure 9 is a schematic diagram of some other structures of the array substrate provided in the embodiments of this disclosure;

[0050] Figure 10 is a schematic diagram of some of the structures of the array substrate provided in the embodiments of this disclosure;

[0051] Figure 11 is a schematic diagram of some of the structures of the array substrate provided in the embodiments of this disclosure;

[0052] Figure 12 is a schematic diagram of some more structures of the array substrate provided in the embodiments of this disclosure;

[0053] Figure 13 is a schematic diagram of some structures of the pixel circuit provided in the embodiments of this disclosure;

[0054] Figure 14 is a schematic diagram of some more structures of the array substrate provided in the embodiments of this disclosure;

[0055] Figure 15 is a schematic diagram of some more structures of the array substrate provided in the embodiments of this disclosure;

[0056] Figure 16 is a schematic diagram of some more structures of the array substrate provided in the embodiments of this disclosure;

[0057] Figure 17 is a schematic diagram of some more structures of the array substrate provided in the embodiments of this disclosure;

[0058] Figure 18 is a schematic diagram of some of the structures of the array substrate provided in the embodiments of this disclosure. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0060] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0061] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0062] Organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), micro light-emitting diodes (Micro LEDs), and mini light-emitting diodes (Mini LEDs) are currently a hot research topic in the field of array substrate applications due to their advantages such as self-illumination and low energy consumption. Pixel circuits are generally used to drive the light-emitting devices. The thin-film transistors (TFTs) in the pixel circuits typically include amorphous silicon (α-Si, a-Si) transistors, low-temperature polycrystalline silicon (LTPS) transistors, and oxide thin-film transistors.

[0063] Low-temperature polysilicon (LTPS) transistors are widely used due to their high mobility and good stability. However, with the improvement of display product performance and the increase in integration, the demand for mobility is increasing. The mobility of pixel circuits formed by combining LPS transistors is limited by the materials, and higher mobility cannot be achieved. Furthermore, the large leakage current leads to higher power consumption in display devices.

[0064] It should be noted that existing transistors are generally classified into two types: P-type transistors and N-type transistors. Since N-type transistors have electron-conducting channels while P-type transistors have hole-conducting channels, N-type transistors have higher mobility than P-type transistors, resulting in better device performance. During the operation of an N-type transistor, the applied voltage to the drain region causes the charge carriers in the channel region to be accelerated by a strong electric field and bombard the crystal lattice, generating electron-hole pairs in the active layer. These generated electron-hole pairs are collected along with the original charge carriers, thus giving the N-type transistor a larger forward output current and a larger leakage current.

[0065] For example, Figures 1 and 2 are simulation curves of N-type and P-type transistors, where the horizontal axis represents the gate voltage and the vertical axis represents the output current. It should be noted that the N-type transistor simulation curve is mirrored for easier observation. The drain voltage in Figure 1 is 5.1V; the drain voltage in Figure 2 is 10.1V. It can be seen that when the gate voltage is the same, the output current of the N-type transistor is greater than that of the P-type transistor, meaning the mobility of the N-type transistor is much greater than that of the P-type transistor. When the gate voltage exceeds 0V, the change in the output current is significant, resulting in a tailing phenomenon in the simulation curve. This tailing phenomenon affects the stability of the transistor.

[0066] To improve the mobility of pixel circuits, it's necessary to use N-type transistors as much as possible to maximize the mobility, which in turn increases the output current. However, while increasing mobility, the leakage current of the pixel circuit also increases, leading to higher power consumption. Therefore, improving the mobility of pixel circuits requires addressing the leakage current issue.

[0067] Based on the above problems, this disclosure provides an array substrate, as shown in FIG3 and FIG4, including: a substrate 100 and a pixel circuit 200 located on the substrate 100;

[0068] The pixel circuit 200 includes a plurality of switching transistors 1 and at least one driving transistor M0. The active layer of each switching transistor 1 includes a source region 101, a drain region 102 and a channel region 103 located between the source region 101 and the drain region 102. Both the source region 101 and the drain region 102 are heavily doped regions.

[0069] The active layer of at least one of the multiple switching transistors 1 further includes a lightly doped region LD1, which is located between at least one of the source region 101 and the drain region 102 and the channel region 103.

[0070] The switching transistor 1 includes a first transistor M1; the lightly doped region LD1 of the first transistor M1 is located between the source region 101 and the channel region 103 and between the drain region 102 and the channel region 103; the gate of the first transistor M1 is coupled to the reset signal terminal RE, the first terminal of the first transistor M1 is coupled to the gate of the driving transistor M0, and the second terminal of the first transistor M1 is coupled to the initialization signal terminal Vint.

[0071] For example, the structure of the first transistor M1 is shown in the switching transistor 1_1 in Figure 3. This configuration can minimize the leakage of the first transistor M1, thereby avoiding leakage current when the pixel circuit is working and reducing power consumption.

[0072] For example, the first transistor M1 can be turned on under the control of the effective level of the reset signal transmitted on the reset signal terminal RE, and can be turned off under the control of the ineffective level of the reset signal. If the first transistor M1 is set as an N-type transistor, then the effective level of the reset signal is a high level, and the ineffective level of the reset signal is a low level.

[0073] This embodiment of the disclosure further includes a lightly doped region in the active layer of at least one of the multiple switching transistors in the pixel circuit. The lightly doped region is located between at least one of the source region and the drain region and the channel region. That is, according to the needs of the pixel circuit in different application scenarios, some switching transistors can be lightly doped, that is, the light doping of the first transistor in the pixel circuit is set between the drain region and the channel region, thereby avoiding leakage current of the first transistor, thereby avoiding leakage current when the pixel circuit is working, reducing power consumption, and thus reducing the power consumption of the display device.

[0074] In this embodiment, the active layer material of the switching transistor is low-temperature polycrystalline silicon, and the switching transistor can be configured as an N-type transistor. This configuration can further improve the pixel circuit mobility, i.e., improve the output capability of the pixel circuit and enhance the display effect. Simultaneously, the increased mobility is equivalent to reducing the equivalent resistance in the pixel circuit, which is explained by the power consumption formula W = I... 2 As can be seen from R, when the resistance decreases, the power consumption also decreases, which can further reduce the power consumption of the pixel circuit.

[0075] For example, Figures 5 to 8 are simulation curves obtained when the width-to-length ratio of the channel of the N-type transistor is the same as that of the P-type transistor, and the N-type transistor has a lightly doped region while the P-type transistor does not. Figures 5 and 6 are simulation curves of the P-type transistor, and Figures 7 and 8 are simulation curves of the N-type transistor. The horizontal axis represents the gate voltage of the transistor, and the vertical axis represents the output current. The drain voltage of the P-type transistor in Figure 5 is -0.1V; the drain voltage of the P-type transistor in Figure 6 is -10.1V. The drain voltage of the N-type transistor in Figure 7 is 0.1V; the drain voltage of the N-type transistor in Figure 8 is 10.1V. As shown in Figures 5 and 7, the output current of the N-type transistor with a lightly doped region is still greater than that of the P-type transistor without a lightly doped region. As shown in Figures 6 and 8, the tailing phenomenon in the simulation curve of the N-type transistor with a lightly doped region is improved, while the tailing phenomenon in the simulation curve of the P-type transistor without a lightly doped region still exists. Therefore, the stability of the N-type transistor with a lightly doped region is improved, meaning that the N-type transistor with a lightly doped region is less prone to leakage. The lightly doped region can effectively suppress the lattice collisions caused by the acceleration of charge carriers in the channel due to the drain of the transistor, thus generating additional electron-hole pairs, effectively suppressing transistor leakage and reducing power consumption.

[0076] In this embodiment of the present disclosure, as shown in FIG4, the switching transistor 1 further includes, by way of example, a second transistor M2; the lightly doped region LD1 of the second transistor M2 is located between the source region 101 and the channel region 103 and between the drain region 102 and the channel region 103; wherein, the gate of the second transistor M2 is coupled to the first scan signal terminal SS1, the first terminal of the second transistor M2 is coupled to the gate of the driving transistor M0, and the second terminal of the second transistor M2 is coupled to the drain of the driving transistor M0.

[0077] For example, the structure of the second transistor M2 is shown in the switching transistor 1_1 in Figure 3. This configuration can minimize the leakage of the second transistor M2, thereby avoiding leakage current when the pixel circuit is working and reducing power consumption.

[0078] For example, the second transistor M2 can be turned on under the control of the effective level of the first scan signal transmitted on the first scan signal terminal SS1, and can be turned off under the control of the ineffective level of the first scan signal. If the second transistor M2 is set as an N-type transistor, then the effective level of the first scan signal is a high level, and the ineffective level of the first scan signal is a low level.

[0079] In this embodiment of the present disclosure, as shown in FIG4, the switching transistor 1 further includes: a third transistor M3; the lightly doped region LD1 of the third transistor M3 is located between the source region 101 and the channel region 103 or between the drain region 102 and the channel region 103; wherein, the gate of the third transistor M3 is coupled to the second scan signal terminal SS2, the first terminal of the third transistor M3 is coupled to the source of the driving transistor M0, and the second terminal of the third transistor M3 is coupled to the data signal terminal DA.

[0080] For example, the structure of the third transistor M3 is shown in the switching transistor 1_2 or 1_3 in Figure 3. This configuration ensures the output capability of the third transistor M3 while minimizing leakage current, thereby preventing leakage current from the pixel circuit during operation and ensuring the output capability of the pixel circuit, i.e., reducing power consumption while ensuring performance.

[0081] For example, the third transistor M3 can be turned on under the control of the effective level of the second scan signal transmitted on the second scan signal terminal SS2, and can be turned off under the control of the ineffective level of the second scan signal. If the third transistor M3 is set as an N-type transistor, then the effective level of the second scan signal is a high level, and the ineffective level of the second scan signal is a low level.

[0082] In this embodiment, the third transistor M3 can also be configured to have a structure without a lightly doped region. The structure of the third transistor M3 is shown in FIG9. The active layer of the third transistor M3 includes a source region 101, a drain region 102, and a channel region 103 located between the source region 101 and the drain region 102. This configuration can improve the output capability of the pixel circuit, that is, improve the performance of the pixel circuit and improve the display effect.

[0083] In this embodiment of the present disclosure, as shown in FIG4, the pixel circuit 200 further includes: a light-emitting device L; the switching transistor 1 further includes: a fourth transistor M4; the lightly doped region LD1 of the fourth transistor M4 is located between the source region 101 and the channel region 103 or between the drain region 102 and the channel region 103; wherein, the gate of the fourth transistor M4 is coupled to the third scan signal terminal SS3, the first terminal of the fourth transistor M4 is coupled to the light-emitting device L, and the second terminal of the fourth transistor M4 is coupled to the initialization signal terminal Vint.

[0084] For example, the structure of the fourth transistor M4 is shown in the switching transistor 1_2 or 1_3 in Figure 3. This configuration ensures the output capability of the fourth transistor M4 while minimizing leakage current, thereby preventing leakage current from the pixel circuit during operation and ensuring the output capability of the pixel circuit, i.e., reducing power consumption while ensuring performance.

[0085] For example, the fourth transistor M4 can be turned on under the control of the effective level of the third scan signal transmitted on the third scan signal terminal SS3, and can be turned off under the control of the ineffective level of the third scan signal. If the fourth transistor M4 is set as an N-type transistor, then the effective level of the third scan signal is a high level, and the ineffective level of the third scan signal is a low level.

[0086] In this embodiment of the disclosure, as shown in FIG4, the anode of the light-emitting device L is coupled to the first terminal of the fourth transistor M4, and the cathode of the light-emitting device L is coupled to the second power supply terminal VSS. Exemplarily, the light-emitting device L can be an electroluminescent diode. For example, the light-emitting device L may include at least one of the following: Organic Light Emitting Diode (OLED), Quantum Dot Light Emitting Diodes (QLED), Micro Light Emitting Diode (Micro LED), and Mini Light Emitting Diode (Mini LED). Exemplarily, the light-emitting device L may include an anode, a light-emitting layer, and a cathode stacked together. Further, the light-emitting layer may also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Of course, in practical applications, the specific structure of the light-emitting device L can be determined according to the needs of the actual application, and is not limited here. Furthermore, the light-emitting device L generally emits light under the action of the output current when the driving transistor M0 is in saturation.

[0087] In this embodiment, the fourth transistor M4 can also be configured to have a structure without a lightly doped region. The structure of the fourth transistor M4 is shown in FIG9. The active layer of the fourth transistor M4 includes a source region 101, a drain region 102, and a channel region 103 located between the source region 101 and the drain region 102. This configuration can improve the output capability of the pixel circuit, that is, improve the performance of the pixel circuit and improve the display effect.

[0088] In this embodiment, the first scan signal terminal SS1, the second scan signal terminal SS2, and the third scan signal terminal SS3 can be loaded with the same signal, that is, the first scan signal terminal SS1, the second scan signal terminal SS2, and the third scan signal terminal SS3 are the same signal terminal. This arrangement can simplify the circuit and facilitate wiring.

[0089] In this embodiment of the present disclosure, as shown in FIG4, the pixel circuit 200 further includes: a first light-emitting transistor M5 and a second light-emitting transistor M6; wherein, the gate of the first light-emitting transistor M5 is coupled to a first light-emitting control signal terminal EM1, the first electrode of the first light-emitting transistor M5 is coupled to a first power supply terminal VDD, and the second electrode of the first light-emitting transistor M5 is coupled to the source of the driving transistor M0; the gate of the second light-emitting transistor M6 is coupled to a second light-emitting control signal terminal EM2, the first electrode of the second light-emitting transistor M6 is coupled to the drain of the driving transistor M0, and the second electrode of the second light-emitting transistor M6 is coupled to the light-emitting device L.

[0090] In this design, both the first light-emitting transistor M5 and the second light-emitting transistor M6 are configured without lightly doped regions. The structures of the first light-emitting transistor M5 and the second light-emitting transistor M6 are shown in Figure 9. The active layers of the first light-emitting transistor M5 and the second light-emitting transistor M6 include a source region 101, a drain region 102, and a channel region 103 located between the source region 101 and the drain region 102. Both the source region 101 and the drain region 102 are heavily doped regions. Furthermore, both the first light-emitting transistor M5 and the second light-emitting transistor M6 are configured as N-type transistors. This configuration maximizes the output capability of the pixel circuit, i.e., increases the output current, thereby shortening the charging time of the pixel circuit and enabling high-frequency display.

[0091] For example, the first light-emitting transistor M5 can be turned on under the control of the effective level of the first light-emitting control signal transmitted on the first light-emitting control signal terminal EM1, and can be turned off under the control of the ineffective level of the first light-emitting control signal. If the first light-emitting transistor M5 is set as an N-type transistor, then the effective level of the first light-emitting control signal is a high level, and the ineffective level of the first light-emitting control signal is a low level.

[0092] For example, the second light-emitting transistor M6 can be turned on under the control of the effective level of the second light-emitting control signal transmitted on the second light-emitting control signal terminal EM2, and can be turned off under the control of the ineffective level of the second light-emitting control signal. If the second light-emitting transistor M6 is set as an N-type transistor, then the effective level of the second light-emitting control signal is a high level, and the ineffective level of the second light-emitting control signal is a low level.

[0093] In this embodiment of the present disclosure, the first light-emitting control signal terminal EM1 and the second light-emitting transistor M6 can be loaded with the same signal, that is, the first light-emitting control signal terminal EM1 and the second light-emitting transistor M6 are the same signal terminal. This arrangement can simplify the circuit and facilitate wiring.

[0094] For example, the first electrode of the transistor described above can be its source, and the second electrode can be its drain. Alternatively, the first electrode can be its drain, and the second electrode can be its source. No limitation is made here.

[0095] In this embodiment, the spacing between the source region and the channel region is 0.1 μm to 1.5 μm, and the spacing between the drain region and the channel region is 0.1 μm to 1.5 μm. This arrangement ensures that while lightly doped regions prevent leakage current in the switching transistor, the output capability of the switching transistor is not excessively affected.

[0096] In this embodiment of the present disclosure, as shown in FIG10, the gate of the driving transistor M0 includes a first gate G1 and a second gate G2, wherein the first gate G1 and the second gate G2 are located in different film layers; the source S0 of the driving transistor M0 is coupled to the first gate G1 of the driving transistor M0. This configuration can improve the stability of the output current of the driving transistor, thereby improving the stability of the pixel circuit and thus improving the display effect.

[0097] By electrically connecting the source of the driving transistor to the first gate of the driving transistor, the floating body effect and drain-induced barrier lowering eflection (DIBL) can be effectively suppressed. This avoids excessive changes in the output current of the driving transistor when different voltages are applied to the gate, and the tailing phenomenon in the simulation curve of the driving transistor can be strictly controlled; that is, the output current of the driving transistor is kept stable.

[0098] It should be noted that the floating body effect occurs when a transistor made by placing silicon on an insulator creates a capacitor relative to the insulator substrate. Charge accumulates on this capacitor, causing various adverse effects. The drain-induced barrier lowering effect (DIBL) refers to the reduction in the threshold voltage caused by the voltage at the transistor's drain.

[0099] In this embodiment of the present disclosure, as shown in FIG10, the driving transistor M0 further includes an active layer; the first gate G1 of the driving transistor M0, the active layer of the driving transistor M0, and the second gate G2 of the driving transistor M0 are stacked sequentially.

[0100] The active layer of the driving transistor M0 includes a source region 101, a drain region 102, and a channel region 103 located between the source region 101 and the drain region 102. The source region 101 of the driving transistor M0 is coupled to the first gate G1 of the driving transistor M0 through a first via K1. The first via K1 penetrates the insulating layer between the active layer of the driving transistor M0 and the first gate G1.

[0101] For example, as shown in Figures 3, 9, and 10, the pixel circuit further includes: a first conductive layer 20 on the substrate 100; a planarization layer 30 on the side of the first conductive layer 20 facing away from the substrate 100; a semiconductor layer 10 on the side of the planarization layer 30 facing away from the substrate 100; a gate insulating layer 40 on the side of the semiconductor layer 10 facing away from the substrate 100; a second conductive layer 50 on the side of the gate insulating layer 40 facing away from the substrate 100; an interlayer insulating layer 60 on the side of the second conductive layer 50 facing away from the substrate 100; and a third conductive layer 7 on the side of the interlayer insulating layer 60 facing away from the substrate 100. 0; wherein, the first conductive layer 20 includes: the first gate G1 of the driving transistor M0; the semiconductor layer 10 includes: the active layer of the driving transistor M0, the active layer of the switching transistor 1, the active layer of the first light-emitting transistor M5, and the active layer of the second light-emitting transistor M6; the second conductive layer 50 includes: the second gate G2 of the driving transistor M0, the gate of the switching transistor 1, the gate of the first light-emitting transistor M5, and the gate of the second light-emitting transistor M6; the third conductive layer 70 includes: the source and drain of the driving transistor M0, the source and drain of the switching transistor 1, the source and drain of the first light-emitting transistor M5, and the source and drain of the second light-emitting transistor M6.

[0102] For example, as shown in FIG10, the first via K1 penetrates the insulating layer between the active layer of the driving transistor M0 and the first gate G1, which is the planarization layer 30.

[0103] In this embodiment of the disclosure, the driving transistor M0 can be set as a P-type transistor. This setting can further ensure the stability of the pixel circuit and avoid leakage.

[0104] In this embodiment of the present disclosure, as shown in FIG10, the source S0 of the driving transistor M0 is coupled to the first gate G1 of the driving transistor M0 through the second via K2; the orthographic projection of the second via K2 on the substrate 100 does not overlap with the active layer of the driving transistor M0; the second via K2 penetrates the insulating layer between the source S0 and the first gate G1 of the driving transistor M0.

[0105] For example, as shown in FIG10, the second via K2 passes through the insulating layer between the source S0 and the first gate G1 of the driving transistor M0, which is a planarization layer 30, a gate insulating layer 40, and an interlayer insulating layer 60.

[0106] In this embodiment of the disclosure, as shown in FIG10, the source S0 of the driving transistor M0 is electrically connected to the first gate G1 through the transition structure Z1, and the transition structure Z1 and the second gate G2 are located on the same layer.

[0107] For example, as shown in FIG4, the pixel circuit 200 further includes: a first capacitor C1; wherein, the first electrode of the first capacitor C1 is coupled to the first power supply terminal VDD, and the second electrode of the first capacitor C1 is electrically connected to the first gate of the first driving transistor M0.

[0108] In summary, the pixel circuit in this embodiment improves stability by electrically connecting the source of the driving transistor to its first gate. By positioning the lightly doped regions of the first and second transistors between the source and channel regions and between the drain and channel regions, leakage current is effectively suppressed, preventing leakage during subsequent compensation of the driving transistor's threshold voltage and reducing power consumption. Furthermore, by setting the first and second light-emitting transistors to have no lightly doped regions, the output capability of the pixel circuit is significantly improved, thereby enhancing charging capability and facilitating higher display frequencies. Additionally, by positioning the lightly doped regions of the third and fourth transistors between the source and channel regions or between the drain and channel regions as needed, leakage current during pixel circuit operation is further avoided while simultaneously ensuring the pixel circuit's output capability, thus improving display performance.

[0109] In this embodiment of the disclosure, as shown in FIG11, the driving transistor M0 can adopt a dual-gate structure, and the first gate G1 of the driving transistor M0 is electrically connected to the second gate G2 of the driving transistor M0. This configuration can increase the output current of the driving transistor.

[0110] In this embodiment of the present disclosure, as shown in FIG12, the orthographic projection of the first gate G1 of the driving transistor M0 on the substrate 100 overlaps with the orthographic projection of the second gate G2 of the driving transistor M0 on the substrate 100. The second gate G2 of the driving transistor M0 is in a floating state. This setting of the second gate can have a light-shielding effect and improve the display effect.

[0111] This disclosure provides other schematic diagrams of pixel circuits, as shown in FIG13, which are modifications of the embodiments described above. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0112] In this embodiment of the present disclosure, as shown in FIG13, the pixel circuit 200 further includes: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, a second capacitor C2, and a third capacitor C3; wherein, the gate of the seventh transistor M7 is coupled to the second electrode of the eighth transistor M8, the first electrode of the seventh transistor M7 is coupled to the gate of the sixth transistor M6, and the second electrode of the seventh transistor M7 is coupled to the second light emission control signal terminal EM2; the gate of the eighth transistor M8 is coupled to the fourth scan signal terminal SS4, and the first electrode of the eighth transistor M8 is coupled to the data signal terminal DA; the first electrode of the second capacitor C2 is coupled to... The second electrode of the eighth transistor M8 is coupled to the second electrode of the second capacitor C2, which is coupled to the initialization signal terminal Vint. The gate of the ninth transistor M9 is coupled to the first electrode of the tenth transistor M10, the first electrode of the ninth transistor M9 is coupled to the gate of the sixth transistor M6, and the second electrode of the ninth transistor M9 is coupled to the pulse width modulation signal terminal HF. The gate of the tenth transistor M10 is coupled to the fifth scan signal terminal SS5, and the second electrode of the tenth transistor M10 is coupled to the data signal terminal DA. The first electrode of the third capacitor C3 is coupled to the first electrode of the tenth transistor M10, and the second electrode of the third capacitor C3 is coupled to the initialization signal terminal Vint.

[0113] Among them, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 can be configured without lightly doped regions, which can improve the output capability of the pixel circuit. Alternatively, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 can be configured with lightly doped regions, located between the source and channel regions or between the drain and channel regions. This configuration minimizes transistor leakage while ensuring output capability, thereby preventing leakage current during pixel circuit operation and maintaining pixel circuit output capability, thus reducing power consumption while ensuring performance.

[0114] This disclosure provides a method for fabricating an array substrate, including:

[0115] Multiple switching transistors in the pixel circuit are formed on the substrate.

[0116] The active layer forming at least one of the multiple switching transistors includes:

[0117] Ion implantation is performed on the active layer, and the concentration of implanted ions is greater than or equal to a first set concentration to form heavily doped regions on both sides of the channel region.

[0118] Ion implantation is performed on at least one region between the channel region and the heavily doped region of the active layer, and the concentration of the implanted ions is less than or equal to a second set concentration to form a lightly doped region, wherein the second set concentration is less than a first set concentration.

[0119] In this embodiment of the disclosure, ion implantation is performed on the active layer, and the concentration of the implanted ions is greater than or equal to a first predetermined concentration to form heavily doped regions on both sides of the channel region, including:

[0120] As shown in Figure 14, a semiconductor layer 10 is deposited on a substrate 100 and the semiconductor layer 10 is patterned to form an initial active layer 104.

[0121] As shown in Figure 14, a gate insulating layer 40 is deposited on the initial active layer 104;

[0122] As shown in Figure 14, a second conductive layer 50 is deposited on the gate insulating layer 40;

[0123] As shown in Figure 14, a photoresist layer 80 is deposited on the second conductive layer 50.

[0124] As shown in Figures 15 and 16, the photoresist layer 80 is patterned so that the orthographic projection of the remaining photoresist on the substrate 100 covers the orthographic projection of the first region 104a of the initial active layer 104 on the substrate 100, and the orthographic projection of the remaining photoresist on the substrate 100 does not overlap with the orthographic projection of the second region 104b of the initial active layer 104 on the substrate 100, with the second region 104b located on both sides of the first region 104a; the patterned photoresist layer 80 is used as a mask to etch the second conductive layer 50.

[0125] As shown in Figure 16, using the patterned photoresist layer 80 as a mask, ion implantation is performed on the second region 104b, and the concentration of implanted ions is greater than or equal to the first set concentration to form a heavily doped region.

[0126] Ion implantation is performed on at least one region between the channel region and the heavily doped region of the active layer, and the concentration of the implanted ions is less than or equal to a second predetermined concentration to form a lightly doped region, including:

[0127] As shown in Figures 17 and 18, the remaining photoresist is patterned again using ashing and etching processes. This ensures that the orthographic projection of the remaining photoresist on the substrate 100 after re-patterning covers the third region 104c of the initial active layer, and that the orthographic projection of the remaining photoresist on the substrate 100 after re-patterning does not overlap with the orthographic projection of the fourth region 104d of the initial active layer on the substrate 100. The first region 104a includes the third region 104c and the fourth region 104d, with the fourth region 104d located between the third region 104c and the second region 104b. Using the re-patterned photoresist layer 80 as a mask, the second conductive layer 50 is etched and modified.

[0128] As shown in Figure 18, using the re-patterned photoresist layer 80 as a mask, ion implantation is performed on the second region 104b, and the concentration of implanted ions is less than or equal to a second set concentration to form a lightly doped region, where the second set concentration is less than the first set concentration.

[0129] Based on the same disclosed concept, this disclosure also provides a display device, including the array substrate described above. The principle by which this display device solves the problem is similar to that of the aforementioned array substrate; therefore, the implementation of this display device can refer to the implementation of the aforementioned array substrate, and the repetitions will not be repeated here.

[0130] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0131] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0132] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: Substrate and pixel circuitry located on the substrate; The pixel circuit includes: a plurality of switching transistors and at least one driving transistor; the active layer of each switching transistor includes a source region, a drain region and a channel region located between the source region and the drain region, wherein the source region and the drain region are both heavily doped regions; The active layer of at least one of the plurality of switching transistors further includes a lightly doped region, the lightly doped region being located between at least one of the source region and the drain region and the channel region; The switching transistor includes: a first transistor; a lightly doped region of the first transistor located between the source region and the channel region and between the drain region and the channel region; the gate of the first transistor is coupled to a reset signal terminal, the first electrode of the first transistor is coupled to the gate of the driving transistor, and the second electrode of the first transistor is coupled to an initialization signal terminal.

2. The array substrate as claimed in claim 1, wherein, The switching transistor further includes: a second transistor; the lightly doped region of the second transistor is located between the source region and the channel region and between the drain region and the channel region; The gate of the second transistor is coupled to the first scan signal terminal, the first terminal of the second transistor is coupled to the gate of the driving transistor, and the second terminal of the second transistor is coupled to the drain of the driving transistor.

3. The array substrate as claimed in claim 1, wherein, The switching transistor further includes: a third transistor; the lightly doped region of the third transistor is located between the source region and the channel region or between the drain region and the channel region; The gate of the third transistor is coupled to the second scan signal terminal, the first terminal of the third transistor is coupled to the source of the driving transistor, and the second terminal of the third transistor is coupled to the data signal terminal.

4. The array substrate as claimed in claim 1, wherein, The pixel circuit further includes: a light-emitting device; the switching transistor further includes: a fourth transistor; the lightly doped region of the fourth transistor is located between the source region and the channel region or between the drain region and the channel region; The gate of the fourth transistor is coupled to the third scan signal terminal, the first terminal of the fourth transistor is coupled to the light-emitting device, and the second terminal of the fourth transistor is coupled to the initialization signal terminal.

5. The array substrate according to any one of claims 1-4, wherein, The pixel circuit further includes: a first light-emitting transistor and a second light-emitting transistor; The gate of the first light-emitting transistor is coupled to the first light-emitting control signal terminal, the first electrode of the first light-emitting transistor is coupled to the first power supply terminal, and the second electrode of the first light-emitting transistor is coupled to the source of the driving transistor. The gate of the second light-emitting transistor is coupled to the second light-emitting control signal terminal, the first terminal of the second light-emitting transistor is coupled to the drain of the driving transistor, and the second terminal of the second light-emitting transistor is coupled to the light-emitting device.

6. The array substrate according to any one of claims 1-4, wherein, The distance between the source region and the channel region is 0.1 μm to 1.5 μm, and the distance between the drain region and the channel region is 0.1 μm to 1.5 μm.

7. The array substrate according to any one of claims 1-4, wherein, The gate of the driving transistor includes a first gate and a second gate, wherein the first gate and the second gate are located in different film layers; The source of the driving transistor is electrically connected to the first gate of the driving transistor.

8. The array substrate as claimed in claim 7, wherein, The driving transistor further includes an active layer; the first gate of the driving transistor, the active layer of the driving transistor, and the second gate of the driving transistor are stacked sequentially. The active layer of the driving transistor includes a source region, a drain region, and a channel region located between the source region and the drain region. The source region of the driving transistor is electrically connected to the first gate of the driving transistor through a first via. The first via penetrates the insulating layer between the active layer of the driving transistor and the first gate. Alternatively, the source of the driving transistor is electrically connected to the first gate of the driving transistor through a second via. The orthographic projection of the second via onto the substrate does not overlap with the active layer of the driving transistor; The second via penetrates the insulating layer between the source and the first gate of the driving transistor; Alternatively, the source of the driving transistor is electrically connected to the first gate via a transition structure, and the transition structure and the second gate are located on the same layer.

9. A display device, wherein, Includes the array substrate as described in any one of claims 1-8.

10. A method for manufacturing an array substrate as described in any one of claims 1-8, wherein, include: Multiple switching transistors in the pixel circuit are formed on the substrate. The active layer forming at least one of the plurality of switching transistors includes: Ion implantation is performed on the active layer, and the concentration of implanted ions is greater than or equal to a first set concentration to form heavily doped regions on both sides of the channel region. Ion implantation is performed on at least one region between the channel region and the heavily doped region of the active layer, and the concentration of the implanted ions is less than or equal to a second set concentration to form a lightly doped region, wherein the second set concentration is less than the first set concentration.

11. The method for fabricating an array substrate as described in claim 10, wherein, The step of ion implantation into the active layer, wherein the concentration of implanted ions is greater than or equal to a first predetermined concentration, to form heavily doped regions on both sides of the channel region, includes: A semiconductor layer is deposited on the substrate and the semiconductor layer is patterned to form an initial active layer; A gate insulating layer is deposited on the initial active layer; A second conductive layer is deposited on the gate insulating layer; A photoresist layer is deposited on the second conductive layer and the photoresist layer is patterned such that the orthographic projection of the remaining photoresist on the substrate covers the orthographic projection of the first region of the initial active layer on the substrate, and the orthographic projection of the remaining photoresist on the substrate does not overlap with the orthographic projection of the second region of the initial active layer on the substrate, wherein the second region is located on both sides of the first region. Ion implantation is performed on the second region, and the concentration of implanted ions is greater than or equal to a first set concentration to form a heavily doped region; The step of ion implantation into at least one region between the channel region and the heavily doped region of the active layer, wherein the concentration of the implanted ions is less than or equal to a second predetermined concentration, to form a lightly doped region, includes: The remaining photoresist is patterned again using an ashing and etching process, so that the orthographic projection of the remaining photoresist on the substrate after repatterning covers the third region of the initial active layer, and the orthographic projection of the remaining photoresist on the substrate after repatterning does not overlap with the orthographic projection of the fourth region of the initial active layer on the substrate. The first region includes the third region and the fourth region, and the fourth region is located between the third region and the second region. Ion implantation is performed on the second region, and the concentration of implanted ions is less than or equal to a second set concentration to form a lightly doped region, wherein the second set concentration is less than the first set concentration.

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