Display panel and display apparatus

Abstract

Disclosed in the present disclosure are a display panel and a display apparatus. An array substrate comprises: a first substrate, a first transparent electrode layer located on the side of the first substrate facing an counter substrate, and a gate layer located on the side of the first transparent electrode layer facing the counter substrate; the first transparent electrode layer is in direct contact with the gate layer, and the first transparent electrode layer comprises a first transparent electrode located in each sub-pixel; the gate layer comprises gate lines extending in a pixel row direction, gates corresponding to the sub-pixels and electrically connected to the gate lines, and a compensation line, the compensation line covering a first edge of the first transparent electrode, the first edge being close to the gate corresponding to the sub-pixel where the first edge is located, and the first edge and the gate lines extending in the same direction; the counter substrate comprises: a second substrate, a plurality of filters located on the side of the second substrate facing the array substrate and arranged corresponding to the sub-pixels, and a black matrix located between the plurality of filters. An orthographic projection of the black matrix on the first substrate covers an orthographic projection of the compensation line on the first substrate.

Description

A display panel and display device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410823557.9, filed on June 24, 2024, entitled "A Display Panel and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0004] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention

[0005] This disclosure provides a display panel and display device for improving pixel aperture ratio. The specific solution is as follows:

[0006] This disclosure provides a display panel including an array substrate and an opposing substrate disposed opposite to each other, and a liquid crystal layer disposed between the array substrate and the opposing substrate;

[0007] The array substrate includes a plurality of pixel units arranged in an array, each pixel unit including a plurality of sub-pixels; the array substrate further includes: a first substrate, a first transparent electrode layer located on the side of the first substrate facing the opposing substrate, and a gate layer located on the side of the first transparent electrode layer facing the opposing substrate; the first transparent electrode layer and the gate layer are in direct contact, the first transparent electrode layer includes a first transparent electrode located in each sub-pixel, the gate layer includes a gate line extending along the pixel row direction, a gate corresponding to each sub-pixel and electrically connected to the gate line, and a compensation line, the compensation line covering a first edge of the first transparent electrode, the first edge being close to the gate corresponding to the sub-pixel, and the first edge having the same extension direction as the gate line;

[0008] The opposing substrate includes: a second substrate, a plurality of filters disposed on the side of the second substrate facing the array substrate and corresponding to the sub-pixels, and a black matrix disposed between the plurality of filters; the orthogonal projection of the black matrix on the first substrate covers the orthogonal projection of the compensation line on the first substrate.

[0009] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the compensation line is conformally arranged along the first edge.

[0010] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the boundary of the compensation line near the gate is flush with the boundary of the first transparent electrode near the gate.

[0011] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the width of the compensation line is smaller than the width of the gate line.

[0012] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the array substrate further includes a second transparent electrode layer located on the side of the gate layer facing the opposing substrate. The second transparent electrode layer includes a second transparent electrode located in each of the sub-pixels and a first overlap between two adjacent second transparent electrodes arranged along the pixel column direction.

[0013] The gate layer further includes a second overlap portion located on the side of the first transparent electrode away from the first substrate and corresponding to the two ends of the first overlap portion. Two adjacent first transparent electrodes arranged along the pixel column direction are electrically connected to the first overlap portion through the second overlap portion.

[0014] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the compensation line and the second overlapping portion corresponding to the same sub-pixel are an integral structure.

[0015] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the second transparent electrode includes a first boundary disposed along the end of the first overlap portion, and the orthogonal projection boundary of the black matrix on the first substrate is flush with the orthogonal projection of the first boundary on the first substrate.

[0016] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the array substrate further includes: a gate insulating layer located between the gate layer and the second transparent electrode layer, an active layer located between the gate insulating layer and the second transparent electrode layer, a source / drain layer located between the active layer and the second transparent electrode layer, and a passivation layer located between the source / drain layer and the second transparent electrode layer; the active layer and the source / drain layer are in direct contact.

[0017] The second overlap is electrically connected to the end of the first overlap through a through-hole penetrating the gate insulation layer and the passivation layer.

[0018] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the array substrate further includes connecting lines extending along the pixel row direction. The connecting lines include a first connecting line and a second connecting line that are stacked and contacted. The first connecting line is located in the first transparent electrode layer, and the second connecting line is located in the gate layer. Each row of the first transparent electrodes is electrically connected to each other through the connecting lines.

[0019] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the second connecting line and the second overlapping portion electrically connected to the first transparent electrode in the corresponding row are an integral structure.

[0020] In one possible implementation, the display panel provided in the embodiments of this disclosure further includes a spacer located between the array substrate and the opposing substrate, wherein the orthographic projection of the spacer on the first substrate is located between two adjacent sub-pixels arranged along the pixel column direction.

[0021] In one possible implementation, in the display panel provided in the embodiments of this disclosure, each row of pixel units arranged along the pixel row direction is electrically connected to at least two rows of gate lines.

[0022] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the first transparent electrode layer is a common electrode layer, the second transparent electrode layer is a pixel electrode layer, the first transparent electrode is a planar electrode, and the second transparent electrode is a slit electrode.

[0023] Accordingly, this disclosure also provides a display device, including the display panel provided in the embodiments of this disclosure. Attached Figure Description

[0024] Figure 1 is a pixel design layout of two adjacent sub-pixels along the pixel column direction in a display panel provided in the related art;

[0025] Figure 2 is a schematic diagram of one of the cross sections in Figure 1;

[0026] Figure 3 is another schematic diagram of a cross-section of Figure 1;

[0027] Figure 4 is a pixel design layout of two adjacent sub-pixels along the pixel column direction in a display panel provided in this disclosure;

[0028] Figure 5 is a schematic diagram of one of the cross sections in Figure 4;

[0029] Figure 6 is another schematic diagram of a cross-section of Figure 4;

[0030] Figure 7 is an optical simulation diagram of the light leakage area above the grid line at the bottom of the black screen corresponding to the structure shown in Figure 1 (43-inch FHD product) in the related technology;

[0031] Figure 8 is an optical simulation diagram of the light leakage area above the grid line at the bottom of the black screen corresponding to the structure shown in Figure 4 of this disclosure (43-inch FHD product);

[0032] Figure 9 is an optical simulation diagram of the light leakage area at the via V under a black screen corresponding to the structure shown in Figure 4 of this disclosure (43-inch FHD product);

[0033] Figure 10 is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure;

[0034] Figure 11 is a schematic diagram of another structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0036] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "comprising" or "including," and similar terms as used in this disclosure, mean that an element or object preceding the term encompasses the elements or objects listed following the term and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "inner," "outer," "upper," and "lower" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0037] As used in this disclosure, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0038] As used in this disclosure, "parallel," "perpendicular," and "equal" include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein an acceptable deviation range for approximate parallelism may be, for example, within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°. "Equal" includes absolute equality and approximate equality, wherein an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 10% of either one.

[0039] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on another layer or substrate, or that there is an intermediate layer between the layer or element and another layer or substrate.

[0040] This disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, for clarity, the thickness of layers and the area of ​​regions are enlarged. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0041] In this disclosure, circles, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined, but can be approximate circles, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances may exist, and chamfers, curved edges, and other deformations may exist.

[0042] With the continuous maturation of liquid crystal display technology, LCD driving backplanes have gradually developed towards lower cost and lower power consumption. Currently, the driving backplane reduces the number of data signal channels by adding gate drive circuits (GOA) and gate lines for time-division driving, thereby reducing the number of driver chips (ICs) used. This is a key research focus in achieving low-cost, low-power multiple gate technology.

[0043] Currently, commonly used multi-gate pixel architectures include Dual Gate (each row of pixel units is driven by two rows of gate lines), Triple Gate (each row of pixel units is driven by three rows of gate lines), and those driven by even more rows of gate lines. Multi-gate driving can reduce power consumption and cost, but it inevitably leads to a decrease in pixel aperture ratio, resulting in a decline in display quality. Therefore, how to increase the number of gate lines to minimize power consumption and cost while maximizing the aperture ratio has become a direction that needs to be researched and solved in this field.

[0044] The structure of an LCD display panel in related technologies is shown in Figures 1-3. Figure 1 shows the pixel layout of two adjacent sub-pixels along the Y-axis of the pixel column in the LCD display panel. Figure 2 is a cross-sectional view of Figure 1, and Figure 3 is another cross-sectional view of Figure 1. This LCD display panel includes an array substrate 1 and an opposing substrate 2 disposed opposite each other, as well as a liquid crystal layer (not shown) and spacers 3 disposed between the array substrate 1 and the opposing substrate 2. The array substrate 1 includes multiple pixel units arranged in an array, each pixel unit including multiple sub-pixels, and the emission colors of the multiple sub-pixels can be different. Optionally, each pixel unit includes three sub-pixels with emission colors of red, green, and blue, respectively. Red, green, and blue are the basic colors in the display field. Various colors are obtained by changing the red, green, and blue color channels and superimposing them, thereby achieving full-color display.

[0045] Specifically, as shown in Figures 1-3, the array substrate 1 further includes: a first substrate 11, a first transparent electrode layer 12 located on the side of the first substrate 1 facing the opposing substrate 2, a gate layer 13 located on the side of the first transparent electrode layer 12 facing the opposing substrate 2, a gate insulating layer 14 located on the side of the gate layer 13 facing the array substrate 2, an active layer 15 located on the side of the gate insulating layer 14 facing the opposing substrate, a source / drain layer 16 located on the side of the active layer 15 facing the opposing substrate 2, a passivation layer 17 located on the side of the source / drain layer 16 facing the opposing substrate 2, and a second transparent electrode layer 18 located on the side of the passivation layer 17 facing the opposing substrate 2; wherein, the first transparent electrode layer 12 and the gate layer 13 are in direct contact, that is, in order to save mask and reduce manufacturing costs, the first transparent electrode layer 12 and the gate layer 13 are fabricated using a single mask process, that is, a halftone mask can be used. Fabricated using Mask (HTM) technology; the first transparent electrode layer 12 includes a first transparent electrode 121 located in each sub-pixel, and the gate layer 13 includes a gate line 131 extending along the pixel row direction X and a gate 132 corresponding to each sub-pixel and electrically connected to the gate line 131. Taking each row of pixel units driven by six rows of gate lines as an example, that is, six rows of gate lines are set between two adjacent rows of pixel units; the active layer 15 and the source / drain layer 16 are in direct contact, that is, in order to save mask and reduce manufacturing costs, the active layer 15 and the source / drain layer 16 are fabricated using a mask process, that is, HTM technology can be used; the second transparent electrode layer 18 includes a second transparent electrode 181 located in each sub-pixel and a first overlap portion 182 located between two adjacent second transparent electrodes 181 arranged along the pixel column direction Y, and two adjacent first transparent electrodes 181 arranged along the pixel column direction Y are electrically connected through the first overlap portion 182.

[0046] Specifically, as shown in Figures 1-3, the opposing substrate 2 includes: a second substrate 21, a plurality of filters (not shown) located on the side of the second substrate 21 facing the array substrate 1 and disposed corresponding to the sub-pixels, and a black matrix 22 located between the plurality of filters.

[0047] Specifically, as shown in Figures 1 and 2, a lateral electric field exists between the gate line 131 and the first transparent electrode 181, causing irregular deflection of the liquid crystal at this location, and the deflection range is relatively large. Simultaneously, the first transparent electrode 181 is transparent, resulting in a large area of ​​black screen light leakage above the gate line 131 along the pixel column direction Y (the area indicated by the bidirectional arrows). Therefore, a large area of ​​black matrix 22 is needed to cover the irregularly deflected area of ​​the liquid crystal. Considering the alignment deviation when aligning the array substrate 1 and the opposing substrate 2, the black matrix 22 needs to cover an even greater distance into the sub-pixel area, leading to a significant loss in aperture ratio. This problem is even more pronounced in multi-gate driven pixel designs, as the increased number of gate lines 131 itself causes a significant loss in aperture ratio. Therefore, a pixel design that maximizes the aperture ratio while ensuring multi-gate driving is required.

[0048] In addition, as shown in Figures 1 and 3, there is a large range of light leakage at the edge of the aperture when two adjacent first transparent electrodes 181 are connected along the Y-axis of the pixel column. This also requires the black matrix 22 to cover a large area, which further leads to a loss of aperture ratio.

[0049] In view of this, in order to improve the pixel aperture ratio of the display panel, this disclosure provides a display panel, as shown in FIG5, including an array substrate 1 and an opposing substrate 2 disposed opposite to each other, and a liquid crystal layer (not shown) disposed between the array substrate 1 and the opposing substrate 2.

[0050] Specifically, as shown in Figures 4 and 5, Figure 4 is a pixel design layout of two adjacent sub-pixels along the pixel column direction in the display panel provided in this disclosure, and Figure 5 is a cross-sectional schematic diagram of Figure 4. The array substrate 1 includes multiple pixel units distributed in an array, and each pixel unit includes multiple sub-pixels. Optionally, the multiple sub-pixels emit different colors. For example, the multiple sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel emits red (R), the second sub-pixel emits green (G), and the third sub-pixel emits blue (B). RGB is the basic color in the display field. Various colors are obtained by changing the R, G, and B color channels and superimposing them, thereby achieving full-color display.

[0051] Specifically, as shown in Figures 4 and 5, the array substrate 1 further includes: a first substrate 11, a first transparent electrode layer 12 located on the side of the first substrate 11 facing the opposing substrate 2, and a gate layer 13 located on the side of the first transparent electrode layer 12 facing the opposing substrate 2; the first transparent electrode layer 12 and the gate layer 13 are in direct contact, that is, in order to save mask and reduce manufacturing costs, the first transparent electrode layer 12 and the gate layer 13 are fabricated using a single mask process, i.e., a halftone mask can be used. Fabricated using Mask (HTM) technology, the first transparent electrode layer 12 includes a first transparent electrode 121 located in each sub-pixel, and the gate layer 13 includes a gate line 131 extending along the pixel row direction X, a gate 132 corresponding to each sub-pixel and electrically connected to the gate line 131, and a compensation line 133. This disclosure takes the driving of each row of pixel units by six rows of gate lines 131 as an example, that is, six rows of gate lines 131 are set between two adjacent rows of pixel units; the compensation line 133 covers the first edge A1 of the first transparent electrode 121, the first edge A1 is close to the gate 132 corresponding to the sub-pixel, and the first edge A1 has the same extension direction as the gate line 131.

[0052] Specifically, as shown in Figures 4 and 5, the first transparent electrode layer 12 can be a common electrode layer, and the first transparent electrode 12 is a planar electrode. In this disclosure, a compensation line 133 is provided on the first edge A1 of the first transparent electrode 121, which is in the same layer as the gate line 131. In this way, when a common voltage (Vcom) is applied to the first transparent electrode 121, since the compensation line 133 is in direct contact with the first transparent electrode 121, the voltage on the compensation line 133 is Vcom. There is no new lateral electric field between the compensation line 133 and the first transparent electrode 121 or the second transparent electrode (i.e., the pixel electrode, which will be introduced later). The setting of the compensation line 133 will not cause abnormal deflection of the liquid crystal. Meanwhile, since the gate layer 13 itself is an opaque material, the originally large range of invalid liquid crystal deflection area (i.e., the light leakage area, the area indicated by the bidirectional arrows) in Figures 1 and 2 can be limited to between the gate line 131 and the newly added compensation line 133, so that the light leakage area above the gate line 131 is greatly reduced. In this way, the black matrix on the opposing substrate 2 (described later) only needs to cover the area where the compensation line 133 is located. The black matrix does not need to cover the sub-pixels above the gate line 131 in a large area. The black matrix coverage area is reduced, which significantly improves the pixel aperture ratio.

[0053] Specifically, as shown in Figures 4 and 5, the opposing substrate 2 includes: a second substrate 21, and a plurality of filters (not shown) located on the side of the second substrate 21 facing the array substrate 1 and disposed corresponding to the sub-pixels; specifically, the plurality of filters include: a red filter (e.g., a red color film) corresponding to the first sub-pixel, a green filter (e.g., a green color film) corresponding to the second sub-pixel, and a blue filter (e.g., a blue color film) corresponding to the third sub-pixel.

[0054] Specifically, as shown in Figures 4 and 5, the opposing substrate 2 also includes a black matrix 22 located between multiple filters. The black matrix 22 is used to avoid light crosstalk between adjacent sub-pixels. Due to the setting of the compensation line 133, the light leakage area above the gate line 131 is greatly reduced. Therefore, the orthographic projection of the black matrix 22 on the first substrate 11 covers the orthographic projection of the compensation line 133 on the first substrate 11. The black matrix 22 does not need to cover the sub-pixels above the gate line 131 in a large area. The coverage area of ​​the black matrix 22 is reduced, which significantly improves the pixel aperture ratio.

[0055] In some embodiments of the display panel provided in this disclosure, as shown in FIG4, during the layout design of the array substrate, the patterns of some structures may avoid the patterns of other structures, resulting in the first edge A1 of the first transparent electrode 121 being either a broken line or an approximately straight line. Therefore, the compensation line 133 may also be either a broken line or an approximately straight line, that is, the compensation line 133 may be set along the shape of the first edge A1. FIG4 of this disclosure embodiment takes the first edge A1 as a broken line as an example, in which case the compensation line 133 is also a broken line. Of course, it is not limited to this. The shape of the compensation line 133 needs to be designed according to the shape of the first edge A1 of the first transparent electrode 121.

[0056] In some embodiments of the display panel provided in this disclosure, as shown in Figures 4 and 5, the boundary B1 of the compensation line 133 near the gate 132 is flush with the boundary C1 of the first transparent electrode 121 near the gate 132. This reduces the area occupied by the compensation line 133 in the sub-pixel, further reducing the area covered by the black matrix 22 in the sub-pixel, thereby further improving the pixel aperture ratio.

[0057] In some embodiments, in the display panel provided in this disclosure, as shown in Figures 4 and 5, the width of the compensation line 133 is smaller than the width of the gate line 131. This further reduces the area of ​​the sub-pixel occupied by the compensation line 133, making the area of ​​the sub-pixel covered by the black matrix 22 even smaller, thereby further improving the pixel aperture ratio. Specifically, when the first transparent electrode layer 12 and the gate layer 13 are fabricated using HTM technology, the mask width corresponding to the compensation line 133 can be a limit value, that is, the added compensation line 133 is as narrow as possible to achieve the limit width of the mask, which can increase the aperture ratio. Ideally, the boundary D1 of the black matrix 22 away from the gate 132 and the boundary B2 of the compensation line 133 away from the gate 132 should be flush. However, due to alignment deviation, the boundary D1 of the black matrix 22 away from the gate 132 generally needs to exceed the boundary B2 of the compensation line 133 away from the gate 132 by a certain distance, for example, this distance can be about 3 μm.

[0058] In some embodiments, as shown in Figures 4 and 5, the display panel provided in this disclosure further includes a spacer 3 located between the array substrate 1 and the opposing substrate 2. The orthographic projection of the spacer 3 on the first substrate 11 is located between two adjacent sub-pixels arranged along the pixel column direction Y. Specifically, the spacer 3 can be disposed in the central region of the area where the six rows of gate lines 131 are located. Generally, the film layer position is relatively higher where metal lines are provided, that is, the film layer height in the area where the six rows of gate lines 131 are located is relatively high. The spacer 3 is easy to slide to the sub-pixel area and scratch the array substrate. The compensation line 133 added in this disclosure forms a grid-like structure with the parallel six rows of gate lines 131, which can prevent the spacer 3 above the six rows of gate lines 131 from sliding excessively to a certain extent, avoiding scratching the sub-pixels and affecting the normal driving of the pixels. Therefore, the compensation line 133 added in this disclosure plays a protective role for the sub-pixels, thereby improving pixel stability and the overall display reliability of the display panel.

[0059] In some embodiments, in the display panel provided in the present disclosure, as shown in Figures 4-6, Figure 6 is another cross-sectional schematic diagram of Figure 4, the array substrate 1 further includes a second transparent electrode layer 18 located on the side of the gate layer 13 facing the opposing substrate 2, a gate insulating layer 14 located between the gate layer 13 and the second transparent electrode layer 18, an active layer 15 located between the gate insulating layer 14 and the second transparent electrode layer 18, a source drain layer 16 located between the active layer 15 and the second transparent electrode layer 18, and a passivation layer 17 located between the source drain layer 16 and the second transparent electrode layer 18; the active layer 15 and the source drain layer 16 are in direct contact, that is, in order to save mask and reduce manufacturing costs, the active layer 15 and the source drain layer 16 are fabricated using a single mask process, that is, they can be fabricated using HTM technology.

[0060] Specifically, as shown in Figures 4-6, the second transparent electrode layer 18 includes a second transparent electrode 181 located in each sub-pixel and a first overlapping portion 182 located between two adjacent second transparent electrodes 181 arranged along the pixel column direction Y. In the structure shown in Figure 3 of the related art, two adjacent first transparent electrodes 121 arranged along the pixel column direction Y are directly electrically connected through the first overlapping portion 182. That is, vias V that penetrate the gate insulating layer 14 and the passivation layer 17 are correspondingly provided below the two ends of the first overlapping portion 182. The first overlapping portion 182 fills the vias V and is electrically connected to the first transparent electrodes 121. Thus, the voltage of the first overlapping portion 182 above the vias V is Vcom, and there is a lateral electric field between it and the second transparent electrodes 181 in the sub-pixel, causing abnormal deflection of the liquid crystal at the vias V. At the same time, since the vias V are overlapped through the transparent first overlapping portion 182, the vias V are light-transmitting positions. When displaying a black screen, there is a large range of light leakage at the edge of the vias V. Therefore, the vias V need to be covered by the black matrix 22.

[0061] Specifically, as shown in Figures 4 and 6, the gate layer 13 of this disclosure further includes a second overlap portion 134 located on the side of the first transparent electrode 121 away from the first substrate 11 and corresponding to the two ends of the first overlap portion 182. Two adjacent first transparent electrodes 121 arranged along the pixel column direction Y are electrically connected to the first overlap portion 182 through the second overlap portion 134, that is, the second overlap portion 134 is directly in contact with the first transparent electrode 121 and electrically connected. The second overlap portion 134 is electrically connected to the end of the first overlap portion 182 through a via V that penetrates the gate insulating layer 14 and the passivation layer 17, thereby realizing that two adjacent first transparent electrodes 121 arranged along the pixel column direction Y are electrically connected through the first overlap portion 182 located in the second transparent electrode layer 18. This disclosure adds a second overlapping portion 134 at the via V location, which is disposed on the same layer as the gate 132. The second overlapping portion 134 is directly overlapping with the first transparent electrode 121. Therefore, the voltage of the second overlapping portion 134 is Vcom, and no additional lateral electric field is introduced. At the same time, since the second overlapping portion 134 itself is an opaque material, the light leakage range of the black screen at the via V is reduced, thereby improving the pixel aperture ratio.

[0062] Specifically, as shown in Figures 1 and 2, the via V in the related technology is a deep hole penetrating the passivation layer 17 and the gate insulating layer 14. Therefore, the slope angle of the via V is relatively large, and the first overlap portion 182 located within the via V is prone to open circuit. This causes the two adjacent first transparent electrodes 121 along the pixel column direction Y to fail to overlap properly, increasing the overall load of the first transparent electrode 121 and increasing the power consumption of the Vcom portion of the IC. As shown in Figures 4 and 6, this disclosure reduces the depth of the via V and the slope angle of the via V by adding a second overlap portion 134 at the via V. This reduces the probability of the first overlap portion 182 located within the via V opening circuit, improves pixel reliability, reduces the possibility of increased Vcom power consumption, improves pixel design reliability, and avoids increased power consumption.

[0063] In some embodiments, in the display panel provided in the present disclosure, as shown in FIG4 and FIG6, the second transparent electrode layer 18 may be a pixel electrode layer and the second transparent electrode 181 may be a slit electrode.

[0064] In some embodiments, as shown in Figures 4-6, in the display panel provided in this disclosure, the compensation line 133 and the second overlapping portion 134 corresponding to the same sub-pixel are integrally structured. Thus, by simply changing the original pattern when forming the compensation line 133, the patterns of the second overlapping portion 134 and the compensation line 133 can be formed in a single patterning process, eliminating the need for a separate process to fabricate the second overlapping portion 134. This simplifies the manufacturing process, saves production costs, and improves production efficiency.

[0065] In some embodiments of the display panel provided in this disclosure, as shown in Figures 4-6, the second transparent electrode 181 includes a first boundary E1 disposed along the end of the first overlap portion 182, and the orthographic projection boundary D2 of the black matrix 22 on the first substrate 11 is flush with the orthographic projection of the first boundary E1 on the first substrate 11. That is, due to the provision of the second overlap portion 134, the light leakage area at the via V can be reduced, so the black matrix 22 only needs to cover the first boundary E1 of the second transparent electrode 181 at the via V, further improving the pixel aperture ratio.

[0066] In a specific implementation, as shown in Figures 4-6, in the display panel provided in the embodiments of this disclosure, each sub-pixel includes a pixel electrode (i.e., a second transparent electrode 18) and a thin-film transistor T electrically connected to the pixel electrode. The thin-film transistor T includes a gate 132, an active layer 15, and a first electrode 161 and a second electrode 162 located in the source-drain layer 16. The gate 132 of the thin-film transistor T is electrically connected to the corresponding gate line 132. The unit electrode 161 of the thin-film transistor T is electrically connected to the corresponding data line 163 located in the source-drain layer 16. The second electrode 162 of the thin-film transistor T is electrically connected to the corresponding second transparent electrode 18.

[0067] Optionally, the first electrode of the thin-film transistor can be the source and the second electrode can be the drain, or the first electrode of the thin-film transistor can be the drain and the second electrode can be the source; no limitation is made here. The active layer of the thin-film transistor can be made of amorphous silicon (a-Si), polycrystalline silicon, oxide (such as indium gallium zinc oxide IGZO), etc.

[0068] Optionally, the materials of the gate insulating layer and the passivation layer can be at least one of inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0069] Optionally, the materials of the first transparent electrode layer and the second transparent electrode layer include transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0070] Optionally, the material of the gate layer may include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The gate layer may be a single-layer structure or a stacked structure, for example, the gate layer may be a single-layer structure composed of a molybdenum metal layer.

[0071] Optionally, the source / drain layer may be made of metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The source / drain layer may be a single-layer structure or a stacked structure, for example, the source / drain layer may be a stacked structure composed of a titanium metal layer / aluminum metal layer / titanium metal layer.

[0072] In some embodiments of the display panel provided in this disclosure, as shown in FIG4, the array substrate 1 further includes a connecting line 3 extending along the pixel row direction X. The connecting line 3 includes a first connecting line 31 and a second connecting line 32 disposed in a stacked contact configuration. The first connecting line 31 is located in the first transparent electrode layer 12, and the second connecting line 32 is located in the gate layer 13. Each row of first transparent electrodes 121 is electrically connected to each other through the connecting line 3. This achieves electrical connection of the first transparent electrodes 121 within all sub-pixels.

[0073] In some embodiments of the display panel provided in this disclosure, as shown in FIG4, the second connecting line 32 and the second overlapping portion 134 electrically connected to the corresponding row of the first transparent electrode 121 are integral structures. Thus, by simply changing the original pattern when forming the second overlapping portion 134, the patterns of the second overlapping portion 134 can be formed in a single patterning process, eliminating the need for a separate process to fabricate the second connecting line 32. This simplifies the manufacturing process, saves production costs, and improves production efficiency.

[0074] In some embodiments, in the display panel provided in this disclosure, as shown in FIG4, each row of pixel units arranged along the pixel row direction X is electrically connected to at least two rows of gate lines 131. Specifically, this disclosure takes the example of each row of pixel units being electrically connected to six rows of gate lines, that is, six rows of gate lines are provided between two adjacent rows of pixel units, that is, each row of pixel units is driven by six rows of gate lines, but it is not limited to this; for example, each row of pixel units arranged along the pixel row direction X is electrically connected to two, three, four, five or even more rows of gate lines 131. Of course, the pixel design of this disclosure is also applicable to single gate (each row of pixel units is driven by one row of gate lines).

[0075] As shown in Figures 7-9, Figure 7 is an optical simulation diagram of the light leakage area above the grid line under a black screen corresponding to the structure shown in Figure 1 (43-inch FHD product) in the related art; Figure 8 is an optical simulation diagram of the light leakage area above the grid line under a black screen corresponding to the structure shown in Figure 4 (43-inch FHD product) in this disclosure; and Figure 9 is an optical simulation diagram of the light leakage area at the via V under a black screen corresponding to the structure shown in Figure 4 (43-inch FHD product) in this disclosure. The black area represents the light leakage area. It can be seen that the width of the light leakage area above the grid line 131 in the related art reaches 14μm, while the width of the light leakage area above the grid line 131 in this disclosure is only 7.5μm. There is no light leakage on the left and top sides of the upper via V, and no light leakage on the left, bottom, and right sides of the lower via V. The inventors have found that the solution of this disclosure can achieve a 5% increase in aperture ratio for the corresponding pixel design of a 43-inch FHD product; in addition, the solution of this disclosure can achieve a 10% increase in aperture ratio for the corresponding pixel design of a 43-inch UHD product.

[0076] In summary, this disclosure proposes a novel multi-gate driven pixel design. Based on multi-gate driving, by adding a compensation line in the same layer as the gate at the edge of the first transparent electrode and adding a second overlapping portion in the same layer as the gate at the connection via of two adjacent first transparent electrodes in the pixel column direction, the light leakage range of the pixel black screen is reduced. This improves the pixel aperture ratio while ensuring low cost and low power consumption, and avoids damage to the array substrate caused by excessive sliding of the spacer.

[0077] It should be noted that other essential components of the display panel are all known to those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0078] Based on the same inventive concept, this disclosure also provides a display device, including the display panel described above. Since the principle by which this display device solves the problem is similar to that of the display panel described above, the implementation of the display device provided in this disclosure can refer to the implementation of the display panel described above, and repeated details will not be elaborated further.

[0079] In some embodiments, as shown in FIG10, the display device provided in the present disclosure further includes a backlight module 5 located on the light-incident side of the array substrate 1.

[0080] In some embodiments, in the display device provided in this disclosure, the backlight module 5 can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature light-emitting diodes (Mini LEDs, Micro LEDs, etc.).

[0081] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.

[0082] In specific implementation, the display device provided in the embodiments of this disclosure is a liquid crystal display device. The liquid crystal display device also includes other necessary components and parts, such as a housing, a main circuit board, a power cord, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here and should not be regarded as a limitation of this disclosure.

[0083] In specific implementation, the display device provided in the embodiments of this disclosure may be a full-screen display device or a flexible display device, etc., and is not limited thereto.

[0084] In specific implementations, the display device provided in this disclosure embodiment can be a full-screen mobile phone as shown in FIG11. Of course, the display device provided in this disclosure embodiment can also be any product or component with display function, such as a tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on this disclosure. This display device includes, but is not limited to, components such as: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in this disclosure embodiment. In other words, the display device provided in this disclosure embodiment can include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0085] The present invention discloses a display panel and display device. By setting a compensation line on the first edge of the first transparent electrode in the same layer as the gate line, and the voltage on the compensation line is Vcom, the originally large range of invalid liquid crystal deflection (light leakage area) in the related technology can be limited to between the gate line and the newly added compensation line. This greatly reduces the light leakage area above the gate line. In this way, the black matrix on the opposing substrate only needs to cover the area where the compensation line 133 is located. It is not necessary for the black matrix to cover a large area of ​​the sub-pixels above the gate line. The black matrix coverage area is reduced, which significantly improves the pixel aperture ratio.

[0086] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0087] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein, It includes an array substrate and a counter substrate disposed opposite to each other, and a liquid crystal layer disposed between the array substrate and the counter substrate; The array substrate includes a plurality of pixel units arranged in an array, each pixel unit including a plurality of sub-pixels; the array substrate further includes: a first substrate, a first transparent electrode layer located on the side of the first substrate facing the opposing substrate, and a gate layer located on the side of the first transparent electrode layer facing the opposing substrate; the first transparent electrode layer and the gate layer are in direct contact, the first transparent electrode layer includes a first transparent electrode located in each sub-pixel, the gate layer includes a gate line extending along the pixel row direction, a gate corresponding to each sub-pixel and electrically connected to the gate line, and a compensation line, the compensation line covering a first edge of the first transparent electrode, the first edge being close to the gate corresponding to the sub-pixel, and the first edge having the same extension direction as the gate line; The opposing substrate includes: a second substrate, a plurality of filters disposed on the side of the second substrate facing the array substrate and corresponding to the sub-pixels, and a black matrix disposed between the plurality of filters; the orthogonal projection of the black matrix on the first substrate covers the orthogonal projection of the compensation line on the first substrate.

2. The display panel as claimed in claim 1, wherein, The compensation line is set along the first edge in a conformal manner.

3. The display panel as described in claim 2, wherein, The compensation line is flush with the boundary of the gate near the first transparent electrode near the gate.

4. The display panel as claimed in claim 3, wherein, The width of the compensation line is smaller than the width of the gate line.

5. The display panel as described in any one of claims 1-4, wherein, The array substrate further includes a second transparent electrode layer located on the side of the gate layer facing the opposing substrate. The second transparent electrode layer includes a second transparent electrode located in each of the sub-pixels and a first overlap between two adjacent second transparent electrodes arranged along the pixel column direction. The gate layer further includes a second overlap portion located on the side of the first transparent electrode away from the first substrate and corresponding to the two ends of the first overlap portion. Two adjacent first transparent electrodes arranged along the pixel column direction are electrically connected to the first overlap portion through the second overlap portion.

6. The display panel as claimed in claim 5, wherein, The compensation line and the second overlapping portion corresponding to the same sub-pixel are an integral structure.

7. The display panel as claimed in claim 6, wherein, The second transparent electrode includes a first boundary disposed along the end of the first overlap portion, and the orthographic projection boundary of the black matrix on the first substrate is flush with the orthographic projection of the first boundary on the first substrate.

8. The display panel according to any one of claims 5-7, wherein, The array substrate further includes: a gate insulating layer located between the gate layer and the second transparent electrode layer; an active layer located between the gate insulating layer and the second transparent electrode layer; a source / drain layer located between the active layer and the second transparent electrode layer; and a passivation layer located between the source / drain layer and the second transparent electrode layer; the active layer and the source / drain layer are in direct contact. The second overlap is electrically connected to the end of the first overlap through a through-hole penetrating the gate insulation layer and the passivation layer.

9. The display panel according to any one of claims 5-8, wherein, The array substrate further includes connecting lines extending along the pixel row direction. The connecting lines include a first connecting line and a second connecting line that are stacked and contacted. The first connecting line is located in the first transparent electrode layer, and the second connecting line is located in the gate layer. Each row of the first transparent electrodes is electrically connected to each other through the connecting lines.

10. The display panel as claimed in claim 9, wherein, The second connecting line and the second overlapping portion that is electrically connected to the first transparent electrode in the corresponding row are an integral structure.

11. The display panel according to any one of claims 1-10, wherein, It also includes a spacer located between the array substrate and the opposing substrate, the orthographic projection of which on the first substrate lies between two adjacent sub-pixels arranged along the pixel column direction.

12. The display panel according to any one of claims 1-11, wherein, Each row of pixel units arranged along the pixel row direction is electrically connected to at least two rows of gate lines.

13. The display panel according to any one of claims 5-10, wherein, The first transparent electrode layer is a common electrode layer, the second transparent electrode layer is a pixel electrode layer, the first transparent electrode is a planar electrode, and the second transparent electrode is a slit electrode.

14. A display device, wherein, Includes the display panel as described in any one of claims 1-13.

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