Display panel and display device

Abstract

A display panel (1100), comprising a pixel circuit (100) and a test circuit (200). The pixel circuit (100) comprises a driving transistor (DT), a data processing sub-circuit (10), a compensation sub-circuit (20), and a functional sub-circuit (30). A control electrode of the driving transistor (DT) is electrically connected to a first node (N1), a first electrode thereof is electrically connected to a second node (N2), and a second electrode thereof is electrically connected to a third node (N3). The data processing sub-circuit (10) is configured to: in a first stage, transmit a first voltage signal (V1) to a fourth node (N4); and in a second stage, transmit a data signal (Vdata) to the fourth node (N4), and adjust the voltage of the first node (N1) on the basis of a voltage variation of the fourth node (N4). The compensation sub-circuit (20) is configured to electrically connect the first node (N1) to the second node (N2). The functional sub-circuit (30) is electrically connected to a control signal end (GX), a first signal line (LX) and a target node, and is configured to electrically connect the first signal line (LX) to the target node. A first end (21) of the test circuit (200) is electrically connected to the first node (N1), the second node (N2), the third node (N3) or the first signal line (LX), and a second end (22) thereof is electrically connected to a data signal line (DL), a first voltage signal line (Vinit1) or the fourth node (N4).

Description

Display panel and display device

[0001] The present application claims priority to Chinese Patent Application No. 202410823622.8, filed on June 24, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0003] With the continuous development of display technology, display panels have been widely applied, and people's requirements for display panels are also getting higher and higher; among them, large size, high pixel density (Pixels Per Inch; referred to as PPI) and high refresh rate are important development directions of display panels. When the display panel is working, the threshold voltage compensation time of the driving transistor of the pixel circuit is getting shorter and shorter, and how to improve the threshold voltage compensation time of the driving transistor of the pixel circuit is an important technical problem faced in the development process of the current display panel. SUMMARY

[0004] In one aspect, a display panel is provided. The display panel includes a plurality of pixel circuits and at least one test circuit. The pixel circuit includes a driving transistor, a data processing sub-circuit, a compensation sub-circuit, and at least one function sub-circuit. The control electrode of the driving transistor is electrically connected to a first node, the first electrode is electrically connected to a second node, and the second electrode is electrically connected to a third node. The driving transistor is configured to electrically connect the second node and the third node under the control of the voltage of the first node. The data processing sub-circuit is electrically connected to a first scan signal terminal, a second scan signal terminal, a data signal line, a first voltage signal line, and the first node. The data processing sub-circuit has a fourth node. The data processing sub-circuit is configured to, in a first stage, transmit a first voltage signal from the first voltage signal line to the fourth node under the control of the first scan signal terminal, in a second stage, transmit a data signal from the data signal line to the fourth node under the control of the second scan signal terminal, and adjust the voltage of the first node according to the voltage variation of the fourth node. The compensation sub-circuit is electrically connected to a third scan signal terminal, the first node, and the second node, and is configured to electrically connect the first node and the second node under the control of the third scan signal terminal. The function sub-circuit is electrically connected to a control signal terminal, a first signal line, and a target node. The target node is one of the first node, the second node, and the third node. The function sub-circuit is configured to electrically connect the first signal line and the target node under the control of the control signal terminal. The test circuit includes a test control terminal, a first terminal, and a second terminal. The first terminal is electrically connected to one of the first node, the second node, the third node, and the first signal line. The second terminal is electrically connected to one of the data signal line, the first voltage signal line, and the fourth node. The test circuit is configured to electrically connect the first terminal and the second terminal under the control of the test signal terminal.

[0005] In some embodiments, the first terminal is electrically connected to one of the first node, the second node, and the third node. The second terminal is electrically connected to the fourth node or the data signal line.

[0006] In some embodiments, the display panel includes a display area and a peripheral area surrounding the display area, and the pixel circuit is located in the display area. The display panel includes a plurality of test circuits, one test circuit corresponds to one pixel circuit, and the plurality of test circuits are located in the display area.

[0007] In some embodiments, the first terminal is electrically connected to the first signal line, and the second terminal is electrically connected to the first voltage signal line or the data signal line.

[0008] In some embodiments, the display panel includes a display area and a peripheral area surrounding the display area, and the pixel circuit is located in the display area. The display panel includes one of the test circuits, and the test circuit is located in the peripheral area.

[0009] In some embodiments, the functional sub-circuit includes a light-emitting control sub-circuit and a first reset sub-circuit. The light-emitting control sub-circuit is electrically connected with a light-emitting control signal end, a second voltage signal line and the second node, and is configured to electrically connect the second voltage signal line with the second node under the control of the light-emitting control signal end. The first reset sub-circuit is electrically connected with a first reset signal end, a third voltage signal line and the third node, and is configured to electrically connect the third voltage signal line with the third node under the control of the first reset signal end. The first signal line includes the second voltage signal line and the third voltage signal line.

[0010] In some embodiments, the functional sub-circuit further includes a second reset sub-circuit. The second reset sub-circuit is electrically connected with the second reset signal end, a fourth voltage signal line and the first node, and is configured to electrically connect the fourth voltage signal line with the first node under the control of the second reset signal end. The first signal line further includes the fourth voltage signal line.

[0011] In some embodiments, the first end is electrically connected with the third node, and the second end is electrically connected with the data signal line.

[0012] In some embodiments, the light-emitting control sub-circuit includes a first transistor. The control electrode of the first transistor is electrically connected with the light-emitting control signal end, the first electrode is electrically connected with the second voltage signal line, and the second electrode is electrically connected with the second node. The first reset sub-circuit includes a second transistor. The control electrode of the second transistor is electrically connected with the first reset signal end, the first electrode is electrically connected with the third voltage signal line, and the second electrode is electrically connected with the third node. The second reset sub-circuit includes a third transistor. The control electrode of the third transistor is electrically connected with the second reset signal end, the first electrode is electrically connected with the fourth voltage signal line, and the second electrode is electrically connected with the first node.

[0013] In some embodiments, the test circuit includes a test transistor, the control electrode of the test transistor forms the test control end, one of the first electrode and the second electrode forms the first end, and the other forms the second end.

[0014] In some embodiments, the data processing sub-circuit includes a fourth transistor, a fifth transistor and a first capacitor. The control electrode of the fourth transistor is electrically connected with the first scan signal terminal, the first electrode is electrically connected with the first voltage signal line, and the second electrode is electrically connected with the fourth node. The control electrode of the fifth transistor is electrically connected with the second scan signal terminal, the first electrode is electrically connected with the data signal line, and the second electrode is electrically connected with the fourth node. One plate of the first capacitor is electrically connected with the fourth node, and the other plate is electrically connected with the first node. The compensation sub-circuit includes a sixth transistor; the control electrode of the sixth transistor is electrically connected with the third scan signal terminal, the first electrode is electrically connected with the first node, and the second electrode is electrically connected with the second node. The pixel circuit further includes a second capacitor; one plate of the second capacitor is electrically connected with the fourth node, and the other plate is electrically connected with the third node. The third node is configured to be electrically connected with the light emitting element.

[0015] In another aspect, a display device is provided. The display device includes the display panel as in any of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0017] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0018] FIG. 2 is a constituent structural diagram of a display device according to some embodiments;

[0019] FIG. 3 is a structural block diagram of a pixel circuit according to some embodiments;

[0020] FIG. 4 is an equivalent circuit diagram of a pixel circuit according to some embodiments;

[0021] FIG. 5 is another structural block diagram of a pixel circuit according to some embodiments;

[0022] FIG. 6 is yet another structural block diagram of a pixel circuit according to some embodiments;

[0023] FIG. 7 is yet another structural block diagram of a pixel circuit according to some embodiments;

[0024] FIG. 8 is another equivalent circuit diagram of a pixel circuit according to some embodiments;

[0025] Figure 9 is a structural block diagram of a test circuit according to some embodiments;

[0026] Figure 10 is a structural block diagram of a pixel circuit and a test circuit according to some embodiments;

[0027] Figure 11 is another structural block diagram of a test circuit according to some embodiments;

[0028] Figure 12 is an equivalent circuit diagram of a pixel circuit and a test circuit according to some embodiments;

[0029] Figure 13 is an equivalent circuit diagram of a pixel circuit and a test circuit according to some embodiments;

[0030] Figure 14 is an equivalent circuit diagram of a pixel circuit and a test circuit according to some embodiments;

[0031] Figure 15 is a timing control diagram of a detection method of a pixel circuit according to some embodiments;

[0032] Figure 16 is yet another structural block diagram of a test circuit according to some embodiments;

[0033] Figure 17 is an equivalent circuit diagram of a pixel circuit and a test circuit according to some embodiments;

[0034] Figure 18 is an equivalent circuit diagram of a pixel circuit and a test circuit according to some embodiments;

[0035] Figure 19 is an equivalent circuit diagram of a pixel circuit and a test circuit according to some embodiments. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It should be apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0037] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an open, inclusive sense as "including, but not limited to." As used throughout the description and the claims, the term "one embodiment," "some embodiments," "an exemplary embodiment," "an example," "a specific example," or "some examples" means that a particular feature, structure, material, or characteristic is included in at least one embodiment or example of the disclosure, but not necessarily all embodiments or examples. The above-mentioned terms do not necessarily refer to the same embodiment or example. Furthermore, the described features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0038] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description, and should not be construed as indicating or implying relative importance or implying that the indicated technical features are limited in number. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0039] In describing some embodiments, "coupled" and "connected", and variations thereof, can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" can also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0040] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0041] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0042] The use of "adapted to" or "configured to" herein is meant as open and inclusive language that does not foreclose devices adapted to or configured to perform additional tasks or steps.

[0043] Additionally, the use of "based on" is meant to mean "based, at least in part, on" which is open and inclusive language that does not foreclose additional based on items.

[0044] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0045] As used herein, "parallel," "perpendicular," "equal" includes the recited condition and conditions that approximate the recited condition within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can have an acceptable range of deviation, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also have an acceptable range of deviation, for example, within 5°. "Equal" includes absolute equality and near equality, where near equality can have an acceptable range of deviation, for example, where the difference between the two is less than or equal to 5% of either.

[0046] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate or intervening layers can also be present.

[0047] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples of exemplary embodiments. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0048] ​The transistor used in the pixel circuit provided by the embodiments of the present disclosure can be a thin film transistor (TFT), a metal oxide semiconductor (MOS), or other switching devices with the same characteristics. In the embodiments of the present disclosure, the transistor is exemplarily described as a thin film transistor. The thin film transistor can be a P-type transistor or an N-type transistor. The P-type transistor is turned on under a low voltage and is turned off under a high voltage. The N-type transistor is turned on under a high voltage and is turned off under a low voltage. In the embodiments of the present disclosure, the thin film transistor included in the pixel circuit is exemplarily described as a P-type transistor. The "effective voltage" is a voltage signal capable of turning on the corresponding thin film transistor.

[0049] The control electrode of each thin film transistor used in the pixel circuit is the gate of the thin film transistor, the first electrode is one of the source and the drain of the thin film transistor, and the second electrode is the other of the source and the drain of the thin film transistor. Since the source and the drain of the thin film transistor can be symmetrical in structure, the source and the drain of the thin film transistor can be indistinguishable in structure, that is, the first electrode and the second electrode of the thin film transistor in the embodiments of the present disclosure can be indistinguishable in structure. Exemplarily, the first electrode of the thin film transistor is the source, and the second electrode of the thin film transistor is the drain.

[0050] Each circuit node in the pixel circuit, such as the first node, the second node, and the like, is not an actual component, but represents a convergence point of relevant electrical connections in the circuit diagram, that is, the nodes are equivalent nodes formed by the convergence point of the relevant electrical connections in the circuit diagram.

[0051] Referring to FIG. 1, the embodiments of the present disclosure provide a display device 1000, which is a product with an image display function. Exemplarily, the display device 1000 can be any device that displays images, whether moving (for example, a video) or fixed (for example, a still image), and whether text or images.

[0052] The display device 1000 described above can be applied to various electronic devices, such as the display device 1000 can be a mobile phone, a wireless device, a personal data assistant (PDA), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a camcorder, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, an automobile display (e.g., an odometer display, etc.), a cockpit controller and / or display, a display of a camera view (e.g., a display of a rearview camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, a package and aesthetic structure (e.g., a display of an image for a piece of jewelry), etc. For example, as shown in FIG. 1, the display device 1000 can be a mobile phone.

[0053] From the perspective of the light-emitting type of the display device 1000, the display device 1000 described above can be a liquid crystal display (LCD), or the display device 1000 described above can also be an organic light-emitting diode display (OLED), a quantum dot light emitting diode display (QLED), or a micro light emitting diode display (MLED), etc. From the perspective of the form of the display device 1000, the display device 1000 described above can be a flat display device, a curved display device, or a foldable display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 described above can be rectangular, circular, or other shapes. In the following, some embodiments of the present disclosure are schematically described by taking an organic light-emitting diode display device as an example, which is rectangular and flat, but the embodiments of the present disclosure are not limited thereto, and any other display device can also be considered as long as the same technical idea is applied.

[0054] In some embodiments, referring to FIG. 2, the display device 1000 includes a display panel 1100 and a driving circuit board 1200. The driving circuit board 1200 may, for example, include a timing controller (TCON), a power management chip DC / DC, and an adjustable resistance voltage dividing circuit (generating Vcom) and other driving circuits. The driving circuit board 1200 may also include other circuit structures, which are not listed here. The driving circuit board 1200 is electrically connected to the display panel 1100, and is used to transmit control signals to the display panel 1100, thereby driving the display panel 1100 to realize image display. Of course, the structure of the display device 1000 is not limited to this. For example, the display device 1000 can also include at least one of a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize multiple different functions such as touch, shooting, video recording, or fingerprint recognition.

[0055] As shown in FIG. 2, the display panel 1100 can include a display area AA and a peripheral area BB disposed on at least one side of the display area AA. For example, the peripheral area BB can be disposed around the display area AA. The display area AA refers to the area of the display panel 1100 used for displaying images, and the peripheral area BB, also referred to as a non-display area, refers to the area of the display panel 1100 outside the display area AA.

[0056] The display panel 1100 includes a plurality of sub-pixels P disposed in the display area AA. The sub-pixel P refers to the smallest light-emitting unit in the display panel 1100. The plurality of sub-pixels P can include at least two sub-pixels that emit light of different colors. For example, the plurality of sub-pixels P include a red light sub-pixel that emits red light, a green light sub-pixel that emits green light, and a blue light sub-pixel that emits blue light, so that the display panel can realize color display.

[0057] The sub-pixel P includes a pixel circuit 100 and a light-emitting element EL. The pixel circuit 100 is electrically connected to the light-emitting element EL, and is configured to transmit a driving current to the light-emitting element EL to drive the light-emitting element EL to emit light. The plurality of pixel circuits 100 included in the plurality of sub-pixels P can be arranged in a plurality of rows and a plurality of columns. Each row of pixel circuits 100 includes a plurality of pixel circuits 100 arranged along a first direction X, and a plurality of rows of pixel circuits 100 are arranged along a second direction Y. Each column of pixel circuits 100 includes a plurality of pixel circuits 100 arranged along the second direction Y, and a plurality of columns of pixel circuits 100 are arranged along the first direction X. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular to each other.

[0058] The display panel 1100 can further include a gate driving circuit (Gate Driver On Array; GOA) and a source driving chip disposed in the peripheral area BB. The gate driving circuit can be connected with the pixel circuit 100 of a row of sub-pixels P through a scan signal line GL, and the source driving chip can be connected with the pixel circuit 100 of a column of sub-pixels P through a data signal line DL and transmit a data signal to the pixel circuit 100 of the column of sub-pixels P.

[0059] In some embodiments, in the case of the display device being an OLED display device or a QLED display device, the display panel can include an array substrate, and a light-emitting element and an encapsulation structure (encapsulation layer) stacked on the array substrate. Of course, the structure of the display panel is not limited thereto, for example, the display panel can further include other functional layers disposed on the side of the encapsulation structure away from the array substrate, which can be one or more of a touch functional layer, an anti-reflection layer, a hardening layer, and an anti-fingerprint layer, so that the display panel can realize corresponding functions, and the embodiments of the present disclosure do not make specific limitations on the types and numbers of the above-mentioned functional layers. The preparation process of the display panel can include an array process and a back-end process. The array substrate can be prepared in the array process, and the light-emitting element and the encapsulation structure can be formed on the array substrate in the back-end process. The pixel circuit 100 is disposed in the array substrate.

[0060] In some embodiments, the pixel circuit 100 described above can include a plurality of thin film transistors (Thin Film Transistor; TFT) and at least one capacitor Cst. For example, the pixel circuit 100 can be a “9T2C” circuit, a “7T1C” circuit, or an “8T1C” circuit, etc., and the embodiments of the present disclosure are not limited thereto, and any other pixel circuit can also be considered as long as the same technical idea is applied. Among them, “T” refers to a TFT, and the number before “T” refers to the number of TFTs; “C” refers to a capacitor Cst, and the number before “C” refers to the number of capacitors Cst.

[0061] Among them, the pixel circuit 100 usually includes at least one driving transistor DT, and the pixel circuit 100 usually includes at least a data writing process and a threshold voltage compensation process in one frame period. The threshold voltage compensation process is configured to compensate the threshold voltage Vth of the driving transistor to the control electrode of the driving transistor, so as to eliminate the influence of the threshold voltage Vth of the driving transistor on the driving current generated by the pixel circuit. The data writing process is configured to couple the data signal to the control electrode of the driving transistor, and then control the driving current size of the driving transistor through the data signal, and control the luminance (the size of the displayed gray scale) of the sub-pixel.

[0062] Generally, the data writing process and the threshold voltage compensation process of a pixel circuit are designed to be performed in the same time period, that is, the threshold voltage of the driving transistor is compensated to the control electrode of the driving transistor in synchronization with the process in which the data signal is written to the control electrode of the driving transistor. However, as the display panel gradually develops in the direction of large size, high pixel density (Pixels Per Inch; PPI), and high refresh rate, the 1H scanning time of a row of pixel circuits is getting shorter and shorter, and the time length of the data writing process is generally 1H, which leads to a shorter and shorter time length of the data writing process, that is, a shorter and shorter time length of the threshold voltage compensation process, which may result in insufficient compensation of the threshold voltage of the driving transistor, poor compensation effect, and influence on the driving current generated by the driving transistor, and thus the display quality of the display panel.

[0063] To solve the above technical problems, referring to FIGS. 3 and 4, the display panel provided by the embodiments of the present disclosure includes a pixel circuit 100, which includes a driving transistor DT, a data processing sub-circuit 10, and a compensation sub-circuit 20.

[0064] The control electrode of the driving transistor DT is electrically connected with a first node N1, the first electrode is electrically connected with a second node N2, and the second electrode is electrically connected with a third node N3. The driving transistor DT is configured to be electrically connected between the second node N2 and the third node N3 under the voltage control of the first node N1. Exemplarily, the driving transistor DT can be an N-type thin film transistor. One of the second node N2 and the third node N3 is configured to be coupled with the light emitting element EL, and the other is configured to be coupled with a power voltage signal line (such as a second voltage signal line VDD).

[0065] The data processing sub-circuit 10 is electrically connected with a first scan signal terminal G1, a second scan signal terminal G2, a data signal line DL, a first voltage signal line Vinit1, and the first node N1. The data processing sub-circuit 10 includes a fourth node N4. The data processing sub-circuit 10 is configured to, in a first stage, transmit a first voltage signal (denoted as: V1) from the first voltage signal line Vinit1 to the fourth node N4 under the control of the first scan signal terminal G1, in a second stage, transmit a data signal (denoted as: Vdata) from the data signal line DL to the fourth node N4 under the control of the second scan signal terminal G2, and adjust the voltage of the first node N1 according to the voltage variation (Vdata-V1) of the fourth node N4. In the embodiments of the present disclosure, “Vdata” is used to represent the data signal itself and the voltage value of the data signal.

[0066] The first voltage signal line Vinit1 is configured to be electrically connected with at least one column of pixel circuits 100, so as to transmit the first voltage signal to the at least one column of pixel circuits 100. For example, the first voltage signal line Vinit1 can be electrically connected with all the pixel circuits, that is, all the pixel circuits 100 included in the display panel are electrically connected with the same first signal line Vinit1. Of course, the first signal line Vinit1 does not necessarily have to be a line segment. For example, the first signal line Vinit1 can include a cross grid structure formed by at least two conductive layers.

[0067] The compensation sub-circuit 20 is electrically connected with the third scan signal terminal G3, the first node N1 and the second node N2, and is configured to electrically connect the first node N1 and the second node N2 under the control of the third scan signal terminal G3.

[0068] Based on the above pixel circuit 100, in the process that the data processing sub-circuit 10 transmits the data signal Vdata to the first node N1, the data signal Vdata can not pass through the compensation sub-circuit 20, and in the process that the first node N1 transmits the threshold voltage Vth of the driving transistor DT, the data processing sub-circuit 10 can also not be passed through. That is, the pixel circuit 100 is a pixel circuit 100 in which data writing and threshold voltage compensation are separated from each other, and the data processing sub-circuit 10 and the compensation sub-circuit 20 of the pixel circuit 100 are independent of each other and can work independently and without affecting each other. Based on this, the pixel circuit 100 can be configured to perform threshold voltage compensation and data signal writing on the control electrode (the first node N1) of the driving transistor DT in different time periods of the same display period (one frame time). That is, the data writing process and the threshold voltage compensation process of the pixel circuit 100 can be independent of each other and performed respectively. In this way, the length of the threshold voltage compensation process can not be limited to 1H, which is beneficial to improving the length of the threshold voltage compensation process, thereby fully compensating the threshold voltage Vth of the driving transistor DT to the control electrode of the driving transistor DT, and is beneficial to improving the accuracy of the driving current generated by the pixel circuit 100, thereby improving the display quality of the display panel.

[0069] In some embodiments, referring to FIG. 4, the data processing sub-circuit 10 includes a fourth transistor T4, a fifth transistor T5 and a first capacitor C1. The compensation sub-circuit 20 includes a sixth transistor T6. For example, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 can all be N-type thin film transistors.

[0070] The control electrode of the fourth transistor T4 is electrically connected with the first scan signal terminal G1, the first electrode is electrically connected with the first voltage signal line Vinit1, and the second electrode is electrically connected with the fourth node N4. The control electrode of the fifth transistor T5 is electrically connected with the second scan signal terminal G2, the first electrode is electrically connected with the data signal line DL, and the second electrode is electrically connected with the fourth node N4. One plate of the first capacitor C1 is electrically connected with the fourth node N4, and the other plate is electrically connected with the first node N1. The control electrode of the sixth transistor T6 is electrically connected with the third scan signal terminal G3, the first electrode is electrically connected with the first node N1, and the second electrode is electrically connected with the second node N2.

[0071] Exemplarily, one display period of the pixel circuit 100 can include a first stage (such as an initialization stage), a second stage (such as a data writing stage), and a third stage (such as a compensation stage).

[0072] In the first stage, the first scan signal terminal G1 transmits a working level (a voltage capable of driving the fourth transistor T4 to be turned on), the fourth transistor T4 is turned on under the control of the working level, and the first voltage signal transmitted on the first voltage signal line Vinit1 is transmitted to the fourth node N4 through the fourth transistor T4. The voltage of the fourth node N4 is V1.

[0073] In the third stage, a voltage signal (marked as VN1) can be transmitted to the first node N1 first, and the driving transistor DT is turned on under the voltage control of the first node N1. A voltage signal (marked as VN3) is transmitted to the third node N3. In addition, the third scan signal terminal G3 transmits a working level (a voltage signal capable of driving the sixth transistor T6 to be turned on), and the sixth transistor T6 is turned on under the control of the working level. In this way, the voltage VN3 of the third node N3 is transmitted to the first node N1 through the driving transistor DT and the sixth transistor T6 in turn, until the voltage of the first node N1 changes from VN1 to VN3+Vth, the voltage difference between the gate (the first node N1) and the source (the third node N3) of the driving transistor DT is (VN3+Vth)-VN3=Vth, at this time, the driving transistor DT is closed. That is, the third stage can achieve the purpose of coupling the threshold voltage Vth of the driving transistor DT to the control electrode (the first node N1) of the driving transistor DT.

[0074] In the second stage, the first scan signal terminal G1 transmits a non-working level (a voltage capable of driving the fourth transistor T4 to be off), and the fourth transistor T4 is off under the control of the non-working level. The second scan signal terminal G2 transmits a working level (a voltage capable of driving the fifth transistor T5 to be on), and the fifth transistor T5 is on under the control of the working level. The data signal Vdata transmitted on the data signal line DL is transmitted to the fourth node N4. The voltage of the fourth node N4 changes from V1 to Vdata, and the voltage variation of the fourth node N4 is (Vdata-V1). Under the bootstrap action of the first capacitor C1, the voltage of the first node N1 changes according to the voltage variation of the fourth node N4 to couple the data signal to the first node N1. Exemplarily, the voltage variation of the first node N1 can be the same as the voltage variation of the fourth node N4.

[0075] Exemplarily, based on the above control process of the pixel circuit, at the end of the third stage, the voltage of the first node N1 is VN3+Vth. In the second stage, the voltage variation of the fourth node N4 is Vdata-V1, and under the action of the first capacitor C1, the voltage of the first node N1 changes from VN3+Vth to VN3+Vth+(Vdata-V1).

[0076] The first stage and the third stage are both located before the second stage, the first stage and the third stage can be completely staggered or partially overlapped, and the respective time length and relative order of the first stage and the second stage can be arbitrarily adjusted as needed. Exemplarily, the time length of the third stage can be greater than that of the first stage, and the first stage is completely located in the third stage, which is conducive to improving the time length of the threshold voltage compensation process and improving the compensation effect of the driving transistor DT. Of course, the control timing of the pixel circuit is not limited thereto, as long as the same pixel circuit structure is adopted.

[0077] In some embodiments, referring to FIG. 5, the pixel circuit 100 further comprises at least one functional sub-circuit 30. The functional sub-circuit 30 is electrically connected with the control signal terminal GX, the first signal line LX and the target node. The target node is one of the first node N1, the second node N2 and the third node N3. Exemplarily, as shown in FIG. 5, the target node is taken as the third node N3 for example. The functional sub-circuit 30 is configured to electrically connect the first signal line LX with the target node under the control of the control signal terminal GX.

[0078] In some embodiments, referring to FIG. 6, the functional sub-circuit 30 includes a light emitting control sub-circuit 31 and a first reset sub-circuit 32. The light emitting control sub-circuit 31 is electrically connected with the light emitting control signal terminal EM, the second voltage signal line VDD and the second node N2, and is configured to electrically connect the second voltage signal line VDD and the second node N2 under the control of the light emitting control signal terminal EM. The first reset sub-circuit 32 is electrically connected with the first reset signal terminal G4, the third voltage signal line Vinit2 and the third node N3, and is configured to electrically connect the third voltage signal line Vinit2 and the third node N3 under the control of the first reset signal terminal G4. The first signal line LX includes the second voltage signal line VDD and the third voltage signal line Vinit2. As shown in FIG. 6, the third node N3 is also configured to be electrically connected with the light emitting element EL.

[0079] The first signal line LX is configured to be electrically connected with at least one column of pixel circuits 100, so as to transmit voltage signals to the at least one column of pixel circuits 100. As an example, the first signal line LX can be electrically connected with all the pixel circuits, i.e., all the pixel circuits 100 included in the display panel are electrically connected with the same first signal line LX. Of course, the first signal line LX does not necessarily have to be a line segment, for example, the first signal line LX can include a mesh structure formed by at least two layers of conductive layers intersecting with each other.

[0080] In some embodiments, in the third stage of a display period, the voltage signal can be transmitted to the third node N3 through the first reset sub-circuit 32. For example, in the third stage, the first reset sub-circuit 32 electrically connects the third voltage signal line Vinit2 and the third node N3 under the control of the first reset signal terminal G4, and the voltage signal (marked as V3) transmitted by the third voltage signal line Vinit2 is transmitted to the third node N3, at which time the voltage (marked as VN3 above) of the third node N3 is V3.

[0081] As an example, a display period can also include a light emitting stage and a non-light emitting stage, and the above-mentioned first stage, second stage and third stage can all be located in the non-light emitting stage. In the light emitting stage, the light emitting control sub-circuit 31 electrically connects the second voltage signal line VDD and the second node N2 under the control of the light emitting control signal terminal EM, and the driving transistor DT is turned on under the voltage difference between the first node N1 and the second node N2 and generates a driving current, which flows through the third node N3 and is transmitted to the light emitting element EL, so as to drive the light emitting element EL to emit light.

[0082] In some embodiments, referring to FIG. 7, the functional sub-circuit 30 can further include a second reset sub-circuit 33. The second reset sub-circuit 33 is electrically connected with the second reset signal terminal G5, the fourth voltage signal line Vref and the first node N1, and is configured to electrically connect the fourth voltage signal line Vref with the first node N1 under the control of the second reset signal terminal G5.

[0083] Exemplarily, one display period can further include a fourth stage (an initialization stage), in which the second reset sub-circuit 33 electrically connects the fourth voltage signal line Vref with the first node N1 under the control of the second reset signal terminal G5, so as to transmit the fourth voltage signal (labeled as V4) transmitted by the fourth voltage signal line Vref to the first node N1, to initialize the voltage of the first node N1. For example, in the third stage described above, the fourth voltage signal can be transmitted to the first node N1 by the second reset sub-circuit 33, so as to control the driving transistor DT to be turned on.

[0084] In some embodiments, referring to FIG. 8, the light emitting control sub-circuit 31 includes a first transistor T1, the first reset sub-circuit 32 includes a second transistor T2, and the second reset sub-circuit 33 includes a third transistor T3. Exemplarily, the first transistor T1, the second transistor T2 and the third transistor T3 can be N-type thin film transistors.

[0085] In some embodiments, referring to FIG. 8, the light emitting control sub-circuit 31 includes a first transistor T1, the first reset sub-circuit 32 includes a second transistor T2, and the second reset sub-circuit 33 includes a third transistor T3. Exemplarily, the first transistor T1, the second transistor T2 and the third transistor T3 can be N-type thin film transistors.

[0086] In some embodiments, continuing to refer to FIG. 8, the pixel circuit 100 further includes a second capacitor C2, one plate of the second capacitor C2 is electrically connected with the fourth node N4, and the other plate is electrically connected with the third node N3.

[0087] Based on the pixel circuit 100 (as shown in FIGS. 3-8) structure, since the data processing sub-circuit 10 and the compensation sub-circuit 20 are independent of each other, and the threshold voltage Vth of the driving transistor DT cannot be transmitted to the data signal line DL through the compensation sub-circuit 20 and the data processing sub-circuit 10. After the array substrate is prepared (after the pixel circuit 100 is formed), the driving transistor DT cannot be detected (such as whether the threshold voltage Vth of the driving transistor is in the preset range) through the structure of the pixel circuit 100 itself, so that the array substrate that does not meet the conditions (defective) cannot be excluded, and the array substrate with problems will still be subjected to subsequent back-end processes, which will cause waste of materials and processes used in the back-end processes, and increase the preparation cost of the display panel.

[0088] In order to solve the above technical problems, referring to FIGS. 9 and 10, the display panel of the embodiment of the present disclosure further comprises a test circuit 200. The test circuit 200 comprises a test control end AT, a first end 21 and a second end 22. The first end 21 is electrically connected with one of the first node N1, the second node N2, the third node N3 and the first signal line LX. The second end 22 is electrically connected with one of the data signal line DL, the first voltage signal line Vinit1 and the fourth node N4. The test circuit 200 is configured to electrically connect the first end 21 and the second end 22 under the control of the test signal end AT. Wherein, FIG. 10 only exemplarily shows one possible connection mode, which should be understood as an exemplary description of the present application, rather than a limitation of the present application.

[0089] In some embodiments, the test circuit 200 is further configured to detect the driving transistor DT. Illustratively, when it is required to detect the array substrate, the test circuit 200 electrically connects the first end 21 and the second end 22 under the control of the test signal end AT, thereby electrically connecting one of the first node N1, the second node N2, the third node N3 (the one connected with the first end 21) and one of the data signal line DL, the first voltage signal line Vinit1 and the fourth node N4 (the one connected with the second end 22), and controls the pixel circuit 100 to make the pixel circuit 100 generate a detection current flowing through the driving transistor DT and capable of being transmitted to the first end 21, then collects the detection current through the data signal line DL or the first voltage signal line Vinit1, and then calculates an ideal current in combination with the voltage applied to each circuit node of the pixel circuit 100, compares the detection current with the ideal current to determine whether the driving transistor DT meets the use condition. If the driving transistor DT meets the use condition, it is considered that the array substrate meets the use requirement, and the array substrate is continuously prepared to form a display panel. If the driving transistor DT does not meet the use condition, it is considered that the array substrate does not meet the use requirement, and the array substrate is subjected to other processing (including but not limited to repair, recycling or scrapping), so as to avoid the array substrate not meeting the condition to enter the later process, reduce the material and process waste of the array substrate not meeting the condition in the later process, and reduce the preparation cost of the display panel.

[0090] Illustratively, the pixel circuit 100 and the test circuit 200 shown in FIG. 10 are taken as examples to exemplarily describe the embodiments of the present disclosure. When it is required to detect the array substrate, a voltage can be transmitted to the first node N1 and the second node N2 respectively to turn on the driving transistor DT, and make the driving transistor DT generate a driving current transmitted to the third node N3, the size of the driving current being related to the actual threshold voltage Vth of the driving transistor DT. The test circuit 200 connects the data signal line DL with the third node N3 under the control of the test signal end AT, so that the driving current can be collected through the data signal line DL. In addition, according to the design condition of the driving transistor DT (including but not limited to the material of the channel structure and the width-length ratio of the channel structure), a design threshold voltage Vth' of the driving transistor DT can be obtained, and according to the voltage value transmitted to the first node N1 and the second node N2 and the design threshold voltage Vth', an ideal current can be obtained. The actual collected driving current is compared with the ideal current. If the driving current deviates from the ideal current by a certain preset range, it is considered that the threshold voltage Vth of the driving transistor DT does not meet the use condition, otherwise it is considered that the threshold voltage Vth of the driving transistor DT meets the use condition.

[0091] The display panel provided by the embodiments of the present disclosure includes the test circuit 200, so that the driving transistor DT of the pixel circuit 100 in the array substrate can be directly detected by the test circuit 200 after the array substrate including the pixel circuit 100 and the test circuit 200 is prepared in the front-end process (array process), and whether the driving transistor DT meets the design requirements is detected, and then the array substrate meeting the conditions is screened out for further preparation of the display panel 1100, and the array substrate not meeting the conditions is screened out for other processing (including but not limited to repair, recycling or scrapping), so as to avoid the array substrate not meeting the conditions from entering the back-end process, reduce the material and process waste of the array substrate not meeting the conditions in the back-end process, and reduce the preparation cost of the display panel.

[0092] In some embodiments, referring to FIGS. 10 and 11, the first end 21 of the test circuit 200 is electrically connected to one of the first node N1, the second node N2 and the third node N3, and the second end 22 of the test circuit 200 is electrically connected to the fourth node N4 or the data signal line DL. At this time, one test circuit 200 can be correspondingly arranged for each pixel circuit 100, which is beneficial to improve the structural uniformity of the array substrate, and the driving transistor DT of each pixel circuit 100 can be accurately detected by the plurality of test circuits 200.

[0093] In some embodiments, referring to FIGS. 10 to 14, in the case that the first end 21 of the test circuit 200 is electrically connected to one of the first node N1, the second node N2 and the third node N3, the display panel can include a plurality of test circuits 200, the plurality of test circuits 200 are located in the display area, and one test circuit 200 is correspondingly connected to one pixel circuit 100, so that the driving transistor DT of each pixel circuit 100 can be accurately detected by the plurality of test circuits 200.

[0094] In some embodiments, referring to FIGS. 12, 13 and 14, the test circuit 200 includes a test transistor T20, the control electrode of the test transistor T20 forms the test control end AT, one of the first electrode and the second electrode forms the first end 21, and the other forms the second end 22.

[0095] In the following, some embodiments of the present disclosure are exemplarily described by taking the pixel circuit 100 with the structure shown in FIG. 8 as an example. Of course, the embodiments of the present disclosure are not limited thereto, and the pixel circuit 100 can consider other arbitrary suitable circuits as long as the same technical idea is adopted.

[0096] Referring to FIG. 12, in one example, the first end 21 of the test transistor T20 can be electrically connected to the third node N3, and the second end 22 can be electrically connected to the fourth node N4.

[0097] Referring to FIG. 13, in one example, the first terminal 21 of the test transistor T20 can be electrically connected with the first node N1, and the second terminal 22 can be electrically connected with the data signal line DL.

[0098] Referring to FIG. 14, in one example, the first terminal 21 of the test transistor T20 can be electrically connected with the second node N2, and the second terminal 22 can be electrically connected with the data signal line DL.

[0099] Embodiments of the present disclosure are not limited thereto, and the connection relationship of the test transistor T20 can be adjusted as needed. For example, when the first terminal 21 of the test transistor T20 is electrically connected with the third node N3, the second terminal 22 can also be electrically connected with the data signal line DL. When the first terminal 21 of the test transistor T20 is electrically connected with the first node N1 or the second node N2, the second terminal 22 can also be electrically connected with the fourth node N4.

[0100] In one example, taking the pixel circuit 100 and the test circuit 200 shown in FIG. 12 as an example, referring to FIG. 15, the detection process D of the pixel circuit 100 can include: the second reset signal terminal G5 transmits a working level, and the third transistor T3 is turned on; the third scan signal terminal G3 transmits a working level, and the sixth transistor T6 is turned on; the test signal terminal AT transmits a working level, and the test transistor T20 is turned on; and the second scan signal terminal G2 transmits a working level, and the fifth transistor T5 is turned on. At the same time, the fourth voltage signal V4 is transmitted to the first node N1 through the fourth voltage signal line Vref, the driving transistor DT is turned on under the control of the fourth voltage signal V4, the fourth voltage signal V4 is transmitted to the data signal line DL through the third transistor T3, the sixth transistor T6, the driving transistor DT, the test transistor T20 and the fifth transistor T5 in turn, and a detection current is formed. In this way, the above detection current can be collected through the data signal line DL.

[0101] In another example, when the pixel circuit 100 and the test circuit 200 are in the connection relationship shown in FIG. 13, different from the above example, the detection process of the pixel circuit 100 can include: the emission control signal end EM transmits a working level, the first transistor T1 is turned on; the second reset signal end G5 transmits a non-working level, the third transistor T3 is turned off. And the voltage signal is transmitted through the second voltage signal line VDD line second node N2. The control process of the sixth transistor T6, the test transistor T20 and the fifth transistor T5 in the detection process is the same as the above example, which will not be described here. The second voltage signal is transmitted to the first node N1 through the first transistor T1 and the sixth transistor T6 in turn, so as to turn on the driving transistor DT. At the same time, the second voltage signal is also transmitted to the data signal line DL through the driving transistor DT, the test transistor T20 and the fifth transistor T5, and a detection current is formed. In this way, the above detection current can be collected through the data signal line DL.

[0102] Referring to FIG. 13, in the case that the first end 21 of the test transistor T20 is electrically connected with the first node N1, and the second end 22 is electrically connected with the data signal line DL, the detection process of the pixel circuit 100 can include: the sixth transistor T6 is turned on to electrically connect the first node N1 with the second node N2. The first transistor T1 is turned on, and the second voltage signal line VDD transmits the second voltage signal to the first node N1 through the first transistor T1 and the sixth transistor T6 in turn, so as to turn on the driving transistor DT; or, the third transistor T3 is turned on, and the fourth voltage signal line Vref transmits the fourth voltage signal to the first node N1, so as to turn on the driving transistor DT. The second transistor T2 is turned on, the third voltage signal line Vinit2 transmits the third voltage signal to the third node N3 through the second transistor T2, and the driving transistor DT generates a detection current under the voltage control of the first node N1 and the third node N3. The detection current is transmitted to the data signal line DL through the driving transistor DT, the sixth transistor T6 and the test transistor T20 in turn. In this way, the above detection current can be collected through the data signal line DL.

[0103] Referring to FIG. 14, in the case that the first end 21 of the test transistor T20 is electrically connected with the second node N2, and the second end 22 is electrically connected with the data signal line DL, the detection process of the pixel circuit 100 can include: the third transistor T3 is turned on, and the fourth voltage signal line Vref transmits the fourth voltage signal to the first node N1, so as to turn on the driving transistor DT. The second transistor T2 is turned on, the third voltage signal line Vinit2 transmits the third voltage signal to the third node N3 through the second transistor T2, and the driving transistor DT generates a detection current under the voltage control of the first node N1 and the third node N3. The detection current is transmitted to the data signal line DL through the driving transistor DT and the test transistor T20 in turn. In this way, the above detection current can be collected through the data signal line DL.

[0104] It can be understood that the detection method of the pixel circuit 100 of the embodiments of the present disclosure is not limited to the above-mentioned multiple embodiments, and other any suitable manner can also be considered as long as the same technical idea is adopted.

[0105] In some embodiments, referring to FIGS. 16-19, the first end 21 of the test circuit 200 can be electrically connected with the first signal line LX, and the second end 22 of the test circuit 200 can be electrically connected with the first voltage signal line Vinit1 or the data signal line DL. At this time, the multiple pixel circuits 100 can share one test circuit 200, which is conducive to reducing the number of test circuits 200 and simplifying the structure of the test substrate 400, and thus simplifying the preparation difficulty and preparation cost of the test substrate 400.

[0106] In one embodiment, in the case that the first end 21 of the test circuit 200 can be electrically connected with the first signal line LX, the display panel can include one test circuit 200, and the test circuit 200 is arranged in the peripheral area of the display panel. In this way, not only can the number of test circuits 200 be greatly reduced, the structure of the test substrate 400 be simplified, and thus the preparation difficulty and preparation cost of the test substrate 400 be simplified, but also the test circuit 200 can be arranged in the peripheral area of the display panel, which is conducive to reducing the space of the display area occupied by the test circuit 200 and improving the pixel density of the display panel. In FIGS. 17-19, the test circuit 200 is drawn in the position of the pixel circuit 100 for the convenience of showing the connection relationship between the pixel circuit 100 and the test circuit 200, but it should be understood that the first signal line LX, the data signal line DL and the first voltage signal line Vinit1 can all extend to the peripheral area, and the test circuit 200 can actually be arranged in the peripheral area of the display panel.

[0107] In the following, some embodiments of the present application are exemplarily described taking the pixel circuit 100 with the structure shown in FIG. 8 as an example, of course, the embodiments of the present disclosure are not limited thereto, and the pixel circuit 100 can consider other any suitable circuit as long as the same technical idea is adopted. The functional sub-circuit 30 includes the light-emitting control sub-circuit 31, the first reset sub-circuit 32 and the second reset sub-circuit 33, and the first signal line LX includes the second voltage signal line VDD, the third voltage signal line Vinit2 and the fourth voltage signal line Vref.

[0108] Referring to FIG. 17, in one example, the first end 21 of the test transistor T20 can be electrically connected with the second voltage signal line VDD, and the second end 22 can be electrically connected with the first voltage signal line Vinit1.

[0109] Referring to FIG. 18, in one example, the first terminal 21 of the test transistor T20 can be electrically connected with the third voltage signal line Vinit2, and the second terminal 22 can be electrically connected with the data signal line DL.

[0110] Referring to FIG. 19, in one example, the first terminal 21 of the test transistor T20 can be electrically connected with the fourth voltage signal line Vref, and the second terminal 22 can be electrically connected with the data signal line DL.

[0111] Embodiments of the present disclosure are not limited to the three examples shown in FIGS. 17-19, and the connection relationship of the test transistor T20 can be adjusted as needed. For example, when the first terminal 21 of the test transistor T20 is electrically connected with the second voltage signal line VDD, the second terminal 22 can also be electrically connected with the data signal line DL. When the first terminal 21 of the test transistor T20 is electrically connected with the third voltage signal line Vinit2 or the fourth voltage signal line Vref, the second terminal 22 can also be electrically connected with the first voltage signal line Vinit1.

[0112] In one example, taking the pixel circuit 100 and the test circuit 200 shown in FIG. 17 as an example, the detection process of the pixel circuit 100 can include: the second reset signal terminal G5 transmits a working level, and the third transistor T3 is turned on; the fourth voltage signal line Vref transmits the fourth voltage signal V4 to the first node N1 through the third transistor T3. The first reset signal terminal G4 transmits a working level, and the second transistor T2 is turned on. The third voltage signal line Vinit2 transmits the third voltage signal to the third node N3 through the second transistor T2, and the drive transistor DT generates a detection current under the voltage control of the first node N1 and the third node N3. The light-emitting control signal terminal EM transmits a working level, and the first transistor T1 is turned on. The test signal terminal AT transmits a working level, and the test transistor T20 is turned on. The above detection current is transmitted to the first voltage signal line Vinit1 through the drive transistor DT, the first transistor T1 and the test transistor T20 in turn. In this way, the above detection current can be collected through the first voltage signal line Vinit1.

[0113] In another example, in the case that the pixel circuit 100 and the test circuit 200 are connected in the manner shown in FIG. 18, the detection process of the pixel circuit 100 can include that one of the first transistor T1 and the third transistor T3 is turned on, and the sixth transistor T6 is turned on, so that the second voltage signal line VDD or the fourth voltage signal line Vref can transmit a voltage signal to the first node N1, thereby turning on the driving transistor DT. And the voltage signal can be transmitted to the third node N3 through the driving transistor DT and form a detection current. The second transistor T2 and the test transistor T20 are both turned on, and the detection current is transmitted to the data signal line DL in turn through the second transistor T2 and the test transistor T20. In this way, the detection current can be collected through the data signal line DL. Wherein, the data signal line DL is provided with a binding pin (Pin) in the peripheral area, compared with collecting the detection current through the first voltage signal line Vinit1, collecting the detection current through the data signal line DL can simplify the structure of the display panel, that is, the change of the structure of the display panel can be reduced.

[0114] In another example, in the case that the pixel circuit 100 and the test circuit 200 are connected in the manner shown in FIG. 19, the detection process of the pixel circuit 100 can include that the third transistor T3 is turned on, and the fourth voltage signal line Vref can transmit a voltage signal to the first node N1. At this time, the fourth voltage signal line Vref can transmit a constant voltage signal. The sixth transistor T6 is turned on to turn on the first node N1 and the second node N2. The second transistor T2 is turned on, and the third voltage signal line Vinit2 transmits a third voltage signal to the third node N3 through the second transistor T2, and the driving transistor DT generates a detection current under the voltage control of the first node N1 and the third node N3. In addition, the test transistor T20 is also in the on state, and the detection current is transmitted to the data signal line DL in turn through the driving transistor DT, the sixth transistor T6, the third transistor T3 and the test transistor T20.

[0115] It should be noted that, referring to FIGS. 17-19, in the case that the first end 21 of the test circuit 200 can be electrically connected with the first signal line LX, since the display panel generally adopts a row scanning driving mode, when detecting the pixel circuit 100, a row of pixel circuits will transmit detection currents to the first signal line LX at the same time. At this time, whether the driving transistor of a row of pixel circuits is abnormal can be detected synchronously, for example, in the case that the difference between the detected detection current and the ideal current is greater than a preset value, it can be considered that the driving transistor of at least one pixel circuit in a row of pixel circuits does not meet the condition, and then the array substrate is subjected to other processing.

[0116] The protection scope of the present application is not limited to the above-mentioned embodiments, and the above-mentioned embodiments can be implemented alone or combined in a reasonable manner. Alternatively, the present application can also include other embodiments, for example, the first end 21 of the test circuit 200 is electrically connected to one of the first node N1, the second node N2 and the third node N3, and the second end 22 is electrically connected to the first voltage signal line Vinit1. The embodiments of the present application do not exemplify one by one.

[0117] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who thinks of changes or replacements within the technical scope disclosed by the present disclosure should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel comprising a plurality of pixel circuits and at least one test circuit; wherein, the pixel circuit comprises: a driving transistor, a control electrode of the driving transistor being electrically connected with a first node, a first electrode being electrically connected with a second node, and a second electrode being electrically connected with a third node; the driving transistor is configured to electrically connect between the second node and the third node under the voltage control of the first node; a data processing sub-circuit, electrically connected with a first scan signal terminal, a second scan signal terminal, a data signal line, a first voltage signal line, and the first node, the data processing sub-circuit comprising a fourth node; the data processing sub-circuit is configured to, in a first stage, transmit a first voltage signal from the first voltage signal line to the fourth node under the control of the first scan signal terminal, and in a second stage, transmit a data signal from the data signal line to the fourth node under the control of the second scan signal terminal, and adjust the voltage of the first node according to the voltage variation of the fourth node; a compensation sub-circuit, electrically connected with a third scan signal terminal, the first node, and the second node, and configured to electrically connect the first node and the second node under the control of the third scan signal terminal; at least one function sub-circuit, electrically connected with a control signal terminal, a first signal line, and a target node; the target node being one of the first node, the second node, and the third node; the function sub-circuit is configured to electrically connect the first signal line and the target node under the control of the control signal terminal; the test circuit comprises a test control terminal, a first terminal, and a second terminal; the first terminal is electrically connected with one of the first node, the second node, the third node, and the first signal line; the second terminal is electrically connected with one of the data signal line, the first voltage signal line, and the fourth node; the test circuit is configured to electrically connect the first terminal and the second terminal under the control of the test signal terminal.

2. The display panel of claim 1, wherein, the first terminal is electrically connected with one of the first node, the second node, and the third node; and the second terminal is electrically connected with the fourth node or the data signal line.

3. The display panel of claim 2, wherein, the display panel comprises a display area and a peripheral area surrounding the display area, and the pixel circuit is located in the display area; the display panel comprises a plurality of the test circuits, one of the test circuits corresponding to one pixel circuit, and the plurality of the test circuits are located in the display area.

4. The display panel of claim 1, wherein, the first terminal is electrically connected with the first signal line, and the second terminal is electrically connected with the first voltage signal line or the data signal line.

5. The display panel of claim 4, wherein, the display panel comprises a display area and a peripheral area surrounding the display area, and the pixel circuit is located in the display area. The display panel comprises one test circuit, and the test circuit is located in the peripheral area.

6. The display panel according to any one of claims 1 to 5, wherein The functional sub-circuit comprises: an emission control sub-circuit, which is electrically connected with the emission control signal end, the second voltage signal line and the second node, and is configured to electrically connect the second voltage signal line with the second node under the control of the emission control signal end; a first reset sub-circuit, which is electrically connected with the first reset signal end, the third voltage signal line and the third node, and is configured to electrically connect the third voltage signal line with the third node under the control of the first reset signal end; wherein the first signal line comprises the second voltage signal line and the third voltage signal line.

7. The display panel according to claim 6, wherein, the functional sub-circuit further comprises a second reset sub-circuit, which is electrically connected with the second reset signal end, the fourth voltage signal line and the first node, and is configured to electrically connect the fourth voltage signal line with the first node under the control of the second reset signal end; the first signal line further comprises the fourth voltage signal line.

8. The display panel according to claim 6 or 7, wherein, the first end is electrically connected with the third node, and the second end is electrically connected with the data signal line.

9. The display panel according to claim 7, wherein, the emission control sub-circuit comprises a first transistor, a control electrode of the first transistor is electrically connected with the emission control signal end, a first electrode is electrically connected with the second voltage signal line, and a second electrode is electrically connected with the second node; the first reset sub-circuit comprises a second transistor, a control electrode of the second transistor is electrically connected with the first reset signal end, a first electrode is electrically connected with the third voltage signal line, and a second electrode is electrically connected with the third node; the second reset sub-circuit comprises a third transistor, a control electrode of the third transistor is electrically connected with the second reset signal end, a first electrode is electrically connected with the fourth voltage signal line, and a second electrode is electrically connected with the first node.

10. The display panel according to any one of claims 1 to 9, wherein, the test circuit comprises a test transistor, a control electrode of the test transistor forms the test control end, one of a first electrode and a second electrode forms the first end, and the other forms the second end.

11. The display panel according to any one of claims 1 to 10, wherein, the data processing sub-circuit comprises a fourth transistor, a fifth transistor and a first capacitor, a control electrode of the fourth transistor is electrically connected with the first scan signal end, a first electrode is electrically connected with the first voltage signal line, and a second electrode is electrically connected with the fourth node; a control electrode of the fifth transistor is electrically connected with the second scan signal end, a first electrode is electrically connected with the data signal line, and a second electrode is electrically connected with the fourth node; one plate of the first capacitor is electrically connected with the fourth node, and the other plate is electrically connected with the first node; The compensation sub-circuit comprises a sixth transistor, a control electrode of the sixth transistor is electrically connected with a third scan signal end, a first electrode is electrically connected with the first node, and a second electrode is electrically connected with the second node; The pixel circuit further comprises a second capacitor, one plate of the second capacitor is electrically connected with the fourth node, and the other plate is electrically connected with the third node; The third node is configured to be electrically connected with a light emitting element.

12. A display device, comprising: The display panel according to any one of claims 1-11; A driving circuit board electrically connected with the display panel and configured to transmit a control signal to the display panel.

Images