Pixel circuit and display device

Abstract

The present disclosure provides a pixel circuit and a display device. The pixel circuit comprises a driving circuit, a compensation control circuit, a first energy storage circuit, a first control circuit, and a second control circuit. Under the control of the potential of a control node, the compensation control circuit controls a first node to be connected to a third node. A first end of the first energy storage circuit is electrically connected to the control node; and a second end of the first energy storage circuit is electrically connected to a first gate driving end. Under the control of a first control signal, the first control circuit controls the first node to be connected to the control node. Under the control of a second control signal, the second control circuit controls the third node to be connected to the first gate driving end. In the present disclosure, threshold voltage compensation is continuously performed on threshold voltage-sensitive transistors, thereby improving image quality and special requirements.

Description

Pixel circuit and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410831312.0, filed on June 25, 2024, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit and a display device. BACKGROUND

[0004] In the related art, with the continuous updating and iteration of the OLED (Organic Light Emitting Diode) industry, pixel circuits suitable for various new functions have also been proposed. In the related LTPO (Low Temperature Polycrystalline Oxide) pixel architecture, the compensation transistor connected to the gate of the driving transistor is an Oxide TFT (Thin Film Transistor), but the PBTS (Positive Bias Temperature Stress) stability of the Oxide TFT is poor, and the Vth (Vth is the threshold voltage) sensitivity of the compensation transistor is poor, which often causes reliability horizontal lines, poor HRD (Hybird Refresh Display) split screen brightness and other defects. SUMMARY

[0005] The main purpose of the present disclosure is to provide a pixel circuit and a display device, which solves the problem that the prior art cannot provide a pixel circuit for threshold voltage compensation of an oxide transistor, cannot continue threshold voltage compensation for a threshold voltage sensitive transistor, and cannot improve image quality and special requirements.

[0006] In one aspect, the embodiments of the present disclosure provide a pixel circuit, comprising a driving circuit, a compensation control circuit, a first energy storage circuit, a first control circuit and a second control circuit;

[0007] The control end of the driving circuit is electrically connected with a first node, the first end of the driving circuit is electrically connected with a second node, the second end of the driving circuit is electrically connected with a third node, and the driving circuit is used for generating a driving current under the control of the potential of the first node;

[0008] The compensation control circuit is electrically connected with a control node, the first node and the third node respectively, and is used for controlling the communication between the first node and the third node under the control of the potential of the control node;

[0009] A first end of the first energy storage circuit is electrically connected with the control node, and a second end of the first energy storage circuit is electrically connected with the first gate driving end, and the first energy storage circuit is used for storing electric energy.

[0010] The first control circuit is electrically connected with the first control end, the first node and the control node respectively, and is used for controlling the communication between the first node and the control node under the control of a first control signal provided by the first control end.

[0011] The second control circuit is electrically connected with the second control end, the third node and the first gate driving end respectively, and is used for controlling the communication between the third node and the first gate driving end under the control of a second control signal provided by the second control end.

[0012] Optionally, the first control end and the second control end are both first scan ends.

[0013] Optionally, the first control end is a first scan end, and the second control end is a second scan end.

[0014] Optionally, the pixel circuit further comprises a first initialization circuit.

[0015] The first initialization circuit is electrically connected with the first scan end, a first initial voltage end and the control node respectively, and is used for writing a first initial voltage provided by the first initial voltage end into the control node under the control of a first scan signal provided by the first scan end.

[0016] The first control end and the second control end are second scan ends.

[0017] Optionally, the transistor included in the compensation control circuit is an oxide transistor, and the transistor included in the first control circuit and the transistor included in the second control circuit are low-temperature polysilicon transistors.

[0018] Optionally, the pixel circuit further comprises a data writing circuit and a second energy storage circuit.

[0019] The data writing circuit is electrically connected with a second gate driving end, a data line and the second node respectively, and is used for writing a data voltage provided by the data line into the second node under the control of a second gate driving signal provided by the second gate driving end.

[0020] The second energy storage circuit is electrically connected with the first node, and is used for maintaining the potential of the first node.

[0021] Optionally, the pixel circuit further comprises a light emitting element, a first light emitting control circuit and a second light emitting control circuit.

[0022] The first light emitting control circuit is electrically connected with the light emitting control end, the power voltage end and the second node respectively, and is configured to control the communication between the power voltage end and the second node under the control of the light emitting control signal provided by the light emitting control end.

[0023] The second light emitting control circuit is electrically connected with the light emitting control end, the third node and the first pole of the light emitting element respectively, and is configured to control the communication between the third node and the first pole of the light emitting element under the control of the light emitting control signal.

[0024] The second pole of the light emitting element is electrically connected with the first voltage end.

[0025] Optionally, the pixel circuit according to any one of the embodiments of the present disclosure further comprises a second initialization circuit.

[0026] The second initialization circuit is electrically connected with the first reset end, the first initial voltage end and the third node respectively, and is configured to write the first initial voltage provided by the first initial voltage end into the third node under the control of the first reset control signal provided by the first reset end.

[0027] Optionally, the pixel circuit according to any one of the embodiments of the present disclosure further comprises a second initialization circuit.

[0028] The second initialization circuit is electrically connected with the first reset end, the first initial voltage end and the first node respectively, and is configured to write the first initial voltage provided by the first initial voltage end into the first node under the control of the first reset control signal provided by the first reset end.

[0029] Optionally, the pixel circuit according to any one of the embodiments of the present disclosure further comprises a third initialization circuit.

[0030] The third initialization circuit is electrically connected with the second reset end, the second initial voltage end and the first pole of the light emitting element respectively, and is configured to write the second initial voltage provided by the second initial voltage end into the first pole of the light emitting element under the control of the second reset control signal provided by the second reset end.

[0031] Optionally, the pixel circuit according to any one of the embodiments of the present disclosure further comprises a fourth initialization circuit.

[0032] The fourth initialization circuit is electrically connected with the second reset end, the third initial voltage end and the second node respectively, and is configured to write the third initial voltage provided by the third initial voltage end into the second node under the control of the second reset control signal provided by the second reset end.

[0033] Optionally, the pixel circuit further comprises a third energy storage circuit, a third control circuit and a fourth control circuit.

[0034] The first end of the third energy storage circuit is electrically connected with the intermediate node, and the second end of the third energy storage circuit is electrically connected with the first reset end, and the third energy storage circuit is used for storing electric energy.

[0035] The third control circuit is electrically connected with the first control end, the first initial voltage end and the intermediate node respectively, and is used for controlling the first initial voltage end and the intermediate node to be in communication under the control of the first control signal.

[0036] The fourth control circuit is electrically connected with the second control end, the first node and the first reset end respectively, and is used for controlling the first node and the first reset end to be in communication under the control of the second control signal.

[0037] Optionally, the driving circuit comprises a driving transistor, the compensation control circuit comprises a first transistor, and the first energy storage circuit comprises a first capacitor; the first control circuit comprises a second transistor, and the second control circuit comprises a third transistor.

[0038] The gate of the driving transistor is electrically connected with the first node, the first pole of the driving transistor is electrically connected with the second node, and the second pole of the driving transistor is electrically connected with the third node.

[0039] The gate of the first transistor is electrically connected with the control node, the first pole of the first transistor is electrically connected with the first node, and the second pole of the first transistor is electrically connected with the third node.

[0040] The first end of the first capacitor is electrically connected with the control node, and the second end of the first capacitor is electrically connected with the first gate driving end.

[0041] The gate of the second transistor is electrically connected with the first control end, the first pole of the second transistor is electrically connected with the first node, and the second pole of the second transistor is electrically connected with the control node.

[0042] The gate of the third transistor is electrically connected with the second control end, the first pole of the third transistor is electrically connected with the third node, and the second pole of the third transistor is electrically connected with the first gate driving end.

[0043] Optionally, the first initialization circuit comprises a fourth transistor.

[0044] The gate of the fourth transistor is electrically connected with the first scan end, the first electrode of the fourth transistor is electrically connected with the first initial voltage end, and the second electrode of the fourth transistor is electrically connected with the control node.

[0045] Optionally, the data writing circuit comprises a fifth transistor, and the second energy storage circuit comprises a second capacitor.

[0046] The gate of the fifth transistor is electrically connected with the second gate driving end, the first electrode of the fifth transistor is electrically connected with the data line, and the second electrode of the fifth transistor is electrically connected with the second node.

[0047] The first end of the second capacitor is electrically connected with the first node, and the second end of the second capacitor is electrically connected with a direct current voltage end.

[0048] Optionally, the first light emitting control circuit comprises a sixth transistor, and the second light emitting control circuit comprises a seventh transistor.

[0049] The gate of the sixth transistor is electrically connected with the light emitting control end, the first electrode of the sixth transistor is electrically connected with the power voltage end, and the second electrode of the sixth transistor is electrically connected with the second node.

[0050] The gate of the seventh transistor is electrically connected with the light emitting control end, the first electrode of the seventh transistor is electrically connected with the third node, and the second electrode of the seventh transistor is electrically connected with the first electrode of the light emitting element.

[0051] Optionally, the second initialization circuit comprises an eighth transistor.

[0052] The gate of the eighth transistor is electrically connected with the first reset end, the first electrode of the eighth transistor is electrically connected with the first initial voltage end, and the second electrode of the eighth transistor is electrically connected with the third node.

[0053] Optionally, the second initialization circuit comprises an eighth transistor.

[0054] The gate of the eighth transistor is electrically connected with the first reset end, the first electrode of the eighth transistor is electrically connected with the first initial voltage end, and the second electrode of the eighth transistor is electrically connected with the first node.

[0055] Optionally, the third initialization circuit comprises a ninth transistor.

[0056] The gate of the ninth transistor is electrically connected with the second reset end, the first electrode of the ninth transistor is electrically connected with the second initial voltage end, and the second electrode of the ninth transistor is electrically connected with the first electrode of the light emitting element.

[0057] Optionally, the fourth initialization circuit includes a tenth transistor.

[0058] The gate of the tenth transistor is electrically connected with the second reset end, the first pole of the tenth transistor is electrically connected with the third initial voltage end, and the second pole of the tenth transistor is electrically connected with the second node.

[0059] Optionally, the third energy storage circuit includes a third capacitor, the third control circuit includes an eleventh transistor, and the fourth control circuit includes a twelfth transistor.

[0060] The first end of the third capacitor is electrically connected with the intermediate node, and the second end of the third capacitor is electrically connected with the first reset end.

[0061] The gate of the eleventh transistor is electrically connected with the first control end, the first pole of the eleventh transistor is electrically connected with the first initial voltage end, and the second pole of the eleventh transistor is electrically connected with the intermediate node.

[0062] The gate of the twelfth transistor is electrically connected with the second control end, the first pole of the twelfth transistor is electrically connected with the first node, and the second pole of the twelfth transistor is electrically connected with the first reset end. In a second aspect, the display device includes the pixel circuit.

[0063] Embodiments of the present disclosure provide a pixel circuit for threshold voltage compensation of oxide transistors, and threshold voltage sensitive transistors continue to be compensated for threshold voltage to improve image quality and special needs. BRIEF DESCRIPTION OF DRAWINGS

[0064] FIG. 1A is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0065] FIG. 1B is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0066] FIG. 2 is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0067] FIG. 3 is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0068] FIG. 4 is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0069] FIG. 5A is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0070] FIG. 5B is a structure diagram of a pixel circuit according to at least one embodiment of the present disclosure; and

[0071] FIG. 6B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0072] FIG. 7A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0073] FIG. 7B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0074] FIG. 8A is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 7A;

[0075] FIG. 8B is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 7B;

[0076] FIG. 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0077] FIG. 10 is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 9;

[0078] FIG. 11A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0079] FIG. 11B is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0080] FIG. 12 is a timing diagram of operation of at least one embodiment of the pixel circuit shown in FIG. 11A. DETAILED DESCRIPTION

[0081] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0082] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two poles of the transistor other than the gate, one of the poles is referred to as the first pole and the other is referred to as the second pole.

[0083] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0084] As shown in FIG. 1A, the pixel circuit according to the embodiments of the present disclosure includes a driving circuit 10, a compensation control circuit 11, a first energy storage circuit 12, a first control circuit 13 and a second control circuit 14;

[0085] A control end of the drive circuit 10 is electrically connected with the first node N1, a first end of the drive circuit 10 is electrically connected with the second node N2, a second end of the drive circuit 10 is electrically connected with the third node N3, and the drive circuit 10 is configured to generate a drive current under the control of the potential of the first node N1.

[0086] The compensation control circuit 11 is electrically connected with the control node NC, the first node N1 and the third node N3 respectively, and is configured to control the communication between the first node N1 and the third node N3 under the control of the potential of the control node NC.

[0087] A first end of the first energy storage circuit 12 is electrically connected with the control node NC, and a second end of the first energy storage circuit 12 is electrically connected with the first gate drive end NGT, and the first energy storage circuit 12 is configured to store electrical energy.

[0088] The first control circuit 13 is electrically connected with the first control end S1, the first node N1 and the control node NC respectively, and is configured to control the communication between the first node N1 and the control node NC under the control of the first control signal provided by the first control end S1.

[0089] The second control circuit 14 is electrically connected with the second control end S2, the third node N3 and the first gate drive end NGT respectively, and is configured to control the communication between the third node N3 and the first gate drive end NGT under the control of the second control signal provided by the second control end S2.

[0090] Embodiments of the present disclosure provide a pixel circuit for threshold voltage compensation of oxide transistors, and threshold voltage sensitive transistors continue to perform threshold voltage compensation to improve image quality and special requirements such as HRD caused defects.

[0091] In at least one embodiment of the present disclosure, the first control end and the second control end are both first scan ends.

[0092] In specific implementation, the first control end and the second control end can be the same control end, and can be first scan ends.

[0093] As shown in FIG. 1B, based on at least one embodiment of the pixel circuit shown in FIG. 1A, the first control end and the second control end are both first scan ends SC1.

[0094] In at least one embodiment of the present disclosure, the first control end is a first scan end, and the second control end is a second scan end.

[0095] The pixel circuit in at least one embodiment of the present disclosure further includes a first initialization circuit.

[0096] The first initialization circuit is electrically connected with the first scan end, the first initial voltage end and the control node respectively, and is configured to write a first initial voltage provided by the first initial voltage end into the control node under control of a first scan signal provided by the first scan end.

[0097] The first control end and the second control end are a second scan end.

[0098] In a specific implementation, the first control end and the second control end can both be a second scan end, and the pixel circuit can further include a first initialization circuit configured to write a first initial voltage into the control node under control of a first scan signal, and reset the potential of the control node.

[0099] As shown in FIG. 2, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1A, the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit 21.

[0100] The first initialization circuit 21 is electrically connected with a first scan end SC1, a first initial voltage end I1 and the control node NC respectively, and is configured to write a first initial voltage Vinit1 provided by the first initial voltage end I1 into the control node NC under control of a first scan signal provided by the first scan end SC1.

[0101] The first control end and the second control end can be a second scan end.

[0102] In at least one embodiment of the present disclosure, the transistor included in the compensation control circuit is an oxide transistor, and the transistors included in the first control circuit and the second control circuit are low-temperature polysilicon transistors.

[0103] The pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit and a second energy storage circuit.

[0104] The data writing circuit is electrically connected with a second gate driving end, a data line and the second node respectively, and is configured to write a data voltage provided by the data line into the second node under control of a second gate driving signal provided by the second gate driving end.

[0105] The second energy storage circuit is electrically connected with the first node, and is configured to maintain the potential of the first node.

[0106] In a specific implementation, the pixel circuit can further include a data writing circuit and a second energy storage circuit, the data writing circuit is configured to write a data voltage into a second node under control of a second gate driving signal, and the second energy storage circuit is configured to maintain the potential of the first node.

[0107] As shown in FIG. 3, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1A, the pixel circuit in at least one embodiment of the present disclosure further includes a data writing circuit 31 and a second energy storage circuit 32.

[0108] The data writing circuit 31 is electrically connected with the second gate driving end PGT, the data line DL and the second node N2 respectively, and is configured to write the data voltage Vdata provided by the data line DL into the second node N2 under the control of the second gate driving signal provided by the second gate driving end PGT.

[0109] The second energy storage circuit 32 is electrically connected with the first node N1, and is configured to maintain the potential of the first node N1.

[0110] As shown in FIG. 4, on the basis of at least one embodiment of the pixel circuit shown in FIG. 2, the pixel circuit in at least one embodiment of the present disclosure further includes a data writing circuit 31 and a second energy storage circuit 32.

[0111] The data writing circuit 31 is electrically connected with the second gate driving end PGT, the data line DL and the second node N2 respectively, and is configured to write the data voltage Vdata provided by the data line DL into the second node N2 under the control of the second gate driving signal provided by the second gate driving end PGT.

[0112] The second energy storage circuit 32 is electrically connected with the first node N1, and is configured to maintain the potential of the first node N1.

[0113] The pixel circuit in at least one embodiment of the present disclosure further includes a light emitting element, a first light emitting control circuit and a second light emitting control circuit.

[0114] The first light emitting control circuit is electrically connected with the light emitting control end, the power voltage end and the second node respectively, and is configured to control the communication between the power voltage end and the second node under the control of the light emitting control signal provided by the light emitting control end.

[0115] The second light emitting control circuit is electrically connected with the light emitting control end, the third node and the first pole of the light emitting element respectively, and is configured to control the communication between the third node and the first pole of the light emitting element under the control of the light emitting control signal.

[0116] The second pole of the light emitting element is electrically connected with the first voltage end.

[0117] In specific implementation, the pixel circuit can further include a light emitting element, a first light emitting control circuit and a second light emitting control circuit, and the first light emitting control circuit and the second light emitting control circuit perform on-off control of the light emitting path under the control of the light emitting control signal.

[0118] Optionally, the first voltage terminal can be a low voltage terminal.

[0119] The pixel circuit further comprises a second initialization circuit.

[0120] The second initialization circuit is electrically connected with the first reset terminal, the first initial voltage terminal and the third node respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal into the third node under control of a first reset control signal provided by the first reset terminal.

[0121] In a specific implementation, the pixel circuit further comprises a second initialization circuit, which writes the first initial voltage into the third node under control of the first reset control signal, so that the first initial voltage can be written into the first node under control of the compensation control circuit when the compensation control circuit controls the communication between the first node and the third node, and the driving circuit can be turned on when the compensation phase starts.

[0122] The pixel circuit further comprises a second initialization circuit.

[0123] The second initialization circuit is electrically connected with the first reset terminal, the first initial voltage terminal and the first node respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal into the first node under control of a first reset control signal provided by the first reset terminal.

[0124] In a specific implementation, the pixel circuit further comprises a second initialization circuit, which writes the first initial voltage into the first node under control of the first reset control signal, so that the first initial voltage can be written into the first node under control of the compensation control circuit when the compensation control circuit controls the communication between the first node and the third node, and the driving circuit can be turned on when the compensation phase starts.

[0125] The pixel circuit further comprises a third initialization circuit.

[0126] The third initialization circuit is electrically connected with the second reset terminal, the second initial voltage terminal and the first electrode of the light emitting element respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light emitting element under control of a second reset control signal provided by the second reset terminal.

[0127] In a specific implementation, the pixel circuit further comprises a third initialization circuit, which writes the second initial voltage into the first electrode of the light emitting element under control of the second reset control signal, and clears the residual charge in the first electrode of the light emitting element.

[0128] The pixel circuit in at least one embodiment of the present disclosure further comprises a fourth initialization circuit.

[0129] The fourth initialization circuit is electrically connected with the second reset end, the third initial voltage end and the second node respectively, and is configured to write the third initial voltage provided by the third initial voltage end into the second node under the control of a second reset control signal provided by the second reset end.

[0130] In a specific implementation, the pixel circuit can further comprise a fourth initialization circuit configured to write a second initial voltage into the second node under the control of a second reset control signal, thereby improving the hysteresis of a driving transistor in the driving circuit.

[0131] As shown in FIG. 5A, the pixel circuit in at least one embodiment of the present disclosure further comprises a light emitting element E1, a first light emitting control circuit 51 and a second light emitting control circuit 52 based on the pixel circuit in at least one embodiment shown in FIG. 3.

[0132] The first light emitting control circuit 51 is electrically connected with a light emitting control end EM, a power voltage end VDD and the second node N2 respectively, and is configured to control the communication between the power voltage end VDD and the second node N2 under the control of a light emitting control signal provided by the light emitting control end EM.

[0133] The second light emitting control circuit 52 is electrically connected with the light emitting control end EM, the third node N3 and a first pole of the light emitting element E1 respectively, and is configured to control the communication between the third node N3 and the first pole of the light emitting element E1 under the control of the light emitting control signal.

[0134] A second pole of the light emitting element E1 is electrically connected with a first voltage end V1.

[0135] The pixel circuit in at least one embodiment of the present disclosure further comprises a second initialization circuit 53.

[0136] The second initialization circuit 53 is electrically connected with a first reset end RSTP, a first initial voltage end I1 and the third node N3 respectively, and is configured to write a first initial voltage Vinit1 provided by the first initial voltage end I1 into the third node N3 under the control of a first reset control signal provided by the first reset end RSTP.

[0137] The pixel circuit in at least one embodiment of the present disclosure further comprises a third initialization circuit 54.

[0138] The third initialization circuit 54 is electrically connected with the second reset end RSTH, the second initial voltage end I2 and the first electrode of the light emitting element E1 respectively, and is configured to write the second initial voltage Vinit2 provided by the second initial voltage end I2 into the first electrode of the light emitting element E1 under the control of the second reset control signal provided by the second reset end RSTH.

[0139] The pixel circuit in at least one embodiment of the present disclosure further comprises a fourth initialization circuit 55.

[0140] The fourth initialization circuit 55 is electrically connected with the second reset end RSTH, the third initial voltage end I3 and the second node N2 respectively, and is configured to write the third initial voltage provided by the third initial voltage end I3 into the second node N2 under the control of the second reset control signal provided by the second reset end RSTH.

[0141] As shown in FIG. 5B, on the basis of the pixel circuit in at least one embodiment shown in FIG. 3, the pixel circuit in at least one embodiment of the present disclosure further comprises a light emitting element E1, a first light emitting control circuit 51 and a second light emitting control circuit 52.

[0142] The first light emitting control circuit 51 is electrically connected with the light emitting control end EM, the power voltage end VDD and the second node N2 respectively, and is configured to control the communication between the power voltage end VDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control end EM.

[0143] The second light emitting control circuit 52 is electrically connected with the light emitting control end EM, the third node N3 and the first electrode of the light emitting element E1 respectively, and is configured to control the communication between the third node N3 and the first electrode of the light emitting element E1 under the control of the light emitting control signal.

[0144] The second electrode of the light emitting element E1 is electrically connected with the first voltage end V1.

[0145] The pixel circuit in at least one embodiment of the present disclosure further comprises a second initialization circuit 53.

[0146] The second initialization circuit 53 is electrically connected with the first reset end RSTP, the first initial voltage end I1 and the first node N1 respectively, and is configured to write the first initial voltage Vinit1 provided by the first initial voltage end I1 into the first node N1 under the control of the first reset control signal provided by the first reset end RSTP.

[0147] The pixel circuit in at least one embodiment of the present disclosure further comprises a third initialization circuit 54.

[0148] The third initialization circuit 54 is electrically connected with the second reset end RSTH, the second initial voltage end I2 and the first electrode of the light emitting element E1 respectively, and is configured to write the second initial voltage Vinit2 provided by the second initial voltage end I2 into the first electrode of the light emitting element E1 under the control of the second reset control signal provided by the second reset end RSTH.

[0149] The pixel circuit in at least one embodiment of the present disclosure further comprises a fourth initialization circuit 55.

[0150] The fourth initialization circuit 55 is electrically connected with the second reset end RSTH, the third initial voltage end I3 and the second node N2 respectively, and is configured to write the third initial voltage provided by the third initial voltage end I3 into the second node N2 under the control of the second reset control signal provided by the second reset end RSTH.

[0151] As shown in FIG. 6A, on the basis of at least one embodiment of the pixel circuit shown in FIG. 4, the pixel circuit in at least one embodiment of the present disclosure further comprises a light emitting element E1, a first light emitting control circuit 51 and a second light emitting control circuit 52.

[0152] The first light emitting control circuit 51 is electrically connected with the light emitting control end EM, the power voltage end VDD and the second node N2 respectively, and is configured to control the communication between the power voltage end VDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control end EM.

[0153] The second light emitting control circuit 52 is electrically connected with the light emitting control end EM, the third node N3 and the first electrode of the light emitting element E1 respectively, and is configured to control the communication between the third node N3 and the first electrode of the light emitting element E1 under the control of the light emitting control signal.

[0154] The second electrode of the light emitting element E1 is electrically connected with the first voltage end V1.

[0155] The pixel circuit in at least one embodiment of the present disclosure further comprises a second initialization circuit 53.

[0156] The second initialization circuit 53 is electrically connected with the first reset end RSTP, the first initial voltage end I1 and the third node N3 respectively, and is configured to write the first initial voltage Vinit1 provided by the first initial voltage end I1 into the third node N3 under the control of the first reset control signal provided by the first reset end RSTP.

[0157] The pixel circuit in at least one embodiment of the present disclosure further comprises a third initialization circuit 54.

[0158] The third initialization circuit 54 is electrically connected with the second reset end RSTH, the second initial voltage end I2 and the first electrode of the light emitting element E1 respectively, and is configured to write the second initial voltage Vinit2 provided by the second initial voltage end I2 into the first electrode of the light emitting element E1 under the control of the second reset control signal provided by the second reset end RSTH.

[0159] The pixel circuit in at least one embodiment of the present disclosure further includes a fourth initialization circuit 55.

[0160] The fourth initialization circuit 55 is electrically connected with the second reset end RSTH, the third initial voltage end I3 and the second node N2 respectively, and is configured to write the third initial voltage provided by the third initial voltage end I3 into the second node N2 under the control of the second reset control signal provided by the second reset end RSTH.

[0161] The pixel circuit in at least one embodiment of the present disclosure further includes a third energy storage circuit, a third control circuit and a fourth control circuit.

[0162] The first end of the third energy storage circuit is electrically connected with the intermediate node, the second end of the third energy storage circuit is electrically connected with the first reset end, and the third energy storage circuit is configured to store electrical energy.

[0163] The third control circuit is electrically connected with the first control end, the first initial voltage end and the intermediate node respectively, and is configured to control the communication between the first initial voltage end and the intermediate node under the control of the first control signal.

[0164] The fourth control circuit is electrically connected with the second control end, the first node and the first reset end respectively, and is configured to control the communication between the first node and the first reset end under the control of the second control signal.

[0165] In at least one embodiment of the present disclosure, when the transistor included in the second initialization circuit is an oxide transistor, threshold voltage compensation can be performed on the transistor included in the second initialization circuit by the third energy storage circuit, the third control circuit and the fourth control circuit, so as to improve the picture quality and special requirements such as the adverse effects caused by HRD.

[0166] As shown in FIG. 6B, on the basis of at least one embodiment of the pixel circuit shown in FIG. 5B, the pixel circuit in at least one embodiment of the present disclosure further includes a third energy storage circuit 61, a third control circuit 62 and a fourth control circuit 63.

[0167] The first end of the third energy storage circuit 61 is electrically connected with the intermediate node NZ, the second end of the third energy storage circuit 61 is electrically connected with the first reset end RSTP, and the third energy storage circuit 61 is configured to store electrical energy.

[0168] The third control circuit 62 is electrically connected with the first control end S1, the first initial voltage end I1 and the intermediate node NZ respectively, and is configured to control the first initial voltage end I1 and the intermediate node NZ to be in communication under the control of the first control signal.

[0169] The fourth control circuit 63 is electrically connected with the second control end S2, the first node N1 and the first reset end RSTP respectively, and is configured to control the first node N1 and the first reset end RSTP to be in communication under the control of the second control signal.

[0170] Optionally, the driving circuit comprises a driving transistor, the compensation control circuit comprises a first transistor, and the first energy storage circuit comprises a first capacitor; the first control circuit comprises a second transistor, and the second control circuit comprises a third transistor.

[0171] The gate of the driving transistor is electrically connected with the first node, the first pole of the driving transistor is electrically connected with the second node, and the second pole of the driving transistor is electrically connected with the third node.

[0172] The gate of the first transistor is electrically connected with the control node, the first pole of the first transistor is electrically connected with the first node, and the second pole of the first transistor is electrically connected with the third node.

[0173] The first end of the first capacitor is electrically connected with the control node, and the second end of the first capacitor is electrically connected with the first gate driving end.

[0174] The gate of the second transistor is electrically connected with the first control end, the first pole of the second transistor is electrically connected with the first node, and the second pole of the second transistor is electrically connected with the control node.

[0175] The gate of the third transistor is electrically connected with the second control end, the first pole of the third transistor is electrically connected with the third node, and the second pole of the third transistor is electrically connected with the first gate driving end.

[0176] Optionally, the first initialization circuit comprises a fourth transistor.

[0177] The gate of the fourth transistor is electrically connected with the first scanning end, the first pole of the fourth transistor is electrically connected with the first initial voltage end, and the second pole of the fourth transistor is electrically connected with the control node.

[0178] Optionally, the data writing circuit comprises a fifth transistor, and the second energy storage circuit comprises a second capacitor.

[0179] A gate of the fifth transistor is electrically connected with the second gate driving end, a first pole of the fifth transistor is electrically connected with the data line, and a second pole of the fifth transistor is electrically connected with the second node.

[0180] A first end of the second capacitor is electrically connected with the first node, and a second end of the second capacitor is electrically connected with the direct current voltage end.

[0181] Optionally, the first light emitting control circuit comprises a sixth transistor, and the second light emitting control circuit comprises a seventh transistor.

[0182] A gate of the sixth transistor is electrically connected with the light emitting control end, a first pole of the sixth transistor is electrically connected with the power voltage end, and a second pole of the sixth transistor is electrically connected with the second node.

[0183] A gate of the seventh transistor is electrically connected with the light emitting control end, a first pole of the seventh transistor is electrically connected with the third node, and a second pole of the seventh transistor is electrically connected with the first pole of the light emitting element.

[0184] Optionally, the second initialization circuit comprises an eighth transistor.

[0185] A gate of the eighth transistor is electrically connected with the first reset end, a first pole of the eighth transistor is electrically connected with the first initial voltage end, and a second pole of the eighth transistor is electrically connected with the third node.

[0186] Optionally, the third initialization circuit comprises a ninth transistor.

[0187] A gate of the ninth transistor is electrically connected with the second reset end, a first pole of the ninth transistor is electrically connected with the second initial voltage end, and a second pole of the ninth transistor is electrically connected with the first pole of the light emitting element.

[0188] Optionally, the fourth initialization circuit comprises a tenth transistor.

[0189] A gate of the tenth transistor is electrically connected with the second reset end, a first pole of the tenth transistor is electrically connected with the third initial voltage end, and a second pole of the tenth transistor is electrically connected with the second node.

[0190] As shown in FIG. 7A, on the basis of at least one embodiment of the pixel circuit shown in FIG. 5A, the driving circuit comprises a driving transistor T0, the compensation control circuit comprises a first transistor T1, the first energy storage circuit comprises a first capacitor C1, the first control circuit comprises a second transistor T2, the second control circuit comprises a third transistor T3, and the light emitting element is an organic light emitting diode O1.

[0191] The gate of the driving transistor T0 is electrically connected with the first node N1, the source of the driving transistor T0 is electrically connected with the second node N2, and the drain of the driving transistor T0 is electrically connected with the third node N3;

[0192] The gate of the first transistor T1 is electrically connected with the control node NC, the source of the first transistor T1 is electrically connected with the first node N1, and the drain of the first transistor T1 is electrically connected with the third node N3;

[0193] The first end of the first capacitor C1 is electrically connected with the control node NC, and the second end of the first capacitor C1 is electrically connected with the first gate driving end NGT;

[0194] The gate of the second transistor T2 is electrically connected with the first scan end SC1, the source of the second transistor T2 is electrically connected with the first node N1, and the drain of the second transistor T2 is electrically connected with the control node NC;

[0195] The gate of the third transistor T3 is electrically connected with the first scan end SC1, the source of the third transistor T3 is electrically connected with the third node N3, and the drain of the third transistor T3 is electrically connected with the first gate driving end NGT;

[0196] The data writing circuit comprises a fifth transistor T5, and the second energy storage circuit comprises a second capacitor C2;

[0197] The gate of the fifth transistor T5 is electrically connected with the second gate driving end PGT, the source of the fifth transistor T5 is electrically connected with the data line DL, and the drain of the fifth transistor T5 is electrically connected with the second node N2;

[0198] The first end of the second capacitor C2 is electrically connected with the first node N1, and the second end of the second capacitor C2 is electrically connected with the power voltage end VDD;

[0199] The first light emitting control circuit comprises a sixth transistor T6, and the second light emitting control circuit comprises a seventh transistor T7;

[0200] The gate of the sixth transistor T6 is electrically connected with the light emitting control end EM, the source of the sixth transistor T6 is electrically connected with the power voltage end VDD, and the drain of the sixth transistor T6 is electrically connected with the second node N2;

[0201] The gate of the seventh transistor T7 is electrically connected with the light emitting control end EM, the source of the seventh transistor T7 is electrically connected with the third node N3, and the drain of the seventh transistor T7 is electrically connected with the anode of the organic light emitting diode O1;

[0202] The second initialization circuit comprises an eighth transistor T8;

[0203] The gate of the eighth transistor T8 is electrically connected with the first reset terminal RSTP, the source of the eighth transistor T8 is electrically connected with the first initial voltage terminal I1, and the drain of the eighth transistor T8 is electrically connected with the third node N3;

[0204] The third initialization circuit comprises a ninth transistor T9;

[0205] The gate of the ninth transistor T9 is electrically connected with the second reset terminal RSTH, the source of the ninth transistor T9 is electrically connected with the second initial voltage terminal I2, and the drain of the ninth transistor T9 is electrically connected with the anode of the organic light-emitting diode O1; the cathode of O1 is electrically connected with the low voltage terminal VSS;

[0206] The fourth initialization circuit comprises a tenth transistor T10;

[0207] The gate of the tenth transistor T10 is electrically connected with the second reset terminal RSTH, the source of the tenth transistor T10 is electrically connected with the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected with the second node N2.

[0208] In at least one embodiment of the pixel circuit shown in FIG. 7A, T1 is an n-type transistor, T0, T2, T3, T5, T6, T7, T8, T9 and T10 are p-type transistors; T1 is an Oxide TFT.

[0209] T1 is a transistor sensitive to threshold voltage.

[0210] As shown in FIG. 8A, at least one embodiment of the pixel circuit shown in FIG. 7A in operation, the display period can include a compensation stage t1, a first reset stage t2, a data writing stage t3, a second reset stage t4 and an emitting stage t5 arranged in sequence;

[0211] In the compensation stage t1, NGT provides a high voltage signal, SC1 provides a low voltage signal, T2 and T3 are turned on, the high voltage signal provided by NGT passes through T3, T1 and T2, and the potential of NC is pulled up, when the potential of NC is Vngt+Vth1, T1 is turned off, C1 maintains the potential of NC, so as to be able to compensate the threshold voltage of T1; wherein, Vngt is the voltage value of the voltage signal provided by NGT, and Vth1 is the threshold voltage of T1;

[0212] In the first reset stage t2, the NGT provides a high voltage signal, the SC1 provides a high voltage signal, the RSTP provides a low voltage signal, the T8 is turned on, Vinit1 is written into N3, the T1 is turned on, Vinit1 is written into N1, and the potential of N1 is reset;

[0213] In the data writing stage t3, the NGT provides a high voltage signal, the PGT provides a low voltage signal, the T5 is turned on, the DL provides a data voltage Vdata to N2, and the T1 is turned on;

[0214] At the beginning of the data writing stage t3, the T0 is turned on, Vdata charges C2 through T5, T0 and T1, changes the potential of N1, and until the potential of N1 becomes Vdata+Vth, Vth is the threshold voltage of T0, and the T0 is turned off;

[0215] After the data writing stage t3, when the potential of the first gate driving signal provided by the NGT jumps low, the potential of NC is pulled low by C1, the potential of NC is equal to Vngt+Vth1+△V×C1z / CNC, the potential of NC always contains Vth1, therefore, the on state of T1 is not affected by the threshold voltage of T1, and the threshold voltage compensation of T1 is achieved; wherein,△V is the change value of the potential of the first gate signal, Cz1 is the capacitance value of C1, and CNC is the total capacitance of NC;

[0216] In the second reset stage t4, the RSTH provides a low voltage signal, the T9 and the T10 are turned on, the I2 provides a second initial voltage Vinit2 to the anode of O1, the residual charge of the anode of O1 is cleared, the I3 provides a third initial voltage Vinit3 to N2, and the hysteresis phenomenon of T0 is improved;

[0217] In the light emitting stage t5, the EM provides a low voltage signal, the T6 and the T7 are turned on, and the T0 drives O1 to emit light.

[0218] As shown in FIG. 7B, based on at least one embodiment of the pixel circuit shown in FIG. 5B,

[0219] The driving circuit includes a driving transistor T0, the compensation control circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1, the first control circuit includes a second transistor T2, the second control circuit includes a third transistor T3, and the light emitting element is an organic light emitting diode O1;

[0220] The gate of the driving transistor T0 is electrically connected with the first node N1, the source of the driving transistor T0 is electrically connected with the second node N2, and the drain of the driving transistor T0 is electrically connected with the third node N3;

[0221] The gate of the first transistor T1 is electrically connected with the control node NC, the source of the first transistor T1 is electrically connected with the first node N1, and the drain of the first transistor T1 is electrically connected with the third node N3;

[0222] The first end of the first capacitor C1 is electrically connected with the control node NC, and the second end of the first capacitor C1 is electrically connected with the first gate driving end NGT;

[0223] The gate of the second transistor T2 is electrically connected with the first scanning end SC1, the source of the second transistor T2 is electrically connected with the first node N1, and the drain of the second transistor T2 is electrically connected with the control node NC;

[0224] The gate of the third transistor T3 is electrically connected with the first scanning end SC1, the source of the third transistor T3 is electrically connected with the third node N3, and the drain of the third transistor T3 is electrically connected with the first gate driving end NGT;

[0225] The data writing circuit comprises a fifth transistor T5, and the second energy storage circuit comprises a second capacitor C2;

[0226] The gate of the fifth transistor T5 is electrically connected with the second gate driving end PGT, the source of the fifth transistor T5 is electrically connected with the data line DL, and the drain of the fifth transistor T5 is electrically connected with the second node N2;

[0227] The first end of the second capacitor C2 is electrically connected with the first node N1, and the second end of the second capacitor C2 is electrically connected with the power voltage end VDD;

[0228] The first light emitting control circuit comprises a sixth transistor T6, and the second light emitting control circuit comprises a seventh transistor T7;

[0229] The gate of the sixth transistor T6 is electrically connected with the light emitting control end EM, the source of the sixth transistor T6 is electrically connected with the power voltage end VDD, and the drain of the sixth transistor T6 is electrically connected with the second node N2;

[0230] The gate of the seventh transistor T7 is electrically connected with the light emitting control end EM, the source of the seventh transistor T7 is electrically connected with the third node N3, and the drain of the seventh transistor T7 is electrically connected with the anode of the organic light emitting diode O1;

[0231] The second initialization circuit comprises an eighth transistor T8;

[0232] The gate of the eighth transistor T8 is electrically connected with the first reset end RSTP, the source of the eighth transistor T8 is electrically connected with the first initial voltage end I1, and the drain of the eighth transistor T8 is electrically connected with the first node N1.

[0233] The third initialization circuit comprises a ninth transistor T9.

[0234] The gate of the ninth transistor T9 is electrically connected with the second reset end RSTH, the source of the ninth transistor T9 is electrically connected with the second initial voltage end I2, and the drain of the ninth transistor T9 is electrically connected with the anode of the organic light emitting diode O1; the cathode of O1 is electrically connected with the low voltage end VSS.

[0235] The fourth initialization circuit comprises a tenth transistor T10.

[0236] The gate of the tenth transistor T10 is electrically connected with the second reset end RSTH, the source of the tenth transistor T10 is electrically connected with the third initial voltage end I3, and the drain of the tenth transistor T10 is electrically connected with the second node N2.

[0237] In at least one embodiment of the pixel circuit shown in FIG. 7B, T1 and T8 are n-type transistors, T0, T2, T3, T5, T6, T7, T9 and T10 are p-type transistors; T1 and T8 are Oxide TFTs.

[0238] T1 is a transistor sensitive to threshold voltage.

[0239] As shown in FIG. 8B, at least one embodiment of the pixel circuit shown in FIG. 7B in operation, the display period can comprise a compensation stage t1, a first reset stage t2, a data writing stage t3, a second reset stage t4 and an emitting stage t5 arranged in sequence;

[0240] In the compensation stage t1, NGT provides a high voltage signal, SC1 provides a low voltage signal, T2 and T3 are turned on, the high voltage signal provided by NGT passes through T3, T1 and T2, and the potential of NC is pulled up, when the potential of NC is Vngt+Vth1, T1 is turned off, and C1 maintains the potential of NC, so as to be able to compensate the threshold voltage of T1; wherein, Vngt is the voltage value of the voltage signal provided by NGT, and Vth1 is the threshold voltage of T1;

[0241] In the first reset stage t2, NGT provides a high voltage signal, SC1 provides a high voltage signal, RSTP provides a high voltage signal, and T8 is turned on to write Vinit1 into N1, and Vinit1 is written into N1 to reset the potential of N1;

[0242] In the data writing stage t3, the NGT provides a high voltage signal, the PGT provides a low voltage signal, the T5 is turned on, the DL provides a data voltage Vdata to the N2, and the T1 is turned on;

[0243] At the beginning of the data writing stage t3, the T0 is turned on, the Vdata charges the C2 through the T5, the T0 and the T1, changes the potential of the N1, and until the potential of the N1 becomes Vdata+Vth, the Vth is the threshold voltage of the T0, and the T0 is turned off;

[0244] After the data writing stage t3, when the potential of the first gate driving signal provided by the NGT jumps low, the potential of the NC is pulled low by the C1, the potential of the NC is equal to Vngt+Vth1+△V×C1z / CNC, the potential of the NC always contains Vth1, thus the on state of the T1 is not affected by the threshold voltage of the T1, and the purpose of compensating the threshold voltage of the T1 is achieved; wherein, the△V is the change value of the potential of the first gate signal, the Cz1 is the capacitance value of the C1, and the CNC is the total capacitance of the NC;

[0245] In the second reset stage t4, the RSTH provides a low voltage signal, the T9 and the T10 are turned on, the I2 provides a second initial voltage Vinit2 to the anode of the O1, and the residual charge of the anode of the O1 is cleared, and the I3 provides a third initial voltage Vinit3 to the N2, and the hysteresis phenomenon of the T0 is improved;

[0246] In the light emitting stage t5, the EM provides a low voltage signal, the T6 and the T7 are turned on, and the T0 drives the O1 to emit light.

[0247] As shown in FIG. 9, on the basis of at least one embodiment of the pixel circuit shown in FIG. 5A, the driving circuit includes a driving transistor T0, the compensation control circuit includes a first transistor T1, and the first energy storage circuit includes a first capacitor C1; the first control circuit includes a second transistor T2, and the second control circuit includes a third transistor T3; and the light emitting element is an organic light emitting diode O1;

[0248] The gate of the driving transistor T0 is electrically connected with the first node N1, the source of the driving transistor T0 is electrically connected with the second node N2, and the drain of the driving transistor T0 is electrically connected with the third node N3;

[0249] The gate of the first transistor T1 is electrically connected with the control node NC, the source of the first transistor T1 is electrically connected with the first node N1, and the drain of the first transistor T1 is electrically connected with the third node N3;

[0250] The first end of the first capacitor C1 is electrically connected with the control node NC, and the second end of the first capacitor C1 is electrically connected with the first gate driving end NGT;

[0251] a gate of the second transistor T2 is electrically connected with the first scan end SC1, a source of the second transistor T2 is electrically connected with the first node N1, and a drain of the second transistor T2 is electrically connected with the control node NC;

[0252] a gate of the third transistor T3 is electrically connected with the second scan end SC2, a source of the third transistor T3 is electrically connected with the third node N3, and a drain of the third transistor T3 is electrically connected with the first gate drive end NGT;

[0253] the data write circuit comprises a fifth transistor T5, and the second energy storage circuit comprises a second capacitor C2;

[0254] a gate of the fifth transistor T5 is electrically connected with the second gate drive end PGT, a source of the fifth transistor T5 is electrically connected with the data line DL, and a drain of the fifth transistor T5 is electrically connected with the second node N2;

[0255] a first end of the second capacitor C2 is electrically connected with the first node N1, and a second end of the second capacitor C2 is electrically connected with the power voltage end VDD;

[0256] the first light emitting control circuit comprises a sixth transistor T6, and the second light emitting control circuit comprises a seventh transistor T7;

[0257] a gate of the sixth transistor T6 is electrically connected with the light emitting control end EM, a source of the sixth transistor T6 is electrically connected with the power voltage end VDD, and a drain of the sixth transistor T6 is electrically connected with the second node N2;

[0258] a gate of the seventh transistor T7 is electrically connected with the light emitting control end EM, a source of the seventh transistor T7 is electrically connected with the third node N3, and a drain of the seventh transistor T7 is electrically connected with an anode of the organic light emitting diode O1;

[0259] the second initialization circuit comprises an eighth transistor T8;

[0260] a gate of the eighth transistor T8 is electrically connected with the first reset end RSTP, a source of the eighth transistor T8 is electrically connected with the first initial voltage end I1, and a drain of the eighth transistor T8 is electrically connected with the third node N3;

[0261] the third initialization circuit comprises a ninth transistor T9;

[0262] A gate of the ninth transistor T9 is electrically connected with the second reset terminal RSTH, a source of the ninth transistor T9 is electrically connected with the second initial voltage terminal I2, and a drain of the ninth transistor T9 is electrically connected with an anode of the organic light emitting diode O1; a cathode of O1 is electrically connected with a low voltage terminal VSS.

[0263] The fourth initialization circuit comprises a tenth transistor T10.

[0264] A gate of the tenth transistor T10 is electrically connected with the second reset terminal RSTH, a source of the tenth transistor T10 is electrically connected with the third initial voltage terminal I3, and a drain of the tenth transistor T10 is electrically connected with the second node N2.

[0265] In at least one embodiment of the pixel circuit shown in FIG. 9, T1 is an n-type transistor, T0, T2, T3, T5, T6, T7, T8, T9 and T10 are p-type transistors; T1 is an Oxide TFT.

[0266] T1 is a transistor sensitive to threshold voltage.

[0267] As shown in FIG. 10, in at least one embodiment of the pixel circuit shown in FIG. 9 of the present disclosure, during operation, a display period can comprise a first reset stage t0, a compensation stage t1, a second reset stage t4, a data writing stage t3, a third reset stage t6 and an emitting stage t5 arranged in sequence;

[0268] In the first reset stage t0, NGT provides a high voltage signal, SC1 provides a low voltage signal, SC2 provides a high voltage signal, RSTP provides a low voltage signal, T8 and T2 are turned on, when the potential of the voltage signal provided by NGT jumps high, the potential of NC is pulled high, Vinit1 provided by I1 passes through T1 and T2, and the potential of NC is reset to Vinit1+Vth1, when the potential of NC is Vinit1+Vth1, T1 is turned off, C1 maintains the potential of NC, and Vth1 is the threshold voltage of T1;

[0269] In the compensation stage t1, NGT provides a high voltage signal, SC1 provides a low voltage signal, SC2 provides a low voltage signal, T2 and T3 are turned on, the high voltage signal provided by NGT passes through T3, T1 and T2, and the potential of NC is pulled high, when the potential of NC is Vngt+Vth1, T1 is turned off, and C1 maintains the potential of NC; Vngt is the potential of the first gate driving signal provided by NGT, and Vth1 is the threshold voltage of T1;

[0270] In the second reset stage t4, SC1 and SC2 provide high voltage signals, RSTP provides a low voltage signal, T8 is turned on, T1 is turned on, and the first initial voltage Vinit1 provided by I1 resets the potential of N1;

[0271] In the data writing stage t3, PGT provides a low voltage signal, NGT provides a high voltage signal, PGT provides a low voltage signal, T5 is turned on, and DL provides the data voltage Vdata to N2, and T1 is turned on;

[0272] At the beginning of the data writing stage t3, T0 is turned on, C2 is charged by Vdata, the potential of N1 is changed until the potential of N1 becomes Vdata+Vth, Vth is the threshold voltage of T0, and T0 is turned off;

[0273] After the data writing stage t3, when the potential of the first gate driving signal provided by NGT jumps low, the potential of NC is pulled low by C1, the potential of NC is equal to Vngt+Vth1+△V×C1z / CNC, the potential of NC always contains Vth1, so the on state of T1 is not affected by the threshold voltage of T1, and the purpose of compensating the threshold voltage of T1 is achieved; wherein △V is the change value of the potential of the first gate signal, Cz1 is the capacitance value of C1, and CNC is the total capacitance of NC;

[0274] In the third reset stage t6, RSTH provides a low voltage signal, T9 and T10 are turned on, I2 provides the second initial voltage Vinit2 to the anode of O1, and the residual charge at the anode of O1 is cleared, I3 provides the third initial voltage Vinit3 to N2, and the hysteresis phenomenon of T0 is improved;

[0275] In the light emitting stage t5, EM provides a low voltage signal, T6 and T7 are turned on, and T0 drives O1 to emit light.

[0276] As shown in FIG. 11A, on the basis of at least one embodiment of the pixel circuit shown in FIG. 6A, the driving circuit includes a driving transistor T0, the compensation control circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1, the first control circuit includes a second transistor T2, the second control circuit includes a third transistor T3, and the light emitting element is an organic light emitting diode O1;

[0277] The gate of the driving transistor T0 is electrically connected with the first node N1, the source of the driving transistor T0 is electrically connected with the second node N2, and the drain of the driving transistor T0 is electrically connected with the third node N3;

[0278] The gate of the first transistor T1 is electrically connected with the control node NC, the source of the first transistor T1 is electrically connected with the first node N1, and the drain of the first transistor T1 is electrically connected with the third node N3.

[0279] The first end of the first capacitor C1 is electrically connected with the control node NC, and the second end of the first capacitor C1 is electrically connected with the first gate driving end NGT.

[0280] The gate of the second transistor T2 is electrically connected with the second scanning end SC2, the source of the second transistor T2 is electrically connected with the first node N1, and the drain of the second transistor T2 is electrically connected with the control node NC.

[0281] The gate of the third transistor T3 is electrically connected with the second scanning end SC2, the source of the third transistor T3 is electrically connected with the third node N3, and the drain of the third transistor T3 is electrically connected with the first gate driving end NGT.

[0282] The first initialization circuit comprises a fourth transistor T4.

[0283] The gate of the fourth transistor T4 is electrically connected with the first scanning end SC1, the source of the fourth transistor is electrically connected with the first initial voltage end I1, and the drain of the fourth transistor T4 is electrically connected with the control node NC.

[0284] The data writing circuit comprises a fifth transistor T5, and the second energy storage circuit comprises a second capacitor C2.

[0285] The gate of the fifth transistor T5 is electrically connected with the second gate driving end PGT, the source of the fifth transistor T5 is electrically connected with the data line DL, and the drain of the fifth transistor T5 is electrically connected with the second node N2.

[0286] The first end of the second capacitor C2 is electrically connected with the first node N1, and the second end of the second capacitor C2 is electrically connected with the power voltage end VDD.

[0287] The first light emitting control circuit comprises a sixth transistor T6, and the second light emitting control circuit comprises a seventh transistor T7.

[0288] The gate of the sixth transistor T6 is electrically connected with the light emitting control end EM, the source of the sixth transistor T6 is electrically connected with the power voltage end VDD, and the drain of the sixth transistor T6 is electrically connected with the second node N2.

[0289] The gate of the seventh transistor T7 is electrically connected with the light-emitting control end EM, the source of the seventh transistor T7 is electrically connected with the third node N3, and the drain of the seventh transistor T7 is electrically connected with the anode of the organic light-emitting diode O1;

[0290] The second initialization circuit comprises an eighth transistor T8.

[0291] The gate of the eighth transistor T8 is electrically connected with the first reset end RSTP, the source of the eighth transistor T8 is electrically connected with the first initial voltage end I1, and the drain of the eighth transistor T8 is electrically connected with the third node N3.

[0292] The third initialization circuit comprises a ninth transistor T9.

[0293] The gate of the ninth transistor T9 is electrically connected with the second reset end RSTH, the source of the ninth transistor T9 is electrically connected with the second initial voltage end I2, and the drain of the ninth transistor T9 is electrically connected with the anode of the organic light-emitting diode O1; the cathode of O1 is electrically connected with the low voltage end VSS.

[0294] The fourth initialization circuit comprises a tenth transistor T10.

[0295] The gate of the tenth transistor T10 is electrically connected with the second reset end RSTH, the source of the tenth transistor T10 is electrically connected with the third initial voltage end I3, and the drain of the tenth transistor T10 is electrically connected with the second node N2.

[0296] In at least one embodiment of the pixel circuit shown in FIG. 11A, T1 is an n-type transistor, T0, T2, T3, T4, T5, T6, T7, T8, T9 and T10 are p-type transistors; T1 is an Oxide TFT.

[0297] T1 is a transistor sensitive to threshold voltage.

[0298] As shown in FIG. 12, when at least one embodiment of the pixel circuit shown in FIG. 11A of the present disclosure works, the display period can include a first reset stage t0, a compensation stage t1, a second reset stage t4, a data writing stage t3, a third reset stage t6 and a light-emitting stage t5 arranged in sequence;

[0299] In the first reset stage t0, the NGT provides a high voltage signal, the SC1 provides a low voltage signal, the T4 is turned on, the first initial voltage Vinit1 provided by the I1 is written to the N1, and the C2 maintains the potential of the N1;

[0300] In the compensation stage t1, the NGT provides a high voltage signal, the SC1 provides a high voltage signal, the SC2 provides a low voltage signal, the T2 and the T3 are opened, the high voltage signal provided by the NGT passes through the T3, the T1 and the T2, and the potential of the NC is pulled high, when the potential of the NC is Vngt+Vth1, the T1 is closed, and the C1 maintains the potential of the NC; Vngt is the potential of the first gate driving signal provided by the NGT, and Vth is the threshold voltage of the T1;

[0301] In the second reset stage t4, the SC1 and the SC2 provide high voltage signals, the RSTP provides a low voltage signal, the T8 is opened, the I1 provides a first initial voltage Vinit1 to the N3, the T1 is opened, and the potential of the N1 is reset by the Vinit1;

[0302] In the data writing stage t3, the PGT provides a low voltage signal, the T5 is opened, the DL provides a data voltage Vdata to the N2, and the T1 is opened;

[0303] At the beginning of the data writing stage t3, the T0 is opened, the C2 is charged by the Vdata, the potential of the N1 is changed, until the potential of the N1 becomes Vdata+Vth, Vth is the threshold voltage of the T0, and the T0 is closed;

[0304] After the data writing stage t3, when the potential of the first gate driving signal provided by the NGT jumps low, the potential of the NC is pulled low by the C1, the potential of the NC is equal to Vngt+Vth1+△V×C1z / CNC, the potential of the NC always contains Vth1, therefore, the opening state of the T1 is not affected by the threshold voltage of the T1, and the purpose of compensating the threshold voltage of the T1 is achieved; wherein,△V is the change value of the potential of the first gate signal, Cz1 is the capacitance value of the C1, and CNC is the total capacitance of the NC;

[0305] In the third reset stage t6, the RSTH provides a low voltage signal, the T10 and the T9 are opened, the I2 provides a second initial voltage Vinit2 to the anode of the O1, and the residual charge of the anode of the O1 is cleared; the I3 provides a third initial voltage Vinit3 to the N2, and the hysteresis phenomenon of the T0 is improved;

[0306] In the light emitting stage t5, the EM provides a low voltage signal, the T6 and the T7 are opened, and the T0 drives the O1 to emit light.

[0307] As shown in FIG. 11B, on the basis of at least one embodiment of the pixel circuit shown in FIG. 7B, the driving circuit comprises the driving transistor T0, the compensation control circuit comprises the first transistor T1, the first energy storage circuit comprises the first capacitor C1, the first control circuit comprises the second transistor T2, the second control circuit comprises the third transistor T3, and the light emitting element is the organic light emitting diode O1.

[0308] The gate of the driving transistor T0 is electrically connected with the first node N1, the source of the driving transistor T0 is electrically connected with the second node N2, and the drain of the driving transistor T0 is electrically connected with the third node N3;

[0309] The gate of the first transistor T1 is electrically connected with the control node NC, the source of the first transistor T1 is electrically connected with the first node N1, and the drain of the first transistor T1 is electrically connected with the third node N3;

[0310] The first end of the first capacitor C1 is electrically connected with the control node NC, and the second end of the first capacitor C1 is electrically connected with the first gate drive end NGT;

[0311] The gate of the second transistor T2 is electrically connected with the first scan end SC1, the source of the second transistor T2 is electrically connected with the first node N1, and the drain of the second transistor T2 is electrically connected with the control node NC;

[0312] The gate of the third transistor T3 is electrically connected with the first scan end SC1, the source of the third transistor T3 is electrically connected with the third node N3, and the drain of the third transistor T3 is electrically connected with the first gate drive end NGT;

[0313] The data write circuit comprises a fifth transistor T5, and the second energy storage circuit comprises a second capacitor C2;

[0314] The gate of the fifth transistor T5 is electrically connected with the second gate drive end PGT, the source of the fifth transistor T5 is electrically connected with the data line DL, and the drain of the fifth transistor T5 is electrically connected with the second node N2;

[0315] The first end of the second capacitor C2 is electrically connected with the first node N1, and the second end of the second capacitor C2 is electrically connected with the power voltage end VDD;

[0316] The first light-emitting control circuit comprises a sixth transistor T6, and the second light-emitting control circuit comprises a seventh transistor T7;

[0317] The gate of the sixth transistor T6 is electrically connected with the light-emitting control end EM, the source of the sixth transistor T6 is electrically connected with the power voltage end VDD, and the drain of the sixth transistor T6 is electrically connected with the second node N2;

[0318] The gate of the seventh transistor T7 is electrically connected with the light-emitting control end EM, the source of the seventh transistor T7 is electrically connected with the third node N3, and the drain of the seventh transistor T7 is electrically connected with the anode of the organic light-emitting diode O1;

[0319] The second initialization circuit comprises an eighth transistor T8;

[0320] A gate of the eighth transistor T8 is electrically connected with the first reset end RSTP, a source of the eighth transistor T8 is electrically connected with the first initial voltage end I1, and a drain of the eighth transistor T8 is electrically connected with the first node N1.

[0321] The third initialization circuit comprises a ninth transistor T9;

[0322] A gate of the ninth transistor T9 is electrically connected with the second reset end RSTH, a source of the ninth transistor T9 is electrically connected with the second initial voltage end I2, and a drain of the ninth transistor T9 is electrically connected with an anode of the organic light-emitting diode O1; a cathode of O1 is electrically connected with the low voltage end VSS.

[0323] The fourth initialization circuit comprises a tenth transistor T10;

[0324] A gate of the tenth transistor T10 is electrically connected with the second reset end RSTH, a source of the tenth transistor T10 is electrically connected with the third initial voltage end I3, and a drain of the tenth transistor T10 is electrically connected with the second node N2.

[0325] The third energy storage circuit comprises a third capacitor C3, the third control circuit comprises an eleventh transistor T11, and the fourth control circuit comprises a twelfth transistor T12.

[0326] A first end of the third capacitor is electrically connected with the intermediate node NZ, and a second end of the third capacitor is electrically connected with the first reset end RSTP.

[0327] A gate of the eleventh transistor is electrically connected with the first scan end SC1, a source of the eleventh transistor T11 is electrically connected with the first initial voltage end I1, and a drain of the eleventh transistor T11 is electrically connected with the intermediate node NZ.

[0328] A gate of the twelfth transistor T12 is electrically connected with the first scan end SC1, a source of the twelfth transistor T12 is electrically connected with the first node N1, and a drain of the twelfth transistor T12 is electrically connected with the first reset end RSTP.

[0329] In at least one embodiment of the pixel circuit shown in FIG. 11B, T1 and T8 are n-type transistors, and the transistors other than T1 and T8 are p-type transistors; T1 and T8 are oxide transistors.

[0330] As shown in FIG. 8B, in at least one embodiment of the pixel circuit shown in FIG. 11B,

[0331] The display period can include a compensation stage t1, a first reset stage t2, a data writing stage t3, a second reset stage t4 and a light emitting stage t5 arranged in sequence;

[0332] In the compensation stage t1, the NGT provides a high voltage signal, the SC1 provides a low voltage signal, the T2 and the T3 are opened, the high voltage signal provided by the NGT passes through the T3, the T1 and the T2, and the potential of the NC is pulled high, when the potential of the NC is Vngt+Vth1, the T1 is closed, the C1 maintains the potential of the NC, so as to be able to compensate the threshold voltage of the T1; wherein, Vngt is the voltage value of the voltage signal provided by the NGT, Vth1 is the threshold voltage of the T1; the T11 and the T12 are opened, the high voltage provided by the NGT passes through the T12, the T8 and the T11, and the potential of the NZ is pulled high; when the potential of the NZ is Vrstp+Vth8, the T8 is closed, the C3 maintains the potential of the NZ, so as to be able to compensate the threshold voltage of the T8, wherein, Vrstp is the voltage value of the voltage signal provided by the RSTP, Vth8 is the threshold voltage of the T8;

[0333] In the first reset stage t2, the NGT provides a high voltage signal, the SC1 provides a high voltage signal, the RSTP provides a high voltage signal, the T8 is opened, and Vinit1 is written to N1 to reset the potential of N1;

[0334] In the data writing stage t3, the NGT provides a high voltage signal, the PGT provides a low voltage signal, the T5 is opened, the DL provides a data voltage Vdata to N2, and the T1 is turned on;

[0335] At the beginning of the data writing stage t3, the T0 is turned on, Vdata charges the C2 through the T5, the T0 and the T1, changes the potential of N1, and until the potential of N1 becomes Vdata+Vth, Vth is the threshold voltage of the T0, and the T0 is closed;

[0336] After the data writing stage t3, when the potential of the first gate driving signal provided by the NGT jumps low, the potential of the NC is pulled low by the C1, the potential of the NC is equal to Vngt+Vth1+△V×C1z / CNC, the potential of the NC always contains Vth1, therefore, the opening state of the T1 is not affected by the threshold voltage of the T1, and the threshold voltage compensation of the T1 is achieved; wherein, △V is the change value of the potential of the first gate signal, Cz1 is the capacitance value of the C1, and CNC is the total capacitance of the NC;

[0337] In the second reset stage t4, the RSTH provides a low voltage signal, the T9 and the T10 are opened, the I2 provides a second initial voltage Vinit2 to the anode of O1 to clear the residual charge of the anode of O1, and the I3 provides a third initial voltage Vinit3 to N2 to improve the hysteresis phenomenon of the T0;

[0338] In the light emitting stage t5, the EM provides a low voltage signal, T6 and T7 are turned on, and TO drives O1 to emit light.

[0339] The display device provided in the embodiments of the present disclosure includes the pixel circuit described above.

[0340] The above is the preferred embodiment of the present disclosure, it should be pointed out that, for those skilled in the art, without departing from the principles of the present disclosure, can also make a number of improvements and refinements, these improvements and refinements should also be considered as the protection scope of the present disclosure.

Claims

1. A pixel circuit, comprising a driving circuit, a compensation control circuit, a first energy storage circuit, a first control circuit and a second control circuit; a control terminal of the driving circuit is electrically connected with a first node, a first terminal of the driving circuit is electrically connected with a second node, a second terminal of the driving circuit is electrically connected with a third node, and the driving circuit is configured to generate a driving current under the control of the potential of the first node; the compensation control circuit is electrically connected with a control node, the first node and the third node respectively, and is configured to control the communication between the first node and the third node under the control of the potential of the control node; a first terminal of the first energy storage circuit is electrically connected with the control node, and a second terminal of the first energy storage circuit is electrically connected with a first gate driving terminal, and the first energy storage circuit is configured to store energy; the first control circuit is electrically connected with a first control terminal, the first node and the control node respectively, and is configured to control the communication between the first node and the control node under the control of a first control signal provided by the first control terminal; the second control circuit is electrically connected with a second control terminal, the third node and the first gate driving terminal respectively, and is configured to control the communication between the third node and the first gate driving terminal under the control of a second control signal provided by the second control terminal.

2. The pixel circuit of claim 1, wherein, The first control terminal and the second control terminal are both first scan terminals.

3. The pixel circuit of claim 1, wherein, The first control terminal is a first scan terminal, and the second control terminal is a second scan terminal.

4. The pixel circuit of claim 1, wherein, Further comprising a first initialization circuit; the first initialization circuit is electrically connected with a first scan terminal, a first initial voltage terminal and the control node respectively, and is configured to write a first initial voltage provided by the first initial voltage terminal into the control node under the control of a first scan signal provided by the first scan terminal; The first control terminal and the second control terminal are second scan terminals.

5. The pixel circuit of any one of claims 1 to 4, wherein, The transistor included in the compensation control circuit is an oxide transistor, and the transistor included in the first control circuit and the transistor included in the second control circuit are low-temperature polysilicon transistors.

6. The pixel circuit of any one of claims 1 to 4, wherein, Further comprising a data writing circuit and a second energy storage circuit; the data writing circuit is electrically connected with a second gate driving terminal, a data line and the second node respectively, and is configured to write a data voltage provided by the data line into the second node under the control of a second gate driving signal provided by the second gate driving terminal; the second energy storage circuit is electrically connected with the first node, and is configured to maintain the potential of the first node.

7. The pixel circuit of any one of claims 1 to 4, wherein, Further comprising a light emitting element, a first light emitting control circuit and a second light emitting control circuit; the first light emitting control circuit is electrically connected with a light emitting control terminal, a power voltage terminal and the second node respectively, and is configured to control the communication between the power voltage terminal and the second node under the control of a light emitting control signal provided by the light emitting control terminal; the second light emitting control circuit is electrically connected with a light emitting control terminal, the third node and a first pole of the light emitting element respectively, and is configured to control the communication between the third node and the first pole of the light emitting element under the control of the light emitting control signal; a second pole of the light emitting element is electrically connected with a first voltage terminal.

8. The pixel circuit of claim 7, wherein, The second initialization circuit is further included; The second initialization circuit is electrically connected with the first reset end, the first initial voltage end and the third node respectively, and is used for writing the first initial voltage provided by the first initial voltage end into the third node under the control of the first reset control signal provided by the first reset end.

9. The pixel circuit of claim 7, wherein, The second initialization circuit is further included; The second initialization circuit is electrically connected with the first reset end, the first initial voltage end and the third node respectively, and is used for writing the first initial voltage provided by the first initial voltage end into the third node under the control of the first reset control signal provided by the first reset end.

10. The pixel circuit of claim 7, wherein, The third initialization circuit is further included; The third initialization circuit is electrically connected with the second reset end, the second initial voltage end and the first pole of the light-emitting element respectively, and is used for writing the second initial voltage provided by the second initial voltage end into the first pole of the light-emitting element under the control of the second reset control signal provided by the second reset end.

11. The pixel circuit of claim 7, wherein, The fourth initialization circuit is further included; The fourth initialization circuit is electrically connected with the second reset end, the third initial voltage end and the second node respectively, and is used for writing the third initial voltage provided by the third initial voltage end into the second node under the control of the second reset control signal provided by the second reset end.

12. The pixel circuit of claim 9, wherein, The third energy storage circuit, the third control circuit and the fourth control circuit are further included; The first end of the third energy storage circuit is electrically connected with the intermediate node, and the second end of the third energy storage circuit is electrically connected with the first reset end, and the third energy storage circuit is used for storing electric energy; The third control circuit is electrically connected with the first control end, the first initial voltage end and the intermediate node respectively, and is used for controlling the communication between the first initial voltage end and the intermediate node under the control of the first control signal; The fourth control circuit is electrically connected with the second control end, the first node and the first reset end respectively, and is used for controlling the communication between the first node and the first reset end under the control of the second control signal.

13. The pixel circuit of claim 1, wherein, The driving circuit includes a driving transistor, the compensation control circuit includes a first transistor, and the first energy storage circuit includes a first capacitor; the first control circuit includes a second transistor, and the second control circuit includes a third transistor; The gate of the driving transistor is electrically connected with the first node, the first pole of the driving transistor is electrically connected with the second node, and the second pole of the driving transistor is electrically connected with the third node; The gate of the first transistor is electrically connected with the control node, the first pole of the first transistor is electrically connected with the first node, and the second pole of the first transistor is electrically connected with the third node; The first end of the first capacitor is electrically connected with the control node, and the second end of the first capacitor is electrically connected with the first gate driving end; The gate of the second transistor is electrically connected with the first control end, the first pole of the second transistor is electrically connected with the first node, and the second pole of the second transistor is electrically connected with the control node; A gate of the third transistor is electrically connected with the second control end, a first electrode of the third transistor is electrically connected with the third node, and a second electrode of the third transistor is electrically connected with the first gate driving end.

14. The pixel circuit of claim 4, wherein, The first initialization circuit comprises a fourth transistor; A gate of the fourth transistor is electrically connected with the first scanning end, a first electrode of the fourth transistor is electrically connected with the first initial voltage end, and a second electrode of the fourth transistor is electrically connected with the control node.

15. The pixel circuit of claim 6, wherein, The data writing circuit comprises a fifth transistor, and the second energy storage circuit comprises a second capacitor; A gate of the fifth transistor is electrically connected with the second gate driving end, a first electrode of the fifth transistor is electrically connected with the data line, and a second electrode of the fifth transistor is electrically connected with the second node; A first end of the second capacitor is electrically connected with the first node, and a second end of the second capacitor is electrically connected with a direct current voltage end.

16. The pixel circuit of claim 7, wherein, The first light emitting control circuit comprises a sixth transistor, and the second light emitting control circuit comprises a seventh transistor; A gate of the sixth transistor is electrically connected with the light emitting control end, a first electrode of the sixth transistor is electrically connected with the power voltage end, and a second electrode of the sixth transistor is electrically connected with the second node; A gate of the seventh transistor is electrically connected with the light emitting control end, a first electrode of the seventh transistor is electrically connected with the third node, and a second electrode of the seventh transistor is electrically connected with a first electrode of the light emitting element.

17. The pixel circuit of claim 8, wherein, The second initialization circuit comprises an eighth transistor; A gate of the eighth transistor is electrically connected with the first reset end, a first electrode of the eighth transistor is electrically connected with the first initial voltage end, and a second electrode of the eighth transistor is electrically connected with the third node.

18. The pixel circuit of claim 9, wherein, The second initialization circuit comprises an eighth transistor; A gate of the eighth transistor is electrically connected with the first reset end, a first electrode of the eighth transistor is electrically connected with the first initial voltage end, and a second electrode of the eighth transistor is electrically connected with the first node.

19. The pixel circuit of claim 10, wherein, The third initialization circuit comprises a ninth transistor; A gate of the ninth transistor is electrically connected with the second reset end, a first electrode of the ninth transistor is electrically connected with the second initial voltage end, and a second electrode of the ninth transistor is electrically connected with a first electrode of the light emitting element.

20. The pixel circuit of claim 11, wherein, The fourth initialization circuit comprises a tenth transistor; A gate of the tenth transistor is electrically connected with the second reset end, a first electrode of the tenth transistor is electrically connected with the third initial voltage end, and a second electrode of the tenth transistor is electrically connected with the second node.

21. The pixel circuit of claim 12, wherein, The third energy storage circuit comprises a third capacitor, the third control circuit comprises an eleventh transistor, and the fourth control circuit comprises a twelfth transistor; A first end of the third capacitor is electrically connected with the intermediate node, and a second end of the third capacitor is electrically connected with the first reset end; A gate of the eleventh transistor is electrically connected with the first control end, a first electrode of the eleventh transistor is electrically connected with the first initial voltage end, and a second electrode of the eleventh transistor is electrically connected with the intermediate node; The gate of the twelfth transistor is electrically connected with the second control end, the first pole of the twelfth transistor is electrically connected with the first node, and the second pole of the twelfth transistor is electrically connected with the first reset end.

22. A display device comprising the pixel circuit according to any one of claims 1 to 21.

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