Display panel and display apparatus

Abstract

Provided in the present disclosure are a display panel and a display apparatus. The display panel comprises pixel circuits arranged in a plurality of rows and columns. Each pixel circuit comprises a data write circuit, wherein the data write circuit accesses a data voltage under the control of a scanning signal; a transistor comprised in the data write circuit comprises a first gate electrode and a second gate electrode, a scanning end comprising a first scanning end and a second scanning end, the first gate electrode of the transistor comprised in the data write circuit being electrically connected to the first scanning end, and the second gate electrode of the transistor comprised in the data write circuit being electrically connected to the second scanning end. The first gate electrode is a top gate, and the second gate electrode is a bottom gate; or, the first gate electrode is a bottom gate, and the second gate electrode is a top gate. The present disclosure can mitigate flickering during low-frequency display.

Description

Display panel and display device

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Chinese Patent Application No. 202410822732.2, filed on June 24, 2024, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0004] In the related art, as the demand for low frequency of display products increases, Flicker as one of the important criteria for evaluating low frequency is increasingly concerned, and how to reduce Flicker has become the main problem of the current researchers. The main reasons for Flicker failing to meet customer criteria are ①△Vp (△Vp is the change value of pixel voltage) is large, resulting in large Flicker value; ②the uniformity of in-plane common electrode voltage Vcom is poor, resulting in poor uniformity of in-plane Flicker. SUMMARY

[0005] The main purpose of the present disclosure is to provide a display panel and a display device to solve the flicker phenomenon of related display products when displaying at low frequency.

[0006] In one aspect, the display panel provided by the embodiments of the present disclosure includes a plurality of rows and columns of pixel circuits; the pixel circuit includes a data writing circuit;

[0007] The data writing circuit is electrically connected with a scanning end and a data line respectively, and is used to access a data voltage provided by the data line under the control of a scanning signal provided by the scanning end;

[0008] The transistor included in the data writing circuit includes a first gate and a second gate, and the scanning end includes a first scanning end and a second scanning end;

[0009] The first gate of the transistor included in the data writing circuit is electrically connected with the first scanning end, and the second gate of the transistor included in the data writing circuit is electrically connected with the second scanning end;

[0010] The first gate is a top gate, and the second gate is a bottom gate; or, the first gate is a bottom gate, and the second gate is a top gate.

[0011] Optionally, when the potential of a first scanning signal provided by the first scanning end decreases, the potential of a second scanning signal provided by the second scanning end increases;

[0012] When a potential of a first scanning signal provided by the first scanning end rises, a potential of a second scanning signal provided by the second scanning end falls.

[0013] Optionally, the display panel further comprises a driving module, wherein the driving module comprises a plurality of driving circuits.

[0014] The driving circuit comprises a first scanning signal output end and a second scanning signal output end.

[0015] The first scanning signal output end of the nth driving circuit of the driving module is electrically connected to a first scanning end of a data writing circuit in the nth row of pixel circuits.

[0016] The second scanning signal output end of the nth driving circuit of the driving module is electrically connected to a second scanning end of a data writing circuit in the nth row of pixel circuits.

[0017] Optionally, the driving circuit comprises a first node control circuit, a second node control circuit, a first scanning signal output circuit and a second scanning signal output circuit.

[0018] The first node control circuit is electrically connected to the first node and is configured to control a potential of the first node.

[0019] The second node control circuit is electrically connected to the second node and is configured to control a potential of the second node.

[0020] The first scanning signal output circuit is electrically connected to the first node, the second node, an output clock signal end, a first voltage end and the first scanning signal output end, respectively, and is configured to, under control of the potential of the first node, control the first scanning signal output end to be in communication with the output clock signal end, and under control of the potential of the second node, control the first scanning signal output end to be in communication with the first voltage end.

[0021] The second scanning signal output circuit is electrically connected to the first node, the first scanning signal output end, a second scanning signal output end, a first voltage end and a second voltage end, respectively, and is configured to, under control of the potential of the first node, control the second scanning signal output end to be in communication with the second voltage end, and under control of a first scanning signal provided by the first scanning signal output end, control the second scanning signal output end to be in communication with the first voltage end.

[0022] The first voltage end provides a first voltage signal, and a voltage value of the first voltage signal is less than a voltage value of a second voltage signal provided by the second voltage end.

[0023] Optionally, the first scan signal output circuit includes a first output transistor and a second output transistor;

[0024] The gate of the first output transistor is electrically connected with the first node, the first pole of the first output transistor is electrically connected with the output clock signal end, and the second pole of the first output transistor is electrically connected with the first scan signal output end.

[0025] The gate of the second output transistor is electrically connected with the second node, the first pole of the second output transistor is electrically connected with the first scan signal output end, and the second pole of the second output transistor is electrically connected with the first voltage end.

[0026] Optionally, the second scan signal output circuit includes a third output transistor and a fourth output transistor;

[0027] The gate of the third output transistor is electrically connected with the first node, the first pole of the third output transistor is electrically connected with the second scan signal output end, and the second pole of the third output transistor is electrically connected with the second voltage end.

[0028] The gate of the fourth output transistor is electrically connected with the first scan signal output end, the first pole of the fourth output transistor is electrically connected with the second scan signal output end, and the second pole of the fourth output transistor is electrically connected with the first voltage end.

[0029] Optionally, the display panel further includes a substrate, and the pixel circuit is arranged on the substrate.

[0030] The top gate of the transistor included in the data write circuit does not overlap with the connection electrode of the transistor included in the data write circuit in the orthographic projection on the substrate.

[0031] The connection electrode of the transistor included in the data write circuit includes the source of the transistor included in the data write circuit and the drain of the transistor included in the data write circuit.

[0032] Optionally, the display panel further includes a substrate, and the pixel circuit is arranged on the substrate.

[0033] The overlapping area between the top gate of the transistor included in the data write circuit and the connection electrode of the transistor included in the data write circuit in the orthographic projection on the substrate is a first area.

[0034] A second area is formed between a normal projection of a bottom gate of a transistor included in the data writing circuit on the substrate and a normal projection of a connection electrode of a transistor included in the data writing circuit on the substrate.

[0035] The first area is smaller than the second area.

[0036] The connection electrode of the transistor included in the data writing circuit includes a source of the transistor included in the data writing circuit and a drain of the transistor included in the data writing circuit.

[0037] Optionally, the display panel according to any one of the embodiments of the present disclosure further includes a substrate, a light shielding metal layer, a semiconductor layer and a gate metal layer.

[0038] The light shielding metal layer, the semiconductor layer and the gate metal layer are arranged in sequence along a direction away from the substrate.

[0039] The semiconductor layer includes a channel of a transistor included in the data writing circuit, and a normal projection of the light shielding metal layer on the substrate covers a normal projection of the channel on the substrate.

[0040] The light shielding metal layer includes the bottom gate, and the gate metal layer includes the top gate.

[0041] Optionally, the display panel according to any one of the embodiments of the present disclosure further includes a plurality of rows and columns of touch electrode blocks, a plurality of columns of signal transmission lines and a voltage providing circuit; the plurality of rows and columns of touch electrode blocks are independent of each other.

[0042] The voltage providing circuit is electrically connected with a first end of the signal transmission line, the signal transmission line includes a connection point, and the connection point is electrically connected with the touch electrode block.

[0043] The voltage providing circuit is configured to provide a corresponding common electrode voltage to the signal transmission line according to a resistance between the first end of the signal transmission line and the connection point of the signal transmission line in a display stage.

[0044] Optionally, the display panel according to any one of the embodiments of the present disclosure further includes a common electrode layer and a detection integrated circuit.

[0045] The common electrode layer includes a plurality of common electrode portions, and the plurality of common electrode portions are in communication with each other.

[0046] The common electrode portion includes at least one detection point.

[0047] The detection integrated circuit is electrically connected with the common electrode part through the detection point, and is configured to detect a potential of the detection point in a detection stage; and the detection integrated circuit is further configured to obtain a corresponding compensation voltage signal according to the potential of the detection point and a target common electrode voltage signal.

[0048] Optionally, the detection point is directly electrically connected with the detection integrated circuit.

[0049] Optionally, the common electrode layer includes a plurality of rows and columns of common electrode parts; the display panel includes a display area and a peripheral area, and the pixel circuit is arranged in the display area.

[0050] The detection point extends to the peripheral area through a first connection line extending in a row direction, and the first connection line is electrically connected with the detection integrated circuit through a second connection line arranged in the peripheral area.

[0051] Optionally, the display panel further includes a switch control module, and the switch control module includes a plurality of switch control circuits.

[0052] The control end of the switch control circuit is electrically connected with the corresponding switch control end, the first end of the switch control circuit is electrically connected with the detection integrated circuit, and the second end of the switch control circuit is electrically connected with the detection point; and the switch control circuit is configured to control the communication between the detection integrated circuit and the detection point in a corresponding detection stage included in a detection period.

[0053] The detection integrated circuit is configured to detect the potential of the detection point in the corresponding detection stage.

[0054] Optionally, the switch control circuit is configured to control the communication between the detection integrated circuit and the detection point in a corresponding compensation stage included in a compensation period.

[0055] The detection integrated circuit is configured to transmit a corresponding compensation voltage signal to the corresponding common electrode part through the switch control circuit in the corresponding compensation stage.

[0056] Optionally, the common electrode layer includes N rows and 2M columns of common electrode parts; N and M are positive integers; the display panel further includes a first switch control module and a second switch control module; the first switch control module includes N first switch control units, and the second switch control module includes N second switch control units.

[0057] The first switch control unit includes M first switch control circuits, and the second switch control unit includes M second switch control circuits.

[0058] The display panel comprises a display area and a peripheral area, the pixel circuit is arranged in the display area, and the first switch control module and the second switch control module are arranged in the peripheral area; the first switch control module is arranged at a first side of the display area, the second switch control module is arranged at a second side of the display area, and the first side and the second side are opposite sides;

[0059] The mth first switch control circuit in the nth first switch control unit is electrically connected with the nth first switch control end, the detection integrated circuit and the nth row and mth column common electrode part respectively, and is used for controlling communication between the detection integrated circuit and a detection point included in the nth row and mth column common electrode part under control of a switch control signal provided by the nth first switch control end;

[0060] The mth second switch control circuit in the nth second switch control unit is electrically connected with the nth second switch control end, the detection integrated circuit and the nth row and M+mth column common electrode part respectively, and is used for controlling communication between the detection integrated circuit and a detection point included in the nth row and M+mth column common electrode part under control of a switch control signal provided by the nth second switch control end;

[0061] N is a positive integer less than or equal to N; and m is a positive integer less than or equal to M.

[0062] Optionally, the common electrode part comprises a plurality of parts arranged in sequence along a first direction.

[0063] The detection point of the nth row and mth column common electrode part is included in an ath part included in the nth row and mth column common electrode part.

[0064] The detection point of the nth row and M+mth column common electrode part is included in a bth part included in the nth row and M+mth column common electrode part.

[0065] a and b are both positive integers, and a is not equal to b.

[0066] Optionally, the display panel further comprises a first switch control signal generation module and a second switch control signal generation module arranged in the peripheral area; the first switch control signal generation module is arranged at a first side of the display area, and the second switch control signal generation module is arranged at a second side of the display area.

[0067] The first switch control signal generation module is electrically connected with N first switch control ends respectively, and is used for providing an effective switch control signal to the nth first switch control end in an nth detection stage included in a detection period.

[0068] The second switch control signal generation module is electrically connected with N second switch control ends respectively, and is configured to provide an effective switch control signal to the nth second switch control end in the nth detection stage included in the detection period.

[0069] The detection integrated circuit is configured to detect the potential of the detection point included in the common electrode part in the nth detection stage.

[0070] Optionally, the first switch control signal generation module is electrically connected with N first switch control ends respectively, and is configured to provide an effective switch control signal to the nth first switch control end in the nth compensation stage included in the compensation period.

[0071] The second switch control signal generation module is electrically connected with N second switch control ends respectively, and is configured to provide an effective switch control signal to the nth second switch control end in the nth compensation stage included in the compensation period.

[0072] The detection integrated circuit is configured to transmit the corresponding compensation voltage signal to the corresponding common electrode part in the nth compensation stage.

[0073] Optionally, the display panel provided in the embodiments of the present disclosure further comprises a voltage supply circuit and a plurality of signal transmission lines.

[0074] The voltage supply circuit is electrically connected with the common electrode part through the signal transmission line, and is configured to provide the compensation voltage signal to the signal transmission line in the compensation stage.

[0075] In a second aspect, the display device provided in the embodiments of the present disclosure comprises the display panel described above.

[0076] In the display panel and the display device provided in the embodiments of the present disclosure, the first gate of the transistor included in the data writing circuit is electrically connected with the first scan end, and the second gate of the transistor included in the data writing circuit is electrically connected with the second scan end, so that the coupling of the scanning signal to the data voltage on the data line is reduced to reduce the △Vp and improve the Flicker phenomenon. BRIEF DESCRIPTION OF DRAWINGS

[0077] FIG. 1A is a circuit diagram of at least one embodiment of a data writing circuit;

[0078] FIG. 1B is a working timing diagram of at least one embodiment of the data writing circuit shown in FIG. 1A;

[0079] FIG. 2 is a circuit diagram of at least one embodiment of a data writing circuit;

[0080] FIG. 3 is a structural diagram of at least one embodiment of a driving circuit in the display panel provided in the present disclosure;

[0081] FIG. 4A is a structural diagram of at least one embodiment of a driving circuit in a display panel according to the present disclosure;

[0082] FIG. 4B is a diagram showing the relationship between the ratio of the channel width-length ratio of the fourth output transistor to the channel width-length ratio of the third output transistor (width-length ratio ratio) and the Flicer value when at least one embodiment of the driving circuit in the display panel according to the present disclosure is in operation;

[0083] FIG. 5 is a circuit diagram of at least one embodiment of a driving circuit in a display panel according to the present disclosure;

[0084] FIGS. 6 and 7 are cross-sectional views of at least one embodiment of a display panel;

[0085] FIGS. 8 and 9 are cross-sectional views of at least one embodiment of a display panel;

[0086] FIGS. 10 and 11 are cross-sectional views of at least one embodiment of a display panel;

[0087] FIG. 12A is a diagram showing a touch electrode block included in a display panel according to at least one embodiment of the present disclosure;

[0088] FIG. 12B is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0089] FIG. 13 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0090] FIG. 14 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0091] FIG. 15 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0092] FIG. 16 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0093] FIG. 17 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0094] FIG. 18 is a structural diagram of a common electrode portion;

[0095] FIG. 19 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0096] FIG. 20 is a structural diagram of a display panel according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0097] With reference to the drawings and embodiments of the present disclosure, the technical solutions in the embodiments of the present disclosure will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present disclosure.

[0098] The transistor used in all embodiments of the present disclosure can be a thin film transistor or a field effect transistor or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two poles of the transistor except the gate, one pole is called the first pole and the other pole is called the second pole.

[0099] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0100] The display panel described in the embodiments of the present disclosure includes a plurality of rows and columns of pixel circuits; the pixel circuit includes a data writing circuit;

[0101] The data writing circuit is electrically connected with a scanning end and a data line respectively, and is used to access a data voltage provided by the data line under the control of a scanning signal provided by the scanning end;

[0102] The transistor included in the data writing circuit includes a first gate and a second gate, and the scanning end includes a first scanning end and a second scanning end;

[0103] The first gate of the transistor included in the data writing circuit is electrically connected with the first scanning end, and the second gate of the transistor included in the data writing circuit is electrically connected with the second scanning end;

[0104] The first gate is a top gate and the second gate is a bottom gate, or the first gate is a bottom gate and the second gate is a top gate.

[0105] In the display panel described in the embodiments of the present disclosure, the first gate of the transistor included in the data writing circuit is electrically connected with the first scanning end, and the second gate of the transistor included in the data writing circuit is electrically connected with the second scanning end, so as to reduce the coupling of the scanning signal to the data voltage on the data line to reduce ΔVp and improve the Flicker phenomenon; wherein ΔVp is the change value of the pixel voltage, and the pixel voltage is the data voltage accessed by the pixel circuit.

[0106] In at least one embodiment of the present disclosure, when the potential of the first scanning signal provided by the first scanning end decreases, the potential of the second scanning signal provided by the second scanning end increases;

[0107] When the potential of the first scan signal provided by the first scan end rises, the potential of the second scan signal provided by the second scan end falls.

[0108] In a specific implementation, when the potential of the first scan signal falls, the potential of the second scan signal rises; when the potential of the first scan signal rises, the potential of the second scan signal falls; and the change in the potential of the second gate of the transistor included in the data write circuit can offset the change in the potential of the first gate of the transistor included in the data write circuit, so as to offset ΔVp.

[0109] As shown in FIG. 1A, at least one embodiment of the data write circuit can include a data write transistor T0.

[0110] The top gate of T0 is electrically connected with the first scan end G1, and the bottom gate of T0 is electrically connected with the second scan end G2.

[0111] The source of T0 is denoted as S, and the drain of T0 is denoted as D.

[0112] As shown in FIG. 1B, at least one embodiment of the data write circuit shown in FIG. 1A, when G1 provides a high voltage signal, G2 provides a first low voltage signal LVGL in operation.

[0113] When G1 provides the first low voltage signal LVGL, G2 provides a second low voltage signal VGL.

[0114] The voltage value of the first low voltage signal LVGL is less than the voltage value of the second low voltage signal VGL.

[0115] As shown in FIG. 2, the data write circuit can include a data write transistor T0.

[0116] The bottom gate of T0 is electrically connected with the first scan end G1, and the top gate of T0 is electrically connected with the second scan end G2.

[0117] The source of T0 is denoted as S, and the drain of T0 is denoted as D.

[0118] The source of T0 can be electrically connected with a data line and access a data voltage.

[0119] The display panel provided in at least one embodiment of the present disclosure further includes a driving module; the driving module includes a plurality of driving circuits;

[0120] The driving circuit includes a first scan signal output end and a second scan signal output end.

[0121] The first scan signal output end included in the nth driving circuit included in the driving module is electrically connected with the first scan end of the data write circuit in the nth row of pixel circuits.

[0122] The nth-stage driving circuit of the driving module includes a second scan signal output end electrically connected to a second scan end of the data write-in circuit in the nth-row pixel circuit.

[0123] In a specific implementation, the display panel further includes a driving module, which includes a first scan signal output end and a second scan signal output end, the first scan signal output end of the nth driving circuit is electrically connected to a first scan end of the data write-in circuit in the nth-row pixel circuit, and the second scan signal output end of the nth-stage driving circuit is electrically connected to a second scan end of the data write-in circuit in the nth-row pixel circuit.

[0124] In at least one embodiment of the present disclosure, the driving circuit includes a first node control circuit, a second node control circuit, a first scan signal output circuit, and a second scan signal output circuit.

[0125] The first node control circuit is electrically connected to the first node and is configured to control the potential of the first node.

[0126] The second node control circuit is electrically connected to the second node and is configured to control the potential of the second node.

[0127] The first scan signal output circuit is electrically connected to the first node, the second node, an output clock signal end, a first voltage end, and a first scan signal output end, respectively, and is configured to, under the control of the potential of the first node, control the first scan signal output end to be in communication with the output clock signal end, and under the control of the potential of the second node, control the first scan signal output end to be in communication with the first voltage end.

[0128] The second scan signal output circuit is electrically connected to the first node, the first scan signal output end, a second scan signal output end, a first voltage end, and a second voltage end, respectively, and is configured to, under the control of the potential of the first node, control the second scan signal output end to be in communication with the second voltage end, and under the control of a first scan signal provided by the first scan signal output end, control the second scan signal output end to be in communication with the first voltage end.

[0129] The voltage value of a first voltage signal provided by the first voltage end is less than the voltage value of a second voltage signal provided by the second voltage end.

[0130] In a specific implementation, the driving circuit comprises a first node control circuit, a second node control circuit, a first scan signal output circuit and a second scan signal output circuit; the first node control circuit controls the potential of the first node; the second node control circuit controls the potential of the second node; the first scan signal output circuit, under the control of the potential of the first node, controls the communication between the first scan signal output end and the output clock signal end, and under the control of the potential of the second node, controls the communication between the first scan signal output end and the first voltage end; the second scan signal output circuit, under the control of the potential of the first node, controls the communication between the second scan signal output end and the second voltage end, and under the control of the first scan signal provided by the first scan signal output end, controls the communication between the second scan signal output end and the first voltage end.

[0131] Optionally, the first voltage end can be a first low voltage end, and the second voltage end can be a second low voltage end.

[0132] As shown in FIG. 3, at least one embodiment of the driving circuit comprises a first node control circuit 31, a second node control circuit 32, a first scan signal output circuit 33 and a second scan signal output circuit 34;

[0133] The first node control circuit 31 is electrically connected with the first node PU, and is configured to control the potential of the first node PU;

[0134] The second node control circuit 32 is electrically connected with the second node PD, and is configured to control the potential of the second node PD;

[0135] The first scan signal output circuit 33 is electrically connected with the first node PU, the second node PD, an output clock signal end CLK, a first scan signal output end OT1 and a first low voltage end respectively, and is configured to, under the control of the potential of the first node PU, control the communication between the first scan signal output end OT1 and the output clock signal end CLK, and under the control of the potential of the second node PD, control the communication between the first scan signal output end OT1 and the first low voltage end;

[0136] The second scan signal output circuit 34 is electrically connected with the first node PU, the first scan signal output end OT1, a second scan signal output end OT2, a first low voltage end and a second low voltage end respectively, and is configured to, under the control of the potential of the first node PU, control the communication between the second scan signal output end OT2 and the second low voltage end, and under the control of the first scan signal provided by the first scan signal output end OT1, control the communication between the second scan signal output end OT2 and the first low voltage end;

[0137] The first low-voltage end is configured to provide a first low-voltage signal LVGL; and the second low-voltage end is configured to provide a second low-voltage signal VGL.

[0138] The voltage value of the first low-voltage signal LVGL is less than the voltage value of the second low-voltage signal VGL.

[0139] Optionally, the first scan signal output circuit comprises a first output transistor and a second output transistor.

[0140] The gate of the first output transistor is electrically connected to the first node, the first pole of the first output transistor is electrically connected to the output clock signal end, and the second pole of the first output transistor is electrically connected to the first scan signal output end.

[0141] The gate of the second output transistor is electrically connected to the second node, the first pole of the second output transistor is electrically connected to the first scan signal output end, and the second pole of the second output transistor is electrically connected to the first voltage end.

[0142] Optionally, the second scan signal output circuit comprises a third output transistor and a fourth output transistor.

[0143] The gate of the third output transistor is electrically connected to the first node, the first pole of the third output transistor is electrically connected to the second scan signal output end, and the second pole of the third output transistor is electrically connected to the second voltage end.

[0144] The gate of the fourth output transistor is electrically connected to the first scan signal output end, the first pole of the fourth output transistor is electrically connected to the second scan signal output end, and the second pole of the fourth output transistor is electrically connected to the first voltage end.

[0145] As shown in FIG. 4A, on the basis of at least one embodiment of the driving circuit shown in FIG. 3, the first scan signal output circuit comprises a first output transistor MO1 and a second output transistor MO2.

[0146] The gate of the first output transistor MO1 is electrically connected to the first node PU, the drain of the first output transistor MO1 is electrically connected to the output clock signal end CLK, and the source of the first output transistor MO1 is electrically connected to the first scan signal output end OT1.

[0147] The gate of the second output transistor MO2 is electrically connected with the second node PD, the drain of the second output transistor MO2 is electrically connected with the first scan signal output end OT1, and the source of the second output transistor MO2 is electrically connected with the first low voltage end for providing a first low voltage signal LVGL.

[0148] The second scan signal output circuit includes a third output transistor MO3 and a fourth output transistor MO4.

[0149] The gate of the third output transistor MO3 is electrically connected with the first node PU, the drain of the third output transistor MO3 is electrically connected with the second scan signal output end OT2, and the source of the third output transistor MO3 is electrically connected with the second low voltage end for providing a second low voltage signal VGL.

[0150] The gate of the fourth output transistor MO4 is electrically connected with the first scan signal output end OT1, the source of the fourth output transistor MO4 is electrically connected with the second scan signal output end OT2, and the drain of the fourth output transistor MO4 is electrically connected with the first low voltage end.

[0151] In at least one embodiment of the driving circuit shown in FIG. 4A, all the transistors are n-type transistors.

[0152] In at least one embodiment of the driving circuit shown in FIG. 4A, the channel width-length ratio of MO4 is greater than the channel width-length ratio of MO3.

[0153] In at least one embodiment of the present disclosure, the ratio between the channel width-length ratio of MO4 and the channel width-length ratio of MO3 can be greater than or equal to 10 and less than or equal to 30; for example, the ratio between the channel width-length ratio of MO4 and the channel width-length ratio of MO3 can be equal to 10, 20, 30, 15 or 25, more specifically, the ratio between the channel width-length ratio of MO4 and the channel width-length ratio of MO3 can be greater than or equal to 15 and less than or equal to 25; but not limited thereto.

[0154] In the specific implementation, the ratio between the channel width-length ratio of MO4 and the channel width-length ratio of MO3 is set to be relatively large, so that when both MO4 and MO3 are turned on, the first low voltage signal LVGL can be output by OT2;

[0155] And, the ratio between the channel width-length ratio of MO4 and the channel width-length ratio of MO3 can not be set too large, so as to prevent the channel width-length ratio of MO4 from being too large, thereby preventing the space occupied by MO4 from being too large, and facilitating the realization of narrow frame.

[0156] As shown in FIG. 4B, when the ratio (width-length ratio ratio) between the channel width-length ratio of MO4 and the channel width-length ratio of MO3 is 1, the Flicer value is -52.2 dB;

[0157] When the ratio between the channel width-length ratio of MO4 and the channel width-length ratio of MO3 is 2, the Flicer value is -52.2 dB;

[0158] When the ratio between the channel width-length ratio of MO4 and the channel width-length ratio of MO3 is 8, the Flicer value is -52.3 dB;

[0159] When the ratio between the channel width-length ratio of MO4 and the channel width-length ratio of MO3 is 10, the Flicer value is -56.6 dB;

[0160] When the ratio between the channel width-length ratio of MO4 and the channel width-length ratio of MO3 is 15, the Flicer value is -57.1 dB;

[0161] When the ratio between the channel width-length ratio of MO4 and the channel width-length ratio of MO3 is 20, the Flicer value is -57.7 dB;

[0162] When the ratio between the channel width-length ratio of MO4 and the channel width-length ratio of MO3 is 25, the Flicer value is -57.9 dB;

[0163] When the ratio between the channel width-length ratio of MO4 and the channel width-length ratio of MO3 is 30, the Flicer value is -58.1 dB.

[0164] As shown in FIG. 4B, when the ratio between the channel width-length ratio of MO4 and the channel width-length ratio of MO3 is greater than or equal to 10, the Flicer value decreases, and the flicker phenomenon can be improved.

[0165] At least one embodiment of the driving circuit shown in FIG. 4A works as follows:

[0166] When the potential of PU is a high voltage signal, and OT1 provides a high voltage signal, both MO3 and MO4 are opened, and since the channel width-length ratio of MO4 is greater than the channel width-length ratio of MO3, OT2 outputs the first low voltage signal LVGL.

[0167] When the potential of PU is a high voltage signal, and CLK provides a low voltage signal, MO3 is opened, MO1 is opened, OT2 outputs the second low voltage signal VGL, and OT1 outputs a low voltage signal; when CLK provides the first low voltage signal LVGL, OT1 outputs the first low voltage signal LVGL; and when CLK provides the second low voltage signal VGL, OT1 outputs the second low voltage signal VGL.

[0168] As shown in FIG. 5, on the basis of at least one embodiment of the driving circuit shown in FIG. 4A, the first node control circuit comprises a first transistor M1, a second transistor M2, a third transistor M3 and a fourth transistor M4;

[0169] The gate of M1 is electrically connected with the input end I1, the drain of M1 is electrically connected with the first scanning voltage end VDS, and the source of M1 is electrically connected with the first node PU;

[0170] The gate of M2 is electrically connected with the second node PD, the drain of M2 is electrically connected with the first node PU, and the source of M2 is electrically connected with the second low voltage end;

[0171] The gate of M3 is electrically connected with the reset end RST, the drain of M3 is electrically connected with the first node PU, and the source of M3 is electrically connected with the second scanning voltage end VSD;

[0172] The gate of M4 is electrically connected with the frame reset end STV0, the drain of M4 is electrically connected with the first node PU, and the source of M4 is electrically connected with the second low voltage end;

[0173] The second node control circuit comprises a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and a first capacitor C1;

[0174] The gate of M7 and the drain of M7 are both electrically connected with the high level end GCH, and the source of M7 is electrically connected with the pull-down control node;

[0175] The gate of M8 is electrically connected with the first node PU, the drain of M8 is electrically connected with the pull-down control node, and the source of M8 is electrically connected with the second low voltage end;

[0176] The gate of M5 is electrically connected with the pull-down control node, the drain of M5 is electrically connected with the high level end GCH, and the source of M5 is electrically connected with the second node PD;

[0177] The gate of M6 is electrically connected with the first node PU, the drain of M6 is electrically connected with the second node PD, and the source of M6 is electrically connected with the second low voltage end;

[0178] The first end of C1 is electrically connected with the first node PU, and the second end of C1 is electrically connected with the first scanning signal output end OT1;

[0179] At least one embodiment of the driving circuit further comprises a seventh transistor M7;

[0180] The gate of M7 is electrically connected with the frame start end STV0, the drain of M7 is electrically connected with the first scanning signal output end OT1, and the source of M7 is electrically connected with the first low voltage end;

[0181] The first low-voltage end is configured to provide a first low-voltage signal LVGL, and the second low-voltage end is configured to provide a second low-voltage signal VGL.

[0182] In at least one embodiment of the driving circuit shown in FIG. 5, all the transistors are n-type transistors.

[0183] In at least one embodiment of the driving circuit shown in FIG. 5, when the charging of the TFT (thin film transistor) is completed, the first scanning signal output by OT1 changes from the high-voltage signal VGH to the second low-voltage signal VGL, and the potential of the second scanning signal provided by OT2 changes from the first low-voltage signal LVGL to the second low-voltage signal VGL; because there is a parasitic capacitance between the top gate of the data writing transistor and the source of the data writing transistor, and there is a parasitic capacitance between the bottom gate of the data writing transistor and the source of the data writing transistor, the voltage of the source of the data writing transistor will rise, which can reduce or even offset △Vp.

[0184] When the first scanning signal output by OT1 rises from the first low-voltage signal LVGL to the high-voltage signal VGH, and the second scanning signal output by OT2 changes from the second low-voltage signal VGL to LVGL, the potential of the first scanning signal rises while the potential of the second scanning signal drops, so as to reduce or even offset △Vp.

[0185] In the related art, when the first scanning signal output by OT1 changes from the high-voltage signal VGH to the second low-voltage signal VGL, △Vp1 is equal to (Cgs / (Cgs+Cst))×(VGH-VGL); wherein Cst is a storage capacitance in the pixel circuit.

[0186] In at least one embodiment of the present disclosure, when the first scanning signal output by OT1 changes from the high-voltage signal VGH to the second low-voltage signal VGL, and the potential of the second scanning signal provided by OT2 changes from the first low-voltage signal LVGL to the second low-voltage signal VGL, △Vp2 is equal to (Cgs / (Cgs+Cst))×(VGH+LVGL-2VGL).

[0187] △Vp1 is greater than △Vp2.

[0188] When VGH is equal to 30V, VGL is equal to -8V, and LVGL is equal to -12V, △Vp1-△Vp2 is equal to 4×(Cgs / (Cgs+Cst)), and △Vp1-△Vp2 increases with the increase of Cgs, and the reduction of △Vp helps to improve Flicker.

[0189] In the related art, △Vp1 is a change value of a pixel voltage, and in at least one embodiment of the present disclosure, △Vp2 is a change value of a pixel voltage.

[0190] The display panel in at least one embodiment of the present disclosure further comprises a substrate; the pixel circuit is arranged on the substrate;

[0191] The top gate of the transistor included in the data writing circuit does not overlap the connection electrode of the transistor included in the data writing circuit in the orthographic projection on the substrate;

[0192] The connection electrode of the transistor included in the data writing circuit comprises the source of the transistor included in the data writing circuit and the drain of the transistor included in the data writing circuit.

[0193] In specific implementation, the top gate of the transistor included in the data writing circuit can not overlap the connection electrode of the transistor included in the data writing circuit in the orthographic projection on the substrate, so as to reduce the gate-source parasitic capacitance Cgs of the transistor included in the data writing circuit, and thus even if the voltage jump amplitude of the bottom gate is much smaller than that of the top gate, a good adjustment of △Vp can also be achieved.

[0194] In addition to the effect of reducing △Vp, the presence of the top gate can shield the pulling of the bottom gate to the common electrode voltage Vcom, and at this time, the voltage jump of the top gate is much smaller than that of the bottom gate, for example, when the voltage of the top gate changes by 4V, the voltage jump of the bottom gate can be 38V, and reducing the pulling of the gate to Vcom can alleviate the LH horizontal line and sensor horizontal line defects of the TDDI (touch and display driver integrated) display product.

[0195] The display panel in at least one embodiment of the present disclosure further comprises a substrate; the pixel circuit is arranged on the substrate;

[0196] The overlapping area between the top gate of the transistor included in the data writing circuit and the connection electrode of the transistor included in the data writing circuit in the orthographic projection on the substrate is a first area;

[0197] The overlapping area between the bottom gate of the transistor included in the data writing circuit and the connection electrode of the transistor included in the data writing circuit in the orthographic projection on the substrate is a second area;

[0198] The first area is smaller than the second area;

[0199] The connection electrode of the transistor included in the data writing circuit comprises the source of the transistor included in the data writing circuit and the drain of the transistor included in the data writing circuit.

[0200] In a specific implementation, an overlapping area between a top gate of a transistor of the data write circuit and a connection electrode of a transistor included in the data write circuit on the substrate can be less than an overlapping area between a bottom gate of the transistor of the data write circuit and the connection electrode of the transistor included in the data write circuit on the substrate, that is, the top gate of the transistor of the data write circuit can be reduced, and a gate-source parasitic capacitance Cgs of the transistor included in the data write circuit can be reduced, so that the data write circuit can play a good role in adjusting △Vp even if a voltage jump amplitude of the bottom gate is much smaller than a voltage jump amplitude of the top gate.

[0201] The display panel also includes a substrate, a light shielding metal layer, a semiconductor layer, and a gate metal layer.

[0202] The light shielding metal layer, the semiconductor layer, and the gate metal layer are arranged in sequence along a direction away from the substrate.

[0203] The semiconductor layer includes a channel of a transistor included in the data write circuit, and a top projection of the light shielding metal layer on the substrate covers a top projection of the channel on the substrate.

[0204] The light shielding metal layer includes the bottom gate, and the gate metal layer includes the top gate.

[0205] In a specific implementation, when the display panel includes the light shielding metal layer arranged between the semiconductor layer and the substrate, the light shielding metal layer can be multiplexed as the gate metal layer, and the light shielding metal layer can include the bottom gate, so that the data write transistor can be set as a double-gate transistor without increasing a mask.

[0206] As shown in FIG. 6, P1 is the substrate, 61 is the first gate metal layer, 71 is the first gate insulating layer, 62 is the semiconductor layer, 72 is the second gate insulating layer, 63 is the source-drain metal layer, and 64 is the second gate metal layer.

[0207] As shown in FIG. 7, the semiconductor layer 62 includes a channel CH of a data write transistor T0, a first conductorized portion D1 of the data write transistor T0, and a second conductorized portion D2 of the data write transistor T0.

[0208] S0 is a source of T0, and D0 is a drain of T0.

[0209] GD is a bottom gate of T0, and GT is a top gate of T0.

[0210] D1 is in communication with S0, and D2 is in communication with D0.

[0211] In at least one embodiment of the present disclosure, as shown in FIG. 8 and FIG. 9, the top gate GT of T0 can be set to be smaller in the projection on the substrate P1, so as to reduce the overlapping area between GT and S0, and reduce the overlapping area between GT and D0.

[0212] As shown in FIG. 8, P1 is a substrate, 61 is a first gate metal layer, 71 is a first gate insulating layer, 62 is a semiconductor layer, 72 is a second gate insulating layer, 63 is a source-drain metal layer, and 64 is a second gate metal layer.

[0213] As shown in FIG. 9, the semiconductor layer 62 includes a channel CH of the data writing transistor T0, a first conductive portion D1 of the data writing transistor T0, and a second conductive portion D2 of the data writing transistor T0.

[0214] S0 is the source of T0, and D0 is the drain of T0.

[0215] GD is the bottom gate of T0, and GT is the top gate of T0.

[0216] D1 is in communication with S0, and D2 is in communication with D0.

[0217] As shown in FIG. 9, the overlapping area between the projection of the bottom gate GD of T0 on the substrate P1 and the projection of the connecting electrode of T0 on the substrate P1 is greater than the overlapping area between the projection of the top gate GT of T0 on the substrate P1 and the projection of the connecting electrode of T0 on the substrate P1.

[0218] As shown in FIG. 10, P1 is a substrate, 101 is a light shielding metal layer, 102 is a buffer layer, 62 is a semiconductor layer, 103 is a gate insulating layer, 63 is a source-drain metal layer, 104 is a gate metal layer, and 105 is an interlayer dielectric layer.

[0219] In at least one embodiment shown in FIG. 10, the light shielding metal layer 101 is multiplexed as a first gate metal layer, the gate metal layer 104 is a second gate metal layer, the bottom gate of the transistor is made by the light shielding metal layer 101, and the top gate of the transistor is made by the gate metal layer 104.

[0220] As shown in FIG. 11, GD is the bottom gate of T0, and GT is the top gate of T0.

[0221] The semiconductor layer 62 includes a channel CH of the data writing transistor T0, a first conductive portion D1 of the data writing transistor T0, and a second conductive portion D2 of the data writing transistor T0;

[0222] The source of T0 is labeled as S0, and the drain of T0 is labeled as D0;

[0223] D1 and S0 are in communication, and D2 and D0 are in communication.

[0224] As shown in FIG. 11, the orthogonal projection of the top gate GT of the data writing transistor T0 on the substrate P1 does not overlap the orthogonal projection of the source S0 of T0 on the substrate P1;

[0225] The orthogonal projection of the bottom gate GD of T0 on the substrate P1 does not overlap the orthogonal projection of the drain D0 of T0 on the substrate P1;

[0226] As shown in FIGS. 10 and 11, the orthogonal projection of the light shielding metal layer 10 on the substrate P1 covers the orthogonal projection of the channel CH on the substrate P1.

[0227] In a specific implementation, in a TDDI display product, flicker can be improved by improving the uniformity of the common electrode voltage Vcom.

[0228] The display panel provided in at least one embodiment of the present disclosure further includes a plurality of rows and columns of touch electrode blocks, a plurality of columns of signal transmission lines, and a voltage supply circuit; the plurality of rows and columns of touch electrode blocks are independent of each other;

[0229] The voltage supply circuit is electrically connected to a first end of the signal transmission line, the signal transmission line includes a connection point, and the connection point is electrically connected to the touch electrode block;

[0230] The voltage supply circuit is configured to, in a display stage, supply a corresponding common electrode voltage to the signal transmission line according to the resistance between the first end of the signal transmission line and the connection point of the signal transmission line.

[0231] In a specific implementation, when the display panel is a TDDI display panel, the display panel can include multiple rows and multiple columns of touch electrode blocks that are independent of each other. In a display stage, the touch electrode blocks can be multiplexed as common electrode blocks and connected to a common electrode voltage Vcom. The display panel can further include multiple columns of signal transmission lines and a voltage supply circuit. The signal transmission lines are electrically connected to the touch electrode blocks through connection points. In the display stage, the voltage supply circuit provides corresponding common electrode voltages to the signal transmission lines according to the resistance between the first end of the signal transmission line and the connection point of the signal transmission line, so that each touch electrode block receives approximately the same common electrode voltage, thereby improving the Vcom uniformity in the TDDI display panel and further improving the Flicker.

[0232] As shown in FIG. 12A, the display panel includes a first row and a first column of touch electrode blocks TB11, a first row and a second column of touch electrode blocks TB12, a first row and a third column of touch electrode blocks TB13, a first row and a fourth column of touch electrode blocks TB14, a first row and a fifth column of touch electrode blocks TB15, a first row and a sixth column of touch electrode blocks TB16, a second row and a first column of touch electrode blocks TB21, a second row and a second column of touch electrode blocks TB22, a second row and a third column of touch electrode blocks TB23, a second row and a fourth column of touch electrode blocks TB24, a second row and a fifth column of touch electrode blocks TB25, a second row and a sixth column of touch electrode blocks TB16, a third row and a first column of touch electrode blocks TB31, a third row and a second column of touch electrode blocks TB32, a third row and a third column of touch electrode blocks TB33, a third row and a fourth column of touch electrode blocks TB34, a third row and a fifth column of touch electrode blocks TB35, a third row and a sixth column of touch electrode blocks TB36, a fourth row and a first column of touch electrode blocks TB41, a fourth row and a second column of touch electrode blocks TB42, a fourth row and a third column of touch electrode blocks TB43, a fourth row and a fourth column of touch electrode blocks TB44, a fourth row and a fifth column of touch electrode blocks TB45, a fourth row and a sixth column of touch electrode blocks TB46, a fifth row and a first column of touch electrode blocks TB51, a fifth row and a second column of touch electrode blocks TB52, a fifth row and a third column of touch electrode blocks TB53, a fifth row and a fourth column of touch electrode blocks TB54, a fifth row and a fifth column of touch electrode blocks TB55, a fifth row and a sixth column of touch electrode blocks TB56, a sixth row and a first column of touch electrode blocks TB61, a sixth row and a second column of touch electrode blocks TB62, a sixth row and a third column of touch electrode blocks TB63, a sixth row and a fourth column of touch electrode blocks TB64, a sixth row and a fifth column of touch electrode blocks TB65, and a sixth row and a sixth column of touch electrode blocks TB66.

[0233] As shown in FIG. 12B, the display panel further includes a voltage supply circuit 10 and multiple columns of signal transmission lines.

[0234] In FIG. 12B, the signal transmission line marked as L0 includes a connection point NJ;

[0235] The voltage supply circuit 10 is electrically connected to the first end of each signal transmission line, and each signal transmission line is electrically connected to a corresponding touch electrode block through a corresponding connection point.

[0236] The voltage supply circuit 10 is configured to supply a corresponding common electrode voltage to the signal transmission line according to the resistance between the first end of the signal transmission line and the connection point of the signal transmission line during the display stage.

[0237] In a specific implementation, the resistance between the first end of the signal transmission line and the connection point of the signal transmission line can be calculated, and the voltage drop on the signal transmission line can be calculated according to the resistance voltage division principle; during the display stage, the common electrode voltage Vcom transmitted on the signal transmission line is insufficient for the corresponding touch electrode block due to the voltage drop caused by the resistance of the signal transmission line itself, and needs to be compensated. At least one embodiment of the present disclosure can adjust the common electrode voltage output by the voltage supply circuit 10 through an algorithm, and compensate the common electrode voltage for the touch electrode blocks located in different rows according to the calculated voltage drop on the signal transmission line, so as to improve the uniformity of the common electrode voltage.

[0238] The display panel according to at least one embodiment of the present disclosure further includes a common electrode layer and a detection integrated circuit.

[0239] The common electrode layer includes a plurality of common electrode parts, and the plurality of common electrode parts are in communication with each other.

[0240] The common electrode part includes at least one detection point.

[0241] The detection integrated circuit is electrically connected to the common electrode part through the detection point, and is configured to detect the potential of the detection point during the detection stage; and the detection integrated circuit is further configured to obtain a corresponding compensation voltage signal according to the potential of the detection point and a target common electrode voltage signal.

[0242] In a non-TDDI display product, a whole layer of common electrode layer is provided, and the common electrode layer can be configured to include a plurality of common electrode parts in communication with each other; the detection integrated circuit is electrically connected to the corresponding common electrode part through the corresponding detection point, and detects the potential of the detection point during the detection stage; and according to the potential of the detection point and a target common electrode voltage signal, a corresponding compensation voltage signal can be obtained.

[0243] Optionally, the target common electrode voltage signal can be the maximum value, the minimum value, or the average value of the common electrode voltages detected by the detection integrated circuit, but is not limited thereto.

[0244] In at least one embodiment of the present disclosure, the detection point is directly electrically connected with the detection integrated circuit.

[0245] In specific implementation, the detection point can be directly electrically connected with a detection IC (Integrated Circuit), and the detection IC directly detects the potential of the detection point.

[0246] In at least one embodiment of the present disclosure, the common electrode layer includes a plurality of rows and columns of common electrode portions; the display panel includes a display area and a peripheral area, and the pixel circuit is arranged in the display area.

[0247] The detection point extends to the peripheral area through a first connection line extending in the row direction, and the first connection line is electrically connected with the detection integrated circuit through a second connection line arranged in the peripheral area.

[0248] In specific implementation, the common electrode layer can include a plurality of rows and columns of common electrode portions in communication with each other, and the detection point can extend to the peripheral area through a first connection line extending in the row direction, and the first connection line is electrically connected with the detection integrated circuit through a second connection line arranged in the peripheral area.

[0249] The display panel of at least one embodiment of the present disclosure further includes a switch control module, and the switch control module includes a plurality of switch control circuits.

[0250] The control end of the switch control circuit is electrically connected with the corresponding switch control end, the first end of the switch control circuit is electrically connected with the detection integrated circuit, the second end of the switch control circuit is electrically connected with the detection point, and the switch control circuit is used to control the communication between the detection integrated circuit and the detection point in the corresponding detection stage included in the detection period.

[0251] The detection integrated circuit is used to detect the potential of the detection point in the corresponding detection stage.

[0252] In specific implementation, the display panel can further include a switch control module, when the common electrode layer includes N rows and 2M columns of common electrode portions, the switch control module can include N switch control circuits; the nth switch control circuit can include M switch control transistors.

[0253] The gate of the mth switch control transistor included in the nth switch control circuit is electrically connected with the nth switch control end, the first pole of the mth switch control transistor included in the nth switch control circuit is electrically connected with the mth terminal of the detection integrated circuit, and the second pole of the mth switch control transistor included in the nth switch control circuit is electrically connected with the detection point included in the nth row and the mth column of common electrode portions.

[0254] When the nth switch control end provides an effective nth switch control signal, the mth switch control transistor included in the nth switch control circuit is turned on, and the mth terminal of the detection integrated circuit is in communication with the detection point included in the mth column of the nth row of common electrode portions.

[0255] In at least one embodiment of the present disclosure, when the nth switch control end provides an effective nth switch control signal in the nth detection stage of the detection period, the mth switch control transistor included in the nth switch control circuit is turned on, and the mth terminal of the detection integrated circuit is in communication with the detection point included in the mth column of the nth row of common electrode portions.

[0256] wherein N and M are positive integers; n is a positive integer less than or equal to N; and m is a positive integer less than or equal to M.

[0257] In at least one embodiment of the present disclosure, the switch control circuit is configured to control the communication between the detection integrated circuit and the detection point in a corresponding compensation stage included in a compensation period.

[0258] The detection integrated circuit is configured to transmit a corresponding compensation voltage signal to the corresponding common electrode portion through the switch control circuit in the corresponding compensation stage.

[0259] In a specific implementation, the compensation period can include N sequentially arranged compensation stages. When the nth switch control end provides an effective nth switch control signal in the nth compensation stage, the mth switch control transistor included in the nth switch control circuit is turned on, and the detection integrated circuit transmits a corresponding compensation voltage signal to the mth column of the nth row of common electrode portions.

[0260] Optionally, the common electrode layer includes N rows of 2M columns of common electrode portions; N and M are positive integers; the display panel further includes a first switch control module and a second switch control module; the first switch control module includes N first switch control units, and the second switch control module includes N second switch control units.

[0261] The first switch control unit includes M first switch control circuits, and the second switch control unit includes M second switch control circuits.

[0262] The display panel includes a display area and a peripheral area; the pixel circuit is arranged in the display area, and the first switch control module and the second switch control module are arranged in the peripheral area; the first switch control module is arranged on a first side of the display area, the second switch control module is arranged on a second side of the display area, and the first side and the second side are opposite sides.

[0263] The mth first switch control circuit in the nth first switch control unit is electrically connected with the nth first switch control end, the detection integrated circuit and the nth row and mth column common electrode part respectively, and is used for controlling the detection integrated circuit to communicate with the detection point included in the nth row and mth column common electrode part under the control of the switch control signal provided by the nth first switch control end;

[0264] The mth second switch control circuit in the nth second switch control unit is electrically connected with the nth second switch control end, the detection integrated circuit and the nth row and M+mth column common electrode part respectively, and is used for controlling the detection integrated circuit to communicate with the detection point included in the nth row and M+mth column common electrode part under the control of the switch control signal provided by the nth second switch control end.

[0265] N is a positive integer less than or equal to N; and m is a positive integer less than or equal to M.

[0266] In a specific implementation, the common electrode layer can include N rows and 2M columns of common electrode parts, the display panel can include a first switch control module and a second switch control module arranged in the peripheral region, the first switch control module is arranged at a first side of the display region, and the second switch control module is arranged at a second side of the display region. For example, the first side can be the left side, and the second side can be the right side.

[0267] The first switch control module can include N first switch control units, and the second switch control module can include N second switch control units. The first switch control unit can include M first switch control circuits, and the second switch control unit can include M second switch control circuits.

[0268] The mth first switch control circuit in the nth first switch control unit controls the detection integrated circuit to communicate with the detection point included in the nth row and mth column common electrode part under the control of the switch control signal provided by the nth first switch control end. The mth second switch control circuit in the nth second switch control unit controls the detection integrated circuit to communicate with the detection point included in the nth row and M+mth column common electrode part under the control of the switch control signal provided by the nth second switch control end.

[0269] Optionally, the common electrode part includes a plurality of parts arranged in sequence along a first direction.

[0270] The detection point of the nth row and mth column common electrode part is included in the a part included in the nth row and mth column common electrode part.

[0271] The detection point of the nth row and M+mth column common electrode part is included in the b part included in the nth row and M+mth column common electrode part.

[0272] a and b are both positive integers, and a is not equal to b.

[0273] In at least one embodiment of the present disclosure, the first direction can be a longitudinal direction, and the first direction can be substantially the same as the extension direction of the data lines.

[0274] In a large-size display product, the size of the common electrode layer is large, and thus the common electrode voltage accessed by different positions of the common electrode layer is not uniform. Therefore, the detection points of the common electrode parts in the same row and longitudinally symmetrical are located in different parts to enable uniform compensation.

[0275] The display panel in at least one embodiment of the present disclosure further includes a first switch control signal generation module and a second switch control signal generation module arranged in the peripheral region; the first switch control signal generation module is arranged at a first side of the display region, and the second switch control signal generation module is arranged at a second side of the display region.

[0276] The first switch control signal generation module is electrically connected with N first switch control terminals respectively, and is configured to provide an effective switch control signal to an nth first switch control terminal in an nth detection stage included in the detection period.

[0277] The second switch control signal generation module is electrically connected with N second switch control terminals respectively, and is configured to provide an effective switch control signal to an nth second switch control terminal in the nth detection stage included in the detection period.

[0278] The detection integrated circuit is configured to detect the potential of the detection point included in each common electrode part in the nth row in the nth detection stage.

[0279] In a specific implementation, the display panel can further include a first switch control signal generation module and a second switch control signal generation module. The first switch control signal generation module provides an effective switch control signal to an nth first switch control terminal in an nth detection stage included in the detection period. The second switch control signal generation module provides an effective switch control signal to an nth second switch control terminal in the nth detection stage included in the detection period. The detection integrated circuit detects the potential of the detection point included in each common electrode part in the nth row in the nth detection stage included in the detection period.

[0280] In at least one embodiment of the present disclosure, the first switch control signal generation module is electrically connected with N first switch control terminals respectively, and is configured to provide an effective switch control signal to an nth first switch control terminal in an nth compensation stage included in the compensation period.

[0281] The second switch control signal generation module is electrically connected with the N second switch control terminals respectively, and is configured to provide an effective switch control signal to the nth second switch control terminal in the nth compensation stage included in the compensation period.

[0282] The detection integrated circuit is configured to transmit a corresponding compensation voltage signal to a corresponding common electrode part in the nth compensation stage.

[0283] In a specific implementation, in the nth compensation stage included in the compensation period, the first switch control signal generation module provides an effective switch control signal to the nth first switch control terminal; the second switch control signal generation module provides an effective switch control signal to the nth second switch control terminal; and the detection integrated circuit transmits a corresponding compensation voltage signal to a corresponding common electrode part.

[0284] The display panel also includes a voltage supply circuit and a plurality of signal transmission lines.

[0285] The voltage supply circuit is electrically connected with the common electrode part through the signal transmission lines, and is configured to provide the compensation voltage signal to the signal transmission lines in the compensation stage.

[0286] In a specific implementation, the voltage supply circuit can provide the compensation voltage signal to the corresponding common electrode part through the signal transmission lines.

[0287] As shown in FIG. 13, at least one embodiment of the display panel can include a common electrode layer.

[0288] The common electrode layer can include four rows and four columns of common electrode parts that are in communication with each other: a first row and first column common electrode part S11, a first row and second column common electrode part S12, a first row and third column common electrode part S13, a first row and fourth column common electrode part S14, a second row and first column common electrode part S21, a second row and second column common electrode part S22, a second row and third column common electrode part S23, a second row and fourth column common electrode part S24, a third row and first column common electrode part S31, a third row and second column common electrode part S32, a third row and third column common electrode part S33, a third row and fourth column common electrode part S34, a fourth row and first column common electrode part S41, a fourth row and second column common electrode part S42, a fourth row and third column common electrode part S43, and a fourth row and fourth column common electrode part S44.

[0289] Each of the common electrode parts is disposed in a display area.

[0290] At least one embodiment of the display panel also includes a first switch control module KC1, a second switch control module KC2, and a detection integrated circuit 130 disposed in a peripheral area.

[0291] The first switch control module KC1 is arranged on the left side of the display area, and the second switch control module KC2 is arranged on the right side of the display area.

[0292] The detection period and the compensation period are arranged in sequence; the detection period comprises first, second, third and fourth detection stages arranged in sequence; and the compensation period comprises first, second, third and fourth compensation stages arranged in sequence.

[0293] The first switch control module KC1 is respectively connected with a first first switch control end K11, a second first switch control end K21, a third first switch control end K31, a fourth first switch control end K41, a first terminal TD1 of the detection integrated circuit 130, a second terminal TD2 of the detection integrated circuit 130, a first row and first column common electrode part S11, a first row and second column common electrode part S12, a second row and first column common electrode part S21, a second row and second column common electrode part S22, a third row and first column common electrode part S31, a third row and second column common electrode part S32, a fourth row and first column common electrode part S41 and a fourth row and second column common electrode part S42.

[0294] The second switch control module KC2 is respectively connected with a first second switch control end K12, a second second switch control end K22, a third second switch control end K32, a fourth second switch control end K42, a third terminal TD3 of the detection integrated circuit 130, a fourth terminal TD4 of the detection integrated circuit 130, a first row and third column common electrode part S13, a first row and fourth column common electrode part S14, a second row and third column common electrode part S23, a second row and fourth column common electrode part S24, a third row and third column common electrode part S33, a third row and fourth column common electrode part S34, a fourth row and third column common electrode part S43 and a fourth row and fourth column common electrode part S44.

[0295] In the first detection stage, under the control of the first first switch control signal provided by K11, the first switch control module KC1 controls TD1 and S11 to be connected, and controls TD2 and S12 to be connected; under the control of the first second switch control signal provided by K12, the second switch control module KC2 controls TD3 and S13 to be connected, and controls TD4 and S14 to be connected; the detection integrated circuit 130 detects the potential of S11, the potential of S12, the potential of S13 and the potential of S14; the detection integrated circuit 130 obtains the first row first column compensation voltage signal according to the potential of S11 and the target common electrode voltage signal, obtains the first row second column compensation voltage signal according to the potential of S12 and the target common electrode voltage signal, obtains the first row third column compensation voltage signal according to the potential of S13 and the target common electrode voltage signal, and obtains the first row fourth column compensation voltage signal according to the potential of S14 and the target common electrode voltage signal;

[0296] In the second detection stage, under the control of the second first switch control signal provided by K21, the first switch control module KC1 controls TD1 and S21 to be connected, and controls TD2 and S22 to be connected; under the control of the second second switch control signal provided by K22, the second switch control module KC2 controls TD3 and S23 to be connected, and controls TD4 and S24 to be connected; the detection integrated circuit 130 obtains the second row first column compensation voltage signal according to the potential of S21 and the target common electrode voltage signal, obtains the second row second column compensation voltage signal according to the potential of S22 and the target common electrode voltage signal, obtains the second row third column compensation voltage signal according to the potential of S23 and the target common electrode voltage signal, and obtains the second row fourth column compensation voltage signal according to the potential of S24 and the target common electrode voltage signal;

[0297] In the third detection stage, under the control of the third first switch control signal provided by K31, the first switch control module KC1 controls TD1 and S31 to be connected, and controls TD2 and S32 to be connected; under the control of the third second switch control signal provided by K32, the second switch control module KC2 controls TD3 and S33 to be connected, and controls TD4 and S34 to be connected; the detection integrated circuit 130 obtains the third row first column compensation voltage signal according to the potential of S31 and the target common electrode voltage signal, obtains the third row second column compensation voltage signal according to the potential of S32 and the target common electrode voltage signal, obtains the third row third column compensation voltage signal according to the potential of S33 and the target common electrode voltage signal, and obtains the third row fourth column compensation voltage signal according to the potential of S34 and the target common electrode voltage signal;

[0298] In the fourth detection stage, under the control of the fourth first switch control signal provided by K41, the first switch control module KC1 controls TD1 to communicate with S41 and controls TD2 to communicate with S42; under the control of the fourth second switch control signal provided by K42, the second switch control module KC2 controls TD3 to communicate with S43 and controls TD4 to communicate with S44; the detection integrated circuit 130 obtains the fourth row first column compensation voltage signal according to the potential of S41 and the target common electrode voltage signal, obtains the fourth row second column compensation voltage signal according to the potential of S42 and the target common electrode voltage signal, obtains the fourth row third column compensation voltage signal according to the potential of S43 and the target common electrode voltage signal, and obtains the fourth row fourth column compensation voltage signal according to the potential of S44 and the target common electrode voltage signal;

[0299] In the first compensation stage, under the control of the first first switch control signal provided by K11, the first switch control module KC1 controls TD1 to communicate with S11 and controls TD2 to communicate with S12; under the control of the second switch control signal provided by K12, the second switch control module KC2 controls TD3 to communicate with S13 and controls TD4 to communicate with S14; the detection integrated circuit 130 transmits the first row first column compensation voltage signal to S11, transmits the first row second column compensation voltage signal to S12, transmits the first row third column compensation voltage signal to S13, and transmits the first row fourth column compensation voltage signal to S14;

[0300] In the second compensation stage, under the control of the second first switch control signal provided by K21, the first switch control module KC1 controls TD1 to communicate with S21 and controls TD2 to communicate with S22; under the control of the second second switch control signal provided by K22, the second switch control module KC2 controls TD3 to communicate with S23 and controls TD4 to communicate with S24; the detection integrated circuit 130 transmits the second row first column compensation voltage signal to S21, transmits the second row second column compensation voltage signal to S22, transmits the second row third column compensation voltage signal to S23, and transmits the second row fourth column compensation voltage signal to S24;

[0301] In the third compensation stage, under the control of the third first switch control signal provided by K31, the first switch control module KC1 controls the communication between TD1 and S31 and controls the communication between TD2 and S32; under the control of the third second switch control signal provided by K32, the second switch control module KC2 controls the communication between TD3 and S33 and controls the communication between TD4 and S34; the detection integrated circuit 130 transmits the third row first column compensation voltage signal to S31, transmits the third row second column compensation voltage signal to S32, transmits the third row third column compensation voltage signal to S33, and transmits the third row fourth column compensation voltage signal to S34.

[0302] In the fourth compensation stage, under the control of the fourth first switch control signal provided by K41, the first switch control module KC1 controls the communication between TD1 and S41 and controls the communication between TD2 and S42; under the control of the fourth second switch control signal provided by K42, the second switch control module KC2 controls the communication between TD3 and S43 and controls the communication between TD4 and S44; the detection integrated circuit 130 transmits the fourth row first column compensation voltage signal to S41, transmits the fourth row second column compensation voltage signal to S42, transmits the fourth row third column compensation voltage signal to S43, and transmits the fourth row fourth column compensation voltage signal to S44.

[0303] As shown in FIG. 14, on the basis of at least one embodiment of the display panel shown in FIG. 13,

[0304] The first switch control module includes a first first switch control unit KD11, a second first switch control unit KD21, a third first switch control unit KD31, and a fourth first switch control unit KD41.

[0305] The second switch control module includes a first second switch control unit KD12, a second second switch control unit KD22, a third second switch control unit KD32, and a fourth second switch control unit KD42.

[0306] KD11 is electrically connected with the first first switch control end K11, the first terminal TD1 of the detection integrated circuit 130, the second terminal TD2 of the detection integrated circuit 130, the first row first column common electrode part S11, and the first row second column common electrode part S12 respectively, and is used for, in the first detection stage and the first compensation stage, under the control of the first first switch control signal provided by K11, controlling the communication between TD1 and S11 and controlling the communication between TD2 and S12.

[0307] The KD21 is electrically connected with the second first switch control end K21, the first terminal TD1 of the detection integrated circuit 130, the second terminal TD2 of the detection integrated circuit 130, the second row first column common electrode part S21 and the second row second column common electrode part S22 respectively, for controlling the communication between TD1 and S21 and the communication between TD2 and S22 under the control of the second first switch control signal provided by K21 in the second detection stage and the second compensation stage;

[0308] The KD31 is electrically connected with the third first switch control end K31, the first terminal TD1 of the detection integrated circuit 130, the second terminal TD2 of the detection integrated circuit 130, the third row first column common electrode part S31 and the third row second column common electrode part S32 respectively, for controlling the communication between TD1 and S31 and the communication between TD2 and S32 under the control of the third first switch control signal provided by K31 in the third detection stage and the third compensation stage;

[0309] The KD41 is electrically connected with the fourth first switch control end K41, the first terminal TD1 of the detection integrated circuit 130, the second terminal TD2 of the detection integrated circuit 130, the fourth row first column common electrode part S41 and the fourth row second column common electrode part S42 respectively, for controlling the communication between TD1 and S41 and the communication between TD2 and S42 under the control of the fourth first switch control signal provided by K41 in the fourth detection stage and the fourth compensation stage;

[0310] The KD12 is electrically connected with the first second switch control end K12, the third terminal TD3 of the detection integrated circuit 130, the fourth terminal TD4 of the detection integrated circuit 130, the first row third column common electrode part S13 and the first row fourth column common electrode part S14 respectively, for controlling the communication between TD3 and S13 and the communication between TD4 and S14 under the control of the first second switch control signal provided by K12 in the first detection stage and the first compensation stage;

[0311] The KD22 is electrically connected with the second second switch control end K22, the third terminal TD3 of the detection integrated circuit 130, the fourth terminal TD4 of the detection integrated circuit 130, the second row third column common electrode part S23 and the second row fourth column common electrode part S24 respectively, for controlling the communication between TD3 and S23 and the communication between TD4 and S24 under the control of the second second switch control signal provided by K22 in the second detection stage and the second compensation stage;

[0312] The KD32 is electrically connected with the third second switch control end K32, the third terminal TD3 of the detection integrated circuit 130, the fourth terminal TD4 of the detection integrated circuit 130, the third row third column common electrode part S33 and the third row fourth column common electrode part S34 respectively, for controlling the communication between TD3 and S33 and the communication between TD4 and S34 under the control of the third second switch control signal provided by K32 in the third detection stage and the third compensation stage;

[0313] The KD42 is electrically connected with the fourth second switch control end K42, the third terminal TD3 of the detection integrated circuit 130, the fourth terminal TD4 of the detection integrated circuit 130, the fourth row third column common electrode part S43 and the fourth row fourth column common electrode part S44 respectively, for controlling the communication between TD3 and S43 and the communication between TD4 and S44 under the control of the fourth second switch control signal provided by K42 in the fourth detection stage and the fourth compensation stage.

[0314] As shown in FIG. 15, on the basis of at least one embodiment of the display panel shown in FIG. 14, the first first switch control unit includes the first row first column switch control circuit C11 and the first row second column switch control circuit C12;

[0315] The second first switch control unit includes the second row first column switch control circuit C21 and the second row second column switch control circuit C22;

[0316] The third first switch control unit includes the third row first column switch control circuit C31 and the third row second column switch control circuit C32;

[0317] The fourth first switch control unit includes the fourth row first column switch control circuit C41 and the fourth row second column switch control circuit C42;

[0318] The C11 is electrically connected with the first first switch control end K11, the first terminal TD1 of the detection integrated circuit 130 and the first row first column common electrode part S11 respectively, for controlling the communication between TD1 and S11 under the control of the first first switch control signal provided by K11 in the first detection stage and the first compensation stage;

[0319] The C12 is electrically connected with the first first switch control end K11, the second terminal TD2 of the detection integrated circuit 130 and the first row second column common electrode part S12 respectively, for controlling the communication between TD2 and S12 under the control of the first first switch control signal provided by K11 in the first detection stage and the first compensation stage;

[0320] C21 is electrically connected with the second first switch control end K21, the first terminal TD1 of the detection integrated circuit 130 and the second row first column common electrode part S21 respectively, for controlling the communication between TD1 and S21 under the control of the second first switch control signal provided by K21 in the second detection stage and the second compensation stage;

[0321] C22 is electrically connected with the second first switch control end K21, the second terminal TD2 of the detection integrated circuit 130 and the second row second column common electrode part S22 respectively, for controlling the communication between TD2 and S22 under the control of the second first switch control signal provided by K21 in the second detection stage and the second compensation stage;

[0322] C31 is electrically connected with the third first switch control end K31, the first terminal TD1 of the detection integrated circuit 130 and the third row first column common electrode part S31 respectively, for controlling the communication between TD1 and S31 under the control of the third first switch control signal provided by K31 in the third detection stage and the third compensation stage;

[0323] C32 is electrically connected with the third first switch control end K31, the second terminal TD2 of the detection integrated circuit 130 and the third row second column common electrode part S32 respectively, for controlling the communication between TD2 and S32 under the control of the third first switch control signal provided by K31 in the third detection stage and the third compensation stage;

[0324] C41 is electrically connected with the fourth first switch control end K41, the first terminal TD1 of the detection integrated circuit 130 and the fourth row first column common electrode part S41 respectively, for controlling the communication between TD1 and S41 under the control of the fourth first switch control signal provided by K41 in the fourth detection stage and the fourth compensation stage;

[0325] C42 is electrically connected with the fourth first switch control end K41, the second terminal TD2 of the detection integrated circuit 130 and the fourth row second column common electrode part S42 respectively, for controlling the communication between TD2 and S42 under the control of the fourth first switch control signal provided by K41 in the fourth detection stage and the fourth compensation stage;

[0326] The first second switch control unit includes the first row third column switch control circuit C13 and the first row fourth column switch control circuit C14;

[0327] The second second switch control unit includes the second row third column switch control circuit C23 and the second row fourth column switch control circuit C24;

[0328] The third second switch control unit comprises a third row third column switch control circuit C33 and a third row fourth column switch control circuit C34;

[0329] The fourth second switch control unit comprises a fourth row third column switch control circuit C43 and a fourth row fourth column switch control circuit C44;

[0330] C13 is electrically connected with the first second switch control terminal K12, the third terminal TD3 of the detection integrated circuit 130 and the first row third column common electrode part S13 respectively, and is used for controlling the communication between TD3 and S13 under the control of the first second switch control signal provided by K12 in the first detection stage and the first compensation stage;

[0331] C14 is electrically connected with the first second switch control terminal K12, the fourth terminal TD4 of the detection integrated circuit 130 and the first row fourth column common electrode part S14 respectively, and is used for controlling the communication between TD4 and S14 under the control of the first second switch control signal provided by K12 in the first detection stage and the first compensation stage;

[0332] C23 is electrically connected with the second second switch control terminal K22, the third terminal TD3 of the detection integrated circuit 130 and the second row third column common electrode part S23 respectively, and is used for controlling the communication between TD3 and S23 under the control of the second second switch control signal provided by K22 in the second detection stage and the second compensation stage;

[0333] C24 is electrically connected with the second second switch control terminal K22, the fourth terminal TD4 of the detection integrated circuit 130 and the second row fourth column common electrode part S24 respectively, and is used for controlling the communication between TD4 and S24 under the control of the second second switch control signal provided by K22 in the second detection stage and the second compensation stage;

[0334] C33 is electrically connected with the third second switch control terminal K32, the third terminal TD3 of the detection integrated circuit 130 and the third row third column common electrode part S33 respectively, and is used for controlling the communication between TD3 and S33 under the control of the third second switch control signal provided by K32 in the third detection stage and the third compensation stage;

[0335] C34 is electrically connected with the third second switch control terminal K32, the fourth terminal TD4 of the detection integrated circuit 130 and the third row fourth column common electrode part S34 respectively, and is used for controlling the communication between TD4 and S34 under the control of the third second switch control signal provided by K32 in the third detection stage and the third compensation stage;

[0336] C43 is electrically connected with the fourth second switch control end K42, the third terminal TD3 of the detection integrated circuit 130 and the fourth row third column common electrode part S43 respectively, for controlling the communication between TD3 and S43 under the control of the fourth second switch control signal provided by K42 in the fourth detection stage and the fourth compensation stage;

[0337] C44 is electrically connected with the fourth second switch control end K42, the fourth terminal TD4 of the detection integrated circuit 130 and the fourth row fourth column common electrode part S44 respectively, for controlling the communication between TD4 and S44 under the control of the fourth second switch control signal provided by K42 in the fourth detection stage and the fourth compensation stage.

[0338] As shown in FIG. 16, on the basis of at least one embodiment of the display panel shown in FIG. 15,

[0339] C11 includes a first first switch transistor MK11, C12 includes a first second switch transistor MK12, C13 includes a first third switch transistor MK13, and C14 includes a first fourth switch transistor MK14;

[0340] C21 includes a second first switch transistor MK21, C22 includes a second second switch transistor MK22, C23 includes a second third switch transistor MK23, and C14 includes a second fourth switch transistor MK24;

[0341] C31 includes a third first switch transistor MK31, C32 includes a third second switch transistor MK32, C33 includes a third third switch transistor MK33, and C34 includes a third fourth switch transistor MK34;

[0342] C41 includes a fourth first switch transistor MK41, C42 includes a fourth second switch transistor MK42, C43 includes a fourth third switch transistor MK43, and C44 includes a fourth fourth switch transistor MK44;

[0343] The gate of MK11 is electrically connected with the first first switch control end K11, the drain of MK11 is electrically connected with the first terminal TD1 of the detection integrated circuit 130, and the source of MK11 is electrically connected with the first row first column common electrode part S11;

[0344] The gate of MK12 is electrically connected with the first first switch control end K11, the drain of MK12 is electrically connected with the second terminal TD2 of the detection integrated circuit 130, and the source of MK12 is electrically connected with the first row second column common electrode part S12;

[0345] The gate of the MK13 is electrically connected with the first second switch control end K12, the drain of the MK13 is electrically connected with the third terminal TD3 of the detection integrated circuit 130, and the source of the MK13 is electrically connected with the first row third column common electrode part S13;

[0346] The gate of the MK14 is electrically connected with the first second switch control end K12, the drain of the MK14 is electrically connected with the fourth terminal TD4 of the detection integrated circuit 130, and the source of the MK12 is electrically connected with the first row fourth column common electrode part S14;

[0347] The gate of the MK21 is electrically connected with the second first switch control end K21, the drain of the MK21 is electrically connected with the first terminal TD1 of the detection integrated circuit 130, and the source of the MK21 is electrically connected with the second row first column common electrode part S21;

[0348] The gate of the MK22 is electrically connected with the second first switch control end K21, the drain of the MK22 is electrically connected with the second terminal TD2 of the detection integrated circuit 130, and the source of the MK22 is electrically connected with the second row second column common electrode part S22;

[0349] The gate of the MK23 is electrically connected with the second second switch control end K22, the drain of the MK23 is electrically connected with the third terminal TD3 of the detection integrated circuit 130, and the source of the MK23 is electrically connected with the second row third column common electrode part S23;

[0350] The gate of the MK24 is electrically connected with the second second switch control end K22, the drain of the MK24 is electrically connected with the fourth terminal TD4 of the detection integrated circuit 130, and the source of the MK24 is electrically connected with the second row fourth column common electrode part S24;

[0351] The gate of the MK31 is electrically connected with the third first switch control end K31, the drain of the MK31 is electrically connected with the first terminal TD1 of the detection integrated circuit 130, and the source of the MK31 is electrically connected with the third row first column common electrode part S31;

[0352] The gate of the MK32 is electrically connected with the third first switch control end K31, the drain of the MK32 is electrically connected with the second terminal TD2 of the detection integrated circuit 130, and the source of the MK32 is electrically connected with the third row second column common electrode part S32;

[0353] The gate of the MK33 is electrically connected with the third second switch control end K32, the drain of the MK33 is electrically connected with the third terminal TD3 of the detection integrated circuit 130, and the source of the MK33 is electrically connected with the third row third column common electrode part S33;

[0354] The gate of the MK34 is electrically connected with the fourth second switch control end K32, the drain of the MK34 is electrically connected with the fourth terminal TD4 of the detection integrated circuit 130, and the source of the MK34 is electrically connected with the fourth row fourth column common electrode part S34.

[0355] The gate of the MK41 is electrically connected with the fourth first switch control end K41, the drain of the MK42 is electrically connected with the second terminal TD2 of the detection integrated circuit 130, and the source of the MK42 is electrically connected with the fourth row second column common electrode part S42.

[0356] The gate of the MK43 is electrically connected with the fourth second switch control end K42, the drain of the MK43 is electrically connected with the third terminal TD3 of the detection integrated circuit 130, and the source of the MK43 is electrically connected with the fourth row third column common electrode part S43.

[0357] The gate of the MK44 is electrically connected with the fourth second switch control end K32, the drain of the MK44 is electrically connected with the fourth terminal TD4 of the detection integrated circuit 130, and the source of the MK44 is electrically connected with the fourth row fourth column common electrode part S44.

[0358] In at least one embodiment of the display panel shown in FIG. 16, all the transistors are n-type transistors.

[0359] In at least one embodiment of the display panel shown in FIG. 16, the detection period and the compensation period are sequentially arranged, the detection period includes sequentially arranged first, second, third and fourth detection stages, and the compensation period includes sequentially arranged first, second, third and fourth compensation stages.

[0360] In the first detection stage and the first compensation stage, K11 provides a high voltage signal, MK11 and MK12 are turned on, TD1 is connected with S11, and TD2 is connected with S12; K12 provides a high voltage signal, MK13 and MK14 are turned on, TD3 is connected with S13, and TD4 is connected with S14.

[0361] In the second detection stage and the second compensation stage, K21 provides a high voltage signal, MK21 and MK22 are turned on, TD1 is connected with S21, and TD2 is connected with S22; K22 provides a high voltage signal, MK23 and MK24 are turned on, TD3 is connected with S23, and TD4 is connected with S24.

[0362] In the third detection stage and the third compensation stage, K31 provides a high voltage signal, MK31 and MK32 are opened, TD1 is communicated with S31, TD2 is communicated with S32; K32 provides a high voltage signal, MK33 and MK34 are opened, TD3 is communicated with S33, TD4 is communicated with S34;

[0363] In the fourth detection stage and the fourth compensation stage, K41 provides a high voltage signal, MK41 and MK42 are opened, TD1 is communicated with S41, TD2 is communicated with S42; K42 provides a high voltage signal, MK43 and MK44 are opened, TD3 is communicated with S43, TD4 is communicated with S44.

[0364] As shown in FIG. 17, on the basis of at least one embodiment of the display panel shown in FIG. 16, S11 includes a first row and a first column of detection points J11, S12 includes a first row and a second column of detection points J12, S13 includes a first row and a third column of detection points J13, and S14 includes a first row and a fourth column of detection points J14;

[0365] S21 includes a second row and a first column of detection points J21, S22 includes a second row and a second column of detection points J22, S23 includes a second row and a third column of detection points J23, and S24 includes a second row and a fourth column of detection points J24;

[0366] S31 includes a third row and a first column of detection points J31, S32 includes a third row and a second column of detection points J12, S33 includes a third row and a third column of detection points J33, and S34 includes a third row and a fourth column of detection points J34;

[0367] S41 includes a fourth row and a first column of detection points J41, S42 includes a fourth row and a second column of detection points J42, S43 includes a fourth row and a third column of detection points J43, and S44 includes a fourth row and a fourth column of detection points J44;

[0368] Each common electrode part is electrically connected with a corresponding switch transistor through a corresponding detection point;

[0369] As shown in FIG. 18, each common electrode part can be divided into three parts in the vertical direction, from top to bottom, the first part B1, the second part B2, and the third part B3;

[0370] As shown in FIG. 17, J11 is located in the first part included by S11, J12 is located in the second part included by S12, J13 is located in the third part included by S13, and J14 is located in the second part included by S14;

[0371] J21 is located in the first part included by S21, J22 is located in the second part included by S22, J23 is located in the third part included by S23, and J24 is located in the second part included by S24;

[0372] J31 is located in the first part included by S31, J32 is located in the second part included by S32, J33 is located in the third part included by S33, and J14 is located in the second part included by S34;

[0373] J41 is located in the first part included by S41, J42 is located in the second part included by S42, J43 is located in the third part included by S43, and J44 is located in the second part included by S44.

[0374] In at least one embodiment of the present disclosure, S11 and S14 are longitudinally symmetrical, S12 and S13 are longitudinally symmetrical, J11 is contained in the first part of S11, J14 is contained in the second part of S14, the first part and the second part are different; J12 is contained in the second part of S12, J13 is contained in the third part of S13, the second part and the third part are different;

[0375] S21 and S24 are longitudinally symmetrical, S22 and S23 are longitudinally symmetrical, J21 is contained in the first part of S21, J24 is contained in the second part of S24, the first part and the second part are different; J22 is contained in the second part of S22, J23 is contained in the third part of S23, the second part and the third part are different;

[0376] S31 and S34 are longitudinally symmetrical, S32 and S33 are longitudinally symmetrical, J31 is contained in the first part of S31, J34 is contained in the second part of S34, the first part and the second part are different; J32 is contained in the second part of S32, J33 is contained in the third part of S33, the second part and the third part are different;

[0377] S41 and S44 are longitudinally symmetrical, S42 and S43 are longitudinally symmetrical, J41 is contained in the first part of S41, J44 is contained in the second part of S44, the first part and the second part are different; J42 is contained in the second part of S42, J43 is contained in the third part of S43, the second part and the third part are different.

[0378] As shown in FIG. 19, the display panel can further include a first common electrode line CL1, a second common electrode line CL2, a third common electrode line CL3, a fourth common electrode line CL4, a fifth common electrode line CL5, a sixth common electrode line CL6, a seventh common electrode line CL7, an eighth common electrode line CL8, a ninth common electrode line CL9, a tenth common electrode line CL10, an eleventh common electrode line CL11, a twelfth common electrode line CL12, a thirteenth common electrode line CL13, a fourteenth common electrode line CL14, a fifteenth common electrode line CL15, and a sixteenth common electrode line CL16.

[0379] The first common electrode line CL1, the second common electrode line CL2, the third common electrode line CL3, the fourth common electrode line CL4, the fifth common electrode line CL5, the sixth common electrode line CL6, the seventh common electrode line CL7, the eighth common electrode line CL8, the ninth common electrode line CL9, the tenth common electrode line CL10, the eleventh common electrode line CL11, the twelfth common electrode line CL12, the thirteenth common electrode line CL13, the fourteenth common electrode line CL14, the fifteenth common electrode line CL15, and the sixteenth common electrode line CL16 extend along a horizontal direction;

[0380] Each common electrode line can be used to provide a common electrode voltage for the common electrode layer;

[0381] Each common electrode line can be arranged in the same layer as the connection lines between the switching transistors and the common electrode portions.

[0382] In at least one embodiment of the display panel shown in FIG. 16, the compensation voltage signal can be provided to each common electrode portion by the voltage supply circuit arranged below the display area through the plurality of vertically extending signal transmission lines.

[0383] In specific implementation, in at least one embodiment of the display panel shown in FIG. 16, each switching transistor can not be arranged, and the detection integrated circuit is directly electrically connected to each common electrode portion through the wires arranged in the peripheral area to perform common electrode voltage detection; and the compensation voltage signal can be provided to each common electrode portion by the voltage supply circuit arranged below the display area through the plurality of vertically extending signal transmission lines.

[0384] As shown in FIG. 20, on the basis of at least one embodiment of the display panel shown in FIG. 16, the display panel described in at least one embodiment of the present disclosure further includes a first switch control signal generation module 201 and a second switch control signal generation module 202.

[0385] The first switch control signal generation module 201 and the second switch control signal generation module 202 are arranged in the peripheral area.

[0386] The first switch control signal generation module 201 is arranged on the left side of the display area, and the second switch control signal generation module 202 is arranged on the right side of the display area.

[0387] The first switch control signal generation module 201 is electrically connected to K11, K21, K31, and K41 respectively, and is used to provide a first first switch control signal for K11, a second first switch control signal for K21, a third first switch control signal for K31, and a fourth first switch control signal for K41.

[0388] The second switch control signal generation module 202 is electrically connected with K12, K22, K32 and K42 respectively, and is configured to provide a first second switch control signal for K12, a second second switch control signal for K22, a third second switch control signal for K32, and a fourth second switch control signal for K42.

[0389] The display device includes the display panel.

[0390] The above is the preferred embodiment of the present disclosure, it should be pointed out that, for those skilled in the art, without departing from the principles of the present disclosure, can also make a number of improvements and refinements, these improvements and refinements should also be considered as the protection scope of the present disclosure.

Claims

1. A display panel comprising multiple rows and columns of pixel circuits; said pixel circuits including data writing circuits; The data writing circuit is electrically connected to the scanning end and the data line respectively, and is used to access the data voltage provided by the data line under the control of the scanning signal provided by the scanning end; The data writing circuit includes transistors with a first gate and a second gate, and the scanning end includes a first scanning end and a second scanning end; The data writing circuit includes a transistor whose first gate is electrically connected to the first scanning terminal, and a data writing circuit includes a transistor whose second gate is electrically connected to the second scanning terminal. The first gate is the top gate and the second gate is the bottom gate; or, the first gate is the bottom gate and the second gate is the top gate.

2. The display panel as claimed in claim 1, wherein, When the potential of the first scan signal provided by the first scan terminal decreases, the potential of the second scan signal provided by the second scan terminal increases; When the potential of the first scan signal provided by the first scan terminal rises, the potential of the second scan signal provided by the second scan terminal falls.

3. The display panel as claimed in claim 1, wherein, It also includes a drive module; the drive module includes multi-stage drive circuits; The driving circuit includes a first scan signal output terminal and a second scan signal output terminal; The driving module includes an nth-level driving circuit whose first scan signal output terminal is electrically connected to the first scan terminal of the data writing circuit in the nth row pixel circuit. The driving module includes an nth-level driving circuit whose second scan signal output terminal is electrically connected to the second scan terminal of the data writing circuit in the nth row pixel circuit.

4. The display panel as claimed in claim 3, wherein, The driving circuit includes a first node control circuit, a second node control circuit, a first scan signal output circuit, and a second scan signal output circuit. The first node control circuit is electrically connected to the first node and is used to control the potential of the first node; The second node control circuit is electrically connected to the second node and is used to control the potential of the second node; The first scan signal output circuit is electrically connected to the first node, the second node, the output clock signal terminal, the first voltage terminal, and the first scan signal output terminal, respectively. It is used to control the connection between the first scan signal output terminal and the output clock signal terminal under the control of the potential of the first node, and to control the connection between the first scan signal output terminal and the first voltage terminal under the control of the potential of the second node. The second scan signal output circuit is electrically connected to the first node, the first scan signal output terminal, the second scan signal output terminal, the first voltage terminal, and the second voltage terminal, respectively. It is used to control the connection between the second scan signal output terminal and the second voltage terminal under the control of the potential of the first node, and to control the connection between the second scan signal output terminal and the first voltage terminal under the control of the first scan signal provided by the first scan signal output terminal. The voltage value of the first voltage signal provided by the first voltage terminal is less than the voltage value of the second voltage signal provided by the second voltage terminal.

5. The display panel as claimed in claim 4, wherein, The first scan signal output circuit includes a first output transistor and a second output transistor; The gate of the first output transistor is electrically connected to the first node, the first terminal of the first output transistor is electrically connected to the output clock signal terminal, and the second terminal of the first output transistor is electrically connected to the first scan signal output terminal. The gate of the second output transistor is electrically connected to the second node, the first terminal of the second output transistor is electrically connected to the first scan signal output terminal, and the second terminal of the second output transistor is electrically connected to the first voltage terminal.

6. The display panel as claimed in claim 4, wherein, The second scan signal output circuit includes a third output transistor and a fourth output transistor; The gate of the third output transistor is electrically connected to the first node, the first terminal of the third output transistor is electrically connected to the second scan signal output terminal, and the second terminal of the third output transistor is electrically connected to the second voltage terminal. The gate of the fourth output transistor is electrically connected to the first scan signal output terminal, the first terminal of the fourth output transistor is electrically connected to the second scan signal output terminal, and the second terminal of the fourth output transistor is electrically connected to the first voltage terminal.

7. The display panel according to any one of claims 1 to 6, wherein, It also includes a substrate; the pixel circuit is disposed on the substrate; The projection of the top gate of the transistor included in the data writing circuit onto the substrate does not overlap with the projection of the connection electrode of the transistor included in the data writing circuit onto the substrate. The data writing circuit includes the source and drain of the transistor as the connection electrodes of the transistor.

8. The display panel according to any one of claims 1 to 6, wherein, It also includes a substrate; the pixel circuit is disposed on the substrate; The overlap area between the orthographic projection of the top gate of the transistor included in the data writing circuit on the substrate and the orthographic projection of the connection electrode of the transistor included in the data writing circuit on the substrate is the first area. The overlapping area between the orthographic projection of the bottom gate of the transistor included in the data writing circuit on the substrate and the orthographic projection of the connection electrode of the transistor included in the data writing circuit on the substrate is the second area. The first area is smaller than the second area; The data writing circuit includes the source and drain of the transistor as the connection electrodes of the transistor.

9. The display panel according to any one of claims 1 to 6, wherein, It also includes a substrate, a light-shielding metal layer, a semiconductor layer, and a gate metal layer; The light-shielding metal layer, semiconductor layer, and gate metal layer are arranged sequentially along a direction away from the substrate; The semiconductor layer includes the channel of the transistor included in the data writing circuit; the orthographic projection of the light-shielding metal layer on the substrate covers the orthographic projection of the channel on the substrate; The light-shielding metal layer includes the bottom gate, and the gate metal layer includes the top gate.

10. The display panel according to any one of claims 1 to 6, wherein, It also includes multi-row, multi-column touch electrode blocks, multi-column signal transmission lines, and voltage supply circuits; the multi-row, multi-column touch electrode blocks are independent of each other; The voltage supply circuit is electrically connected to the first end of the signal transmission line, and the signal transmission line includes a connection point, which is electrically connected to the touch electrode block. The voltage supply circuit is used to provide a corresponding common electrode voltage to the signal transmission line during the display stage, based on the resistance between the first end of the signal transmission line and the connection point of the signal transmission line.

11. The display panel as claimed in claim 2, wherein, It also includes a common electrode layer and a detection integrated circuit; The common electrode layer includes multiple common electrode sections, which are interconnected. The common electrode section includes at least one detection point; The detection integrated circuit is electrically connected to the common electrode through the detection point and is used to detect the potential of the detection point during the detection phase; the detection integrated circuit is also used to obtain a corresponding compensation voltage signal based on the potential of the detection point and the target common electrode voltage signal.

12. The display panel as claimed in claim 11, wherein, The detection point is directly electrically connected to the detection integrated circuit.

13. The display panel as claimed in claim 12, wherein, The common electrode layer includes multiple rows and columns of common electrode sections; the display panel includes a display area and a peripheral area, and the pixel circuit is disposed in the display area; The detection point extends to the surrounding area via a first connecting line extending along the row direction, and the first connecting line is electrically connected to the detection integrated circuit via a second connecting line disposed in the surrounding area.

14. The display panel as claimed in claim 11, wherein, It also includes a switch control module, which comprises multiple switch control circuits; The control terminal of the switch control circuit is electrically connected to the corresponding switch control terminal. The first terminal of the switch control circuit is electrically connected to the detection integrated circuit, and the second terminal of the switch control circuit is electrically connected to the detection point. The switch control circuit is used to control the connection between the detection integrated circuit and the detection point during the corresponding detection phase included in the detection cycle. The detection integrated circuit is used to detect the potential of the detection point during the corresponding detection stage.

15. The display panel as claimed in claim 14, wherein, The switch control circuit is used to control the connection between the detection integrated circuit and the detection point during the corresponding compensation phase included in the compensation cycle; The detection integrated circuit is used to transmit the corresponding compensation voltage signal to the corresponding common electrode section through the switch control circuit during the corresponding compensation phase.

16. The display panel as claimed in claim 11, wherein, The common electrode layer includes N rows and 2M columns of common electrode sections; N and M are positive integers; the display panel also includes a first switch control module and a second switch control module; the first switch control module includes N first switch control units, and the second switch control module includes N second switch control units; The first switch control unit includes M first switch control circuits, and the second switch control unit includes M second switch control circuits; The display panel includes a display area and a peripheral area. The pixel circuit is disposed in the display area, and the first switch control module and the second switch control module are disposed in the peripheral area. The first switch control module is disposed on a first side of the display area, and the second switch control module is disposed on a second side of the display area. The first side and the second side are opposite sides. The m-th first switch control circuit in the n-th first switch control unit is electrically connected to the n-th first switch control terminal, the detection integrated circuit, and the common electrode section in the n-th row and m-th column, respectively, and is used to control the connection between the detection integrated circuit and the detection points included in the common electrode section in the n-th row and m-th column under the control of the switch control signal provided by the n-th first switch control terminal; The m-th second switch control circuit in the n-th second switch control unit is electrically connected to the n-th second switch control terminal, the detection integrated circuit, and the common electrode section in the n-th row and M+m-th column, respectively, and is used to control the connection between the detection integrated circuit and the detection points included in the common electrode section in the n-th row and M+m-th column under the control of the switch control signal provided by the n-th second switch control terminal; n is a positive integer less than or equal to N; m is a positive integer less than or equal to M.

17. The display panel as claimed in claim 16, wherein, The common electrode section includes multiple parts arranged sequentially along a first direction; The detection point of the common electrode section in row n and column m is included in the a-th part of the common electrode section in row n and column m; The detection point of the common electrode section in row n and column M+m is included in the b-th part of the common electrode section in row n and column M+m. Both a and b are positive integers, and a is not equal to b.

18. The display panel as claimed in claim 16, wherein, It also includes a first switch control signal generation module and a second switch control signal generation module disposed in the surrounding area; the first switch control signal generation module is disposed on a first side of the display area, and the second switch control signal generation module is disposed on a second side of the display area; The first switch control signal generation module is electrically connected to N first switch control terminals respectively, and is used to provide an effective switch control signal to the nth first switch control terminal during the nth detection stage of the detection cycle; The second switch control signal generation module is electrically connected to N second switch control terminals respectively, and is used to provide an effective switch control signal to the nth second switch control terminal during the nth detection stage of the detection cycle; The detection integrated circuit is used in the nth detection stage to detect the potential of the detection points included in each common electrode section located in the nth row.

19. The display panel as claimed in claim 18, wherein, The first switch control signal generation module is electrically connected to N first switch control terminals respectively, and is used to provide an effective switch control signal to the nth first switch control terminal during the nth compensation stage included in the compensation period; The second switch control signal generation module is electrically connected to N second switch control terminals respectively, and is used to provide an effective switch control signal to the nth second switch control terminal during the nth compensation stage included in the compensation cycle; The detection integrated circuit is used to transmit the corresponding compensation voltage signal to the corresponding common electrode section during the nth compensation stage.

20. The display panel as claimed in claim 12, 13, 14, 16 or 17, wherein, It also includes voltage supply circuitry and multiple rows of signal transmission lines; The voltage supply circuit is electrically connected to the common electrode section through the signal transmission line, and is used to provide the compensation voltage signal to the signal transmission line during the compensation phase.

21. A display device comprising a display panel as claimed in any one of claims 1 to 20.

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