Electronic paper display substrate and display device

Abstract

An electronic paper display substrate and a display device. The electronic paper display substrate comprises: a base substrate; first signal lines and second signal lines, a plurality of first signal lines and a plurality of second signal lines intersecting to define a plurality of pixel regions; pixel electrodes and common electrodes, arranged in the pixel regions; and an insulating layer, arranged between the pixel electrodes and the common electrodes. First portions of the first signal lines and the common electrodes are arranged on the same layer, second portions of the first signal lines and the pixel electrodes are arranged on the same layer, and the first portions are electrically connected to the second portions through via holes in the insulating layer; the orthographic projection of the first portions on the base substrate is a first projection, the orthographic projection of the second portions on the base substrate is a second projection, and the orthographic projection of the pixel electrodes on the base substrate is a third projection; and a first distance between the first projection and the third projection in a second direction is less than a second distance between the second projection and the third projection in the second direction, so that the sides of the pixel electrodes close to the first portions can be made larger so as to increase the pixel aperture ratio.

Description

Electronic paper display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202410831663.1, filed on June 25, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] At least one embodiment of this disclosure relates to an electronic paper display substrate and a display device. Background Technology

[0003] Electronic paper is a high-tech display technology that mimics the texture and reading experience of traditional paper, but with the ability to update content. Electronic paper mostly uses electrophoresis display (EPD) technology, and its display effect is close to that of natural paper, reducing reading fatigue. However, with the development of display technology, the pixel aperture ratio of electronic paper needs to be improved. Summary of the Invention

[0004] At least one embodiment of this disclosure provides an electronic paper display substrate and a display device.

[0005] At least one embodiment of this disclosure provides an electronic paper display substrate, comprising: a substrate; a plurality of first signal lines and a plurality of second signal lines disposed on the substrate, the plurality of first signal lines extending along a first direction and arranged along a second direction, the plurality of second signal lines extending along the second direction and arranged along the first direction; the first direction and the second direction intersect, the plurality of first signal lines and the plurality of second signal lines intersecting to define a plurality of pixel regions; a pixel electrode and a common electrode disposed in the pixel regions; an insulating layer disposed between the pixel electrode and the common electrode; wherein, the first signal lines include a first portion and a second portion, the first portion being disposed in the same layer as the common electrode, the second portion being disposed in the same layer as the pixel electrode, and the first portion being electrically connected to the second portion through a via in the insulating layer; the orthographic projection of the first portion on the substrate is a first projection, the orthographic projection of the second portion on the substrate is a second projection, and the orthographic projection of the pixel electrode on the substrate is a third projection; a first distance between the first projection and the third projection in the second direction is less than a second distance between the second projection and the third projection in the second direction.

[0006] For example, according to at least one embodiment of this disclosure, the first projection and the third projection do not overlap.

[0007] For example, according to at least one embodiment of this disclosure, the first spacing is 0.

[0008] For example, according to at least one embodiment of the present disclosure, at least one first signal line includes a plurality of first portions and a plurality of second portions, and the plurality of first portions and the plurality of second portions are alternately arranged in the first direction.

[0009] For example, according to at least one embodiment of the present disclosure, the pixel electrode includes a main body portion and a protruding portion connected to each other; at least a portion of the orthographic projection of the protruding portion on the substrate is located between the orthographic projection of the main body portion on the substrate and the first projection.

[0010] For example, according to at least one embodiment of this disclosure, the first signal line is a data line and the second signal line is a gate line; the electronic paper display substrate further includes a transistor disposed on the substrate, the gate of the transistor is connected to the gate line, the source of the transistor is connected to the data line, and the drain of the transistor is connected to the pixel electrode; the transistor is located on one side of the pixel electrode in the first direction, and the protrusion includes a first protrusion connected to at least one side of the main body portion along the second direction.

[0011] For example, according to at least one embodiment of the present disclosure, the protruding portion further includes a second protruding portion connected to at least one side of the main body portion along the first direction, wherein the orthographic projection of the second protruding portion on the substrate does not overlap with the orthographic projection of the gate line on the substrate, and the orthographic projection of the second protruding portion on the substrate does not overlap with the orthographic projection of the transistor on the substrate.

[0012] For example, according to at least one embodiment of the present disclosure, the gate line includes a gate body portion and a gate connection portion connected to each other; the gate body portion includes the gate gate, the width of the gate connection portion in the first direction is smaller than the width of the gate body portion in the first direction, and the gate connection portion overlaps with the orthographic projection of the second protrusion portion on a straight line extending along the second direction.

[0013] For example, according to at least one embodiment of this disclosure, the first signal line is a gate line, and the second signal line is a data line; the electronic paper display substrate further includes a transistor disposed on the substrate, the gate of the transistor is connected to the gate line, the source of the transistor is connected to the data line, and the drain of the transistor is connected to the pixel electrode; the transistor is located on one side of the pixel electrode in the second direction, and at least a portion of the protrusion is connected to at least one side of the main body portion along the second direction.

[0014] For example, according to at least one embodiment of the present disclosure, the first part includes a first main body and a first adapter connected to each other, and the second part includes a second main body and a second adapter connected to each other; the first adapter is electrically connected to the second adapter through the via; the orthographic projection of the first adapter on the substrate overlaps with the orthographic projection of the second adapter on the substrate.

[0015] For example, according to at least one embodiment of this disclosure, the first signal line is a data line, and the second signal line is a gate line; the electronic paper display substrate further includes a transistor disposed on the substrate, the gate of the transistor is connected to the gate line, the source of the transistor is connected to the data line, and the drain of the transistor is connected to the pixel electrode; the gate is disposed on the same layer as the first portion, and the source and the drain are both disposed on the same layer as the second portion; the transistor further includes an active layer, the gate is located on the side of the active layer away from the substrate, and a gate insulating layer is disposed between the active layer and the gate.

[0016] For example, according to at least one embodiment of this disclosure, the first signal line is a data line, and the second signal line is a gate line; the electronic paper display substrate further includes a transistor disposed on the substrate, the gate of the transistor is connected to the gate line, the source of the transistor is connected to the data line, and the drain of the transistor is connected to the pixel electrode; the gate is disposed on the same layer as the first portion, and the source and the drain are both disposed on the same layer as the second portion; the transistor further includes an active layer, the active layer is located on the side of the gate away from the substrate, and a gate insulating layer is disposed between the active layer and the gate.

[0017] For example, according to at least one embodiment of the present disclosure, the electronic paper display substrate further includes a common connection line extending along the second direction, the common connection line connecting a common electrode of two adjacent pixel regions; the pixel electrode has a first edge and a second edge disposed opposite to each other in the first direction, the first edge being located on the side of the second edge away from the transistor electrically connected to the pixel electrode; the maximum distance between the edge of the orthographic projection of the common connection line on the substrate and the orthographic projection of the first edge on the substrate is a first distance, the minimum distance between the edge of the orthographic projection of the common connection line on the substrate and the orthographic projection of the second edge on the substrate is a second distance, and the first distance is less than the second distance.

[0018] For example, according to at least one embodiment of the present disclosure, the pixel electrode includes a main body portion and a protrusion portion connected to at least one side of the main body portion; the ratio of the maximum dimension of the first portion in the first direction to the maximum dimension of the main body portion in the first direction is 0.5 to 1.

[0019] For example, according to at least one embodiment of this disclosure, the first signal line is a gate line and the second signal line is a data line; the electronic paper display substrate further includes a transistor disposed on the substrate, the gate of the transistor is connected to the gate line, the source of the transistor is connected to the data line, and the drain of the transistor is connected to the pixel electrode; the gate is disposed on the same layer as the second portion, and the source and the drain are both disposed on the same layer as the first portion.

[0020] For example, according to at least one embodiment of the present disclosure, the electronic paper display substrate further includes a common connection line extending along the second direction, the common connection line connecting a common electrode of two adjacent pixel regions; the first projection is located on the side where the orthogonal projection of the common connection line on the substrate is away from the orthogonal projection of the source of the transistor on the substrate.

[0021] At least one embodiment of this disclosure provides a display device including the electronic paper display substrate described in any of the above embodiments. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0023] Figure 1 is a planar schematic diagram of an electronic paper display substrate for an electronic paper product.

[0024] Figure 2 is a partial planar schematic diagram of an electronic paper display substrate provided in at least one embodiment of the present disclosure.

[0025] Figure 3 is a planar schematic diagram of one pixel region in Figure 2.

[0026] Figure 4A is a schematic diagram of the film layer where the common electrode is located in Figure 3.

[0027] Figure 4B is a schematic diagram of the film layer where the pixel electrode is located in Figure 3.

[0028] Figure 5 is a schematic diagram of the cross-section at AA' shown in Figure 3.

[0029] Figure 6 is a schematic diagram of the first, second, and third projections of the electronic paper display substrate shown in Figure 3.

[0030] Figure 7 is a schematic diagram of the data lines on the electronic paper display substrate shown in Figure 3.

[0031] Figure 8 is a schematic diagram of the cross-section at BB' shown in Figure 3.

[0032] Figure 9A is a cross-sectional schematic diagram of an electronic paper display substrate for an electronic paper product.

[0033] Figure 9B is a partial schematic diagram of Figure 9A.

[0034] Figure 10 is a partial planar schematic diagram of an electronic paper display substrate provided in at least one embodiment of the present disclosure.

[0035] Figure 11 is a schematic cross-sectional view of CC' shown in Figure 10.

[0036] Figure 12 is a partial planar schematic diagram of an electronic paper display substrate provided in at least one embodiment of the present disclosure.

[0037] Figures 13A to 13G are cross-sectional views of the steps involved in fabricating the transistors in the electronic paper display substrate shown in Figure 12.

[0038] Figures 14A and 14B are cross-sectional views of partial steps in the fabrication of a transistor provided in another example of at least one embodiment of this disclosure.

[0039] Figure 15 is a partial planar schematic diagram of an electronic paper display substrate provided in at least one embodiment of the present disclosure.

[0040] Figure 16 is a planar schematic diagram of one pixel region in Figure 15.

[0041] Figure 17 is a schematic diagram of the cross-section at MM' shown in Figure 16.

[0042] Figure 18 is a cross-sectional schematic diagram of NN' shown in Figure 16.

[0043] Figure 19 is a planar schematic diagram of an electronic paper display substrate.

[0044] Figure 20 is a schematic diagram of the film layer structure of an electronic paper display substrate. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0046] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0047] The terms “perpendicular,” “parallel,” and “identical” as used in this disclosure include the strictly defined meanings of “perpendicular,” “parallel,” and “identical,” as well as terms such as “approximately perpendicular,” “approximately parallel,” and “approximately identical” which contain a certain degree of error. Taking into account the measurement and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), they represent the acceptable deviation range for a particular value as determined by a person skilled in the art.

[0048] Electronic paper products utilize the reflection of a paper film to achieve a display effect. Colored particles in the paper film can move up and down under the influence of an electric field, thus displaying text or images by the colored particles on the upper layer under the control of the electric field. In their research, the inventors of this application discovered that electronic paper products have a low aperture ratio, which makes it difficult to improve the brightness of electronic paper products, hinders energy consumption reduction, and limits the clarity of the displayed image.

[0049] Figure 1 is a planar schematic diagram of a display substrate for an electronic paper product.

[0050] For example, referring to Figure 1, in some electronic paper products, the display substrate includes data lines 11, gate lines 12, transistors 13, pixel electrodes 14, and common electrodes 15. Data lines 11 and pixel electrodes 14 are disposed on the same layer, and gate lines 12 and common electrodes 15 are disposed on the same layer. To prevent short circuits and other issues, a minimum safe distance must be maintained between pixel electrodes 14 and data lines 11. Therefore, the area of ​​pixel electrodes 14 is limited, resulting in a low aperture ratio. Taking a pixel unit with a size of 194 × 194 square micrometers in the aforementioned display substrate as an example, the pixel aperture ratio is approximately 78.9%.

[0051] At least one embodiment of this disclosure provides an electronic paper display substrate, comprising: a substrate; a plurality of first signal lines and a plurality of second signal lines disposed on the substrate, the plurality of first signal lines extending along a first direction and arranged along a second direction, the plurality of second signal lines extending along the second direction and arranged along the first direction; the first direction and the second direction intersect, the plurality of first signal lines and the plurality of second signal lines intersecting to define a plurality of pixel regions; a pixel electrode and a common electrode disposed in the pixel regions; an insulating layer disposed between the pixel electrode and the common electrode; wherein, the first signal lines include a first portion and a second portion, the first portion being disposed in the same layer as the common electrode, the second portion being disposed in the same layer as the pixel electrode, and the first portion being electrically connected to the second portion through a via in the insulating layer; the orthographic projection of the first portion on the substrate is a first projection, the orthographic projection of the second portion on the substrate is a second projection, and the orthographic projection of the pixel electrode on the substrate is a third projection; a first distance between the first projection and the third projection in the second direction is less than a second distance between the second projection and the third projection in the second direction.

[0052] At least one embodiment of this disclosure provides a display device including the electronic paper display substrate described in any of the above embodiments.

[0053] In at least one embodiment of the electronic paper display substrate and display device disclosed herein, the first portion and the second portion of the data line are located on different layers, and the first portion and the pixel electrode are located on different layers. The portion of the pixel electrode closer to the first portion does not require consideration of a minimum safe distance from the data line. Furthermore, the first distance between the first projection and the third projection in the second direction is smaller than the second distance between the second projection and the third projection in the second direction, allowing the side of the pixel electrode closer to the first portion to be made larger to increase the pixel aperture ratio.

[0054] The electronic paper display substrate and display device are described below with reference to the accompanying drawings and through some embodiments.

[0055] Figure 2 is a partial planar schematic diagram of an electronic paper display substrate provided in at least one embodiment of the present disclosure.

[0056] Referring to FIG2, at least one embodiment of the present disclosure provides an electronic paper display substrate, including a substrate 10, a first signal line 100, a second signal line 200, a pixel electrode 300, a common electrode 400, and an insulating layer 500.

[0057] The following explanation uses the first signal line 100 as the data line 101 and the second signal line 200 as the gate line 201.

[0058] Referring to Figure 2, multiple data lines 101 and multiple gate lines 201 are disposed on a substrate 10. The multiple data lines 101 extend along a first direction X and are arranged along a second direction Y. The multiple gate lines 201 extend along the second direction Y and are arranged along the first direction X. The first direction X and the second direction Y intersect. The multiple data lines 101 and the multiple gate lines 201 intersect to define multiple pixel regions 01. Pixel electrodes 300 and common electrodes 400 are disposed in the pixel regions 01, and an insulating layer 500 is disposed between the pixel electrodes 300 and the common electrodes 400. For example, the pixel electrodes 300 in different pixel regions 01 are insulated from each other. For example, the common electrode 400 and the pixel electrode 300 can be made of a transparent conductive material. For example, the material of the common electrode 400 and the pixel electrode 300 can include indium tin oxide (ITO). For example, the common electrode 400 can be located on the side of the pixel electrode 300 away from the substrate 10. For example, the pixel electrode 300 can be located on the side of the common electrode 400 away from the substrate 10.

[0059] For example, referring to Figure 2, multiple pixel regions 01 are arranged in an array along a first direction X and a second direction Y, with the first direction X intersecting the second direction Y. For example, the first direction X is perpendicular to the second direction Y. However, it is not limited to this; the angle between the first direction X and the second direction Y can be 80 to 100 degrees, such as 85 to 95 degrees. For example, pixel region 01 is a display area for displaying images, and the substrate 10 also includes a peripheral area surrounding the display area.

[0060] Referring to Figure 2, in some examples, at least one data line 101 includes a plurality of first portions 110 and a plurality of second portions 120, which are alternately arranged in a first direction X. As shown in Figure 2, in the first direction X, the first portions 110 of the data line 101 are disposed between two second portions 120, thereby enabling the transmission of image data signals, such as those between two adjacent pixel areas 01 in the first direction X.

[0061] Figure 3 is a planar schematic diagram of a pixel region in Figure 2. Figure 4A is a schematic diagram of the film layer where the common electrode is located in Figure 3. Figure 4B is a schematic diagram of the film layer where the pixel electrode is located in Figure 3. Figure 5 is a cross-sectional schematic diagram of AA' shown in Figure 3.

[0062] Referring to Figures 3 to 5, the data line 101 includes a first portion 110 and a second portion 120. As shown in Figure 4A, the first portion 110 is disposed on the same layer as the common electrode 400. As shown in Figure 4B, the second portion 120 is disposed on the same layer as the pixel electrode 300. Referring to Figures 3 to 5, the first portion 110 is electrically connected to the second portion 120 through a via 510 in the insulating layer 500. The first portion 110 and the second portion 120 of the data line 101 are located on different layers, and the first portion 110 and the pixel electrode 300 are located on different layers. The portion of the pixel electrode 300 closest to the first portion 110 does not need to consider the minimum safe distance between it and the data line 101.

[0063] Figure 6 is a schematic diagram of the first, second, and third projections of the electronic paper display substrate shown in Figure 3.

[0064] Referring to Figures 3 and 6, the orthographic projection of the first portion 110 on the substrate 10 is the first projection 110a, the orthographic projection of the second portion 120 on the substrate 10 is the second projection 120a, and the orthographic projection of the pixel electrode 300 on the substrate 10 is the third projection 300a. The first distance D11 between the first projection 110a and the third projection 300a in the second direction Y is smaller than the second distance D12 between the second projection 120a and the third projection 300a in the second direction Y. Because the first distance D11 is smaller than the second distance D12, the side of the pixel electrode 300 closer to the first portion 110 can be made larger to increase the pixel aperture ratio. For example, the second distance D12 between the second portion 120 and the pixel electrode 300, which are disposed in the same layer as the pixel electrode 300, can be the minimum safe distance between metals in the same layer.

[0065] In some examples, the first spacing can be 0, meaning that the outer contour edges of the first projection and the third projection can overlap, thereby maximizing the area of ​​the pixel electrode.

[0066] In some examples, as shown in FIG6, the first projection 110a and the third projection 300a do not overlap, thereby preventing the pixel electrode 300 and the data line 101 from having overlapping portions in the direction perpendicular to the substrate and thus generating coupling capacitance.

[0067] For example, referring to Figures 3 and 6, the size of the second spacing D12 is 2 micrometers to 5 micrometers, thereby maintaining a minimum safe distance between the second portion 120 and the pixel electrode 300. For example, the size of the second spacing is 2.5 micrometers to 4.5 micrometers. For example, the size of the second spacing is 3 micrometers to 4 micrometers. For example, the size of the second spacing is 3 micrometers.

[0068] Referring to Figures 3 and 6, in some examples, the pixel electrode 300 includes a main body portion 310 and a protruding portion 320 connected to each other. At least a portion of the orthographic projection 320a of the protruding portion 320 on the substrate 10 is located between the orthographic projection 310a of the main body portion 310 on the substrate 10 and a first projection 110a. Providing the protruding portion 320 increases the overall area of ​​the pixel electrode 300, thereby increasing the pixel aperture ratio. For example, the orthographic projection of the protruding portion on the substrate may be partially located between the orthographic projection of the main body portion on the substrate and the first projection, and partially overlap with the first projection. For example, the orthographic projection of the protruding portion on the substrate may also be partially located on both sides of the orthographic projection of the main body portion on the substrate along a first direction. For example, the orthographic projections of the protruding portions located on both sides of the orthographic projection of the main body portion on the substrate along a second direction may be completely located between the orthographic projection of the main body portion on the substrate and the first projection, and do not overlap with the first projection, thereby preventing coupling capacitance between the protruding portion and the first portion. For example, the main body portion and the protruding portion are integrally formed. For example, the outer contour of the main body is roughly rectangular, and the drain portion (e.g., drain 630 in the example described later) and the protrusion portion, which are integral structures with the main body, are located in the peripheral area of ​​the rectangle. However, this disclosure is not limited to this, and the protrusion portion, the drain portion, and the main body portion may also be independent parts rather than integral structures.

[0069] Figure 7 is a schematic diagram of the data lines on the electronic paper display substrate shown in Figure 3.

[0070] Referring to Figures 3, 6, and 7, in some examples, the first portion 110 includes a first main body portion 111 and a first adapter portion 112 connected to each other, and the second portion 120 includes a second main body portion 121 and a second adapter portion 122 connected to each other. The first adapter portion 112 is electrically connected to the second adapter portion 122 through a via 510. The orthographic projection of the first adapter portion 112 on the substrate 10 overlaps with the orthographic projection of the second adapter portion 122 on the substrate 10, thereby achieving the electrical connection between the first portion 110 and the second portion 120. For example, the orthographic projection of the first adapter portion 112 on the substrate 10 covers the orthographic projection of the via 510, and the orthographic projection of the second adapter portion 122 on the substrate 10 covers the orthographic projection of the via 510. For example, the orthographic projection of the via 510 on the substrate 10 may be located within the orthographic projection of the first adapter portion 112 on the substrate 10, and also within the orthographic projection of the second adapter portion 122 on the substrate 10. For example, the orthographic projection of the first adapter 112 on the substrate 10 covers the orthographic projection of the via 510 on the substrate 10, and the orthographic projection of the second adapter 122 on the substrate 10 covers the orthographic projection of the via 510 on the substrate 10, thereby improving the electrical connection reliability of the first part 110 and the second part 120.

[0071] Referring to Figures 3 and 7, in some examples, the protrusion 320 is connected to at least one side of the main body 310, and the ratio of the maximum dimension L1 of the first part 110 in the first direction X to the maximum dimension L2 of the main body 310 in the first direction X is 0.5 to 1. For example, the dimensions of the first transition portion 112 in the first part 110 and the second transition portion 122 in the second part 120 can be made smaller, and the distance between the two first transition portions 112 disposed opposite each other in the first direction X can be made larger, thereby extending the dimension of the first part 110 in the first direction X and increasing the area of ​​the protrusion 320.

[0072] For example, the ratio of the maximum dimension of the first part in the first direction to the maximum dimension of the main body in the first direction is 0.55 to 0.95. For example, the ratio of the maximum dimension of the first part in the first direction to the maximum dimension of the main body in the first direction is 0.6 to 0.9. For example, the ratio of the maximum dimension of the first part in the first direction to the maximum dimension of the main body in the first direction is 0.65 to 0.85. For example, the ratio of the maximum dimension of the first part in the first direction to the maximum dimension of the main body in the first direction is 0.7 to 0.8. For example, the ratio of the maximum dimension of the first part in the first direction to the maximum dimension of the main body in the first direction is 0.75.

[0073] Referring to Figures 2, 6, and 7, for example, in two adjacent pixel regions 01 arranged along the second direction Y, the spacing between the two pixel electrodes 300 in the second direction Y is 9 micrometers to 11 micrometers. For example, this spacing is the spacing between two adjacent protrusions in the second direction Y. For example, the spacing is 9.5 micrometers to 10.5 micrometers. For example, the spacing is 10 micrometers. Thus, the spacing between the two pixel electrodes 300 can prevent the pixel electrodes 300 from overlapping with the first transition portion 112 in a direction perpendicular to the substrate 10, and can ensure a minimum safe distance between the pixel electrodes 300 and the second transition portion 122.

[0074] Referring to Figures 2 and 3, in some examples, the electronic paper display substrate further includes a transistor 600 disposed on the substrate, with the gate 610 of the transistor 600 connected to the gate line 201. For example, the transistor 600 used in the embodiments of this disclosure can be a thin-film transistor, a field-effect transistor, or other switching devices with the same characteristics. The embodiments of this disclosure are all described using a thin-film transistor as an example. The transistor 600 includes a gate 610, a source 620, and a drain 630. The source 620 and drain 630 of the transistor 600 used here can be symmetrical in structure, so their source 620 and drain 630 can be structurally indistinguishable. The number of transistors connected to the same pixel electrode can be one or more. Figures 2 and 3 schematically show a dual-gate transistor, but it is not limited to this; a single-gate transistor can also be used. For example, the transistors in the embodiments of this disclosure can adopt a top-gate structure or a bottom-gate structure, and this disclosure does not limit this.

[0075] Referring to Figures 2 and 3, the source 620 of transistor 600 is connected to data line 101, and the drain 630 of transistor 600 is connected to pixel electrode 300. The figures schematically show the source and data line as an integral structure, but this disclosure is not limited to this; the source and data line may also be non-integrated structures. For example, gate line 201 is electrically connected to the gate 610 of transistor 600 to control the opening or closing of transistor 600, pixel electrode 300 is electrically connected to the drain 630 of transistor 600, and data line 101 is electrically connected to the source 620 of transistor 600. Data line 101 inputs the voltage signal required for displaying the image to pixel electrode 300 through transistor 600 to realize the display panel.

[0076] Referring to Figures 2 and 3, the transistor 600 is located on one side of the pixel electrode 300 in the first direction X, and the protrusion 320 includes a first protrusion 321 connected to at least one side of the main body portion 310 along the second direction Y. The first protrusion 321 can increase the overall area of ​​the pixel electrode 300. At the same time, the data lines 101 disposed on both sides of the main body portion 310 in the second direction Y do not need to consider avoiding the transistor 600 disposed on one side of the pixel electrode 300 in the first direction X, thereby increasing the size of the first portion 110 in the first direction X, and correspondingly increasing the size of the first protrusion 321 in the first direction X, making the overall area of ​​the pixel electrode 300 larger.

[0077] Referring to Figures 2 and 3, for example, the first protrusion 321 can be connected to one side of the main body portion 310 in the second direction Y, or it can be connected to opposite sides of the main body portion 310 in the second direction Y. For example, referring to Figure 2, in two adjacent pixel areas 01 in the second direction Y, the two first protrusions 321 facing each other can be symmetrically arranged with the data line 101 as the axis of symmetry.

[0078] Referring to Figures 2 and 3, for example, the maximum size of the gap between the first protrusion 321 and the second transition portion 122 in the first direction X is 2 micrometers to 5 micrometers, thereby maintaining a minimum safe distance between the second transition portion 122 and the first protrusion 321 in the pixel electrode 300. For example, the maximum size of the gap is 2.5 micrometers to 4.5 micrometers. For example, the maximum size of the gap is 3 micrometers to 4 micrometers. For example, the maximum size of the gap is 3 micrometers.

[0079] Referring to Figures 2 and 3, in some examples, the protrusion 320 further includes a second protrusion 322 connected along the first direction X to at least one side of the main body 310. The orthographic projection of the second protrusion 322 on the substrate does not overlap with the orthographic projection of the gate line 201 on the substrate, and the orthographic projection of the second protrusion 322 on the substrate does not overlap with the orthographic projection of the transistor 600 on the substrate. Therefore, providing the second protrusion 322 increases the overall area of ​​the pixel electrode 300. Furthermore, the second protrusion 322 does not overlap with the gate line 201 in a direction perpendicular to the substrate, preventing the generation of coupling capacitance, and the second protrusion 322 does not interfere with the transistor 600.

[0080] For example, referring to Figures 2 and 3, transistor 600 is positioned near the lower left corner in the plan view, and the second protrusion 322 can be positioned near the lower right corner in the plan view. For example, the second protrusion 322 can be connected to one side of the main body portion 310 in the first direction X, or it can be connected to opposite sides of the main body portion 310 in the first direction X. For example, referring to Figure 2, in two adjacent pixel regions 01 in the first direction X, the second protrusion 322 in the lower pixel region 01 in the plan view will not interfere with transistor 600 in the upper pixel region 01 in the plan view. For example, Figure 2 schematically shows a dual-gate transistor 600. For example, the transistor includes two gates connected in series, the source connected to a data line, and the drain connected to a pixel electrode. When the electronic paper display substrate is used in a high-voltage display device (e.g., electronic paper), the dual-gate transistor can reduce leakage current.

[0081] Of course, a single-gate transistor can also be used to increase the size of the second protrusion in the first direction, and this disclosure is not limited thereto. For example, the transistor can be positioned near the lower center of the plan view, and the second protrusion can include two portions located on either side of the transistor in the second direction.

[0082] Referring to Figures 2 and 3, in some examples, the gate line 201 includes a gate body portion 210 and a gate connection portion 220 connected to each other. The gate body portion 210 includes a gate gate 610. The width W2 of the gate connection portion 220 in the first direction X is smaller than the width W1 of the gate body portion 210 in the first direction X. The gate connection portion 220 overlaps with the orthographic projection of the second protrusion portion 322 on a straight line extending along the second direction Y. The smaller width W2 of the gate connection portion 220 provides greater clearance space for the second protrusion portion 322, increasing the area of ​​the second protrusion portion 322 and thus making the overall area of ​​the pixel electrode 300 larger.

[0083] Referring to Figures 2 and 3, in some examples, the electronic paper display substrate further includes a common connection line 401 extending along the second direction Y, which connects the common electrodes 400 of two adjacent pixel regions 01. For example, the common connection line 401 may be integral with the common electrode 400, but this disclosure is not limited thereto. The pixel electrode 300 has a first edge 301 and a second edge 302 disposed opposite to each other in the first direction X, with the first edge 301 located on the side of the second edge 302 away from the transistor 600 electrically connected to the pixel electrode 300. The maximum distance between the edge of the orthographic projection of the common connection line 401 on the substrate and the orthographic projection of the first edge 301 on the substrate is a first distance D21, and the minimum distance between the edge of the orthographic projection of the common connection line 401 on the substrate and the orthographic projection of the second edge 302 on the substrate is a second distance D22, wherein the first distance D21 is smaller than the second distance D22. For example, the first distance D21 is the spacing between the lower edge of the orthographic projection of the common connection line 401 on the substrate and the orthographic projection of the first edge 301 on the substrate, and the second distance D22 is the spacing between the lower edge of the orthographic projection of the common connection line 401 on the substrate and the orthographic projection of the second edge 302 on the substrate. A longer second distance D22 allows the first portion 110 of the data line 101 to be made longer, thereby increasing the area of ​​the first protrusion 321 and thus making the overall area of ​​the pixel electrode 300 larger.

[0084] The display principle of electronic paper products differs from that of liquid crystal displays (LCDs), and the two also differ significantly in technology and application. For example, electronic paper products rely on reflecting ambient light to achieve visual effects, while LCDs rely on backlighting. For instance, LCDs control the brightness of the LCD by switching transistors on and off. Each transistor corresponds to a display pixel on the LCD panel, and the backplane composed of the array of all pixel transistors directly affects the quality of the display. The switching speed of pixels (i.e., the rate of brightness change) is related to the refresh rate, and the total number of pixels in the display determines the resolution. Electronic paper products, on the other hand, are a reflective display solution. They do not emit their own light and do not require a backlight; they achieve display by reflecting ambient light. This gives them a display effect similar to traditional paper and achieves low power consumption, allowing the image to continue displaying even when the power source is removed.

[0085] For example, electronic paper products use a light-shielding layer in the paper film to shield the thin-film transistors (TFTs), while liquid crystal displays (LCDs) use a black matrix (BM) to shield the TFTs. Some LCDs employ a bottom-gate structure to block backlighting, using an opaque gate metal layer to prevent light from reaching the active layer of the transistors and affecting their off-state current characteristics. Unlike LCDs, electronic paper products do not have a backlight at the bottom; therefore, they can use either a bottom-gate or top-gate structure.

[0086] Figure 8 is a schematic diagram of the cross-section at BB' shown in Figure 3.

[0087] In some examples, the gate 610 is disposed on the same layer as the first portion 110, and the source 620 and drain 630 are both disposed on the same layer as the second portion 120. For example, the pixel electrode 300, source 620, drain 630 and second portion 120 are disposed on the same layer. For example, the common electrode 400, gate 610 and first portion 110 are disposed on the same layer. For example, the transistor 600 can be a bottom-gate structure. Referring to FIG8, in some examples, the transistor 600 further includes an active layer 640, which is located on the side of the gate 610 away from the substrate 10, and a gate insulating layer 650 is disposed between the active layer 640 and the gate 610. It is understood that FIG3 and FIG8 show transistors with a bottom-gate structure in the electronic paper display substrate, and the first signal line (e.g., a data line or a gate line) in the electronic paper display substrate includes a first portion and a second portion of different layers, but this disclosure is not limited thereto, and the first signal line can also be an integral structure of the same layer.

[0088] Figure 9A is a cross-sectional schematic diagram of a display substrate for an electronic paper product.

[0089] Electronic paper products rely on the reflection of ambient light for display. Since the paper film on top of electronic paper products is translucent, sunlight can affect the display effect. Figure 9A shows a display substrate using a bottom-gate transistor structure.

[0090] Referring to Figure 9A, the display substrate includes a substrate 701, a transistor 702, a pixel electrode 703, a common electrode 704, a gate insulating layer 705, and a passivation layer 706. The transistor 702 includes a gate 7021, a source 7022, a drain 7023, and an active layer 7024. To improve the display performance of electronic paper products for outdoor use, a metal layer 707 needs to be placed on top of the thin-film transistors in the electronic paper product for light shielding. This results in an increase in the number of masks. As shown in Figure 9A, the display substrate requires at least four patterning processes, i.e., at least four masks, making the fabrication process cumbersome and costly.

[0091] Figure 9B is a partial schematic diagram of Figure 9A.

[0092] As shown in Figure 9B, the circled area illustrates the conductive channel. In a bottom-gate transistor, the conductive channel needs to penetrate the thickness of the active layer 7024, connecting the source 7022 and drain 7023 from the conductive channel near the lower side of the gate 7021. Furthermore, when the metal layer above the active layer 7024 is etched to form the film containing the source 7022 and drain 7023, the surface of the conductive channel in the active layer 7024 becomes rough due to the etching process, resulting in deteriorated off-state characteristics.

[0093] Figure 10 is a partial planar schematic diagram of an electronic paper display substrate provided in at least one embodiment of the present disclosure. Figure 11 is a cross-sectional schematic diagram at CC' shown in Figure 10.

[0094] As shown in Figures 10 and 11, in some examples, transistor 600 further includes an active layer 640, a gate 610 located on the side of the active layer 640 away from the substrate 10, and a gate insulating layer 650 disposed between the active layer 640 and the gate 610. Thus, the top-gate transistor 600 can shield the active layer 640 through the gate 610, eliminating the need for an additional light-shielding layer and saving a mask. Furthermore, as shown in Figure 11, the conductive channel (circled in Figure 11) is located above the active layer 640, directly and horizontally connecting the source 620 and the drain 630, resulting in lower resistance and a larger on-state current. Additionally, in the top-gate transistor shown in Figure 11, the surface of the conductive channel can be protected by the gate insulating layer from etching. It is understood that Figures 10 and 11 show transistors with a top-gate structure in the electronic paper display substrate, and the first signal line (e.g., a data line or a gate line) in the electronic paper display substrate includes a first part and a second part of different layers, but this disclosure is not limited thereto, and the first signal line may also be an integral structure of the same layer.

[0095] Figure 12 is a partial planar schematic diagram of an electronic paper display substrate provided in at least one embodiment of this disclosure. Figures 13A to 13G are cross-sectional views of the steps involved in fabricating the transistors in the electronic paper display substrate shown in Figure 12. Figure 13G is a cross-sectional schematic diagram along point GG' shown in Figure 12. It should be noted that Figure 12 schematically shows data lines and gate lines, which may have the same or different structures as those shown in Figure 3. Figures 12 and 3 may also differ in other ways, such as the structure of the common electrode, the structure of the pixel electrode, the position and structure of the transistors, or the relative positional relationship of the film layers in the electronic paper display substrate. Of course, Figures 12 and 3 may also have other similarities or differences, which are not limited in this disclosure.

[0096] As shown in Figure 13A, an active material layer 604, a first insulating material layer 605, and a gate material layer 601 are sequentially deposited on a substrate 10. After coating the side of the gate material layer 601 away from the substrate 10 with photoresist 606, a photomask, such as a halftone photomask, is used for exposure. The areas where the active material layer 604, the first insulating material layer 605, and the gate material layer 601 need to be etched are fully exposed; the areas where the active material layer 604 needs to be retained are half-exposed; and the areas where the active material layer 604, the first insulating material layer 605, and the gate material layer 601 need to be retained are not exposed.

[0097] As shown in Figures 13A and 13B, after exposure, a first wet etching is performed to etch away the gate material layer 601 in the fully exposed area, resulting in the remaining photoresist 606a and the gate material intermediate layer 601a.

[0098] As shown in Figures 13B and 13C, after the first wet etching, the first dry etching is performed to remove the fully exposed area of ​​the first insulating material layer 605 and the partially exposed area of ​​the remaining photoresist 606a, resulting in the first insulating material intermediate layer 605a and the remaining photoresist 606b.

[0099] As shown in Figures 13C and 13D, a second wet etching is then performed to etch the semi-exposed area of ​​the gate material intermediate layer 601a to obtain the gate 610.

[0100] As shown in Figures 13D and 13E, a second dry etching is then performed to remove the half-exposed area of ​​the first insulating material intermediate layer 605a and the fully exposed area of ​​the active material layer 604, resulting in the gate insulating layer 650 and the active layer 640.

[0101] As shown in Figure 13F, the exposed portion of the active layer 640 is then doped to form a doped region 640a. A second insulating material layer is then deposited, and the material in the regions of the second insulating material layer that need to connect the upper and lower conductive layers is removed. For example, Figure 13F shows the insulating layer 500 obtained after removing the second insulating material layer from the source and drain regions. Alternatively, a portion of the structure in the gate material layer 601 shown in Figure 13A can be removed to obtain the first transition portion 112 as shown in Figure 7.

[0102] As shown in Figure 13G, a metal layer is then deposited and etched by exposure to obtain a conductive pattern layer. For example, as shown in Figures 13G and 12, the conductive pattern layer may include the source 620 and drain 630 of the transistor 600, may include the pixel electrode 300 in the electronic paper display substrate, and may also include other conductive connection signal lines (such as part of the data line structure), etc., which are not limited in this disclosure.

[0103] Figures 14A and 14B are cross-sectional views of some steps in the fabrication of a transistor provided in another example of at least one embodiment of this disclosure. For example, after obtaining the cross-sectional structure shown in Figure 13E by the fabrication method shown in Figures 13A to 13E, the fabrication steps shown in Figures 14A and 14B can be performed.

[0104] As shown in Figure 14A, after obtaining the gate insulating layer 650 and the active layer 640, a second insulating material layer is deposited, and the material in the region of the second insulating material layer that needs to connect the upper and lower conductive layers is removed to obtain the insulating layer 500. Then, the active layer 640 is doped to obtain the doped layer 640a.

[0105] As shown in Figure 14B, a metal layer is then deposited and etched by exposure to obtain a conductive pattern layer. For example, as shown in Figures 14B and 12, the conductive pattern layer may include the source 620 and drain 630 of the transistor 600, may include the pixel electrode 300 in the electronic paper display substrate, and may also include other conductive connection signal lines (such as part of the data line structure), etc., which are not limited in this disclosure.

[0106] The following explanation uses the first signal line as the gate line and the second signal line as the data line.

[0107] Figure 15 is a partial planar schematic diagram of an electronic paper display substrate provided in at least one embodiment of the present disclosure. Figure 16 is a planar schematic diagram of a pixel area in Figure 15.

[0108] The difference between Figure 15 and Figure 2 is that the first signal line in Figure 2 is a data line, and the second signal line in Figure 2 is a gate line; the first signal line in Figure 15 is a gate line, and the second signal line in Figure 15 is a data line. The pointing direction of the first direction in Figure 2 is different from that in Figure 15, and the pointing direction of the second direction in Figure 2 is different from that in Figure 15. Other differences may also exist between Figure 2 and Figure 15, such as the different structures of the common electrodes, the different structures of the pixel electrodes, and the different relative positions of the film layers in the electronic paper display substrate. Of course, Figure 2 and Figure 15 may also have other similarities or differences, and this disclosure does not limit this.

[0109] Referring to Figures 15 and 16, the relative positional relationship between the first portion 110 and the second portion 120 of the gate line 201 and the pixel electrode 300 can be referred to the description in the foregoing embodiments, and will not be repeated here. As shown in Figure 15, in the first direction X, the first portion 110 of the gate line 201 is disposed between the two second portions 120, thereby realizing the transmission of signals such as scan signals or turn-on signals between two adjacent pixel areas 01 in the first direction X.

[0110] Referring to Figures 15 and 16, in some examples, the electronic paper display substrate further includes a transistor 600 disposed on the substrate. The gate 610 of the transistor 600 is connected to the gate line 201, the source 620 of the transistor 600 is connected to the data line 101, and the drain 630 of the transistor 600 is connected to the pixel electrode 300. The transistor 600 shown in Figures 15 and 16 may be the same as or different from the transistor 600 shown in Figure 2 above. This disclosure does not limit this and will not elaborate further. The transistor 600 is located on one side of the pixel electrode 300 in the second direction Y, and at least a portion of the protrusion 320 is connected to at least one side of the main body portion 310 along the second direction Y. For example, the first portion 110 of the gate line 201 is on a different layer from the pixel electrode 300, thereby enabling the protrusion 320 to be provided on the side of the main body portion 310 near the first portion 110, thereby increasing the overall area of ​​the pixel electrode 300.

[0111] Referring to Figure 16, in some examples, the electronic paper display substrate also includes a common connection line 401 extending along the second direction Y, which connects the common electrode 400 of two adjacent pixel regions 01. The orthographic projection of the first portion 110 on the substrate is a first projection, which is located on the side of the orthographic projection of the common connection line 401 on the substrate that is away from the orthographic projection of the source 620 of the transistor 600 on the substrate. This makes the first portion 110 larger in the first direction X, increases the area of ​​the protrusion 320, and makes the overall area of ​​the pixel electrode 300 larger.

[0112] Figure 17 is a cross-sectional schematic diagram of MM' shown in Figure 16. Figure 18 is a cross-sectional schematic diagram of NN' shown in Figure 16.

[0113] Referring to Figures 17 and 18, in some examples, the gate 610 is disposed on the same layer as the second portion 120, and the source 620 and drain 630 are both disposed on the same layer as the first portion 110. For example, the pixel electrode 300, gate 610, and second portion 120 are disposed on the same layer, and the common electrode 400, source 620, drain 630, and first portion 110 are disposed on the same layer. The pixel electrode 300 is disposed on the top layer, allowing it to directly contact the medium used for display, resulting in better driving performance.

[0114] Figure 19 is a planar schematic diagram of an electronic paper display substrate. Figure 20 is a schematic diagram of the film layer structure of an electronic paper display substrate. For example, Figure 20 only schematically shows a schematic diagram of the film layer stacking order. Figure 20 can be a partial cross-sectional schematic diagram of the electronic paper display substrate shown in Figure 19, or it can be a schematic diagram of the film layer structure in other electronic paper display substrates. This disclosure does not limit it in this way.

[0115] Referring to Figure 19, the electronic paper display substrate can be a backplane employing electrophoretic display (EPD) technology. For example, the electronic paper display substrate includes an active area (AA) and a peripheral area 010 located around the active area. The active area AA displays the image, and the peripheral area 010 is equipped with ITO (Indium Tin Oxide). The peripheral area 010 can display corresponding colors as needed. The short ring 020 is a long metal line used to collect electrostatic discharge (ESD). The gate line 030 is a lead for transmitting gate scan signals, used to control the switching of the thin-film transistors (TFTs) of the pixels. The data line 040 is a lead for transmitting data signals (source). The panel break detection structure 050 can receive the panel break test signal output by the IC, used to detect whether the edge of the panel is damaged. The common electrode line Vcom is the trace connecting the Vcom signal on the backplane. It is generally composed of multiple branches and is connected to the FPC (or IC), for example. The ESD circuit consists of multiple TFTs and can open to conduct ESD to the short-circuit ring when encountering a large charge. Silver paste (Ag) dots 060 are used to connect the Vcom signal on the backplane to the ITO in the periphery of the paper film on the electronic paper display substrate. For example, silver paste dots 060 are silver paste via connection points. The IC is a driver integrated circuit, bonded to the backplane, providing drive for the display of the electronic paper display device. The FPC is a flexible printed circuit board, also known as a flexible board.

[0116] Referring to Figure 20, the electronic paper display substrate is provided with a glass substrate 001, a first insulating layer 002, a second insulating layer 003, and an ITO layer 004 stacked sequentially. The film layer 005 containing the gate lines is disposed on the substrate 001, and the film layer 006 containing the data lines is disposed on the side of the first insulating layer 002 away from the substrate 001. The film layer containing the common electrode lines is located on the side of the substrate away from the gate lines (not shown in the figure).

[0117] At least one embodiment of this disclosure provides a display device including an electronic paper display substrate of any of the above embodiments. Since the electronic paper display substrate according to the embodiments of this disclosure is used in the above-described display device, it also has corresponding beneficial technical effects, which will not be elaborated further here. For example, the display device can be an electronic paper display device. For example, the display device can be a wearable device, mobile phone, electronic price tag, electronic table sign, electronic door sign, billboard, notice board, electronic paper reader, and other display products; this disclosure does not limit these applications.

[0118] The following points need to be explained:

[0119] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0120] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0121] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. An electronic paper display substrate, comprising: Substrate; Multiple first signal lines and multiple second signal lines are disposed on the substrate. The multiple first signal lines extend along a first direction and are arranged along a second direction, and the multiple second signal lines extend along the second direction and are arranged along the first direction. The first direction and the second direction intersect, and the multiple first signal lines and the multiple second signal lines intersect to define multiple pixel areas. Pixel electrodes and a common electrode are disposed in the pixel region; An insulating layer is disposed between the pixel electrode and the common electrode; The first signal line includes a first part and a second part. The first part is disposed on the same layer as the common electrode, and the second part is disposed on the same layer as the pixel electrode. The first part is electrically connected to the second part through a via in the insulating layer. The orthographic projection of the first part on the substrate is a first projection, the orthographic projection of the second part on the substrate is a second projection, and the orthographic projection of the pixel electrode on the substrate is a third projection; The first distance between the first projection and the third projection in the second direction is less than the second distance between the second projection and the third projection in the second direction.

2. The electronic paper display substrate according to claim 1, wherein, The first projection and the third projection do not overlap.

3. The electronic paper display substrate according to claim 1 or 2, wherein, The first spacing is 0.

4. The electronic paper display substrate according to any one of claims 1-3, wherein, At least one first signal line includes a plurality of first portions and a plurality of second portions, and the plurality of first portions and the plurality of second portions are alternately arranged in the first direction.

5. The electronic paper display substrate according to any one of claims 1-4, wherein, The pixel electrode includes a main body portion and a protruding portion that are connected to each other; At least a portion of the orthographic projection of the protruding portion on the substrate lies between the orthographic projection of the main body portion on the substrate and the first projection.

6. The electronic paper display substrate according to claim 5, wherein, The first signal line is a data line, and the second signal line is a gate line; The electronic paper display substrate also includes a transistor disposed on the substrate, wherein the gate of the transistor is connected to the gate line, the source of the transistor is connected to the data line, and the drain of the transistor is connected to the pixel electrode. The transistor is located on one side of the pixel electrode in the first direction, and the protrusion includes a first protrusion connected to at least one side of the main body portion along the second direction.

7. The electronic paper display substrate according to claim 6, wherein, The protruding portion further includes a second protruding portion connected to at least one side of the main body portion along the first direction, wherein the orthographic projection of the second protruding portion on the substrate does not overlap with the orthographic projection of the gate line on the substrate, and the orthographic projection of the second protruding portion on the substrate does not overlap with the orthographic projection of the transistor on the substrate.

8. The electronic paper display substrate according to claim 7, wherein, The grid line includes a grid body portion and a grid connection portion that are connected to each other; The gate body includes the gate, the width of the gate connection portion in the first direction is smaller than the width of the gate body portion in the first direction, and the gate connection portion overlaps with the orthographic projection of the second protrusion portion on a straight line extending along the second direction.

9. The electronic paper display substrate according to claim 5, wherein, The first signal line is a gate line, and the second signal line is a data line; The electronic paper display substrate also includes a transistor disposed on the substrate, wherein the gate of the transistor is connected to the gate line, the source of the transistor is connected to the data line, and the drain of the transistor is connected to the pixel electrode. The transistor is located on one side of the pixel electrode in the second direction, and at least a portion of the protrusion is connected to at least one side of the main body portion along the second direction.

10. The electronic paper display substrate according to any one of claims 1-9, wherein, The first part includes a first main body and a first connecting part connected to each other, and the second part includes a second main body and a second connecting part connected to each other; The first adapter is electrically connected to the second adapter through the via; The orthographic projection of the first adapter portion on the substrate overlaps with the orthographic projection of the second adapter portion on the substrate.

11. The electronic paper display substrate according to any one of claims 1-5, wherein, The first signal line is a data line, and the second signal line is a gate line; the electronic paper display substrate also includes a transistor disposed on the substrate, the gate of the transistor is connected to the gate line, the source of the transistor is connected to the data line, and the drain of the transistor is connected to the pixel electrode. The gate is disposed in the same layer as the first part, and the source and drain are both disposed in the same layer as the second part; The transistor further includes an active layer, the gate is located on the side of the active layer away from the substrate, and a gate insulating layer is disposed between the active layer and the gate.

12. The electronic paper display substrate according to any one of claims 1-5, wherein, The first signal line is a data line, and the second signal line is a gate line; the electronic paper display substrate also includes a transistor disposed on the substrate, the gate of the transistor is connected to the gate line, the source of the transistor is connected to the data line, and the drain of the transistor is connected to the pixel electrode. The gate is disposed in the same layer as the first part, and the source and drain are both disposed in the same layer as the second part; The transistor further includes an active layer and a gate insulating layer. The active layer is located on the side of the gate away from the substrate, and a gate insulating layer is disposed between the active layer and the gate.

13. The electronic paper display substrate according to claim 11 or 12, further comprising a common connection line extending along the second direction, the common connection line connecting a common electrode of two adjacent pixel regions; The pixel electrode has a first edge and a second edge disposed opposite to each other in the first direction, the first edge being located on the side of the second edge away from the transistor electrically connected to the pixel electrode; The maximum distance between the edge of the orthographic projection of the common connection line on the substrate and the orthographic projection of the first edge on the substrate is the first distance, and the minimum distance between the edge of the orthographic projection of the common connection line on the substrate and the orthographic projection of the second edge on the substrate is the second distance, wherein the first distance is less than the second distance.

14. The electronic paper display substrate according to claim 13, wherein, The pixel electrode includes a main body portion and a protruding portion connected to at least one side of the main body portion; The ratio of the maximum dimension of the first part in the first direction to the maximum dimension of the main body part in the first direction is 0.5 to 1.

15. The electronic paper display substrate according to any one of claims 1-5, wherein, The first signal line is a gate line, and the second signal line is a data line; The electronic paper display substrate also includes a transistor disposed on the substrate, wherein the gate of the transistor is connected to the gate line, the source of the transistor is connected to the data line, and the drain of the transistor is connected to the pixel electrode. The gate is disposed on the same layer as the second part, and the source and the drain are disposed on the same layer as the first part.

16. The electronic paper display substrate according to claim 15, further comprising a common connection line extending along the second direction, the common connection line connecting a common electrode of two adjacent pixel regions; The first projection is located on the side where the orthogonal projection of the common connection line on the substrate is away from the orthogonal projection of the source of the transistor on the substrate.

17. A display device comprising an electronic paper display substrate according to any one of claims 1-16.

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