Display panel, display module, and display apparatus

Abstract

A display panel provided with a display area, wherein the display area comprises an aperture area, an isolation area, and a pixel area. The display panel comprises a substrate, a first isolation structure, a cathode layer, and a conductive block. The first isolation structure is disposed on the substrate and located in the isolation area; the first isolation structure surrounds at least part of the aperture area. The cathode layer comprises a first sub-portion and a second sub-portion separated from one another, wherein the first sub-portion and the second sub-portion are located in the isolation area, the first sub-portion is located on a side of the first isolation structure away from the substrate, and the second sub-portion is located on a side of the first isolation structure away from or close to the aperture area; and the first sub-portion and the second sub-portion are electrically connected by means of the first isolation structure. The conductive block is disposed between the substrate and the first isolation structure, and is located in the isolation area; a boundary of the conductive block close to the aperture area is flush with a boundary of the aperture area; a voltage difference between the conductive block and the first sub-portion and the second sub-portion is less than or equal to a driving voltage of a first ion, and the first ion chemically reacts with an inorganic material.

Description

Display panel, display module and display device

[0001] This application claims priority to Chinese Patent Application No. 202410823597.3, filed on June 24, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to a display panel, a display module and a display device. BACKGROUND

[0003] With the development of display technology, display devices (such as mobile phones, notebook computers or tablet computers, etc.) are increasingly applied to people's lives. Organic light-emitting diode (OLED) display devices have the advantages of active light-emitting, wide viewing angle, high contrast, fast response speed, low power consumption, ultra-thin, etc., and therefore are widely concerned. SUMMARY

[0004] In one aspect, a display panel is provided. The display panel has a display area; the display area includes an aperture area, an isolation area and a pixel area; the isolation area is located between the aperture area and the pixel area. The display panel includes a substrate, a first isolation structure, a cathode layer and a conductive block. The first isolation structure is disposed on the substrate and located in the isolation area; the first isolation structure surrounds at least part of the aperture area. The cathode layer covers the isolation area; the cathode layer includes a first sub-part and a second sub-part separated by the first isolation structure, the first sub-part and the second sub-part are located in the isolation area, the first sub-part is located on a side of the first isolation structure away from the substrate, and the second sub-part is located on a side of the first isolation structure away from or close to the aperture area; and the first sub-part and the second sub-part are electrically connected through the first isolation structure. The conductive block is disposed between the substrate and the first isolation structure and located in the isolation area; the boundary of the conductive block close to the aperture area is flush with the boundary of the aperture area; the voltage difference between the conductive block and the first sub-part and the second sub-part is less than or equal to the driving voltage of the first ion; wherein the first ion chemically reacts with inorganic material.

[0005] In some embodiments, the conductive block and the first isolation structure are electrically insulated. The display panel further includes a first connection line. The first connection line is connected with the conductive block and connected with a first voltage terminal.

[0006] In some embodiments, the voltage on the cathode layer is the same as the voltage received at the first voltage terminal.

[0007] In some embodiments, the conductive block is connected with the first isolation structure or the second sub-portion.

[0008] In some embodiments, the display panel further comprises a first insulating stack. The first insulating stack is located in the pixel region and extends to the isolation region. The first insulating stack is located between the first isolation structure and the conductive block. The first insulating stack has a first via hole penetrating through the first insulating stack. The first isolation structure extends into the first via hole and is connected with the conductive block.

[0009] In some embodiments, the display panel further comprises a first connection line. The first connection line is connected with the conductive block and connected with a first voltage terminal. The conductive block is configured to have a voltage difference between the conductive block and the support layer that is less than or equal to a driving voltage of the first ion.

[0010] In some embodiments, the first voltage terminal is ground.

[0011] In some embodiments, the display panel further comprises a pixel circuit stack and a light emitting device layer stack. The pixel circuit stack is disposed between the substrate and the cathode layer. The pixel circuit stack comprises a plurality of first pixel circuits and a plurality of redundant pixel circuits. The plurality of first pixel circuits are located in the pixel region. The plurality of redundant pixel circuits are located in the isolation region. The plurality of redundant pixel circuits are adjacent to the first pixel circuits located in the pixel region and close to the edge of the aperture region. The light emitting device layer stack is located on a side of the pixel circuit stack away from the substrate. The light emitting device layer stack comprises a plurality of light emitting devices. The first pixel circuits are electrically connected with the light emitting devices. The redundant pixel circuits are electrically insulated from the light emitting devices.

[0012] In some embodiments, the redundant pixel circuit comprises a second transistor. The pixel circuit stack further comprises an active layer, a first source-drain conductive layer, and at least one third insulating layer. The active layer comprises an active portion of the second transistor. The first source-drain conductive layer is located between the active layer and the cathode layer. The first source-drain conductive layer comprises a first electrode of the second transistor. The first connection line and the first electrode of the second transistor are disposed in the same layer and connected with the first electrode of the second transistor. The at least one third insulating layer is disposed between the first electrode of the second transistor and the conductive block, located in the pixel region and extending to the isolation region. The at least one third insulating layer is provided with a second via hole penetrating through the at least one third insulating layer. The first electrode of the second transistor extends into the second via hole and is connected with the conductive block.

[0013] In some embodiments, the redundant pixel circuit includes a second transistor, and the pixel circuit stack further includes an active layer, a first source-drain conductive layer, at least one third insulating layer, and at least one fourth insulating layer. The active layer includes an active portion of the second transistor; the first source-drain conductive layer is between the active layer and the cathode layer; the first source-drain conductive layer includes a first electrode of the second transistor; the at least one third insulating layer is disposed between the first source-drain conductive layer and the conductive block, is located in the pixel area, and extends to the isolation area; the at least one third insulating layer is between the conductive block and the first electrode of the second transistor; the at least one third insulating layer is provided with a second via hole penetrating the at least one third insulating layer; the first electrode of the second transistor extends into the second via hole and is connected with the conductive block. The at least one fourth insulating layer is disposed between the first source-drain conductive layer and the cathode layer, is located in the pixel area, and extends to the isolation area; the at least one fourth insulating layer is provided with a third via hole; wherein the first connection line is disposed between the at least one fourth insulating layer and the cathode layer, and the first connection line extends into the third via hole and is connected with the first electrode of the second transistor.

[0014] In some embodiments, the display panel further has a fan-out area, which is disposed on one side of the display area along a second direction; the display area further includes a central area and an edge area, which is disposed on at least one side of the central area along a first direction; wherein the first direction intersects the second direction. The display panel further includes a plurality of data lines, a plurality of first transfer lines, and a plurality of second transfer lines. The plurality of data lines are disposed on the substrate; the plurality of data lines are arranged at intervals along the first direction; the plurality of data lines include a first data line; the first data line is disposed in the edge area and extends along the second direction; the plurality of first transfer lines are disposed in the same layer as the plurality of data lines and are located in the central area; the first transfer line extends along the second direction and is connected with the fan-out area; the plurality of second transfer lines are disposed between the plurality of first transfer lines and the first source-drain conductive layer, or are disposed between the plurality of first transfer lines and the cathode layer; the second transfer line extends along the first direction, and one second transfer line is connected with one first data line and one first transfer line; wherein the first connection line is disposed in the same layer as the first transfer line and / or the second transfer line.

[0015] In some embodiments, the first connection line includes a plurality of first sub-lines and a plurality of second sub-lines. The plurality of first sub-lines extend along the second direction and are spaced apart along the first direction; the first sub-lines and the first adapter lines are arranged in the same layer; the plurality of second sub-lines extend along the first direction and are spaced apart along the second direction; the second sub-lines and the second adapter lines are arranged in the same layer; the plurality of second sub-lines and the plurality of first sub-lines are connected to form a mesh structure.

[0016] In some embodiments, the first connection line and the conductive block are arranged in the same layer.

[0017] In some embodiments, the display panel includes a plurality of first isolation structures; along a direction from the isolation region to the aperture region, the plurality of first isolation structures are spaced apart. The display panel further includes a pad. The pad is located between the substrate and the cathode layer; the pad is partially located between two adjacent first isolation structures, partially located on a side of a first isolation structure away from the substrate, and covers part of an end surface of the first isolation structure away from the substrate; a surface of the pad away from the substrate protrudes in a direction away from the substrate. The cathode layer further includes a third sub-portion, which is located on a side of the pad away from the substrate and connected with an adjacent first sub-portion; a minimum distance between a surface of the third sub-portion away from the substrate and the pad is smaller than a minimum distance between a surface of the first sub-portion away from the substrate and the first isolation structure, and smaller than a minimum distance between a surface of the second sub-portion away from the substrate and the substrate.

[0018] In some embodiments, the display panel further includes a plurality of first conductive layers arranged in layers. The plurality of first conductive layers arranged in layers are arranged between the first isolation structure and the substrate; the conductive block is located in the first conductive layer closest to the substrate among the plurality of first conductive layers.

[0019] In some embodiments, the display panel further includes an inorganic encapsulation layer, a plurality of first conductive layers arranged in layers, and a second insulating stack. The inorganic encapsulation layer is located in the display region and extends to the isolation region; the inorganic encapsulation layer is located on a side of the cathode layer away from the substrate and covers the cathode layer; the plurality of first conductive layers arranged in layers are arranged between the first isolation structure and the substrate; the conductive block is located in one of the first conductive layers; the second insulating stack is located in the pixel region and extends to the isolation region, and is located between the first isolation structure and the first conductive layer including the conductive block; along a direction perpendicular to the substrate, a thickness of the second insulating stack is greater than a thickness of the inorganic encapsulation layer.

[0020] In some embodiments, the display panel further comprises an active layer and a light shielding layer. The active layer is located in the pixel region and between the substrate and the cathode layer; the active layer comprises a channel portion; the light shielding layer is located between the active layer and the substrate; the light shielding layer comprises a plurality of light shielding blocks, and a projection of the light shielding blocks on the substrate at least partially overlaps with a projection of the channel portion on the substrate.

[0021] In another aspect, a display module is provided. The display module comprises a support layer, a display panel as described in any of the above embodiments, and a polarizer. The support layer is grounded; the display panel has a display side and a non-display side arranged oppositely, the display side is farther away from the support layer than the non-display side; the polarizer is located on a side of the display panel away from the support layer; and a material of the polarizer comprises a first ion.

[0022] In yet another aspect, a display device is provided, comprising a display panel as described in any of the above embodiments, or a display module as described in any of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings described in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0024] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0025] FIG. 2 is another structural diagram of a display device according to some embodiments;

[0026] FIG. 3 is a cross-sectional view of a display device according to some embodiments;

[0027] FIG. 4 is a structural diagram of a display panel according to some embodiments;

[0028] FIG. 5 is a cross-sectional view along the section line C-C in FIG. 4;

[0029] FIG. 6 is another cross-sectional view along the section line C-C in FIG. 4;

[0030] FIG. 7 is a cross-sectional view along the section line D-D in FIG. 1;

[0031] FIG. 8 is a partial enlarged view of E in FIG. 7;

[0032] FIG. 9 is another cross-sectional view along the section line D-D in FIG. 1;

[0033] Fig. 10 is a partial enlarged view of F in Fig. 9;

[0034] Fig. 11 is another sectional view along the section line D-D in Fig. 1;

[0035] Fig. 12 is a partial enlarged view of G in Fig. 11;

[0036] Fig. 13 is another sectional view along the section line D-D in Fig. 1;

[0037] Fig. 14 is a partial enlarged view of H in Fig. 13;

[0038] Fig. 15 is a partial enlarged view of I in Fig. 4;

[0039] Fig. 16 is a partial enlarged view of J in Fig. 4;

[0040] Fig. 17 is a sectional view along the section line K-K in Fig. 16;

[0041] Fig. 18 is another sectional view along the section line K-K in Fig. 16;

[0042] Fig. 19 is another sectional view along the section line K-K in Fig. 16;

[0043] Fig. 20 is another sectional view along the section line K-K in Fig. 16;

[0044] Fig. 21 is a partial enlarged view of L in Fig. 4;

[0045] Fig. 22 is a structure diagram of a light shielding block and a conductive block arranged in the same layer according to some embodiments. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art are within the scope of protection of the present disclosure.

[0047] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise," and variations thereof (e.g., "comprises" and "comprising"), will be construed to be inclusive in a manner consistent with the term's plain meaning, namely, "including but not limited to." In describing the description, the terms "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example" or "some examples," and the like, mean that a particular feature, structure, material, or characteristic is included in at least one embodiment or example of the disclosure, but that it can not be included in other embodiments or examples. The illustrative appearance of the foregoing terms in various places in the description are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0048] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description and should not be construed as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0049] In describing some embodiments, "coupled" and "connected," and variations thereof, can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "communicatively coupled" can also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0050] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0051] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0052] As used herein, the term "if' is, optionally, interpreted as meaning "when" or "while" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [stated condition or event] is detected," is, optionally, interpreted as meaning "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0053] The use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude additional devices or steps not specifically recited.

[0054] Additionally, the use of "based on" means open and inclusive, as the process, step, calculation, or other action that is based on one or more stated conditions or values can in fact be based on additional conditions or values beyond those stated.

[0055] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0056] As used herein, "parallel," "perpendicular," "equal" includes the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can be within an acceptable deviation range of, for example, 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also be within an acceptable deviation range of, for example, 5°. "Equal" includes absolute equality and near equality, where near equality can be within an acceptable deviation range of, for example, less than or equal to 5% of either of the two quantities being compared.

[0057] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0058] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic and are not intended to be ascribed to planar or cross-sectional geometries of the examples. In other words, the exemplary embodiments to be described are not intended to be bound by the illustrative representations that are being provided by way of example only. In the drawings, the thickness of layers and regions are exaggerated for clarity, and the thickness of layers, regions, and / or areas can be irregular over the drawings' surface. Accordingly, the exemplary embodiments should not be construed as being limited to the shapes illustrated in the drawings, which are schematically represented. For example, the etching region illustrated as a rectangle will typically have a curved shape. The shapes of the regions illustrated in the drawings are therefore intended to exemplify the regions of the devices, and are not intended to limit the scope of the exemplary embodiments to the precise shapes illustrated. The drawings are intended to be more conceptually illustrative than strictly precise depictions of the regions and devices.

[0059] Some embodiments of the present disclosure provide a display device 1000, as shown in FIG. 1, which can be a notebook computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a car central screen, or any product or component having a display function.

[0060] In some examples, as shown in FIG. 1, the display device 1000 can be a portable display product. For example, the display device 1000 can be a mobile phone as shown in FIG. 1.

[0061] In yet other examples, as shown in FIG. 2, the display device 1000 can be a wearable device. For example, the display device 1000 can be a watch as shown in FIG. 2.

[0062] The display device 1000 described above can be a liquid crystal display (LCD), an organic light emitting display device, a quantum dot light emitting display (QLED) device, a micro light emitting diode (Micro LED) device, a mini light emitting diode (Mini LED) device, or an active-matrix organic light emitting diode (AMOLED) display device.

[0063] It should be noted that the Micro LED refers to an LED with a size (e.g., length) less than 50 μm, and the Mini LED refers to an LED with a size (e.g., length) of 50 μm to 200 μm.

[0064] In the following, some embodiments of the present disclosure will be illustratively described taking an OLED display device as an example, but the embodiments of the present disclosure are not limited thereto, and other display devices can also be considered as long as the same technical idea is applied.

[0065] In some embodiments, as shown in FIG. 3, the display device 1000 includes a display module 100, and the display module 100 includes a support layer 10, a display panel 20, and a polarizer 30.

[0066] The support layer 10 is configured to support the display panel 20. The material of the support layer 10 can include at least one of stainless steel, aluminum, or copper. In addition, the support layer 10 is also configured to be grounded, which can reduce the risk of the display panel 20 being affected by external electromagnetic interference, and can also reduce the risk of the user being electrocuted due to the leakage of the display panel 20, so as to protect the safety of the user.

[0067] As shown in FIG. 3, the display panel 20 has a display side 20A and a non-display side 20B opposite to each other. It should be noted that the display side 20A refers to the side of the display panel 20 displaying an image (the upper side of the display panel 20 in FIG. 3), and the non-display side 20B refers to the other side opposite to the display side 20A (the lower side of the display panel 20 in FIG. 3). Among them, the display side 20A is farther away from the support layer 10 than the non-display side 20B.

[0068] As shown in FIG. 4, the display panel 20 has a display area AA and a peripheral area BB disposed on at least one side of the display area AA. In FIG. 4, the peripheral area BB is disposed around the display area AA as an example. The peripheral area BB is a region that does not display an image, and the peripheral area BB is configured to dispose a display pixel circuit, such as a scanning pixel circuit and a source pixel circuit.

[0069] As shown in FIG. 3, the polarizer 30 is located on the side of the display panel 20 away from the support layer 10. The polarizer 30 is disposed on the side of the display panel 20 away from the support layer 10, and the polarizer 30 has a normal projection on the plane of the display panel 20 covering at least the display area AA of the display panel 20, so as to reduce the reflection of ambient light by the display panel 20. Among them, the material of the polarizer 30 includes first ions, and the first ions can chemically react with inorganic materials. For example, the first ions include potassium ions.

[0070] Exemplarily, the polarizer 30 includes a circular polarizer.

[0071] It can be understood that, as shown in FIG. 3, the display module 100 further comprises a first adhesive layer 40, which is located between the display panel 20 and the polarizer 30, and is used to bond the display panel 20 and the polarizer 30. The material of the first adhesive layer 40 includes an optical clear adhesive (OCA for short) or a pressure sensitive adhesive (PSA for short) or other adhesive materials with high light transmittance (for example, the light transmittance is greater than or equal to 90%), for example, the material of the first adhesive layer 40 includes an optical clear adhesive.

[0072] On the basis of the above-mentioned embodiments, as shown in FIG. 3, the display module 100 further comprises a cover plate 50, which is located on the side of the polarizer 30 away from the display panel 20. The material of the cover plate 50 includes glass, a colorless polyimide (CPI for short) or polyethylene terephthalate (PET for short).

[0073] In this case, when the display module 100 collides with an object or the display module 100 collides with the ground, the object or the ground will first collide with the cover plate 50 and will not collide with the polarizer 30, so that the cover plate 50 can reduce the risk that the polarizer 30 is damaged due to the direct collision of the object outside the display module 100 with the polarizer 30.

[0074] In some embodiments, as shown in FIG. 1, the display device 1000 further comprises a functional device 200, which can be a camera, an infrared sensor, a proximity sensor, an eye tracking module, a face recognition module or the like. Exemplarily, as shown in FIG. 1, the functional device 200 is a camera.

[0075] As shown in FIG. 4, the display panel 20 can be provided with a mounting hole H, and the functional device 200 can be mounted at the mounting hole H to avoid that the display panel 20 blocks the light collection of the functional device 200.

[0076] Exemplarily, the mounting hole H can be cut by a knife wheel or laser.

[0077] In some embodiments, as shown in FIG. 4, the display area AA comprises an opening area AA1, a separation area AA2 and a pixel area AA3. The separation area AA2 is arranged between the opening area AA1 and the pixel area AA3. Among them, the pixel area AA3 is used for displaying a picture, the opening area AA1 is used for arranging the mounting hole H, and the separation area AA2 is used for blocking the invasion of water and oxygen from the opening area AA1 into the pixel area AA3.

[0078] In some embodiments, as shown in FIGS. 4, 5 and 6, the display panel 20 includes a substrate 21 and a plurality of sub-pixels 22.

[0079] As shown in FIGS. 5 and 6, the substrate 21 can be a flexible substrate 21 or a rigid substrate 21. The material used by the substrate 21 can include a polymer resin or glass. Exemplarily, the substrate 21 can be flexible, and the material used by the substrate 21 includes one of a polymer resin such as Polyethersulfone (PES), Polyarylate (PAR), Polyetherimide (PEI), Polyethylene Naphthalate Two Formic Acid Glycol Ester (PEN), Polyethylene Terephthalate (PET), Polyphenyl Sulfide Granula (PPS), Polyimide (PI), Polycarbonate (PC) and Cellulose Acetate Propionate (CAP). Exemplarily, the substrate 21 can be rigid, and the material of the substrate 21 includes glass containing SiO2 as a main component.

[0080] As shown in FIG. 4, the plurality of sub-pixels 22 are arranged on the substrate 21 and located in the pixel region AA3.

[0081] Exemplarily, as shown in FIG. 4, the plurality of sub-pixels 22 can be arranged in multiple rows and multiple columns, each row of sub-pixels 22 includes at least two sub-pixels 22 arranged along a first direction X, and each column of sub-pixels 22 includes at least two sub-pixels 22 arranged along a second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular.

[0082] In some examples, the plurality of sub-pixels 22 can include a first sub-pixel with a first color, a second sub-pixel with a second color, and a third sub-pixel with a third color. The first color, the second color and the third color are three primary colors. For example, the first color is red, the second color is blue, and the third color is green, which are not limited in the embodiments of the present disclosure.

[0083] In some examples, the plurality of sub-pixels 22 includes a first sub-pixel emitting a first color, a second sub-pixel emitting a second color, a third sub-pixel emitting a third color, and a fourth sub-pixel emitting a fourth color. The first color, the second color, and the third color are three primary colors, and the fourth color is white. For example, the first color is red, the second color is blue, and the third color is green.

[0084] It can be understood that, as shown in FIGS. 5 and 6, the sub-pixel 22 includes the first pixel circuit 221 and the light emitting device 222.

[0085] In some examples, as shown in FIGS. 5 and 6, the display panel 20 further includes a pixel circuit stack 23 and a light emitting device stack 24 on the substrate 21 in a direction perpendicular to and away from the substrate 21.

[0086] The pixel circuit stack 23 includes a plurality of pixel circuits 231, and each pixel circuit 231 includes a plurality of transistors 2311 and a storage capacitor 2312 (Capacitor, abbreviated as C). The plurality of pixel circuits 231 includes the first pixel circuit 221.

[0087] The transistors 2311 used in the circuit provided by the embodiments of the present disclosure can be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the embodiments of the present disclosure are all described by taking thin film transistors as examples.

[0088] For example, the transistors 2311 are oxide thin film transistors, and the carrier mobility of the oxide thin film transistors is relatively high.

[0089] Alternatively, for example, the transistors 2311 are low-temperature polysilicon thin film transistors, and the low-temperature polysilicon thin film transistors have high mobility and fast charging.

[0090] In some examples, as shown in FIG. 5, the plurality of transistors 2311 includes low-temperature polysilicon thin film transistors and oxide thin film transistors. In this way, the low-temperature polysilicon transistors and the oxide transistors can be integrated on one display panel 20, which can reduce the power consumption of the display panel 20 and improve the display quality of the display panel 20.

[0091] As shown in FIGS. 5 and 6, the transistor 2311 includes an active part 23111, a source 23112, a drain 23113, and a gate 23114, and the source 23112 and the drain 23113 are in contact with the active part 23111. The storage capacitor 2312 includes two oppositely arranged plates.

[0092] It should be noted that the source 23112 and the drain 23113 can be interchanged, i.e., 23112 in FIGS. 5 and 6 represents the drain, and 23113 represents the source.

[0093] The structure of the pixel circuit 231 can include various structures, which can be selected according to actual needs. For example, the structure of the pixel circuit 231 can include a "2T1C", "3T1C", "6T1C", "7T1C", "6T2C", or "7T2C" structure. Among them, "T" represents the transistor 2311, the number before "T" represents the number of transistors 2311, and "C" represents the storage capacitor 2312, and the number before "C" represents the number of storage capacitors 2312.

[0094] In some examples, the plurality of transistors in the pixel circuit 231 can include P-type transistors and N-type transistors. In other examples, the plurality of transistors in the pixel circuit 231 can all be P-type transistors or can all be N-type transistors, which can simplify the process flow, reduce the process difficulty of the display panel 20, and improve the yield of the product.

[0095] In some embodiments, along a direction perpendicular to the substrate 21 and close to the substrate 21, as shown in FIGS. 5 and 6, the light emitting device stack 24 includes an anode layer 241, a light emitting functional layer 242, and a cathode layer 243 which are stacked.

[0096] As shown in FIGS. 5 and 6, the anode layer 241 includes a plurality of anodes 2411, and the cathode layer 243 includes a plurality of cathodes 2431. One anode 2411 and one cathode 2431 are arranged opposite to each other. The anode 2411 and the cathode 2431 arranged opposite to each other and the light emitting functional layer 242 between the anode 2411 and the cathode 2431 form a light emitting device 222.

[0097] The anode 2411 can be electrically connected to the source 23112 or the drain 23113 of the plurality of transistors 2311 as a driving transistor, for example, as shown in FIGS. 5 and 6, the anode 2411 is electrically connected to the drain 23113 of the transistor 2311. In this way, the pixel circuit 231 can drive the corresponding light emitting device 222 to emit light.

[0098] The light-emitting functional layer 242 can include only a light-emitting layer, or can further include at least one of an electron transporting layer (ETL), an electron injection layer (EIL), a hole blocking layer (HBL), a hole transporting layer (HTL), a hole injection layer (HIL), and an electron blocking layer (EBL) in addition to the light-emitting layer.

[0099] In some embodiments, as shown in FIGS. 5 and 6, the display panel 20 further includes an encapsulation layer 25. The encapsulation layer 25 is disposed in the pixel area AA3 and extends to the isolation area AA2. The encapsulation layer 25 is disposed on a side of the light-emitting device stack 24 away from the substrate 21, and the encapsulation layer 25 is used to encapsulate the light-emitting device 222 and improve the service life of the light-emitting device 222. The encapsulation layer 25 can be an encapsulation film or an encapsulation substrate, and the specific form of the encapsulation layer 25 is not limited in the embodiments of the present disclosure.

[0100] For example, the encapsulation layer 25 can include one encapsulation film, or two or more encapsulation films stacked together. For example, as shown in FIGS. 3 and 4, the encapsulation layer 25 includes a first inorganic encapsulation layer 251, a first organic encapsulation layer 252, and a second inorganic encapsulation layer 253 stacked together in a direction perpendicular to and away from the substrate 21. The first inorganic encapsulation layer 251 and the second inorganic encapsulation layer 253 can be made of any one or more of silicon nitride, silicon oxynitride, or silicon oxide. The first organic encapsulation layer 252 can be made of a polymer resin, such as polyimide.

[0101] Hereinafter, some embodiments of the present disclosure will be described by way of example with the encapsulation layer including the first inorganic encapsulation layer 251, the first organic encapsulation layer 252, and the second inorganic encapsulation layer 253, but the embodiments of the present disclosure are not limited thereto, and other encapsulation layers can also be considered as long as the same technical idea is applied.

[0102] It can be understood that the cathode voltage of all the light-emitting devices 222 is the same. Therefore, the cathode layer 243 can be an integral layer structure, i.e., the cathode layer 243 is located in the pixel area AA3 and extends to the isolation area AA2. In this way, the preparation difficulty of the cathode layer 243 can be reduced to reduce the preparation cost of the display panel 20.

[0103] In some embodiments, as shown in FIG. 4, the display panel 20 further comprises a first isolation structure 26 disposed in the isolation area AA2. As shown in FIG. 7, FIG. 8, FIG. 9 and FIG. 10, the first isolation structure 26 is located between the substrate 21 and the cathode layer 243. The first isolation structure 26 surrounds at least part of the aperture area AA1, which is taken as an example in FIG. 4.

[0104] As shown in FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG. 13 and FIG. 14, the cathode layer 243 located in the isolation area AA2 comprises a first sub-part 2432 and a second sub-part 2433 separated from each other, the first sub-part 2432 is disposed on the side of the first isolation structure 26 away from the substrate 21, and the second sub-part 2433 is disposed on the side of the first isolation structure 26 away from or close to the aperture area AA1, that is, the cathode layer 243 is disconnected at the first isolation structure 26, which can reduce the risk of water and oxygen invading the pixel area AA3 from the aperture area AA1 through the cathode layer 243, thereby improving the problem of Growing Dark Spot In Hole (GDSH) of the display panel 20.

[0105] The specific structure of the first isolation structure 26 is illustrated below.

[0106] In some embodiments, as shown in FIG. 7, FIG. 8, FIG. 9 and FIG. 10, along the direction perpendicular to the substrate 21 and away from the substrate 21, the first isolation structure 26 is laminated with a first isolation part 261, a second isolation part 262 and a third isolation part 263, along the direction of the isolation area AA2 pointing to the aperture area AA1, both ends of the first isolation part 261 exceed the second isolation part 262, both ends of the third isolation part 263 exceed the second isolation part 262 and are flush with both ends of the first isolation part 261, and the materials of the first isolation part 261, the second isolation part 262 and the third isolation part 263 all comprise metal. The materials of the first isolation part 261, the second isolation part 262 and the third isolation part 263 all comprise metal. The first sub-part 2432 is located on the side of the third isolation part 263 away from the substrate 21, the second sub-part 2433 is located on the side of the first isolation part 261 away from or close to the aperture area AA1, and is in contact with the first isolation part 261.

[0107] In yet some embodiments, as shown in FIG. 11, FIG. 12, FIG. 13 and FIG. 14, along the direction perpendicular to the substrate 21 and away from the substrate 21, the first isolation structure 26 is laminated with a first isolation part 261 and a second isolation part 262, along the direction of the isolation area AA2 pointing to the aperture area AA1, both ends of the second isolation part 262 exceed the first isolation part 261.

[0108] In some examples, as shown in FIGS. 11 and 12, the material of the first isolation portion 261 includes an insulating material, and the material of the second isolation portion 262 includes a metal material. The first sub-portion 2432 is located on the side of the second isolation portion 262 away from the substrate 21, the second sub-portion 2433 is located on the side of the first isolation portion 261 away from or close to the aperture region AA1, and is located on the side of the second isolation portion 262 close to the substrate 21, the second sub-portion 2433 covers the sidewall of the first isolation portion 261, and the second sub-portion 2433 and the surface of the second isolation portion 262 close to the substrate 21 are in contact.

[0109] Exemplarily, the display panel 20 further includes a third insulating stack 1. The third insulating stack 1 is arranged between the substrate 21 and the cathode layer 243, and the surface of the third insulating stack 1 away from the substrate 21 has a plurality of isolation grooves 101, the sidewall of the isolation groove 101 is inclined, the plurality of isolation grooves 101 are arranged in the isolation region AA2, and are arranged along the direction of the isolation region AA2 pointing to the aperture region AA1, the plurality of isolation grooves 101 are arranged at intervals, and the isolation groove 101 at least partially surrounds the aperture region AA1, that is, the third insulating stack 1 between any two adjacent isolation grooves 101 forms the first isolation portion 261. The boundary of the orthographic projection of the second isolation portion 262 on the substrate 21 is arranged in the range of the orthographic projection of the isolation groove 101 on the substrate 21. The second sub-portion 2433 is arranged in the isolation groove 101.

[0110] In yet some examples, as shown in FIGS. 13 and 14, the materials of the first isolation portion 261 and the second isolation portion 262 both include metal materials, the first sub-portion 2432 is located on the side of the second isolation portion 262 away from the substrate 21, the second sub-portion 2433 is located on the side of the first isolation portion 261 away from or close to the aperture region AA1, and is in contact with the first isolation portion 261.

[0111] In the related art, the display panel generates a black spot at the edge of the hole. Through research, the inventors found that although the first sub-portion and the second sub-portion are separated, the second sub-portion is in contact with the first isolation structure, so that the second sub-portion and the first sub-portion are electrically connected through the first isolation structure. The voltage received at the cathode end is transmitted from the pixel region to the isolation region through the cathode layer, causing the first sub-portion and the second sub-portion to have the cathode voltage. The voltage difference between the support layer and the first sub-portion and the second sub-portion is greater than the driving voltage of the potassium ion. The first ion in the polarizer moves along the edge of the mounting hole, and under the action of the voltage difference between the support layer and the first sub-portion and the second sub-portion, the first ion moves into the second sub-portion and the first sub-portion. Under the action of electrons and water vapor, the first ion reacts with the first inorganic encapsulation layer and / or the second inorganic encapsulation layer on the side of the first sub-portion and the second sub-portion away from the substrate, causing damage to the first inorganic encapsulation layer and / or the second inorganic encapsulation layer, thereby causing the display panel 20 to generate a black spot at the edge of the hole (English: Growing Dark Spot In Hole, abbreviated as: GDSH).

[0112] To solve the above technical problems, as shown in FIG. 7, FIG. 8, FIG. 9 and FIG. 10, some embodiments of the present disclosure provide a display panel 20, which further comprises a conductive block 27. The conductive block 27 is arranged between the substrate 21 and the first isolation structure 26, and is located in the isolation area AA2. The conductive block 27 is flush with the boundary of the aperture area AA1. The voltage difference between the conductive block 27 and the first sub-part 2432 and the second sub-part 2433 is less than or equal to the driving voltage of the first ion. For example, the driving voltage of the first ion is 1.5V, and the voltage difference between the conductive block 27 and the first sub-part 2432 and the second sub-part 2433 is less than 1V.

[0113] In this way, the voltage difference between the conductive block 27 and the first sub-part 2432 and the second sub-part 2433 is not enough to drive the first ion located between the conductive block 27 and the first sub-part 2432 and the second sub-part 2433 to move into the first sub-part 2432 and the second sub-part 2433, so as to reduce the number of the first ion in the first sub-part 2432 and the second sub-part 2433, so that the number of the first ion in the first sub-part 2432 and the second sub-part 2433 is less or none, which is beneficial to reduce the degree and speed of the reaction between the first inorganic encapsulation layer 251 and / or the second inorganic encapsulation layer 253 and the first ion away from the substrate 21, so as to reduce the risk of damage of the first inorganic encapsulation layer 251 and / or the second inorganic encapsulation layer 253, and further improve the problem of black spot of the display panel 20 at the aperture edge.

[0114] For example, as shown in FIG. 15, the orthographic projection of the first isolation structure 26 on the substrate 21 is located in the range of the orthographic projection of the conductive block 27 on the substrate 21.

[0115] In some embodiments, as shown in FIG. 15, the minimum distance between the first isolation structure 26 and the boundary of the aperture area AA3 is less than the accuracy of the cutter wheel or laser cutting (for example, ±15μm). In this way, the risk of cutting off the first isolation structure 26 can be reduced.

[0116] For example, the minimum distance between the first isolation structure 26 and the boundary of the aperture area AA3 is 15μm.

[0117] In some embodiments, as shown in FIG. 7 and FIG. 8, the conductive block 27 and the first isolation structure 26 are electrically insulated. The display panel 20 further comprises a first connecting line 28. The first connecting line 28 is connected with the conductive block 27 and connected with a first voltage terminal. Wherein, the voltage received at the first voltage terminal is less than the driving voltage of the first ions by the difference of the voltage on the first sub-portion 2432 and the second sub-portion 2433. In this way, the voltage difference between the conductive block 27 and the first sub-portion 2432 and the second sub-portion 2433 is less than or equal to the driving voltage of the first ions, which is beneficial to improve the problem of black spots at the hole edge of the display panel 20.

[0118] In some examples, as shown in FIG. 4, the peripheral area BB further comprises a binding area BB1, which is located at one side of the display area AA along the second direction Y. The display panel 20 further comprises a plurality of binding pins 29. The plurality of binding pins 29 are located on the substrate 21, and the plurality of binding pins 29 are located in the binding area BB1. The plurality of binding pins 29 are used for binding with a driving chip. The plurality of binding pins 29 comprises a first binding pin 291, and the first binding pin 291 is connected with the first voltage terminal. In this way, the signal on the first binding pin 291 can be transmitted to the conductive block 27 through the first voltage terminal and the first connecting line 28, so that the voltage difference between the conductive block 27 and the first sub-portion 2432 and the second sub-portion 2433 is less than or equal to the driving voltage of the first ions.

[0119] For example, the first binding pin 291 is configured to transmit a cathode signal, so that the voltage on the cathode layer 243 is the same as the voltage received at the first voltage terminal. In this way, the voltage difference between the conductive block 27 and the first sub-portion 2432 and the second sub-portion 2433 is 0, which cannot drive the first ions between the conductive block 27 and the first sub-portion 2432 and the second sub-portion 2433 to move, which is beneficial to improve the problem of black spots at the hole edge of the display panel 20.

[0120] Alternatively, for example, the first binding pin 291 is configured to transmit an initialization signal, so that the voltage difference between the conductive block 27 and the first sub-portion 2432 and the second sub-portion 2433 is small and less than the driving voltage of the first ions. In this way, the voltage difference between the conductive block 27 and the first sub-portion 2432 and the second sub-portion 2433 is not enough to drive the first ions between the conductive block 27 and the first sub-portion 2432 and the second sub-portion 2433 to move into the first sub-portion 2432 and the second sub-portion 2433, which is beneficial to improve the problem of black spots at the hole edge of the display panel 20.

[0121] In addition, the first binding pin 291 also transmits an initialization signal to the pixel circuit 231, and then initializes the node in the pixel circuit 231. In this way, the problem that the potential of the previous image frame remaining in the node affects the display image of the next image frame can be improved, thereby improving the brightness uniformity of the display panel 20.

[0122] In some embodiments, as shown in FIGS. 9 and 10, the conductive block 27 is connected with the first isolation structure 26 or the second sub-part 2433. In this way, the voltage difference between the conductive block 27 and the first sub-part 2432 and the second sub-part 2433 is 0, and the first ions between the conductive block 27 and the first sub-part 2432 and the second sub-part 2433 cannot be driven to move, which is beneficial to improve the problem of the black spot of the hole edge of the display panel 20.

[0123] Exemplarily, as shown in FIGS. 9 and 10, the display panel 20 further includes a first insulating layer 201. The first insulating layer 201 is located in the pixel area AA3 and extends to the isolation area AA2. The first insulating layer 201 is located between the first isolation structure 26 and the conductive block 27, and the first insulating layer 201 has a first through hole 2011 penetrating the first insulating layer 201. The first isolation structure 26 extends into the first through hole 2011 and is connected with the conductive block 27.

[0124] In some embodiments, the display panel 20 further includes a first connection line 28. The first connection line 28 is connected with the conductive block 27 and connected with the first voltage terminal, so that the voltage difference between the support layer 10 and the conductive block 27 is less than or equal to the driving voltage of the first ions.

[0125] In this way, the voltage difference between the support layer 10 and the conductive block 27 is not enough to drive the first ions between the support layer 10 and the conductive block 27 to move into the conductive block 27, which can reduce the number of the first ions in the conductive block 27, so that the number of the first ions in the conductive block 27 is less or none. This is beneficial to reduce the degree and speed of the reaction between the inorganic film layer on the side of the conductive block 27 away from the substrate 21 and the first ions, thereby reducing the risk of damage to the inorganic film layer.

[0126] In some examples, the first voltage terminal is grounded, so that the voltage difference between the support layer 10 and the conductive block 27 is 0, and the first ions between the support layer 10 and the conductive block 27 cannot be driven to move, which is beneficial to reduce the risk of damage to the inorganic film layer.

[0127] Exemplarily, the first binding pin 291 is configured to transmit a grounding signal, so that the conductive block 27 is grounded, and the voltage difference between the support layer 10 and the conductive block 27 is 0.

[0128] In some embodiments, as shown in FIG. 16, the plurality of pixel circuits 231 further include a plurality of redundant pixel circuits 2301, the plurality of first pixel circuits 221 are located in the pixel area AA3, and the plurality of redundant pixel circuits 2301 are located in the isolation area AA2. The plurality of redundant pixel circuits 2301 are adjacent to the first pixel circuits 221 located in the pixel area AA3 and close to the edge of the aperture area AA1. The redundant pixel circuits 2301 are electrically insulated from the light emitting devices 222, that is, the redundant pixel circuits 2301 do not control any light emitting device 222 to emit light, and even if the redundant pixel circuits 2301 have poor uniformity problems, it will not affect the light emission of any light emitting device 222.

[0129] In this way, the plurality of pixel circuits 231 are transferred from the first pixel circuits 221 to the redundant pixel circuits 2301 close to the edge of the aperture area AA1, which can improve the uniformity of the first pixel circuits 221, so that the light emitting devices 222 connected to the first pixel circuits 221 close to the aperture area AA1 can emit light normally, and the redundant pixel circuits 2301 are electrically insulated from the light emitting devices 222, that is, the redundant pixel circuits 2301 do not control any light emitting device 222 to emit light, and even if the redundant pixel circuits 2301 have poor uniformity problems, it will not affect the light emission of any light emitting device 222. Therefore, it is beneficial to reduce the risk of display panel 20 display abnormality.

[0130] In some examples, the pixel circuit layer 23 includes a semiconductor layer ACT. The semiconductor layer ACT includes an active layer pattern of the plurality of first pixel circuits 221 and an active layer pattern of the redundant pixel circuits 2301. Among them, the active layer pattern of the first pixel circuit 221 and the anode 2411 of the light emitting device 222 are connected, and the active layer pattern of the redundant pixel circuit 2301 and the anode 2411 of the light emitting device 222 are electrically insulated.

[0131] In this way, the semiconductor layer ACT is transferred from the active layer pattern of the first pixel circuit 221 to the active layer pattern of the redundant pixel circuit 2301 close to the edge of the aperture area AA1. In turn, avoid the first pixel circuit 221 from having poor uniformity problems, and improve the display effect of the display panel 20.

[0132] In some embodiments, as shown in FIG. 5 and FIG. 6, the first pixel circuit 221 includes a first transistor 2211, as shown in FIG. 17, FIG. 19, FIG. 19 and FIG. 20, the redundant pixel circuit 2301 includes a second transistor 23011. The above-mentioned semiconductor layer ACT includes an active part 23111 of the first transistor 2211 and an active part 23111 of the second transistor 23011.

[0133] The display panel 20 further comprises a first source-drain conductive layer SD1 and at least one third insulating layer 2302. The first source-drain conductive layer SD1 is located between the semiconductor layer ACT and the cathode layer 243, and comprises a first electrode of the second transistor 23011, wherein the first electrode is one of the source electrode and the drain electrode of the second transistor 23011. The at least one third insulating layer 2302 is arranged between the first electrode of the second transistor 23011 and the conductive block 27, and is located in the pixel area AA3 and extends to the isolation area AA2.

[0134] In some examples, as shown in FIG. 17, the first connection line 28 and the first electrode of the second transistor 23011 are arranged in the same layer and are connected to the first electrode of the second transistor 23011. The at least one third insulating layer 2302 is provided with a second through hole 23021 penetrating the at least one third insulating layer 2302. The first electrode of the second transistor 23011 extends into the second through hole 23021 and is connected to the conductive block 27.

[0135] In this way, on the one hand, the conductive block 27 can be connected to the first voltage terminal. The first voltage terminal can apply an electrical signal to the conductive block 27, so that the voltage difference between the conductive block 27 and the first sub-part 2432 and the second sub-part 2433 is less than or equal to the driving voltage of the first ion. On the other hand, the second through hole 23021 in the redundant pixel circuit 2301 can be used to connect the first connection line 28 and the conductive block 27 without the need to re-punch the at least one third insulating layer 2302, thereby simplifying the structure of the display panel 20.

[0136] In yet other examples, as shown in FIGS. 18, 19 and 20, the display panel 20 further comprises at least one fourth insulating layer 2303 arranged between the first electrode of the second transistor 23011 and the cathode layer 243. The at least one fourth insulating layer 2303 is located in the pixel area AA3 and extends to the isolation area AA2. The at least one fourth insulating layer 2303 is provided with a third through hole 23031.

[0137] The first connection line 28 is arranged between the at least one fourth insulating layer 2303 and the cathode layer 243, and extends into the third through hole 23031 and is connected to the first electrode of the second transistor 23011, so as to connect the conductive block 27 and the first voltage terminal. The first voltage terminal can apply an electrical signal to the conductive block 27, so that the voltage difference between the conductive block 27 and the first sub-part 2432 and the second sub-part 2433 is less than or equal to the driving voltage of the first ion.

[0138] Exemplarily, as shown in FIG. 18, the pixel circuit stack 23 further comprises a second source-drain conductive layer SD2. The second source-drain conductive layer SD2 is located between the at least one fourth insulating layer 2303 and the cathode layer 243. The first connection line 28 is located on the second source-drain conductive layer SD2. The third via hole 23031 is one in number and penetrates the at least one fourth insulating layer 2303, and the first connection line 28 is in contact with the first electrode of the second transistor 23011 by extending into the third via hole 23031.

[0139] Alternatively, exemplarily, as shown in FIG. 19 and FIG. 20, the pixel circuit stack 23 further comprises a second source-drain conductive layer SD2 and a third source-drain conductive layer SD3. The at least one fourth insulating layer 2303 comprises a first sub-layer 23032 and a second sub-layer 23033. The first sub-layer 23032 is located between the second source-drain conductive layer SD2 and the first source-drain conductive layer SD1, and the second sub-layer 23033 is located between the third source-drain conductive layer SD3 and the second source-drain conductive layer SD2. The first connection line 28 is located on the third source-drain conductive layer SD3.

[0140] As shown in FIG. 19, the third via hole 23031 is one in number and penetrates the first sub-layer 23032 and the second sub-layer 23033, and the first connection line 28 is in contact with the first electrode of the second transistor 23011. Alternatively, as shown in FIG. 20, the display panel 20 further comprises a transfer block 5 located on the second source-drain conductive layer SD2. The third via hole 23031 is two in number, one of which penetrates the first sub-layer 23032, and at this time, the transfer block 5 is in contact with the first electrode of the second transistor 23011 by extending into the third via hole 23031. The other one penetrates the second sub-layer 23033, and at this time, the first connection line 28 is in contact with the transfer block 5 by extending into the third via hole 23031.

[0141] In some embodiments, as shown in FIG. 4, the peripheral area BB comprises a fan-out area BB2, which is arranged on one side of the display area AA along the second direction Y. Exemplarily, the fan-out area BB2 is arranged on the lower side of the display area AA, and the fan-out area BB2 and the display area AA share a boundary (as shown in FIG. 4). In the case where the peripheral area BB comprises a binding area BB1, the fan-out area BB2 is located between the display area AA and the binding area BB1.

[0142] As shown in FIG. 4, the display area AA further comprises a central region AA4 and an edge region AA5, which is arranged on at least one side of the central region AA4 along the first direction X. Exemplarily, as shown in the figure, the edge region AA5 is arranged on both sides of the central region AA4.

[0143] It can be understood that the mounting hole H can be arranged in the central region AA4 and / or the edge region AA5. In some examples, the mounting hole H can be arranged in the central region AA4, i.e., the opening region AA1 and the isolation region AA2 are located in the central region AA4. In other examples, the mounting hole H can be arranged in the edge region AA5, i.e., the opening region AA1 and the isolation region AA2 are located in the edge region AA5. In yet other examples, the mounting hole H is partially located in the central region AA4 and partially located in the edge region AA5, i.e., the opening region AA1 and the isolation region AA2 are located in the central region AA4 and also located in the edge region AA5.

[0144] As shown in FIG. 21, the display panel 20 further includes a plurality of data lines 202 arranged on the substrate 21 and located on the side of the first electrode of the second transistor 23011 away from the substrate 21, the plurality of data lines 202 are arranged at intervals along the first direction X and extend along the second direction Y.

[0145] In this document, "the plurality of data lines 202 extend along the second direction Y" means that the overall wiring direction of the plurality of data lines 202 is along the second direction Y, but it is not limited to that each position of the plurality of data lines 202 strictly extends along the second direction Y. That is, "extend along the second direction Y" here not only includes the plurality of data lines 202 that strictly extend along the second direction Y at each position, but also includes the plurality of data lines 202 that locally bend to avoid interference with other structures.

[0146] The plurality of data lines 202 includes a first data line 2021 arranged in the edge region AA5.

[0147] On this basis, the display panel 20 further includes a plurality of first transfer lines 203 and a plurality of second transfer lines 204. The plurality of first transfer lines 203 is arranged in the same layer as the plurality of data lines 202 and located in the central region AA4. The plurality of first transfer lines 203 extends along the second direction Y and is connected with the fan-out region BB2. The plurality of second transfer lines 204 is arranged between the plurality of first transfer lines 203 and the first electrode of the second transistor 23011, or arranged between the plurality of first transfer lines 203 and the cathode layer 243. The plurality of second transfer lines 204 extends along the first direction X, and one second transfer line 204 is connected with one first data line 2021 and one first transfer line 203.

[0148] As shown in FIG. 21, the plurality of data lines 202 further includes a plurality of second data lines 2022 arranged in the central region AA4, and the plurality of second data lines 2022 are arranged at intervals along the first direction X. The plurality of second data lines 2022 is directly connected with the fan-out region BB2.

[0149] That is, the second data line 2022 disposed in the central region AA4 is directly connected with the fan-out region BB2, and the first data line 2021 disposed in the edge region AA5 is connected through the first adapter line 203, the second adapter line 204 and the fan-out region BB2. This arrangement can be referred to as a display area AA fan-out FIAA (English: Fanout In AA; for short: FIAA) or fan-out in panel (English: Fanout In Panel; for short: FIP). In this way, the size of the fan-out region BB2 along the second direction Y can be reduced, that is, the frame width of the display panel 20 is reduced, and the display device 1000 can realize a narrow frame.

[0150] On the basis of the above-mentioned embodiments, the first connection line 28 is disposed in the same layer as the first adapter line 203 and / or the second adapter line 204.

[0151] In this way, the first connection line 28 and the first adapter line 203 and / or the second adapter line 204 can be formed by a one-time patterning process, thereby reducing the manufacturing cost of the display panel 20.

[0152] In some examples, as shown in FIG. 21, the first connection line 28 includes a plurality of first sub-lines 281 and a plurality of second sub-lines 282. The plurality of first sub-lines 281 extend along the second direction Y and are spaced apart along the first direction X, and the first sub-lines 281 and the first adapter line 203 are disposed in the same layer. In this way, the first sub-lines 281 and the first adapter line 203 can be formed by a one-time patterning process, thereby reducing the manufacturing cost of the display panel 20.

[0153] The plurality of second sub-lines 282 extend along the first direction X and are spaced apart along the second direction Y, and the second sub-lines 282 and the second adapter line 204 are disposed in the same layer. In this way, the second sub-lines 282 and the second adapter line 204 can be formed by a one-time patterning process, thereby reducing the manufacturing cost of the display panel 20.

[0154] For example, the plurality of second sub-lines 282 and the plurality of first sub-lines 281 are connected to form a mesh structure. In this way, the capacitive load of the first connection line 28 can be reduced, thereby reducing the power consumption of the display panel 20.

[0155] In some embodiments, as shown in FIG. 21, the display panel 20 further includes a plurality of first signal lines 205 and a plurality of second signal lines 206. The plurality of first signal lines 205 extend along the second direction Y and pass through the pixel region AA3, that is, in the pixel region AA3, the length of the first signal line 205 along the second direction Y is substantially equal to the length of the display area AA.

[0156] Part of the first signal line 205 has a first opening K1, which divides the first signal line 205 into a first signal segment 2051 and a second signal segment 2052. The first signal segment 2051 is located on the side of the second signal segment 2052 close to the fan-out area BB2. The first signal segment 2051 constitutes the first transfer line 203. The second signal segment 2052 and at least part of the first signal line 205 without the opening constitute the first sub-line 281.

[0157] The second signal line 206 extends along the first direction X and passes through the pixel area AA3, that is, both ends of the second signal line 206 along the first direction X extend to the edge of the pixel area AA3.

[0158] Part of the second signal line 206 has a second opening K2, which divides the first signal line 205 into a third signal segment 2061 and a fourth signal segment 2062. The third signal segment 2061 is located on the side of the fourth signal segment 2062 close to the edge area AA5. Part of the second signal line 206 has a third opening K3 and a fourth opening K4, which divide the second signal line 206 into a fifth signal segment 2063, a sixth signal segment 2064, and a seventh signal segment 2065. The sixth signal segment 2064 is located between the fifth signal segment 2063 and the seventh signal segment 2065. The third signal segment 2061 and the sixth signal segment 2064 constitute the second transfer line 204. The fourth signal segment 2062, the fifth signal segment 2063, the seventh signal segment 2065, and at least part of the second signal line 206 without the opening constitute the second sub-line 282.

[0159] In some embodiments, as shown in FIG. 22, the first connection line 28 and the conductive block 27 are arranged in the same layer. In this way, the first connection line 28 and the conductive block 27 are formed in one patterning process, which can reduce the manufacturing cost of the display panel 20.

[0160] For example, the first connection line 28 extends along the first direction X and extends to the peripheral area BB to be connected with the first voltage terminal. Alternatively, for example, the first connection line 28 extends along the second direction Y and extends to the peripheral area BB to be connected with the first voltage terminal.

[0161] In some embodiments, as shown in FIG. 7, FIG. 8, FIG. 9, and FIG. 10, the display panel 20 includes a plurality of first isolation structures 26, for example, the display panel 20 includes seven first isolation structures 26. The plurality of first isolation structures 26 are arranged at intervals in the direction from the isolation area AA2 to the aperture area AA1. In this way, the number of the cathode layer 243 broken in the isolation area AA2 can be increased, and the risk of water vapor invading the pixel area AA3 from the aperture area AA1 through the cathode layer 243 can be further reduced, thereby improving the problem of the display panel 20 generating black spots at the hole edge.

[0162] On this basis, as shown in FIGS. 7, 8, 9 and 10, the display panel 20 further comprises a pad 207. The pad 207 is located between the substrate 21 and the cathode layer 243, the pad 207 is partially located between two adjacent first isolation structures 26, partially located on a side of the first isolation structure 26 away from the substrate 21, and covers an end surface of the first isolation structure 26 away from the substrate 21, and a surface of the pad 207 away from the substrate 21 protrudes in a direction away from the substrate 21. The cathode layer 243 further comprises a third sub-portion 2434, the third sub-portion 2434 is located on a side of the pad 207 away from the substrate 21, and is connected with an adjacent first sub-portion 2432.

[0163] In the process of preparing the cathode layer 243, due to the influence of gravity, the minimum distance between the surface of the third sub-portion 2434 away from the substrate 21 and the pad 207 is smaller than the minimum distance between the surface of the first sub-portion 2432 away from the substrate 21 and the first isolation structure 26, and smaller than the minimum distance between the surface of the second sub-portion 2433 away from the substrate 21 and the substrate 21, that is, the minimum thickness of the third sub-portion 2434 is smaller than the minimum thickness of the first sub-portion 2432, and smaller than the minimum thickness of the second sub-portion 2433. In this way, the resistance of the third sub-portion 2434 is larger, which can make the resistance of the cathode layer 243 larger (for example, the resistance of the cathode layer 243 is increased from 194 ohms to 5400 ohms), so as to make the current on the cathode layer 243 smaller, and thus reduce the power consumption of the display panel 20.

[0164] In the case that the conductive block 27 is connected with the first isolation structure 26 or the second sub-portion 2433, and the first connection line 28 is connected with the conductive block 27, at this time, the voltage difference between the cathode voltage terminal and the first voltage terminal is larger (for example, the voltage difference is 4.6V), the resistance of the third sub-portion 2434 is larger, which can make the resistance of the cathode layer 243 larger, can reduce the risk of short-circuiting between the cathode voltage terminal and the first voltage terminal, and is beneficial to improving the service life of the display panel 20.

[0165] In some embodiments, as shown in FIGS. 17, 18, 19 and 20, the display panel 20 further comprises a plurality of first conductive layers 208 which are stacked, and the plurality of first conductive layers 208 are arranged between the first isolation structure 26 and the substrate 21.

[0166] It can be understood that the closer to the substrate 21 the first conductive layer 208 is, the more the number of insulating layers between the first conductive layer 208 and the first isolation structure 26, that is, the thicker the film thickness of the insulating layers between the first conductive layer 208 and the first isolation structure 26.

[0167] The conductive block 27 is located in the first conductive layer 208 closest to the substrate 21, so that when the first ions enter the conductive block 27, the insulating layer between the first conductive layer 208 and the first isolation structure 26 is thick, and the reaction time of the first ions is long, thereby prolonging the service life of the display panel 20.

[0168] In some embodiments, as shown in FIGS. 17, 18, 19 and 20, the display panel 20 further includes a plurality of first conductive layers 208 and a second insulating layer 209 stacked. The plurality of first conductive layers 208 is arranged between the first isolation structure 26 and the substrate 21. The second insulating layer 209 is located in the pixel area AA3 and extends to the isolation area AA2. The second insulating layer 209 is located between the first isolation structure 26 and the first conductive layer 208 including the conductive block 27.

[0169] The thickness of the second insulating layer 209 (for example, 8 mm) is greater than the thickness of the inorganic encapsulation layer (for example, 2 mm) in a direction perpendicular to the substrate 21. In this way, when the first ions enter the conductive block 27, the second insulating layer 209 can also make the reaction time of the first ions longer, thereby prolonging the service life of the display panel 20. The inorganic encapsulation layer includes a first inorganic encapsulation layer 251 and a second inorganic encapsulation layer 253.

[0170] In some embodiments, as shown in FIGS. 7 and 9, the display panel 20 further includes at least one barrier structure 6. The barrier structure 6 is arranged in the isolation area AA2 and located on a side of the first isolation structure 26 away from the opening. The barrier structure 6 is arranged around the opening area AA1. The barrier structure 6 is used to block water and oxygen, thereby improving the water and oxygen blocking performance of the encapsulation layer 25. In the process of preparing the first organic encapsulation layer 252, the barrier structure 6 is also used to block the first organic encapsulation layer 252, so that the first organic encapsulation layer 252 is located on a side of the barrier structure 6 away from the opening area AA1, thereby enabling the second inorganic encapsulation layer 253 to completely cover the first organic encapsulation layer 252, and improving the problem that water and oxygen corrode the first organic encapsulation layer 252 and cause the first organic encapsulation layer 252 to fail. That is, the part of the encapsulation layer 25 located on a side of the barrier structure 6 away from the opening area AA1 includes the first inorganic encapsulation layer 251, the first organic encapsulation layer 252 and the second inorganic encapsulation layer 253 stacked, and the part of the encapsulation layer 25 located on a side of the barrier structure 6 close to the opening area AA1 includes the first inorganic encapsulation layer 251 and the second inorganic encapsulation layer 253 stacked, and the first inorganic encapsulation layer 251 and the second inorganic encapsulation layer 253 are in contact.

[0171] On this basis, as shown in FIG. 7 and FIG. 9, the display panel 20 further comprises a second isolation structure 7, which is arranged in the isolation area AA2 and is located on the side of the barrier wall structure 6 away from the first isolation structure 26. The structure of the second isolation structure 7 can be the same as that of the first isolation structure 26. That is, the cathode layer 243 in the isolation area AA2 is also disconnected at the second isolation structure 7, which can further reduce the risk of water vapor invading the pixel area AA3 from the opening area AA1 through the cathode layer 243, thereby improving the problem of black spots generated by the display panel 20 at the hole edge.

[0172] In some embodiments, as shown in FIG. 7, FIG. 9 and FIG. 15, the orthographic projection of the second isolation structure 7 on the substrate 21 is also located within the range of the orthographic projection of the conductive block 27 on the substrate 21.

[0173] In some embodiments, in the direction perpendicular to the substrate 21 and away from the substrate 21, the pixel circuit layer 23 comprises a light shielding layer BSM, at least one semiconductor layer ACT and a plurality of gate conductive layers GT.

[0174] Among them, the conductive block 27 can be located in any one of the light shielding layer BSM, the semiconductor layer ACT or the gate conductive layer GT.

[0175] Exemplarily, as shown in FIG. 22, the conductive block 27 is located in the light shielding layer BSM, so that the distance between the conductive block 27 and the first isolation structure 26 is the largest, so as to make the film thickness of the insulating layer between the conductive block 27 and the first isolation structure 26 the thickest, which is beneficial to improve the reaction time of the first ion.

[0176] It can be understood that in the case that the conductive block 27 is located in the low-temperature polysilicon semiconductor layer ACT1 or the oxide semiconductor layer ACT2, the conductive block 27 is conductive, and the properties (for example, conductivity) of the conductive block 27 are substantially the same as those of the conductor.

[0177] In addition, as shown in FIG. 22, the light shielding layer BSM comprises a plurality of light shielding blocks 8, and the orthographic projection of the light shielding blocks 8 on the substrate 21 at least partially overlaps with the orthographic projection of the active part 23111 on the substrate 21. In this way, the conductive block 27 and the light shielding block 8 can be formed by one patterning process, so as to reduce the preparation cost of the display panel 20.

[0178] The above embodiments are exemplified below in combination with the film layers included in the pixel circuit layer 23.

[0179] In some embodiments, as shown in FIG. 5, the pixel circuit 231 includes low-temperature polysilicon thin film transistors and oxide thin film transistors. At this time, in the direction perpendicular to the substrate 21 and away from the substrate 21, the pixel circuit stack 23 includes, in sequence, the light shielding layer BSM, the low-temperature polysilicon semiconductor layer ACT1, the first gate insulating layer GI1, the first gate conductive layer GT1, the second gate insulating layer GI2, the second gate conductive layer GT2, the first interlayer insulating layer ILD1, the oxide semiconductor layer ACT2, the third gate insulating layer GI3, the third gate conductive layer GT3, the second interlayer insulating layer ILD2, the first source-drain conductive layer SD1, the first planarization layer PLN1, the second planarization layer PLN2, the third source-drain conductive layer SD3, and the third planarization layer PLN3.

[0180] The conductive block 27 is located in the light shielding layer BSM. The active part 23111 of the low-temperature polysilicon thin film transistor is located in the low-temperature polysilicon semiconductor layer ACT1. The gate 23114 of the low-temperature polysilicon thin film transistor is located in the first gate conductive layer GT1. The active part 23111 of the oxide thin film transistor is located in the oxide semiconductor layer ACT2. The gate 23114 of the oxide thin film transistor is located in the third gate conductive layer GT3. The source 23112 and the drain 23113 of the low-temperature polysilicon thin film transistor, and the source 23112 and the drain 23113 of the oxide thin film transistor are all located in the first source-drain conductive layer SD1. The data line 202 and the first switching line 203 are located in the second source-drain conductive layer SD2, and the second switching line 204 is located in the third source-drain conductive layer SD3.

[0181] In some examples, as shown in FIGS. 7 and 9, in the direction perpendicular to the substrate 21 and away from the substrate 21, the first source-drain conductive layer SD1 includes the first sub-conductive layer 2, the second sub-conductive layer 3, and the third sub-conductive layer 4 which are stacked, the material of the first sub-conductive layer 2 and the third sub-conductive layer 4 includes titanium, and the material of the second sub-conductive layer 3 includes aluminum. The first isolation structure 26 includes the first isolation part 261, the second isolation part 262, and the third isolation part 263, the first sub-conductive layer 2 and the first isolation part 261 are located in the same layer, the second sub-conductive layer 3 and the second isolation part 262 are located in the same layer, and the third sub-conductive layer 4 and the third isolation part 263 are located in the same layer.

[0182] In some examples, as shown in FIGS. 11 and 12, the conductive block 27 is located in the light shielding layer BSM, and in the direction perpendicular to the substrate 21 and away from the substrate 21, the first isolation structure 26 includes the first isolation part 261 and the second isolation part 262 which are stacked, the material of the first isolation part 261 includes an insulating material, and the material of the second isolation part 262 includes a metal material. The second isolation part 262 is located in the first source-drain conductive layer SD1, and the third insulating stack 1 includes the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the third gate insulating layer GI3, and the second interlayer insulating layer ILD2.

[0183] In some examples, as shown in FIG. 13 and FIG. 14, the conductive block 27 is located in the light shielding layer BSM, the first isolation structure 26 is located in the first isolation portion 261 and the second isolation portion 262, and the material of the first isolation portion 261 and the second isolation portion 262 includes a metal material.

[0184] In some examples, as shown in FIG. 9 and FIG. 10, the first isolation structure 26 is located in the first source-drain conductive layer SD1, and the conductive block 27 is located in the light shielding layer BSM. At this time, the first insulating layer 201 includes the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the third gate insulating layer GI3, and the second interlayer insulating layer ILD2.

[0185] In some examples, as shown in FIG. 9 and FIG. 10, the first isolation structure 26 is located in the first source-drain conductive layer SD1, and the conductive block 27 is located in the light shielding layer BSM. At this time, the second insulating layer 209 includes the first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the third gate insulating layer GI3, and the second interlayer insulating layer ILD2.

[0186] In some examples, the first connection line 28 and the first electrode of the second transistor 23011 are located in the same layer, and the first connection line 28 is located in the first source-drain conductive layer SD1.

[0187] In some examples, the first connection line 28 is located between the first electrode and the cathode layer 243, and the first connection line 28 is located in the second source-drain conductive layer SD2 and / or the third source-drain conductive layer SD3.

[0188] Exemplarily, the first connection line 28 includes a first sub-line 281 and a second sub-line 282. The first sub-line 281 is located in the second first source-drain conductive layer SD1, and the second sub-line 282 is located in the first source-drain conductive layer SD1.

[0189] In yet another embodiment, as shown in FIG. 6, the pixel circuit 231 includes a low-temperature polysilicon thin film transistor. At this time, along the direction perpendicular to the substrate 21 and away from the substrate 21, the pixel circuit layer 23 includes the light shielding layer BSM, the low-temperature polysilicon semiconductor layer ACT1, the first gate insulating layer GI1, the first gate conductive layer GT1, the second gate insulating layer GI2, the second gate conductive layer GT2, the interlayer insulating layer ILD, the first source-drain conductive layer SD1, the first planarization layer PLN1, the second planarization layer PLN2, the third source-drain conductive layer SD3, and the third planarization layer PLN3, which are sequentially arranged.

[0190] The conductive block 27 is located in the light shielding layer BSM. The active part 23111 of the low-temperature polysilicon thin film transistor is located in the low-temperature polysilicon semiconductor layer ACT1. The gate 23114 of the low-temperature polysilicon thin film transistor is located in the first gate conductive layer GT1. The source 23112 and the drain 23113 of the low-temperature polysilicon thin film transistor are located in the first source-drain conductive layer SD1, the data line 202 and the first transfer line 203 are located in the second source-drain conductive layer SD2, and the second transfer line 204 is located in the third source-drain conductive layer SD3.

[0191] In some examples, as shown in FIGS. 7 and 9, along a direction perpendicular to the substrate 21 and away from the substrate 21, the first source-drain conductive layer SD1 includes the first sub-conductive layer 2, the second sub-conductive layer 3 and the third sub-conductive layer 4 which are arranged in a stack, the material of the first sub-conductive layer 2 and the third sub-conductive layer 4 includes titanium, and the material of the second sub-conductive layer 3 includes aluminum. The first isolation structure 26 includes the first isolation part 261, the second isolation part 262 and the third isolation part 263, the first sub-conductive layer 2 and the first isolation part 261 are arranged in the same layer, the second sub-conductive layer 3 and the second isolation part 262 are arranged in the same layer, and the third sub-conductive layer 4 and the third isolation part 263 are arranged in the same layer.

[0192] In some examples, as shown in FIGS. 11 and 12, the conductive block 27 is located in the light shielding layer BSM, along a direction perpendicular to the substrate 21 and away from the substrate 21, the first isolation structure 26 includes the first isolation part 261 and the second isolation part 262 which are arranged in a stack, the material of the first isolation part 261 includes an insulating material, and the material of the second isolation part 262 includes a metal material. The second isolation part 262 is located in the first source-drain conductive layer SD1, and the third insulating layer 1 includes the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD.

[0193] In some examples, as shown in FIGS. 13 and 14, the conductive block 27 is located in the light shielding layer BSM, along a direction perpendicular to the substrate 21 and away from the substrate 21, the first isolation structure 26 includes the first isolation part 261 and the second isolation part 262 which are arranged in a stack, and the material of the first isolation part 261 and the second isolation part 262 includes a metal material. The first isolation part 261 is located in the first source-drain conductive layer SD1, and the second isolation part 262 is located in the second source-drain conductive layer SD2.

[0194] In some examples, as shown in FIGS. 9 and 10, the first isolation structure 26 is located in the first source-drain conductive layer SD1, and the conductive block 27 is located in the light shielding layer BSM. At this time, the first insulating layer 201 includes the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD.

[0195] In some examples, as shown in FIG. 9 and FIG. 10, the first isolation structure 26 is located in the first source-drain conductive layer SD1, and the conductive block 27 is located in the light-blocking layer BSM. At this time, the second insulating layer stack 209 includes the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD.

[0196] In some examples, the first connection line 28 and the first electrode of the second transistor 23011 are located in the same layer, and the first connection line 28 is located in the first source-drain conductive layer SD1.

[0197] In some examples, the first connection line 28 is located between the first electrode and the cathode layer 243, and the first connection line 28 is located in the second source-drain conductive layer SD2 and / or the third source-drain conductive layer SD3.

[0198] Exemplarily, the first connection line 28 includes a first sub-line 281 and a second sub-line 282. The first sub-line 281 is located in the second first source-drain conductive layer SD1, and the second sub-line 282 is located in the first source-drain conductive layer SD1.

[0199] In the description of this specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0200] The above description is merely specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who thinks of changes or replacements within the technical scope disclosed by the present disclosure should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel having a display area; the display area comprising an opening area, an isolation area, and a pixel area; The isolation zone is located between the aperture area and the pixel area; the display panel includes: Substrate; A first isolation structure is disposed on the substrate and located in the isolation region; the first isolation structure surrounds at least a portion of the opening region; A cathode layer covers the isolation region; the cathode layer includes a first sub-part and a second sub-part separated from each other, the first sub-part and the second sub-part being located in the isolation region, the first sub-part being located on the side of the first isolation structure away from the substrate, and the second sub-part being located on the side of the first isolation structure away from or close to the opening region; and the first sub-part and the second sub-part are electrically connected through the first isolation structure. A conductive block is disposed between the substrate and the first isolation structure and located in the isolation region; the conductive block is flush with the boundary of the opening region near the boundary of the opening region; the voltage difference between the conductive block and the first sub-part and the second sub-part is less than or equal to the driving voltage of the first ion; wherein the first ion reacts chemically with the inorganic material.

2. The display panel according to claim 1, wherein, The conductive block and the first isolation structure are electrically insulated; the display panel further includes: The first connecting line is connected to the conductive block and to the first voltage terminal.

3. The display panel according to claim 2, wherein, The voltage on the cathode layer is the same as the voltage received at the first voltage terminal.

4. The display panel according to claim 1, wherein, The conductive block is connected to the first isolation structure or the second sub-part.

5. The display panel according to claim 4, further comprising: A first insulating stack is located in the pixel area and extends to the isolation area. The first insulating stack is located between the first isolation structure and the conductive block. The first insulating stack has a first through-hole that penetrates the first insulating stack. The first isolation structure extends into the first through-hole and connects with the conductive block.

6. The display panel according to claim 4 or 5, further comprising: A first connecting line is connected to the conductive block and to a first voltage terminal; the conductive block is configured such that the voltage difference between it and the support layer is less than or equal to the driving voltage of the first ion.

7. The display panel according to claim 6, wherein, The first voltage terminal is grounded.

8. The display panel according to any one of claims 2, 3, 6 and 7, further comprising: A pixel circuit stack is disposed between the substrate and the cathode layer, the pixel circuit stack including a plurality of first pixel circuits and a plurality of redundant pixel circuits; The plurality of first pixel circuits are located in the pixel region, and the plurality of redundant pixel circuits are located in the isolation region; the plurality of redundant pixel circuits are adjacent to the first pixel circuits located in the pixel region and close to the edge of the aperture region. The light-emitting device stack is located on the side of the pixel circuit stack away from the substrate; the light-emitting device stack includes multiple light-emitting devices; the first pixel circuit is electrically connected to the light-emitting device, and the redundant pixel circuit is electrically insulated from the light-emitting device.

9. The display panel according to claim 8, wherein, The redundant pixel circuit includes a second transistor, and the pixel circuit stack further includes: The active layer includes the active portion of the second transistor; A first source-drain conductive layer is located between the active layer and the cathode layer; the first source-drain conductive layer includes the first electrode of the second transistor; the first connecting line and the first electrode of the second transistor are disposed in the same layer and are connected to the first electrode of the second transistor; At least one third insulating layer is disposed between the first electrode of the second transistor and the conductive block, located in the pixel region and extending to the isolation region; the at least one third insulating layer is provided with a second through hole penetrating the at least one third insulating layer; the first electrode of the second transistor extends into the second through hole and is connected to the conductive block.

10. The display panel according to claim 8, wherein, The redundant pixel circuit includes a second transistor, and the pixel circuit stack further includes: The active layer includes the active portion of the second transistor; A first source / drain conductive layer is located between the active layer and the cathode layer; the first source / drain conductive layer includes the first electrode of the second transistor; At least one third insulating layer is disposed between the first source / drain conductive layer and the conductive block, located in the pixel region, and extending to the isolation region; the at least one third insulating layer is located between the conductive block and the first electrode of the second transistor; the at least one third insulating layer is provided with a second through-hole penetrating the at least one third insulating layer; the first electrode of the second transistor extends into the second through-hole and connects to the conductive block; At least one fourth insulating layer is disposed between the first source / drain conductive layer and the cathode layer, located in the pixel region, and extending to the isolation region; the at least one fourth insulating layer is provided with a third via. The first connecting line is disposed between the at least one fourth insulating layer and the cathode layer, and the first connecting line extends into the third through hole and connects to the first electrode of the second transistor.

11. The display panel according to claim 10, further comprising a fan-out area, wherein the fan-out area is disposed on one side of the display area along a second direction; the display area further comprising a central area and an edge area, wherein the edge area is disposed on at least one side of the central area along a first direction; wherein, The first direction intersects with the second direction; The display panel also includes: Multiple data lines are disposed on the substrate; the multiple data lines are arranged at intervals along the first direction; the multiple data lines include a first data line; the first data line is disposed in the edge region and extends along the second direction; Multiple first adapter cables are arranged on the same layer as the multiple data cables and located in the central area; the first adapter cables extend along the second direction and are connected to the fan-out area; Multiple second adapter lines are disposed between the multiple first adapter lines and the first source / drain conductive layer, or between the multiple first adapter lines and the cathode layer; the second adapter lines extend along the first direction, and one second adapter line is connected to one first data line and one first adapter line; The first connecting line is disposed on the same layer as the first adapter line and / or the second adapter line.

12. The display panel according to claim 11, wherein, The first connecting line includes: Multiple first sub-lines extend along the second direction and are spaced apart along the first direction; the first sub-lines and the first adapter lines are arranged on the same layer; Multiple second sub-lines extend along the first direction and are spaced apart along the second direction; the second sub-lines and the second adapter line are arranged on the same layer; the multiple second sub-lines and the multiple first sub-lines are connected to form a mesh structure.

13. The display panel according to any one of claims 2, 3, 6 and 7, wherein the first connecting line and the conductive block are disposed on the same layer.

14. The display panel according to any one of claims 1 to 13, comprising a plurality of first isolation structures; The plurality of first isolation structures are spaced apart along the direction from the isolation zone to the opening zone; The display panel also includes: A pad is located between the substrate and the cathode layer; the pad is partially located between two adjacent first isolation structures, partially located on the side of the first isolation structure away from the substrate, and covers part of the end face of the first isolation structure away from the substrate; the surface of the pad away from the substrate protrudes in a direction away from the substrate; The cathode layer further includes a third sub-part located on the side of the pad away from the substrate and connected to the adjacent first sub-part; the minimum distance between the surface of the third sub-part away from the substrate and the pad is less than the minimum distance between the surface of the first sub-part away from the substrate and the first isolation structure, and less than the minimum distance between the surface of the second sub-part away from the substrate and the substrate.

15. The display panel according to any one of claims 1 to 14, further comprising: A multilayer first conductive layer is stacked and disposed between the first isolation structure and the substrate; The conductive block is located in the first conductive layer of the multilayer first conductive layer that is closest to the substrate.

16. The display panel according to any one of claims 1 to 15, further comprising: An inorganic encapsulation layer is located in the display area and extends into the isolation area; The inorganic encapsulation layer is located on the side of the cathode layer away from the substrate and covers the cathode layer; A multilayer first conductive layer is stacked and disposed between the first isolation structure and the substrate; the conductive block is located in one of the first conductive layers; A second insulating stack is located in the pixel region and extends into the isolation region. The second insulating stack is located between the first isolation structure and the first conductive layer including the conductive block. The thickness of the second insulating stack is greater than the thickness of the inorganic encapsulation layer in a direction perpendicular to the substrate.

17. The display panel according to any one of claims 1 to 16, further comprising: An active layer is located in the pixel region and between the substrate and the cathode layer; The active layer includes a channel section; A light-shielding layer is located between the active layer and the substrate; The light-shielding layer includes a plurality of light-shielding blocks, and the orthographic projection of the light-shielding blocks on the substrate at least partially overlaps with the orthographic projection of the channel portion on the substrate; The conductive block is located in the light-shielding layer.

18. A display module, comprising: A support layer, which is grounded; The display panel as claimed in any one of claims 1 to 17, the display panel having a display side and a non-display side disposed opposite to each other, the display side being farther away from the support layer than the non-display side; A polarizer is located on the side of the display panel away from the support layer; the material of the polarizer includes a first ion.

19. A display device, comprising: The display panel as described in any one of claims 1 to 17, or the display module as described in claim 18.

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