Memory fault prediction method and system

Abstract

Embodiments of the present application provide a memory fault prediction method and system. The method comprises: when a correctable error occurs in a target memory, a first fault parsing module of a host unit acquires a physical address of the target memory, and parses the physical address in M dimensions to obtain M first parsing results, wherein each first parsing result is used for indicating that a correctable error occurs in a corresponding dimension in the target memory; a baseboard management controller acquires the M first parsing results, and inputs the M first parsing results into M prediction models corresponding to the M dimensions, so as to obtain M prediction values; and the baseboard management controller fuses the M prediction values to obtain a fused value, wherein the fused value is used for predicting whether an uncorrectable error will occur in the target memory. The present application solves the problem in the related art of weak memory fault prediction performance, thereby achieving the effect of improving the memory fault prediction performance.

Description

Method and system for memory failure prediction

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202410851428.0, filed on June 27, 2024, and entitled "Method and system for memory failure prediction", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present application relate to the field of artificial intelligence, in particular, to a method and system for memory failure prediction. BACKGROUND

[0004] The reliability of memory is an important indicator affecting the performance of the entire server system. Once a memory failure occurs, it may cause a server system failure, leading to system crash or data loss, and even server downtime when uncorrectable errors occur. Therefore, reducing the impact of memory failure on the server and ensuring the reliability of the memory are crucial to ensuring the stable operation of the server system.

[0005] Traditional fault diagnosis techniques can only locate the position of the fault occurrence after the memory failure occurs, and give a diagnosis result after the fault occurs, which cannot recover the serious consequences caused by the error. Therefore, it is necessary to predict the memory failure of the device before the fault occurs and take corresponding maintenance measures, so as to avoid the serious consequences after the fault occurs. However, the current memory failure prediction method usually uses a special inference server node, and the prediction model deployed on the inference node performs the prediction action. Since the inference node is usually connected to each server node to be predicted through a star topology, once the inference node fails, the memory failure prediction service will be terminated, making the reliability of the fault prediction system weak and the memory failure prediction performance weak. Moreover, deploying the prediction system requires additional manpower and resources, and when the scale of the data center is large, it requires a large overhead to achieve memory failure prediction.

[0006] At present, there is no effective solution to the above problems. SUMMARY

[0007] Embodiments of the present application provide a method and system for memory failure prediction to at least solve the problem of weak memory failure prediction performance in the related art.

[0008] According to a first aspect of embodiments of the present application, a memory fault prediction method is provided, comprising: in the case that a target memory has a correctable error, a first fault resolution module of a host unit acquires a physical address of the target memory, and resolves the physical address in M dimensions to obtain M first resolution results, wherein M is an integer greater than or equal to 2, the M dimensions are obtained based on different storage unit granularities of the target memory, and the first resolution result is used to indicate that the target memory has a correctable error in the corresponding dimension; a baseboard management controller acquires the M first resolution results, inputs the M first resolution results into M prediction models corresponding to the M dimensions to obtain M prediction values; and the baseboard management controller fuses the M prediction values to obtain a fused value, wherein the fused value is used to predict whether the target memory will have an uncorrectable error.

[0009] In an example embodiment, the first fault resolution module in the host unit acquires the physical address of the target memory, comprising: in the case that the host unit detects that the target memory has a correctable error, the modular electronic control unit of the host unit sends the detected fault information to a register and sends an interrupt signal to an interrupt control management module of the host unit; in the case that the interrupt control management module receives the interrupt signal, the first fault resolution module acquires the physical address from the fault information stored in the register.

[0010] In an example embodiment, the baseboard management controller acquires the M first resolution results from the host unit and inputs the M first resolution results into the M prediction models corresponding to the M dimensions, comprising: in a self-checking phase at system startup, the host unit reports the M first resolution results output by the first fault resolution module to the baseboard management controller through a first interface of the host unit; the baseboard management controller stores the M first resolution results to a data storage module; and the baseboard management controller inputs the M first resolution results into the M prediction models to obtain the M prediction values.

[0011] In an example embodiment, in the case that the M prediction models are online models, the baseboard management controller inputs the M first resolution results into the M prediction models to obtain the M prediction values, comprising: in the case that the target memory has a correctable error in the t th prediction period, the baseboard management controller acquires a correctable error sequence of the target memory in the t th prediction period from the data storage module, wherein the correctable error sequence includes resolution results obtained by the first fault resolution module resolving the physical address of the target memory in the t th prediction period, and the correctable error sequence includes the M first resolution results; the baseboard management controller determines a first error sequence corresponding to the target memory in the t-1 th prediction period; and the baseboard management controller inputs the correctable error sequence and the first error sequence into the M prediction models to obtain the M prediction values.

[0012] In an example embodiment, the substrate management controller inputs the correctable error sequence and the first error sequence into the M prediction models to obtain M prediction values, comprising: the substrate management controller divides the correctable error sequence into q correctable error subsequences according to M dimensions, wherein each of the q correctable error subsequences corresponds to one of the M dimensions, and q is a positive integer less than or equal to M; the substrate management controller determines a target prediction model corresponding to each correctable error subsequence in the M prediction models, wherein each correctable error subsequence and the target prediction model corresponding thereto belong to the same dimension; and the substrate management controller inputs the correctable error subsequence and the first error sequence into the target prediction model to obtain a prediction value output by the target prediction model.

[0013] In an example embodiment, the substrate management controller determines the first error sequence corresponding to the target memory in the t-1 prediction period, comprising: in the case of a historical failure score, the substrate management controller calculates the historical failure score and the actual number of each dimension distributed in the t-1 prediction period by the following formula to obtain the first error sequence:

[0014] wherein δ is an error scaling factor, x t is a sequence value in the historical correctable error sequence.

[0015] In an example embodiment, the substrate management controller determines the historical failure score by the following formula:

[0016] wherein is the actual number of correctable errors of the target memory distributed in each dimension in the t-2 prediction period, σ is a constant, α is a preset scaling factor, and β is a preset offset.

[0017] In an example embodiment, the substrate management controller fuses the M prediction values to obtain a fused value, comprising: predicting the fused value by the following formula: cell P(t) = P row (t) + d · (P col (t) + P 2 (t)) + d bank · P 3 (t) + d dev · P 4 (t) + d rank · P

[0018] d is a decay factor less than 1, P cell (t) is a prediction value output by the prediction model corresponding to the storage unit dimension, and P row(t) is a prediction value P storing a prediction model output corresponding to the row dimension col (t) is a prediction value P storing a prediction model output corresponding to the column dimension bank (t) is a prediction value P storing a prediction model output corresponding to the array dimension dev (t) is a prediction value P storing a prediction model output corresponding to the grain dimension rank (t) is a prediction value P storing a prediction model output corresponding to the block dimension

[0019] In an example embodiment, in the case where the M dimensions are divided into multiple levels, the higher the level of the dimension, the larger the granularity of the storage unit corresponding to the dimension, and in the case where the M prediction models are regular models, the substrate management controller inputs the M first analysis results into the M prediction models to obtain M prediction values, including: the substrate management controller obtains a target sub-level included in a failure level in which the prediction target memory is predicted to have an uncorrectable error, wherein the target sub-level corresponds to a target dimension among the M dimensions, and the prediction model corresponding to the target dimension is a target prediction model; the target prediction model predicts whether the target memory has an uncorrectable error at the target sub-level according to the first analysis result, to obtain a first prediction value, wherein the M prediction values include the first prediction value; the target prediction model determines a target probability that the target memory has an uncorrectable error at the target sub-level based on the first prediction value; and the target prediction model determines whether an uncorrectable error will occur based on the target probability.

[0020] In an example embodiment, the target prediction model predicts whether the target memory has an uncorrectable error at the target sub-level according to the first analysis result to obtain a first prediction value, including: in the case where the target sub-level includes a storage array level, the target prediction model determines a second address included in the first analysis result, wherein the second address is an address of a storage array having a correctable error in the same storage block, and predicts whether the target memory has an uncorrectable error at the target sub-level based on a first number of addresses belonging to the same target storage array included in the second address, to obtain the first prediction value; in the case where the target sub-level includes a memory grain level, the target prediction model determines a second number of target storage arrays having a correctable error in the same memory grain and a third number of target storage arrays having a correctable error based on the first analysis result, and predicts whether the target memory has an uncorrectable error at the target sub-level based on the second number and the third number, to obtain the first prediction value; and in the case where the target sub-level includes a memory sub-array level, the target prediction model determines a third address of a memory sub-array having a correctable error in a memory sub-array belonging to the same storage array based on the first analysis result, and predicts whether the target server memory has an uncorrectable error at the target sub-level based on a fourth number of storage units included in the third address, to obtain the first prediction value.

[0021] In an example embodiment, the first prediction value is determined based on a first number of addresses included in the second address that belong to the same target storage array, and the first prediction value indicates whether the uncorrectable error will occur in the target sub-tier of the target in-place storage.

[0022] In an example embodiment, the first prediction value is determined based on the second number and a third number, and the first prediction value indicates whether the uncorrectable error will occur in the target sub-tier of the target in-place storage.

[0023] In an example embodiment, the first prediction value is determined based on a fourth number of storage units included in the third address, and the first prediction value indicates whether the uncorrectable error will occur in the target sub-tier of the target in-place storage.

[0024] In an example embodiment, when the M prediction models are offline models, the baseboard management controller inputs the M first analysis results into the M prediction models to obtain M prediction values, including: the baseboard management controller inputs the M first analysis results into the M offline models to obtain M prediction values, wherein the offline models are trained using training sample data, the training sample data includes a sample in-place storage that has the correctable error in the M dimensions, and a label of the sample in-place storage, and the label of the sample in-place storage indicates whether the uncorrectable error actually occurs in the sample in-place storage.

[0025] In an example embodiment, the baseboard management controller fuses the M prediction values to obtain a fused value, including: the baseboard management controller obtains M weight values corresponding to the M dimensions; and the baseboard management controller performs weighted summation on the M weight values and the M prediction values to obtain the fused value.

[0026] According to a second aspect of the embodiments of the present application, a memory failure prediction method is provided, comprising: in the case that a correctable error occurs in a target memory, a modular electronic control unit of a host unit sends detected failure information to a register of the host unit; the register stores the failure information; a second failure analysis module of a baseboard management controller acquires a physical address from the failure information of the register through a second interface, and analyzes the physical address in M dimensions to obtain M second analysis results, where M is an integer greater than or equal to 2, and the M dimensions are obtained based on different storage unit granularities of the target memory, and the second analysis result is used to indicate that the target memory has a correctable error in the corresponding dimension; the baseboard management controller acquires the M second analysis results from the second failure analysis module, inputs the M second analysis results into M prediction models corresponding to the M dimensions, and obtains M prediction values; and the baseboard management controller fuses the M prediction values to obtain a fusion value, where the fusion value is used to predict whether the target memory will have an uncorrectable error.

[0027] In one example embodiment, the method further comprises: in the case that the second failure analysis module fails to acquire the physical address from the register, a first failure analysis module of the host unit acquires the physical address of the target memory from the failure information stored in the register, and analyzes the physical address in the M dimensions to obtain M first analysis results, where the first analysis result is used to indicate that the target memory has a correctable error in the corresponding dimension; the baseboard management controller acquires the M first analysis results, inputs the M first analysis results into the M prediction models corresponding to the M dimensions, and obtains M prediction values; and the baseboard management controller fuses the M prediction values to obtain a fusion value, where the fusion value is used to predict whether the target memory will have an uncorrectable error; and the case that the second failure analysis module fails to acquire the physical address from the register comprises: within a preset time length of a host unit restart, the second failure analysis module fails to acquire the physical address from the register.

[0028] In one example embodiment, the first failure analysis module of the host unit acquires the physical address of the target memory from the failure information stored in the register, comprising: the modular electronic control unit of the host unit sends an interrupt signal to an interrupt control management module in the case that the second interface fails to send the physical address to the second failure analysis module; and the interrupt control management module triggers the first failure analysis module to acquire the physical address from the failure information stored in the register in the case that the interrupt signal is received.

[0029] In one example embodiment, the method further comprises: a data storage module of the baseboard management controller acquires the M first analysis results from the first failure analysis module through the first interface, and stores the M first analysis results; and the data storage module of the baseboard management controller acquires the M second analysis results from the second failure analysis module, and stores the M second analysis results.

[0030] In an example embodiment, the baseboard management controller obtains M second resolution results from the second fault resolution module, inputs the M second resolution results into M prediction models corresponding to the M dimensions, and obtains M prediction values, including: in a case where the M prediction models are online models, the baseboard management controller inputs the M second resolution results into the M prediction models to obtain the M prediction values, including: in a case where the target memory has a correctable error in a tth prediction period, the baseboard management controller obtains a correctable error sequence of the target memory in the tth prediction period from the data storage module, where the correctable error sequence includes resolution results obtained by the second fault resolution module on physical addresses of the target memory in the tth prediction period, and the correctable error sequence includes the M second resolution results; the baseboard management controller determines a first error sequence corresponding to the target memory in a (t-1)th prediction period; and the baseboard management controller inputs the correctable error sequence and the first error sequence into the M prediction models to obtain the M prediction values.

[0031] In an example embodiment, in a case where the M dimensions are divided into multiple levels, the higher the level of the dimension, the larger the granularity of the storage unit corresponding to the dimension, and in a case where the M prediction models are rule models, the baseboard management controller inputs the M second resolution results into the M prediction models to obtain the M prediction values, including: the baseboard management controller obtains a target sub-level included in a fault level in which the target memory is predicted to have an uncorrectable error, where the target sub-level corresponds to a target dimension among the M dimensions, and a target prediction model corresponding to the target dimension; the target prediction model predicts whether the target memory has an uncorrectable error in the target sub-level according to the second resolution results to obtain a second prediction value, where the M prediction values include the second prediction value; the target prediction model determines a target probability that the target memory has an uncorrectable error in the target sub-level based on the second prediction value; and the target prediction model determines whether the uncorrectable error occurs based on the target probability.

[0032] In an example embodiment, in a case where the M prediction models are offline models, the baseboard management controller inputs the M first resolution results into the M prediction models to obtain the M prediction values, including: the baseboard management controller inputs the M second resolution results into the M offline models to obtain the M prediction values, where the offline models are trained using training sample data, and the training sample data includes a sample memory having a correctable error in the M dimensions and a label of the sample memory, and the label of the sample memory is whether the sample memory actually has an uncorrectable error.

[0033] According to a third aspect of embodiments of the present application, a system for memory failure prediction is provided, comprising: a host unit comprising a first failure analysis module configured to, in a case where a correctable error occurs in a target memory, acquire a physical address of the target memory and analyze the physical address in M dimensions to obtain M first analysis results, wherein M is an integer greater than or equal to 2; a baseboard management controller configured to acquire the M first analysis results from the host unit, input the M first analysis results into corresponding prediction models of a multi-dimensional prediction model to obtain M prediction values, wherein the multi-dimensional prediction model comprises M prediction models corresponding to the M dimensions; and the baseboard management controller is further configured to fuse the M prediction values by a fusion strategy to obtain a fusion value, wherein the fusion value is used to represent a probability of an uncorrectable error occurring in the target memory.

[0034] In an example embodiment, the host unit further comprises: a modular electronic control unit, an interrupt control management module, and a register, the modular electronic control unit is configured to, in a case where a correctable error is detected in the target memory, send the detected failure information to the register and send an interrupt signal to the interrupt control management module; and the interrupt control management module is configured to, in a case where the interrupt signal is received, trigger the first failure analysis module to acquire the physical address from the failure information stored in the register.

[0035] In an example embodiment, the host unit further comprises: a first interface, one end of the first interface is connected to the first failure analysis module, and the other end is connected to a data storage module of the baseboard management controller; and the first interface is used to transmit the M first analysis results in the first failure analysis module to the data storage module, so as to record the M first analysis results in the data storage module.

[0036] In an example embodiment, the baseboard management controller further comprises: a data storage module configured to record the M first analysis results; and a multi-dimensional prediction module connected to the data storage module, the multi-dimensional prediction module comprises M prediction models and is configured to acquire the M first analysis results from the data storage module, input the M first analysis results into corresponding prediction models respectively, predict a probability of an uncorrectable error occurring in the target memory at a corresponding level by the prediction models, and obtain M prediction values; and the baseboard management controller further comprises: a fusion module configured to fuse the M prediction values based on a fusion strategy to obtain a fusion value.

[0037] According to a fourth aspect of the embodiments of the present application, a system for memory fault prediction is provided, comprising: a host unit, a baseboard management controller; the host unit comprises a modular electronic control unit, a register, and a second interface; the modular electronic control unit is configured to send detected fault information to the register in the case of detecting a correctable error of a target memory; the register is configured to store the fault information of the target memory; one end of the second interface is connected to the register, and the other end is connected to a second fault analysis module of the baseboard management controller; the baseboard management controller comprises: the second fault analysis module is configured to obtain a physical address from the fault information of the register through the second interface, and analyze the physical address in M dimensions to obtain M second analysis results, wherein M is an integer greater than or equal to 2, the M dimensions are different levels based on different storage unit granularities of the target memory, the higher the level, the larger the storage unit granularity, and the storage unit at a high level comprises a plurality of storage units at a low level, and the second analysis result is used to indicate the level where the correctable error of the target memory occurs.

[0038] In an example embodiment, the host unit further comprises a first fault analysis module configured to obtain the physical address from the register and analyze the physical address in the M dimensions to obtain M first analysis results in the case that the second fault analysis module fails to obtain the physical address from the register, wherein the first analysis result is used to indicate the level where the correctable error of the target memory occurs, and the second fault analysis module failing to obtain the physical address from the register comprises: the second fault analysis module failing to obtain the physical address from the register within a preset time length of a host unit restart.

[0039] In an example embodiment, the host unit further comprises: an interrupt control management module connected to the modular electronic control unit, and the modular electronic control unit is further configured to send an interrupt signal to the interrupt control management module in the case of detecting that the second interface fails to send the physical address to the second fault analysis module; and the interrupt control management module is configured to trigger the first fault analysis module to obtain the physical address from the fault information stored in the register in the case of receiving the interrupt signal.

[0040] According to a fifth aspect of the embodiments of the present application, a computer readable storage medium is further provided, and the computer readable storage medium stores a computer program, wherein the computer program is configured to execute the steps in any of the method embodiments when running.

[0041] According to a sixth aspect of the embodiments of the present application, an electronic device is further provided, comprising a memory and a processor, the memory stores a computer program, and the processor is configured to execute the computer program to execute the steps in any of the method embodiments.

[0042] According to a seventh aspect of the embodiments of the present application, a computer program product is also provided, comprising a computer program which, when executed by a processor, implements the steps in any of the method embodiments described above.

[0043] According to the present application, in the case that a correctable error occurs in the target memory, the first fault resolution module of the host unit acquires the physical address of the target memory, and resolves the physical address in M dimensions to obtain M first resolution results, where M is an integer greater than or equal to 2, and the M dimensions are obtained based on different storage unit granularities of the target memory, and the first resolution result is used to indicate that the target memory has a correctable error in the corresponding dimension; the baseboard management controller acquires the M first resolution results, inputs the M first resolution results into M prediction models corresponding to the M dimensions to obtain M prediction values; and the baseboard management controller fuses the M prediction values to obtain a fusion value, where the fusion value is used to predict whether the target memory will have an uncorrectable error.

[0044] Thanks to the joint work of the host unit and the BMC, the full-link automatic processing process from target memory fault detection to fault state information recording, to memory fault location resolution, to synchronization of the fault location resolution result to the BMC unit, to processing and prediction of the fault location resolution result is realized, thus solving the problem of weak memory fault prediction performance in the related art, and improving the memory fault prediction performance. BRIEF DESCRIPTION OF DRAWINGS

[0045] FIG. 1 is a hardware structure block diagram of an operation device according to an embodiment of the present application;

[0046] FIG. 2 is a flowchart of a memory fault prediction method according to an embodiment of the present application;

[0047] FIG. 3 is an example diagram of a learning type memory fault prediction algorithm according to an embodiment of the present application;

[0048] FIG. 4 is a schematic diagram of a memory row fault according to an embodiment of the present application;

[0049] FIG. 5 is a structural schematic diagram of a DRAM particle according to an embodiment of the present application;

[0050] FIG. 6 is a connection schematic diagram of a central controller and a dual in-line memory module according to an embodiment of the present application;

[0051] FIG. 7 is a connection schematic diagram of a channel and a Rank according to an embodiment of the present application;

[0052] FIG. 8 is a storage area level fault prediction schematic diagram according to an embodiment of the present application;

[0053] FIG. 9 is a Device level fault prediction schematic diagram according to an embodiment of the present application;

[0054] FIG. 10 is a schematic diagram of a memory subarray level failure prediction according to an embodiment of the present application;

[0055] FIG. 11 is a fusion mode update flowchart according to an embodiment of the present application;

[0056] FIG. 12 is a failure prediction system workflow diagram one according to an embodiment of the present application;

[0057] FIG. 13 is a failure prediction system workflow diagram two according to an embodiment of the present application;

[0058] FIG. 14 is a failure prediction system workflow diagram two according to an embodiment of the present application;

[0059] FIG. 15 is a failure prediction system workflow diagram three according to an embodiment of the present application;

[0060] FIG. 16 is a schematic diagram of the architecture of a failure prediction system according to an embodiment of the present application;

[0061] FIG. 17 is a schematic diagram of the architecture of a multi-dimensional prediction model according to an embodiment of the present application;

[0062] FIG. 18 is a schematic diagram of the architecture of a failure prediction system according to an embodiment of the present application;

[0063] FIG. 19 is a structural block diagram of an apparatus for predicting the failure type of a memory according to an embodiment of the present application. DETAILED DESCRIPTION

[0064] In recent years, with the rapid development of the artificial intelligence industry, especially the emergence of AIGC (Artificial Intelligence General Certification), various industries have shown diversified and explosive development. At the same time, the demand for server computing power has increased dramatically, and the requirements for memory as a fast storage unit have become higher and higher. In particular, the reliability of memory has become an important indicator affecting the performance of the entire server system. Memory failures often cause server system failures, and when uncorrectable errors occur, it can even cause the server to crash. According to statistics, about 50% of hardware-triggered server downtime is caused by memory failures, and 1.3% to 4% of machines are affected by uncorrectable errors every year. Therefore, how to reduce the impact of memory failures on servers has become a hot issue that needs to be solved in the current server industry field.

[0065] Traditional fault diagnosis technology can locate the position of the fault after the memory fault occurs, such as the position number of the fault memory stick (dimm), storage channel (MM) and the like, but since it can only give a diagnosis result after the fault occurs, it cannot recover the serious consequences caused by the error. Therefore, from the perspective of reducing economic losses caused by faults, the fault diagnosis technology shows great limitations. In order to realize the early prediction of memory fault state, memory fault prediction technology emerges as the times require.

[0066] Traditional memory fault prediction usually adopts a dedicated inference server node, that is, the memory fault information of each server is collected to the inference node, and then the prediction model deployed on the inference node performs the prediction action; in addition, the prediction process basically uses single dimension information of memory (such as minimum storage cell dimension fault information) as the prediction input. However, the above memory prediction scheme has two problems. One is poor system reliability and large deployment overhead. Since the inference node is usually connected to each server node to be predicted through a star topology, once the inference node fails, the memory fault prediction service will be terminated, that is, the system reliability is weak, and in addition, deploying the prediction system requires additional manpower and resources, and when the scale of the data center is large, it requires a large overhead to realize memory fault prediction. The second is poor system prediction performance. The factors leading to memory failure are complex and numerous, such as electromagnetic interference between memory cells and internal amplifier circuit damage, which makes it much more difficult to predict memory failure than hard disks and other parts. The traditional prediction only considers cell dimension fault data as the input of model training and prediction, and does not fully utilize other dimension fault information, so the overall prediction performance of the system is poor.

[0067] In summary, in order to solve the above problems, the present application proposes a fault prediction system which ensures accurate prediction while improving system reliability and reducing overall system deployment overhead.

[0068] The English abbreviations in the present application are explained as follows:

[0069] BMC: Baseboard Management Controller, baseboard management controller, server management unit.

[0070] CPU: Central Processing Unit, central processor, as the operation and control core of the computer system, it is the final execution unit of information processing and program running.

[0071] PECI: Platform Environment Control Interface, platform environment control interface.

[0072] ECC: Error Checking and Correcting. ECC is a memory error correction principle and a relatively advanced means of checking and correcting memory errors.

[0073] CE: Correctable Error, refers to errors that the system can detect and automatically correct.

[0074] UCE: Uncorrectable Error, refers to an error that the system cannot automatically correct.

[0075] eSPI: Enhanced Serial Peripheral Interface.

[0076] SMI: System Management Interrupt.

[0077] MSR: Model-Specific Register.

[0078] CSR: Control and Status Register.

[0079] DRAM: Dynamic Random Access Memory, is a type of volatile memory used in computer systems that requires periodic refresh to maintain the stored data.

[0080] DIMM: Dual In-line Memory Module, is a modular device used to install and expand computer memory.

[0081] DQs: Data Queue lines, are signal lines that connect memory modules (such as DRAM) to the memory controller.

[0082] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0083] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0084] The host unit and the basic controller in the method embodiments provided in the embodiments of the present application can be executed in a server device or similar computing device. Taking an example of running on a computing device, Fig. 1 is a hardware structure block diagram of the computing device according to the embodiments of the present application. As shown in Fig. 1, the computing device can include one or more (only one is shown in Fig. 1) processors 102 (the processor 102 can include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 configured to store data, wherein the computing device can further include a transmission device 106 configured to have a communication function and an input and output device 108. Those skilled in the art can understand that the structure shown in Fig. 1 is only schematic, which does not limit the structure of the computing device. For example, the computing device can further include more or less components than those shown in Fig. 1, or have a different configuration from that shown in Fig. 1.

[0085] The memory 104 can be configured to store computer programs, for example, software programs of application software and modules, such as the computer program corresponding to the memory failure prediction method in the embodiments of the present application. The processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, that is, implements the above-mentioned method. The memory 104 can include a high-speed random access memory, and can further include a non-volatile memory, such as one or more magnetic storage devices, a flash memory, or other non-volatile solid-state memories. In some examples, the memory 104 can include a memory remotely arranged with respect to the processor 102, and these remote memories can be connected to the computing device through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0086] The transmission device 106 is configured to receive or send data via a network. The optional example of the above-mentioned network can include a wireless network provided by a communication provider of the server device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC for short), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, RF for short) module, which is configured to communicate with the Internet in a wireless manner.

[0087] In the embodiments of the present application, a memory failure prediction method is provided, and Fig. 2 is a flow chart I of the memory failure prediction method according to the embodiments of the present application, as shown in Fig. 2, the flow includes the following steps:

[0088] In step S202, in the case that the target memory has a correctable error, the first fault analysis module of the host unit acquires the physical address of the target memory and analyzes the physical address in M dimensions to obtain M first analysis results, where M is an integer greater than or equal to 2, and the M dimensions are obtained based on different storage unit granularities of the target memory, and the first analysis result is used to indicate that the target memory has a correctable error in the corresponding dimension.

[0089] The host unit can be a BIOS (Basic Input / Output System, Basic Input / Output System, BIOS for short), and the first fault analysis module is configured to analyze the physical address of the target memory having a correctable error. The first fault analysis module can analyze the physical address of the target memory from multiple dimensions, where the multiple dimensions can be storage dimensions of the target memory, such as a minimum storage unit (cell), a storage row (row), a storage column (col), a storage array (bank), a storage block (rank), a storage channel (DQ), a memory particle (also known as a storage particle, device), a memory stick (dimm), a memory channel (channel), etc. In the case that the target memory has a correctable error, the host unit acquires fault information of the target memory and stores the fault information in a register inside the host unit. The fault information includes the physical address of the target memory. At the same time, the first fault analysis module of the host unit analyzes the physical address of the target memory from multiple dimensions to obtain multiple analysis results.

[0090] In some embodiments, the modular electronic control unit of the host unit sends the detected fault information to the register and sends an interrupt signal to the interrupt control management module of the host unit in the case that the target memory has a correctable error. In the case that the interrupt control management module receives the interrupt signal, the first fault analysis module acquires the physical address from the fault information stored in the register.

[0091] The modular electronic control unit can be an IMC (Internal Model Control) controller, which is configured to detect fault information of the target memory. The fault can be a single-bit error (correctable by ECC logic) or a multi-bit error (causing ECC failure). The register can be an MSR / CSR register, which is configured to store the fault information detected by the modular electronic control unit, such as the physical address of the faulty target memory. When a correctable error occurs in the target memory, the modular electronic control unit detects the fault information of the target memory. At this time, the modular electronic control unit triggers an SMI interrupt to the interrupt control management module and records the fault information of the target memory in the MSR and CSR registers in the CPU. When the interrupt control management module receives the interrupt signal, the interrupt control management module triggers the first fault analysis module to obtain the physical address of the target memory from the register, thereby completing the physical address analysis of the target memory. By analyzing the physical address of the target memory with correctable error from different dimensions through the first fault analysis module, the problem can be located without understanding the dimensions, which helps to predict memory faults from different dimensions, improves the stability and reliability of the system. At the same time, through the analysis of the first fault analysis module, the memory fault can be found and repaired in time, the risk of system crash is reduced, and the performance and efficiency of the system are improved. Through the analysis of different dimensions, the reasons for the memory fault can be more comprehensively understood, targeted measures can be taken to avoid similar problems from occurring again, and the maintainability and reliability of the system are improved.

[0092] In step S204, the baseboard management controller obtains M first analysis results, inputs the M first analysis results into M prediction models corresponding to M dimensions, and obtains M prediction values.

[0093] The M prediction models can be prediction models corresponding to different dimensions, such as a minimum storage unit (cell), a storage row, a storage column (col), a storage array (bank), a storage block (rank), a memory access channel (DQ), a memory device, a memory dimm, a memory channel, and the like. The prediction models can be online prediction models, offline prediction models, rule matching prediction models, and the like. The M prediction models are used to predict the corresponding analysis results in the M first analysis results obtained by the first fault analysis module, and obtain M prediction values. Since different memory fault prediction models are embedded in the baseboard management controller (BMC) of each server to match different configuration types (such as different configurations of memory dimm models, capacities, batches, and the like) of the servers, the prediction models are flexibly and accurately matched with the configurations of the servers, better prediction performance is achieved, and at the same time, different types of prediction algorithms and different dimension fault information of the memory are considered, the value of the available fault information of the memory is fully tapped, the utilization rate of the fault information is improved, and the memory fault prediction dimension is effectively expanded.

[0094] In some embodiments, during a self-check phase at system startup, the host unit reports the M first analysis results output by the first fault analysis module to the baseboard management controller through a first interface of the host unit; the baseboard management controller stores the M first analysis results in a data storage module; and the baseboard management controller inputs the M first analysis results into M prediction models to obtain M prediction values.

[0095] The data storage module is configured to store analysis results of the target memory physical address. The first interface can be an eSPI interface, which is connected to the first fault analysis module of the host unit and the data storage module of the BMC, respectively. Through the first interface, the host unit transmits the first analysis results of the target memory obtained by the first fault analysis module to the BMC unit and stores them in the data storage module. During a self-check phase (POST) at system startup, the host unit transmits the first analysis results obtained by the first fault analysis module to the BMC through the first interface and stores them in the data storage module of the BMC. After preprocessing the first analysis results stored in the data storage module, the BMC inputs the preprocessed first analysis results into the M prediction models. The preprocessing includes removing abnormal data, completing missing data, classifying data, labeling data, and the like. Through preprocessing of the analysis results of the target memory physical address, the quality and availability of the analysis results are improved, thereby helping to improve the accuracy and efficiency of the model.

[0096] In step S206, the substrate management controller fuses the M prediction values to obtain a fused value, wherein the fused value is used to predict whether the target memory will have an uncorrectable error.

[0097] Through the above steps, the joint host unit cooperates with the BMC to realize the automatic processing process of the whole link from target memory fault detection to fault state information recording, to memory fault location resolution, to synchronization of the fault location resolution result to the BMC unit, to processing and prediction of the fault location resolution result, thereby solving the problem of weak memory fault prediction performance in the related art, and improving the memory fault prediction performance.

[0098] Meanwhile, by predicting the probability of the target memory having an uncorrectable error through the BMC, each server has the function of memory fault prediction, thereby eliminating the need to rely on an additional inference server, reducing the risk of prediction function paralysis caused by inference server failure, improving the reliability of the prediction function, and avoiding the deployment of inference node servers, saving a lot of manpower and resources, and reducing system deployment overhead.

[0099] The execution subject of the above steps can be a server, a terminal, etc., but is not limited thereto.

[0100] In some embodiments, in the case that the M prediction models are online models, the substrate management controller inputs the M first resolution results into the M prediction models to obtain M prediction values, including: in the case that the target memory has a correctable error in the tth prediction period, the substrate management controller acquires a correctable error sequence of the target memory in the tth prediction period in the data storage module, wherein the correctable error sequence includes the resolution result obtained by the first fault resolution module resolving the physical address of the target memory in the tth prediction period, and the correctable error sequence includes M first resolution results; the substrate management controller determines the corresponding first error sequence of the target memory in the t-1th prediction period; and the substrate management controller inputs the correctable error sequence and the first error sequence into the M prediction models to obtain M prediction values.

[0101] In some embodiments, the substrate management controller inputs the correctable error sequence and the first error sequence into the M prediction models to obtain M prediction values, including: the substrate management controller divides the correctable error sequence into q correctable error subsequences according to M dimensions, wherein each of the q correctable error subsequences corresponds to one of the M dimensions, and q is a positive integer less than or equal to M; the substrate management controller determines a target prediction model corresponding to each correctable error subsequence in the M prediction models, wherein each correctable error subsequence and the target prediction model corresponding thereto belong to the same dimension; and the substrate management controller inputs the correctable error subsequence and the first error sequence into the target prediction model to obtain a prediction value output by the target prediction model.

[0102] In some embodiments, in actual application, for an online model, after obtaining the fault information of the target memory, the first fault analysis module of the host unit analyzes the physical address of the target memory, and subdivides and classifies the target memory fault data into six different dimensions of minimum storage unit (cell), storage row (row), storage column (col), storage array (bank), storage device (device), and storage block (rank). Through a learning algorithm, the entire data set does not need to be loaded into the memory for model training, but the minimum storage unit cell is taken as the minimum unit, and the model parameters are updated according to the samples in the fault data set at a certain time interval. Since in the memory fault prediction learning algorithm, the learning process of each cell is relatively independent, large-scale data sets can be processed more effectively, so that data processing can also be efficiently performed in a BMC environment with limited memory resources. In addition, a key advantage of the learning algorithm is continuous learning of new fault data. With the continuous collection of new fault data, the model can immediately extract the features of these data and adjust the parameters, thereby maintaining the best fitting to the current memory usage mode and fault mode.

[0103] That is, by dividing the fault dimensions and determining the corresponding fault prediction sub-models, the fault prediction of the current dimension is completed by using the fault sub-models corresponding to different dimensions. After the learning algorithm completes the fault prediction of each dimension, the first prediction values corresponding to different dimensions are collected and fused, the prediction values of these multiple dimensions are fused, and finally a prediction result is output. At the same time, in order to optimize the use of computing resources, only the minimum storage units (cells) that have appeared at least once are recorded to assist the fault prediction sub-models in adjusting.

[0104] By the above steps, the memory failure data corresponding to the t-1th prediction period is determined as a sample for predicting the failure in the tth prediction period, and the relationship between the actual situation of the memory failure data occurring in the t-1th prediction period and the failure prediction value is determined, the error sequence for adjusting the algorithm is determined based on the relationship, and thus the prediction value of the memory failure in the t+1th prediction period is determined in combination with the correctable error sequence of the tth prediction period and the error sequence corresponding to the t-1th prediction period, the failure situation of the same memory is determined according to the prediction value, so that the determination of the monitoring mode for the memory is determined in advance, the early prediction before the failure is realized, and the above early prediction only needs the memory failure data at the current time and the error sequence corresponding to the last time, which reduces the operation demand of system resources, thus solving the problems that the judgment process of memory failure in the related art is complex and the system resource consumption in the judgment process is large, achieving the early prediction of the possible memory failure of the memory, and only adjusting the scoring error at the current time each time, avoiding that a single large error covers the cumulative effect before, and realizing the effect of improving the prediction accuracy.

[0105] By dividing the failure dimension, the memory failure characteristics on the server are fully mined, compared with the single-level prediction mode, the corresponding failure prediction sub-model is determined for the failure dimension, the utilization rate of the failure information can be improved, and the accuracy of the failure prediction is improved.

[0106] In some embodiments, the baseboard management controller determines a first error sequence corresponding to the target memory in the t-1th prediction period, including: in the case that there is a historical failure score, the baseboard management controller calculates the historical failure score and the actual number distributed in each dimension in the t-1th prediction period by the following formula to obtain the first error sequence;

[0107] Wherein, δ is an error scaling factor, x t is a sequence value in the historical correctable error sequence.

[0108] In some embodiments, the baseboard management controller determines the historical failure score by the following formula:

[0109] Wherein, y τ is the actual number of correctable errors of the target memory distributed in each dimension in the t-2th prediction period, σ is a constant, α is a preset scaling factor, and β is a preset offset.

[0110] It should be noted that in actual application, the CE history of the same cell is periodically detected and recorded continuously to obtain the CE history record X t= (x0, x1,..., x t-1 t ) as input. Wherein, represents the number of CE occurred on the cell in the time range (τ-1, τ). At time t, the algorithm will score the memory failure at next time based on the CE history, determined by the first formula; wherein, the correlation function R(τ) in the first formula is defined as follows:

[0111] Optionally, since a and β are scaling factor and offset in the Gaussian function respectively, they are used to adjust the output value of the correlation function. It should be noted that in the process of optimizing the algorithm of the present application, a and β can be adjusted as needed to achieve the best performance.

[0112] At the same time, at time t, the prediction error can be calculated according to the memory failure prediction value of the t-1th prediction period and the actual CE event, and the prediction error sequence y t = (y0, y1,..., y t-1 ) is constructed, and the second formula can be associated with the first formula, wherein the sigmoid function is used in the second formula to normalize the CE record of the t+1th prediction period, the purpose is to smooth the dramatic fluctuations caused by CE. Normalization ensures that the error value is compressed to a suitable interval, maintains the stability of the algorithm and promotes its convergence. In the formula, δ is used as an error scaling factor, which is used to fine-tune the expansion speed of the error. By reasonably selecting the value of δ, the sensitivity in the learning process can be controlled. The formula compares the actual number of CEs observed by the cell (after normalization) with the predicted value to calculate the prediction error. The error is used to correct the prediction behavior at the previous time. Through the above design, the historical prediction error sequence y t (x t ) of the cell gradually matches the true failure pattern during use.

[0113] In summary, the calculation of the failure prediction value of the first formula takes into account the historical error sequence, which can be determined by the second formula combined with historical memory failure data and the failure correlation determined by R(τ). And if the past prediction value of a cell is too high, it indicates that the cell has experienced multiple CEs and presents lower reliability. However, when the cell has not occurred CE for a long time, due to the correlation function R(τ), the new prediction value will gradually decrease due to the high prediction value caused by frequent CE. Therefore, the algorithm of the present application uses a dynamic learning process to retain the influence of historical CE, and only adjusts the prediction value error at the current time for each prediction, avoiding the problem of single large error masking the cumulative effect before, and improving the adaptability of the prediction result to the actual situation.​

[0114] In some embodiments, the substrate management controller fuses the M predicted values to obtain a fused value, comprising: predicting the fused value by the following formula: P(t) = P cell (t) + d · (P row (t) + P col (t)) + d 2 · P bank (t) + d 3 · P dev (t) + d 4 · P rank (t),

[0115] d is an attenuation factor less than 1, P cell (t) is a predicted value of a predicted model output corresponding to a storage unit dimension, P row (t) is a predicted value of a predicted model output corresponding to a storage row dimension, P col (t) is a predicted value of a predicted model output corresponding to a storage column dimension, P bank (t) is a predicted value of a predicted model output corresponding to a storage array dimension, P dev (t) is a predicted value of a predicted model output corresponding to a storage device dimension, P rank (t) is a predicted value of a predicted model output corresponding to a storage bank dimension, and P(t) is the fused value.

[0116] The M predicted values of the M dimensions are calculated using the fusion formula to obtain the fused value of the multi-level learning predicted model output. It should be noted that the cell dimension directly determines the reliability of the memory, so the cell level occupies the most important position in the prediction model. At the same time, the row fault and the col fault have equal important reference value in the memory fault prediction, and are factors that cannot be ignored. The multi-point fault of multiple storage arrays is usually reflected at the bank level, and the fault on the DQs line often appears at the device level. Based on the above principles, the above polynomial-based accumulation method is proposed to combine the memory fault prediction values of cell, row, col, bank, device and rank, and the influence of row and col is considered uniformly by multiplying d in the above combination process, while the influence of bank, device and rank is weighted by d^2, d^3 and d^4 respectively, so as to reflect that their contribution to the overall fault prediction is relatively small.

[0117] In summary, the above multi-accumulation weights are used to weight the fault levels in the prediction process, thereby improving the precision and recall rate of the prediction, and enhancing the memory fault prediction capability of the server management unit for the newly added memory of the server.

[0118] In some embodiments, FIG. 3 is an online memory failure prediction algorithm principle example diagram of an embodiment of the present application, and the determination of the prediction result according to the first formula and the second formula includes three periods. The first period is the period corresponding to the t-1 time, and the main content is to collect and record the CE history at the t-1 time, and calculate the memory failure prediction value at the t time. The prediction value can be used to predict whether the memory will fail at the t time at the t-1 time; the second period is the period corresponding to the t time, and the main content is to collect and record the CE history at the t time, and calculate the error by using the real CE number and the memory failure prediction value obtained at the t-1 time, as the prediction error at the t-1 time. Then, the prediction error at the t-1 time is calculated, and the memory failure prediction value at the t time is calculated, and this score is used to predict whether the memory will fail at the t+1 time at the t time; the third period is the period corresponding to the t+1 time, and the main content is to collect and record the CE history at the t+1 time, and calculate the error by using the real CE number and the memory failure prediction value obtained at the t time, as the prediction error at the t+1 time. Then, the prediction error at the t time is calculated, and the memory failure prediction value at the t+1 time is calculated, and this score is used to predict whether the memory will fail at the t+1 time at the t time; that is, the failure prediction value needs to be determined according to the failure prediction value at the t time and the real CE number at the t+1 time.

[0119] It should be noted that the above time corresponds to the prediction period in the above embodiment, t is used to indicate the time when the prediction in the prediction period starts, t-1 is the last time when the prediction starts, and 1 here refers to 1 prediction period unit, which can be hours or days, and then at each prediction time, the error data containing the correctable error sequence is collected first to expand (i.e. update) the correctable error sequence used by the multi-level learning prediction model, then according to the prediction result at the last time, the prediction error (equivalent to the first error sequence in the above embodiment) is calculated, and then the failure prediction value is calculated through the prediction error.

[0120] The above formula primarily focuses on a single cell, describing the algorithm's temporal prediction of potential failures in the smallest storage unit of memory. It's understandable that spatial failure characteristics also significantly impact memory failure occurrence, especially when frequent Complete Errors (CEs) occur in adjacent positions within the same column, increasing the likelihood of UCEs in that column; similarly, a row with numerous CEs also increases the probability of UCEs. These failures may stem from permanent failures in shared hardware circuitry (such as sense amplifiers) of rows or columns, or non-permanent failures caused by specific data patterns or repeated read operations from adjacent rows. Simply relying on rule matching to screen for such failures can be too coarse, sometimes leading to pages being incorrectly marked as permanently failed, potentially quickly exhausting redundant memory storage. Rule-based predictions in the spatial dimension often overlook the importance of the temporal dimension, while spatial failure characteristics also exhibit unique patterns over time.

[0121] In some embodiments, for higher-level spatial dimensions in memory, such as row, col, bank, device, and rank, time-related calculations and fault prediction values ​​can also be performed by slightly modifying the above-mentioned formulas. Figure 4 is a schematic diagram of a memory row fault according to an embodiment of this application. Taking the memory row fault shown in Figure 4 as an example, we focus on the i-th row in a certain bank. If two cells in this row have experienced CE (Complete Error) within the time interval, with 3 occurrences and 1 occurrence respectively, the algorithm considers that the row has experienced 2 CEs (here, we only focus on the number of cells that have experienced CEs, not the number of CEs on the cells). In the multi-level fault information filtering stage shown in Figure 1, a fault history record X is constructed with the row as the unit. t i =(X0) i X1 i ,...,X t-1 i ,X t i ), where X τ i = N. Based on this historical record, the algorithm in this application can perform historical fault correlation assessment, calculate row fault prediction value, and calculate row prediction error for this row. According to the above analysis, the fault prediction value calculated for the i-th row can be expressed using the formula: The above formula represents the prediction error and correlation in the row dimension, respectively.

[0122] In some embodiments, the memory failure prediction value in the (t+1)th prediction period can be used to predict whether there will be a failure in the (t+2)th prediction period.

[0123] In summary, through the above prediction method, through the online learning ability, compared with the traditional offline machine learning algorithm of the server, it can not only learn and update the model from the continuously generated CE data in real time by the BMC, without waiting for a large amount of data to accumulate and then using artificial batch processing and training. The instant learning feature makes the algorithm more suitable for running in the BMC environment with limited computing power and storage resources, and improves the maintenance efficiency of the server system.

[0124] In some embodiments, in the case where the M dimensions are divided into multiple levels, the higher the level of the dimension, the larger the granularity of the storage unit corresponding to the dimension, and in the case where the M prediction models are rule type models, the substrate management controller inputs the M first analysis results into the M prediction models to obtain M prediction values, comprising: the substrate management controller acquires a target sub-level included in a failure level in which the prediction target memory will occur an uncorrectable error, wherein the target sub-level corresponds to a target dimension in the M dimensions, and the target dimension corresponds to a target prediction model; the target prediction model predicts whether the target memory will occur an uncorrectable error at the target sub-level according to the first analysis result, to obtain a first prediction value, wherein the M prediction values include the first prediction value; the target prediction model determines a target probability that the target memory will occur an uncorrectable error at the target sub-level based on the first prediction value; and the target prediction model determines whether an uncorrectable error will occur based on the target probability.

[0125] In the above embodiment, the host unit can detect whether the target memory has occurred a correctable error. In the case where the host unit detects that the target memory has occurred a correctable error, the failure information of the target memory is acquired, and the physical address of the target memory is analyzed, and the analysis result is sent to the BMC. After receiving the analysis result, the BMC can determine that the target memory has occurred a correctable error, and acquire historical data. The historical data can be data within a predetermined time period before the current time. For example, it can be data within 1 hour before the current time, and it can also be data within 30 minutes before the current time. That is, the predetermined time period can be 1 hour, 30 minutes, and can also be 2 hours, 10 minutes, etc., which is not limited in the present application. It should be noted that the predetermined time period can be the nearest time period to the current time, for example, the last time period included in the predetermined time period can be the current time point.

[0126] In the above embodiment, the memory of the target server can include Channel, Dimm, Rank, Bank, and Row / Column, wherein Channel refers to the number of channels in which the memory controller is connected to the memory slot, Dimm refers to a dual in-line memory module, Rank refers to a memory Rank, which is a collection of a group of DRAM particles, these chips share the same data bus (DQs) and can be accessed by the memory controller at the same time, Bank refers to a memory Bank, which refers to a storage area divided internally in a DRAM chip, and a memory particle usually contains multiple Banks. And Row / Column refers to the physical address location in the memory. Therefore, the location information can include Dimm address, Rank address, Bank address, and Row / Column address, etc.

[0127] In the above embodiment, the structure diagram of the DRAM particle can refer to FIG. 5, as shown in FIG. 5, a plurality of cells form rows and columns, the rows and columns form a two-dimensional array, which is called a sub-array, that is, a memory sub-array, which is the most basic array. A plurality of sub-arrays form a bank, that is, a storage array, a plurality of banks form a device, that is, a storage particle. A plurality of devices form a rank, that is, a storage block. The connection diagram of the central controller and the dual in-line memory module can refer to FIG. 6, as shown in FIG. 6, the central controller is connected with the Memory Controller, the Memory Controller is connected with the DIMM through the channel, the DIMM includes a plurality of Ranks, each chip in the Rank includes a Bank, and the Bank includes Row / Column. Wherein, the connection diagram of the channel and the Rank can refer to FIG. 7, as shown in FIG. 7, the channel is connected with the DRAM included in the Rank through the data bus DQs, and each DRAM includes a plurality of Banks.

[0128] In the above embodiment, the fault level can include a memory sub-array level, that is, a sub-array level, a storage array level, that is, a bank level, a storage particle level, that is, a device level, and a storage block level, that is, a rank level. Different fault levels can include different target sub-levels, for example, when the fault level is the storage block level, the target sub-level can include the storage block level, the storage particle level, the storage array level, and the memory array level. When the fault level is the memory particle level, the target sub-level can include the memory particle level, the storage array level, and the memory sub-array level. When the fault level is the storage array level, the target sub-level includes the storage array level and the memory sub-array level.

[0129] In the above embodiment, the target algorithm can be used to predict the failure level of the target server memory that will cause uncorrectable errors, wherein the target algorithm can be a neural network model, and the neural network model can be trained to predict whether the target server memory will cause uncorrectable errors, the failure level of the target server memory that will cause uncorrectable errors, and the target confidence of the failure level that will cause uncorrectable errors. The neural network model can be a convolutional neural network model or other network model, which is not limited in the present application. For example, the target algorithm can include multiple sub-algorithms, each of which is used to predict whether a level of the target server memory will cause uncorrectable errors, and each sub-algorithm predicts a different level. For example, the target algorithm can be used to predict the failure level of the target server memory that will cause uncorrectable errors by determining a correctable error sequence of the target memory in the tth prediction period and determining a corresponding first error sequence of the target memory in the t-1th prediction period; wherein the correctable error sequence includes at least n correctable errors, the n correctable errors are determined by analyzing the memory failure data of the target memory in the tth prediction period, M levels are different levels obtained based on different storage unit granularities of the target memory, the higher the level, the larger the storage unit granularity, the storage unit of the high level includes multiple storage units of the low level, t and n are positive integers, and M is a positive integer greater than 1; the correctable error sequence and the first error sequence are input into the target algorithm (such as a multi-level learning prediction model) to obtain a failure prediction value of the target memory that will cause memory failure in the t+1th prediction period, wherein one or more memories include: the target memory, the multi-level learning prediction model includes M failure prediction sub-models, and the M failure prediction sub-models are prediction models corresponding to the M levels respectively. After obtaining the failure prediction value, the failure level of the failure can be determined according to the failure prediction value. Wherein, the correctable error sequence and the first error sequence are input into the multi-level learning prediction model to obtain a failure prediction value of the target memory that will cause memory failure in the t+1th prediction period, including: performing level classification on the correctable error sequence to obtain q correctable error subsequences respectively belonging to different levels, wherein q is a positive integer less than or equal to M; determining a target learning prediction sub-model of the multi-level learning prediction model corresponding to the level of each correctable error subsequence; inputting the correctable error subsequence and the first error sequence into the failure prediction sub-model to obtain a prediction value of the level corresponding to the correctable error subsequence; and fusing M prediction values of M levels of the target memory to obtain a fusion value. The M prediction values of the M levels of the target memory can be fused by weighted summation, and the value after weighted summation is determined as the failure score.In the above embodiments, it can be predicted according to the physical address whether the memory of the target server will have an uncorrectable error at the target sub-level, for example, it can be predicted according to the physical address whether the memory will have an uncorrectable error at the storage array level, whether it will have an uncorrectable error at the storage memory particle level, whether it will have an uncorrectable error at the memory sub-array level, to obtain a first prediction value. Wherein, Sub-array is a memory sub-array, which can be a storage unit subdivided within a DRAM Bank, set to organize and manage cells. The design of the sub-array helps to optimize the access speed and power consumption management of the memory. The first prediction value can include an uncorrectable error at the target sub-level or no uncorrectable error at the target sub-level.

[0130] In the above embodiments, the first prediction value can be converted into a Boolean variable, for example, when the first prediction value is that an uncorrectable error will occur at the target sub-level, output 1, and when the first prediction value is that an uncorrectable error will not occur at the target sub-level, output zero. After obtaining the first prediction value, the first prediction value can be converted into a target probability of an uncorrectable error at the target sub-level. According to the target probability, it is predicted whether the target server will have an uncorrectable error. For example, when the target probability is greater than or equal to a predetermined threshold, it is considered that an uncorrectable error will occur, and when the target probability is less than or equal to a predetermined threshold, it is considered that an uncorrectable error will not occur.

[0131] It should be noted that in the present application, prediction can be a speculation of the situation at a target time period after the current time, i.e. a future time. For example, it can be predicted according to the position information whether the memory of the target server will have an uncorrectable error at a certain time in the future. It can also be predicted according to the target algorithm whether the memory of the target server will have an uncorrectable error at a certain time in the future, and the level of the uncorrectable error.

[0132] In some embodiments, the target prediction model predicts whether the target internal storage at the target sub-level will have uncorrectable errors according to the first analysis result, to obtain a first prediction value, including: in the case that the target sub-level includes the storage array level, the target prediction model determines a second address included in the first analysis result, wherein the second address is an address of a storage array in the same memory block that has correctable errors, and predicts whether the target internal storage at the target sub-level will have uncorrectable errors based on a first number of addresses belonging to the same target storage array included in the second address, to obtain the first prediction value; in the case that the target sub-level includes the memory particle level, the target prediction model determines a second number of target storage arrays in the same memory particle that have correctable errors based on the first analysis result, and a third number of target storage arrays that have correctable errors, and predicts whether the target internal storage at the target sub-level will have uncorrectable errors based on the second number and the third number, to obtain the first prediction value; in the case that the target sub-level includes the memory sub-array level, the target prediction model determines a third address of a memory sub-array in the same storage array that has correctable errors based on the first analysis result, and predicts whether the internal storage of the target server at the target sub-level will have uncorrectable errors based on a fourth number of storage units included in the third address, to obtain the first prediction value.

[0133] In the present embodiment, when the target sub-level includes the storage array level, the memory failure prediction algorithm at the Bank level aims to predict whether UCE occurs by analyzing the number of CEs and their spatial distribution on the entire Rank of the server memory system. It can be assumed that (C) represents the set of all Channels in the server DRAM system, (D) represents the set of all Dimms in a certain Channel, (R) represents the set of all Ranks in a certain Dimm, and (B) represents the set of all Banks in a certain Rank. DQs(c, d, r, b) represents the number of different DQs on which a CE occurs in the historical record, in a specific Channel (c ∈ C), Dimm (d ∈ D), Rank (r ∈ R) and Bank (b ∈ D). It needs to be noted that DQs(c, d, r, b) does not represent the total number of CE events. For example, if 5 CEs have occurred on a DQs, the algorithm of the present application will record DQs(c, d, r, b) = 1, not 5. Therefore, the second address of the storage array bank in the same memory block Rank that sends correctable errors can be determined from the position information, and the storage array can come from different devices. Whether the target internal storage of the target server at the target sub-level will have uncorrectable errors is predicted according to the first number of addresses belonging to the same target storage array included in the second address.

[0134] In the above embodiment, FIG. 8 is a schematic diagram of a storage area level fault prediction according to an embodiment of the present application. As shown in FIG. 8, a Rank includes 16 x4 Devices, and each Device includes 4 Banks. In this memory structure, all Banks within each Device share 4 DQs. Each Bank is further divided into 4 sub-arrays. When performing read / write operations, each sub-array contributes data on one DQ, respectively. Therefore, each Device obtains 4 bits at a time when reading data from a Bank, and the 16 Devices together constitute a 64-bit Rank read operation. It should be noted that each read operation is parallel for the Device, and data is read from the same Bank of all Devices at the same time, so the Bank here refers to the Rank level Bank rather than the Device level Bank.

[0135] In the above embodiment, continuing to refer to FIG. 8, the second address can include DQs1, DQs35, and DQs60. Among them, the addresses belonging to the same target storage array can include DQs1 and DQs60, and at this time, the target storage array is Bank0.

[0136] In the above embodiment, the storage array level fault in the memory in the target server can be monitored and diagnosed according to the storage array address, the accuracy of predicting the storage array level fault is improved, and the accuracy of predicting whether the target memory will occur uncorrectable error is improved.

[0137] In the above embodiment, in the case where the target sub-level includes the memory particle level, i.e., the device level, the second number of banks in the device in which correctable errors occur and the third number of banks in which correctable errors occur can be determined, and the prediction is performed according to the second number and the third number.

[0138] Figure 9 is a schematic diagram of device-level failure prediction according to an embodiment of the present application. As shown in Figure 9, a memory device can include multiple banks, such as bank 0, bank 1, bank 2, and bank 3. Device-level memory failure prediction can focus on capturing potential failures on a single memory device on the target server. For example, it can monitor whether a CE occurs on different banks of the same device (it is noted that the same device includes the same channel, the same dimm, and the same rank). To this end, (B) can be defined as a set of all banks on a device, and CE(b) represents the number of CEs that have occurred on a particular bank b. According to the occurrence of CEs on banks belonging to the same device, it can be predicted whether the target memory has a memory device-level failure.

[0139] In the above embodiment, by predicting whether the target memory has an uncorrectable error at the device level according to the number of banks in which a CE occurs in the same device and the number of CEs issued in the bank, it is focused on identifying the impact of failures within the device on uncorrectable errors, and the accuracy of predicting uncorrectable errors is improved.

[0140] In the above embodiment, each bank can include multiple memory sub-arrays, and memory sub-array-level failure is more concerned about the scope of failure impact than device-level failure or bank-level failure. The sub-array-level failure prediction algorithm aims to capture more fine-grained memory failure patterns. A sub-array is a smaller unit in a memory bank, consisting of a series of rows and columns. It is the smallest unit in a memory array that can be identified by DQs, and can provide the most accurate failure localization capability. In sub-array-level prediction, if a CE occurs on the same device, the same bank, and the same DQs, it can be concluded that the CE occurs in the same sub-array. (S) is defined as a set of all sub-arrays in a bank, and ADDR(s) is a function representing the number of different addresses on which a CE has occurred in a particular sub-array (s∈S). It is noted that the number of different addresses of the CE refers to how many cells in s have occurred.

[0141] In some embodiments, the first prediction value is determined based on a first number of addresses included in the second address that belong to the same target storage array, and whether an uncorrectable error will occur in the target sub-level of the target in-situ is predicted, including: in a case where the first number is greater than or equal to a first threshold value, determining that the first prediction value includes that an uncorrectable error will occur in the target sub-level of the target in-situ; in a case where the first number is less than the first threshold value, determining that the first prediction value includes that an uncorrectable error will not occur in the target sub-level of the target in-situ.

[0142] In the embodiment, the determination rule of the Device-level fault prediction algorithm for making the UCE prediction can be: CE(b1)≥1∧CE(b2)≥1, b1, b2∈B, b1≠b2. That is, if there are at least two different Banks on the same Device, each of which records a CE event and more than one CE event, and each Bank has occurred at least once, the determination rule will predict that the Device has a high risk of UCE. Although the occurrence of CE in the server memory system can be random, the occurrence of CE can also imply that there are potential problems in some hardware circuits, which can eventually lead to UCE. Although the memory ECC mechanism can correct single-bit errors, and even some advanced memory can correct double-bit errors. However, if 2 or more errors occur in the same Bank in the same Rank, this is a dangerous signal from a statistical point of view. This indicates that the probability of failure of the Bank has increased significantly, and CE is more likely to be caused by hardware circuit failure. If not intervened, the system is likely to encounter UCE, resulting in serious consequences. Therefore, when the first number is greater than or equal to 2, it can be determined that the first prediction result includes that an uncorrectable error will occur in the bank level of the target server. It should be noted that the first threshold value is 2, which is only an example, and the first threshold value can also be other values. The first threshold value can be a value determined according to statistics, and the present application does not limit this. For example, it can also be set to 3, 4, etc.

[0143] Continuing to refer to FIG. 8, it can be seen that there are two Banks affected by CE: Bank1 of Device8 has occurred once, and Bank0 of Device0 and Device15 has occurred once. Therefore, the DQs(c, d, r, b) of Bank1 is 1, and the DQs(c, d, r, b) of Bank0 is 2. Among them, Bank0 satisfies the condition of DQs(c, d, r, b)≥2, so it can be judged that the Dimm will have UCE at the Bank level.

[0144] In the above embodiments, the way of determining whether a memory will experience a storage region level failure at a storage array level in the memory by using the first number of addresses in the addresses of the storage arrays in which the correctable errors occur in the same storage block belonging to the same target storage array can make the prediction more fine and targeted. Not only the number of error occurrences is considered, but also the distribution pattern of errors across the entire Rank of the memory space is concerned. By identifying the concentrated trend of CEs on multiple DQs lines within a specific Bank, potential local hardware problems can be revealed, thus providing a more accurate failure prediction.

[0145] In some embodiments, predicting whether the target in-memory storage will experience uncorrectable errors at the target sub-level based on the second number and the third number to obtain a first prediction value includes: in a case where the second number is greater than or equal to a second threshold value and the third number is greater than or equal to a third threshold value, determining that the first prediction value includes that the target in-memory storage will experience uncorrectable errors at the target sub-level; in a case where the second number is less than the second threshold value and / or the third number is less than the third threshold value, determining that the first prediction value includes that the target in-memory storage will not experience uncorrectable errors at the target sub-level.

[0146] In the present embodiment, in a case where it is determined that there are at least two storage regions in a device in which CEs occur, and the second number of CEs occurring in each storage region in which CEs occur is greater than a second threshold value, it can be determined that the target in-memory storage will experience uncorrectable errors at a storage grain level, otherwise, it is considered that the target in-memory storage will not experience uncorrectable errors at the storage grain level.

[0147] In the above embodiments, (B) can be defined as a set of all Banks on a device, and the function CE(b) represents the number of CEs that have occurred on a specific Bank b. When the prediction rule E(b1)≥1∧CE(b2)≥1, b1, b2∈B, b1≠b2 is met, it is predicted that the device has a high risk of UCE. For example, if at least two different Banks on the same device each record one or more than one CE event, and at least one CE occurs in each Bank, the determination rule will predict that the device has a high risk of UCE. Referring to FIG. 9, as shown in FIG. 9, a device includes four Banks, and each Bank is connected to a Bank selector, i.e., a Bank Select, through DQs. The selector determines which DQs of the Banks to enable according to the Bank ID in the DRAM address. In this example, if CEs are monitored on DQ0 of Bank1 and Bank2, the above prediction rule is met, and it can be considered that the device has potential unreliability. Therefore, the Dimm to which the device belongs may experience UCE in the future.

[0148] In the above embodiments, the prediction of Device-level failure focuses on identifying a widespread failure impact within a Device. From a statistical significance analysis, a correctable error (CE) within a single Bank can be merely due to random noise or a transient soft error, which does not change even if the Bank has multiple occurrences of CEs. However, if two or more Banks within the same Device have recorded CE events, this can no longer be a coincidence but a sign of the existence of a systematic failure. This situation indicates that the failure has spread beyond a single local area and can involve functional areas of the Device, especially those circuits shared by multiple Banks. It is worth noting that the Device-level failure warning surpasses the Bank-level failure in severity because it reveals a more concentrated failure area, indicating that the reliability of the entire Device is under threat. Therefore, by predicting whether a memory device-level failure is predicted, the accuracy of predicting uncorrectable errors can be improved.

[0149] In some embodiments, predicting whether an uncorrectable error will occur in the target sub-level of the target memory based on the fourth number of memory cells included in the third address includes: in a case where the fourth number is greater than or equal to a fourth threshold value, determining that the first prediction value includes that an uncorrectable error will occur in the target sub-level of the target memory; and in a case where the fourth number is less than the fourth threshold value, determining that the first prediction value includes that an uncorrectable error will not occur in the target sub-level of the target memory.

[0150] Each Bank can include multiple memory sub-arrays, and memory sub-array level failure is more concerned about the scope of failure impact than device level failure or Bank level failure. The sub-array level failure prediction algorithm aims to capture more fine-grained memory failure patterns. A sub-array is a smaller unit in a memory Bank, which is composed of a series of rows and columns. It is the smallest unit in a memory array that can be identified by DQs, and can provide the most accurate failure localization capability. In sub-array level prediction, if the CE occurs on the same device, the same bank, and the same DQs, it can be inferred that the CE occurs in the same sub-array. Define (S) as the set of all sub-arrays in a Bank, and ADDR(s) as a function representing the number of different addresses on which CE has occurred in a particular sub-array (s∈S). It should be noted that the number of different addresses of CE refers to how many memory cells have occurred in s. When ADDR(s)≥2, it can be determined that the memory of the target server has a memory sub-array level failure. That is, the fourth threshold value can be 2. It should be noted that the fourth threshold value can also take other values, such as 3, 4, and the fourth threshold value can be a value calculated according to statistics, which is not limited in the present application.

[0151] In the above embodiment, if at least two CEs are monitored in a specific sub-array in the same Bank and occur on different cells, the algorithm will predict that this Bank is at high risk of UCE. It can be inferred that the UCE risk of the entire Dimm including the Bank also increases accordingly. FIG. 10 is a schematic diagram of memory sub-array level failure prediction according to an embodiment of the present application. As shown in FIG. 10, the diagram discloses the internal structure of a Bank, which is composed of 4 sub-arrays, each of which corresponds to a DQs. According to the above rules, the sub-array connected with DQs0 in FIG. 10 records two CE events occurring on different cells, so it can be inferred that the Bank and the Dimm where it is located have a high probability of CE.

[0152] In the above embodiments, in the memory architecture at the sub-array level, each cell is the basic unit constituting the memory array, which is composed of a storage capacitor and an access transistor. When a voltage is applied to the word line, the access transistor is activated, allowing data to be read or written to the storage capacitor through the bit line. Therefore, the memory cell is the core element to realize the data storage function. At the microscopic level of the sub-array, the occurrence of CE is no longer randomly distributed, but may be concentrated in a particular location, and this concentration form more obviously indicates the occurrence of potential failure. Satisfying the above rule, i.e., at least two times of CE occurring on different cells in the same sub-array, may indicate the failure of the word line or the bit line, or the problem of affecting the local row buffer and other shared circuits. The occurrence of this failure mode is far more serious than the failure prediction at the Bank level and the Device level. At the sub-array level, since the failure area is more concentrated, it may be a precursor of larger-scale failure or direct evidence of the degradation of internal fine circuits of the memory. The sub-array level failure prediction algorithm can effectively identify this error mode and detect and solve potential failure points at an early stage.

[0153] In some embodiments, when the M prediction models are offline models, the substrate management controller inputs the M first analysis results into the M prediction models to obtain M prediction values, including: the substrate management controller inputs the M first analysis results into the M offline models to obtain M prediction values, wherein the offline model is obtained by training using training sample data, the training sample data includes that the sample internal memory occurs correctable errors in M dimensions, and the label of the sample internal memory, the label of the sample internal memory is whether the sample internal memory actually occurs uncorrectable errors.

[0154] The above offline model can be a neural network model or a machine learning model, and M prediction models are trained using historical data of target memory failures as training samples, so as to make predictions according to the results.

[0155] In some embodiments, the substrate management controller fuses the M prediction values to obtain a fused value, including: the substrate management controller obtains M weight values corresponding to M dimensions; the substrate management controller performs weighted summation on the M weight values and the M prediction values to obtain the fused value.

[0156] In some embodiments, the fusion manner is updated to obtain an updated fusion manner, including at least one of the following: obtaining the number of times of correctable errors occurring in each level in the N levels, in a case where the number of times of correctable errors occurring in a target level in the N levels exceeds a preset number threshold, increasing the weight value corresponding to the target level by a preset value; otherwise, decreasing the weight value corresponding to the target level by a preset value; obtaining the number of storage units of a low level in a high level that have correctable errors in a preset time range, in a case where the number exceeds a preset number threshold, increasing the weight value corresponding to the high level by a preset value; otherwise, decreasing the weight value corresponding to the high level by a preset value.

[0157] FIG. 11 is a fusion manner updating flowchart according to an embodiment of the present application, as shown in FIG. 11, the optional updating flow is as follows:

[0158] S1101: initialize the fusion algorithm of the fusion logic unit, such as using a linear weighting algorithm, update the fusion strategy unit (which stores the latest fusion strategy at the current time);

[0159] S1102: the fusion logic unit obtains the fusion strategy in the fusion strategy unit, calculates the current input prediction result, judges through the prediction decision unit to obtain the prediction result at the current time, and stores it in the memory historical fault result unit, reads the prediction result at the last time from the memory historical fault result unit, wherein the prediction result at the current time is judged by setting a preset threshold, in a case where the fusion value is greater than or equal to the preset threshold, the target memory is determined to have occurred uncorrectable error, in a case where the fusion value is less than the preset threshold, the target memory is determined to have not occurred uncorrectable error;

[0160] S1103: the fusion strategy updating unit re-calculates the fusion strategy according to the prediction result at the last time and the real result at the current time, and outputs it to the strategy selection unit, for example: in a case where the number of times of correctable errors occurring in a target level in the N levels exceeds a preset number threshold, the weight value corresponding to the target level is increased by a preset value; otherwise, the weight value corresponding to the target level is decreased by a preset value, or, in a case where the number of storage units of a low level in a high level that have correctable errors in a preset time range exceeds a preset number threshold, the weight value corresponding to the high level is increased by a preset value; otherwise, the weight value corresponding to the high level is decreased by a preset value;

[0161] S1104: alternatively, the output of the strategy selection unit is from the fusion strategy updating unit or an external strategy file according to the state of the strategy control signal, wherein the external strategy file can be a json format file or other general text file, and the import mode includes but is not limited to serial port of BMC or external Flash reading and writing BMC;

[0162] S1105: The output according to the strategy selection obtains a new fusion strategy, and is stored in the fusion strategy unit in the figure, and thus one round of fusion strategy updating is completed;

[0163] S1106: The next moment fusion logic unit receives a new prediction result, and goes to S1102, and the above process is repeatedly cycled.

[0164] In some embodiments, FIG. 12 is a fault prediction system workflow diagram one according to embodiments of the application, as shown in FIG. 12, the system mainly includes a host unit and a BMC unit, wherein the optional working process of the host unit and the BMC unit is as follows:

[0165] Host unit:

[0166] S1201, when the target memory fails (correctable error), the modular electronic control unit detects the failure of the target memory, at this time, the modular electronic control unit triggers an SMI interrupt to the interrupt control management module;

[0167] S1202, record the failure information of the target memory to the MSR and CSR registers in the CPU internal;

[0168] S1203, the interrupt control management module triggers the first fault analysis module to obtain the physical address of the target memory from the register, and the first fault analysis module obtains the physical address from multiple levels of analysis to obtain multiple first analysis results;

[0169] S1204, in the POST stage of system startup, the first fault analysis module reports the multiple first analysis results to the BMC unit through the first two interfaces;

[0170] BMC unit:

[0171] S1205, the data storage module receives and stores the multiple first analysis results sent by the first fault analysis module;

[0172] S1206, pre-process the first analysis results stored in the data storage module to obtain input data for a multi-dimensional prediction model;

[0173] S1207, inference calculation is performed through the multi-dimensional prediction model;

[0174] S1208, input the inference result of the multi-dimensional prediction model into the fusion module for comprehensive decision to obtain a final prediction result.

[0175] In this embodiment, a memory fault prediction method is provided, and FIG. 13 is a flowchart of a memory fault prediction method according to embodiments of the application, as shown in FIG. 13, the flowchart includes the following steps:

[0176] Step S1302, in the case of a correctable error of the target memory, the modular electronic control unit of the host unit sends the detected fault information to the register of the host unit; the register stores the fault information;

[0177] The modular electronic control unit can be an IMC controller, which is configured to detect fault information of the target memory, which can be a single-bit error (correctable by ECC logic) or a multi-bit error (causing ECC failure); the register can be an MSR / CSR register, which is configured to store the fault information detected by the modular electronic control unit, such as the physical address of the target memory that has failed; when the target memory has a correctable error, the modular electronic control unit detects the fault information of the target memory and records the fault information of the target memory in the MSR and CSR registers inside the CPU.

[0178] Step S1304, the second fault analysis module of the baseboard management controller obtains the physical address from the fault information of the register through the second interface, and analyzes the physical address in M dimensions to obtain M second analysis results, where M is an integer greater than or equal to 2, and the M dimensions are obtained based on different storage unit granularities of the target memory, and the second fault analysis result is used to indicate that the target memory has a correctable error in the corresponding dimension;

[0179] The second fault analysis module is configured to analyze the physical address of the target memory that has a correctable error, and the second fault analysis module can analyze the physical address of the target memory from multiple dimensions, where the multiple dimensions can be storage dimensions of the target memory, such as a minimum storage unit (cell), a storage row (row), a storage column (col), a storage array (bank), a storage block (rank), a storage path (DQs), a memory particle (device), a memory stick (diMM), a memory channel (channel), etc.; the second interface can be a PECI interface, through which the storage information in the host unit can be transmitted to the BMC unit; in the case of a correctable error of the target memory, the host unit obtains the fault information of the target memory and stores it in the register inside the host unit, and the fault information includes the physical address of the target memory; the second fault analysis module in the BMC obtains the physical address of the target memory through the second interface, and analyzes the physical address from multiple dimensions to obtain multiple second analysis results.

[0180] Step S1306, the baseboard management controller obtains M second analysis results from the second fault analysis module, inputs the M second analysis results into M prediction models corresponding to the M dimensions, and obtains M prediction values;

[0181] In step S1308, the substrate management controller fuses the M predicted values to obtain a fused value, wherein the fused value is used to predict whether the target memory will have an uncorrectable error.

[0182] Through the above steps, the joint host unit and the BMC work together to realize the automatic processing process of the whole link from target memory fault detection to fault state information recording, to memory fault location resolution, to synchronization of the fault location resolution result to the BMC unit, to processing and prediction of the fault location resolution result, solve the problem of weak memory fault prediction performance in the related art, and improve the memory fault prediction performance.

[0183] At the same time, by predicting the probability of the target memory having an uncorrectable error through the BMC, each server has the function of memory fault prediction, thereby eliminating the need to rely on an additional inference server, reducing the risk of prediction function paralysis caused by inference server failure, improving the reliability of the prediction function, and avoiding the deployment of inference node servers, saving a lot of manpower and material resources, and reducing system deployment overhead.

[0184] In some embodiments, in the case that the second fault resolution module cannot obtain the physical address from the register, the first fault resolution module of the host unit obtains the physical address of the target memory from the register and resolves the physical address in M dimensions to obtain M first resolution results, wherein the first resolution result is used to indicate that the target memory has a correctable error in the corresponding dimension; the substrate management controller obtains the M first resolution results, inputs the M first resolution results into M prediction models corresponding to the M dimensions to obtain M predicted values; the substrate management controller fuses the M predicted values to obtain a fused value, wherein the fused value is used to predict whether the target memory will have an uncorrectable error; the second fault resolution module cannot obtain the physical address from the register, including: within a preset time length of host unit downtime restart, the second fault resolution module cannot obtain the physical address from the register.

[0185] In some embodiments, the first fault resolution module of the host unit obtains the physical address of the target memory from the register, including: the modular electronic control unit of the host unit sends an interrupt signal to the interrupt control management module in the case that the second interface cannot send the physical address to the second fault resolution module; the interrupt control management module triggers the first fault resolution module to obtain the physical address from the fault information stored in the register in the case that the interrupt signal is received.

[0186] In some embodiments, the data storage module of the baseboard management controller acquires the M first analysis results from the first fault analysis module through the first interface and stores the M first analysis results; and the data storage module of the baseboard management controller acquires the M second analysis results from the second fault analysis module and stores the M second analysis results.

[0187] In some embodiments, the baseboard management controller acquires the M second analysis results from the second fault analysis module, inputs the M second analysis results into the M prediction models corresponding to the M dimensions to obtain M prediction values, including: in the case that the M prediction models are online models, the baseboard management controller inputs the M second analysis results into the M prediction models to obtain the M prediction values, including: in the case that the target memory has a correctable error in the t th prediction period, the baseboard management controller acquires a correctable error sequence of the target memory in the t th prediction period from the data storage module, wherein the correctable error sequence includes analysis results obtained by the second fault analysis module analyzing the physical address of the target memory in the t th prediction period, and the correctable error sequence includes the M second analysis results; the baseboard management controller determines a first error sequence corresponding to the target memory in the t-1 th prediction period; and the baseboard management controller inputs the correctable error sequence and the first error sequence into the M prediction models to obtain the M prediction values.

[0188] In some embodiments, in the case that the M dimensions are divided into multiple levels, the higher the level of the dimension, the larger the granularity of the storage unit corresponding to the dimension, and in the case that the M prediction models are rule models, the baseboard management controller inputs the M second analysis results into the M prediction models to obtain M prediction values, including: the baseboard management controller acquires a target sub-level included in a fault level in which the target memory is predicted to have an uncorrectable error, wherein the target sub-level corresponds to a target dimension among the M dimensions, and the target dimension corresponds to a target prediction model; the target prediction model predicts whether the target memory in the target sub-level will have an uncorrectable error according to the second analysis result to obtain a second prediction value, wherein the M prediction values include the second prediction value; the target prediction model determines a target probability that the target memory in the target sub-level will have an uncorrectable error based on the second prediction value; and the target prediction model determines whether the uncorrectable error will occur based on the target probability.

[0189] In some embodiments, when the M prediction models are offline models, the substrate management controller inputs the M first analysis results into the M prediction models to obtain M prediction values, including: the substrate management controller inputs the M second analysis results into the M offline models to obtain M prediction values, wherein the offline models are trained using training sample data, and the training sample data includes occurrence of a correctable error in the sample and a label of the sample, and the label of the sample is whether the sample actually occurs an uncorrectable error.

[0190] It should be noted that the optional implementation method of obtaining the prediction value through the prediction model can refer to the memory failure prediction method provided in the above embodiments.

[0191] In some embodiments, Figure 14 is a second workflow diagram of a failure prediction system according to an embodiment of the present application, as shown in Figure 14, the system mainly includes a host unit and a BMC unit, wherein the optional working processes of the host unit and the BMC unit are as follows:

[0192] S1401, when the target memory fails (correctable error), the modular electronic control unit detects the failure of the target memory;

[0193] S1402, record the failure information of the target memory to the MSR and CSR registers in the CPU;

[0194] BMC unit:

[0195] S1403, the BMC unit collects the physical address of the target memory stored in the register of the host unit through the second interface;

[0196] S1404, the second failure analysis obtains a plurality of second analysis results from the physical address obtained from the plurality of levels, and stores the plurality of second analysis results in a data storage module;

[0197] S1405, pre-processing the second analysis results stored in the data storage module to obtain input data for the multi-dimensional prediction model;

[0198] S1406, inference calculation is performed through the multi-dimensional prediction model;

[0199] S1407, input the inference result of the multi-dimensional prediction model into the fusion module for comprehensive decision to obtain the final prediction result.

[0200] In some embodiments, Figure 15 is a third workflow diagram of a failure prediction system according to an embodiment of the present application, as shown in Figure 15, the system mainly includes a host unit and a BMC unit, wherein the optional working processes of the host unit and the BMC unit are as follows:

[0201] S1501, when the target memory fails (correctable error), the modular electronic control unit detects the failure of the target memory, at this time, the modular electronic control unit triggers an SMI interrupt to the interrupt control management module;

[0202] S1502, record the failure information of the target memory to the MSR and CSR registers in the CPU;

[0203] S1503, the interrupt control management module triggers the first fault analysis module to obtain the physical address of the target memory from the register, and the first fault analysis module obtains the physical address from multiple levels of analysis to obtain multiple first analysis results;

[0204] S1504, in the POST stage of system startup, the first fault analysis module reports the multiple first analysis results to the BMC unit through the first interface;

[0205] BMC unit:

[0206] S1505, the data storage module receives and stores the multiple first analysis results sent by the first fault analysis module, and the BMC unit collects the physical address of the target memory stored in the register of the host unit through the second interface;

[0207] S1506, the second fault analysis obtains the physical address from multiple levels of analysis to obtain multiple second analysis results, and stores the multiple second analysis results in the data storage module;

[0208] S1507, preprocessing the first analysis result and the second analysis result stored in the data storage module to obtain input data for the multi-dimensional prediction model;

[0209] S1508, inference calculation is performed through the multi-dimensional prediction model;

[0210] S1509, input the inference result of the multi-dimensional prediction model into the fusion module for comprehensive decision to obtain the final prediction result.

[0211] In the embodiment, a fault prediction system is provided, and Fig. 16 is a schematic diagram of an architecture of the fault prediction system according to the embodiment of the present application. As shown in Fig. 16, the system comprises a host unit including a first fault analysis module configured to, in a case where a correctable error occurs in a target memory, acquire a physical address of the target memory and analyze the physical address in M dimensions to obtain M first analysis results, where M is an integer greater than or equal to 2; and a baseboard management controller configured to acquire the M first analysis results from the host unit, input the M first analysis results into corresponding prediction models of a multi-dimensional prediction model to obtain M prediction values, where the multi-dimensional prediction model comprises M prediction models corresponding to the M dimensions; and further configured to fuse the M prediction values by a fusion strategy to obtain a fusion value, where the fusion value is used to represent a probability of an uncorrectable error occurring in the target memory.

[0212] The host unit is mainly configured to detect memory faults, record fault states, analyze fault positions, and provide a fault data access interface function. The host unit mainly comprises a first fault analysis module, which can analyze the detected faults from multiple dimensions. In a case where a correctable error occurs in a target memory, the physical address of the target memory is analyzed from multiple levels by the first fault analysis module of the host unit, and multiple first analysis results can be obtained.

[0213] The baseboard management controller (BMC) is mainly configured to collect memory fault data, process prediction data, and fuse multi-dimensional model fault prediction. Based on the multiple first analysis results, the BMC can predict the probability of an uncorrectable error occurring in the target memory in the corresponding dimension from different dimensions, fuse the obtained multiple prediction results according to a fusion strategy, and obtain the probability of an uncorrectable error occurring in the target memory. For example, in a case where a correctable error occurs in a target memory A, the physical address of the target memory A is analyzed by the first fault analysis module to obtain a corresponding minimum storage unit cell21 and a corresponding storage row row2 of the target memory A. The analysis results are input into the prediction model of the minimum storage unit and the prediction model of the storage row, respectively, to obtain the probability p1 of an uncorrectable error occurring in the minimum storage unit cell of the target memory A and the probability p2 of an uncorrectable error occurring in the storage row. According to the fusion strategy, p1 and p2 are fused to obtain the probability P of an uncorrectable error occurring in the target memory A.

[0214] The multi-dimensional prediction model comprises multiple models of different dimensions. Fig. 17 is a schematic diagram of an architecture of the multi-dimensional prediction model according to the embodiment of the present application. As shown in Fig. 17, the prediction model can be divided into two levels:

[0215] One level refers to an algorithm level, which is represented by a multi-dimensional algorithm fusion table in FIG. 17. The multi-dimension here refers to the use of multiple prediction algorithms, which can include online algorithms, offline algorithms, and rule-based algorithms. Among them, the online algorithm refers to an online machine learning algorithm, which adjusts and updates the prediction parameters in real time according to the input; the offline algorithm refers to a machine learning model obtained through offline training. This type of algorithm model is usually trained and parameter-optimized by a dedicated training node server according to the training set of the parsed result data; the rule-based algorithm refers to a prediction model constructed according to the prediction rules. The typical algorithm is to determine the prediction result by whether the number of correctable memory errors occurring in a period of time exceeds a certain threshold.

[0216] Another level of multi-dimensional prediction model is mainly related to the physical composition structure of the memory medium, which is represented by a multi-dimensional level fusion table in FIG. 17. For example, the physical composition related to the memory medium is composed of structures at levels of the smallest storage unit cell, storage row, storage column, storage array bank, storage device, and storage block rank from micro to macro. In the multi-dimensional prediction model mentioned in this embodiment, the "multi-dimension" refers to considering not only the cell-level fault prediction model, but also the row, column, bank, rank, and device-level fault prediction model when performing memory failure prediction. By coordinating the prediction models of these dimensions, the prediction performance is improved.

[0217] It should be noted that multi-dimensional level fusion and multi-dimensional algorithm fusion are not in an opposite relationship. For example, the rule-based algorithm is not limited to determining the number of correctable memory errors occurring in a period of time for each cell. It can also consider the number of correctable memory errors occurring in a period of time for each row.

[0218] By predicting the probability of the target memory of the BMC occurring uncorrectable errors, each server has the function of memory failure prediction, thereby eliminating the need to rely on an additional inference server, reducing the risk of prediction function paralysis caused by inference server failure, improving the reliability of the prediction function, and avoiding the deployment of inference node servers, saving a lot of manpower and resources, and reducing system deployment overhead.

[0219] In some embodiments, the host unit further includes a modular electronic control unit, an interrupt control management module, and a register. The modular electronic control unit is configured to send the detected fault information to the register and send an interrupt signal to the interrupt control management module in the case of detecting that the target memory occurs correctable errors. The interrupt control management module is configured to trigger the first fault analysis module to obtain the physical address from the fault information stored in the register in the case of receiving the interrupt signal.

[0220] The register can be an MSR / CSR register configured to store fault information detected by the modular electronic control unit, such as a physical address of a target memory that has failed, and the like; the modular electronic control unit can be an IMC controller configured to detect fault information of a target memory, which can be a single-bit error (correctable by ECC logic) or a multi-bit error (causing ECC failure); the interrupt control management module can be a UBOX (a module in the CPU for interrupt control management); when a correctable error occurs in the target memory, the modular electronic control unit detects the fault information of the target memory, at which time the modular electronic control unit triggers an SMI interrupt to the interrupt control management module and records the fault information of the target memory in the MSR and CSR registers inside the CPU; in the case where the interrupt control management module receives an interrupt signal, the interrupt control management module triggers the first fault analysis module to obtain the physical address of the target memory from the register, thereby completing the physical address analysis of the target memory.

[0221] In some embodiments, the host unit further comprises: the host unit further comprises: a first interface, one end of the first interface is connected to the first fault analysis module, and the other end is connected to the data storage module of the baseboard management controller; the first interface is used to transmit the M first analysis results in the first fault analysis module to the data storage module, so as to record the M first analysis results in the data storage module.

[0222] The data storage module can be configured to store the analysis result of the physical address of the target memory, and the first interface can be an eSPI interface, which is connected to the first fault analysis module of the host unit and the data storage module of the BMC respectively, and through the first interface, the first analysis results of the target memory obtained by the first fault analysis module of the host unit are transmitted to the BMC and stored in the data storage module.

[0223] In some embodiments, the baseboard management controller further comprises: the baseboard management controller further comprises: a data storage module configured to record the M first analysis results; a multi-dimensional prediction module connected to the data storage module, the multi-dimensional prediction module comprising M prediction models, configured to obtain the M first analysis results from the data storage module, input the M first analysis results into the corresponding prediction models respectively, and predict the probability of the target memory having an uncorrectable error at the corresponding level through the prediction models to obtain M prediction values; the baseboard management controller further comprises: a fusion module configured to fuse the M prediction values based on a fusion strategy to obtain a fusion value.

[0224] The data storage module is configured to store the analysis result of the target memory physical address. The multi-dimensional prediction model can include a plurality of dimensional prediction models, such as online prediction models, offline prediction models, rule matching prediction models, and the like, or a plurality of prediction models of different levels of faults, and the like. Different memory fault prediction models can be embedded in the BMC of each server to match different configuration types (such as different configurations of memory bank models, capacities, batches, and the like) of the servers, so that the prediction model is flexibly and accurately matched with the configuration of the server, better prediction performance is achieved, and at the same time, different types of prediction algorithms and different dimensional fault information of the memory are considered in the prediction, the value of the available fault information of the memory is fully tapped, the utilization rate of the fault information is improved, and the dimension of the memory fault prediction is effectively expanded. The fusion module is configured to fuse a plurality of results output by the multi-dimensional prediction model. The output results of the multi-dimensional prediction model are fused by a suitable fusion strategy, the accuracy of the model prediction is effectively improved, and the memory fault prediction performance is improved.

[0225] In some embodiments, the data storage module and the multi-dimensional prediction module of the substrate management controller further include a data processing module configured to obtain a first analysis result from the memory fault data unit and pre-process the first analysis result to obtain a processed first analysis result.

[0226] The data processing module is configured to preliminarily analyze the analysis result obtained from the data storage module. The data processing module includes a plurality of pre-processing methods, such as rejecting abnormal data, completing missing data, classifying data, and labeling data, and the like. The quality and availability of the analysis result are improved by pre-processing the analysis result of the target memory physical address, so as to help improve the accuracy and efficiency of the model.

[0227] In some embodiments, the N levels include: a minimum storage unit, a storage row, a storage column, a storage array, a storage block, a storage channel, a storage grain, a memory bank, and a memory channel.

[0228] In the embodiment, another memory fault prediction system is provided, and Fig. 18 is a schematic diagram of architecture of a fault prediction system according to the embodiment of the application. As shown in Fig. 18, the system comprises a host unit, a baseboard management controller. The host unit comprises a modular electronic control unit, a register, and a second interface. The modular electronic control unit is configured to send detected fault information to the register in the case where a correctable error occurs in a target memory. The register is configured to store the fault information of the target memory. One end of the second interface is connected to the register, and the other end is connected to a second fault analysis module of the baseboard management controller. The baseboard management controller comprises the second fault analysis module configured to obtain a physical address from the fault information of the register through the second interface, and analyze the physical address in M dimensions to obtain M second analysis results, where M is an integer greater than or equal to 2, and the M dimensions are different levels based on different storage unit granularities of the target memory. The higher the level, the larger the storage unit granularity. The storage unit at a high level comprises a plurality of storage units at a low level. The second analysis result is used to indicate the level where the correctable error of the target memory occurs.

[0229] The host unit is mainly configured to detect memory faults, record fault states, and provide a fault data access interface function. The host unit mainly comprises a modular electronic control unit, a register, and a second interface. The modular electronic control unit can be an IMC controller. The register can be an MSR / CSR register. The register is configured to store the fault information detected by the modular electronic control unit, such as the physical address of the target memory where the fault occurs. The second interface can be a PECI interface. Through the second interface, the information stored in the host unit can be transmitted to the BMC unit. When a correctable error occurs in the target memory, the modular electronic control unit detects the fault information of the target memory. At this time, the fault information of the target memory is recorded in the MSR and CSR registers in the CPU.

[0230] The baseboard management controller, i.e., the BMC unit, comprises a second fault analysis module. The second fault analysis module can analyze the detected fault from multiple levels. In the case where a correctable error occurs in the target memory, the BMC unit obtains the physical address of the target memory stored in the register in the host unit through the second interface, and analyzes the physical address of the target memory from multiple levels through the second fault analysis module, so as to obtain a plurality of second analysis results.

[0231] In some embodiments, the host unit further comprises a first fault resolution module configured to acquire the physical address from the register and resolve the physical address in M dimensions to obtain M first resolution results in a case that the second fault resolution module fails to acquire the physical address from the register, wherein the first resolution result is used to represent a level at which the target memory occurs a correctable error, and the second fault resolution module failing to acquire the physical address from the register comprises that the second fault resolution module fails to acquire the physical address from the register within a preset time length of a restart of the host unit.

[0232] Fig. 19 is a schematic diagram of architecture of a fault prediction system according to an embodiment of the present application. As shown in Fig. 19, the host unit can further comprise a first fault resolution module configured to resolve the detected fault from multiple levels, for example, a storage row and a minimum storage unit cell are storage units of two different dimensions, the level of the storage row is greater than that of the minimum storage unit, and each storage row comprises a plurality of minimum storage units. Resolving the fault from different dimensions can obtain that the fault occurs in the minimum storage unit cell 21, and the fault also occurs in the storage row 2. In a case that the target memory occurs a correctable error, resolving the physical address of the target memory from multiple levels by the first fault resolution module of the host unit can obtain a plurality of first resolution results.

[0233] In a case that the second fault resolution module of the BMC unit fails, the physical address of the target memory stored in the register can be acquired by the first fault resolution module, and the physical address of the target memory is resolved. Since the fault resolution modules are respectively arranged in the host unit and the BMC unit, in a case that any fault resolution module fails to work, the physical address of the target memory can still be resolved, the fault tolerance of the system is effectively improved, the influence of system failure on the whole system is reduced, the normal operation of the memory fault prediction is ensured, and the reliability and stability of the system are improved.

[0234] In some embodiments, the host unit further comprises an interrupt control management module connected to the modular electronic control unit, and the modular electronic control unit is further configured to send an interrupt signal to the interrupt control management module in a case that the second interface fails to send the physical address to the second fault resolution module; and the interrupt control management module is configured to trigger the first fault resolution module to acquire the physical address from the fault information stored in the register in a case that the interrupt signal is received.

[0235] The interrupt control management module can be a UBOX (i.e., a module for interrupt control management in a CPU), which is configured to trigger the first fault resolution module to obtain the physical address of the target memory from the register; when the modular electronic control unit detects that the second interface cannot send the physical address to the second fault resolution module, it indicates that the second fault resolution module has failed, at which time the modular electronic control unit sends an interrupt signal to the interrupt control management module, and the interrupt control management module receives the interrupt signal and triggers the first fault resolution module to obtain the physical address of the target memory from the fault information stored in the register.

[0236] In some embodiments, the host unit further includes: a first interface, one end of the first interface being connected to the first fault resolution module, and the other end being connected to a data storage unit of the baseboard management controller; the first interface is configured to transmit the N first resolution results in the first fault resolution module to the data storage unit, so as to record the N first resolution results in the data storage unit.

[0237] The first interface can be an eSPI interface, which is connected to the first fault resolution module of the host unit and the data storage module of the BMC unit, respectively, and through the first interface, the plurality of first resolution results of the target memory obtained by the first fault resolution module in the host unit are transmitted to the BMC unit and stored in the data storage module.

[0238] In some embodiments, the baseboard management controller further includes: a data storage unit, one end of the data storage unit being connected to the first interface, and the other end being connected to the second fault resolution module, which is configured to record the N first resolution results and the N second resolution results; a multi-dimensional prediction module including N prediction models, which is connected to the data storage unit and is configured to obtain the first resolution results and / or the second resolution results from the data storage unit, input the first resolution results and / or the second resolution results into the corresponding prediction models, and predict the probability of the target memory having an uncorrectable error at the corresponding level by the prediction models to obtain N prediction values; wherein, the more times a correctable error occurs in the N levels, the greater the probability of an uncorrectable error occurring in the level; and / or, the more the number of low levels in a high level that have a correctable error within a preset time range, the greater the probability of an uncorrectable error occurring in the high level; the baseboard management controller further includes: a fusion module, which is configured to fuse the N prediction values based on a fusion strategy to obtain a fusion value, wherein the fusion value determines the probability of the target memory having an uncorrectable error.

[0239] The data storage module is configured to store the analysis result of the target memory physical address, which can be the plurality of first analysis results analyzed by the first fault analysis module, or the second analysis result analyzed by the second fault analysis module; the multi-dimensional prediction model can include a plurality of dimensional prediction models, such as online prediction models, offline prediction models, rule matching prediction models, and a plurality of dimensional models, or a plurality of different level fault prediction models, etc. Different memory fault prediction models can be embedded in the BMC of each server to match different configuration types of each server (such as different configurations of memory bank models, capacity, batch, etc.), so that the prediction model is flexibly and accurately matched with the configuration of the server, achieving better prediction performance. At the same time, by predicting from multiple dimensions, different types of prediction algorithms and different dimensions of memory fault information are considered, the value of available memory fault information is fully tapped, the utilization rate of fault information is improved, and the dimension of memory fault prediction is effectively expanded; the fusion module is configured to fuse the plurality of results output by the multi-dimensional prediction model. By using a suitable fusion strategy to fuse the output results of the multi-dimensional prediction model, the accuracy of the model prediction can be effectively improved, thereby improving the memory fault prediction performance.

[0240] Through the BMC unit, the probability of the target memory at the corresponding level to occur uncorrectable error can be predicted from different levels based on the plurality of first analysis results and / or the plurality of second analysis results, and the plurality of prediction results obtained are fused according to the fusion strategy to obtain the probability of the target memory to occur uncorrectable error. For example, the target memory A occurs correctable error, the physical address of the target memory A is analyzed by the first fault analysis module to obtain the corresponding minimum storage unit cell21 and the corresponding storage row row2, the analysis results are respectively input into the prediction model of the minimum storage unit and the prediction model of the storage row, the probability of the target memory A to occur uncorrectable error at the minimum storage unit cell is p1, and the probability of the target memory A to occur uncorrectable error at the storage row is p2. Among them, the more times the correctable error occurs in the N levels, the greater the probability of uncorrectable error in the level; and / or in a predetermined time range, the more the number of low levels in the high level that occur correctable error, the greater the probability of uncorrectable error in the high level; p1 and p2 are fused according to the fusion strategy, and the probability of the target memory A to occur uncorrectable error is P.

[0241] The BMC unit predicts the probability of the target memory to occur uncorrectable error, so that each server has the function of memory fault prediction, thereby eliminating the need to rely on an additional inference server, reducing the risk of prediction function paralysis caused by inference server failure, improving the reliability of the prediction function, and avoiding the deployment of inference node servers, saving a lot of manpower and resources, and reducing system deployment overhead.

[0242] In some embodiments, between the data storage unit of the baseboard management controller and the multi-dimensional prediction module, a data processing module is further included, configured to obtain the first analysis result and the second analysis result from the memory failure data unit, and pre-process the first analysis result and the second analysis result to obtain a processed first analysis result.

[0243] The data processing module is configured to preliminarily analyze the analysis result obtained from the data storage module, and the data processing module includes multiple pre-processing modes, such as rejecting abnormal data, completing missing data, classifying data, and labeling data. By pre-processing the analysis result of the target memory physical address, the quality and availability of the analysis result are improved, thereby helping to improve the accuracy and efficiency of the model.

[0244] In some embodiments, the N levels include: a minimum storage unit, a storage row, a storage column, a storage array, a storage block, a storage channel, a storage particle, a memory bank, and a memory channel.

[0245] From the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software and a general hardware platform as required, and of course, it can also be implemented by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solutions of the present application or the parts that contribute to the related art can be embodied in the form of a software product, which is stored in a computer readable storage medium (such as a ROM / RAM, a magnetic disk, or an optical disk), and includes a plurality of instructions for causing a terminal device (which can be a mobile phone, a computer, a server, or a network device) to execute the method of each embodiment of the present application.

[0246] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when running, and the computer readable storage medium can be a non-volatile computer readable storage medium.

[0247] In an example embodiment, the above computer readable storage medium can include, but is not limited to: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0248] The embodiments of the present application further provide an electronic device, comprising a memory and a processor, the memory storing a computer program, and the processor is configured to execute the computer program to perform the steps in any of the method embodiments.

[0249] In an example embodiment, the electronic device described above can further comprise a transmission device connected to the processor, and an input / output device connected to the processor.

[0250] The embodiments of the present application further provide a computer program product, the computer program product comprising a computer program, the computer program being executed by a processor to implement the steps in any of the method embodiments.

[0251] The optional examples in the embodiments can refer to the examples described in the above embodiments and example implementations, which will not be described herein again.

[0252] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be realized by general computing devices, which can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, which can be realized by program codes executable by the computing devices, so that they can be stored in storage devices and executed by the computing devices, and in some cases, the steps shown or described can be executed in different order, or they can be manufactured into individual integrated circuit modules, or multiple modules or steps can be manufactured into a single integrated circuit module. Thus, the present application is not limited to any particular combination of hardware and software.

[0253] The above is only optional embodiments of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method of memory failure prediction, the method comprising: Comprise: In the case of a correctable error occurring in the target memory, the first fault resolution module of the host unit obtains the physical address of the target memory and resolves the physical address in M dimensions to obtain M first resolution results, wherein M is an integer greater than or equal to 2, the M dimensions are obtained based on different storage unit granularity divisions of the target memory, and the first resolution result is used to indicate that the target memory has the correctable error in the corresponding dimension. The baseboard management controller obtains the M first resolution results, inputs the M first resolution results into M prediction models corresponding to the M dimensions to obtain M prediction values. The baseboard management controller fuses the M prediction values to obtain a fusion value, wherein the fusion value is used to predict whether the target memory will have an uncorrectable error.

2. The method of claim 1, wherein, The first fault resolution module in the host unit obtains the physical address of the target memory, comprising: The modular electronic control unit of the host unit sends the detected fault information to the register and sends an interrupt signal to the interrupt control management module of the host unit in the case of detecting that the target memory has the correctable error. The interrupt control management module triggers the first fault resolution module to obtain the physical address from the fault information stored in the register in the case of receiving the interrupt signal.

3. The method of claim 1, wherein, The baseboard management controller obtains the M first resolution results from the host unit, inputs the M first resolution results into M prediction models corresponding to the M dimensions, comprising: In the self-checking phase at system startup, the host unit reports the M first resolution results output by the first fault resolution module to the baseboard management controller through the first interface of the host unit; The baseboard management controller stores the M first resolution results to a data storage module; The baseboard management controller inputs the M first resolution results into the M prediction models to obtain M prediction values.

4. The method according to claim 1 or 3, characterized in that, In the case that the M prediction models are online models, the baseboard management controller inputs the M first resolution results into the M prediction models to obtain M prediction values, comprising: In the case that the target memory has the correctable error in the tth prediction period, the baseboard management controller obtains a correctable error sequence of the target memory in the tth prediction period in the data storage module, wherein the correctable error sequence includes the resolution results obtained by the first fault resolution module resolving the physical address of the target memory in the tth prediction period, and the correctable error sequence includes the M first resolution results; The baseboard management controller determines a first error sequence corresponding to the target memory in the t-1th prediction period; The baseboard management controller inputs the correctable error sequence and the first error sequence into the M prediction models to obtain the M prediction values.

5. The method of claim 4, wherein, The baseboard management controller fuses the M prediction values to obtain a fusion value, comprising: The baseboard management controller obtains M weight values corresponding to the M dimensions; The baseboard management controller performs weighted summation on the M weight values and the M predicted values to obtain the fusion value.

6. A method of memory failure prediction, the method comprising: Comprise: In the case that the target memory has a correctable error, the modular electronic control unit of the host unit sends the detected fault information to the register of the host unit; The register stores the fault information; The second fault analysis module of the baseboard management controller obtains the physical address from the fault information of the register through the second interface, and analyzes the physical address in M dimensions to obtain M second analysis results, wherein M is an integer greater than or equal to 2, the M dimensions are obtained based on different storage unit granularities of the target memory, and the second analysis result is used to indicate that the target memory has the correctable error in the corresponding dimension; The baseboard management controller obtains the M second analysis results from the second fault analysis module, inputs the M second analysis results into M prediction models corresponding to the M dimensions, and obtains M predicted values; The baseboard management controller fuses the M predicted values to obtain a fusion value, wherein the fusion value is used to predict whether the target memory will have an uncorrectable error.

7. The method of claim 6, wherein, Comprise: In the case that the second fault analysis module cannot obtain the physical address from the register, the first fault analysis module of the host unit obtains the physical address of the target memory from the register and analyzes the physical address in M dimensions to obtain M first analysis results, wherein the first analysis result is used to indicate that the target memory has the correctable error in the corresponding dimension; The baseboard management controller obtains the M first analysis results, inputs the M first analysis results into M prediction models corresponding to the M dimensions, and obtains M predicted values; The baseboard management controller fuses the M predicted values to obtain a fusion value, wherein the fusion value is used to predict whether the target memory will have an uncorrectable error; The second fault analysis module cannot obtain the physical address from the register, comprising: within a preset time length of the host unit restart, the second fault analysis module cannot obtain the physical address from the register.

8. The method of claim 7, wherein, The first fault analysis module of the host unit obtains the physical address of the target memory from the register, comprising: The modular electronic control unit of the host unit sends an interrupt signal to the interrupt control management module in the case that it detects that the second interface cannot send the physical address to the second fault analysis module; The interrupt control management module triggers the first fault analysis module to obtain the physical address from the fault information stored in the register in the case that it receives the interrupt signal.

9. The method of claim 7, wherein, The method further comprises: The data storage module of the baseboard management controller obtains the M first analysis results from the first fault analysis module through the first interface, and stores the M first analysis results; The data storage module of the baseboard management controller acquires the M second analysis results from the second fault analysis module and stores the M second analysis results.

10. The method of claim 9, wherein, The baseboard management controller acquires the M second analysis results from the second fault analysis module, inputs the M second analysis results into M prediction models corresponding to the M dimensions to obtain M prediction values, including: In the case that the M prediction models are online linear models, the baseboard management controller inputs the M second analysis results into the M prediction models to obtain M prediction values, including: In the case that the target memory has the correctable error in the tth prediction period, the baseboard management controller acquires a correctable error sequence of the target memory in the tth prediction period in the data storage module, wherein the correctable error sequence includes analysis results obtained by the second fault analysis module analyzing the physical address of the target memory in the tth prediction period, and the correctable error sequence includes the M second analysis results; The baseboard management controller determines a first error sequence corresponding to the target memory in a (t-1)th prediction period; The baseboard management controller inputs the correctable error sequence and the first error sequence into M prediction models to obtain the M prediction values.

11. A system for memory failure prediction, the system comprising: including: The host unit includes a first fault analysis module, which is configured to acquire a physical address of a target memory in the case that the target memory has a correctable error, and analyze the physical address in M dimensions to obtain M first analysis results, wherein M is an integer greater than or equal to 2; The baseboard management controller is configured to acquire the M first analysis results from the host unit, input the M first analysis results into corresponding prediction models in a multi-dimensional prediction model to obtain M prediction values, wherein the multi-dimensional prediction model includes M prediction models corresponding to the M dimensions; and the baseboard management controller is further configured to fuse the M prediction values by a fusion strategy to obtain a fusion value, wherein the fusion value is used to represent a probability of the target memory having an uncorrectable error.

12. The system of claim 11, wherein The host unit further includes a modular electronic control unit, an interrupt control management module, and a register, the modular electronic control unit is configured to send detected fault information to the register and send an interrupt signal to the interrupt control management module in the case that the target memory is detected to have the correctable error; The interrupt control management module is configured to trigger the first fault analysis module to acquire the physical address from the fault information stored in the register in the case that the interrupt signal is received.

13. The system of claim 11, wherein The host unit further includes a first interface, one end of the first interface is connected to the first fault analysis module, and the other end is connected to a data storage module of the baseboard management controller. The first interface is configured to transmit the M first analysis results in the first fault analysis module to the data storage module, so as to record the M first analysis results in the data storage module.

14. The system of claim 13, wherein, The baseboard management controller further comprises the data storage module configured to record the M first analysis results. The multi-dimensional prediction module is connected to the data storage module and comprises the M prediction models, and is configured to obtain the M first analysis results from the data storage module, input the M first analysis results into the corresponding prediction models respectively, and obtain the M prediction values by predicting the probability of occurrence of the uncorrectable error at the corresponding level in the target memory through the prediction models. The baseboard management controller further comprises the fusion module configured to fuse the M prediction values based on a fusion strategy to obtain the fusion value.

15. A system for memory failure prediction, the system comprising: The system comprises: The baseboard management controller comprises: The host unit comprises a modular electronic control unit, a register, and a second interface, the modular electronic control unit is configured to send the detected fault information to the register in the case of detecting the occurrence of the correctable error in the target memory, the register is configured to store the fault information of the target memory, and one end of the second interface is connected to the register and the other end is connected to the second fault analysis module of the baseboard management controller. The baseboard management controller comprises the second fault analysis module configured to obtain the physical address from the fault information of the register through the second interface and analyze the physical address in M dimensions to obtain M second analysis results, wherein M is an integer greater than or equal to 2, the M dimensions are different levels obtained based on different storage unit granularities of the target memory, the higher the level, the larger the storage unit granularity, and the storage unit at a high level comprises a plurality of storage units at a low level, and the second analysis result is used to represent the level at which the correctable error occurs in the target memory.

16. The system of claim 15, wherein, The host unit further comprises a first fault analysis module configured to obtain the physical address from the register and analyze the physical address in M dimensions to obtain M first analysis results in the case that the second fault analysis module fails to obtain the physical address from the register, wherein the first analysis result is used to represent the level at which the correctable error occurs in the target memory, and the second fault analysis module failing to obtain the physical address from the register comprises that the second fault analysis module fails to obtain the physical address from the register within a preset time length of the host unit restart.

17. The system of claim 16, wherein, The host unit further comprises an interrupt control management module connected to the modular electronic control unit, the modular electronic control unit being further configured to send an interrupt signal to the interrupt control management module in case that the second interface is detected to be unable to send the physical address to the second fault resolution module; The interrupt control management module is configured to trigger the first fault resolution module to obtain the physical address from the fault information stored in the register in case that the interrupt signal is received. 18.A non-volatile computer readable storage medium, comprising a computer program, wherein the computer program is executed by a processor to implement the steps of the method in any one of claims 1 to 5 or claims 6 to 10. 19.An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method in any one of claims 1 to 5 or claims 6 to 10 when executing the computer program. 20.A computer program product, comprising a computer program, wherein the computer program is executed by a processor to implement the steps of the method in any one of claims 1 to 5 or claims 6 to 10. ​ ​ ​

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