Data processing method, apparatus, and related device

Abstract

Provided in the embodiments of the present invention are a data processing method, an apparatus, and a related device. The method comprises: acquiring an original data group; on the basis of the original data group, generating an error correction data group; interleaving the error correction data group to obtain a data block to be processed, the data block to be processed comprising an original data region obtained by interleaving an original data block and an error correction data region obtained by interleaving an error correction data block, and in the data block to be processed, each column of data being transmitted on the basis of a transmission channel and each row of data being transmitted on the basis of a clock tick, wherein a piece of symbol data in the original data block is configured in a column of data in the original data region, a piece of symbol data in the error correction data block is configured in a column of data in the error correction data region, and data in the data block to be processed is aligned on a row basis; and, on the basis of a transmission rule for the data block to be processed, transmitting to a preset component the data block to be processed. The data processing solution improves data error correction efficiency.

Description

Data processing method, device and related equipment

[0001] Related applications

[0002] The present application claims priority to the Chinese Invention Patent Application No. 202410840307.6, filed on June 26, 2024, entitled "Data processing method, device and related equipment", the contents of which are hereby incorporated by reference in their entirety. TECHNICAL FIELD

[0003] Embodiments of the present application relate to the field of computer integrated circuit design and manufacturing technology, in particular to a data processing method, device and related equipment. BACKGROUND

[0004] In a computer system, ECC (Error Correction Code) technology is a commonly used error correction technology, which is used to detect and correct errors by adding redundant error correction data to the data. In the data transmission and access process, the original data and the error correction data need to be transmitted and processed synchronously, so as to realize real-time error correction of the original data in the data transmission and access process. Correspondingly, in hardware implementation, a transmission channel for transmitting / receiving error correction information is usually set at the same time as a transmission channel for transmitting / receiving original data, so as to realize simultaneous transmission of original data and error correction information. At the same time, a storage structure matched with the number of transmission channels can be set on the hardware to realize convenient access to data.

[0005] However, in the existing data transmission and access process, the data error correction performance is affected by the hardware setting, and the data error correction efficiency needs to be improved.

[0006] Content of the present application

[0007] Therefore, embodiments of the present application provide a data processing method, device and related equipment to improve the data error correction efficiency.

[0008] In a first aspect, embodiments of the present application provide a data processing method, comprising:

[0009] obtaining an original data group;

[0010] generating an original data block and an error correction data block corresponding to the original data block based on the original data group, wherein an original data block and an error correction data block corresponding thereto form an error correction data group;

[0011] The error correction data groups are interleaved to obtain a to-be-processed data block, the to-be-processed data block comprises an original data area obtained by interleaving original data blocks and an error correction data area obtained by interleaving error correction data blocks, wherein a column of data in the to-be-processed data block is used for transmission based on a transmission channel, and a row of data is used for transmission based on a tap, wherein a symbol data in the original data block is arranged in a column of data in the original data area, a symbol data in the error correction data block is arranged in a column of data in the error correction data area, and the data in the to-be-processed data block is based on row alignment;

[0012] The to-be-processed data block is transmitted to a preset device based on a transmission rule of the to-be-processed data block.

[0013] Optionally, the original data groups are used to generate original data blocks and error correction data blocks corresponding to the original data blocks, comprising:

[0014] The original data groups are divided into original data blocks with a preset bit number.

[0015] The original data blocks are encoded to generate error correction data blocks corresponding to the data blocks.

[0016] Optionally, the to-be-processed data block comprises a plurality of error correction data groups, and the interleaving of the error correction data groups to obtain the to-be-processed data block comprises: arranging data of different error correction data groups in sequence based on an order of the error correction data groups, or interleaving data of different error correction data groups in sequence based on an order of symbols in the error correction data groups.

[0017] Optionally, the to-be-processed data block comprises four error correction data groups, namely a first error correction data group, a second error correction data group, a third error correction data group and a fourth error correction data group, each error correction data group comprises n symbols, the first k symbols are symbols in the original data block, the k+1th symbol to the nth symbol are symbols in the error correction data block, the first n symbol represents the nth symbol in the first error correction data group, the second n symbol represents the nth symbol in the second error correction data group, the third n symbol represents the nth symbol in the third error correction data group, and the fourth n symbol represents the nth symbol in the fourth error correction data group, n and k are positive integers.

[0018] The interleaving of data of different error correction data groups in sequence based on an order of symbols in the error correction data groups obtains a to-be-processed data block as follows:

[0019] The first column to the fourth column correspond to the symbols in the original data block of the plurality of error correction data groups, wherein the first column corresponds to the first 1 symbol, the second column corresponds to the second 1 symbol, the third column corresponds to the third 1 symbol, the fourth column corresponds to the fourth 1 symbol, and the number of columns is alternately arranged in sequence until the fourth k-3 column to the fourth k column, wherein the fourth k-3 column corresponds to the first k symbol, the fourth k-2 column corresponds to the second k symbol, the fourth k-1 column corresponds to the third k symbol, and the fourth k column corresponds to the fourth k symbol;

[0020] The fourth k+1 column to the fourth n column correspond to the symbols in the error correction data block of the plurality of error correction data groups, n=k+2t, 4n=4k+8t, wherein the fourth k+1 column corresponds to the first k+1 symbol, the fourth k+2 column corresponds to the second k+1 symbol, the fourth k+3 column corresponds to the third k+1 symbol, the fourth k+4 column corresponds to the fourth k+1 symbol, and the number of columns is alternately arranged in sequence until the fourth n-3 column to the fourth n column, wherein the fourth n-3 column corresponds to the first n symbol, the fourth n-2 column corresponds to the second n symbol, the fourth n-1 column corresponds to the third n symbol, and the fourth n column corresponds to the fourth n symbol.

[0021] Optionally, the to-be-processed data block includes two error correction data groups, which are a fifth error correction data group and a sixth error correction data group, and each error correction data group includes n symbols, the first k symbols are symbols in the original data block, and the k+1th symbol to the n symbol are symbols in the error correction data block, the fifth n symbol represents the n symbol in the fifth error correction data group, and the sixth n symbol represents the n symbol in the sixth error correction data group, n and k are positive integers;

[0022] The to-be-processed data block obtained by sequentially interleaving the data of different error correction data groups based on the order of the symbols in the error correction data groups is:

[0023] The first column to the second k column correspond to the symbols in the original data block of the plurality of error correction data groups, wherein the first column corresponds to the fifth 1 symbol, the second column corresponds to the sixth 1 symbol, and the number of columns is alternately arranged in sequence until the second k-1 column to the second k column, wherein the second k-1 column corresponds to the fifth k symbol, and the second k column corresponds to the sixth k symbol.

[0024] The second k+1 column to the second n column correspond to the symbols in the error correction data block of the plurality of error correction data groups, n=k+2t, 2n=2k+4t, wherein the second k+1 column corresponds to the fifth k+1 symbol, the second k+2 column corresponds to the sixth k+1 symbol, and the number of columns is alternately arranged in sequence until the second n-1 column to the second n column, wherein the second n-1 column corresponds to the fifth n symbol, and the second n column corresponds to the sixth n symbol.

[0025] Optionally, interleaving the error correction data groups to obtain the to-be-processed data block includes:

[0026] arranging data in the original data block in an original data area of the data block to be processed;

[0027] arranging data in the error correction data block in an error correction data area of the data block to be processed.

[0028] Optionally, a burst length corresponds to data amounts of a plurality of data blocks to be processed, and the data blocks to be processed are transmitted to the preset device based on the transmission rule of the data blocks to be processed, specifically, data of the plurality of data blocks to be processed is transmitted in a burst length.

[0029] Optionally, when a data block to be processed includes a plurality of error correction data groups, the data blocks to be processed are transmitted to the preset device based on the transmission rule of the data blocks to be processed, specifically, data of different error correction data groups is transmitted in adjacent transmission channels in a particle chip.

[0030] In a second aspect, an embodiment of the present application provides a data processing method, comprising:

[0031] obtaining a data block to be processed, the data block to be processed being obtained based on interleaving of an error correction data group, the error correction data group including an original data block and an error correction data block, the data block to be processed including an original data area obtained by interleaving of the original data block and an error correction data area obtained by interleaving of the error correction data block, a symbol data in the original data block being arranged in a column of data in the original data area, a symbol data in the error correction data block being arranged in a column of data in the error correction data area, data in the data block to be processed being based on row alignment, wherein a column of data in the data block to be processed is used for transmission based on a transmission channel, and a row of data is used for transmission based on a shot;

[0032] deinterleaving the data block to be processed to obtain an error correction data group;

[0033] correcting data errors of the original data block in the error correction data group based on the error correction data block in the error correction data group;

[0034] generating an original data group based on the original data block after error correction.

[0035] Optionally, the obtaining of the data block to be processed is specifically based on a transmission rule of hardware.

[0036] The transmission rule includes:

[0037] based on a correspondence between each column of data and a hardware port, obtaining each column of data of the data block to be processed from different hardware ports;

[0038] based on a number of data blocks to be processed transmitted in a burst length, obtaining a corresponding number of data blocks to be processed.

[0039] Optionally, the obtaining the data block to be processed comprises:

[0040] obtaining data of a burst length;

[0041] dividing the data of the burst length into a plurality of data blocks to be processed based on a symbol length in the data block to be processed.

[0042] Optionally, the data block to be processed comprises a plurality of error correction data groups, and the deinterleaving the data block to be processed to obtain an error correction data group comprises determining symbol data belonging to different error correction data groups and corresponding arrangement orders based on a preset data arrangement order.

[0043] Optionally, the determining symbol data belonging to different error correction data groups and corresponding arrangement orders based on a preset data arrangement order comprises:

[0044] when data of different error correction data groups in the data block to be processed is sequentially arranged based on an order of the error correction data groups, sequentially extracting original data blocks and / or error correction data blocks in the different error correction data groups;

[0045] or,

[0046] when data of different error correction data groups in the data block to be processed is sequentially interleaved based on symbol data in the error correction data groups, extracting symbols of original data blocks and / or symbols of error correction data blocks in the different error correction data groups based on an interleaving order in the interleaving process.

[0047] Optionally, the correcting data errors of the original data blocks in the error correction data group based on the error correction data blocks in the error correction data group comprises:

[0048] calculating positions of error data in the original data blocks based on the error correction data blocks in the error correction data group;

[0049] correcting data errors at the positions of the error data in the original data blocks.

[0050] Optionally, the original data group comprises a plurality of original data blocks, and the generating an original data group based on the original data blocks after error correction comprises combining the original data blocks based on a preset rule to generate the original data group.

[0051] Optionally, after the generating an original data group based on the original data blocks after error correction, the method further comprises:

[0052] counting positions of error data in the data block to be processed to determine a type of data errors.

[0053] Optionally, the position of the error data in the data block to be processed is counted to determine the error type of the data, comprising:

[0054] The position of the error data in the data block to be processed is counted.

[0055] It is judged whether the error data is located in a preset number of column data, if yes, the error data is a preset error; if not, the preset error is excluded.

[0056] In a third aspect, an embodiment of the present application provides a data processing device, comprising:

[0057] A first data acquisition module is configured to acquire an original data group.

[0058] An error correction data group generation module is configured to generate an original data block and an error correction data block corresponding to the original data block based on the original data group, wherein an original data block and an error correction data block corresponding thereto form an error correction data group.

[0059] An interleaving module is configured to interleave the error correction data group to obtain a data block to be processed, the data block to be processed comprising an original data area obtained by interleaving the original data block and an error correction data area obtained by interleaving the error correction data block, wherein a column of data in the data block to be processed is used for transmission based on a transmission channel, and a row of data is used for transmission based on a beat, wherein a symbol data in the original data block is arranged in a column of data in the original data area, a symbol data in the error correction data block is arranged in a column of data in the error correction data area, and the data in the data block to be processed is based on row alignment.

[0060] A data transmission module is configured to transmit the data block to be processed to a preset device based on a transmission rule of the data block to be processed.

[0061] In a fourth aspect, an embodiment of the present application provides a data processing device, comprising:

[0062] A second data acquisition module is configured to acquire a data block to be processed, the data block to be processed being obtained by interleaving an error correction data group, the error correction data group comprising an original data block and an error correction data block, the data block to be processed comprising an original data area obtained by interleaving the original data block and an error correction data area obtained by interleaving the error correction data block, a symbol data in the original data block being arranged in a column of data in the original data area, a symbol data in the error correction data block being arranged in a column of data in the error correction data area, and the data in the data block to be processed being based on row alignment, wherein a column of data in the data block to be processed is used for transmission based on a transmission channel, and a row of data is used for transmission based on a beat.

[0063] A deinterleaving module is configured to deinterleave the data block to be processed to obtain an error correction data group.

[0064] an error correction module, configured to correct data errors of the original data block in the error correction data group based on the error correction data block in the error correction data group;

[0065] an original data group generation module, configured to generate an original data group based on the original data block after error correction.

[0066] In a fifth aspect, an embodiment of the present application provides a memory controller,

[0067] The memory controller is configured with the data processing apparatus in the third aspect.

[0068] and / or

[0069] The memory controller is configured with the data processing apparatus in the fourth aspect.

[0070] In a sixth aspect, an embodiment of the present application provides an electronic device, comprising the memory controller in the fifth aspect.

[0071] In a seventh aspect, an embodiment of the present application provides a storage medium, which stores one or more computer executable instructions, and the one or more computer executable instructions are executed to implement the data processing method in the first aspect, and / or implement the data processing method in the second aspect.

[0072] In an eighth aspect, an embodiment of the present application provides a computer program product, which comprises one or more computer executable instructions, and the one or more computer executable instructions are executed to implement the data processing method in the first aspect, and / or implement the data processing method in the second aspect.

[0073] The embodiment of the present application provides a data processing method, device and related equipment, and the method comprises the following steps: obtaining an original data group; generating an original data block and an error correction data block corresponding to the original data block based on the original data group, wherein an original data block and an error correction data block corresponding to the original data block form an error correction data group; interleaving the error correction data group to obtain a to-be-processed data block, the to-be-processed data block comprises an original data area obtained by interleaving the original data block and an error correction data area obtained by interleaving the error correction data block, wherein a column of data in the to-be-processed data block is used for transmission based on a transmission channel, and a row of data is used for transmission based on a shot, wherein a symbol data in the original data block is arranged in a column of data in the original data area, a symbol data in the error correction data block is arranged in a column of data in the error correction data area, and the data in the to-be-processed data block is aligned based on rows; and transmitting the to-be-processed data block to a preset device based on a transmission rule of the to-be-processed data block.

[0074] It can be seen that, in the data processing method provided by the embodiment of the present application, when the to-be-processed data block is obtained through interleaving, one symbol data in the original data block is arranged in one column of data in the original data area of the to-be-processed data block, one symbol data in the error correction data block is arranged in one column of data in the error correction data area of the to-be-processed data block, and the data in the to-be-processed data block is aligned based on a row. Since one column of data in the to-be-processed data block is transmitted based on one transmission channel, one symbol data only corresponds to one transmission channel and does not occupy multiple transmission channels of one storage chip. In the error correction process based on a symbol, the corresponding error correction can be performed based on one transmission channel, and is no longer limited to one storage chip. Therefore, the data error correction capability can be maximized, and the data error correction efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS

[0075] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort based on the provided drawings.

[0076] Fig. 1 is a structural schematic diagram of a to-be-processed data block;

[0077] Fig. 2 is an optional flow schematic diagram of a data processing method provided by an embodiment of the present application;

[0078] Fig. 3 is an optional flow schematic diagram of step S110 provided by an embodiment of the present application;

[0079] Fig. 4 is an optional schematic diagram of a data processing flow provided by an embodiment of the present application;

[0080] Fig. 5 is an optional schematic diagram of data interleaving provided by an embodiment of the present application;

[0081] Fig. 6 is another optional schematic diagram of data interleaving provided by an embodiment of the present application;

[0082] Fig. 7 is a data structure schematic diagram of a burst length provided by an embodiment of the present application;

[0083] Fig. 8 is an optional schematic diagram of a hardware module provided by an embodiment of the present application;

[0084] Fig. 9 is an optional flow schematic diagram of another data processing method provided by an embodiment of the present application;

[0085] Fig. 10 is still another optional flow schematic diagram of another data processing method provided by an embodiment of the present application;

[0086] Fig. 11 is a schematic diagram of an optional structure of another hardware module according to an embodiment of the present application;

[0087] Fig. 12 is a schematic diagram of a data structure for transmitting a burst length to an X4 granular chip according to an embodiment of the present application;

[0088] Fig. 13 is a schematic diagram of a data structure for transmitting a burst length according to a four-way RS8(10, 8) encoding and interleaving of error correction data according to an embodiment of the present application;

[0089] Fig. 14 is a schematic diagram of a data structure for transmitting a burst length according to a two-way RS8(20, 16) encoding and interleaving of error correction data according to an embodiment of the present application;

[0090] Fig. 15 is an optional block diagram of a data processing apparatus according to an embodiment of the present application;

[0091] Fig. 16 is an optional block diagram of another data processing apparatus according to an embodiment of the present application. DETAILED DESCRIPTION

[0092] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0093] As described in the background, in the existing data transmission and access process, the error correction performance of data is affected by the software and hardware settings, and the maximum error correction efficiency cannot be achieved.

[0094] Referring to Fig. 1, a schematic diagram of a structure of a data block to be processed is shown, which corresponds to a data storage structure of an X4 granular chip (i.e., each granular storage chip corresponds to 4 interfaces, i.e., 4 transmission channels). The data storage structure corresponds to 40 transmission channels, and a burst length corresponds to 16 taps, which are Burst0-Burst15. The data in DATA0-DATA7 can be regarded as data for transmission and storage to 8 data chips (storage chips for storing valid data), which correspond to 32 transmission channels. The data in ECC0 and ECC1 can be regarded as data for transmission and storage to 2 error correction chips (storage chips for storing error correction data), which correspond to 8 transmission channels.

[0095] In the data transmission / storage process, data is encoded and interleaved based on a symbol as the minimum transmission unit / minimum storage unit of data. In the data storage process, one symbol data should be stored in one storage chip. FIG. 1 takes 8-bit symbol as an example. In the encoding and interleaving process, one symbol data is evenly divided into two rows, each row having 4 bits (only the configuration mode of symbol 1 in Data 5 and ECC 1 is illustrated by the diagonal line in the figure, and in fact, each Data / ECC corresponding area is configured with one symbol data every two rows). Then, the to-be-processed data block is formed, and the to-be-processed data block is transmitted / stored to the X4 grain chip based on the corresponding transmission channel.

[0096] From the error correction rate, in the data structure in the to-be-processed data block shown in FIG. 1, taking RS (Reed-Solomon code) encoding as an example (a kind of encoding using 2t and error correction symbol to correct t symbol errors, t is a positive integer), the corresponding data transmission channel can be regarded as 40-bit width, in which 8-bit is ECC bit width. In the RS encoding of 8-bit as one symbol, RS8 (10, 8) encoding is applicable, that is, in 10 symbols, 8 symbols are original data, and 2 symbols are error correction data. Correspondingly, this mode can correct 8-bit data in one symbol.

[0097] However, the inventor believes that based on one symbol corresponding to being configured in one storage chip, and the symbol occupying all data transmission channels of the storage chip, the total number of symbols is too small, and the number of symbols that can be corrected is also small. For example, the to-be-processed data block shown in FIG. 1 corresponds to 10 symbols for data corresponding to 40 transmission channels, and the corresponding encoding mode is only applicable to RS8 (10, 8) encoding, so that only 8-bit data in one symbol can be corrected, that is, data error in one storage chip. At this time, if multiple storage chips are wrong, error correction cannot be achieved.

[0098] Obviously, the error correction capability of this scheme is limited, so the maximum error correction efficiency cannot be achieved.

[0099] In view of this, the data processing method, device and related equipment provided by the embodiments of the present application include: obtaining an original data group; generating an original data block and an error correction data block corresponding to the original data block based on the original data group, wherein an original data block and an error correction data block corresponding thereto form an error correction data group; interleaving the error correction data group to obtain a to-be-processed data block, wherein a column of data in the to-be-processed data block is used for transmission based on a transmission channel, and a row of data is used for transmission based on a beat, wherein a symbol data in the original data block is arranged in a column of data in the to-be-processed data block, a symbol data in the error correction data block is arranged in a column of data in the to-be-processed data block, and the data in the to-be-processed data block is based on row alignment; and transmitting the to-be-processed data block to a preset device based on a transmission rule of the to-be-processed data block.

[0100] It can be seen that, in the data processing method provided by the embodiments of the present application, when the to-be-processed data block is obtained by interleaving, a symbol data in the original data block is arranged in a column of data in the original data area of the to-be-processed data block, a symbol data in the error correction data block is arranged in a column of data in the error correction data area of the to-be-processed data block, and the data in the to-be-processed data block is based on row alignment. Since a column of data in the to-be-processed data block is transmitted based on a transmission channel, a symbol data only corresponds to a transmission channel, and does not occupy multiple transmission channels of a storage chip. In the error correction process based on a symbol unit, the corresponding error correction can be performed based on a transmission channel, and is no longer limited to a storage chip. Therefore, the data error correction capability can be maximized, and the data error correction efficiency is improved.

[0101] Further, the number of symbols in the to-be-processed data block is determined based on the number of transmission channels in the storage chip, rather than based on the number of storage chips. Therefore, the number of symbols in the to-be-processed data block is doubled, and the number of symbols that can be corrected is also doubled. Therefore, the limitation of the error correction capability of the to-be-processed data block by the software and hardware is reduced, and the error correction efficiency is maximized.

[0102] Still taking the to-be-processed data block described in FIG. 1 as an example, if one symbol data corresponds to one column of data in the to-be-processed data block (referring to the configuration mode of symbol2 identified by Data7 in FIG. 1), the total number of symbols is consistent with the number of hardware transmission channels, that is, 40, at this time, the corresponding encoding mode can be RS8(10, 8), RS8(20, 16) or RS8(40, 32). Taking RS8(10, 8) as an example, the to-be-processed data block can include 4 groups of RS8(10, 8) encoded error correction data groups, and correspondingly, each group can correct one symbol, so that the to-be-processed data block can correct 4 symbols; taking RS8(20, 16) as an example, the to-be-processed data block can include 2 groups of RS8(20, 16) encoded error correction data groups, and correspondingly, each group can correct two symbols, so that the to-be-processed data block can correct 4 symbols; taking RS8(40, 32) as an example, the to-be-processed data block can include 1 group of RS8(40, 32) encoded error correction data groups, and each group can correct four symbols, so that the to-be-processed data block can correct 4 symbols.

[0103] Based on the fact that symbol data corresponds to transmission channels rather than storage chips, the data that can be corrected is based on transmission channels rather than limited to one storage chip. Still taking the error correction scheme provided in the above example as an example, the scheme can correct 4 symbols, so that the transmission data of 4 transmission channels on multiple chips can be corrected, and it is not limited to one storage chip.

[0104] Obviously, the data processing method, device and related equipment provided by the embodiment of the application reduce the limitation of the error correction capability of the to-be-processed data block and improve the error correction efficiency.

[0105] Meanwhile, the inventors believe that, based on the influence of hardware and software, data errors usually occur in a number of data transmission channels. This is because, from the hardware perspective, signal interference factors that may occur based on hardware location or hardware device performance and the like, certain fixed data transmission channels are bound to be prone to data transmission errors under the premise that hardware reasons cannot be ruled out, which is manifested as concentrated data errors in the corresponding data transmission channels; from the software perspective, in some optional scenarios, data transmission is based on the bounded fault mechanism to detect error data in the data, and the error data is concentrated and isolated in certain fixed time or space, at this time, the data transmission channels used to transmit the error data are manifested as concentrated data errors in certain transmission channels (referring to the shaded area in Data2 in FIG. 1).

[0106] For such a scenario, if the symbol data is still configured in the configuration mode identified by symbol1, the error correction data can only be limited to correcting data errors under the corresponding bounded fault mechanism, and cannot correct other storage chips that may have errors. In contrast, the scheme provided by the embodiments of the present application corresponds the symbol data to the transmission channel rather than the storage chip, so that when data errors occur in a certain data transmission channel, the error correction capability can be maximized. In addition to correcting data errors under the bounded fault mechanism, more error correction power can be provided to correct other column data errors, thereby maximizing data error correction efficiency.

[0107] To better understand the scheme provided by the embodiments of the present application, the specific content of the data processing scheme is further explained below.

[0108] In the embodiments of the present application, a data processing method is provided, and an optional flowchart of a data processing method is shown in FIG. 2. The method comprises:

[0109] Step S100: obtaining an original data group;

[0110] It can be understood that the data error correction mechanism can be applied to the data transmission process to correct possible data errors in the data transmission process, or can be applied to the data storage process to store data to the memory, so as to correct possible data errors in the data storage process when reading data. Wherein, when the data needs to be transmitted to the preset position, the original data group can be the data to be transmitted, and when the data needs to be transmitted and saved to the memory, the original data group can be the data to be saved.

[0111] The original data group can be understood as processed data to be transmitted or data to be saved, which can be binary data, and the corresponding length can be determined based on the data transmission mechanism or the data saving mechanism of the hardware device. In an optional example, the length of the original data group corresponds to the data amount of the original data that can be transmitted by a hardware burst length (burst), such as 128bit, 256bit, 512bit, etc.

[0112] Step S110: generating an original data block and an error correction data block corresponding to the original data block based on the original data group, wherein an original data block and an error correction data block corresponding thereto form an error correction data group;

[0113] The original data block is a data block with a data bit number required by a predetermined encoding mode, which is used as the original data part in the error correction data group, so that the original data is corrected based on the error correction data in the error correction data group in the subsequent process.

[0114] In this step, the generated original data block can be one or multiple, and the number of original data blocks can be determined based on the bit number of the original data group, the preset encoding mode, and the bit width of the hardware (i.e., the number of transmission channels).

[0115] The error correction data block is a redundant data block obtained based on the original data and a specific encoding algorithm, and is used to correct error data in the original data. The specific encoding algorithm has different calculation methods based on different error correction capabilities of the error correction data. For example, the calculation method of the error correction data of RS8 (20, 16) encoding that can correct 2 code elements is different from the calculation method of the error correction data of RS8 (40, 32) encoding that can correct 4 code elements. Moreover, the specific encoding algorithm can determine the position of the error data of the original data based on a specific decoding algorithm corresponding thereto, so as to correct the corresponding error data based on the position of the error data.

[0116] In an optional example, a specific encoding algorithm can be determined based on the hardware configuration and the system configuration, and the specific encoding algorithm can be fixedly configured in the hardware. For example, a specific hardware can be configured to execute the specific encoding algorithm as an encoding module.

[0117] One error correction data block can be understood as a set of error correction data corresponding to an original data block. In this step, the generated error correction data block can be one or multiple, and the number of error correction data blocks can be determined based on the number of original data blocks, i.e., the number of error correction data blocks is the same as the number of original data blocks.

[0118] In an optional flow, referring to the optional flowchart of step S110 shown in FIG. 3, step S110 includes:

[0119] Step S111: dividing the original data group into original data blocks with a preset bit number;

[0120] The bit number of the original data block is determined based on the preset encoding mode. When RSm (n, k) is used for encoding, the preset bit number is k*m, where m, n, and k are positive integers, m is the bit number of one code element, n is the total number of code elements of the subsequent formed error correction data group, and k is the number of code elements of the original data block of the subsequent formed data block to be processed.

[0121] It can be understood that the number of original data blocks can be determined based on the number of original data groups and the preset number of original data blocks. The number of original data blocks can be one or multiple. In the present example, referring to the optional schematic diagram of the data processing flow shown in FIG. 4, taking the original data group of 512 bits and the encoding mode of RS8 (10, 8) as an example, the corresponding original data block is 8 symbols, and the total number of bits is 64. The original data group of 512 bits is divided into 8 original data blocks.

[0122] In other examples, if the original data group is 512 bits and the encoding mode is RS8 (20, 16), the corresponding original data block is 16 symbols, and the total number of bits is 128. The original data group of 512 bits is divided into 4 original data blocks. In another example, if the original data group is 512 bits and the encoding mode is RS8 (40, 32), the corresponding original data block is 32 symbols, and the total number of bits is 256. The original data group of 512 bits is divided into 4 original data blocks.

[0123] Continuing to refer to FIG. 3, step S112 is performed: encoding the original data blocks to generate error correction data blocks corresponding to the data blocks;

[0124] The error correction data blocks are redundant data obtained based on a specific algorithm on the basis of the original data blocks. The error correction data blocks correspond one-to-one to the original data blocks. An original data block and the error correction data block corresponding thereto are used as an error correction data group. Thus, the original data can be corrected based on the error correction data in the error correction data group.

[0125] Specifically, the number of symbols of the error correction data block is 2t = n-k, and the corresponding number of data bits is (n-k)*m. The error correction data block can correct m bits of data in t symbols of the original data block, where t = (n-k) / 2.

[0126] The number of error correction data blocks is the same as the number of original data blocks, which can be one or multiple. In the present example, continuing to refer to FIG. 4, taking the original data group of 512 bits and the encoding mode of RS8 (10, 8) as an example, the corresponding original data block is 8 symbols, and the total number of bits is 64. The corresponding error correction data block is 2 symbols, and the total number of bits is 16. The original data group of 512 bits is divided into 8 original data blocks, and 8 error correction data blocks are generated correspondingly.

[0127] In other examples, if the original data group is 512 bits, the encoding mode is RS8 (20, 16), the corresponding original data block is 16 symbols, and the total is 128 bits, the corresponding error correction data block is 4 symbols, and the total is 32 bits. The 512-bit original data is divided into 4 original data blocks, and 4 error correction data blocks are generated accordingly. In another example, if the original data group is 512 bits, the encoding mode is RS8 (40, 32), the corresponding original data block is 32 symbols, and the total is 256 bits. The corresponding error correction data block is 8 symbols, and the total is 64 bits. The 512-bit original data is divided into 4 original data blocks, and 4 error correction data blocks are generated accordingly.

[0128] In a specific example, the encoding module can be configured in hardware, so that the error correction data block corresponding to the original data block is calculated by using the encoding module. Referring to the optional schematic diagram of a hardware module provided by the embodiment of the application shown in FIG. 8, the encoding module is set to generate error correction data (also referred to as error correction code) based on the original data.

[0129] Continuing to refer to FIG. 2, step S120 is performed: interleaving the error correction data group to obtain a to-be-processed data block, the to-be-processed data block including an original data area obtained by interleaving the original data block and an error correction data area obtained by interleaving the error correction data block, wherein a column of data in the to-be-processed data block is used for transmission based on a transmission channel, and a row of data is used for transmission based on a shot, wherein a symbol of data in the original data block is arranged in a column of data in the original data area, a symbol of data in the error correction data block is arranged in a column of data in the error correction data area, and the data in the to-be-processed data block is aligned based on rows.

[0130] To adapt to the hardware bit width, the error correction data group can be interleaved and processed into a to-be-processed data block conforming to the hardware bit width. In the embodiment of the application, a symbol of data is arranged in a column of data, and a column of data is transmitted based on a transmission channel. Accordingly, the data arrangement order of the original data and the error correction data is arranged based on the column direction in the to-be-processed data block. For example, the data of a symbol of data in the original data is 01001010, and the data is arranged vertically in a column in the data block.

[0131] In the embodiment of the application, a row of data is used for transmission based on a shot, and is used for controlling the data to be transmitted based on timing. In the to-be-processed data block, the data in the error correction data group can be aligned based on rows, so as to ensure that the data transmission of the same error correction data group is kept synchronous in timing.

[0132] The to-be-processed data block can include one error correction data group or multiple error correction data groups, and the specific number is determined based on the number of symbols in the error correction data group. The number of symbols in the to-be-processed data block is at least one or more times the bit width. For example, for hardware with a bit width of 40, 40 symbols of data should be configured. For an error correction data group with an encoding mode of RS8 (10, 8), a total of 10 symbols, the to-be-processed data block can be formed by interleaving 4 error correction data groups. For an error correction data group with an encoding mode of RS8 (20, 16), a total of 20 symbols, the to-be-processed data block can be formed by interleaving 2 error correction data groups. For an error correction data group with an encoding mode of RS8 (40, 32), a total of 40 symbols, the to-be-processed data block can be formed by interleaving 1 error correction data group.

[0133] It can be understood that in the hardware transmission channel, part of the transmission channel is used to transmit original data, and part of the transmission channel is used to transmit error correction data. The transmission channel used to transmit the original data is concentrated on one side to transmit data corresponding to the original data area, and the transmission channel used to transmit the error correction data is concentrated on the other side to transmit data corresponding to the error correction data area. Correspondingly, in the specific interleaving process, the original data block is sequentially configured in the original data area of the to-be-processed data block based on the symbol, and the error correction data block is sequentially configured in the error correction data area of the to-be-processed data block based on the symbol.

[0134] In specific examples, different data interleaving can be performed based on different hardware. Specifically, the original interleaving module can be configured to perform data interleaving of the original data block, and the error correction interleaving module can be configured to perform data interleaving of the error correction data block.

[0135] In the specific interleaving process, when the to-be-processed data block includes multiple error correction data groups, the data of different error correction data groups can be sequentially arranged based on the order of the error correction data groups, or the data of different error correction data groups can be sequentially interleaved based on the order of the symbols in the error correction data groups. It should be noted that regardless of the arrangement method, the original data block and the error correction data block in the error correction data group should be configured respectively, that is, the data in the original data block is arranged in the original data area of the to-be-processed data block, and the data in the error correction data block is arranged in the error correction data area of the to-be-processed data block.

[0136] Referring to FIG. 5, an optional schematic diagram of data interleaving is shown. The data block to be processed includes four error correction data groups, i.e., a first error correction data group, a second error correction data group, a third error correction data group, and a fourth error correction data group. Each error correction data group includes n symbols (n = 10 is taken as an example in the figure). The first k symbols are the symbols in the original data block (k = 8 is taken as an example in the figure). The k+1th symbol to the nth symbol are the symbols in the error correction data block. The first (1) symbol represents the first symbol in the first error correction data group, the first (2) symbol represents the second symbol in the first error correction data group, the first (n) symbol represents the nth symbol in the first error correction data group, and so on. The second n symbol represents the nth symbol in the second error correction data group, the third n symbol represents the nth symbol in the third error correction data group, and the fourth n symbol represents the nth symbol in the fourth error correction data group. n and k are positive integers.

[0137] The sequential arrangement of the data block to be processed based on the order of the error correction data groups means that the original data blocks of different error correction data groups are sequentially arranged in the original data area, and the error correction data blocks of different error correction data groups are sequentially arranged in the error correction data area. Specifically, continuing to refer to FIG. 5, taking the aforementioned data block to be processed including four error correction data groups as an example, the following is shown in the data block to be processed:

[0138] The first column to the 4kth column correspond to the symbols in the original data blocks of the multiple error correction data groups. The first column to the kth column correspond to the symbols in the original data block of the first error correction data group, which can be the first (1) symbol, the first (2) symbol,..., and the first (k) symbol in sequence. The k+1th column to the 2kth column correspond to the symbols in the original data block of the second error correction data group, which can be the second (1) symbol, the second (2) symbol,..., and the second (k) symbol in sequence. The 2k+1th column to the 3kth column correspond to the symbols in the original data block of the third error correction data group, which can be the third (1) symbol, the third (2) symbol,..., and the third (k) symbol in sequence. The 3k+1th column to the 4kth column correspond to the symbols in the original data block of the fourth error correction data group, which can be the fourth (1) symbol, the fourth (2) symbol,..., and the fourth (k) symbol in sequence.

[0139] The 4k+1th column to the 4n column correspond to the symbols in the error correction data block of the plurality of error correction data groups, n=k+2t, 4n=4k+8t, wherein the 4k+1th column to the 4k+2t column correspond to the symbols of the error correction data block in the first error correction data group, which can be the first (k+1) symbol, the first (k+2) symbol, …, the first (n) symbol in turn; the 4k+2t+1th column to the 4k+4t column correspond to the symbols of the error correction data block in the second error correction data group, which can be the second (k+1) symbol, the second (k+2) symbol, …, the second (n) symbol in turn; the 4k+4t+1th column to the 4k+6t column correspond to the symbols of the error correction data block in the third error correction data group, which can be the third (k+1) symbol, the third (k+2) symbol, …, the third (n) symbol in turn; the 4k+6t+1th column to the 4k+8t column (i.e., the 4n column) correspond to the symbols of the error correction data block in the fourth error correction data group, which can be the fourth (k+1) symbol, the fourth (k+2) symbol, …, the fourth (n) symbol in turn.

[0140] The data in the to-be-processed data block is sequentially interleaved based on the order of the symbols in the error correction data groups, which means that the symbols in the original data block of different error correction data groups are sequentially and alternately arranged in the original data area, and the symbols in the error correction data block of different error correction data groups are sequentially and alternately arranged in the error correction data area. Specifically, referring to another optional diagram of data interleaving shown in FIG. 6, taking the to-be-processed data block including four error correction data groups as an example, the data in the to-be-processed data block is as follows:

[0141] The 1st column to the 4k column correspond to the symbols in the original data block of the plurality of error correction data groups, wherein the 1st column corresponds to the first (1) symbol, the 2nd column corresponds to the second (1) symbol, the 3rd column corresponds to the third (1) symbol, and the 4th column corresponds to the fourth (1) symbol; the number of columns is alternately arranged in turn thereafter, that is, the 5th column corresponds to the first (2) symbol, the 6th column corresponds to the second (2) symbol, the 7th column corresponds to the third (2) symbol, and the 8th column corresponds to the fourth (2) symbol, and so on until the 4k-3th column to the 4k column, wherein the 4k-3th column corresponds to the first (k) symbol, the 4k-2th column corresponds to the second (k) symbol, the 4k-1th column corresponds to the third (k) symbol, and the 4k column corresponds to the fourth (k) symbol, wherein k is the number of symbols in an original data block.

[0142] The 4k+1th column to the 4n column correspond to the symbols in the error correction data block of the plurality of error correction data groups, n=k+2t, 4n=4k+8t, wherein the 4k+1th column corresponds to the first (k+1) symbol, the 4k+2th column corresponds to the second (k+1) symbol, the 4k+3th column corresponds to the third (k+1) symbol, and the 4k+4th column corresponds to the fourth (k+1) symbol; the number of columns is alternately arranged in turn thereafter until the 4n-3th column to the 4n column, wherein the 4n-3th column corresponds to the first (n) symbol, the 4n-2th column corresponds to the second (n) symbol, the 4n-1th column corresponds to the third (n) symbol, and the 4n column corresponds to the fourth (n) symbol.

[0143] In a further example, the to-be-processed data block includes two error correction data groups, a fifth error correction data group and a sixth error correction data group, each of which includes n symbols, the first k symbols are the symbols in the original data block, the k+1th symbol to the n symbol are the symbols in the error correction data block, the fifth n symbol represents the n symbol in the fifth error correction data group, and the sixth n symbol represents the n symbol in the sixth error correction data group, n and k are positive integers;

[0144] The data of different error correction data groups are sequentially interleaved based on the order of the symbols in the error correction data group, and the to-be-processed data block obtained is:

[0145] The first column to the 2k column correspond to the symbols in the original data block of the plurality of error correction data groups, wherein the first column corresponds to the fifth 1 symbol, the second column corresponds to the sixth 1 symbol, and the number of columns is alternately arranged in sequence until the 2k-1 column to the 2k column, wherein the 2k-1 column corresponds to the fifth k symbol, and the 2k column corresponds to the sixth k symbol;

[0146] The 2k+1 column to the 2n column correspond to the symbols in the error correction data block of the plurality of error correction data groups, n=k+2t, 2n=2k+4t, wherein the 2k+1 column corresponds to the fifth k+1 symbol, the 2k+2 column corresponds to the sixth k+1 symbol, and the number of columns is alternately arranged in sequence until the 2n-1 column to the 2n column, wherein the 2n-1 column corresponds to the fifth n symbol, and the 2n column corresponds to the sixth n symbol,

[0147] The to-be-processed data block is alternately arranged based on the order of the error correction data groups, which can further improve the error correction rate.

[0148] In a specific example, based on the different positions of the original data block and the error correction data block in the to-be-processed data block, the original data block and the error correction data block can be interleaved based on different hardware modules. Continuing to refer to the optional schematic diagram of the hardware module provided by the embodiment of the application shown in FIG. 8, the interleaving module can include an original data interleaving module and an error correction data interleaving module, wherein the original data interleaving module is used to interleave the original data block, and the error correction data interleaving module is used to interleave the error correction data block. Wherein, the error correction data interleaving module is connected to the encoding module, and then after the encoding module generates the error correction data block, the interleaving of the error correction data can be further performed, thereby generating the to-be-processed data block, which is transmitted and saved to the memory.

[0149] For interleaving of error correction data blocks, in order to make error correction data blocks in multiple error correction data groups be processed synchronously, in a data encoding process, the same number of encoding modules as the number of error correction data groups (or original data blocks) in a data block to be processed can be configured in hardware, wherein one error correction data group (or original data block) corresponds to one encoding module, so that all error correction data blocks in the data block to be processed are obtained by synchronous calculation using the encoding modules, and the obtained error correction data blocks are synchronously entered into an interleaving module for data interleaving. In a specific example, the interleaving module can support a bounded fault mechanism.

[0150] It can be understood that when corresponding to 4 error correction data groups (i.e. 4 encoding modules), the interleaving module needs to perform 4-way interleaving; when corresponding to 2 error correction data groups (i.e. 2 encoding modules), the interleaving module needs to perform 2-way interleaving.

[0151] It can be understood that corresponding to one original data group, the number of data blocks to be processed can be one or multiple, which can be determined based on the data amount of original data that can be accommodated by the original data group and the data block to be processed, for example, when the original data group is 512 bits (bit), and the original data accommodated by one data block to be processed is 256 bits, then the data block to be processed is 2.

[0152] Among them, based on the column data in the data block to be processed, the hardware transmission channel is aligned, and when there are multiple data blocks to be processed, the multiple data blocks to be processed are aligned in the column direction, so that the data blocks to be processed are transmitted in turn based on the hardware transmission channel.

[0153] In a specific example, based on the original data group matching a data amount of a burst, when the corresponding data block to be processed is multiple, it means that one column of data transmitted in a burst corresponds to multiple symbols of the data block to be processed. Correspondingly, in one column of data in the burst, different symbols correspond to different error correction data groups. For example, referring to a data structure diagram of a burst shown in FIG. 7, the data block to be processed is 2, and one column of data transmitted in a burst corresponds to 2 symbols, and the 2 symbols belong to the 2 data blocks to be processed respectively.

[0154] Step S130: transmitting the data block to be processed to a preset device based on the transmission rule of the data block to be processed;

[0155] The original data group is to-be-transmitted data or to-be-saved data. Correspondingly, the to-be-processed data block obtained after processing the original data group can be used for transmission to a preset position (such as a data receiving end) or transmission to a memory and saving. The difference is that the to-be-processed data block obtained after processing the to-be-transmitted data is subjected to data decoding and error correction after being transmitted to the data receiving end, so as to determine whether the data transmission process is wrong and correct the wrong data. The to-be-processed data block obtained after processing the to-be-saved data is saved after being transmitted to the memory, and data decoding and error correction are performed when reading out, so as to determine whether the saved data is wrong and correct the wrong data.

[0156] The transmission rule of the to-be-processed data block can include the correspondence between each column of data and the hardware port, so that each column of data is transmitted based on different hardware ports. Further, the transmission rule can further include the number of to-be-processed data blocks in a burst length transmission. For example, when a burst length corresponds to the data amount of a plurality of to-be-processed data blocks, a plurality of to-be-processed data blocks are sequentially transmitted in a burst length. In combination with the foregoing, the length of the original data group corresponds to the data amount of the original data that can be transmitted by matching the burst length of the hardware, so that the data of two to-be-processed data blocks is sequentially transmitted in a burst length, which corresponds to the data of an original data group being sequentially transmitted in a burst length.

[0157] In a further example, if transmitted to the memory, the number of transmission channels of the grain chip and the arrangement of the grain chip are also considered. To further improve the error correction capability of the scheme, when a to-be-processed data block includes a plurality of error correction data groups, the data of different error correction data groups transmitted by adjacent transmission channels in a grain chip is allowed, that is, the symbol data in the to-be-processed data block is alternately arranged based on the order of the error correction data groups. The corresponding arrangement mode can be referred to the foregoing description.

[0158] In a further example, the embodiment of the present application also provides a data processing method for correcting original data based on error correction data in a to-be-processed data block. Specifically, referring to the optional flowchart of another data processing method shown in FIG. 9, the data processing method comprises:

[0159] Step S200: obtaining a to-be-processed data block;

[0160] The to-be-processed data block is data received by a preset device or obtained from the preset device after being encoded and interleaved and transmitted to the preset device. For example, the to-be-processed data block can be data received by a receiving end, or data saved in a memory and read from the memory.

[0161] The to-be-processed data block is obtained based on error correction data groups, for example, is obtained by using the method described in the foregoing embodiments; the error correction data groups include original data blocks and error correction data blocks, the to-be-processed data block includes original data areas obtained by interleaving the original data blocks and error correction data areas obtained by interleaving the error correction data blocks, one symbol of data in the original data block is arranged in one column of data in the original data area, one symbol of data in the error correction data block is arranged in one column of data in the error correction data area, and the data in the to-be-processed data block is aligned based on rows, wherein one column of data in the to-be-processed data block is used for transmission based on one transmission channel, and one row of data is used for transmission based on one shot.

[0162] In the process of obtaining the to-be-processed data block, the obtaining can be performed based on a transmission rule of hardware. The transmission rule can include obtaining each column of data of the to-be-processed data block from different hardware ports based on the correspondence between each column of data and the hardware ports. Specifically, different data in the to-be-processed data block is transmitted based on different transmission channels, that is, in the hardware transmission channels, a part of the transmission channels is used for transmitting original data, and a part of the transmission channels is used for transmitting error correction data. Correspondingly, in the specific obtaining process, the data in the original data area is obtained from the original data transmission channel, and the data in the error correction data area is obtained from the error correction data transmission channel. Referring to another optional structure diagram of a hardware module shown in FIG. 11, taking reading data from the memory as an example, the original data and the error correction data can be distinguished based on the transmission channels of the data when reading.

[0163] Further, the transmission rule can further include obtaining a corresponding number of to-be-processed data blocks based on the number of to-be-processed data blocks transmitted based on one burst length, for example, when a plurality of (for example, 2) to-be-processed data blocks correspond to one burst length, the data of the plurality of (for example, 2) to-be-processed data blocks is transmitted in turn corresponding to one burst length.

[0164] In this way, the column data in the to-be-processed data block is aligned based on the hardware transmission channel, and when there are a plurality of to-be-processed data blocks, the plurality of to-be-processed data blocks are aligned based on the column direction, so that the to-be-processed data blocks can be obtained in turn based on the data transmission sequence in the hardware transmission channel.

[0165] Correspondingly, when the number of to-be-processed data blocks transmitted based on one burst length is a plurality, it means that one column of data transmitted in one burst length corresponds to a plurality of symbols of the to-be-processed data blocks. Correspondingly, in one column of data in the burst length, different symbols correspond to different error correction data groups. For example, when there are two to-be-processed data blocks, one column of data transmitted in one burst length corresponds to two symbols, and the two symbols belong to the two to-be-processed data blocks respectively.

[0166] The one row of data is used for transmission based on one beat in the embodiment of the application, and the data required for transmission is controlled based on timing. In the transmission of the to-be-processed data block, the data in the error correction data group is based on row alignment, and the data transmission of the same error correction data group can be kept synchronous in timing.

[0167] It should be noted that when the to-be-processed data block corresponding to one burst length of data is multiple, that is, the number of to-be-processed data blocks for one burst length transmission is multiple, and one column of data transmitted in one burst length corresponds to multiple symbols of the to-be-processed data block, the processing procedure corresponding to the present step can include: obtaining one burst length of data; based on the symbol length in the to-be-processed data block, the one burst length of data is segmented into multiple to-be-processed data blocks, and then the multiple to-be-processed data blocks are obtained.

[0168] Step S210: deinterleaving the to-be-processed data block to obtain an error correction data group;

[0169] The error correction data group includes an original data block and an error correction data block, wherein the original data block is a data block obtained by segmenting the original data group and meeting the required number of data bits of the preset encoding mode, and the error correction data block is a redundant data block obtained based on a specific encoding algorithm based on the original data in the original data block.

[0170] In a specific example, the original data block and the error correction data block are obtained based on different channels based on the to-be-processed data block, and the deinterleaving of the original data block and the error correction data block can be further performed based on different hardware. Specifically, the original data deinterleaving module can be configured to perform the data deinterleaving of the original data block, and at the same time, the error correction data deinterleaving module can be configured to perform the data deinterleaving of the error correction data block. Referring to FIG. 11, the original data deinterleaving module and the error correction data deinterleaving module can be configured in the deinterleaving module, so as to respectively perform the deinterleaving of the original data and the error correction data.

[0171] In a specific deinterleaving process, when the to-be-processed data block includes multiple error correction data groups, the symbol data belonging to different error correction data groups and the corresponding arrangement order thereof can be determined based on a preset data arrangement order (for example, the reverse order of the data arrangement order in the interleaving process) in the present step.

[0172] Specifically, when the data of different error correction data groups in the to-be-processed data block is sequentially arranged based on the order of the error correction data groups, the original data block and / or the error correction data block in different error correction data groups can be sequentially extracted; when the data of different error correction data groups in the to-be-processed data block is sequentially interleaved based on the symbol data in the error correction data group, the symbols of the original data block and / or the symbols of the error correction data block in different error correction data groups can be extracted based on the interleaving order in the interleaving process.

[0173] The arrangement of the original data block and the error correction data block in the to-be-processed data block is described above. Based on the arrangement, the arrangement of the symbols in each error correction data group in the to-be-processed data block can be determined, and thus the deinterleaving of the to-be-processed data block can be performed based on the arrangement of the symbols.

[0174] Step S220: correcting data errors of the original data block in the error correction data group based on the error correction data block in the error correction data group.

[0175] The error correction data block is a redundant data block obtained based on the original data in the original data block and a specific encoding algorithm. Correspondingly, the original data block can be corrected based on a specific decoding algorithm.

[0176] It can be understood that the specific encoding algorithm can correct the original data block based on a specific decoding algorithm corresponding thereto. Different specific encoding algorithms have different error correction capabilities and correspond to different specific decoding algorithms. For example, the decoding manner corresponding to the error correction data of RS8 (20, 16) encoding that can correct 2 symbols is different from the decoding manner corresponding to the error correction data of RS8 (40, 32) encoding that can correct 4 symbols. Therefore, in hardware, the specific decoding algorithm corresponding to the specific encoding algorithm is also determined. Correspondingly, the specific decoding algorithm can be fixedly configured in the hardware, for example, a specific hardware can be configured as a decoding module to execute the specific decoding algorithm. Referring to FIG. 11, a decoding module is configured to decode data, and the decoding module can be connected to the deinterleaving module to decode the deinterleaved data.

[0177] Specifically, the data errors of the original data block in the error correction data group can be corrected in the following process: based on the error correction data block in the error correction data group, the position of the error data in the original data block is calculated; and the data error at the position of the error data in the original data block is corrected.

[0178] It can be understood that based on the specific decoding algorithm, the position of the error data in the original data block can be determined by calculating the original data in the original data block and the error correction data in the error correction data block. In binary data, data is either “0” or “1”, and thus after the position of the error data in the original data block is determined, the data at the position can be corrected by converting the error data, for example, the data is converted from “0” to “1” or from “1” to “0”.

[0179] In hardware, an error correction module can be fixedly configured in the hardware to execute the data correction. Referring to FIG. 11, an error correction module connected to the decoding module is configured to correct errors in data.

[0180] Step S230: generating the original data group based on the original data block after error correction;

[0181] The original data group can be understood as the data to be transmitted before transmission in the data transmission process, or the data to be saved before storage in the process of storing data into the memory. In a specific example, when the original data group includes a plurality of original data blocks, the original data group can be generated based on a preset rule to combine the original data blocks.

[0182] It can be understood that after the original data group is generated, the original data group can be further transmitted to a target device, such as a CPU (Central Processing Unit) or the like.

[0183] In a further example, the data processing method of the embodiment of the application can also count the error data to determine the error type of the system. Specifically, referring to another optional flowchart of another data processing method shown in FIG. 10, the data processing method can further include:

[0184] Step S240: counting the position of the error data in the data block to be processed to determine the error type of the data;

[0185] Based on the embodiment of the application, the symbol data of the error correction data group is arranged based on the column data in the data block to be processed, and one column data is used for transmission based on one transmission channel. Accordingly, the specific column position of the data can be determined based on the position of the error data in one or more data blocks to be processed, and the error type of the data can be determined.

[0186] For example, when the error data set appears in some transmission channels, it is considered that the error type of the data is bounded fault (boundary fault). Correspondingly, the error data at this time appears in a preset number of column data sets in one or more data blocks to be processed, and when the error data of a plurality of data blocks to be processed is counted, the column position to which the error data belongs corresponds to each other in a plurality of data blocks to be processed. For example, when the error data set is isolated in the 2 transmission channels based on the bounded fault mechanism, the error data appears in the 2 column data sets in a plurality of data blocks to be processed, and the column position to which the error data belongs corresponds to the same transmission channel.

[0187] When the error data appears in different transmission channels, it is considered that the error type of the data is not bounded fault. Correspondingly, the error data at this time appears in a plurality of column data in the data block to be processed.

[0188] Specifically, the execution flow of the step can include: counting the position of the error data in the to-be-processed data block; judging whether the error data is located in a preset number of column data, if yes, the error data is a preset error (for example, can be a bounded fault); if no, excluding the preset error.

[0189] It should be noted that the error data in the to-be-processed data block can be error data in the original data or error data in the error correction data. Correspondingly, in the counting process, in addition to counting the error data in the original data, the error data in the error correction data can also be counted.

[0190] When counting the error data, the number of the to-be-processed data blocks can be determined based on the hardware and software configuration. In an optional example, the number of the to-be-processed data blocks can be determined based on the number of the to-be-processed data blocks corresponding to the original data group, that is, when the original data group corresponds to two to-be-processed data blocks, the error data can be counted based on the two to-be-processed data blocks when counting the error data, that is, the position of the error data in the to-be-processed data block corresponding to the original data group is counted. The preset number is determined based on the configuration mechanism of the preset error. When the preset error isolates the error data in the two transmission channels, the preset number is two. The preset error is, for example, a bounded fault. When the corresponding judgment result is yes, the error data is considered to be a preset error. When the corresponding judgment result is no, the preset error is excluded.

[0191] In a further example, the embodiment of the application further configures an error mode counting module at the hardware level, so as to realize the counting of the error data and the judgment of the error type based on the configured error mode counting module. Referring to FIG. 11, an error information counting module connected with the error correction module can be configured to realize the counting of the error information and the judgment of the error type.

[0192] It can be understood that counting the error position and determining the error type is an important prerequisite for improving the error correction capability. By analyzing the error and selecting a suitable error correction method, the efficiency and reliability of the system can be improved.

[0193] It should be noted that in some examples of symbol data corresponding to the arrangement of storage chips (i.e., one symbol data corresponding to the transmission channel of one storage chip, which is reflected in one or more rows in the parallel multiple columns in the to-be-processed data block), in order to determine the position of the specific error data, the symbol where each error data is located and its position in the symbol need to be calculated, and a large amount of error data and its corresponding symbol and position in the symbol need to be repeatedly calculated and recorded, thereby consuming a large amount of software and hardware resources. Compared with the symbol data based on column arrangement in the embodiment of the present application, the embodiment of the present application can simply and quickly determine the position of the error data and judge the error type. Correspondingly, the hardware implementation or software time corresponding to the error type judgment of the embodiment of the present application is relatively simple, and the software and hardware cost is small.

[0194] The error pattern statistical module provided in the embodiment of the present application can collect more error data and information corresponding to the error data (such as the position of the error data) with smaller cost, and then provide data support for establishing a system-level error model, so as to provide convenience for subsequent research and improvement based on the system-level error model.

[0195] Next, based on a specific example, the data processing method and its corresponding effect of the embodiment of the present application in the scenario of storing data to the memory are further described.

[0196] For a hardware system with 40 transmission channels (the storage chip can be an X4 particle chip or an X8 particle chip), the to-be-processed data block includes at least 40 symbols, of which 8 symbols are error correction data. The error correction data group interleave in this example can be a four-way RS8(10, 8) encoded error correction data group interleave, or a two-way RS8(20, 16) encoded error correction data group interleave, or a one-way RS8(40, 32) encoded error correction data group interleave. Regardless of the interleave mode, it can support correcting up to 4 symbols of data, and the symbol data can be located on the same particle chip or different particle chips.

[0197] The symbol bit number corresponding to the interleaving mode in the example can be 4 bits, 8 bits, 16 bits, etc. Referring to the data structure reference diagram shown in FIG. 12 for transmitting a burst length to an X4 granular chip, from left to right, the symbol data is 4 bits, 8 bits, and 16 bits, respectively. The burst length can be 16 bits, 32 bits, etc. Taking 16 bits as an example, when the symbol data is 4 bits, referring to the shaded area shown in symbol 3 in FIG. 12, a symbol data is arranged vertically (i.e., arranged in the column direction), the number of symbols corresponding to one column of data is 4, and the burst length can transmit 4 data blocks to be processed; when the symbol data is 8 bits, referring to the shaded area shown in symbol 4 in FIG. 12, a symbol data is arranged vertically (i.e., arranged in the column direction), the number of symbols corresponding to one column of data is 2, and the burst length can transmit 2 data blocks to be processed; when the symbol data is 16 bits, referring to the shaded area shown in symbol 5 in FIG. 12, a symbol data is arranged vertically (i.e., arranged in the column direction), the number of symbols corresponding to one column of data is 1, and the burst length can transmit 1 data block to be processed.

[0198] Taking 8 bits as the symbol bit number and 512 bits as the original data group as an example, FIG. 13 shows a data structure reference diagram of a four-way RS8(10, 8) encoded error correction data group interleaving a burst length transmission, in which the first eight beats of Burst 0-7 correspond to the transmission of one data block to be processed, and the last eight beats of Burst 8-15 correspond to the transmission of another data block to be processed.

[0199] As can be seen, the 8-bit data corresponding to eight beats of a transmission channel is one 8-bit symbol, and there are four error correction data groups interleaved in the first eight beats. In the data block to be processed, the left 32 columns are used to configure the original data, and the right 8 columns are used to configure the error correction data. Correspondingly, in a specific storage chip, 0-7 of an X4 granular chip (or 0-3 of an X8 granular chip) can be used as the storage location corresponding to the original data of the data block to be processed, and 8-9 of the X4 granular chip (or 4 of the X8 granular chip) can be used as the storage location corresponding to the error correction data of the data block to be processed.

[0200] Continuing to refer to FIG. 13, 0-63 in the original data in the to-be-processed data block is taken as an original data block, 0-15 in the error correction data is taken as an error correction data block corresponding to the original data block, and the original data block and the error correction data block can be taken as error correction data group 0; 64-127 in the original data is taken as an original data block, 16-31 in the error correction data is taken as an error correction data block corresponding to the original data block, and the original data block and the error correction data block can be taken as error correction data group 1; 128-191 in the original data is taken as an original data block, 32-47 in the error correction data is taken as an error correction data block corresponding to the original data block, and the original data block and the error correction data block can be taken as error correction data group 2; and 192-255 in the original data is taken as an original data block, 48-63 in the error correction data is taken as an error correction data block corresponding to the original data block, and the original data block and the error correction data block can be taken as error correction data group 3.

[0201] In the to-be-processed data block, each error correction data group uses an RS8(10, 8) error correction code and can correct any 1 eight-bit symbol.

[0202] Specifically, taking 32-39, 96-103, 168-175 and 232-239 in the original data as examples, 32-39 in the original data belongs to error correction data group 0, 96-103 in the original data belongs to error correction data group 1, 168-175 in the original data belongs to error correction data group 2, and 232-239 in the original data belongs to error correction data group 3, and one symbol of data can be corrected based on one error correction data group, and the above error data can be corrected.

[0203] In addition, when one bounded fault occurs in one X4 granule chip or X8 granule chip, one random error is also supported to be corrected.

[0204] Continuing to refer to FIG. 13, when a bounded fault occurs in the x4 granule chip 7 (for the x8 granule chip 3), one column of error data exists in error correction data group 1 and error correction data group 2, for example, one symbol of data 120-127 in the original data and one symbol of data 184-191 in the original data are error data, at this time, one symbol of data can be corrected based on one error correction data group, and the error data of the two symbols can be completely corrected based on the error correction algorithm.

[0205] At this time, if one random error occurs in 11 in the error correction data, since error correction data group 0 (green) has no other error, the random error of 11 in the error correction data can also be corrected based on the corresponding error correction algorithm, and finally the entire data belongs to correctable error (CE).

[0206] Further, taking 8 bits as a symbol bit number and 512 bits as an original data group as an example, Fig. 14 shows a reference diagram of a data structure of a burst length transmission under interleaving of two RS8 (20, 16) encoded error correction data groups, wherein the first eight beats of Burst 0-7 correspond to transmission of a to-be-processed data block, and the last eight beats of Burst 8-15 correspond to transmission of another to-be-processed data block.

[0207] Continuing to refer to Fig. 14, 0-127 in the original data in the to-be-processed data block is taken as an original data block, and 0-31 in the error correction data is taken as an error correction data block corresponding to the original data block, which can be taken as error correction data group 5; 128-255 in the original data is taken as an original data block, and 32-63 in the error correction data is taken as an error correction data block corresponding to the original data block, which can be taken as error correction data group 6.

[0208] In the to-be-processed data block, each error correction data group uses RS8 (20, 16) error correction code, which can correct any 2 8-bit symbols.

[0209] Specifically, taking 32-39, 96-103, 160-167 and 224-231 in the original data as examples (i.e., a total of 4 8-bit symbols are wrong, see the shaded area in Fig. 14), 32-39 and 96-103 in the original data belong to error correction data group 5, and 160-167 and 224-231 in the original data belong to error correction data group 6, and based on the error correction capability of 2 symbols per error correction data group, the above error data can be corrected.

[0210] That is, when data errors occur in two chips, the method provided by the embodiment of the application can also perform error correction.

[0211] It can be understood that the data mapping and error correction capability of the to-be-processed data blocks corresponding to the first eight beats and the last eight beats are completely consistent, and therefore, the scheme provided by the embodiment of the application can correct all errors on a maximum of 4 transmission channels.

[0212] Therefore, for a hardware system of 40 transmission channels, the embodiment of the application can correct:

[0213] bounded faults of 2 memory chips, each with 2 transmission channels corresponding to data errors;

[0214] bounded faults of 3 memory chips, one of which has 2 transmission channels corresponding to data errors, and the other two each have 1 transmission channel corresponding to data errors;

[0215] 4 memory chips have bounded fault, each has 1 transmission channel corresponding data error.

[0216] In further example, for hardware system with 36 transmission channels (the memory chip can be X4 particle chip), the data block to be processed includes at least 36 symbols, wherein 4 symbols are error correction data, the error correction data group interleaving in this example can be two-way RS8(18, 16) encoded error correction data group interleaving, or one-way RS8(36, 32) encoded error correction data group interleaving; no matter what kind of interleaving mode, it can support correcting up to 2 symbols of data, and the symbol data can be located in the same particle chip, or can be located on different particle chips.

[0217] And for the bounded fault characteristic, this example can correct one x4 particle that supports bounded fault, and has a probability of correcting two x4 particles (wherein the two particles only have 1 channel corresponding data error).

[0218] It should be noted that the embodiment of the present application can also process errors on the link, such as when adjacent symbols do not belong to the same error correction data group, the data error caused by inter-symbol interference can be corrected. In the traditional way, the same data on two adjacent transmission channels must belong to the same error correction data group, and if crosstalk occurs on two adjacent transmission channels, it will introduce 1 error on each of the two symbols, and further may cause an uncorrectable error (UE).

[0219] Therefore, for a hardware system with 36 transmission channels, the embodiment of the present application can correct:

[0220] 2 memory chips have bounded fault, each has 1 transmission channel corresponding data error;

[0221] 1 memory chip has bounded fault, and 2 transmission channels have corresponding data error.

[0222] Next, the data processing device provided by the embodiment of the present application is introduced, and the data processing device described below can be considered as a software function module or hardware function module required to be set to realize the data processing method provided by the embodiment of the present application; the content of the data processing device described below can be mutually corresponding to the method content and hardware module content described above.

[0223] In optional implementation, Fig. 15 shows an optional block diagram of the data processing device provided by the embodiment of the present application, which is used to realize the data processing method with data interleaving, as shown in Fig. 15, the data processing device can include:

[0224] The first data acquisition module 300 is configured to acquire an original data group;

[0225] The error correction data block generation module 310 is configured to generate an original data block and an error correction data block corresponding to the original data block based on the original data group, wherein one original data block and the error correction data block corresponding to the original data block form one error correction data group.

[0226] The interleaving module 320 is configured to interleave the error correction data group to obtain a to-be-processed data block, the to-be-processed data block including an original data area obtained by interleaving the original data block and an error correction data area obtained by interleaving the error correction data block, wherein one column of data in the to-be-processed data block is used for transmission based on one transmission channel, and one row of data is used for transmission based on one tap, wherein one symbol data in the original data block is arranged in one column of data in the original data area, one symbol data in the error correction data block is arranged in one column of data in the error correction data area, and the data in the to-be-processed data block is aligned based on rows.

[0227] The data transmission module 330 is configured to transmit the to-be-processed data block to a preset device based on a transmission rule of the to-be-processed data block.

[0228] Optionally, the error correction data block generation module 310 is configured to generate an original data block and an error correction data block corresponding to the original data block based on the original data group, and the generation includes:

[0229] The data segmentation module is configured to segment the original data group into original data blocks with a preset bit number.

[0230] The encoding module is configured to encode the original data block to generate an error correction data block corresponding to the data block.

[0231] Optionally, the to-be-processed data block includes a plurality of error correction data groups, and the interleaving module 320 is configured to interleave the error correction data groups to obtain the to-be-processed data block, and specifically, arrange data of different error correction data groups in sequence based on an order of the error correction data groups, or interleave and arrange data of different error correction data groups in sequence based on an order of symbols in the error correction data groups.

[0232] Optionally, the to-be-processed data block includes four error correction data groups, respectively a first error correction data group, a second error correction data group, a third error correction data group and a fourth error correction data group, each error correction data group includes n symbols, the first k symbols are symbols in the original data block, the k+1th symbol to the n symbol are symbols in the error correction data block, the first n symbol represents the n symbol in the first error correction data group, the second n symbol represents the n symbol in the second error correction data group, the third n symbol represents the n symbol in the third error correction data group, and the fourth n symbol represents the n symbol in the fourth error correction data group, n and k are positive integers;

[0233] The interleaving module 320 is configured to sequentially interleave data of different error correction data groups based on the order of the symbols in the error correction data groups, and obtain a to-be-processed data block as follows:

[0234] The first column to the 4k column correspond to symbols in the original data block of the multiple error correction data groups, wherein the first column corresponds to the first 1 symbol, the second column corresponds to the second 1 symbol, the third column corresponds to the third 1 symbol, and the fourth column corresponds to the fourth 1 symbol, and the number of columns is alternately arranged in sequence until the 4k-3 column to the 4k column, wherein the 4k-3 column corresponds to the first k symbol, the 4k-2 column corresponds to the second k symbol, the 4k-1 column corresponds to the third k symbol, and the 4k column corresponds to the fourth k symbol.

[0235] The 4k+1 column to the 4n column correspond to symbols in the error correction data block of the multiple error correction data groups, n=k+2t, 4n=4k+8t, wherein the 4k+1 column corresponds to the first k+1 symbol, the 4k+2 column corresponds to the second k+1 symbol, the 4k+3 column corresponds to the third k+1 symbol, and the 4k+4 column corresponds to the fourth k+1 symbol, and the number of columns is alternately arranged in sequence until the 4n-3 column to the 4n column, wherein the 4n-3 column corresponds to the first n symbol, the 4n-2 column corresponds to the second n symbol, the 4n-1 column corresponds to the third n symbol, and the 4n column corresponds to the fourth n symbol.

[0236] Optionally, the to-be-processed data block includes two error correction data groups, respectively a fifth error correction data group and a sixth error correction data group, each error correction data group includes n symbols, the first k symbols are symbols in the original data block, the k+1th symbol to the n symbol are symbols in the error correction data block, the fifth n symbol represents the n symbol in the fifth error correction data group, and the sixth n symbol represents the n symbol in the sixth error correction data group, n and k are positive integers.

[0237] The interleaving module 320 is configured to sequentially interleave data of different error correction data groups based on the order of the symbols in the error correction data groups, and obtain a to-be-processed data block as follows:

[0238] The first column to the 2kth column correspond to symbols in the original data block of the plurality of error correction data groups, wherein the first column corresponds to the first symbol, the second column corresponds to the second symbol, and the number of columns is alternately arranged in sequence until the 2k-1th column to the 2kth column, wherein the 2k-1th column corresponds to the kth symbol, and the 2kth column corresponds to the (k+1)th symbol;

[0239] The 2k+1th column to the 2nth column correspond to symbols in the error correction data block of the plurality of error correction data groups, n=k+2t, 2n=2k+4t, wherein the 2k+1th column corresponds to the (k+1)th symbol, the 2k+2th column corresponds to the (k+2)th symbol, and the number of columns is alternately arranged in sequence until the 2n-1th column to the 2nth column, wherein the 2n-1th column corresponds to the nth symbol, and the 2nth column corresponds to the (n+1)th symbol.

[0240] Optionally, the interleaving module 320 is configured to interleave the error correction data groups to obtain a to-be-processed data block, and the to-be-processed data block comprises:

[0241] The data in the original data block is arranged in an original data area of the to-be-processed data block.

[0242] The data in the error correction data block is arranged in an error correction data area of the to-be-processed data block.

[0243] Optionally, a burst length corresponds to the data amount of a plurality of to-be-processed data blocks, and the data transmission module 330 is configured to transmit the to-be-processed data blocks to a preset device based on a transmission rule of the to-be-processed data blocks, and specifically, the data of the plurality of to-be-processed data blocks is transmitted in sequence in one burst length.

[0244] Optionally, one to-be-processed data block comprises a plurality of error correction data groups, and the data transmission module 330 is configured to transmit the to-be-processed data blocks to a preset device based on a transmission rule of the to-be-processed data blocks, and specifically, the data of different error correction data groups is transmitted in adjacent transmission channels in one particle chip.

[0245] In an optional implementation, FIG. 16 shows an optional block diagram of another data processing apparatus provided by an embodiment of the present application, which is used to implement the data processing method with data deinterleaving. As shown in FIG. 16, the data processing apparatus can comprise:

[0246] The second data acquisition module 400 is configured to acquire a to-be-processed data block, the to-be-processed data block is obtained based on error correction data group interleaving, the error correction data group comprises an original data block and an error correction data block, the to-be-processed data block comprises original data areas obtained by interleaving the original data block and error correction data areas obtained by interleaving the error correction data block, one symbol data in the original data block is arranged in one column of data in the original data area, one symbol data in the error correction data block is arranged in one column of data in the error correction data area, and data in the to-be-processed data block is based on line alignment, wherein one column of data in the to-be-processed data block is used for transmission based on one transmission channel, and one line of data is used for transmission based on one shot.

[0247] The deinterleaving module 410 is configured to deinterleave the to-be-processed data block to obtain an error correction data group.

[0248] The error correction module 420 is configured to correct data errors of the original data block in the error correction data group based on the error correction data block in the error correction data group.

[0249] The original data generation module 430 is configured to generate an original data group based on the original data block after error correction.

[0250] Optionally, the second data acquisition module 400 is configured to acquire a to-be-processed data block, and specifically, the to-be-processed data block is acquired based on a hardware transmission rule.

[0251] The transmission rule comprises:

[0252] Based on the correspondence between each column of data and the hardware port, each column of data of the to-be-processed data block is acquired from different hardware ports.

[0253] Based on the number of to-be-processed data blocks transmitted based on a burst length, a corresponding number of to-be-processed data blocks are acquired.

[0254] Optionally, the second data acquisition module 400 is configured to acquire a to-be-processed data block, and specifically comprises:

[0255] Acquire data of a burst length;

[0256] Based on the symbol length in the to-be-processed data block, the data of the burst length is divided into a plurality of to-be-processed data blocks.

[0257] Optionally, the to-be-processed data block comprises a plurality of error correction data groups, and the deinterleaving module 410 is configured to deinterleave the to-be-processed data block to obtain an error correction data group, and specifically, the symbol data belonging to different error correction data groups and the corresponding arrangement order are determined based on a preset data arrangement order.

[0258] Optionally, the deinterleaving module 410 is configured to determine the symbol data belonging to different error correction data groups and the corresponding arrangement order based on a preset data arrangement order, including:

[0259] When the data of different error correction data groups in the to-be-processed data block are sequentially arranged based on the order of the error correction data groups, the original data block and / or the error correction data block in the different error correction data groups are sequentially extracted;

[0260] Alternatively,

[0261] When the data of different error correction data groups in the to-be-processed data block are sequentially interleaved based on the symbol data in the error correction data groups, the symbol of the original data block and / or the symbol of the error correction data block in the different error correction data groups are extracted based on the interleaving order in the interleaving process

[0262] Optionally, the error correction module 420 is configured to correct the data error of the original data block in the error correction data group based on the error correction data block in the error correction data group, including:

[0263] Based on the error correction data block in the error correction data group, the position of the error data in the original data block is calculated;

[0264] The data error at the error data position of the original data block is corrected.

[0265] Optionally, the original data group includes a plurality of original data blocks, and the original data generation module 430 is configured to generate an original data group based on the original data block after error correction, specifically, the original data group is generated by combining the original data blocks based on a preset rule.

[0266] Optionally, the data processing apparatus further includes:

[0267] The error information statistical module 440 is configured to count the position of the error data in the plurality of original data blocks to determine the error type of the data.

[0268] Optionally, the error information statistical module 440 is configured to count the position of the error data in the plurality of original data blocks to determine the error type of the data, including:

[0269] Count the position of the error data in the plurality of original data blocks;

[0270] Determine whether the error data is located in a preset number of column data, if yes, the error data is a preset error; if not, the preset error is excluded.

[0271] The embodiment of the present application further provides a memory controller, which can be configured with the data processing apparatus with the interleaving module provided by the above embodiment, and / or the memory controller can be configured with the data processing apparatus with the deinterleaving module provided by the above embodiment.

[0272] The embodiment of the present application further provides an electronic device, which can include the memory controller.

[0273] The embodiment of the present application further provides a storage medium, which stores one or more computer executable instructions, and the one or more computer executable instructions are executed to implement the data processing method with the interleaving processing and / or the data processing method with the deinterleaving processing.

[0274] The embodiment of the present application further provides a computer program product, which includes one or more computer executable instructions, and the one or more computer executable instructions are executed to implement the data processing method with the interleaving processing and / or the data processing method with the deinterleaving processing.

[0275] Optionally, the electronic device further includes an external crystal oscillator, which is used to provide a reference clock signal for the chip when the chip is powered on and the phase-locked loop is not started.

[0276] The above describes a plurality of embodiment schemes provided by the embodiment of the present application, and each optional mode introduced by each embodiment scheme can be combined, cross-referenced in the case of no conflict, thereby extending a plurality of possible embodiment schemes, which can be considered as the embodiment schemes disclosed and published by the embodiment of the present application.

[0277] Although the embodiment of the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A data processing method, characterized by, The method comprises the following steps: obtaining an original data group; generating original data blocks and error correction data blocks corresponding to the original data blocks based on the original data group, wherein an original data block and an error correction data block corresponding to the original data block form an error correction data group; interleaving the error correction data groups to obtain a to-be-processed data block, the to-be-processed data block comprising an original data area obtained by interleaving the original data blocks and an error correction data area obtained by interleaving the error correction data blocks, one column of data in the to-be-processed data block being used for transmission based on a transmission channel and one row of data being used for transmission based on a tap, wherein one symbol data in the original data block is arranged in one column of data in the original data area, one symbol data in the error correction data block is arranged in one column of data in the error correction data area, and the data in the to-be-processed data block is aligned based on rows; transmitting the to-be-processed data block to a preset device based on a transmission rule of the to-be-processed data block.

2. The method of claim 1, wherein, The generating of the original data blocks and the error correction data blocks corresponding to the original data blocks based on the original data group comprises the following steps: dividing the original data group into original data blocks with a preset number of bits; encoding the original data blocks to generate error correction data blocks corresponding to the original data blocks.

3. The method according to claim 1 or 2, characterized in that, The to-be-processed data block comprises a plurality of error correction data groups; the interleaving of the error correction data groups to obtain the to-be-processed data block comprises the following steps: sequentially arranging the data of different error correction data groups based on the order of the error correction data groups, or sequentially interleaving the data of different error correction data groups based on the order of the symbols in the error correction data groups.

4. The method of claim 3, wherein, The to-be-processed data block comprises four error correction data groups, namely a first error correction data group, a second error correction data group, a third error correction data group and a fourth error correction data group, each error correction data group comprising n symbols, the first k symbols being symbols in the original data blocks, the k+1th symbol to the n symbol being a symbol in the error correction data blocks, the first n symbol representing the n symbol in the first error correction data group, the second n symbol representing the n symbol in the second error correction data group, the third n symbol representing the n symbol in the third error correction data group, and the fourth n symbol representing the n symbol in the fourth error correction data group, n and k being positive integers. The to-be-processed data block obtained by sequentially interleaving the data of different error correction data groups based on the order of the symbols in the error correction data groups is as follows: the first column to the 4kth column correspond to the symbols in the original data blocks of the plurality of error correction data groups, wherein the first column corresponds to the first 1 symbol, the second column corresponds to the second 1 symbol, the third column corresponds to the third 1 symbol, the fourth column corresponds to the fourth 1 symbol, and the number of columns is alternately arranged in sequence until the 4k-3th column to the 4kth column, wherein the 4k-3th column corresponds to the first k symbol, the 4k-2th column corresponds to the second k symbol, the 4k-1th column corresponds to the third k symbol, and the 4kth column corresponds to the fourth k symbol. The 4k+1th column to the 4n th column correspond to the symbols in the error correction data block of the plurality of error correction data groups, n=k+2t, 4n=4k+8t, wherein the 4k+1th column corresponds to the first k+1 symbol, the 4k+2th column corresponds to the second k+1 symbol, the 4k+3th column corresponds to the third k+1 symbol, the 4k+4th column corresponds to the fourth k+1 symbol, and the number of columns is alternately arranged in sequence until the 4n-3th column to the 4n th column, wherein the 4n-3th column corresponds to the first n symbol, the 4n-2th column corresponds to the second n symbol, the 4n-1th column corresponds to the third n symbol, and the 4n th column corresponds to the fourth n symbol.

5. The method of claim 3, wherein, The to-be-processed data block includes two error correction data groups, which are a fifth error correction data group and a sixth error correction data group, and each error correction data group includes n symbols, the first k symbols are the symbols in the original data block, the k+1th symbol to the n th symbol are the symbols in the error correction data block, the fifth n symbol represents the n th symbol in the fifth error correction data group, and the sixth n symbol represents the n th symbol in the sixth error correction data group, n and k are positive integers; The to-be-processed data block obtained by sequentially interleaving the data of different error correction data groups based on the order of the symbols in the error correction data groups is: The 1st column to the 2kth column correspond to the symbols in the original data block of the plurality of error correction data groups, wherein the 1st column corresponds to the fifth 1 symbol, the 2nd column corresponds to the sixth 1 symbol, and the number of columns is alternately arranged in sequence until the 2k-1th column to the 2kth column, wherein the 2k-1th column corresponds to the fifth k symbol, and the 2kth column corresponds to the sixth k symbol; The 2k+1th column to the 2n th column correspond to the symbols in the error correction data block of the plurality of error correction data groups, n=k+2t, 2n=2k+4t, wherein the 2k+1th column corresponds to the fifth k+1 symbol, the 2k+2th column corresponds to the sixth k+1 symbol, and the number of columns is alternately arranged in sequence until the 2n-1th column to the 2n th column, wherein the 2n-1th column corresponds to the fifth n symbol, and the 2n th column corresponds to the sixth n symbol.

6. The method of claim 1 or 2, wherein, The interleaving of the error correction data groups to obtain a to-be-processed data block includes: Arranging the data in the original data block in the original data area of the to-be-processed data block; Arranging the data in the error correction data block in the error correction data area of the to-be-processed data block.

7. The method according to claim 1 or 2, characterized in that, A burst length corresponds to the data amount of a plurality of to-be-processed data blocks, and the to-be-processed data blocks are transmitted to a preset device based on the transmission rule of the to-be-processed data blocks, specifically, the data of a plurality of to-be-processed data blocks is transmitted in sequence in a burst length.

8. The method of claim 7, wherein, When a to-be-processed data block includes a plurality of error correction data groups, the to-be-processed data blocks are transmitted to a preset device based on the transmission rule of the to-be-processed data blocks, specifically, the data of different error correction data groups is transmitted in adjacent transmission channels in a particle chip.

9. A data processing method, characterized by, It includes: The method comprises the following steps: obtaining a to-be-processed data block, wherein the to-be-processed data block is obtained based on error correction data group interleaving, the error correction data group comprises an original data block and an error correction data block, the to-be-processed data block comprises original data areas obtained by interleaving the original data block and error correction data areas obtained by interleaving the error correction data block, one symbol data in the original data block is arranged in one column of data in the original data area, one symbol data in the error correction data block is arranged in one column of data in the error correction data area, and the data in the to-be-processed data block is based on row alignment, wherein one column of data in the to-be-processed data block is used for transmission based on one transmission channel, and one row of data is used for transmission based on one shot; de-interleaving the to-be-processed data block to obtain the error correction data group; correcting data errors of the original data block in the error correction data group based on the error correction data block in the error correction data group; generating an original data group based on the original data block after error correction.

10. The method of claim 9, wherein, The to-be-processed data block is obtained based on a hardware transmission rule. The transmission rule comprises: each column of data in the to-be-processed data block is obtained from different hardware ports based on the correspondence between each column of data and the hardware port; a corresponding number of to-be-processed data blocks are obtained based on the number of to-be-processed data blocks transmitted based on one burst length.

11. The method of claim 9, wherein, The to-be-processed data block is obtained by: obtaining data of one burst length; segmenting the data of one burst length into a plurality of to-be-processed data blocks based on the symbol length in the to-be-processed data block.

12. The method of claim 9, wherein, The to-be-processed data block comprises a plurality of error correction data groups, and the to-be-processed data block is de-interleaved to obtain the error correction data group based on a preset data arrangement order to determine the symbol data belonging to different error correction data groups and the corresponding arrangement order.

13. The method of claim 12, wherein, The to-be-processed data block is de-interleaved to obtain the error correction data group based on a preset data arrangement order to determine the symbol data belonging to different error correction data groups and the corresponding arrangement order. When the data of different error correction data groups in the to-be-processed data block is sequentially arranged based on the order of the error correction data group, the original data block and / or the error correction data block in different error correction data groups are sequentially extracted; or, when the data of different error correction data groups in the to-be-processed data block is sequentially interleaved based on the symbol data in the error correction data group, the symbol of the original data block and / or the symbol of the error correction data block in different error correction data groups are extracted based on the interleaving order in the interleaving process.

14. The method of claim 9, wherein, The to-be-processed data block is de-interleaved to obtain the error correction data group based on a preset data arrangement order to determine the symbol data belonging to different error correction data groups and the corresponding arrangement order. The to-be-processed data block is de-interleaved to obtain the error correction data group based on a preset data arrangement order to determine the symbol data belonging to different error correction data groups and the corresponding arrangement order. The original data group comprises a plurality of original data blocks, and the original data group is generated based on the original data block after error correction, specifically, the original data block is combined based on a preset rule to generate the original data group.

15. The method of claim 9, wherein, After the original data group is generated based on the original data block after error correction, the following steps are further included:

16. The method of claim 9, wherein, The position of the error data in the to-be-processed data block is counted to determine the error type of the data. ​ 17. The method of claim 16, wherein, The position of error data in the to-be-processed data block is counted to determine the error type of the data, comprising: Counting the position of error data in the to-be-processed data block; Determining whether the error data is located in a preset number of column data, if yes, the error data is a preset error; if no, excluding the preset error.

18. A data processing apparatus, characterized by Comprising: The first data acquisition module is configured to acquire an original data group; The error correction data group generation module is configured to generate an original data block and an error correction data block corresponding to the original data block based on the original data group, wherein an original data block and an error correction data block corresponding thereto form an error correction data group; The interleaving module is configured to interleave the error correction data group to obtain a to-be-processed data block, the to-be-processed data block comprising an original data area obtained by interleaving an original data block and an error correction data area obtained by interleaving an error correction data block, one column of data in the to-be-processed data block being used for transmission based on one transmission channel, and one row of data being used for transmission based on one beat, wherein one symbol data in the original data block is arranged in one column of data in the original data area, one symbol data in the error correction data block is arranged in one column of data in the error correction data area, and the data in the to-be-processed data block is based on row alignment; The data transmission module is configured to transmit the to-be-processed data block to a preset device based on the transmission rule of the to-be-processed data block.

19. A data processing apparatus, characterized by Comprising: The second data acquisition module is configured to acquire a to-be-processed data block, the to-be-processed data block being obtained by interleaving an error correction data group, the error correction data group comprising an original data block and an error correction data block, the to-be-processed data block comprising an original data area obtained by interleaving an original data block and an error correction data area obtained by interleaving an error correction data block, one symbol data in the original data block being arranged in one column of data in the original data area, one symbol data in the error correction data block being arranged in one column of data in the error correction data area, and the data in the to-be-processed data block being based on row alignment, wherein one column of data in the to-be-processed data block is used for transmission based on one transmission channel, and one row of data is used for transmission based on one beat; The deinterleaving module is configured to deinterleave the to-be-processed data block to obtain an error correction data group; The error correction module is configured to correct the data error of the original data block in the error correction data group based on the error correction data block in the error correction data group; The original data group generation module is configured to generate an original data group based on the original data block after error correction.

20. A memory controller, comprising: The memory controller is configured with the data processing device of claim 18; And / or The memory controller is configured with the data processing device of claim 19.

21. An electronic device, comprising: The memory controller of claim 20.

22. A storage medium, characterized by The storage medium stores one or more computer executable instructions, which when executed, implement the data processing method of any one of claims 1-8, and / or implement the data processing method of any one of claims 9-17.

23. A computer program product, characterised in that, comprising one or more computer-executable instructions to implement the data processing method according to any one of claims 1 to 8, and / or to implement the data processing method according to any one of claims 9 to 17.

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