Clock duty cycle correction circuit, and serializer / deserializer

Abstract

Provided in the embodiments of the present disclosure are a clock duty cycle correction circuit, and a serializer / deserializer. The clock duty cycle correction circuit comprises: a delay module and an edge capture module. The delay module comprises a plurality of controllable capacitors, and is configured to control the delay magnitude of an input clock signal by controlling the number of capacitors among the plurality of controllable capacitors that are connected in a circuit, and to output two delayed clock signals. The edge capture module comprises four field effect transistors, and is configured to receive the two delayed clock signals and perform edge selection on the two delayed clock signals by means of a control signal, and determine an output clock signal on the basis of an edge selection result, wherein the duty cycle of the output clock signal is determined on the basis of the delay magnitude of the two delayed clock signals.

Description

Clock duty cycle correction circuit and serial deserializer

[0001] Cross Reference to Related Applications

[0002] The present disclosure is based on Chinese Patent Application No. 202410862588.5 entitled “Clock duty cycle correction circuit and serial deserializer” filed on June 28, 2024, and claims priority to the same, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate to the field of optical communication technology, in particular to a clock duty cycle correction circuit and a serial deserializer. BACKGROUND

[0004] In a serial deserializer (SERDES) system, the data eye diagram performance of the data sent by the sending end plays a decisive role in communication quality and improving communication rate, and calibrating the reference clock in the sending end can reduce deterministic jitter (DJ) and help improve the data eye diagram performance.

[0005] Calibrating the reference clock, i.e., calibrating the duty cycle of the reference clock, usually uses a clock duty cycle correction (DCC) circuit. However, as the communication rate increases, the frequency of the reference clock of the sending end also increases. For a 112G PAM4 Serdes, the reference clock uses a 14GHz, 4-phase mode. For such a high clock frequency, the duty cycle adjustment precision requirement is very high, usually less than 100fs / step, and the linearity requirement is less than 1. However, the existing DCC does not have such high precision and high linearity adjustment. SUMMARY

[0006] Embodiments of the present disclosure provide a clock duty cycle correction circuit and a serial deserializer to at least solve the problem in the related art that as the communication rate increases, a DCC circuit with higher calibration precision, lower power consumption, and smaller integrated area is needed.

[0007] According to one embodiment of the present disclosure, a clock duty cycle correction circuit is provided, comprising: a delay module, an edge capture module; the delay module comprises a plurality of controllable capacitors, which are configured to control the time delay size of an input clock signal by controlling the number of the plurality of controllable capacitors connected in the circuit, and output two delayed clock signals; the edge capture module comprises four field effect transistors, which are configured to receive the two delayed clock signals and select the edges of the two delayed clock signals through a control signal; and an output clock signal is determined according to the edge selection result, wherein the duty cycle of the output clock signal is determined by the time delay size of the two delayed clock signals.

[0008] According to another embodiment of the present disclosure, a serial deserializer is provided, comprising the clock duty cycle correction circuit in the above-mentioned embodiment. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1 is a structural block diagram of a DCC circuit according to an embodiment of the present disclosure;

[0010] FIG. 2 is a schematic diagram of the structure of a DCC circuit according to an embodiment of the present disclosure;

[0011] FIG. 3 is a schematic diagram of the internal structure of a delay module according to an embodiment of the present disclosure;

[0012] FIG. 4 is a schematic diagram of the internal structure of an edge capture module according to an embodiment of the present disclosure;

[0013] FIG. 5 is a flowchart of an output clock signal determination method according to an embodiment of the present disclosure;

[0014] FIG. 6 is a schematic diagram of input and output waveforms when the DCC circuit is working according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in conjunction with the embodiments.

[0016] It should be noted that the terms “first”, “second” and the like in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0017] Serdes is a commonly used high-speed communication protocol, which is used for large-capacity data transmission in fiber optic networks. With the rapid development of the fields of Internet, artificial intelligence (AI), data center, cloud computing, etc., the demand for network bandwidth is also increasing, which puts higher requirements on the communication rate of Serdes.

[0018] High-speed Serdes is mainly composed of a transmitting end (TX) and a receiving end (RX), wherein the TX is responsible for converting multi-bit parallel data into a high-speed serial signal, driving a package and a transmission line of a PCB to the RX; and the RX is responsible for receiving the serial signal and recovering data and a clock through a clock and data recovery (CDR) circuit.

[0019] Currently, a DCC circuit is commonly used to calibrate a reference clock of the SERDES to reduce deterministic jitter and improve the eye diagram quality of TX transmitted data, thereby ensuring communication quality. Mainstream DCC implementation modes mainly include the following modes:

[0020] 1. A controlled inverter is used to adjust the driving capability of a rising edge or a falling edge of an inverter output by controlling the conduction quantity of PMOS and NMOS in the inverter, thereby adjusting the slope of the rising edge and the falling edge of the output clock respectively, affecting the flip time of a receiving inverter, and thereby changing the duty cycle of the output clock.

[0021] 2. An ACC (AC Couple) structure is used to couple an original clock through a capacitor and control a direct current component after coupling to overall raise or lower the original clock waveform. Since the edge of the clock has a slope, the flip decision point of a receiving inverter can be changed by changing the common mode level of the clock, thereby affecting the flip time of the inverter.

[0022] Embodiments of the present disclosure propose a technology of a capacitive delay combined with edge capture, which can realize a correction step less than 50 fs / step, a linearity less than 1, excellent clock calibration accuracy, and low power consumption, and is suitable for application scenarios of high-speed Serdes.

[0023] Specifically, the technology is mainly applied to a high-speed Serdes of a passive optical network system optical line terminal and a clock phase calibration module of a high-speed Serdes of a data exchange center.

[0024] Embodiments of the present disclosure propose a new structure of an edge capture circuit, which cooperates with a capacitive delay scheme to obtain a high-precision low-power high-speed DCC structure.

[0025] The edge capture circuit has a function of capturing a jump edge of a signal from one or more signals; for the implementation of the function, the edge capture circuit in the embodiments of the present disclosure can be realized by using only four transistors.

[0026] The edge capture circuit also has a selectable type of captured edge, the edge type including: rising edge, falling edge; only the first capture is valid in a period of time, and the captured signal is directly output in the form of a step, which is very suitable for processing of high-speed clock signals.

[0027] The edge capture technology in the related art uses an RC differential circuit to determine the arrival of an edge by coupling a certain amount of charge through a capacitor in a short time by using the feature that the potential switches quickly when the edge arrives. However, this structure does not have the ability to select the type of captured edge, and the captured signal is output in the form of a pulse, which needs to be converted into a required clock step signal through additional processing, and is not suitable for processing of high-speed clock signals.

[0028] The edge capture circuit proposed in the embodiments of the present disclosure can realize decoupling and recombination of rising edges and falling edges of a clock signal, thereby realizing independent delay control of the rising edges and the falling edges and adjusting the DCC. Since the rising and falling edges of the generated clock are from two independent clock signals, the influence of the delay operation on the other type of edge does not need to be considered when the clock is operated, so that a capacitive delay scheme with excellent performance can be used in the structure. Since the delay precision in the capacitive delay scheme is determined by the size of the capacitor, a small capacitor is easier to make in an integrated circuit, so the delay precision is obviously improved. In addition, the capacitor is a passive device, which does not need additional power supply when used, and the edge selection circuit itself uses very few devices, so the scheme can also reduce power consumption. In summary, the edge capture circuit combined with the capacitive delay scheme can design a high-precision and low-power high-speed DCC structure.

[0029] FIG. 1 is a structural block diagram of a DCC circuit according to an embodiment of the present disclosure. As shown in FIG. 1, the clock duty cycle correction circuit includes a delay module 10 and an edge capture module 20.

[0030] The delay module 10 includes a plurality of controllable capacitors, which are configured to control the delay size of an input clock signal by controlling the number of the plurality of controllable capacitors connected in the circuit, and output two delayed clock signals.

[0031] The edge capture module 20 includes four field effect transistors, which are configured to receive the two delayed clock signals and select edges of the two delayed clock signals through a control signal; and determine an output clock signal according to the edge selection result, wherein a duty cycle of the output clock signal is determined by the delay sizes of the two delayed clock signals.

[0032] In one embodiment, the delay module 10 includes a first delay module 11 and a second delay module 12.

[0033] The first delay module 11 comprises a plurality of first controllable capacitors, configured to receive an input clock signal and control a delay size of the input clock signal by adjusting a number of first controllable capacitors in a circuit connected in the first delay module, and output a first delayed clock signal.

[0034] The second delay module 12 comprises a plurality of second controllable capacitors, configured to receive the input clock signal and control a delay size of the input clock signal by adjusting a number of second controllable capacitors in a circuit connected in the second delay module, and output a second delayed clock signal; wherein the delay size corresponding to the first input clock signal is different from the delay size corresponding to the second input clock signal; and the plurality of controllable capacitors comprises the plurality of first controllable capacitors and the plurality of second controllable capacitors.

[0035] In one embodiment, the clock duty cycle correction circuit further comprises a control module 30 configured to control the delay module to adjust the number of controllable capacitors in the circuit connected in the plurality of controllable capacitors.

[0036] Fig. 2 is a schematic diagram of a DCC circuit structure according to an embodiment of the present disclosure. As shown in Fig. 2, the input clock signal is divided into three paths, two of which are used as delay paths and connected to two delay modules (DELAY_CELL 1 and DELAY_CELL 2) respectively. DELAY_CELL 1 is functionally equivalent to the first delay module 11 in the above embodiment, and DELAY_CELL 2 is functionally equivalent to the second delay module 12 in the above embodiment. The remaining path is connected to an edge capture module (EDGE_SEL in Fig. 2) together with the outputs of the delay modules, and the output of the edge capture module is the final output of the DCC. The code value of CTRL_CODE_IN is controlled by the control module (DECODER in Fig. 2) to control the delay sizes of the two delay modules, for example, by controlling the number of controllable capacitors in the circuit connected in the delay module to control the delay size, thereby controlling the adjustment range.

[0037] In one embodiment, the delay module further comprises a first inverter and a second inverter connected in series with the first inverter, wherein the second inverter is connected to a common connection point of the plurality of controllable capacitors.

[0038] In one embodiment, the first inverter and the second inverter are configured to generate a delay for the input clock signal; wherein the correction accuracy of the clock duty cycle correction circuit is determined by the driving capability of the second inverter.

[0039] Fig. 3 is a schematic diagram of the internal structure of the delay module according to an embodiment of the present disclosure. As shown in Fig. 3, the delay module includes two inverters INV1 and INV2, and a direction device configured to drive controllable capacitors. The INV1 is functionally equivalent to the first inverter in the above embodiment, and the INV2 is functionally equivalent to the second inverter in the above embodiment. The delay module further includes N controllable capacitors (i.e., CTRL CAP in Fig. 3), where N is an integer greater than zero.

[0040] The input clock signal is driven through two-stage inverters and then connected to the network of N controllable capacitors. The output of the network is the output of the delay module. The delay of the input clock signal can be controlled by controlling the number of controllable capacitors connected to the network.

[0041] In the embodiment, the two inverters at the input end of the delay module are necessary because the subsequent edge capture circuit can work normally only after the delay provided by the two inverters. That is, when the number of controllable capacitors connected to the network is zero, the delay module still works normally due to the two inverters, so that the edge capture module can work normally.

[0042] In the embodiment, the correction accuracy can be adjusted by adjusting the driving capability of the inverters and / or the capacitance of the controllable capacitors.

[0043] In one embodiment, the delay module further includes a third inverter connected in series with the first inverter and in parallel with the second inverter. The third inverter is a controllable inverter. By controlling whether the third inverter works or not, the delay can be controlled. In combination with the edge capture module according to the embodiment of the present disclosure, the function of adjusting the DCC correction range can be realized.

[0044] In one embodiment, the edge capture module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The source of the first PMOS transistor is connected to a power supply, the gate of the first PMOS transistor is connected to the output of the first delay module, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the first NMOS transistor is connected to the source of the second NMOS transistor. The gate of the second PMOS transistor is connected to the gate of the first NMOS transistor, and the output of the edge capture module is connected to the drain of the second PMOS transistor and the drain of the first NMOS transistor. The source of the second NMOS transistor is connected to the ground, and the gate of the second NMOS transistor is connected to the output of the second delay module.

[0045] In one embodiment, a bipolar junction transistor (BJT) can be used instead of a field effect transistor in the edge capture module to achieve the same function.

[0046] Fig. 4 is a schematic diagram of the internal structure of the edge capture module according to an embodiment of the present disclosure. As shown in Fig. 4, the edge capture module is composed of four MOSFETs, two PMOSs numbered M1 and M2 and two NMOSs numbered M3 and M4. Among them, M1 is functionally equivalent to the first PMOS in the above embodiment, M2 is functionally equivalent to the second PMOS in the above embodiment, M3 is functionally equivalent to the first NMOS in the above embodiment, and M4 is functionally equivalent to the second NMOS in the above embodiment.

[0047] Among them, the source of M1 is connected to the power supply AVDD, the drain of M1 is connected to the source of M2, the drain of M2 is connected to the drain of M3 as the output terminal OUT, the source of M3 is connected to the drain of M4, and the source of M4 is connected to the ground AVSS. The gate of M1 is connected to the signal FALL_EDGE as the input terminal of the falling edge to be captured signal, the gate of M4 is connected to the signal RISE_EDGE as the input terminal of the rising edge to be captured signal, and the gates of M2 and M3 are connected together as the input of the control signal CTRL.

[0048] In this embodiment, the control signal is used to control the selective conduction of the four MOSFETs.

[0049] In one embodiment, the edge capture module is configured to, in the case that the control signal is at a low level, change the output clock signal from a low level to a high level according to the falling edge of the first delay clock signal; and in the case that the control signal is at a high level, change the output clock signal from a high level to a low level according to the rising edge of the second delay clock signal.

[0050] Based on the DCC circuit provided by the above embodiments of the present disclosure, the present disclosure further provides an output clock signal determination method after clock calibration. Fig. 5 is a flowchart of the output clock signal determination method according to an embodiment of the present disclosure. As shown in Fig. 5, the method comprises the following steps:

[0051] In step S501, the to-be-calibrated signal is input as the control signal CTRL, and is divided into two other signals to generate the FALL_EDGE signal and the RISE_EDGE signal.

[0052] Based on the delay module of Fig. 3, the FALL_EDGE signal and the RISE_EDGE signal are both passed through two inverters compared with the CTRL signal, so that the edges of the two signals are both delayed by a certain time compared with the CTRL signal.

[0053] In one embodiment, the delay module is further configured to adjust the edge slope of the delay clock signal by adjusting the number of controllable capacitors in the access circuit of the plurality of controllable capacitors, so as to achieve the delay function of the clock by adjusting the edge slope of the delay clock signal.

[0054] In one embodiment, controllable capacitors can be selectively added to the first delay module and / or the second delay module to independently control the rising and falling edge slope of each path, so as to achieve the delay control. The signal waveform diagram of the RISE_EDGE path after adding the controllable capacitors is shown in FIG. 6. Since the clock of the RISE_EDGE path is additionally delayed by the controllable capacitors, the rising edge of the RISE_EDGE path lags behind the falling edge of the FALL_EDGE path, and the falling edge of the FALL_EDGE path lags behind the rising edge of the FALL_EDGE path. Therefore, the low level time of the generated clock is shortened, and the duty cycle of the output clock is increased. Moreover, the greater the delay of the RISE_EDGE path, the greater the duty cycle of the output clock. Conversely, if the RISE_EDGE path is not delayed and the FALL_EDGE path is delayed, the high level time of the output clock is shortened, and the duty cycle of the output clock is decreased.

[0055] In step S502, the rising edge of the RISE_EDGE path is captured, and the output clock signal is converted from high level to low level.

[0056] Specifically, when the CTRL signal is high, M2 is turned off and M3 is turned on, so that no current flows through the circuit in which M1 and M2 are located. The conduction state of the circuit in which M3 and M4 are located depends on the level of the RISE_EDGE signal at the gate of M4. When the level of the RISE_EDGE signal is converted from low level to high level, the state of M4 is changed from off to on, the rising edge of the RISE_EDGE signal is captured, the circuit in which M3 and M4 are located is turned on, and the output is converted from high level to low level.

[0057] In step S503, the falling edge of the FALL_EDGE path is captured, and the output clock signal is converted from low level to high level.

[0058] Specifically, when the CTRL signal is low, M3 is turned off, and no current flows through the circuit in which M3 and M4 are located. The conduction state of the circuit in which M1 and M2 are located depends on the level of the FALL_EDGE signal at the gate of M1. When the level of the FALL_EDGE signal is converted from high level to low level, the state of M1 is changed from off to on, the falling edge of the FALL_EDGE signal is captured, the circuit in which M1 and M2 are located is turned on, and the output is converted from low level to high level.

[0059] Figure 6 is a schematic diagram of input and output waveforms when the DCC circuit is working, according to an embodiment of the present disclosure. As shown in Figure 6, based on the above-mentioned output clock signal determination method, when the rising edge of RISE_EDGE (i.e. the RISE_EDGE waveform in Figure 6) is captured by the edge capture module, the output clock signal (i.e. the OUT waveform in Figure 6) will have a high level transition to a low level. When the rising edge of FALL_EDGE (i.e. the FALL_EDGE waveform in Figure 6) is captured by the edge capture module, the output clock signal will have a low level transition to a high level.

[0060] Through the above steps, the DCC structure proposed in the embodiments of the present disclosure can realize the duty cycle adjustment of the output clock by controlling the delay of the two paths of FALL_EDGE and RISE_EDGE, and the step of controlling the delay is the precision of controlling the DCC calibration.

[0061] The embodiments of the present disclosure separate the delay control of the rising edge and the falling edge by the clock edge capture technology, so that the design of the delay module is more flexible. In the existing DCC structure, the delay design must consider the influence of the delay of the edge of the opposite polarity (for example: when only the falling edge of the clock signal is delayed, the delay module will also have an influence on the rising edge, in order to reduce this influence, the flexibility and performance of the circuit design are sacrificed), and the DCC structure proposed in the embodiments of the present disclosure does not need to consider this problem at all, which makes the design of the delay structure can use the capacitive delay technology with higher performance. Capacitive delay has the characteristics of low power consumption, high precision, area saving, etc., so that the final performance of the embodiments of the present disclosure is very excellent.

[0062] In one embodiment, two delay modules and edge capture modules are used in parallel and connected to differential clocks of opposite polarity, so that the duty cycle calibration of the differential clock can be realized.

[0063] In one embodiment, by designing the control logic to make the two delay modules in Figure 2 work at the same time and control the number of working capacitors to be the same, the clock can be delayed without changing the duty cycle by using this module, and the 0°-90° phase calibration function of the four-phase clock can be realized by using this effect, thereby developing a QEC calibration circuit.

[0064] In one embodiment, if the two delay modules are controlled to work at the same time and the number of working capacitors of the two paths is different, a four-phase clock calibration circuit that combines the functions of DCC and QEC can be developed.

[0065] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software on a necessary general hardware platform, and of course can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present disclosure can be embodied in the form of a software product in essence or in the form of a part of the prior art that contributes to the present disclosure. The computer software product is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disk), and includes a plurality of instructions for causing an end device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the method described in each embodiment of the present disclosure.

[0066] The embodiments of the present disclosure also provide a serial deserializer, wherein the clock duty cycle correction circuit in the above embodiments is arranged in the serial deserializer.

[0067] The embodiments of the present disclosure also provide a chip, wherein the serial deserializer in the above embodiments is arranged in the chip.

[0068] The above only describes the preferred embodiments of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A clock duty cycle correction circuit, comprising: Delay module, edge capture module; The delay module includes multiple controllable capacitors, configured to control the delay of the input clock signal by controlling the number of the multiple controllable capacitors connected in the circuit, and output two delayed clock signals. The edge-capturing module includes four field-effect transistors, configured to receive the two delayed clock signals and perform edge selection on the two delayed clock signals through a control signal; and determine the output clock signal based on the edge selection result, wherein the duty cycle of the output clock signal is determined by the delay magnitude of the two delayed clock signals.

2. The clock duty cycle correction circuit according to claim 1, wherein, The delay module further includes: a first inverter, a second inverter connected in series with the first inverter, and the second inverter being connected to the common connection point of the plurality of controllable capacitors.

3. The clock duty cycle correction circuit according to claim 2, wherein, The delay module further includes a third inverter, which is connected in series with the first inverter and in parallel with the second inverter.

4. The clock duty cycle correction circuit according to claim 2, wherein, The first inverter and the second inverter are configured to generate a time delay for the input clock signal; wherein the correction accuracy of the clock duty cycle correction circuit is determined by the driving capability of the second inverter.

5. The clock duty cycle correction circuit according to claim 1, wherein, The delay module includes a first delay module and a second delay module; The first delay module includes a plurality of first controllable capacitors, configured to receive an input clock signal, and control the delay of the input clock signal by adjusting the number of first controllable capacitors connected in the circuit among the plurality of first controllable capacitors in the first delay module, and output a first delayed clock signal; The second delay module includes a plurality of second controllable capacitors, configured to receive the input clock signal and control the delay of the input clock signal by adjusting the number of second controllable capacitors connected in the circuit among the plurality of second controllable capacitors in the second delay module, and output a second delayed clock signal; wherein the delay corresponding to the first delayed clock signal is different from the delay corresponding to the second delayed clock signal; the plurality of controllable capacitors include the plurality of first controllable capacitors and the plurality of second controllable capacitors.

6. The clock duty cycle correction circuit according to claim 5, wherein, The edge-catching module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The source of the first PMOS transistor is connected to the power supply, the gate of the first PMOS transistor is connected to the output terminal of the first delay module, the drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor and then connected to the output terminal of the edge capture module, the gate of the second PMOS transistor is connected to the gate of the first NMOS transistor and receives the control signal, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is connected to the output terminal of the second delay module.

7. The clock duty cycle correction circuit according to claim 6, wherein, The control signal is used to control the selective conduction of the four field-effect transistors.

8. The clock duty cycle correction circuit according to claim 6, wherein, The edge capture module is configured to change the output clock signal from low to high based on the falling edge of the first delayed clock signal when the control signal is low; and to change the output clock signal from high to low based on the rising edge of the second delayed clock signal when the control signal is high.

9. The clock duty cycle correction circuit according to claim 1, wherein, The delay module is further configured to adjust the edge slope of the delay clock signal by adjusting the number of controllable capacitors connected in the circuit among the plurality of controllable capacitors, so as to realize the clock delay function by adjusting the edge slope of the delay clock signal.

10. The clock duty cycle correction circuit according to claim 1, further comprising: The control module is configured to control the delay module to adjust the number of controllable capacitors connected to the circuit among the plurality of controllable capacitors.

11. A serial deserializer, comprising the clock duty cycle correction circuit of any one of claims 1-10.

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