Pipeline analog-to-digital conversion circuit, chip and electronic device

Abstract

Provided in the present application are a pipeline analog-to-digital conversion circuit, a chip and an electronic device. The pipeline analog-to-digital conversion circuit comprises: first and second analog-to-digital conversion modules; an inter-stage gain module, which is connected between the first and second analog-to-digital conversion modules and configured to amplify a quantization residue of the first analog-to-digital conversion module; and an adjustment module, which is configured to, in a current analog-to-digital conversion cycle, output a first adjustment voltage and a second adjustment voltage on the basis of one or more historical codes, inject the first adjustment voltage into an input terminal of the inter-stage gain module, and inject the second adjustment voltage into an output terminal of the inter-stage gain module to cancel the first adjustment voltage, wherein any historical code is a code obtained by the second analog-to-digital conversion module by means of performing analog-to-digital conversion on a corresponding quantization residue in any analog-to-digital conversion cycle preceding the current analog-to-digital conversion cycle. The embodiments of the present application can eliminate the impact of gain errors of the inter-stage gain module, thus improving the performance of the analog-to-digital conversion circuit.

Description

Pipeline analog-to-digital conversion circuit, chip and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202410819357.6, filed on June 24, 2024, and entitled "Pipeline analog-to-digital conversion circuit, chip and electronic device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of analog-to-digital conversion, in particular to a pipeline analog-to-digital conversion circuit, chip and electronic device. BACKGROUND

[0003] Pipeline analog-to-digital converter (Pipeline ADC) belongs to multi-stage converter, which can include at least two analog-to-digital conversion modules, and an inter-stage amplifier is arranged between the two analog-to-digital conversion modules. The inter-stage amplifier amplifies the quantization residual (also known as residual voltage) of the first analog-to-digital conversion module, and then outputs it to the second analog-to-digital conversion module for further fine quantization. Pipeline ADC needs to use an inter-stage amplifier with accurate gain. Especially under advanced process nodes, the power supply voltage is reduced, and it is very difficult to realize a high-gain amplifier. The gain error of the inter-stage amplifier is not easy to eliminate, which affects the performance of the Pipeline ADC. TECHNICAL SOLUTION

[0004] In view of the above problems, the embodiments of the present application provide a pipeline analog-to-digital conversion circuit, chip and electronic device to solve the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides a pipelined analog-to-digital conversion circuit, comprising: a first analog-to-digital conversion module; a second analog-to-digital conversion module; an inter-stage gain module connected between the first analog-to-digital conversion module and the second analog-to-digital conversion module, configured to amplify a quantization residual of the first analog-to-digital conversion module; and an adjustment module configured to output a first adjustment voltage and a second adjustment voltage based on one or more historical code values at a current analog-to-digital conversion period, inject the first adjustment voltage at an input end of the inter-stage gain module, and inject the second adjustment voltage at an output end of the inter-stage gain module to offset the first adjustment voltage; wherein any historical code value of the one or more historical code values is a code value obtained by performing analog-to-digital conversion on a corresponding quantization residual by the second analog-to-digital conversion module at any analog-to-digital conversion period before the current analog-to-digital conversion period in the two analog-to-digital conversion stages. In the embodiment of the present application, the adjustment module predicts the size of the quantization residual of the current analog-to-digital conversion period based on the one or more historical code values, injects the first adjustment voltage at the input end of the inter-stage gain module to realize high-pass filtering, and injects the second adjustment voltage at the output end of the inter-stage gain module to offset the first adjustment voltage, thereby restoring the quantization residual of the current analog-to-digital conversion period, eliminating the influence of the gain error of the inter-stage gain module, and improving the performance of the pipelined analog-to-digital conversion circuit.

[0006] In a second aspect, an embodiment of the present application further provides a chip comprising the pipelined analog-to-digital conversion circuit described above.

[0007] In a third aspect, an embodiment of the present application further provides an electronic device comprising the chip or the pipelined analog-to-digital conversion circuit described above. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0009] FIG. 1 shows a schematic diagram of a pipelined analog-to-digital conversion circuit according to an embodiment of the present application.

[0010] FIG. 2 shows a schematic diagram of another pipelined analog-to-digital conversion circuit according to an embodiment of the present application.

[0011] FIG. 3 shows a schematic diagram of still another pipelined analog-to-digital conversion circuit according to an embodiment of the present application.

[0012] FIG. 4 shows a schematic diagram of a pipelined analog-to-digital conversion circuit according to an embodiment of the present application.

[0013] FIG. 5 shows a timing diagram of the pipelined analog-to-digital conversion circuit 400.

[0014] FIG. 6 shows a schematic diagram of another pipeline analog-to-digital conversion circuit according to an embodiment of the present application.

[0015] FIG. 7 shows a timing diagram of the pipeline analog-to-digital conversion circuit 600.

[0016] FIG. 8 shows a circuit diagram of a pipeline analog-to-digital conversion circuit according to an embodiment of the present application.

[0017] FIG. 9 shows a circuit diagram of another pipeline analog-to-digital conversion circuit according to an embodiment of the present application.

[0018] FIG. 10 shows a circuit diagram of a first injection unit according to an embodiment of the present application.

[0019] FIG. 11 shows a circuit diagram of another first injection unit according to an embodiment of the present application.

[0020] FIG. 12 shows a circuit diagram of a second injection unit according to an embodiment of the present application.

[0021] FIG. 13 shows a flowchart of an analog-to-digital conversion method according to an embodiment of the present application.

[0022] Embodiments of the present application

[0023] The embodiments of the present application will be described in detail below with reference to the drawings, in which the same or similar components are denoted by the same or similar reference numerals, and therefore the description will be given only with respect to the differences between the embodiments. The embodiments described below are merely exemplary of the present application, and therefore should not be considered to limit the present application.

[0024] In order to make the technical personnel in the art better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0025] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second and the like are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between or among the entities or actions.

[0026] Also, the term "comprise", "comprising", or any other variant thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0027] In the description of the embodiments of the present application, the word "example" or "for example" is used to mean serving as an example, instance, or illustration. Any embodiment or design presented as an "example" or "for example" in the present application is not necessarily to be construed as preferred or having more advantages than other embodiments or designs. The use of the word example or for example is intended to present clear concepts. The word "example" or "for example" does not indicate that a specific embodiment or design is preferred over another embodiment or design.

[0028] In addition, "multiple" in the embodiments of the present application refers to two or more. In view of this, "multiple" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included, for example, including at least one of A, B and C, then the included can be A, B, C, A and B, A and C, B and C, or A and B and C.

[0029] It should be noted that in the embodiments of the present application, the association relationship of the associated objects described by "and / or" can represent three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. In addition, the character " / ", if not specially specified, generally represents a "or" relationship between the front and rear associated objects.

[0030] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical elements can be direct or indirect connection between the two electrical elements. For example, A is connected to B, which can be direct connection between A and B, or indirect connection between A and B through one or more other electrical elements.

[0031] The circuit structure provided by the embodiments of the present application, the nodes such as the first node and the second node do not represent actual existing components, but represent the convergence point of the relevant coupling in the circuit diagram, that is, these nodes are nodes equivalent to the convergence point of the relevant coupling in the circuit diagram.

[0032] The embodiments of the present application provide a pipeline analog-to-digital conversion circuit.

[0033] FIG. 1 shows a schematic diagram of a pipeline analog-to-digital conversion circuit according to an embodiment of the present application. As shown in FIG. 1, the pipeline analog-to-digital conversion circuit 100 can include at least a first analog-to-digital conversion module 110-1 and a second analog-to-digital conversion module 110-2, an inter-stage gain module 120 connected between the first analog-to-digital conversion module 110-1 and the second analog-to-digital conversion module 110-2, and an adjustment module 130.

[0034] As shown in FIG. 1, the first analog-to-digital conversion module 110-1 performs analog-to-digital conversion on its input signal and outputs a first code value D fir , the inter-stage gain module 120 amplifies the quantization residue of the first analog-to-digital conversion module 110-1, the second analog-to-digital conversion module 110-2 performs analog-to-digital conversion on the amplified quantization residue and outputs a second code value D sce . The adjustment module 130 outputs a first adjustment voltage V1 and a second adjustment voltage V2 based on one or more historical code values in a current analog-to-digital conversion period, and injects the first adjustment voltage V1 at the input end of the inter-stage gain module 120 and the second adjustment voltage V2 at the output end of the inter-stage gain module 120 to offset the first adjustment voltage V1. Any of the one or more historical code values is a second code value obtained by the second analog-to-digital conversion module 110-2 performing analog-to-digital conversion on a corresponding quantization residue in any analog-to-digital conversion period before the current analog-to-digital conversion period.

[0035] In some embodiments, the pipeline analog-to-digital conversion circuit 100 can include a conventional pipeline analog-to-digital conversion circuit. For example, the first analog-to-digital conversion module 110-1 and the second analog-to-digital conversion module 110-2 can include a flash analog-to-digital conversion unit, a digital-to-analog conversion unit, and a subtraction unit. The flash analog-to-digital conversion unit performs analog-to-digital conversion on the input of the current stage and outputs a code value of the current stage. The digital-to-analog conversion unit performs digital-to-analog conversion on the code value of the current stage. The subtraction unit performs subtraction operation on the input of the current stage and the result of the digital-to-analog conversion and outputs a quantization residue.

[0036] In some embodiments, the pipeline analog-to-digital conversion circuit 100 can include a mixed-structure analog-to-digital conversion circuit, such as a successive approximation pipeline analog-to-digital conversion circuit (SAR-Pipeline ADC). For example, the first analog-to-digital conversion module 110-1 and the second analog-to-digital conversion module 110-2 can include a successive approximation analog-to-digital conversion module. The successive approximation analog-to-digital conversion module performs analog-to-digital conversion on the input of the current stage and outputs a code value of the current stage and a quantization residue.

[0037] In some embodiments, the inter-stage gain module 120 can include an amplification unit for amplifying the quantization residual, and a feedback network connected between the input and output of the amplification unit. The feedback network can include a feedback capacitor. The adjustment module 130 can eliminate the gain error of the amplifier itself and the gain error introduced by the feedback network mismatch.

[0038] In some embodiments, assuming the ideal gain of the inter-stage gain module 120 is G, the first adjustment voltage V1 and the second adjustment voltage V2 satisfy the following relationship: V1 = 1 / G*V2. The first adjustment voltage V1 is substantially amplified G times by the inter-stage gain module 120 and is substantially equal to the second adjustment voltage V2, which can offset the first adjustment voltage V1. As an embodiment, the adjustment module 130 can subtract the first adjustment voltage V1 at the input of the inter-stage gain module 120, and add the second adjustment voltage V2 at the output of the inter-stage gain module 120, that is, the input of the inter-stage gain module 120 is the difference between the quantization residual and the first adjustment voltage V1, and the output of the inter-stage gain module 120 is the sum of the amplified quantization residual and the first adjustment voltage V1 and the second adjustment voltage V2.

[0039] In the embodiments of the present application, the size of the code value (i.e., the quantization residual of the current analog-to-digital conversion period) of the second analog-to-digital conversion module in the current analog-to-digital conversion period is predicted based on one or more historical code values, the first adjustment voltage is injected at the input of the inter-stage gain module based on the predicted code value to achieve high-pass filtering, and the second adjustment voltage is injected at the output of the inter-stage gain module to offset the first adjustment voltage, thereby restoring the quantization residual of the current analog-to-digital conversion period, which can eliminate the influence of the gain error of the inter-stage gain module and improve the performance of the pipeline analog-to-digital conversion circuit.

[0040] In some embodiments, the adjustment module 130 can inject the first adjustment voltage V1 at the input of the inter-stage gain module 120 and inject the second adjustment voltage V2 at the output of the inter-stage gain module 120 based on one historical code value. Thus, first-order gain error elimination is achieved. The adjustment module 130 can be connected with the second analog-to-digital conversion module 110-2 to receive at least part of the digital bits of the historical code value of the second analog-to-digital conversion module 110-2.

[0041] For example, the current analog-to-digital conversion period is represented as i, the previous analog-to-digital conversion period is represented as i-1, and the code value output by the second analog-to-digital conversion module 110-2 in the previous analog-to-digital conversion period of the current analog-to-digital conversion period is represented as D sec (i-1). The adjustment module 130 injects the first adjustment voltage V1 at the input of the inter-stage gain module 120 based on D sec(i-1) outputting a first adjustment voltage V1 and a second adjustment voltage V2, the first adjustment voltage V1 and the second adjustment voltage V2 satisfying: V1 = 1 / G*V2, G represents an ideal gain of the inter-stage gain module 120. The adjustment module 130 can subtract the first adjustment voltage V1 at the input end of the inter-stage gain module 120, and add the second adjustment voltage V2 at the output end of the inter-stage gain module 120.

[0042] For example, the adjustment module 130 can convert D sec (i-1) into a corresponding voltage, inject the voltage as the second adjustment voltage V2 at the output end of the inter-stage gain module 120, and reduce the voltage according to the ideal gain G of the inter-stage gain module 120, inject the reduced voltage as the first adjustment voltage V1 at the input end of the inter-stage gain module 120, so that the first adjustment voltage V1 and the second adjustment voltage V2 satisfy:

[0043] V1 = 1 / G*V2, and the second adjustment voltage V2 substantially offsets the first adjustment voltage V1.

[0044] For another example, the adjustment module 130 can convert D sec (i-1) into a corresponding voltage, inject the voltage as the second adjustment voltage V2 at the output end of the inter-stage gain module 120, and reduce the voltage according to the ideal gain G of the inter-stage gain module 120, inject the reduced voltage as the first adjustment voltage V1 at the input end of the inter-stage gain module 120, so that the first adjustment voltage V1 and the second adjustment voltage V2 satisfy: V1 = 1 / G*V2, and the second adjustment voltage V2 substantially offsets the first adjustment voltage V1.

[0045] For another example, the adjustment module 130 can convert D sec (i-1) into a corresponding first voltage, reduce the first voltage according to the gain of the inter-stage gain module 120, and inject the reduced first voltage as the first adjustment voltage V1 at the input end of the inter-stage gain module 120; convert D sec (i-1) into a corresponding second voltage, and inject the second voltage as the second adjustment voltage V2 at the output end of the inter-stage gain module 120. Wherein the reduced first voltage (i.e. the first adjustment voltage V1) is 1 / G of the second voltage (i.e. the second adjustment voltage V2), G represents an ideal gain of the inter-stage gain module 120, and M1 and M2 are different.

[0046] In other embodiments, the adjustment module 130 can subtract the first adjustment voltage V1 at the input end of the inter-stage gain module 120, and add the second adjustment voltage V2 at the output end of the inter-stage gain module 120, based on a plurality of historical code values. Thus, high-order gain error cancellation is achieved.

[0047] For example, the current analog-to-digital conversion cycle is denoted as i, the previous analog-to-digital conversion cycle is denoted as i-1, the two previous analog-to-digital conversion cycles are denoted as i-2, and the code value output by the second analog-to-digital conversion module 110-2 in the previous analog-to-digital conversion cycle of the current analog-to-digital conversion cycle is denoted as D(i-1) sec For example, the current analog-to-digital conversion cycle is denoted as i, the previous analog-to-digital conversion cycle is denoted as i-1, the two previous analog-to-digital conversion cycles are denoted as i-2, and the code value output by the second analog-to-digital conversion module 110-2 in the previous analog-to-digital conversion cycle of the current analog-to-digital conversion cycle is denoted as D(i-1) sec For example, the current analog-to-digital conversion cycle is denoted as i, the previous analog-to-digital conversion cycle is denoted as i-1, the two previous analog-to-digital conversion cycles are denoted as i-2, and the code value output by the second analog-to-digital conversion module 110-2 in the previous analog-to-digital conversion cycle of the current analog-to-digital conversion cycle is denoted as D(i-1) sec For example, the current analog-to-digital conversion cycle is denoted as i, the previous analog-to-digital conversion cycle is denoted as i-1, the two previous analog-to-digital conversion cycles are denoted as i-2, and the code value output by the second analog-to-digital conversion module 110-2 in the previous analog-to-digital conversion cycle of the current analog-to-digital conversion cycle is denoted as D(i-1)

[0048] For example, the current analog-to-digital conversion cycle is denoted as i, the previous analog-to-digital conversion cycle is denoted as i-1, the two previous analog-to-digital conversion cycles are denoted as i-2, and the code value output by the second analog-to-digital conversion module 110-2 in the previous analog-to-digital conversion cycle of the current analog-to-digital conversion cycle is denoted as D(i-1) sec For example, the current analog-to-digital conversion cycle is denoted as i, the previous analog-to-digital conversion cycle is denoted as i-1, the two previous analog-to-digital conversion cycles are denoted as i-2, and the code value output by the second analog-to-digital conversion module 110-2 in the previous analog-to-digital conversion cycle of the current analog-to-digital conversion cycle is denoted as D(i-1) sec For example, the current analog-to-digital conversion cycle is denoted as i, the previous analog-to-digital conversion cycle is denoted as i-1, the two previous analog-to-digital conversion cycles are denoted as i-2, and the code value output by the second analog-to-digital conversion module 110-2 in the previous analog-to-digital conversion cycle of the current analog-to-digital conversion cycle is denoted as D(i-1) sec For example, the current analog-to-digital conversion cycle is denoted as i, the previous analog-to-digital conversion cycle is denoted as i-1, the two previous analog-to-digital conversion cycles are denoted as i-2, and the code value output by the second analog-to-digital conversion module 110-2 in the previous analog-to-digital conversion cycle of the current analog-to-digital conversion cycle is denoted as D(i-1) sec For example, the current analog-to-digital conversion cycle is denoted as i, the previous analog-to-digital conversion cycle is denoted as i-1, the two previous analog-to-digital conversion cycles are denoted as i-2, and the code value output by the second analog-to-digital conversion module 110-2 in the previous analog-to-digital conversion cycle of the current analog-to-digital conversion cycle is denoted as D(i-1) sec For example, the current analog-to-digital conversion cycle is denoted as i, the previous analog-to-digital conversion cycle is denoted as i-1, the two previous analog-to-digital conversion cycles are denoted as i-2, and the code value output by the second analog-to-digital conversion module 110-2 in the previous analog-to-digital conversion cycle of the current analog-to-digital conversion cycle is denoted as D(i-1)

[0049] In some embodiments, as shown in FIG. 2, the adjustment module 130 can include a first injection unit 131 and a second injection unit 132. The first injection unit 131 is connected with the second analog-to-digital conversion module 110-2, and is configured to receive a first control code value and generate a first adjustment voltage based on the first control code value. The second injection unit 132 is connected with the second analog-to-digital conversion module 110-2, and is configured to receive a second control code value and generate a second adjustment voltage based on the second control code value. The first control code value and the second control code value are at least part of digital bits of a same historical code value, for example, the first control code value and the second control code value are code values output by the second analog-to-digital conversion module 110-2 in a previous analog-to-digital conversion period. As an example, the first control code value and the second control code value have the same number of bits, for example, both are code values output by the second analog-to-digital conversion module 110-2 in a previous analog-to-digital conversion period. As another example, the first control code value and the second control code value have different numbers of bits.

[0050] In some embodiments, as shown in FIG. 3, the adjustment module 130 can include a first injection unit 131, a second injection unit 132, and a preprocessing unit 133.

[0051] As an example, the preprocessing unit 133 takes a historical code value as a control code value, outputs high P1 bits of the control code value as the first control code value, and outputs high P2 bits of the control code value as the second control code value. P1 can be equal to or different from P2.

[0052] As an example, the current analog-to-digital conversion period is denoted as i, the previous analog-to-digital conversion period is denoted as i-1, and the code value output by the second analog-to-digital conversion module 110-2 in the previous analog-to-digital conversion period of the current analog-to-digital conversion period is denoted as D sec (i-1). The preprocessing unit 133 can output high P1 bits of D sec (i-1) as the first control code value, and output high P2 bits of D sec (i-1) as the second control code value. The first injection unit 131 generates the first adjustment voltage V1 according to the high P1 bits of D sec (i-1), and the second injection unit 132 generates the second adjustment voltage V2 according to the high P2 bits of D sec (i-1). The first adjustment voltage V1 and the second adjustment voltage V2 satisfy: V1 = 1 / G*V2, where G represents an ideal gain of the inter-stage gain module 120.

[0053] As another example, the preprocessing unit 133 generates the control code value based on a plurality of historical code values, and the first control code value and the second control code value are at least part of digital bits of the control code value generated based on the plurality of historical code values.

[0054] For example, the current analog-to-digital conversion cycle is denoted as i, the previous analog-to-digital conversion cycle is denoted as i-1, the two previous analog-to-digital conversion cycles are denoted as i-2, and the code value output by the second analog-to-digital conversion module 110-2 in the previous analog-to-digital conversion cycle is denoted as D. sec (i-1), the code value output by the second analog-to-digital converter module 110-2 in the first two analog-to-digital converter cycles of the current analog-to-digital converter cycle is represented as D. sec (i-2), the preprocessing unit 133 is based on D(i-1) and D sec (i-2) Generate the control code value. For example, the preprocessing unit 133 can generate the control code value according to the following formula: D ctr =2*D sec (i-1)-D sec (i-2)

[0055] Among them, D ctr This represents the control code value used to form the first and second adjustment voltages.

[0056] For example, continuing from the above example, the code value output by the second analog-to-digital conversion module 110-2 in the first three analog-to-digital conversion cycles of the current conversion cycle is represented as D. sec (i-3), the preprocessing unit 133 is based on D(i-1), D sec (i-2) and D sec (i-3) Generate control code value.

[0057] For example, the preprocessing unit 133 can generate the control code value according to the following formula: D ctr =3*D sec (i-1)-3D sec (i-2)+D sec (i-3)

[0058] Among them, D ctr This represents the control code value used to form the first and second adjustment voltages.

[0059] For example, continuing from the above example, the code value output by the second analog-to-digital conversion module 110-2 in the first four analog-to-digital conversion cycles of the current conversion cycle is represented as D. sec (i-4), the preprocessing unit 133 is based on D(i-1), D sec (i-2), D sec (i-3) and D sec (i-4) Generate control code value.

[0060] For example, the preprocessing unit 133 can generate the control code value according to the following formula: D ctr =4*D sec (i-1)-6Dsec (i-2) + 4D sec (i-3) - D sec (i-4)

[0061] wherein, D ctr represents a control code value used for forming the first adjustment voltage and the second adjustment voltage.

[0062] Further, the preprocessing unit 133 can take at least part of the digital bits of the control code value as the first control code value and the second control code value. For example, the preprocessing unit 133 can take the high P3 bits of D ct as the first control code value output, and take the high P4 bits of D ctr as the second control code value output. Wherein, P3 and P4 can be equal or not equal.

[0063] The first injection unit 131 receives the first control code value output by the preprocessing unit 133, and generates the first adjustment voltage based on the first control code value. The second injection unit 132 receives the second control code value output by the preprocessing unit 133, and generates the second adjustment voltage based on the second control code value. The first adjustment voltage V1 and the second adjustment voltage V2 satisfy: V1 = 1 / G*V2, G represents the ideal gain of the inter-stage gain module 120.

[0064] As an implementation, with reference to FIG. 1 to FIG. 3, when the first analog-digital conversion module 110-1 is in the holding state, the inter-stage gain module 120 is in the amplification state, the first injection unit 131 and the second injection unit 132 are in the injection state, and the second analog-digital conversion module 110-2 is in the sampling state. Wherein, when the first analog-digital conversion module 110-1 is in the holding state, the quantization residual is output to the inter-stage gain module 120; when the inter-stage gain module 120 is in the amplification state, the quantization error is amplified; when the first injection unit 131 is in the injection state, the first adjustment voltage V1 is subtracted at the input end of the inter-stage gain module 120; and when the second injection unit 132 is in the injection state, the second adjustment voltage V2 is added at the output end of the inter-stage gain module 120.

[0065] Optionally, when the first analog-to-digital conversion module 110-1 is in the sampling state or the conversion state, the inter-stage gain module 120, the first injection unit 131 and the second injection unit 132 are in the reset state. When the first analog-to-digital conversion module 110-1 is in the sampling state, the input signal is sampled. When the first analog-to-digital conversion module 110-1 is in the conversion state, the sampled input signal is converted into a digital signal and a first code value is output. When the first analog-to-digital conversion module 110-1 is in the holding state, a quantization residual is output. When the inter-stage gain module 120, the first injection unit 131 and the second injection unit 132 are in the reset state, the inter-stage gain module 120 is disconnected from the first analog-to-digital conversion module 110-1 and does not perform amplification. The first injection unit 131 and the second injection unit 132 can receive a preset code value and generate a corresponding voltage. When the first injection unit 131 and the second injection unit 132 are in the injection state, the first injection unit 131 is controlled by a first control code value to decrease the output voltage, and the second injection unit 132 is controlled by a second control code value to increase the output voltage, so as to subtract the first adjustment voltage at the input end of the inter-stage gain module 120 and add the second adjustment voltage at the output end of the inter-stage gain module 120.

[0066] For example, when the inter-stage gain module 120, the first injection unit 131 and the second injection unit 132 are in the reset state, the preprocessing unit 133 outputs a first preset code value to the first injection unit 131, and outputs a second preset code value to the second injection unit 132.

[0067] In some embodiments, the second injection unit 132 at least partially multiplexes the second analog-to-digital conversion module 110-2. For example, the second analog-to-digital conversion module 110-2 includes a switched capacitor array, and the second injection unit 132 at least partially multiplexes the switched capacitor array of the second analog-to-digital conversion module 110-2, which can save area and power consumption. For example, the second analog-to-digital conversion module 110-2 is a successive approximation register (SAR) analog-to-digital converter, which can include a digital-to-analog conversion unit, a comparator and SAR logic. The digital-to-analog conversion unit can be a capacitive analog-to-digital conversion unit, which can include a switched capacitor array. The switched capacitor array is controlled by a sampling control signal to sample in a sampling stage, and is controlled by the SAR logic to convert in a conversion stage. The second injection unit 132 can multiplex a high preset bit of the switched capacitor array.

[0068] As an implementation, when the second injection unit 132 multiplexes the switched capacitor array of the second analog-to-digital conversion module 110-2, and the first analog-to-digital conversion module 110-1 is in a holding state, the inter-stage gain module 120 is in an amplification state, the first injection unit 131 is in an injection state, and the second analog-to-digital conversion module 110-2 is in an injection and sampling state. Taking the second control code value with P2 bits as an example, when the second analog-to-digital conversion module 110-2 is in an injection and sampling state, the high P2 bits of the switched capacitor array of the second analog-to-digital conversion module 110-2 are controlled by the second control code value, and the remaining bits are controlled by the sampling control signal, so that the sampling result includes the output of the inter-stage gain module and the injected second adjustment voltage; when the second analog-to-digital conversion module 110-2 is in a conversion state, the switched capacitor array of the second analog-to-digital conversion module 110-2 is controlled by the conversion logic, and P2 is less than the number of bits of the second analog-to-digital conversion module 110-2.

[0069] For example, the second analog-to-digital conversion module 110-2 is an SAR analog-to-digital converter, which includes an L-bit switched capacitor array, the second code value output by the second analog-to-digital conversion module 110-2 is L bits, and the second injection unit 132 can multiplex the high preset bits of the switched capacitor array. That is, in the sampling stage of the second analog-to-digital conversion module 110-2, the high preset bits (for example, the high P2 bits) of the L-bit switched capacitor array are controlled by the second control code value, and the remaining bits are controlled by the sampling control signal, and the sampling stage obtains the output of the inter-stage gain module 120 and the injected second adjustment voltage; in the conversion stage of the second analog-to-digital conversion module 110-2, the L-bit switched capacitor array is controlled by the SAR logic to perform analog-to-digital conversion on the signal obtained in the sampling stage, and since the second adjustment voltage offsets the first adjustment voltage, the conversion result is the conversion result corresponding to the quantization residual after gain amplification.

[0070] FIG. 4 shows a schematic diagram of a pipeline analog-to-digital conversion circuit according to an embodiment of the present application. As shown in FIG. 4, the pipeline analog-to-digital conversion circuit 400 includes a first analog-to-digital conversion module 411, a second analog-to-digital conversion module 412, an inter-stage gain module 420, an adjustment module 430, and a code value merging module 440. The adjustment module 430 includes a first injection unit 431, a second injection unit 432, and a preprocessing unit 433. It should be understood that the embodiments of the present application are not limited to two-stage pipeline analog-to-digital converters, but can be applied to multi-stage pipeline analog-to-digital converters, and an inter-stage gain module and a corresponding adjustment module can be arranged between any two adjacent stages.

[0071] As an implementation, as shown in FIG. 4, the inter-stage gain module 420 can include an amplification unit 421 and a feedback network 422.

[0072] Figure 5 shows a timing diagram of the pipelined analog-to-digital conversion circuit 400. As shown in Figure 5, during the sampling (SH1) and conversion (SAR1) of the first analog-to-digital conversion module 411, the first injection unit 431, the inter-stage gain module 420, and the second injection unit 432 are in a reset state.

[0073] When the first analog-to-digital conversion module 411 finishes conversion, a first code value D1 is obtained <m-1:0>and output to the code value merging module 440, the first analog-digital conversion module 411 enters a holding state, and outputs the generated quantization residual to the inter-stage gain module 420, while the preprocessing unit 433 outputs D3 <p-1:0>to the first injection unit 431 and the second injection unit 432, where D3 <p-1:0>may be derived from the D2 of the previous cycle or cycles <l-1:0>P = L, the number of bits of the first injection unit 431 and the second injection unit 432 and the second analog-to-digital conversion module 412 are the same; when P < L, the pre-processing unit 433 processes D2 <l-1:0>Truncating low data gives D3 <p-1:0>). The first injection unit 431 is based on D3 <p-1:0>The first and second adjustment voltages are output, the first adjustment voltage is injected at the input of the inter-stage gain module 420, and the second adjustment voltage is injected at the output of the inter-stage gain module 420.

[0074] When the first analog-to-digital conversion module 411 enters the holding state, the inter-stage gain module 420 is in the amplification state (RA) at the same time, and the second analog-to-digital conversion module 412 is in the sampling stage (SH2) at the same time. After the second analog-to-digital conversion module 412 ends sampling, it enters the conversion stage (SAR2), and the first injection unit 431, the inter-stage gain module 420, and the second injection unit 432 return to the reset state, wherein the preprocessing unit 431 outputs D3 <p-1:0>reverts to default values. The first analog to digital conversion module 411 enters the pipeline operation of sampling and conversion for the next cycle.

[0075] D2 is generated when the second analog to digital conversion module 412 completes conversion <l-1:0>, the final overall code value D is generated by the code value merging module 440 <n-1:0>The structure can eliminate the influence of gain error of the inter-stage gain module and improve the performance of the pipeline analog-to-digital conversion circuit by adjusting the first adjustment voltage at the input end of the inter-stage gain module based on the predicted quantization residual to realize high-pass filtering and injecting the second adjustment voltage at the output end of the inter-stage gain module to restore the quantization residual of the current analog-to-digital conversion cycle. The gain error of the amplifier and the gain error introduced by the capacitor mismatch in the feedback network can be eliminated, and the performance of the overall pipeline analog-to-digital converter can be improved.

[0076] FIG. 6 shows a schematic diagram of another pipeline analog-to-digital conversion circuit provided by the embodiment of the present application. As shown in FIG. 6, the pipeline analog-to-digital conversion circuit 600 can include a first analog-to-digital conversion module 611, a second analog-to-digital conversion module 612, an inter-stage gain module 620, an adjustment module 630, and a code value merging module 640. The adjustment module 630 includes a first injection unit 631 and a preprocessing unit 633. The embodiment multiplexes the second analog-to-digital conversion module 612 as a second injection unit. As an embodiment, as shown in FIG. 6, the inter-stage gain module 620 can include an amplification unit 621 and a feedback network 622.

[0077] The second analog-to-digital conversion module 612 can include a digital-to-analog conversion unit, and the second injection unit 632 at least partially multiplexes the digital-to-analog conversion unit of the second analog-to-digital conversion module 612, which can save area and power consumption. For example, the second analog-to-digital conversion module 612 is a successive approximation analog-to-digital converter, which can include a digital-to-analog conversion unit, a comparator, and SAR logic. The digital-to-analog conversion unit can include a capacitor switching array. The second injection unit 632 can multiplex the high preset bit of the switching capacitor array.

[0078] FIG. 7 shows a timing diagram of the pipeline analog-to-digital conversion circuit 600. As shown in FIG. 7, during the sampling and conversion of the first analog-to-digital conversion module 611, the first injection unit 631 and the inter-stage gain module 620 are in a reset state, and when the first analog-to-digital conversion module 611 completes conversion to obtain D1 <m-1:0>After outputting to the code value merging module 640, the first analog-digital conversion module 611 enters a holding state.

[0079] When the first analog-digital conversion module 611 enters the holding state, the generated quantization residual is output to the inter-stage gain module 620, and the pre-processing unit 633 outputs D3 <p-1:0>to the first injection unit and the second analog-to-digital conversion module 612 (multiplexed as the second injection unit), the D3 <p-1:0>D2 of the previous or several previous cycles <l-1:0>Produced.

[0080] When the first analog-to-digital conversion module 611 enters the hold state, the inter-stage gain module 620 is in the amplification state, and the second analog-to-digital conversion module 612 is simultaneously in the sampling and injection phase (D3 <p-1:0>control takes effect). After the second analog-to-digital conversion module 612 ends sampling, it enters the conversion phase, and the first injection unit 631 and the inter-stage gain module 620 return to the reset state. At the same time, the first analog-to-digital conversion module 611 can enter the pipeline operation of sampling and conversion of the next cycle, in which the preprocessing unit 633 outputs D3 <p-1:0>Resets to default, this stage the second analog conversion module 612 gives priority to conversion function, D3 <p-1:0>The control function of the first module does not take effect.

[0081] When the second analog-to-digital conversion module 612 completes conversion, D2 <l-1:0>, the final overall code value D is generated by the code value merging module 640 <n-1:0>.

[0082] In this embodiment, the gain error of the amplifier and the gain error introduced by the capacitor mismatch in the feedback network can be eliminated by the pre-processing unit combined with the first injection unit and the second injection unit, the performance of the overall pipeline ADC is improved, and the second ADC module is reused as the second injection unit to save area and power consumption.

[0083] FIG. 8 shows a circuit diagram of a pipeline ADC circuit according to an embodiment of the present application. As shown in FIG. 8, the pipeline ADC circuit 800 can include a first ADC module 811, a second ADC module 812, an inter-stage gain module 820, an adjusting module 830, and a code merging module 840. The first ADC module 811 includes an M-bit SAR ADC, and the second ADC module 812 includes an L-bit SAR ADC. The inter-stage gain module 820 includes an amplifier AMP and a feedback capacitor CFP / N. The adjusting module 830 includes a first injection unit 831, a second injection unit 832, and a pre-processing unit 833.

[0084] During the sampling (SW1P / N is on) and conversion (SW1P / N is off) of the first ADC module 811, the first injection unit 831, the inter-stage gain module, and the second injection unit are all in the reset state, the switches S2 / S3 / S4 in the inter-stage gain module are all in the on state, S1 / S5 are in the off state, and the control signal D3 of the first injection unit and the second injection unit is in the reset value (for example, D3 <p-1:0>= 100000, P = 6). When the first analog-to-digital conversion module 811 completes conversion, D1 <m-1:0>and output to the code value merging module 840, after which the first analog-digital conversion module 811 enters a holding state, and the generated quantization residue is output to the inter-stage gain module 820, while the preprocessing unit outputs D3 <p-1:0>to the first injection unit 831 and the second injection unit 832, this D3 <p-1:0>D2 of the previous or several previous cycles <l-1:0>produced (e.g., in a manner that only utilizes the D2 results of the previous cycle to produce D3: D3(i) <p-1:0>= D2(i-1) <l-1:0>, P = L, where D2(i-1) represents the D2 generated in the previous cycle; and the manner of generating D3 using the results of D2 of the previous two cycles, for example: D3 <p-1:0>= 2 * D2(i-1) <l-1:0>- D2(i-2) <l-1:0>D2(i) = D2(i-1) + D2(i-2), P = L, where D2(i-1) represents the D2 generated in the previous cycle, and D2(i-2) represents the D2 generated in the cycle before the previous cycle). When the first analog-to-digital conversion module 811 enters the holding state (SW1 P / N holding is off), the amplifier AMP in the inter-stage gain module 820 is in the amplification state, where the switches S2 / S3 / S4 in the inter-stage gain module 820 are all in the off state, S1 / S5 are in the on state, the second injection unit 832 is in the injection state, and the second analog-to-digital conversion module 812 is in the sampling state (SW2 P / N is on) at the same time. When the sampling of the second analog-to-digital conversion module 812 is completed, the conversion stage is entered (SW2 P / N is off), and the first injection unit 831, the inter-stage gain module 820, and the second injection unit 832 all return to the reset state, and the first analog-to-digital conversion module 811 enters the pipeline operation of the sampling and conversion in the next cycle, where the preprocessing unit 833 outputs D3 <p-1:0>Restore to default values (such as D3 <p-1:0>= 100000, P = 6). When the second analog-to-digital conversion module 812 completes conversion, D2 <l-1:0>, the final overall code value D is generated by the code value merging module <n-1:0>The structure can eliminate the gain error of the amplifier and the gain error introduced by the capacitance mismatch in the feedback network through the pre-processing unit 833 combined with the first injection unit 832 and the second injection unit 831, and improve the performance of the overall pipeline analog-to-digital converter.

[0085] FIG. 9 shows a circuit diagram of another pipeline analog-to-digital conversion circuit according to an embodiment of the present application. As shown in FIG. 9, the pipeline analog-to-digital conversion circuit 900 can include a first analog-to-digital conversion module 911, a second analog-to-digital conversion module 912, an inter-stage gain module 920, an adjustment module 930, and a code value merging module 940. The first analog-to-digital conversion module 911 includes an M-bit SAR ADC, and the second analog-to-digital conversion module 912 includes an L-bit SAR ADC. The inter-stage gain module 920 includes an amplifier AMP and a feedback capacitance CFP / N. The adjustment module 930 includes a first injection unit 931 and a pre-processing unit 933, and the second analog-to-digital conversion module 912 is multiplexed as a second injection unit.

[0086] During the sampling (SW1P / N is turned on) and conversion (SW1P / N is turned off) of the first analog-to-digital conversion module 911, the first injection unit 931 and the inter-stage gain module 920 are in a reset state, the switches S2 / S3 / S4 in the inter-stage gain module 920 are all in a conducting state, S1 / S5 are in a non-conducting state, and the control signal D3 of the first injection unit and the second injection unit (the second analog-to-digital conversion module 912 is multiplexed) is in a reset value (for example, D3 <p-1:0>= 100000, P = 6). When the first analog-to-digital conversion module 911 completes conversion, D1 <m-1:0>and output to the code value merging module 940, after which the first analog-digital conversion module 911 enters a hold state (SW1 P / N hold closed), outputting the generated quantization residue to the inter-stage gain module, while the preprocessing unit outputs D3 <p-1:0>to the first and second injection units, the D3 <p-1:0>D2 from the previous cycle or cycles <l-1:0>produced (e.g., in a manner that only utilizes the D2 results of the previous cycle to produce D3: D3(i) <p-1:0>= D2(i-1) <l-1:0>, P = L, where D2(i-1) represents the D2 generated in the previous cycle; and the manner of generating D3 using the results of D2 of the previous two cycles, for example: D3 <p-1:0>= 2 * D2(i-1) <l-1:0>- D2(i-2) <l-1:0>, P = L, where D2(i - 1) represents the D2 generated in the previous cycle, and D2(i - 2) represents the D2 generated in the previous two cycles). When the first analog-to-digital conversion module 911 enters the hold state (SW1 P / N hold is off), the amplifier is in the amplification state, in which the switches S2 / S3 / S4 in the inter-stage gain module are all in the off state, and S1 / S5 are in the on state, and the second analog-to-digital conversion module 912 simultaneously performs the sampling (SW2 P / N is on) and injection stages (D3 control is effective). After the sampling and injection of the second analog-to-digital conversion module 912 are completed, the conversion stage (SW2 P / N is off) is entered, and the first injection unit and the amplifier both return to the reset state, and at the same time, the first analog-to-digital conversion module 911 enters the pipeline operation of the sampling and conversion in the next cycle, in which the preprocessing unit outputs D3 <p-1:0>Restore to default values (such as D3 <p-1:0>= 100000, P = 6), the second A / D conversion module 912 is given priority to perform the conversion function, and the control function of D3 is not effective. When the second A / D conversion module 912 completes the conversion, D2 is generated <l-1:0>, the final overall code value D is generated by the code value merging module <n-1:0>The structure can eliminate the gain error of the amplifier and the gain error introduced by the capacitor mismatch in the feedback network, improve the performance of the overall pipeline analog-to-digital converter, and multiplex the second analog-to-digital conversion module 912 as the second injection unit, thereby saving area and power consumption.

[0087] FIG. 10 shows a circuit diagram of a first injection unit according to an embodiment of the present application, and FIG. 11 shows a circuit diagram of another first injection unit according to an embodiment of the present application. As shown in FIGS. 10 and 11, the first injection unit in the foregoing FIGS. 1 to 3, 4, 6, 8, or 9 can include a first conversion unit 1001 and a scaling unit 1002. The first conversion unit 1001 is configured to convert a first control code value into a first voltage. The scaling unit 1002 is configured to scale down the first voltage according to a gain of an inter-stage gain module and output a first adjusted voltage.

[0088] In some embodiments, referring to FIG. 8 or 9, the inter-stage gain module can include an amplification unit configured to amplify a gain margin, and a feedback capacitor connected between an input terminal and an output terminal of the amplification unit. The scaling unit 1002 can include a scaling capacitor connected between an output terminal of the first conversion unit 1002 and the input terminal of the amplification unit, and the scaling capacitor has a same capacitance value as the feedback capacitor. Through this embodiment, the first voltage is scaled down according to the gain of the inter-stage gain module and the first adjusted voltage is outputted on the basis of the feedback capacitor in combination with the scaling capacitor having the same capacitance value.

[0089] Referring to FIGS. 8, 9, 10, and 11, the feedback capacitor can include a first feedback capacitor CFP connected between a first input terminal and a first output terminal of the amplification unit, and a second feedback capacitor CFN connected between a second input terminal and a second output terminal of the amplification unit. The scaling capacitor can include a first scaling capacitor CSP connected between a first output terminal of the first conversion unit 1001 and the first input terminal of the amplification unit, and a second scaling capacitor CSN connected between a second output terminal of the first conversion unit and the second input terminal of the amplification unit. The first scaling capacitor CSP has a same capacitance value as the first feedback capacitor CFP, and the second scaling capacitor CSN has a same capacitance value as the second feedback capacitor CFN. Thus, the first voltage is scaled down according to the gain of the inter-stage gain module and the first adjusted voltage is outputted.

[0090] As an embodiment, referring to FIG. 10, the first conversion unit 1001 can include a first switched capacitor array, for example, a CP / N <p-1:0>Capacitor array, CP / N of P bits <p-1:0>Each switch in the array of capacitors receives a first control code value to convert the first control code value to its corresponding first voltage. Optionally, as shown in FIG. 10, the scaling unit 1002 can include a first scaling capacitor CSP and a second scaling capacitor CSN, whose outputs VO1P / N are connected to the VP / N nodes in FIG. 8 or FIG. 9, respectively, and whose sizes are equal to the feedback capacitors CFP / N in the inter-stage gain module to scale down the first voltage by the gain of the inter-stage gain module and output a first adjusted voltage.

[0091] As another implementation, referring to FIG. 11, the first converting unit 1001 can include a first array of switch resistors, for example, as shown in FIG. 11, the first array of switch resistors can include a string of P bits of resistors, each switch in the string of P bits of resistors receiving a first control code value to convert the first control code value to its corresponding first voltage. Optionally, as shown in FIG. 11, the scaling unit 1002 can include a first scaling capacitor CSP and a second scaling capacitor CSN, whose outputs VO1P / N are connected to the VP / N nodes in FIG. 8 or FIG. 9, respectively, and whose sizes are equal to the feedback capacitors CFP / N in the inter-stage gain module to scale down the first voltage by the gain of the inter-stage gain module and output a first adjusted voltage.

[0092] FIG. 12 shows a circuit diagram of a second injecting unit according to an embodiment of the present application, wherein the second injecting unit can include a CP / N <p-1:0>The capacitor array, output V02P / N is connected to the VRAM POP / N node in Figure 8, respectively. And CP / N <p-1:0>The capacitance values from high to low are respectively and the second analog-to-digital conversion module CP / N <l-1:0>The capacitance values from the high to the low are equal. CP / N <p-1:0>The second control code value is converted into a second adjustment voltage corresponding thereto, and each switch in the capacitor array can receive the second control code value to realize the conversion. It should be understood that the second injection unit can also adopt the resistor array shown in FIG. 11, and the embodiments of the present application do not repeat the description.

[0093] The pipeline analog-digital conversion circuit in the embodiments of the present application adds the first injection unit, the second injection unit and the preprocessing unit on the basis of the traditional structure, eliminates the influence of the gain error of the amplifier itself and the gain error introduced by the feedback network mismatch. Meanwhile, the second analog-digital conversion module can be multiplexed as the second injection unit, thereby saving the area and power consumption.

[0094] The embodiments of the present application also provide an analog-digital conversion method, which can be realized by the analog-digital conversion circuit in the embodiments of the present application. As shown in FIG. 13, the method comprises the following steps:

[0095] In step S1301, the first analog-digital conversion module performs analog-digital conversion on the input thereof and outputs a first code value.

[0096] In step S1302, the inter-stage gain module amplifies the quantization residue of the first analog-digital conversion module.

[0097] In step S1303, during the amplification, the adjustment module outputs a first adjustment voltage and a second adjustment voltage based on one or more historical code values, injects the first adjustment voltage at the input end of the inter-stage gain module, and injects the second adjustment voltage at the output end of the inter-stage gain module to offset the second adjustment voltage.

[0098] Any historical code value is a code value obtained by the second analog-digital conversion module by performing analog-digital conversion on the corresponding quantization residue in any analog-digital conversion period before the current analog-digital conversion period.

[0099] In step S1304, the second analog-digital conversion module performs analog-digital conversion on the output of the inter-stage gain module and outputs a second code value.

[0100] In the embodiments of the present application, the analog-digital conversion result can be output based on the first code value and the second code value.

[0101] The method predicts the size of the quantization residue of the current analog-digital conversion period based on one or more historical code values, injects the first adjustment voltage at the input end of the inter-stage gain module to realize high-pass filtering, and injects the second adjustment voltage at the output end of the inter-stage gain module to offset the first adjustment voltage, thereby restoring the quantization residue of the current analog-digital conversion period, eliminating the influence of the gain error of the inter-stage gain module, and improving the performance of the pipeline analog-digital conversion circuit.

[0102] The chip also referred to as an integrated circuit (IC), the chip can be, but is not limited to, a SOC (System on Chip) chip, a SIP (system in package) chip. The chip eliminates the influence of the gain error of the amplifier itself and the gain error introduced by the feedback network mismatch by adding the first injection unit, the second injection unit and the preprocessing unit on the basis of the traditional structure. At the same time, the second analog-to-digital conversion module can be multiplexed as the second injection unit, saving area and power consumption.

[0103] The electronic device can be, but is not limited to, a body weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle-mounted charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a touch pen, a truly wireless earphone, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, and a cervical vertebra massage instrument. The mobile terminal includes, but is not limited to, a smart phone, a notebook computer, a tablet computer, and a POS (point of sales terminal) machine. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart sweeper, and a smart lamp. The electronic device eliminates the influence of the gain error of the amplifier itself and the gain error introduced by the feedback network mismatch by adding the first injection unit, the second injection unit and the preprocessing unit on the basis of the traditional structure. At the same time, the second analog-to-digital conversion module can be multiplexed as the second injection unit, saving area and power consumption.

[0104] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as the above preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes, without departing from the technical solution of the present application. Any modification, change, equivalent change and modification of the above embodiment according to the technical essence of the present application are still within the scope of the technical solution of the present application.

Claims

1. A pipelined analog-to-digital conversion circuit, characterized by Comprising: a first analog-to-digital conversion module; a second analog-to-digital conversion module; an inter-stage gain module connected between the first analog-to-digital conversion module and the second analog-to-digital conversion module, configured to amplify a quantization residual of the first analog-to-digital conversion module; an adjustment module configured to output a first adjustment voltage and a second adjustment voltage based on one or more historical code values in a current analog-to-digital conversion period, and inject the first adjustment voltage at an input end of the inter-stage gain module and the second adjustment voltage at an output end of the inter-stage gain module to offset the first adjustment voltage; wherein any historical code value of the one or more historical code values is a code value obtained by analog-to-digital conversion of a corresponding quantization residual by the second analog-to-digital conversion module in any analog-to-digital conversion period before the current analog-to-digital conversion period.

2. The pipelined analog-to-digital conversion circuit of claim 1, wherein, The adjustment module comprises: a first injection unit configured to receive a first control code value and output the first adjustment voltage based on the first control code value; wherein the first control code value is at least part of a digital bit of one of the historical code values; or the first control code value is at least part of a digital bit of a control code value generated based on a plurality of the historical code values.

3. The pipelined analog-to-digital conversion circuit of claim 2, wherein, The adjustment module further comprises: a second injection unit configured to receive a second control code value and output the second adjustment voltage based on the second control code value; wherein the first control code value and the second control code value have the same or different bit numbers; the first control code value and the second control code value are at least part of a digital bit of the same historical code value; or the first control code value and the second control code value are at least part of a digital bit of a control code value generated based on a plurality of the historical code values.

4. The pipelined analog-to-digital conversion circuit of claim 3, wherein, The adjustment module further comprises a preprocessing unit configured to: use one of the historical code values as a control code value, or generate the control code value based on a plurality of the historical code values; output high P1 bits of the control code value as the first control code value; output high P2 bits of the control code value as the second control code value, where P1 and P2 are positive integers.

5. The pipelined analog-to-digital conversion circuit of claim 3, wherein, When the first analog-to-digital conversion module is in a hold state, the inter-stage gain module is in an amplification state, the first injection unit and the second injection unit are in an injection state, and the second analog-to-digital conversion module is in a sampling state; wherein, when the first injection unit is in the injection state, the first adjustment voltage is injected at the input end of the inter-stage gain module; when the second injection unit is in the injection state, the second adjustment voltage is injected at the output end of the inter-stage gain module.

6. The pipelined analog-to-digital conversion circuit of claim 5, wherein, When the first analog-to-digital conversion module is in a sampling state or a conversion state, the inter-stage gain module, the first injection unit and the second injection unit are in a reset state.

7. The pipelined analog-to-digital conversion circuit of claim 2, wherein, The first injection unit comprises: a first conversion unit configured to convert the first control code value into a first voltage; a scaling unit configured to scale down the first voltage according to a gain of the inter-stage gain module and output the first adjustment voltage.

8. The pipeline analog-to-digital conversion circuit of claim 7, wherein, The inter-stage gain module comprises: an amplification unit configured to amplify the quantization residual; and a feedback capacitor connected between an input terminal and an output terminal of the amplification unit. The scaling unit comprises: a scaling capacitor connected between an output terminal of the first conversion unit and an input terminal of the amplification unit, and a capacitance value of the scaling capacitor is equal to a capacitance value of the feedback capacitor.

9. The pipelined analog-to-digital conversion circuit of claim 7, wherein, The first conversion unit comprises: a first switched-capacitor array, each switch in the first switched-capacitor array receiving the first control code value to convert the first control code value into the first voltage; or a first switched-resistor array, each switch in the first switched-resistor array receiving the first control code value to convert the first control code value into the first voltage.

10. The pipelined analog-to-digital conversion circuit of claim 3, wherein, The second injection unit comprises: a second conversion unit configured to convert the second control code value into the second adjustment voltage.

11. The pipelined analog-to-digital conversion circuit of claim 10, wherein, The second conversion unit comprises: a second switched-capacitor array, each switch in the second switched-capacitor array receiving the second control code value to convert the second control code value into the second adjustment voltage; or a second switched-resistor array, each switch in the second switched-resistor array receiving the second control code value to convert the second control code value into the second adjustment voltage.

12. The pipelined analog-to-digital conversion circuit of claim 3, wherein, The second injection unit at least partially multiplexes the second analog-to-digital conversion module.

13. The pipelined analog-to-digital conversion circuit of claim 12, wherein, The second analog-to-digital conversion module comprises a switched-capacitor array; When the second analog-to-digital conversion module is in an injection and sampling state, high P2 bits of the switched-capacitor array of the second analog-to-digital conversion module are controlled by the second control code value, and remaining bits are controlled by a sampling control signal; When the second analog-to-digital conversion module is in a conversion state, the switched-capacitor array of the second analog-to-digital conversion module is controlled by conversion logic.

14. The pipelined analog-to-digital conversion circuit of any of claims 1 to 13, wherein, The adjustment module is configured to predict a code value of a current analog-to-digital conversion period based on one or more historical code values, and output the first adjustment voltage and the second adjustment voltage based on the predicted code value, the second adjustment voltage being G times the first adjustment voltage, G representing an ideal gain of the inter-stage gain module.

15. A chip, characterized by The pipeline analog-to-digital conversion circuit comprises any one of the pipeline analog-to-digital conversion circuits in claims 1-14.

16. An electronic device, comprising: The device comprises a device body and a chip as claimed in claim 15 disposed on the device body.

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