Systems and methods for design of a metrology target

Abstract

Improved systems and methods for optimizing a two-dimensional metrology target are disclosed. The method includes decomposing a two-dimensional metrology target associated with a lithography process into one or more reduced-dimension metrology targets, simulating a performance of the one or more reduced-dimension metrology targets, and optimizing the two-dimensional metrology target based on the simulated performance of the one or more reduced-dimension metrology targets.

Description

SYSTEMS AND METHODS FOR DESIGN OF A METROLOGY TARGETCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of International application PCT / CN2024 / 101247 which was filed on 25 June 2024 and which is incorporated herein in its entirety by reference.TECHNICAL FIELD

[0002] The embodiments provided herein relate to methods and apparatuses for designing metrology targets used in manufacturing semiconductor devices using lithography processes, and more particularly to methods of simulating the design of two-dimensional continuous bias diffraction-based overlay (2D-cDBO) targets.BACKGROUND

[0003] In a manufacturing process, variations in various process parameters may have significant impact on the design of a suitable metrology target or alignment target to faithfully reflect a device design. Such process parameters that may alter the metrology target or alignment target may include, but are not limited to, side-wall angle (determined by e.g., the etching or development process), refractive index (of a device layer or a resist layer), thickness (of a device layer or a resist layer), frequency of incident radiation, etch depth, floor tilt, extinction coefficient for the radiation source, coating asymmetry (for a resist layer or a device layer), variation in erosion during a chemicalmechanical polishing process, and the like. Computational techniques may also be used to define a metrology target for use in, e.g., a metrology system through a metrology system simulation or in a target manufacturing process simulation (e.g., including exposing the metrology target using a lithographic process, developing the metrology target, etching the target, etc.). In a similar manner an alignment target may be defined. A metrology target design or alignment target design may be characterized by various parameters. For the metrology target these parameters may be, for example, target coefficient (TC), stack sensitivity (SS), overlay impact (OV), or the like. Stack sensitivity may be understood as a measurement of how much the intensity of the signal changes as e.g., overlay changes because of diffraction between target (e.g., grating) layers. Target coefficient may be understood as a measurement of signal-to-noise ratio for a particular measurement time as a result of variations in photon collection by the measurement system. In an embodiment, the target coefficient may also be thought of as the ratio of stack sensitivity to photon noise; that is, the signal (i.e., the stack sensitivity) may be divided by a measurement of the photon noise to determine the target coefficient. Overlay impact measures the change in overlay error as a function of target geometry changes.

[0004] The metrology target design or alignment target design may specify one or more design parameters (e.g., geometric dimensions) for the target and further discrete values or a range of valuesmay be specified for the one or more design parameters. Furthermore, a user or the system may impose one or more constraints on one or more design parameters (e.g., a relationship between pitch and trench width, a limit on pitch or trench width, a relationship between critical dimension (CD) and pitch (e.g., CD is less than pitch), etc.) either in the same layer or between layers, based on, e.g., the lithographic process for which the target is desired. The one or more constraints may alternatively be on the one or more design parameters for which discrete values or a range has been specified, or on one or more other design parameters. The potential metrology target designs or alignment target designs may be input to a simulation to determine, for example, the viability and / or suitability of one or more of the target designs. The constraints may comprise a metrology parameter constraint. For example, in some metrology systems, the physics of the system may place a constraint (e.g., a wavelength of radiation used in the system may constrain the pitch of the target design). Alternatively, the constraint may be a process parameter constraint (e.g., a constraint dependent on etch type, development type, resist type, etc.). The terms “target,” ’’target grating,” and ’’target structure” as used herein do not require that the structure has been provided specifically for the measurement being performed. Targets may comprise gratings, e.g., used in diffraction measurement techniques, but also other target types may be used such as box-in-box image-based overlay targets. The metrology targets may be used to determine overlay, CD, focus, dose, etc., and may be defined using a data structure such as a pixel-based data structure or a polygon-based data structure. The polygon-based data structure may, for example, be described using GDSII data formats, which are rather common in the chip manufacturing industry. Still, any suitable data structure or data format may be used without departing from the scope of the embodiments.SUMMARY

[0005] Some embodiments of the present disclosure provide a method of optimizing a metrology target. The method may comprise decomposing a two-dimensional metrology target associated with a lithography process into one or more reduced-dimension metrology targets, simulating a performance of the one or more reduced-dimension metrology targets, and optimizing the two-dimensional metrology target based on the simulated performance of the one or more reduced-dimension metrology targets.

[0006] Another aspect of the present disclosure is directed to a computer program product comprising a non-transitory computer-readable medium having a set of instructions stored thereon, the instructions when executed by at least one processor of an apparatus are configured to cause the processor to perform a method for optimizing a two-dimensional metrology target. The method may comprise decomposing a two-dimensional metrology target associated with a lithography process into one or more reduced-dimension metrology targets, simulating a performance of the one or more reduced-dimension metrology targets, and optimizing the two-dimensional metrology target based on the simulated performance of the one or more reduced-dimension metrology targets.

[0007] Other advantages of the embodiments of the present disclosure will become apparent from the following description taken in conjunction with the accompanying drawings wherein are set forth, by way of illustration and example, certain embodiments of the present invention.BRIEF DESCRIPTION OF FIGURES

[0008] The above and other aspects of the present disclosure will become more apparent from the description of exemplary embodiments, taken in conjunction with the accompanying drawings.

[0009] Fig. 1 illustrates a block diagram of various exemplary subsystems of a lithography system, consistent with embodiments of the present disclosure.

[0010] Fig. 2 shows a flowchart listing stages of an exemplary method to design metrology targets, consistent with embodiments of the present disclosure.

[0011] Fig. 3A shows a schematic layout of an exemplary cDBO target, consistent with embodiments of the present disclosure.

[0012] Figs. 3B and 3C illustrate first order diffraction from a pDBO target and a cDBO target, respectively, consistent with embodiments of the disclosure.

[0013] Fig. 4 is a process flowchart for an exemplary method for optimizing a metrology target associated with a lithography process, consistent with embodiments of the present disclosure.

[0014] Fig. 5 illustrates an exemplary 2D-cDBO metrology target decomposed as two ID-cDBO metrology targes, consistent with embodiments of the present disclosure.

[0015] Fig. 6 illustrates exemplary dark-field diffraction images of ID-cDBO metrology target in the x- and y- directions and a superimposed dark-field diffraction image of ID-cDBO metrology target, consistent with embodiments of present disclosure.

[0016] Fig. 7 illustrates an exemplary hybrid metrology target, consistent with embodiments of the present disclosure.

[0017] Fig. 8 illustrates a block diagram of an exemplary apparatus for processing data, consistent with some embodiments of the present disclosure.DETAILED DESCRIPTION

[0018] Relative dimensions of components in drawings may be exaggerated for clarity. Within the following description of drawings, the same or like reference numbers refer to the same or like components or entities, and only the differences with respect to the individual embodiments are described. As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a component may include A or B, then, unless specifically stated otherwise or infeasible, the component may include A, or B, or A and B. As a second example, if it is stated that a component may include A, B, or C, then, unless specifically stated otherwise or infeasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0019] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments do not represent all implementations. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the disclosed embodiments as recited in the appended claims. For example, although some embodiments are described in the context of utilizing electron beams, the disclosure is not so limited. Other types of charged particle beams may be similarly applied. Furthermore, other imaging systems may be used, such as optical imaging, photo detection, x-ray detection, etc.

[0020] Manufacturing semiconductor devices, typically involves processing a substrate (e.g., a semiconductor wafer) using a number of fabrication processes to form various features and multiple layers of the devices. Such layers and features are typically manufactured and processed using, e.g., deposition, lithography (which typically involves transferring a pattern to a radiation-sensitive resist arranged on the substrate), etch, chemical-mechanical polishing, and ion implantation. Multiple devices may be fabricated on a plurality of dies on a substrate and then separated into individual devices.

[0021] Metrology processes are used at various steps during a device manufacturing process to monitor and control the process. For example, metrology processes are used to measure one or more characteristics of a substrate, such as a relative location (e.g., overlay, alignment, etc.) or dimension (e.g., line width, critical dimension, thickness, etc.) of features formed on the substrate during a process, such that the performance of the process can be determined from the one or more characteristics. If the one or more characteristics are unacceptable (e.g., out of a predetermined range for the characteristic(s)), the measurements of the one or more characteristics may be used to alter one or more parameters of the process such that further substrates manufactured by the process have an acceptable characteristic(s).

[0022] So, significant aspects to enabling a device manufacturing process include developing the process itself, setting it up for monitoring and control and then actually monitoring and controlling the process itself. Assuming a configuration of the fundamentals of the device manufacturing process, such as the patterning device pattern(s), the resist type(s), the post-lithography process steps, etc., it is desirable to setup the lithographic apparatus for transferring the pattern onto the substrates, design and develop the metrology targets to monitor the process, setup the metrology processes to measure the metrology targets and then implement a process of monitoring and controlling the process based on measurements of the metrology targets.

[0023] Although specific reference may be made in this text to the manufacture of ICs, it should be explicitly understood that the description herein has many other possible applications. For example, it may be employed in the manufacture of integrated optical systems, guidance and detection patternsfor magnetic domain memories, liquid-crystal display panels, thin-film magnetic heads, etc. The skilled artisan will appreciate that, in the context of such alternative applications, any use of the terms “reticle,” “wafer,” or “die” in this text should be considered as interchangeable with the more general terms “mask,” “substrate,” and “target portion,” respectively. The term “mask” or “patterning device” as employed in this text may be broadly interpreted as referring to a generic patterning device that can be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate. Besides the classic mask (transmissive or reflective, binary, phase-shifting, hybrid, etc.), examples of other such patterning devices include: a programmable mirror array. An example of such a device is a matrix-addressable surface having a viscoelastic control layer and a reflective surface. The basic principle behind such an apparatus is that (for example) addressed areas of the reflective surface reflect incident radiation as diffracted radiation, whereas unaddressed areas reflect incident radiation as undiffracted radiation. Using an appropriate filter, the said undiffracted radiation can be filtered out of the reflected beam, leaving only the diffracted radiation behind; in this manner, the beam becomes patterned according to the addressing pattern of the matrix-addressable surface. The required matrix addressing can be performed using suitable electronic means.

[0024] The patterning device can comprise, or can form, one or more design layouts. The design layout can be generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional design layouts / patterning devices. These rules are set by processing and design limitations. For example, design rules define the space tolerance between devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the devices or lines do not interact with one another in an undesirable way. One or more of the design rule limitations may be referred to as “critical dimension” (CD). A critical dimension of a device can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed device. Of course, one of the goals in device fabrication is to faithfully reproduce the original design intent on the substrate (via the patterning device).

[0025] In the present document, the terms “radiation” and “beam” are used to encompass all types of electromagnetic radiation, including ultraviolet radiation (e.g., with a wavelength of 365 nm, 248 nm, 193 nm, 157 nm or 126 nm) and EUV (extreme ultra-violet radiation, e.g., having a wavelength in the range of about 5-100 nm).

[0026] A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, a patterning device (e.g., a mask) may contain or provide a circuit pattern corresponding to an individual layer of the IC (“design layout”), and this circuit pattern can be transferred onto a target portion (e.g. comprising one or more dies) on a substrate (e.g., a silicon wafer) that has been coated with a layer of radiation-sensitive material (“resist”), by methods such asirradiating the target portion through the circuit pattern on the patterning device. In general, a single substrate contains a plurality of adjacent target portions to which the circuit pattern is transferred successively by the lithographic apparatus, one target portion at a time. In one type of lithographic apparatuses, the circuit pattern on the entire patterning device is transferred onto one target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, a projection beam scans over the patterning device in a given reference direction (the “scanning” direction) while synchronously moving the substrate parallel or anti-parallel to this reference direction. Different portions of the circuit pattern on the patterning device are transferred to one target portion progressively. Since, in general, the lithographic apparatus will have a magnification factor M (generally <1), the speed F at which the substrate is moved will be a factor M times that at which the projection beam scans the patterning device.

[0027] Prior to transferring the circuit pattern from the patterning device to the substrate, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement / inspection of the transferred circuit pattern. This array of procedures is used as a basis to make an individual layer of a device, e.g., an IC. The substrate may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemical-mechanical polishing, etc., all intended to finish off the individual layer of the device. If several layers are required in the device, then the whole procedure, or a variant thereof, is repeated for each layer. Eventually, a device will be present in each target portion on the substrate. These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.

[0028] As noted, microlithography is a central step in the manufacturing of ICs, where patterns formed on substrates define functional elements of the ICs, such as microprocessors, memory chips etc. Similar lithographic techniques are also used in the formation of flat panel displays, micro- electro-mechanical systems (MEMS) and other devices.

[0029] In lithographic processes, it is desirable to frequently make measurements of structures created for process control and verification. One or more parameters of the structures are typically measured or determined, for example, the overlay error between successive layers formed in or on the substrate. However, target selection by frequent measurement is labor-intensive and time-consuming. Therefore, it makes sense to implement a computer-aided design (CAD) system that is capable of automatically generating designs of metrology targets in the simulation domain without the need for actual frequent measurement. The metrology targets as described herein may be, for example, overlay targets designed for use with a metrology tool, including an optical metrology tool such as a spectrometer, or a spectroscopic ellipsometer, or the like. In general, metrology targets for use withsuch systems should be printed on the substrate with dimensions that meet the design specification for the particular microelectronic device to be imaged on that substrate.

[0030] Currently, metrology target designers measure dimensions of patterns formed on a resist layer, and feed that data to a computerized lithography process model to predict the device structure that will be printed on the actual substrate. However, as lithography processes get more complex, the device structure formed on the substrate after processing tend to become significantly different from the patterns formed in the resist. Examples of complex lithography processes include spacer-based double lithography process, FinFET processes etc. Because of the process-induced complexities, it is becoming difficult for metrology target designers to render the correct target structure from measured or modeled resist patterns.

[0031] Additionally, some substrate structures (e.g., odd number of fins in a FinFET) are not compatible with the lithography process, but a designer could manually add those problematic structures by mistake. Those structures cannot be generated properly via a CAD tool. Also, without the CAD tool, targets of different designs for every layer or layer pairs have to be drawn one at a time. With the large number of lithography layers and different design options, the manual drawing of all possible targets become unmanageable. Therefore, not only automatic generation of metrology target design is important, but proper organization and easy retrieval of the auto-generated designs are equally important.

[0032] Further, it may be beneficial to alter target dimensions to test the design robustness with respect to process variations. Currently, the dimensional alterations are purely geometrical and may not be compatible with existing process flows. For example, in a FinFET process, some of the fin side wall angles are related and should be altered together. But the current methods cannot handle this special requirement. Therefore, it is desirable to have the capability to design multiple metrology targets in a flexible and time-and-resource-efficient manner in the simulation domain from which a lithographer may select the targets that are optimal for a selected process.

[0033] Fig. 1 is a schematic block diagram of various subsystems of a lithography system, consistent with embodiments of the present disclosure. A lithography apparatus or a lithography system is an apparatus that applies a desired pattern onto a target portion of a substrate such as a silicon wafer. As shown in Fig. 1, a lithography system 10 may comprise an illumination source 12, illumination optics 14, a mask 16 (or a reticle), and projection optics 18. Illumination source 12 may be a deep-ultraviolet excimer laser source or other type of sources including extreme ultraviolet (EUV) sources.Illumination optics 14 may define the partial coherence and may include optical components 14a and 14b that shape radiation from illumination source 12. Projection optics 18 can project an image of a mask pattern onto a substrate plane 19. An adjustable filter or aperture at the pupil plane of projection optics 18 may restrict the range of beam angles that impinge on the substrate plane 19. Although not illustrated, lithography apparatus may further include a processor, a preprocessor, a microprocessor, or the like, to process obtained data, implement simulations or models, etc.

[0034] In a lithographic apparatus, illumination source 12 provides an illumination (i.e., radiation) beam 13 to mask 16, which may impart a pattern to the illumination beam 13. For example, mask 16 may comprise any patterning device such as a reticle, a programmable mirror array such as a digital micromirror device (DMD), a computer-generated hologram (CGH), or other element configured to selectively modulate or block portions of illumination beam 13 to impart the pattern. The pattern may comprise, e.g., a layer in an integrated circuit or another semiconductor device pattern. Projection optics 18 may direct and shape the illumination, via mask 16, onto a substrate W. An adjustable filter or aperture 17 at the pupil plane of the projection optics may restrict the range of beam angles that impinge on the substrate plane 19, where the largest possible angle defines the numerical aperture of the projection optics NA= n*sin (0max), where “n” is the refractive index of the media between the substrate and the last element of the projection optics, and 0maxis the largest angle of the beam exiting from the projection optics that can still impinge on the substrate plane.

[0035] The term “projection optics” is broadly defined here to include any optical component that may alter the wavefront of the radiation beam. For example, projection optics may include at least some of illumination optics 14 and projection optics 18. In some embodiments, projection optics 18 may project a reduced image of the illuminated pattern by a reduction ratio of e.g., 4:1 or 5:1. As discussed below, in some embodiments, the projection optics may comprise an anamorphic system in which a first reduction ratio in a first direction on the pattern image may be different from a second reduction ratio in a second perpendicular direction on the pattern image.

[0036] In a lithographic projection apparatus, a source provides illumination (i.e., radiation) to a patterning device and projection optics direct and shape the illumination, via the patterning device, onto a substrate. The projection optics may include at least some of the optical components. An aerial image is the radiation intensity distribution at substrate level. A resist layer on the substrate is exposed and the aerial image is transferred to the resist layer as a latent “resist image” (RI) therein. The resist image (RI) can be defined as a spatial distribution of solubility of the resist in the resist layer. A resist model can be used to calculate the resist image from the aerial image, an example of which can be found in U.S. Patent Application Publication No. US 2009-0157260, the disclosure of which is hereby incorporated by reference in its entirety. The resist model is related only to properties of the resist layer (e.g., effects of chemical processes which occur during exposure, PEB and development). Optical properties of the lithographic projection apparatus (e.g., properties of the source, the patterning device, and the projection optics) dictate the aerial image. Since the patterning device used in the lithographic projection apparatus can be changed, it may be desirable to separate the optical properties of the patterning device from the optical properties of the rest of the lithographic projection apparatus including at least the source and the projection optics.

[0037] In a system for simulating a manufacturing process involving lithography and metrology targets, the major manufacturing system components and processes can be described by various functional modules. The functional modules may include a design layout module configured to definea metrology target design pattern, a patterning device layout module configured to define how the patterning device pattern is laid out in polygons based on the target design, a patterning device model module which models the physical properties of the pixelated and continuous-tone patterning device to be utilized during the simulation process, an optical model module configured to define the performance of the optical components of the lithography system, a resist model module configured to define the performance of the photoresist being utilized in a given process, a process model module configured to define performance of the post-resist development processes (e.g., etch), and a metrology module which defines the performance of a metrology system used with the metrology target and thus the performance of the metrology target when used with the metrology system. The results of one or more of the functional simulation modules, for example, predicted contours and CDs, are provided in a result module.

[0038] The properties of the illumination and projection optics are captured in the optical model module that includes, but is not limited to, NA-sigma (o) settings as well as any particular illumination source shape, where o (or sigma) is outer radial extent of the illuminator. The optical properties of the photo-resist layer coated on a substrate — i.e. refractive index, film thickness, propagation, and polarization effects — may also be captured as part of the optical model module. The resist model module may describe the effects of chemical processes which occur during resist exposure, post exposure bake (PEB) and development, in order to predict, for example, contours of resist features formed on the substrate. The patterning device model module is configured to capture how the target design features are laid out in the pattern of the patterning device and may include a representation of detailed physical properties of the patterning device. The objective of the simulation is to accurately predict, for example, edge placements and critical dimensions (CDs), which can then be compared against the target design. The target design is generally defined as the pre-OPC patterning device layout, and may be provided in a standardized digital file format such as GDSII or OASIS.

[0039] In a manufacturing process, variations in process parameters have significant impact on the design of a suitable target that can faithfully reflect a device design. Such process parameters include, but are not limited to, side-wall angle (determined by the etching or development process), refractive index of a device layer or a resist layer, thickness of a device layer or a resist layer, frequency of incident radiation, etch depth, floor tilt, extinction coefficient for the radiation source, coating asymmetry for a resist layer or a device layer, variation in erosion during a chemical-mechanical polishing process, or the like.

[0040] A metrology target design can be characterized by various parameters such as, for example, diffraction efficiency (DE), stack sensitivity (SS), overlay error (OVL), or the like. Stack sensitivity, as referred to herein, is a measurement of change in signal intensity as overlay changes because of diffraction between target (e.g., grating) layers. Diffraction efficiency can be understood as ratio of diffracted light intensity, of a given order, to the incident light intensity of a given wavelength.Overlay error is a measurement of the misalignment between neighboring patterned layers on a wafer or a substrate. To assist with the metrology target design, a computer-implemented method or a computer-implemented software program may be used.

[0041] Fig. 2 shows a flowchart listing stages of an exemplary computer-implemented method to design metrology targets. One or more stages may be added, omitted, or edited, as appropriate. In stage 210, the materials to be used in a lithography process may be selected. The materials may be selected from a materials library interfaced with a computer-implemented software program through appropriate GUI. In stage 220, a lithography process is defined by entering each of the process steps, and building a computer simulation model for the entire process sequence. In stage 230, a metrology target is defined, i.e. dimensions and other characteristics of various features included in the target are entered into the computer-implemented software program. For example, if a grating is included in a structure, then number of grating elements, width of individual grating elements, spacing between two grating elements etc., have to be defined. In stage 240, the 3D geometry is created. This step also takes into account if there is any information relevant to a multi-layer target design, for example, the relative shifts between different layers. This feature enables multi-layer target design. In stage 250, the final geometry of the designed target is visualized. As will be explained in greater detail below, not only the final design is visualized, but as the designer applies various steps of the lithography process, the designer can visualize how the 3D geometry is being formed and changed because of process-induced effects. For example, the 3D geometry after resist patterning may be different from the 3D geometry after resist removal and etching. Other steps, though not shown in the flowchart, may include, but are not limited to, visualization of the target design, run-time estimation plots, model parameters, layouts or target renderings, resist profiles, simulated responses on a metrology tool, etc.

[0042] The semiconductor industry continues to drive computing forward by increasing the computing power of IC chips and therefore, also the density of devices in the chips. The high density is achieved by a multilayered architecture made possible with complex lithographic processes. As the complexity of the architecture increases, so does the requirement for overlay and registration control. Overlay refers to the lateral displacement of a lithographically exposed and developed pattern in one layer with respect to a previously created underlying structure in another layer, and overlay metrology refers to the measurement of the lateral displacement between patterns on stacked layers. The measurement and control of the overlay between subsequent lithography steps is one of the critical steps in high volume semiconductor manufacturing. Currently, the overlay in high-end manufacturing is of the order of 1-2 nm and the precision of overlay metrology is of the order of 0.1 -0.2 nm. Existing state of overlay metrology relies on multi- wavelength diffraction-based overlay (DBO) techniques such as micro-DBO (pDBO), for example.

[0043] An overlay target used in pDBO metrology may include small overlapping gratings in a resist layer and an underlying layer. Such stacked gratings form a cell, and there may be multiple cells in a target. In pDBO metrology, the overlay is calculated by diffraction of incident light (e.g., havingsingle or multiple wavelengths) on an overlay target. The target includes a top and a bottom grating having the same grating period (pitch). In each cell, the top grating is intentionally shifted (biased), by a known offset, with respect to the bottom grating. An overlay error between these stacked gratings changes the intensities of the +1 and -1 diffraction order, which may be used to determine the stack overlay error. This technique is also referred to as intensity-based overlay metrology.

[0044] The robustness of multi-wavelength p DBG) metrology technique against process effects that induce grating asymmetries may be further improved by adding multiple known biases (intentional shift between the top and bottom grating pitches) in the metrology target. Such metrology targets are referred to as continuous-bias diffraction-based overlay (cDBO) targets, in which the multiple biases have an effect of having a different bias value along the grating length. While in the pDBG) targets, the diffraction of the incident light results in a uniform intensity pattern carrying the overlay information, for cDBO, the intensity pattern is oscillatory (e.g., a fringe pattern) and the overlay information is carried in the phase of the pattern. Such a phase-based overlay technique offers better robustness compared to intensity-based metrology, and may further reduce the need for multiple wavelengths.

[0045] Fig. 3A shows a schematic layout of an exemplary cDBO target 300, consistent with embodiments of the present disclosure. cDBO target 300 may include gratings 310-1 and 310-2 forming the top gratings, and gratings 320-1 and 320-2 forming the bottom gratings. It is to be appreciated that while exemplary cDBO target 300 is shown to have two gratings forming the top gratings and two gratings forming the bottom gratings, it may have any suitable number of top and bottom gratings. Top grating 310-1 may comprise features or structures having a pitch PTi, top grating 310-2 may comprise features having a pitch PT2 different from pitch PTi, bottom grating 320- 1 may comprise features having a pitch PBi, and bottom grating 320-2 may comprise features having a pitch PB2.

[0046] As illustrated in Fig. 3A, cDBO target 300 may include one or more pads, each pad comprising a pair of superimposed gratings having different grating pitches. For example, cDBO target 300 may include a first pad Pl comprising top grating 310-1 placed vertically above bottom grating 320-1, and a second pad P2 adjacent the first pad Pl and comprising top grating 310-2 placed vertically above bottom grating 320-2. The pads (e.g., Pl and P2) of a cDBO target, as shown in Fig. 3A, may be identified as an “M” pad or as a “W” pad, based on the configuration and the placement of the gratings. As an example, first pad Pl, in which the pitch PTi of top grating 310-1 is greater than pitch PBi of bottom grating 320-1 (PTi>PBi), may be identified as an “M” pad, and second pad P2, in which the pitch PT2 of top grating 310-2 is smaller than pitch PB2 of bottom grating 320-2 (PT2<PB2), may be identified as a “W” pad.

[0047] Reference is now made to Figs. 3B and 3C, which illustrate the first order diffraction of a pDBG) target and a cDBO target, respectively, consistent with embodiments of the disclosure. Fig. 3B shows a pDBG) target 350 which includes a top grating and a bottom grating of substantially equalgrating pitches. For overlay error measurement, a positive or a negative bias may be applied to the bottom or the top grating to induce a small but an intentional shift between the relative positions of the features in the top and the bottom gratings. The light diffracted from both bottom and top gratings interferes and results in a uniform intensity pattern. With a cDBO target 300, as shown in Fig. 3C, the diffraction directions are no longer equal, resulting in a fringe pattern with a period that depends on the difference between the grating pitches of the top and the bottom gratings. With cDBO targets, overlay information may be derived by adding the “M” and “W” phases, and overlay sensitivity for cDBO target may be derived based on the fringe contrast determined by the amplitude of the fringe M and average amplitude (A).

[0048] As discussed herein, cDBO targets offer enhanced robustness against variation or process- induced perturbations over the existing image-based overlay targets or intensity-based pDBO overlay targets. In addition to superior robustness in comparison with pDBO overlay targets, overlay information derived from cDBO target metrology includes a frequency component, which enables better signal resolution for low signal layers (e.g., low diffraction efficiency targets). The frequency of the signal carrying the overlay information may be further tuned to enhance resolution by adjusting target characteristics such as, but not limited to, grating pitches, pitch combinations, target dimensions, etc. One or more characteristics of cDBO targets (e.g., cDBO target 300) may be optimized using a target optimization simulation package or a software program.

[0049] Simulating performance of a one-dimensional cDBO target is challenging and more timeconsuming than simulating performance of a pDBO target. For a 2D-cDBO target, performance simulation of the target design is even more time-consuming and more complex compared to onedimensional cDBO target due to the increased number of harmonics caused by an unequal pitch of the top and bottom gratings along x and y directions. Because the performance simulation of 2D-cDBO targets is so time-consuming, users (target design engineers) are often forced to simulate the performance of only a limited number of metrology target designs with fixed features including, top / bottom grating pitch combinations, contact hole dimensions, target dimensions, swing curve simulations, etc. to evaluate target performance. Existing target design optimization approaches using software programs or simulation packages limit the number of 2D-cDBO target designs that can be evaluated, or limit the combinations of characteristics that can be implemented in a target design, among other drawbacks. A direct consequence of this limitation is that the optimum metrology target design for a product or a process may be missed or overlooked, potentially impacting the yield, throughput, or both. Therefore, there exists a need for simulation methods and systems to evaluate 2D-cDBO target designs by simulating performance of multiple 2D-cDBO target designs in a timeefficient manner to enable selection of the optimal target design for overlay metrology.

[0050] Embodiments of the present disclosure provide systems and methods for evaluating 2D- cDBO metrology target designs by approximating performance metrics of 2D-cDBO metrology targets based on performance simulation of reduced dimensional target designs. Reference is nowmade to Fig. 4, which illustrates a process flowchart for an exemplary method 400 for optimizing a metrology target associated with a lithography process, consistent with embodiments of the present disclosure. Method 400 may include steps performed to evaluate 2D-cDBO overlay metrology target designs by using lower dimensional approximate features. In some embodiments, the illustrated method 400 may be altered to modify the order of steps and to include additional or fewer steps.

[0051] Step 410 includes decomposing a two-dimensional metrology target into one or more reduced-dimension metrology targets. In some embodiments, the two-dimensional metrology target may be a 2D-cDBO metrology target. As discussed earlier, a cDBO metrology target consists of multiple pads or unit cells, each unit cell comprising a pair of vertically stacked gratings. Generally, each unit cell of a cDBO metrology target includes a top grating and a bottom grating. A grating, as used herein, refers to a plurality of structures or features arranged with a predetermined periodicity in lateral or longitudinal direction (x-direction or y-direction). In a cDBO metrology target, the pitch of the top grating is different from the pitch of the bottom grating. In a 2D-cDBO metrology target, however, the gratings include structures in a two-dimensional grid pattern (x-direction and y- direction). An exemplary arrangement of top and bottom gratings in a 2D-cDBO metrology target (discussed with reference to Fig. 5).

[0052] A reduced-dimension metrology target, as used herein, refers to a metrology target derived from a two-dimensional metrology target, such as a 2D-cDBO metrology target. The reduced- dimension metrology target may include a one-dimensional metrology target (e.g., a ID-cDBO metrology target), a two-dimensional metrology target with reduced geometry (e.g., a hybrid metrology target discussed later with reference to Fig. 6), or any metrology target derived from the two-dimensional metrology target and having reduced number of harmonics.

[0053] In some embodiments, decomposing a two-dimensional metrology target may comprise forming two one-dimensional metrology targets in the x-direction and y-direction, respectively, from the two-dimensional metrology target. As an example, a 2D-cDBO metrology target may be decomposed as a ID-cDBO x-direction metrology target (e.g., ID-cDBO metrology target 510 of Fig. 5) and a ID-cDBO y-direction metrology target (e.g., ID-cDBO y-direction metrology target 520 of Fig. 5). In some embodiments, a 2D-cDBO metrology target may be geometrically decomposed as a superimposition of two ID-cDBO metrology targets.

[0054] In some embodiments, decomposing a two-dimensional metrology target may comprise reducing the two-dimensional metrology target as a hybrid metrology target with reduced two- dimensional geometry. An example of a hybrid metrology target is illustrated in Fig. 7 (e.g., hybrid metrology target 720, discussed later). A hybrid metrology target may comprise a two-dimensional geometry in which the first and the second gratings have a substantially similar pitch in a non-overlay direction. The non-overlay direction may be one of x-direction or y-direction. It is to be appreciated that the gratings may be interchangeably referred to as first and second, or top and bottom, or a pair of vertically stacked gratings. A two-dimensional hybrid metrology target (e.g., hybrid metrology target720) may be further reduced by selecting a representative unit cell from multiple unit cells. The representative unit cell (e.g., unit cell 730 of Fig. 7) comprises an array of top and bottom gratings having a substantially similar pitch in the non-overlay direction (e.g., y-direction for unit cell 730) and different pitches in the overlay direction (e.g., x-direction for unit cell 730).

[0055] Step 420 includes simulating a performance of the one or more reduced-dimension metrology targets. In some embodiments, simulating a performance may include simulating dark-field diffraction images of the reduced-dimension metrology targets, such as the ID-cDBO targets in the x- and y- directions. The simulated dark-field diffraction images may be processed, using an image processing system, to compute performance characteristics corresponding with the reduced-dimension metrology target. In some embodiments, performance characteristics may include, but are not limited to, stack sensitivity (SS), diffraction efficiency (DE), or overlay error (OVL). Simulation of performance of reduced-dimension metrology targets such as ID-cDBO metrology targets can be used to predict, by approximation for example, performance characteristics of 2D-cDBO metrology targets. The simulation time for ID-cDBO metrology targets or reduced dimension metrology targets is significantly less than the simulation time for 2D-cDBO metrology targets and the performance simulation results are accurate, allowing faster and a more exhaustive evaluation of 2D-cDBO metrology targets.

[0056] Step 430 includes optimizing the two-dimensional metrology target based on the simulated performance of the one or more reduced-dimension metrology targets. In some embodiments, optimizing the 2D-cDBO target comprises approximating performance characteristics of the 2D- cDBO target based on the simulated dark-field diffraction image of the 2D-cDBO target.

[0057] Reference is now made to Fig. 5, which illustrates an exemplary 2D-cDBO metrology target decomposed as two ID-cDBO metrology targes, consistent with embodiments of the present disclosure. 2D-cDBO metrology target 550 may comprise top gratings and bottom gratings arranged in a two-dimensional array. It is to be appreciated that in this disclosure, the top and the bottom gratings may be interchangeably referred to as first and second gratings as well. In Fig. 5, the top gratings or the first gratings of 2D-cDBO metrology target 550 are indicated by the darker contrast square array and the bottom gratings or the second gratings are indicated by the lighter contrast square array. In 2D-cDBO metrology target 550, a pitch of the top gratings in the x-direction and in the y- direction is different from a pitch of the bottom gratings in the x-direction and in the y-direction. The difference in pitches between the top and the bottom gratings in two dimensions gives the 2D-cDBO metrology target 550 the effect of having a continuous bias (intentional shift between top and bottom gratings).

[0058] As previously discussed, simulating performance characteristics of 2D-cDBO metrology target 550 is a time-consuming process. The proposed method for optimizing 2D-cDBO metrology targets includes reducing the dimensions by decomposing 2D-cDBO metrology targets (e.g., 2D- cDBO metrology target 550) as two reduced-dimension metrology targets (e.g., ID-cDBO metrologytargets 510 and 520). The reduced-dimension metrology targets, derived from 2D-cDBO metrology targets, provide a good approximation of the performance characteristics of higher dimensional targets. The accuracy and speed of performance simulation of reduced-dimension metrology targets allows prediction of performance characteristics of 2D-cDBO metrology targets in a time-efficient manner. In some embodiments, performance characteristics, as used herein, may refer to key performance indicators (KPI) which include, but are not limited to, overlay stack sensitivity, diffraction efficiency, overlay error, etc.

[0059] In some embodiments, 2D-cDBO metrology target 550 may be geometrically decomposed into ID-cDBO metrology target 510 in the x-direction and ID-cDBO metrology target 520 in the y- direction. The geometrical decomposition of 2D-cDBO metrology target 550 as a superimposition of ID-cDBO metrology targets 510 and 520 allows prediction of performance characteristics of a 2D- cDBO metrology target based on simulated performance characteristics of the individual onedimensional targets.

[0060] Simulating a 2D-cDBO metrology target performance includes decomposing the 2D-cDBO metrology target into two ID-cDBO metrology targets, simulating dark-field diffraction images of diffraction patterns arising from the gratings of the two ID-cDBO metrology targets, processing the simulated dark-field diffraction images, and computing overlay information associated with the 2D- cDBO metrology target based on the processed dark-field diffraction images of the ID-cDBO metrology targets. Fig. 6 illustrates exemplary dark-field diffraction images of reduced-dimension metrology targets and a superimposed dark-field diffraction image of ID-cDBO metrology target, consistent with embodiments of present disclosure. Image 610 represents a dark-field image of diffraction pattern corresponding to ID-cDBO metrology target 510 and image 620 represents a darkfield image of diffraction pattern corresponding to ID-cDBO metrology target 520.

[0061] In some embodiments, dark-field diffraction images 610 and 620 corresponding to ID-cDBO metrology targets 510 and 520, respectively, may be simulated using a computer-implemented method such as a software program. Because of the reduction in dimensionality, the simulation time for dark-field diffraction images 610 and 620 is significantly less compared to the simulation time for a simulated dark-field diffraction image of a 2D-cDBO metrology target (e.g., simulated dark-field diffraction image 640).

[0062] Fig. 6 illustrates a reconstructed dark-field diffraction image 630 of two superimposed 1D- cDBO metrology targets in x- and y- directions. The reconstructed dark-field diffraction image 630 may be generated, via image processing means, by mathematically adding simulated dark-field diffraction images 610 and 620 of ID-cDBO metrology targets formed by decomposing a 2D-cDBO metrology target (e.g., 2D-cDBO metrology target 550 of Fig. 5). Qualitatively, reconstructed darkfield diffraction image 630 of a ID-cDBO metrology target in x- and y- directions and a simulated dark-field diffraction image 640 of a 2D-cDBO metrology target are substantially similar, indicating ahigher accuracy in predictability of performance characteristics of a 2D-cDBO metrology target based on simulation of performance characteristics of constituent ID-cDBO metrology targets.

[0063] In some embodiments, a 2D-cDBO metrology target may be optimized based on simulation of performance characteristics of a corresponding hybrid metrology target comprising reduced 2D geometry. Fig. 7 illustrates an exemplary hybrid metrology target, consistent with embodiments of the present disclosure.

[0064] An exemplary 2D-cDBO metrology target 710 comprises a two-dimensional array of top and bottom gratings. It is to be appreciated that although the top and bottom gratings are represented in a 5x5 array, the array size is not limited as such. 2D-cDBO metrology target 710 comprises top gratings (represented by lighter contrast features) and bottom gratings (represented by darker contrast features) having different pitches in the x- and y- directions.

[0065] In some embodiments, 2D-cDBO metrology target 710 may be decomposed as a hybrid metrology target 720. As used herein, hybrid metrology target 720 refers to a reduced two- dimensional geometry metrology target formed by decomposing 2D-cDBO metrology target 710. In some embodiments, hybrid metrology target 720 may be formed by taking a substantially similar pitch of the top and bottom gratings in a non-overlay direction. In this context, substantially similar refers to a higher degree of similarity of a given dimension, shape, or size, between the compared features. Specifically, substantially similar pitches of top and bottom gratings is understood to mean that the difference in the pitches of the top and bottom gratings is negligible or + 2%. As used herein, a non-overlay direction refers to the direction other than the direction in which an overlay is being measured. As an example, in hybrid metrology target 720 the non-overlay direction is the y-direction and the overlay direction is the x-direction. Exemplary hybrid metrology target 720 may be configured to determine overlay in the x-direction, rendering the y-direction as the non-overlay direction. Hybrid metrology target 720 comprises a varying degree of overlap between the top and bottom gratings in the x-direction and a constant overlap between the top and bottom gratings in the y-direction. In other words, the overlay direction is the direction in which the bias is induced.

[0066] In some embodiments, hybrid metrology target 720 in which the overlay direction is the x- direction, may comprise multiple rows of biased (shifted in the x-direction) top and bottom gratings. As an example, hybrid metrology target 720 comprises five substantially similar rows of biased top and bottom gratings. In some embodiments, hybrid metrology target 720 may be further reduced to a unit cell 730 of biased top and bottom gratings. Unit cell 730 may comprise a representative array of biased top and bottom gratings. In some embodiments, unit cell 730 may comprise a further reduced two-dimensional hybrid metrology target. A computer-implemented system or a software program may be used to predict performance characteristics of 2D-cDBO metrology targets based on simulation of performance characteristics of unit cell 730. It is to be appreciated that although not illustrated, a hybrid metrology target and a unit cell in which the non-overlay direction is the x- direction is also possible.

[0067] Generally, the simulation time increases with an increase in expected accuracy of prediction from a simulation based on known parameters. Simulation of performance characteristics of a 2D- cDBO metrology target is time consuming. This is because the simulation is required to solve, using a multi-dimensional solver, a large number of boundary conditions in both dimensions i.e., x- and y- directions. In some embodiments, to mitigate this issue of excessive time-consumption for simulating performance characteristics of a 2D-cDBO metrology target, the number of harmonics may be reduced by reducing the accuracy of the solver in the non-overlay direction, while preserving the accuracy in the overlay direction. Because the performance characteristics of a 2D-cDBO metrology target can be approximated, with good accuracy, based on simulated performance characteristics of reduced-dimensional metrology targets (e.g., ID-cDBO metrology targets of Fig. 5 or reduced two- dimensional geometry of Fig. 7), it may be beneficial to reduce the number of harmonics for simulation purposes, by reducing the accuracy expectation from the solver in the non-overlay direction.

[0068] Fig. 8 illustrates a block diagram of an example apparatus 800 for processing image data, consistent with embodiments of the present disclosure. In some embodiments, the simulated darkfield diffraction images may be processed using at least one apparatus 800. For example, apparatus 800 may be a preprocessor or an image processor. As shown in Fig. 8, apparatus 800 may include processor 802. When processor 802 executes instructions described herein, apparatus 800 can become a specialized machine for processing data, preprocessing, encoding, or decoding image data. Processor 802 can be any type of circuitry capable of manipulating or processing information. For example, processor 802 can include any combination of any number of a central processing unit (or “CPU”), a graphics processing unit (or “GPU”), a neural processing unit (“NPU”), a microcontroller unit (“MCU”), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PL A), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), or the like. In some embodiments, processor 802 can also be a set of processors grouped as a single logical component. For example, as shown in Fig. 8, processor 802 may include multiple processors, including processor 802a, processor 802b, and processor 802n.

[0069] Apparatus 800 may further include memory 804 configured to store data (e.g., a set of instructions, computer codes, intermediate data, or the like). For example, as shown in Fig. 8, the stored data may include program instructions (e.g., program instructions for implementing one or more steps in method 400) and data for processing (e.g., metrology data, model data, statistical analysis data, or the like). Processor 802 may access the program instructions and data for processing via bus 810), and execute the program instructions to perform an operation or manipulation on the data for processing. Memory 804 can include a high-speed random-access storage device or a non-volatile storage device. In some embodiments, memory 804 may include any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or the like. Memory 804 can also be a group of memories (not shown) grouped as a single logical component.

[0070] Bus 810 may be a communication device that transfers data between components inside apparatus 800, such as an internal bus (e.g., a CPU-memory bus), an external bus (e.g., a universal serial bus port, a peripheral component interconnect express port), or the like.

[0071] For ease of explanation without causing ambiguity, processor 802 and other data processing circuits are collectively referred to as a “data processing circuit” in this disclosure. The data processing circuit can be implemented entirely as hardware, or as a combination of software, hardware, or firmware. In addition, the data processing circuit can be a single independent module or can be combined entirely or partially into any other component of apparatus 800.

[0072] Apparatus 800 may further include network interface 806 to provide wired or wireless communication with a network (e.g., the Internet, an intranet, a local area network, a mobile communications network, or the like). In some embodiments, network interface 806 can include any combination of any number of a network interface controller (NIC), a radio frequency (RF) module, a transponder, a transceiver, a modem, a router, a gateway, a wired network adapter, a wireless network adapter, a Bluetooth adapter, an infrared adapter, a near-field communication (“NFC”) adapter, a cellular network chip, or the like.

[0073] In some embodiments, optionally, apparatus 800 may further include peripheral interface 808 to provide a connection to one or more peripheral devices. As shown in Fig. 8, the peripheral device can include, but is not limited to, a cursor control device (e.g., a mouse, a touchpad, or a touchscreen), a keyboard, a display (e.g., a cathode-ray tube display, a liquid crystal display, or a light-emitting diode display), a video input device (e.g., a camera or an input interface coupled to a video archive), or the like.

[0074] A non-transitory computer readable medium may be provided that stores instructions for one or more processors (e.g., processor 802) of a controller to carry out, among other things, image generating, image processing, simulation by executing algorithms, computing, and at least some steps of method 400. Common forms of non-transitory media include, for example, a floppy disk, a flexible disk, hard disk, solid state drive, magnetic tape, or any other magnetic data storage medium, a Compact Disc Read Only Memory (CD-ROM), any other optical data storage medium, any physical medium with patterns of holes, a Random Access Memory (RAM), a Programmable Read Only Memory (PROM), and Erasable Programmable Read Only Memory (EPROM), a FLASH-EPROM or any other flash memory, Non-Volatile Random Access Memory (NVRAM), a cache, a register, any other memory chip or cartridge, and networked versions of the same.

[0075] Although specific reference may be made in this text to the use of the embodiments in the manufacture of ICs, it should be explicitly understood that the embodiments have many other possible applications. For example, it may be employed in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid-crystal display panels, thin-film magnetic heads, etc. The skilled artisan will appreciate that, in the context of such alternative applications, any use of the terms “reticle,” “wafer” or “field” in this text should be considered as interchangeable with the more general terms “mask,” “substrate” and “target portion,” respectively.

[0076] Block diagrams in the figures may illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer hardware or software products according to various exemplary embodiments of the present disclosure. In this regard, each block in a schematic diagram may represent certain arithmetical or logical operation processing that may be implemented using hardware such as an electronic circuit. Blocks may also represent a module, segment, or portion of code that comprises one or more executable instructions for implementing the specified logical functions. It should be understood that in some alternative implementations, functions indicated in a block may occur out of the order noted in the figures. For example, two blocks shown in succession may be executed or implemented substantially concurrently, or two blocks may sometimes be executed in reverse order, depending upon the functionality involved. Some blocks may also be omitted. It should also be understood that each block of the block diagrams, and combination of the blocks, may be implemented by special purpose hardware -based systems that perform the specified functions or acts, or by combinations of special purpose hardware and computer instructions.

[0077] The embodiments of the present disclosure may further be described using the following clauses:1. A method for optimizing a two-dimensional metrology target, the method comprising: decomposing a two-dimensional metrology target associated with a lithography process into one or more reduced-dimension metrology targets; simulating a performance of the one or more reduced-dimension metrology targets; and optimizing the two-dimensional metrology target based on the simulated performance of the one or more reduced-dimension metrology targets.2. The method of clause 1 , wherein the two-dimensional metrology target comprises a two- dimensional continuous-bias diffraction-based overlay (2D-cDBO) target.3. The method of clause 2, wherein decomposing comprises reducing the 2D-cDBO target as two one-dimensional continuous-bias diffraction-based overlay (ID-cDBO) targets in an x-direction and a y-direction, respectively.4. The method of clause 3, comprising simulating a performance of the two ID-cDBO targets, wherein simulating the performance comprises simulating dark-field diffraction images of the ID-cDBO targets in the x-direction and the y-direction.5. The method of clause 4, wherein simulating the performance further comprises computing information associated with overlay including stack sensitivity (SS), diffraction efficiency (DE), or overlay error (OVL) from the simulated dark-field diffraction images of the ID-cDBO targets in the x- and y-directions.6. The method of clause 5, further comprising simulating a dark-field diffraction image of the 2D-cDBO target by performing a mathematical summation of the simulated dark-field diffraction images of the ID-cDBO targets in the x- and y-directions.7. The method of clause 6, wherein optimizing the 2D-cDBO target comprises approximating performance characteristics of the 2D-cDBO target based on the simulated dark-field diffraction image of the 2D-cDBO target.8. The method of clause 2, wherein decomposing comprises reducing the 2D-cDBO target as a hybrid metrology target, the hybrid metrology target comprising a reduced two- dimensional geometry.9. The method of clause 8, wherein the hybrid metrology target comprises top and bottom gratings having a substantially similar pitch in a non-overlay direction, and wherein the non-overlay direction is one of an x-direction or a y-direction.10. The method of any one of clauses 8-9, further comprising simulating a performance of the hybrid metrology target, wherein simulating the performance comprises simulating a dark-field diffraction image of the hybrid metrology target.11. The method of clause 10, wherein simulating the performance of the hybrid metrology target comprises computing information associated with overlay including stack sensitivity (SS), diffraction efficiency (DE), or overlay error (OVL) from the simulated dark-field diffraction image of the hybrid metrology target.12. The method of clause 11, wherein optimizing the 2D-cDBO target comprises approximating characteristics of the 2D-cDBO target based on the simulated dark-field diffraction image of the hybrid metrology target.13. The method of any one of clauses 8-12, wherein the reduced two-dimensional geometry of the hybrid metrology target comprises a reduced number of harmonics in comparison with the 2D-cDBO target.14. The method of any one of clauses 2-13, wherein the 2D-cDBO target comprises a first plurality of gratings and a second plurality of gratings configured to be superimposed on the first plurality of gratings, and wherein a pitch of the first plurality of gratings is different from a pitch of the second plurality of gratings.15. A computer program product comprising a non-transitory computer-readable medium having a set of instructions stored thereon, the instructions when executed by at least one processor of an apparatus are configured to cause the processor to perform a method for optimizing a two-dimensional metrology target, the method comprising: decomposing a two-dimensional metrology target associated with a lithography process into one or more reduced-dimension metrology targets; simulating a performance of the one or more reduced-dimension metrology targets; and optimizing the two-dimensional metrology target based on the simulated performance of the one or more reduced-dimension metrology targets.

[0078] It will be appreciated that the embodiments of the present disclosure are not limited to the exact construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. The present disclosure has been described in connection with various embodiments, other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Claims

CLAIMS1. A method for optimizing a two-dimensional metrology target, the method comprising: decomposing a two-dimensional metrology target associated with a lithography process into one or more reduced-dimension metrology targets; simulating a performance of the one or more reduced-dimension metrology targets; and optimizing the two-dimensional metrology target based on the simulated performance of the one or more reduced-dimension metrology targets.

2. The method of claim 1 , wherein the two-dimensional metrology target comprises a two- dimensional continuous-bias diffraction-based overlay (2D-cDBO) target.

3. The method of claim 2, wherein decomposing comprises reducing the 2D-cDBO target as two one-dimensional continuous-bias diffraction-based overlay (ID-cDBO) targets in an x-direction and a y-direction, respectively.

4. The method of claim 3, comprising simulating a performance of the two ID-cDBO targets, wherein simulating the performance comprises simulating dark-field diffraction images of the 1D- cDBO targets in the x-direction and the y-direction.

5. The method of claim 4, wherein simulating the performance further comprises computing information associated with overlay including stack sensitivity (SS), diffraction efficiency (DE), or overlay error (OVL) from the simulated dark-field diffraction images of the ID-cDBO targets in the x- and y-directions.

6. The method of claim 5, further comprising simulating a dark-field diffraction image of the 2D-cDBO target by performing a mathematical summation of the simulated dark-field diffraction images of the ID-cDBO targets in the x- and y-directions.

7. The method of claim 6, wherein optimizing the 2D-cDBO target comprises approximating performance characteristics of the 2D-cDBO target based on the simulated dark-field diffraction image of the 2D-cDBO target.

8. The method of claim 2, wherein decomposing comprises reducing the 2D-cDBO target as a hybrid metrology target, the hybrid metrology target comprising a reduced two-dimensional geometry.

9. The method of claim 8, wherein the hybrid metrology target comprises top and bottom gratings having a substantially similar pitch in a non-overlay direction, and wherein the non-overlay direction is one of an x-direction or a y-direction.

10. The method of any one of claims 8-9, further comprising simulating a performance of the hybrid metrology target, wherein simulating the performance comprises simulating a dark-field diffraction image of the hybrid metrology target.

11. The method of claim 10, wherein simulating the performance of the hybrid metrology target comprises computing information associated with overlay including stack sensitivity (SS), diffraction efficiency (DE), or overlay error (OVL) from the simulated dark-field diffraction image of the hybrid metrology target.

12. The method of claim 11, wherein optimizing the 2D-cDBO target comprises approximating characteristics of the 2D-cDBO target based on the simulated dark-field diffraction image of the hybrid metrology target.

13. The method of any one of claims 8-12, wherein the reduced two-dimensional geometry of the hybrid metrology target comprises a reduced number of harmonics in comparison with the 2D-cDBO target.

14. The method of any one of claims 2-13, wherein the 2D-cDBO target comprises a first plurality of gratings and a second plurality of gratings configured to be superimposed on the first plurality of gratings, and wherein a pitch of the first plurality of gratings is different from a pitch of the second plurality of gratings.

15. A computer program product comprising a non-transitory computer-readable medium having a set of instructions stored thereon, the instructions when executed by at least one processor of an apparatus are configured to cause the processor to perform a method for optimizing a two- dimensional metrology target, the method comprising: decomposing a two-dimensional metrology target associated with a lithography process into one or more reduced-dimension metrology targets; simulating a performance of the one or more reduced-dimension metrology targets; and optimizing the two-dimensional metrology target based on the simulated performance of the one or more reduced-dimension metrology targets.

Images