Semiconductor device and method for fabricating semiconductor device

Abstract

The present invention provides a semiconductor device having a transistor with high field-effect mobility. The semiconductor device has a semiconductor layer, a first conductive layer, and a first insulating layer. The first insulating layer is located on the semiconductor layer. The first conductive layer has a region overlapping the semiconductor layer with the first insulating layer interposed therebetween. The semiconductor layer contains crystalline indium oxide. The semiconductor layer is between 1 nm and 10 nm thick, inclusive. The semiconductor layer contains crystal grains. The grain size of the crystal grains is 0.3 μm or larger. The semiconductor layer preferably has a first region and a second region that do not overlap the first conductive layer. Preferably, the first region and the second region each contain a first element. The first element is preferably one or more of hydrogen, boron, and phosphorus.

Description

Semiconductor device and method for manufacturing the same

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a display device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a transistor and a manufacturing method thereof.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, there has been a demand for high-definition display devices. Devices requiring high-definition display devices, such as devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR), have been actively developed.

[0005] Examples of display devices include display devices having liquid crystal elements and display devices having light-emitting elements (also referred to as light-emitting devices). Examples of light-emitting elements include organic electroluminescence (EL) elements and light-emitting diodes (LEDs). Patent Document 1 discloses a high-definition display device using organic EL elements.

[0006] Technologies related to transistors using semiconductor thin films have been attracting attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention.

[0007] Examples of oxide semiconductors that can be used in transistors include indium oxide, indium gallium zinc oxide, etc. Non-Patent Document 1 discloses a thin film transistor using hydrogenated polycrystalline indium oxide formed by low-temperature solid phase crystallization.

[0008] International Publication No. 2016 / 038508

[0009] Y. Magari et al., "High-mobility hydrogenated polycrystalline InO(InO:H) thin-film transistors", Nature Communications, 13, 1078 (2022) Takashi Koida, "High-mobility transparent conductive film", National Research and Development Agency, National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf> John Y. W. Seto, “The electrical properties of polycrystalline silicon films”, Journal of Applied Physics, 1975, volume 46, No. 12, p. 5247-5254

[0010] An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high field-effect mobility. Another object is to provide a semiconductor device including a transistor with high on-state current. Another object is to provide a semiconductor device including a micro-sized transistor. Another object is to provide a semiconductor device including a transistor with a short channel length. Another object is to provide a semiconductor device including a transistor with favorable electrical characteristics. Another object is to provide a semiconductor device that operates at high speed. Another object is to provide a semiconductor device with a small occupation area. Another object is to provide a semiconductor device with low wiring resistance. Another object is to provide a semiconductor device or display device with low power consumption. Another object is to provide a highly reliable transistor, semiconductor device, or display device. Another object is to provide a high-resolution display device. Another object is to provide a manufacturing method of the above-described transistor, semiconductor device, or display device. Another object is to provide a manufacturing method of a highly productive transistor, semiconductor device, or display device. Another object is to provide a novel transistor, semiconductor device, or display device, or a manufacturing method thereof.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention is a semiconductor device including a semiconductor layer, a first conductive layer, and a first insulating layer. The first insulating layer is located over the semiconductor layer. The first conductive layer has a region overlapping with the semiconductor layer with the first insulating layer interposed therebetween. The semiconductor layer includes crystalline indium oxide. The thickness of the semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The semiconductor layer includes crystal grains. The grain size of the crystal grains is greater than or equal to 0.3 μm.

[0013] The aforementioned semiconductor device preferably includes a second conductive layer and a third conductive layer. The semiconductor layer preferably includes a first region and a second region that do not overlap with the first conductive layer. The first region and the second region preferably each include a first element. The first element is preferably one or more of hydrogen, boron, and phosphorus. The second conductive layer preferably includes a region that contacts the first region. The third conductive layer preferably includes a region that contacts the second region.

[0014] One embodiment of the present invention is a semiconductor device including a transistor and a first insulating layer. The transistor includes a semiconductor layer, a first conductive layer, and a second conductive layer. The first insulating layer is located over the first conductive layer. The second conductive layer is located over the first insulating layer. The first insulating layer and the second conductive layer have openings reaching the first conductive layer. The semiconductor layer has a region in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer. The semiconductor layer includes crystalline indium oxide. The thickness of the semiconductor layer is 1 nm to 10 nm. The semiconductor layer includes crystal grains. The grain size of the crystal grains is 0.3 μm or more.

[0015] The aforementioned semiconductor device preferably includes a second insulating layer. The second insulating layer preferably has a region in contact with the lower surface of the first conductive layer. The first insulating layer preferably includes a third insulating layer and a fourth insulating layer on the third insulating layer. The second insulating layer preferably includes silicon, nitrogen, and hydrogen. The third insulating layer preferably includes silicon and nitrogen. The fourth insulating layer preferably includes silicon and oxygen. The second insulating layer preferably includes a region having a higher hydrogen content than the third insulating layer.

[0016] One embodiment of the present invention is a method for manufacturing a semiconductor device, in which an indium oxide layer is formed, heat treatment is performed to increase the crystallinity of the indium oxide layer to form a semiconductor layer, a gate insulating layer is formed over the semiconductor layer, and a gate electrode is formed over the gate insulating layer. The heat treatment temperature is from 400° C. to 670° C.

[0017] In the above-described method for manufacturing a semiconductor device, the indium oxide layer is preferably formed by a sputtering method using oxygen gas, hydrogen gas, and argon gas.

[0018] In the above-described method for manufacturing a semiconductor device, a first element is preferably supplied to the semiconductor layer using the gate electrode as a mask, and the first element is preferably one or more of hydrogen, boron, and phosphorus.

[0019] One embodiment of the present invention is a method for manufacturing a semiconductor device, comprising: forming a first conductive layer; depositing a first insulating film over the first conductive layer; forming a second conductive layer over the first insulating film, the second conductive layer having a first opening in a region overlapping with the first conductive layer; removing the region of the first insulating film overlapping with the first opening; forming the first insulating layer having a second opening reaching the first conductive layer; forming an indium oxide layer in contact with a top surface of the first conductive layer, side surfaces of the first insulating layer, and top surfaces and side surfaces of the second conductive layer; increasing the crystallinity of the indium oxide layer by heat treatment to form a semiconductor layer; forming a gate insulating layer over the semiconductor layer; and forming a gate electrode over the gate insulating layer. The heat treatment is performed at a temperature of 400° C. to 670° C.

[0020] In the above-described method for manufacturing a semiconductor device, the indium oxide layer is preferably formed by a sputtering method using oxygen gas, hydrogen gas, and argon gas.

[0021] According to one embodiment of the present invention, a semiconductor device including a transistor with high field-effect mobility can be provided. Alternatively, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a micro-sized transistor can be provided. Alternatively, a semiconductor device including a transistor with a short channel length can be provided. Alternatively, a semiconductor device including a transistor with favorable electrical characteristics can be provided. Alternatively, a semiconductor device that operates at high speed can be provided. Alternatively, a semiconductor device with a small occupation area can be provided. Alternatively, a semiconductor device with low wiring resistance can be provided. Alternatively, a semiconductor device or display device with low power consumption can be provided. Alternatively, a highly reliable transistor, semiconductor device, or display device can be provided. Alternatively, a high-resolution display device can be provided. Alternatively, a manufacturing method for the above-described transistor, semiconductor device, or display device can be provided. Alternatively, a manufacturing method for a highly productive transistor, semiconductor device, or display device can be provided. Alternatively, a novel transistor, semiconductor device, or display device, or a manufacturing method thereof can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0023] FIG. 1A is a top view showing an example of a semiconductor device. FIGS. 1B and 1C are cross-sectional views showing an example of a semiconductor device. FIG. 2A is a top view showing an example of a semiconductor device. FIGS. 2B and 2C are cross-sectional views showing an example of a semiconductor device. FIGS. 3A and 3B are cross-sectional views showing an example of a semiconductor device. FIGS. 4A to 4D are cross-sectional views showing an example of a semiconductor device. FIG. 5A is a top view showing an example of a semiconductor device. FIG. 5B is a cross-sectional view showing an example of a semiconductor device. FIG. 6A is a top view showing an example of a semiconductor device. FIGS. 6B and 6C are cross-sectional views showing an example of a semiconductor device. FIGS. 7A to 7D are perspective views showing an example of a semiconductor device. FIGS. 8A and 8B are cross-sectional views showing an example of a semiconductor device. FIG. 9A is a top view showing an example of a semiconductor device. FIG. 9B is a cross-sectional view showing an example of a semiconductor device. FIGS. 10A and 10B are cross-sectional views showing an example of a semiconductor device. FIG. 11A is a top view showing an example of a semiconductor device. FIGS. 11B and 11C are cross-sectional views showing an example of a semiconductor device. FIGS. 12A and 12B are cross-sectional views showing an example of a semiconductor device. FIG. 13A is a top view illustrating an example of a semiconductor device. FIGS. 13B and 13C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 14A and 14B are cross-sectional views illustrating an example of a semiconductor device. FIG. 15A is a top view illustrating an example of a semiconductor device. FIG. 15B is a cross-sectional view illustrating an example of a semiconductor device. FIG. 16A is a top view illustrating an example of a semiconductor device. FIG. 16B is a cross-sectional view illustrating an example of a semiconductor device. FIGS. 17A to 17F are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 18A to 18E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 19A to 19E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 20A to 20D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 21A to 21C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 22A and 22B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 23A and 23B are diagrams illustrating carrier concentration dependence of hole mobility. FIG. 23C is a cross-sectional view illustrating an indium oxide film. FIG. 24 is a perspective view showing an example of a display device.25A and 25B are cross-sectional views showing an example of a display device. FIG. 26 is a cross-sectional view showing an example of a display device. FIG. 27 is a cross-sectional view showing an example of a display device. FIG. 28 is a cross-sectional view showing an example of a display device. FIG. 29 is a cross-sectional view showing an example of a display device. FIGS. 30A to 30C are cross-sectional views showing an example of a display device. FIGS. 31A and 31B are cross-sectional views showing an example of a display device. FIG. 32 is a cross-sectional view showing an example of a display device. FIG. 33 is a cross-sectional view showing an example of a display device. FIG. 34 is a cross-sectional view showing an example of a display device. FIG. 35 is a cross-sectional view showing an example of a display device. FIGS. 36A to 36D are views showing an example of an electronic device. FIGS. 37A to 37F are views showing an example of an electronic device. FIGS. 38A to 38G are views showing an example of an electronic device. FIGS. 39A and 39B are views showing Id-Vg characteristics of transistors according to examples. FIGS. 40A and 40B are views showing Id-Vg characteristics of transistors according to examples. FIGS. 41A to 41C are views showing electrical characteristics of transistors according to examples. FIG. 42 is a diagram showing the reliability of a transistor according to an example. FIG. 43 is a diagram showing the reliability of a transistor according to an example. FIG. 44 is a diagram showing the reliability of a transistor according to an example. FIG. 45A is a cross-sectional STEM image of a transistor according to an example. FIGS. 45B and 45C are cross-sectional TEM images of a transistor according to an example. FIGS. 46A and 46B are diagrams showing the Id-Vg characteristics of a transistor according to an example. FIGS. 47A and 47B are diagrams showing the Id-Vg characteristics of a transistor according to an example. FIGS. 48A to 48D are TDS spectra according to an example. FIG. 49 is a diagram showing the Id-Vg characteristics of a transistor according to an example. FIG. 50 is an SEM image of an indium oxide film according to an example. FIGS. 51A and 51B are diagrams showing KFM measurement results according to an example. FIGS. 52A and 52B are diagrams showing KFM measurement results according to an example. FIG. 53 is a diagram showing Hall effect measurement results according to an example. 54A and 54B are diagrams showing Hall effect measurement results according to an example. Figures 55A and 55B are diagrams showing Id-Vg characteristics of a transistor according to an example.56A and 56B are diagrams showing electrical characteristics of a transistor according to an example. FIG. 57 is a diagram showing electrical characteristics of a transistor according to an example. FIGS. 58A to 58C are diagrams showing Id-Vg characteristics of a transistor according to an example. FIGS. 59A to 59C are diagrams showing Id-Vd characteristics of a transistor according to an example. FIG. 60 is a diagram showing reliability of a transistor according to an example. FIG. 61A is a diagram showing Id-Vg characteristics of a transistor according to an example. FIG. 61B is a diagram showing SCM measurement results according to an example. FIG. 62A is a diagram showing Id-Vg characteristics of a transistor according to an example. FIG. 62B is a diagram showing electrical characteristics of a transistor according to an example.

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0026] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0027] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between the components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0028] In this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", or "[m, n]" may be added to the reference numeral. Furthermore, when explaining matters common to multiple elements to which an identification numeral is added, or when it is not necessary to distinguish between them, the elements may be described without the identification numeral.

[0029] The words "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0030] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0031] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. The source and drain of a transistor may be appropriately referred to as the source terminal and drain terminal, or the source electrode and drain electrode, depending on the situation.

[0032] The terms "gate" and "back gate" can be used interchangeably. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0033] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A and B represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0034] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0035] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0036] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0037] In this specification, unless otherwise specified, the on-state current refers to the drain current (also referred to as Id) when a transistor is in an on state (also referred to as a conductive state). Unless otherwise specified, the on state refers to a state in which the voltage between the gate and the source (also referred to as gate voltage, Vg or Vgs) is equal to or higher than a threshold voltage (also referred to as Vth) for an n-channel transistor, or a state in which the voltage is equal to or lower than the threshold voltage for a p-channel transistor.

[0038] In this specification and the like, unless otherwise specified, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and the source is lower than the threshold voltage in an n-channel transistor, and higher than the threshold voltage in a p-channel transistor.

[0039] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0040] In this specification, the top surface shape of a component refers to the contour shape of the component as viewed from above (also referred to as a plan view). The top surface view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0041] In this specification, the phrase "top surface shapes that match or approximately match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes that match or approximately match" may also be used. Furthermore, when the top surface shapes match or approximately match, it can also be said that "edges match or approximately match" or "edges are aligned or approximately aligned."

[0042] In this specification, a tapered shape refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface or a surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes referred to as a taper angle.

[0043] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0044] In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer is physically separated from the adjacent metal oxide layer.

[0045] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Because devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of resolution due to the alignment accuracy of the metal mask. Furthermore, devices with an MML structure can eliminate the need for equipment for manufacturing metal masks and a metal mask cleaning process. Furthermore, devices with an MML structure are suitable for mass production because they can keep manufacturing costs low.

[0046] In this specification and the like, a structure in which light-emitting layers are separately formed for light-emitting elements (light-emitting devices) with different emission wavelengths may be referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, thereby expanding the range of material and configuration options and facilitating improvements in brightness and reliability.

[0047] In this specification and the like, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0048] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes (a first electrode and a second electrode). The light-emitting element has a first electrode, an EL layer on the first electrode, and a second electrode on the EL layer. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer functioning as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the first electrode and the second electrode may be referred to as a pixel electrode, and the other may be referred to as a common electrode.

[0049] In this specification and the like, flexibility refers to the property of an object being soft and bendable, i.e., the property of an object being able to deform in response to an external force applied to the object, regardless of whether or not the object has elasticity or the ability to return to its original shape before deformation.

[0050] For example, a flexible electronic device can deform in response to an external force. A flexible electronic device can be used while fixed in a deformed state, or can be used after repeatedly deforming. A flexible display device (also referred to as a flexible display device, flexible display device, flexible display, etc.) can deform in response to an external force. A flexible display device can be used while fixed in a deformed state, or can be used after repeatedly deforming, or can be used in an undeformed state. A flexible battery (also referred to as a flexible battery, flexible battery, flexible battery, etc.) can deform in response to an external force. A flexible battery can be used while fixed in a deformed state, or can be used after repeatedly deforming, or can be used in an undeformed state. A flexible substrate (also referred to as a flexible substrate, flexible substrate, etc.) can deform in response to an external force. A flexible substrate can be used while fixed in a deformed state, or can be used after repeatedly deforming, or can be used in an undeformed state. Note that the above phrase "deform in response to an external force" refers to deformation by an average adult's hand without requiring excessive force. Flexibility can be evaluated using a testing machine capable of performing stress-strain measurements (such as a tensile testing machine or a compression testing machine). In stress-strain measurements, an external force is applied to an object, and the strain of the object caused by the resulting stress is measured, thereby making it possible to quantify the flexibility of the object.

[0051] In this specification, when an object is described as having flexibility, it means that at least a part of the object has flexibility. In other words, a flexible object may have a non-flexible part (also called a hard part).

[0052] In this specification, when two objects are deformed by the same external force, the object that deforms more is said to be the object with higher flexibility. Also, when a first part and a second part of an object are deformed by the same external force, the part that deforms more is said to be the part with higher flexibility.

[0053] 1A to 22B , a semiconductor device according to one embodiment of the present invention can be suitably used for, for example, one or both of a pixel circuit and a driver circuit of a display device.

[0054] 1A shows a top view (also referred to as a plan view) of a semiconductor device 10 according to one embodiment of the present invention. FIG. 1B shows a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 1A, and FIG. 1C shows a cross-sectional view of a cut surface taken along dashed dotted line B1-B2 in FIG.

[0055] The semiconductor device 10 includes a transistor 100. The transistor 100 includes an insulating layer 105 over a substrate 102, a semiconductor layer 108 over the insulating layer 105, an insulating layer 106 over the semiconductor layer 108, and a conductive layer 104 over the insulating layer 106. The conductive layer 104 has a region facing the semiconductor layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 104 functions as a gate electrode of the transistor 100, and the insulating layer 106 functions as a gate insulating layer. An insulating layer 195 is provided over the conductive layer 104 and the insulating layer 106.

[0056] The semiconductor layer 108 has a region 108P and a region 108Q that do not overlap with the conductive layer 104. In the transistor 100, the region 108P functions as one of the source region and the drain region, and the region 108Q functions as the other of the source region and the drain region. In the semiconductor layer 108, a region that is located between the source region and the drain region and overlaps with the conductive layer 104 with the insulating layer 106 interposed therebetween functions as a channel formation region.

[0057] The semiconductor layer 108 preferably includes a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. A transistor using an oxide semiconductor (hereinafter also referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device. When an oxide semiconductor is used for the semiconductor layer, the semiconductor layer can be referred to as an oxide semiconductor layer or a metal oxide layer.

[0058] The metal oxide preferably contains at least indium. For example, indium oxide (IO) can be suitably used for the semiconductor layer 108. Note that a transistor using indium oxide for the semiconductor layer 108 may be referred to as an IO transistor.

[0059] By increasing the thickness T108 of the channel formation region of the semiconductor layer 108, the on-state current of the transistor can be increased. However, if the thickness T108 is too thick, oxygen vacancies (V Ｏ ), and defects in which hydrogen enters oxygen vacancies (hereinafter referred to as V Ｏ The amount of V (also written as VH) increases. ＯH functions as a donor and may generate electrons as carriers. This may cause the transistor to have normally-on characteristics. Furthermore, reliability may be reduced. The thickness T108 is preferably 1 nm to 50 nm, more preferably 1 nm to 40 nm, even more preferably 1 nm to 30 nm, even more preferably 1 nm to 20 nm, and even more preferably 1 nm to 10 nm. By setting the thickness T108 within the above range, a transistor with good electrical characteristics and high reliability can be obtained. The thickness T108 can be the shortest distance between the surface where the semiconductor layer 108 is to be formed (here, the top surface of the insulating layer 105) and the top surface of the semiconductor layer 108 in a cross-sectional view. In FIG. 1B , the thickness T108 is indicated by a solid arrow. Note that the thickness T108 is not limited to the above range.

[0060] The crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0061] The semiconductor layer 108 preferably has crystallinity. Using a crystalline oxide semiconductor for the semiconductor layer 108 is preferable because it can suppress deterioration of transistor characteristics. The semiconductor layer 108 preferably has high crystallinity, and is preferably polycrystalline or single-crystalline. A polycrystalline indium oxide film is preferably used as the semiconductor layer 108, and a single-crystalline indium oxide film is more preferably used. Note that indium oxide having crystal grains may be referred to as crystalline indium oxide (Crystal IO) or crystalline indium oxide (Crystalline IO).

[0062] A single-crystal film is particularly preferable because it does not have grain boundaries, thereby suppressing carrier scattering at grain boundaries and enabling a transistor with high field-effect mobility. Compared to microcrystalline films and amorphous films, a polycrystalline film can reduce carrier scattering, enabling a transistor with high field-effect mobility. When a polycrystalline film is used for the semiconductor layer 108, the grain size of the crystal grains contained in the semiconductor layer 108 is preferably large. Using a polycrystalline film with large grain sizes can reduce the number of grain boundaries located in the channel formation region and shorten the length of the grain boundaries located in the channel formation region, resulting in a transistor with high field-effect mobility. Furthermore, it is preferable that the number of grain boundaries intersecting the drain current flow direction (also referred to as the channel length direction) in the channel formation region is small. Even a polycrystalline film can achieve the same effects as a single-crystal film if no grain boundaries are located in the channel formation region.

[0063] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film.Furthermore, a semiconductor layer in which the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation within one crystal grain in the channel formation region can be called a single crystal film.

[0064] When a non-single-crystal (e.g., polycrystalline) film is used as the semiconductor layer 108, it is preferable that the barrier height at the grain boundary is low. A low barrier height at the grain boundary reduces the influence of grain boundary scattering, resulting in a transistor with high field-effect mobility. Generally, the barrier height at the grain boundary of low-temperature polysilicon (LTPS) is 60 meV to 80 meV. When polycrystalline indium oxide is used for the semiconductor layer 108, it is preferable that the barrier height at the grain boundary is lower than the barrier height at the grain boundary of LTPS. For example, the barrier height at the grain boundary of indium oxide is preferably less than 60 meV, more preferably 55 meV or less, and even more preferably 50 meV or less. Since a low barrier height at the grain boundary is preferable, no lower limit is set. The barrier height at the grain boundaries of indium oxide is not limited to the above range.

[0065] The barrier height at the grain boundary can be measured using, for example, Kelvin Probe Force Microscopy (KFM). KFM is a type of measurement mode in Scanning Probe Microscopy (SPM), in which a sample surface is scanned with a conductive probe and the electrostatic force between the probe and the sample surface is detected, thereby enabling the distribution of potential on the sample surface to be evaluated. Measuring the same location multiple times increases the signal-to-noise ratio (SNR), thereby improving measurement accuracy.

[0066] The semiconductor layer 108 can be formed by depositing a metal oxide film to be the semiconductor layer 108 and processing the metal oxide film into an island shape. The metal oxide film can be deposited by sputtering, atomic layer deposition (ALD), or chemical vapor deposition (CVD). After depositing the metal oxide film or processing the metal oxide film into an island shape, heat treatment is preferably performed to crystallize the metal oxide film. The heat treatment can increase the grain size of crystal grains contained in the semiconductor layer 108 and improve the crystallinity of the semiconductor layer 108. Furthermore, the heat treatment can reduce defects in the semiconductor layer 108. Furthermore, the heat treatment can remove impurities (e.g., hydrogen and water) contained in the semiconductor layer 108 or adsorbed on the surface of the semiconductor layer 108.

[0067] It is preferable to form a metal oxide film under conditions that result in low crystallinity of the metal oxide film. After forming a metal oxide film with low crystallinity, heat treatment is performed to crystallize the film, thereby increasing the grain size of the crystal grains. When forming the metal oxide film, a gas containing hydrogen element (e.g., H ２ or H ２ It is preferable to use hydrogen gas and argon gas as the deposition gas for the metal oxide film. This can reduce the number of crystal grains generated during deposition of the metal oxide film, thereby making it possible to obtain a metal oxide film with low crystallinity. For example, hydrogen gas and argon gas can be suitably used as the deposition gas for the metal oxide film.

[0068] By using oxygen gas as the deposition gas for the metal oxide film, oxygen deficiency (V Ｏ ) can be suppressed. In addition, by using oxygen gas as the deposition gas for the metal oxide film, the amount of oxygen contained in the metal oxide film can be increased, which can promote crystallization in the subsequent heat treatment. For example, oxygen gas and argon gas can be suitably used as the deposition gas for the metal oxide film.

[0069] It is preferable to use hydrogen gas and oxygen gas as a deposition gas for the metal oxide film. A mixture of hydrogen gas, oxygen gas, and argon gas can be used as a deposition gas for the metal oxide film. This allows the semiconductor layer 108 to have large crystal grains and few defects.

[0070] It is preferable that the substrate temperature is low when forming the metal oxide film. For example, it is preferable that the metal oxide film is formed without heating the substrate. This can reduce the number of crystal grains generated during the formation of the metal oxide film, resulting in a metal oxide film with low crystallinity.

[0071] The temperature of heat treatment after forming the metal oxide film or after processing the metal oxide film into an island shape is preferably high. Increasing the temperature of heat treatment can increase the crystallinity of the semiconductor layer 108. Here, low-crystallinity regions (e.g., amorphous regions) may exist between crystal grains in the semiconductor layer 108. In particular, if low-crystallinity regions exist in the channel formation region, carrier scattering may reduce the field-effect mobility of the transistor. Increasing the temperature of heat treatment can increase the grain size of the crystal grains and reduce the low-crystallinity regions between the crystal grains. This allows for a transistor with high field-effect mobility. Increasing the temperature of heat treatment can also increase the grain size of the crystal grains in the semiconductor layer 108. Increasing the temperature of heat treatment can further reduce defects in the semiconductor layer 108. Furthermore, impurities (e.g., hydrogen and water) contained in or adsorbed on the surface of the semiconductor layer 108 can be efficiently removed by heat treatment. Alternatively, impurities contained in the semiconductor layer 108 (for example, one or more of impurities caused by hydrogen gas, impurities caused by oxygen gas, and impurities caused by argon gas used as deposition gases) can be efficiently removed by heat treatment.

[0072] The temperature of the heat treatment is preferably 100° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 670° C. or lower, even more preferably 300° C. or higher and 670° C. or lower, even more preferably 350° C. or higher and 670° C. or lower, even more preferably 400° C. or higher and 670° C. or lower, and even more preferably 450° C. or higher and 670° C. or lower. In the heat treatment, the temperature of the substrate is preferably within the above-mentioned temperature range. Note that the temperature of the substrate in the heat treatment is not limited to the above-mentioned range.

[0073] The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA) can be used. The heat treatment is preferably performed in an atmosphere containing oxygen. By performing the heat treatment in an oxygen-containing atmosphere, the effects of reducing defects and increasing the grain size of crystal grains may be enhanced. CDA can be suitably used as the atmosphere for the heat treatment. It is preferable that the content of hydrogen, water, and the like in the atmosphere be as low as possible. It is preferable to use a high-purity gas with a dew point of −60° C. or less, preferably −100° C. or less, as the atmosphere. By using an atmosphere with as low a content of hydrogen, water, and the like as possible, it is possible to prevent hydrogen, water, and the like from being taken into the semiconductor layer 108 as much as possible.

[0074] The heating apparatus used for the heating treatment is not particularly limited, and may be, for example, an apparatus that heats by thermal conduction or thermal radiation from a heating element. For example, an oven or a rapid thermal annealing (RTA) apparatus may be used for the heating treatment. An LRTA (Lamp RTA) apparatus, which heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp, may be used as the RTA apparatus. Examples of such lamps include a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, and a high-pressure mercury lamp. Alternatively, a GRTA (Gas RTA) apparatus, which heats the workpiece using high-temperature gas, may be used as the RTA apparatus. The use of an RTA apparatus can shorten the heating treatment time. The treatment time is preferably 1 minute to 10 minutes, more preferably 3 minutes to 10 minutes, and even more preferably 5 minutes to 10 minutes. When a short heat treatment time is performed using an RTA apparatus, the heat treatment temperature can be set to a temperature equal to or higher than the strain point of the substrate, thereby further shortening the heat treatment time. Typically, a GRTA apparatus can be used, performing heat treatment at 650° C. for 6 minutes.

[0075] The grain size of the crystal grains contained in the semiconductor layer 108 is preferably 0.1 μm or more, more preferably 0.2 μm or more, even more preferably 0.3 μm or more, even more preferably 0.4 μm or more, even more preferably 0.5 μm or more, even more preferably 0.6 μm or more, and even more preferably 0.7 μm or more. Since a large grain size of the crystal grains is preferable, no upper limit is particularly set for the grain size. Note that the grain size of the crystal grains is not limited to the above-mentioned range.

[0076] The crystallinity of the semiconductor layer 108 can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis can be performed by combining a plurality of these techniques.

[0077] The grain size of the crystal grains contained in the semiconductor layer 108 can be analyzed by, for example, a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), or an electron backscatter diffraction pattern (EBSD or EBSP). Alternatively, the analysis can be performed by combining a plurality of these techniques. For example, the average value of the grain sizes of a plurality of crystal grains can be used as the grain size. Furthermore, the grain size of a crystal grain can be, for example, the diameter of a circle having the same area as the area of ​​the crystal grain. Note that this diameter is sometimes referred to as the circle equivalent diameter.

[0078] In this specification, the term "grain boundary" refers to, for example, a boundary between adjacent crystal grains with different crystal orientations. Therefore, in this specification, the term "grain boundary" does not include a boundary between adjacent crystal grains with the same crystal orientation. For example, even if a boundary is observed between two crystal grains in a TEM image, if the crystal orientations of the two crystal grains are identical or approximately identical, the boundary may not be called a grain boundary. Furthermore, in EBSD, if the difference in crystal orientation between adjacent measurement points is small (for example, if the difference in crystal orientation is less than 5 degrees), these measurement points can be considered to belong to the same crystal grain.

[0079] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). In addition, space group numbers in the International Tables for Crystallography Volume A (hereinafter also referred to as ITA) may be assigned. Crystal planes and crystal directions are also expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal directions are expressed with a bar above the number. However, due to formatting restrictions, in this specification, instead of a bar above the number, a minus sign (-) may be placed before the number. Individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent directions with < >, individual planes indicating crystal planes with ( ), and collective planes with equivalent symmetry with {}. Even if the space group number is the same, the space group notation may differ depending on how the crystal axes are arranged.

[0080] In addition, cubic In ２ O ３ The crystal structure of belongs to space group Ia-3 (space group number 206).

[0081] The grain size of the crystal grains can also be confirmed by, for example, an optical microscope or a scanning electron microscope (SEM). Furthermore, by creating unevenness on the surface of the semiconductor layer 108 using an etchant whose etching rate varies depending on the crystal plane or crystallinity, the crystal grains can be easily observed even with an optical microscope or a scanning electron microscope (SEM). When an indium oxide film is used as the semiconductor layer 108, the crystal grains of the indium oxide can be easily observed by using an etchant containing an acid. As the acid, for example, one or more of phosphoric acid, oxalic acid, nitric acid, and hydrochloric acid can be used. Note that if the etching rate is too fast, part of the semiconductor layer 108 may be lost, making it difficult to observe the crystal grains. Therefore, it is preferable to adjust the etching rate by adjusting the concentration, temperature, and treatment time of the etchant so that the semiconductor layer 108 is thinned without being lost (also referred to as half etching). By performing half etching, the crystal grains can be easily observed.

[0082] If the thickness T108 is small, it may not be possible to evaluate the crystallinity and grain size of the semiconductor layer 108.

[0083] The impurity concentration in the channel formation region is preferably low. The channel formation region is preferably highly pure. In the channel formation region, impurities can act as a carrier scattering source, which can reduce the field-effect mobility. Furthermore, impurities can also hinder crystal growth.

[0084] Impurities in an indium oxide film include gallium, zinc, boron, aluminum, and silicon. In the channel formation region, the concentration of each of these impurities is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less. Examples of elements that can be contained in an indium oxide film include carbon and hydrogen. Carbon and hydrogen are elements that can be contained in a film-forming gas (e.g., a precursor) for an indium oxide film, and may exist in the indium oxide film in greater amounts than the aforementioned impurities. Note that ppm is an abbreviation for "parts per million," and 1 ppm is 1×10 −６ is.

[0085] The concentration of impurities in the semiconductor layer 108 can be analyzed by, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectrometry (XPS). Note that XPS is sometimes called Electron Spectrometry for Chemical Analysis (ESCA). When XPS analysis is used, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front or back side of the sample with XPS analysis. Note that in a low concentration region, quantification may be difficult or the concentration may be below the detection limit.

[0086] The concentrations of gallium, zinc, boron, aluminum, and silicon in the channel formation region are each 1×10 ２０ atoms / cm ３ Preferably, it is less than 5×10 １９ atoms / cm ３ Preferably, it is less than 3×10 １９ atoms / cm ３ Preferably, it is equal to or less than 1×10 １９ atoms / cm ３ Preferably, it is less than 3×10 １８ atoms / cm ３ Preferably, it is equal to or less than 1×10 １８ atoms / cm ３ The following is preferred:

[0087] By using an indium oxide film with large crystal grains and a low impurity concentration in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, even 100 cm ２ / (V·s) or more, and even 150 cm ２ / (V s) or more, even 200 cm ２ / (V s) or more, and even 250 cm ２ / (V·s) or more.

[0088] As described above, by using indium oxide for the semiconductor layer, a transistor with high on-state current can be obtained. Therefore, a semiconductor device that operates at high speed can be provided. When the semiconductor device of one embodiment of the present invention is applied to a display device, the display device can operate at high speed and have high display quality. Furthermore, a transistor using indium oxide for the semiconductor layer has high field-effect mobility, and thus can obtain a large on-state current even when the channel width is small. Therefore, the area occupied by the transistor can be reduced, and the area occupied by the semiconductor device can be reduced. When the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit (e.g., one or both of a gate line driver circuit and a source line driver circuit) of a display device, the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame.

[0089] In the semiconductor layer 108, the length of a region that is located between the source region and the drain region and that overlaps with the conductive layer 104 via the insulating layer 106 is the channel length L of the transistor 100. In Figures 1A and 1B, the channel length L is indicated by a dashed double-headed arrow. The width of the region where the semiconductor layer 108 and the conductive layer 104 overlap in a direction perpendicular to the channel length direction is the channel width W of the transistor 100. In Figures 1A and 1C, the channel width W is indicated by a solid double-headed arrow.

[0090] The transistor 100 is a so-called top-gate transistor having a gate electrode above the semiconductor layer 108. By supplying impurities to the semiconductor layer 108 using the conductive layer 104 functioning as the gate electrode as a mask, regions 108P and 108Q functioning as source and drain regions can be formed in a self-aligned manner. The transistor 100 can be referred to as a TGSA (Top Gate Self-Aligned) transistor.

[0091] The regions 108P and 108Q contain impurities. Supplying impurities to the semiconductor layer 108 can reduce the electrical resistance of the regions 108P and 108Q. The impurity concentrations in the regions 108P and 108Q are higher than the impurity concentration in the channel formation region. The elements contained in the impurities (hereinafter also referred to as first elements) can be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of hydrogen, boron, phosphorus, aluminum, magnesium, and silicon as the first element.

[0092] Ion implantation can be suitably used to supply impurities. Ion implantation can control the concentration profile in the depth direction with high precision by adjusting the ion acceleration energy and dose. Furthermore, by using an ion implantation method in which a source gas is ionized and the ions are mass-separated before supply, ions of a specific mass can be supplied, thereby increasing the purity of the supplied impurities. Alternatively, by using an ion implantation method in which ions are supplied without mass separation, productivity can be increased. Unless otherwise specified in this specification, the presence or absence of mass separation is not limited. Note that a method in which ions are mass-separated before supplying them is sometimes called an ion implantation method, and a method in which ions are supplied without mass separation is sometimes called an ion doping method.

[0093] When an element that easily bonds with oxygen is used as the first element, the first element removes oxygen from the semiconductor layer 108 and exists in a state of being bonded to oxygen. Ｏ) occurs. When an element that becomes stable when bonded with oxygen is used as the first element, the first element in the semiconductor layer 108 exists stably in an oxidized state and is therefore unlikely to be desorbed by heat or the like applied during the manufacturing process of the semiconductor device, and the electrical resistance of the regions 108P and 108Q can be kept low. For this reason, it is preferable to use an element whose oxide can exist in a solid state at least at the temperature during the manufacturing process as the first element. One or both of boron and phosphorus can be suitably used as the first element.

[0094] When boron is used as the first element, the boron contained in the regions 108P and 108Q can exist in a state of being bonded to oxygen. ２ O ３ In XPS analysis, peaks due to the presence of elemental boron may not be observed or may have extremely low peak intensities, such as background intensity.

[0095] The supply of hydrogen causes oxygen vacancies (V Ｏ ) occurs, and oxygen deficiency (V Ｏ ) by entering V Ｏ The generation of H can effectively reduce the electrical resistance of the regions 108P and 108Q. Therefore, hydrogen can be suitably used as the first element.

[0096] In supplying the impurity, it is preferable to adjust the supply conditions so that the impurity concentration is highest on the surface of the semiconductor layer 108 or in a region close to the surface.

[0097] The source material used to supply the impurity may be, for example, a gas containing the first element. When boron is supplied, a typical example is B ２ H ６ Gas, or BF ３ In addition, when phosphorus is supplied, one or more of the following gases can be used: PH ３ Furthermore, gases obtained by diluting these source gases with noble gases can also be used.

[0098] As a raw material used for supplying impurities, for example, CH ４ , N ２ , N.H. ３ , AlH ３ , AlCl ３ , SiH ４ , Si ２ H ６ , F ２ , H.F., H. ２ , (C ５ H ５ ) ２ Mg and noble gases can be used. Note that the raw material is not limited to gas, and a solid or liquid can also be heated and vaporized for use.

[0099] The supply of impurities can be controlled by setting conditions such as acceleration voltage and dose amount in consideration of the composition, density, thickness, and the like of the insulating layer 106 and the semiconductor layer 108. Note that when the impurities are supplied to the semiconductor layer 108 through the insulating layer 106 using the conductive layer 104 as a mask, the region of the insulating layer 106 that does not overlap with the conductive layer 104 may also contain the impurities when the impurities are supplied to the region. In addition, the region of the insulating layer 105 that does not overlap with the conductive layer 104 may also contain the impurities when the impurities are supplied to the region.

[0100] For example, when boron is supplied by ion implantation, the acceleration voltage can be set to, for example, 5 kV or more and 100 kV or less, preferably 7 kV or more and 70 kV or less, and more preferably 10 kV or more and 50 kV or less. １３ ions / cm ２ 1x10 or more １７ ions / cm ２ Below 1 × 10, preferably １４ ions / cm ２ 5x10 or more １６ ions / cm ２ Less than 1×10, more preferably 1×10 １５ ions / cm ２ That's it, 3 x 10 １６ ions / cm ２ The range can be as follows:

[0101] When phosphorus is supplied by ion implantation, the acceleration voltage can be set to, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less, and more preferably 40 kV or more and 80 kV or less. The dose can be set to, for example, 1×10 １３ ions / cm ２ 1x10 or more １７ ions / cm ２ Below 1 × 10, preferably １４ ions / cm ２ 5x10 or more １６ ions / cm ２ Less than 1×10, more preferably 1×10 １５ ions / cm ２ 3x10 or more １６ ions / cm ２ The range can be as follows:

[0102] The method of supplying the impurities is not limited to this, and for example, plasma treatment or treatment utilizing thermal diffusion by heating can also be used. In the case of plasma treatment, the impurities can be supplied by generating plasma in a gas atmosphere containing the impurities to be supplied and performing the plasma treatment. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, etc. can be used.

[0103] For example, by using a plasma CVD apparatus to perform plasma treatment in an atmosphere containing a gas containing a hydrogen element, hydrogen can be supplied as an impurity to a region of the semiconductor layer 108 that does not overlap with the conductive layer 104. Furthermore, by using a plasma CVD apparatus to supply the impurity and form the insulating layer 195, the supply of the impurity and the formation of the insulating layer 195 can be performed successively within the apparatus, thereby improving productivity.

[0104] The insulating layer 195 and the insulating layer 106 have an opening 147a that reaches the region 108P and an opening 147b that reaches the region 108Q.

[0105] A conductive layer 112a is provided to cover the opening 147a. In the opening 147a, the conductive layer 112a is in contact with and connected to the region 108P. A conductive layer 112b is provided to cover the opening 147b. In the opening 147b, the conductive layer 112b is in contact with and connected to the region 108Q. The conductive layer 112a functions as one of the source and drain electrodes of the transistor 100, and the conductive layer 112b functions as the other of the source and drain electrodes.

[0106] An insulating layer 218 is provided over the conductive layers 112a and 112b and the insulating layer 195. The insulating layer 195 and the insulating layer 218 each function as a protective layer for the transistor 100.

[0107] In the TGSA transistor, the physical distance between the conductive layers 112 a and 112 b functioning as a source electrode and a drain electrode and the conductive layer 104 functioning as a gate electrode can be increased, and therefore, the parasitic capacitance therebetween can be reduced.

[0108] [Semiconductor Layer 108] Metal oxides that can be used for the semiconductor layer 108 will be specifically described. As described above, the metal oxide preferably contains at least indium. Indium oxide can be suitably used as the metal oxide. Alternatively, for example, gallium oxide (also referred to as gallium oxide) or zinc oxide (also referred to as zinc oxide) can be used as the metal oxide. Alternatively, the metal oxide preferably contains one or both of indium and zinc. Alternatively, the metal oxide preferably contains one or more elements selected from indium, element M, and zinc. Note that element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have a high bond energy with oxygen and an ionic radius similar to that of indium or zinc. Furthermore, tin is more preferred because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0109] The semiconductor layer 108 may be formed of, for example, indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium tungsten oxide (In—W oxide, also referred to as IWO), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide), , AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO), etc. Alternatively, indium tin oxide containing silicon (In-Sn-Si oxide, also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0110] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, the presence of a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0111] The metal oxide may contain one or more nonmetallic elements. The nonmetallic elements in the metal oxide may increase the carrier concentration or narrow the band gap, thereby increasing the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0112] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0113] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When multiple elements are contained as element M, the sum of the ratios of the number of atoms of element M to the sum of the numbers of atoms of all contained metal elements can be referred to as the content of element M.

[0114] By increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0115] By increasing the content of element M in the metal oxide, it is possible to obtain a metal oxide with a large band gap. Ｏ ) is suppressed, the formation of oxygen vacancies (V Ｏ ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage (Vg) is 0 V can be reduced, and a normally-off transistor can be obtained. In addition, a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0116] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer 108. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0117] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M Examples of suitable compositions include In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

[0118] The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, oxygen deficiency (V Ｏ ) can be suppressed.

[0119] When the element M contains a plurality of elements, the atomic ratio of the element M can be the sum of the atomic ratios of these elements.

[0120] By using a material with a high indium content for the semiconductor layer 108, the on-state current or the field-effect mobility of the transistor can be increased. Ｏ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, even more preferably 0.1% to 10%, even more preferably 0.1% to 8%, even more preferably 0.1% to 6%, and even more preferably 0.1% to 4%. This allows for a transistor with excellent electrical characteristics. For example, it is preferable to use a metal oxide having a ratio of In:M:Zn=40:1:10 or thereabouts. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, a metal oxide having a ratio of In:Sn:Zn=40:1:10 or thereabouts can be suitably used. Alternatively, a metal oxide having a ratio of In:Al:Zn=40:1:10 or thereabouts can be suitably used.

[0121] Here, when a metal oxide having a polycrystalline structure is used for the semiconductor layer 108, the unevenness of the surface of the semiconductor layer 108 may become large. As a result, the step on the surface on which a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 is formed becomes large, and defects such as discontinuities or voids may occur in the layer. When a metal oxide having a composition that easily forms a polycrystalline structure is used for the semiconductor layer 108, it is preferable to include an element that inhibits crystallization. This prevents the semiconductor layer 108 from becoming a polycrystalline structure, and a transistor with a large on-state current can be obtained. Furthermore, the coverage of a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 can be improved, and defects such as discontinuities or voids in the layer can be prevented.

[0122] For example, compared to ITO, ITSO is less likely to form a polycrystalline structure, and therefore is suitable for use in the semiconductor layer 108. When ITSO is used, the silicon content (the ratio of the number of silicon atoms to the sum of the numbers of atoms of all metal elements contained) is preferably 1% to 20%, more preferably 3% to 20%, even more preferably 3% to 15%, and even more preferably 5% to 15%. Suitable atomic ratios of metal elements include, for example, In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, and metal oxides in the vicinity thereof. When ITSO is used for the semiconductor layer 108, it is preferable that the ITSO have crystallinity. Note that the semiconductor layer 108 may have an amorphous region or may be amorphous.

[0123] A metal oxide not containing element M can be used for the semiconductor layer 108. When the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 1:2, In:Zn = 3:1, In:Zn = 3:2, In:Zn = 2:3, In:Zn = 4:1, In:Zn = 4:3, In:Zn = 5:1, In:Zn = 5:2, In:Zn = 5:3, In:Zn = 5:4, In:Zn = 5:6, In:Zn = 5:7, In:Zn = 5:8, In:Zn = 5:9, In:Zn = 7:1, In:Zn = 10:1, In:Zn = 10:3, In:Zn = 10:7, and compositions in the vicinity thereof. Furthermore, it is more preferable that the atomic ratio of In is equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0124] The composition of the semiconductor layer 108 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and identify and quantify the elements. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or element M may be below the lower detection limit.

[0125] The metal oxide film can be preferably formed by sputtering or atomic layer deposition (ALD). When a metal oxide film is formed by sputtering, the composition of the formed metal oxide film may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide film may decrease to about 50% of that in the sputtering target.

[0126] It is preferable to use a crystalline metal oxide for the semiconductor layer 108. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0127] The semiconductor layer 108 is preferably formed using a CAAC-OS or an nc-OS.

[0128] The CAAC-OS has a plurality of layered crystals. The c-axes of the crystals are oriented in the normal direction to the surface where the semiconductor layer 108 is formed. The semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the surface where the semiconductor layer 108 is formed. For example, the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the top surface of the conductive layer 112b in a region in contact with the top surface of the conductive layer 112b and layered crystals parallel or approximately parallel to the side surface of the conductive layer 112b in a region in contact with the side surface of the conductive layer 112b. In particular, the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the side surface of the insulating layer 110 where the semiconductor layer 108 is formed. With this structure, the layered crystals of the semiconductor layer 108 are formed parallel or approximately parallel to the channel length direction of the transistor 100, thereby enabling the transistor to have a large on-state current.

[0129] When a metal oxide is used for the semiconductor layer 108, V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, impurities such as water and hydrogen in the metal oxide must be removed (sometimes referred to as dehydration or dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V Ｏ It is important to repair the Ｏ By using a metal oxide in which impurities such as H are sufficiently reduced for a channel formation region, a transistor with stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0130] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0131] The semiconductor layer 108 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0132] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0133] [Insulating Layer 106, Insulating Layer 105] The insulating layer 106 and the insulating layer 105 each preferably have one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0134] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0135] The insulating layer 106 has a region in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, at least a part of the region of the insulating layer 106 in contact with the semiconductor layer 108 preferably contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 108 and the insulating layer 106. Specifically, the region of the insulating layer 106 in contact with the channel formation region preferably contains oxygen. One or more of an oxide and an oxynitride can be preferably used for the region of the insulating layer 106 in contact with the channel formation region. The same applies to the insulating layer 105. For example, the insulating layer 106 and the insulating layer 105 each preferably contain silicon and oxygen. The insulating layer 106 and the insulating layer 105 can each preferably contain silicon oxide or silicon oxynitride.

[0136] Note that in a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0137] Although the insulating layer 106 and the insulating layer 105 each have a single-layer structure in FIG. 1B and the like, one embodiment of the present invention is not limited to this. One or both of the insulating layer 106 and the insulating layer 105 can have a stacked structure of two or more layers. When the insulating layer 106 has a stacked structure, the insulating layer on the semiconductor layer 108 side preferably contains oxide or oxynitride. Similarly, when the insulating layer 105 has a stacked structure, the insulating layer on the semiconductor layer 108 side preferably contains oxide or oxynitride. The insulating layer on the semiconductor layer 108 side can be preferably made of, for example, one or more of silicon oxide, silicon oxynitride, and aluminum oxide.

[0138] It is preferable to use a material that is difficult for substances to permeate for at least one of the layers constituting the insulating layer 106. The layer can also be said to function as a barrier film. By providing a layer that functions as a barrier film, it is possible to prevent metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in layers formed on the transistor 100 from diffusing into the semiconductor layer 108 through the insulating layer 106. Furthermore, it is possible to prevent oxygen contained in the semiconductor layer 108 from diffusing into the conductive layer 104 through the insulating layer 106. This prevents oxygen deficiency (V Ｏ) can be suppressed. In addition, it is possible to suppress an increase in the electrical resistance of the conductive layer 104 due to oxidation of the conductive layer 104 by oxygen contained in the semiconductor layer 108. As a result, a transistor with good electrical characteristics and high reliability can be obtained. Similarly, it is preferable to provide a layer that functions as a barrier film in at least one of the layers that form the insulating layer 105.

[0139] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of making it difficult for a target substance to diffuse and thereby suppressing the substance from permeating the film (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering). For example, an insulating layer having barrier properties can be referred to as a barrier insulating layer.

[0140] The barrier film can be formed using, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing silicon, an oxynitride containing silicon, and a nitride oxide containing silicon. Typically, the barrier film can be formed using, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, silicon oxynitride, and silicon nitride oxide. The barrier film of the insulating layer 106 can be formed using, for example, one or more of an oxide and an oxynitride, and aluminum oxide can be preferably used. The barrier film of the insulating layer 105 can be formed using, for example, one or more of a nitride and a nitride oxide, and silicon nitride can be preferably used.

[0141] The insulating layer 106 can have, for example, a stacked structure of a silicon oxynitride film and a silicon nitride film over the silicon oxynitride film. Alternatively, the insulating layer 106 can have a stacked structure of a silicon oxynitride film and an aluminum oxide film over the silicon oxynitride film. Alternatively, the insulating layer 106 can have a stacked structure of an aluminum oxide film and a silicon oxynitride film over the aluminum oxide film. Alternatively, the insulating layer 106 can have a stacked structure of an aluminum oxide film and a silicon nitride film over the aluminum oxide film. Although an example in which the insulating layer 106 has a two-layer structure is shown here, one embodiment of the present invention is not limited to this. The insulating layer 106 can also have a stacked structure of three or more layers.

[0142] The insulating layer 105 can have, for example, a stacked-layer structure of a silicon nitride film and a silicon oxynitride film over the silicon nitride film. Although the insulating layer 105 has a two-layer stacked structure in this example, one embodiment of the present invention is not limited to this. The insulating layer 105 can also have a stacked-layer structure of three or more layers.

[0143] The configurations of the insulating layer 106 and the insulating layer 105 shown here can also be applied to other configuration examples.

[0144] [Conductive Layer 112a, Conductive Layer 112b, and Conductive Layer 104] The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each have a single-layer structure or a stacked structure of two or more layers. Materials that can be used for the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys containing one or more of the above metals. The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each be preferably made of a conductive material with low electrical resistivity, such as one or more of copper, silver, gold, and aluminum. Copper or aluminum is particularly preferred because of its excellent mass productivity.

[0145] The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each be formed using a conductive metal oxide (also referred to as an oxide conductor (OC)). Examples of oxide conductors include indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, ITSO, zinc oxide to which gallium is added, and In—Ga—Zn oxide. In particular, an oxide conductor containing indium is preferable because of its high conductivity.

[0146] When oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes electrically conductive, and the conductivity of the metal oxide increases. The metal oxide that has become electrically conductive can be called an oxide conductor.

[0147] The conductive layers 112a, 112b, and 104 can each have a stacked-layer structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0148] A nitride conductor may be used for each of the conductive layer 112a, the conductive layer 112b, and the conductive layer 104. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0149] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can also be applied to each of the conductive layer 112a, the conductive layer 112b, and the conductive layer 104. By using a Cu-X alloy film, it can be processed by wet etching, thereby reducing manufacturing costs.

[0150] Note that the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can be formed using the same material, or at least one of them can be formed using a different material.

[0151] [Insulating Layer 195] The insulating layer 195 preferably includes one or more inorganic insulating layers. The inorganic insulating layer can be formed using the materials listed for the insulating layer 106 and the insulating layer 105.

[0152] The insulating layer 195 preferably functions as a barrier film. This effectively prevents impurities (e.g., water and hydrogen) from diffusing into the transistor from the outside, thereby improving the reliability of the semiconductor device. For example, one or both of silicon nitride and silicon nitride oxide can be suitably used as the insulating layer 195. The above description can be referred to for the barrier film.

[0153] [Insulating Layer 218] The insulating layer 218 can be an inorganic insulating layer or an organic insulating layer, or both. The inorganic insulating layer can be made of the materials listed for the insulating layer 106 and the insulating layer 105. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The organic insulating layer functions as a planarization layer that reduces unevenness caused by transistors.

[0154] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it is necessary that the material have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. Alternatively, a substrate on which a semiconductor element is provided can be used as the substrate 102. Alternatively, a substrate on which an insulating film is formed on the surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited and can be, for example, circular or rectangular.

[0155] A flexible substrate can be used as the substrate 102, and the transistor 100 and the like can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistor 100 and the like. By providing the peeling layer, after a semiconductor device is partially or entirely completed thereon, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0156] The following describes a configuration example that has some configurations different from the above-described configuration example 1-1. Note that, below, descriptions of parts that overlap with configuration example 1-1 may be omitted. Also, in the drawings shown below, parts that have the same functions as the above-described configuration example 1-1 may be hatched with the same pattern and may not be assigned reference numerals.

[0157] Note that there is no particular limitation on the structure of a transistor that can be used in a semiconductor device that is one embodiment of the present invention.

[0158] 2A shows a top view of a semiconductor device 10A according to one embodiment of the present invention, FIG. 2B shows a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 2A, and FIG. 2C shows a cross-sectional view of a cut surface taken along dashed dotted line B1-B2 in FIG.

[0159] The semiconductor device 10A includes a transistor 100A. The transistor 100A differs from the transistor 100 shown in FIG.

[0160] The conductive layer 103 is provided between the substrate 102 and the insulating layer 105. The conductive layer 103 functions as a back gate electrode of the transistor 100A. The conductive layer 103 has a region overlapping with the conductive layer 104 with the insulating layer 105, the semiconductor layer 108, and the insulating layer 106 interposed therebetween. The insulating layer 105 functions as a back gate insulating layer of the transistor 100A.

[0161] By providing the back gate electrode, the potential on the back gate electrode side (also referred to as the back channel side) of the semiconductor layer 108 is fixed, and the saturation of the Id-Vd characteristics can be improved. Furthermore, by fixing the potential on the back channel side of the semiconductor layer 108, a shift in the threshold voltage can be suppressed. Therefore, a transistor with a small cutoff current can be obtained, and a semiconductor device with low power consumption can be provided.

[0162] In this specification and the like, a small change in current in the saturation region in the Id-Vd characteristics of a transistor may be expressed as "high saturation."

[0163] The conductive layer 103 preferably has a region that protrudes beyond the end portion of the conductive layer 104. This can enhance the effect of making an electric field generated outside the transistor less likely to act on the channel formation region (also referred to as an electric field shielding effect).

[0164] The conductive layer 103 can be connected to the conductive layer 112a or the conductive layer 112b. For example, an opening reaching the conductive layer 103 can be formed in the insulating layer 195, the insulating layer 106, and the insulating layer 105, and the conductive layer 112a can be provided to cover the opening, thereby making it possible to form a structure in which the conductive layer 103 and the conductive layer 112a are in contact with each other. By connecting the conductive layer 112a to the conductive layer 103, one of the source electrode and the drain electrode and the back gate electrode can have the same potential. For example, when the conductive layer 112a functions as a source electrode, a shift in the threshold voltage of the transistor 100A can be suppressed. Furthermore, the reliability of the transistor 100A can be improved.

[0165] The conductive layer 103 can be connected to the conductive layer 104. For example, openings reaching the conductive layer 103 are provided in the insulating layers 106 and 105, and the conductive layer 104 is provided to cover the openings, so that the conductive layers 103 and 104 are in contact with each other. By connecting the gate electrode and the back gate electrode, the back gate electrode and the gate electrode can have the same potential, and the on-state current of the transistor 100A can be increased.

[0166] The conductive layer 103 can be formed using the materials listed for the conductive layer 104, the conductive layer 112a, and the conductive layer 112b. Since the conductive layer 103 is formed before the semiconductor layer 108, it is preferable to use a material that can withstand heat treatment for forming the semiconductor layer 108. The conductive layer 103 is preferably formed using a high-melting-point material (for example, tungsten or molybdenum) that has both heat resistance and conductivity. For example, tungsten can be suitably used for the conductive layer 103.

[0167] The structure of the conductive layer 103 shown here can also be applied to other structure examples.

[0168] [Configuration Example 1-3] Cross-sectional views of a semiconductor device 10B according to one embodiment of the present invention are shown in Fig. 3A and Fig. 3B. For a top view of the semiconductor device 10B, see Fig. 2A. Fig. 3A is a cross-sectional view of the cut surface taken along dashed line A1-A2 in Fig. 2A, and Fig. 3B is a cross-sectional view of the cut surface taken along dashed line B1-B2.

[0169] The semiconductor device 10B includes a transistor 100B. The transistor 100B differs mainly from the transistor 100A shown in FIG. 2B and the like in that the insulating layer 105 has a stacked-layer structure.

[0170] 3A and 3B show an example in which the insulating layer 105 includes an insulating layer 105a and an insulating layer 105b on the insulating layer 105a.

[0171] The insulating layer 105b has a region in contact with the semiconductor layer 108. As described above, the insulating layer 105b in contact with the semiconductor layer 108 preferably contains oxygen.

[0172] The insulating layer 105a located on the substrate 102 and conductive layer 103 side preferably functions as a barrier film. By providing the barrier film, it is possible to prevent components (e.g., metals) contained in the substrate 102 and the conductive layer 103 from diffusing into the transistor, thereby providing a highly reliable semiconductor device. The above description of the barrier film can be referred to. The insulating layer 105a preferably contains nitrogen.

[0173] The insulating layer 105a preferably contains silicon and nitrogen, and the insulating layer 105b preferably contains silicon and oxygen. For example, silicon nitride can be preferably used for the insulating layer 105a, and silicon oxynitride can be preferably used for the insulating layer 105b.

[0174] The configuration of the insulating layer 105 shown here can also be applied to other configuration examples.

[0175] 4A and 4B show cross-sectional views of a semiconductor device 10C according to one embodiment of the present invention. For a top view of the semiconductor device 10C, see FIG. 2A. FIG. 4A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 2A, and FIG. 4B is a cross-sectional view of a cut surface taken along dashed line B1-B2 in FIG.

[0176] The semiconductor device 10C includes a transistor 100C. The transistor 100C differs from the transistor 100A shown in FIG. 2B and other figures mainly in that the edge of the insulating layer 106 coincides with or substantially coincides with the edge of the conductive layer 104.

[0177] An end portion of the insulating layer 106 is located on the semiconductor layer 108. The insulating layer 106 does not overlap with either the region 108P or the region 108Q. It can also be said that the top surface shape of the insulating layer 106 coincides with or substantially coincides with that of the conductive layer 104. The insulating layer 106 can be formed, for example, by processing using a resist mask for processing the conductive layer 104.

[0178] The insulating layer 195 has regions in contact with the top surface and side surface of the semiconductor layer 108, the side surface of the insulating layer 106, and the top surface and side surface of the conductive layer 104. The insulating layer 195 has an opening 147a that reaches the region 108P and an opening 147b that reaches the region 108Q. The conductive layers 112a and 112b are formed to cover the openings 147a and 147b. The conductive layer 112a contacts the region 108P at the opening 147a and is connected to the region 108P. The conductive layer 112b contacts the region 108Q at the opening 147b and is connected to the region 108Q.

[0179] 4C and 4D show examples of a configuration different from those shown in FIGS. 4A and 4B . FIGS. 4C and 4D are cross-sectional views of a semiconductor device 10D according to one embodiment of the present invention. For a top view of the semiconductor device 10D, refer to FIG. 2A . FIG. 4C is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 2A , and FIG. 4D is a cross-sectional view of a cut surface taken along dashed dotted line B1-B2.

[0180] The semiconductor device 10D includes a transistor 100D, which differs from the transistor 100C shown in FIG.

[0181] An end of the insulating layer 106 is located on the semiconductor layer 108, and an end of the conductive layer 104 is located on the insulating layer 106. It can also be said that the end of the insulating layer 106 is located outside the end of the conductive layer 104. The insulating layer 106 has a region that overlaps with the conductive layer 104 and a region that does not overlap with the conductive layer 104 on the semiconductor layer 108.

[0182] The semiconductor layer 108 has a channel formation region, regions 108R and 108S that sandwich the channel formation region, and regions 108P and 108Q that are located outside of the channel formation region. The regions 108R and 108S are regions of the semiconductor layer 108 that overlap with the insulating layer 106 but do not overlap with the conductive layer 104. The region 108R is located between the channel formation region and the region 108P, and the region 108S is located between the channel formation region and the region 108Q.

[0183] The regions 108R and 108S function as buffer regions for alleviating the drain electric field. The regions 108R and 108S do not overlap with the conductive layer 104, and therefore, a channel is hardly formed in the regions 108R and 108S even when a gate voltage is applied to the conductive layer 104. The regions 108R and 108S preferably have a higher carrier concentration than the channel formation region. This allows the regions 108R and 108S to function as LDD (lightly doped drain) regions.

[0184] Compared to the channel formation region, the regions 108R and 108S can also be described as regions with the same or lower electrical resistance, regions with the same or higher carrier concentration, regions with the same or higher oxygen defect density, and regions with the same or higher impurity concentration.

[0185] Compared to regions 108P and 108Q, regions 108R and 108S can also be described as regions with the same or higher electrical resistance, regions with the same or lower carrier concentration, regions with the same or lower oxygen defect density, and regions with the same or lower impurity concentration.

[0186] The insulating layer 195 has regions in contact with the top surface and side surfaces of the semiconductor layer 108 , the top surface and side surfaces of the insulating layer 106 , and the top surface and side surfaces of the conductive layer 104 .

[0187] Note that the configuration of the insulating layer 106 and the semiconductor layer 108 shown here can be applied to other configuration examples.

[0188] [Configuration Example 1-5] Fig. 5A shows a top view of a semiconductor device 10E according to one embodiment of the present invention. Fig. 5B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in Fig. 5A. For a cross-sectional view of the cut surface taken along dashed dotted line B1-B2, see Fig. 2C.

[0189] The semiconductor device 10E includes a transistor 100E. The transistor 100E differs from the transistor 100D shown in FIG. 4C and the like mainly in that the conductive layers 112a and 112b are formed in the same process as the conductive layer 104.

[0190] The insulating layer 106 has openings 147a and 147b that reach the semiconductor layer 108. Conductive layers 112a and 112b are provided so as to cover part of the openings 147a and 147b. The conductive layer 112a has a region in contact with the semiconductor layer 108 in the opening 147a, and the conductive layer 112b has a region in contact with the semiconductor layer 108 in the opening 147b.

[0191] The conductive layer 104, the conductive layer 112a, and the conductive layer 112b can be formed using the same material and in the same process. For example, an insulating film that becomes the insulating layer 106 is formed over the semiconductor layer 108 and then processed to form the insulating layer 106 having the openings 147a and 147b. Then, a conductive film that becomes the conductive layer 104, the conductive layer 112a, and the conductive layer 112b is formed so as to cover the insulating layer 106 and the openings 147a and 147b, and then processed to form the conductive layer 104, the conductive layer 112a, and the conductive layer 112b. Forming the conductive layer 112a and the conductive layer 112b in the same process as the conductive layer 104 can simplify the process.

[0192] By supplying the first element to the semiconductor layer 108 using the conductive layer 104, the conductive layer 112a, and the conductive layer 112b as masks, the regions 108P and 108Q can be formed in a self-aligned manner. The regions 108P and 108Q are formed in regions of the semiconductor layer 108 that do not overlap with any of the conductive layer 104, the conductive layer 112a, the conductive layer 112b, and the insulating layer 106. Furthermore, the regions 108R and 108S are formed in regions of the semiconductor layer 108 that do not overlap with any of the conductive layer 104, the conductive layer 112a, and the conductive layer 112b, and that overlap with the insulating layer 106.

[0193] A region of the semiconductor layer 108 in contact with the conductive layer 112a and a region 108P in contact with the conductive layer 112a function as one of a source region and a drain region. A region of the semiconductor layer 108 in contact with the conductive layer 112b and a region 108Q in contact with the conductive layer 112b function as the other of the source region and the drain region.

[0194] 5B illustrates a structure example in which the insulating layer 218 is not provided; however, one embodiment of the present invention is not limited to this. The insulating layer 218 can also be provided over the insulating layer 195.

[0195] Note that the structures of the conductive layers 112a and 112b shown here can be applied to other structure examples.

[0196] <Configuration Example 2> [Configuration Example 2-1] A top view of the semiconductor device 20 is shown in FIG. 6A. FIG. 6B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 6A, and FIG. 6C shows a cross-sectional view of the cut surface taken along dashed dotted line B1-B2. Note that some of the components of the semiconductor device 20 (such as a gate insulating layer) are omitted in FIG. 6A. As with FIG. 6A, some of the components are also omitted in the top views of the semiconductor device in the subsequent drawings. FIGS. 7A to 7D show perspective views of the semiconductor device 20. FIG. 7B shows a cross-sectional view taken along dashed dotted line C1-C2 in FIG. 7A. In FIG. 7C, the insulating layer shown in FIG. 7A is shown transparently, with its outline indicated by a dashed line. Similarly, in FIG. 7D, the insulating layer shown in FIG. 7B is shown transparently, with its outline indicated by a dashed line.

[0197] The semiconductor device 20 includes a transistor 200 and an insulating layer 110. The semiconductor device 20 is provided on an insulating surface. In Fig. 6B and other figures, the semiconductor device 20 is provided on a substrate 102 having an insulating surface. Note that an insulating film may be provided on the substrate 102, and the semiconductor device 20 may be provided on the insulating film.

[0198] The transistor 200 includes a conductive layer 204, an insulating layer 206, a semiconductor layer 208, a conductive layer 212a, and a conductive layer 212b. In the transistor 200, the conductive layer 204 functions as a gate electrode, and the insulating layer 206 functions as a gate insulating layer. The conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other. In the semiconductor layer 208, a region that overlaps with the gate electrode between the source electrode and the drain electrode via the gate insulating layer functions as a channel formation region. In the semiconductor layer 208, a region in contact with the source electrode functions as a source region, and a region in contact with the drain electrode functions as a drain region. In the semiconductor layer 208, the channel formation region is located between the source region and the drain region.

[0199] A conductive layer 212a is provided on the substrate 102, an insulating layer 110 is provided on the conductive layer 212a, and a conductive layer 212b is provided on the insulating layer 110. The insulating layer 110 is in contact with the conductive layer 212a and the conductive layer 212b and has a region sandwiched between them. The conductive layer 212a has a region overlapping with the conductive layer 212b via the insulating layer 110. The insulating layer 110 has an opening 141 that reaches the conductive layer 212a. It can also be said that the conductive layer 212a is exposed in the opening 141. The conductive layer 212b has an opening 143 in a region overlapping with the conductive layer 212a. The opening 143 is provided in a region overlapping with the opening 141. Note that in Figure 6A and other figures, the opening 141 in the insulating layer 110 and the opening 143 in the conductive layer 212b are denoted by different reference numerals, but these openings can be collectively referred to as one opening. In other words, the insulating layer 110 and the conductive layer 212b have openings that reach the conductive layer 212a.

[0200] The semiconductor layer 208 is provided to cover the openings 141 and 143. The semiconductor layer 208 has a region in contact with the top surface of the conductive layer 212a and the side surface of the insulating layer 110 in the opening 141, and a region in contact with the side surface of the conductive layer 212b in the opening 143. Furthermore, the semiconductor layer 208 preferably has a region in contact with the top surface of the conductive layer 212b. The semiconductor layer 208 has a shape that follows the shapes of the top surface and side surface of the conductive layer 212b, the side surface of the insulating layer 110, and the top surface of the conductive layer 212a.

[0201] The semiconductor layer 208 can be formed using the materials listed for the semiconductor layer 108. For the semiconductor layer 208, the description of the semiconductor layer 108 can be referred to. For the semiconductor layer 208, indium oxide can be suitably used, for example.

[0202] The insulating layer 206, which functions as a gate insulating layer of the transistor 200, is provided to cover the openings 141 and 143. The insulating layer 206 is provided over the semiconductor layer 208, the conductive layer 212b, and the insulating layer 110. The insulating layer 206 has a region in contact with the top surface and side surfaces of the semiconductor layer 208, the top surface and side surfaces of the conductive layer 212b, and the top surface of the insulating layer 110. The insulating layer 206 has a shape that follows the shapes of the top surface of the insulating layer 110, the top surface and side surfaces of the conductive layer 212b, the top surface and side surfaces of the semiconductor layer 208, and the top surface of the conductive layer 212a.

[0203] The insulating layer 206 can be formed using the materials listed for the insulating layer 106. For the insulating layer 206, the description of the insulating layer 106 can be referred to.

[0204] The conductive layer 204 functioning as a gate electrode of the transistor 200 is provided over the insulating layer 206 and has a region in contact with the top surface of the insulating layer 206. The conductive layer 204 has a region facing the semiconductor layer 208 with the insulating layer 206 interposed therebetween. The conductive layer 204 has a shape that follows the shape of the top surface of the insulating layer 206.

[0205] The conductive layer 204 can be formed using the materials listed for the conductive layer 104. For the conductive layer 204, the description of the conductive layer 104 can be referred to.

[0206] The conductive layers 212a and 212b can be formed using the materials listed for the conductive layers 112a, 112b, and 104. For the conductive layers 212a and 212b, the descriptions of the conductive layers 112a, 112b, and 104 can be referred to.

[0207] The conductive layer 212a and the conductive layer 212b each have a region in contact with the semiconductor layer 208. When an oxide semiconductor is used for the semiconductor layer 208, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer 212a or the conductive layer 212b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 212a or the conductive layer 212b and the semiconductor layer 208, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is not easily oxidized or a conductive material that maintains low electrical resistance even when oxidized for the conductive layer 212a and the conductive layer 212b. An oxide conductor can be suitably used for each of the conductive layer 212a and the conductive layer 212b. Alternatively, a nitride conductor can be used for each of the conductive layer 212a and the conductive layer 212b. The above description can be referred to for the oxide conductor and the nitride conductor.

[0208] The conductive layer 212 a and the conductive layer 212 b can be made of, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are difficult to oxidize or materials that maintain low electrical resistance even when oxidized.

[0209] When the conductive layer 212a or the conductive layer 212b has a stacked structure, it is preferable to use a conductive material that is not easily oxidized or a conductive material that maintains low electrical resistance even when oxidized, for at least a layer in contact with the semiconductor layer 208.

[0210] The conductive layers 212a and 212b are preferably formed using a material that can withstand heat treatment for forming the semiconductor layer 208 because they are formed before the semiconductor layer 208. ITO or ITSO can be preferably used for the conductive layers 212a and 212b, respectively.

[0211] The insulating layer 110 can be an inorganic insulating layer or an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The insulating layer 110 preferably has one or more inorganic insulating layers. The materials listed for the insulating layer 106 and the insulating layer 105 can be used for the inorganic insulating layer.

[0212] The insulating layer 110 has a region in contact with the semiconductor layer 208. When a metal oxide is used for the semiconductor layer 208, at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 208 preferably contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 208 and the insulating layer 110. Specifically, the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 208 preferably contains oxygen. One or more of an oxide and an oxynitride can be suitably used for the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 208.

[0213] When a metal oxide is used for the semiconductor layer 208, it is preferable that at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 208 releases oxygen when heat is applied. As a result, oxygen is supplied from the insulating layer 110 to the semiconductor layer 208, and oxygen vacancies (V Ｏ ), and V Ｏ H can be reduced.

[0214] FIG. 9B shows an enlarged view of the transistor 200 shown in FIG. 6C and its vicinity. The thickness T208 of the channel formation region of the semiconductor layer 208 is preferably within the range of the thickness T108 of the semiconductor layer 108 described above. This allows a transistor to have favorable electrical characteristics. The thickness T208 can be the shortest distance between the side surface of the insulating layer 110 and the side surface of the semiconductor layer 208 in a cross-sectional view. Specifically, the thickness T208 can be the thickness of the semiconductor layer 208 at the midpoint between the height of the top surface and the height of the bottom surface of the insulating layer 110. In FIG. 9B, the thickness T208 is indicated by a solid arrow. Note that the thickness T208 is not limited to the above-described range.

[0215] In the transistor 200, the source electrode and the drain electrode are located at different heights with respect to the surface of the substrate 102, which is a surface where the transistor 200 is formed, and a drain current flows in a direction perpendicular or approximately perpendicular to the surface of the substrate 102. It can also be said that the drain current flows vertically in the transistor 200. Therefore, the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like. The conductive layer 212a can be called a lower electrode of the transistor, and the conductive layer 212b can be called an upper electrode. Since the source electrode, the semiconductor layer, and the drain electrode can be provided in a stacked manner in the VFET, the occupied area can be significantly reduced compared to a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.

[0216] The channel length of the transistor 200 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 212a and the conductive layer 212b. Therefore, a transistor having a channel length shorter than the minimum exposure dimension of an exposure device used to manufacture the transistor can be manufactured with high precision. Furthermore, the characteristic variation among the plurality of transistors 200 is also reduced. Therefore, the operation of the semiconductor device 20 can be stabilized and the reliability can be improved. Furthermore, the reduced characteristic variation of the transistors increases the degree of freedom in circuit design, and the operating voltage of the semiconductor device can be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

[0217] By using indium oxide for the semiconductor layer 208 of the transistor 200 with a short channel length, the on-state current can be further increased. Therefore, a semiconductor device that operates at high speed can be obtained. Furthermore, because a large on-state current can be obtained even with a small channel width, the area occupied by the transistor can be further reduced. Therefore, the area occupied by the semiconductor device can be further reduced.

[0218] The conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can each function as a wiring, and the transistor 200 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 200 and a wiring, the area occupied by the transistor 200 and the wiring can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided. Furthermore, when the semiconductor device is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-resolution display device can be provided. Furthermore, for example, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be provided.

[0219] 6B and the like show an example in which the semiconductor layer 208, the insulating layer 206, and the conductive layer 204 cover the openings 141 and 143; however, one embodiment of the present invention is not limited to this. A step may be formed between the insulating layer 110, the conductive layer 212b, and the conductive layer 212a, and the semiconductor layer 208, the insulating layer 206, and the conductive layer 204 may be provided along the step.

[0220] [Insulating Layer 110] The insulating layer 110 preferably has a stacked structure. Fig. 6A and other figures show an example in which the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can each be made of the materials listed for the insulating layer 110.

[0221] A region of the semiconductor layer 208 in contact with the insulating layer 110b functions as a channel formation region. The insulating layer 110b preferably contains oxygen and is preferably made of one or more of the above-described oxides and oxynitrides. Specifically, the insulating layer 110b can be made of silicon oxide, silicon oxynitride, or both.

[0222] It is more preferable to use a material that releases oxygen when heat is applied to the insulating layer 110b. When heat is applied during the manufacturing process of the semiconductor device 20, the insulating layer 110b releases oxygen, which allows oxygen to be supplied to the semiconductor layer 208. By supplying oxygen from the insulating layer 110b to the semiconductor layer 208, particularly to the channel formation region, oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0223] For example, oxygen can be supplied to the insulating layer 110b by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 110b by forming a film on the top surface of the insulating layer 110b by a sputtering method in an oxygen-containing atmosphere. Then, the film can be removed.

[0224] The insulating layer 110b is preferably formed by a sputtering method or a PECVD method. In particular, when the insulating layer 110b is formed by a method that does not use a gas containing a hydrogen element (e.g., hydrogen gas or ammonia gas) as a deposition gas, the film can have an extremely low hydrogen content. The sputtering method is particularly suitable for forming the insulating layer 110b. This can suppress the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of the transistor 200.

[0225] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 212a. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 212b. The insulating layer 110a and the insulating layer 110c preferably release small amounts of impurities (e.g., water and hydrogen) from themselves. Furthermore, the insulating layer 110a and the insulating layer 110c preferably are impermeable to substances (e.g., atoms, molecules, and ions). The insulating layer 110a and the insulating layer 110c can also be said to function as barrier films. Specifically, the insulating layer 110a and the insulating layer 110c preferably are impermeable to impurities. This can prevent impurities contained in the insulating layer 110a and the insulating layer 110c from diffusing into the channel formation region. Therefore, a highly reliable transistor can be obtained, exhibiting favorable electrical characteristics.

[0226] The insulating layer 110a and the insulating layer 110c are preferably made of a material that is difficult for oxygen to permeate. This can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 212a side through the insulating layer 110a. Similarly, it can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 212b side through the insulating layer 110c. This increases the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 208, reducing oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor exhibiting favorable electrical characteristics and high reliability can be obtained. Furthermore, the conductive layer 212a can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which would prevent the electrical resistance of the conductive layer 212a from increasing. Similarly, the conductive layer 212b can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which would prevent the electrical resistance of the conductive layer 212b from increasing. Therefore, a transistor with a large on-state current can be obtained.

[0227] The above description can be referred to for materials that can be used for the barrier film. For the insulating layer 110a and the insulating layer 110c, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide can be suitably used. The insulating layer 110a and the insulating layer 110c can be made of the same material. Alternatively, the insulating layer 110a and the insulating layer 110c can be made of different materials.

[0228] By using an oxide or an oxynitride for the insulating layer 110c, oxygen can be supplied to the insulating layer 110b (or the insulating film that becomes the insulating layer 110b) when the insulating layer 110c (or the insulating film that becomes the insulating layer 110c) is formed.

[0229] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0230] One or more of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can have a stacked structure.

[0231] When the insulating layer 110c has a stacked structure, the layers constituting the insulating layer 110c can be made of the materials listed for the insulating layer 110c. An oxide or an oxynitride can be preferably used for the layer provided on the insulating layer 110b side. More specifically, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly preferably used for the layer provided on the insulating layer 110b side. By using an oxide or an oxynitride for the layer provided on the insulating layer 110b side, oxygen can be supplied to the insulating layer 110b (or the insulating film that will become the insulating layer 110b) during the formation of the layer (or the film that will become the layer), which is preferable. The insulating layer 110c can have a stacked structure, for example, of a first film containing an oxide or an oxynitride and a second film containing a nitride or a nitride oxide on the first film. More specifically, the insulating layer 110c can have a stacked structure of, for example, an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0232] 8A and 8B are cross-sectional views of a semiconductor device 20A according to one embodiment of the present invention. For a top view of the semiconductor device 20A, see FIG. 6A . FIG. 8A is a cross-sectional view of the cut surface taken along dashed line A1-A2 in FIG. 6A , and FIG. 8B is a cross-sectional view of the cut surface taken along dashed line A1-A2.

[0233] The semiconductor device 20A includes a transistor 200 and an insulating layer 110. The semiconductor device 20A differs from the semiconductor device 20 shown in FIG. 6B etc. mainly in that the insulating layer 110 includes an insulating layer 110d and an insulating layer 110e.

[0234] The insulating layer 110 includes an insulating layer 110d, an insulating layer 110a on the insulating layer 110d, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110e on the insulating layer 110c.

[0235] The insulating layer 110d is provided between the conductive layer 212a and the insulating layer 110a. The insulating layer 110d is provided so as to cover the conductive layer 212a. The insulating layer 110d has regions in contact with the top surface and side surfaces of the conductive layer 212a, the top surface of the substrate 102, and the side surfaces of the semiconductor layer 208.

[0236] The insulating layer 110e is provided between the conductive layer 212b and the insulating layer 110c. The insulating layer 110e has regions in contact with the top surface of the insulating layer 110c, the bottom surface of the conductive layer 212a, and the side surface of the semiconductor layer 208.

[0237] It is more preferable that the insulating layer 110d and the insulating layer 110e each be made of a material that releases impurities (e.g., water and hydrogen) that reduce the electrical resistance of the semiconductor layer 208. Impurities are released from the insulating layer 110d and diffuse into a region of the semiconductor layer 208 that is in contact with the insulating layer 110d. This allows the region of the semiconductor layer 208 that is in contact with the insulating layer 110d to contain impurities and become a low-resistance region. The semiconductor layer 208 can have a low-resistance region between a region that is in contact with the conductive layer 212a (one of the source and drain regions) and the channel formation region. Similarly, by using a material that releases impurities for the insulating layer 110e, impurities are released from the insulating layer 110e and diffuse into a region of the semiconductor layer 208 that is in contact with the insulating layer 110e. The region of the semiconductor layer 208 that is in contact with the insulating layer 110e contains impurities and becomes a low-resistance region. The semiconductor layer 208 may have a low-resistance region between a region in contact with the conductive layer 212b (the other of the source and drain regions) and the channel formation region. The low-resistance region may function as a buffer region for reducing the drain electric field. Note that the low-resistance region may function as the source or drain region.

[0238] By providing a low-resistance region between the drain region and the channel formation region, a high electric field is less likely to be generated near the drain region, which can suppress the generation of hot carriers and the deterioration of the transistor. For example, when the conductive layer 212a functions as a drain electrode and the conductive layer 212b functions as a source electrode, by forming a region of the semiconductor layer 208 in contact with the insulating layer 110d as a low-resistance region, a high electric field is less likely to be generated near the drain region, which can suppress the generation of hot carriers and the deterioration of the transistor. When the conductive layer 212a functions as a source electrode and the conductive layer 212b functions as a drain electrode, by forming a region of the semiconductor layer 208 in contact with the insulating layer 110e as a low-resistance region, a high electric field is less likely to be generated near the drain region, which can suppress the generation of hot carriers and the deterioration of the transistor.

[0239] When the region of the semiconductor layer 208 in contact with the insulating layer 110d functions as a source region or a drain region, the distance from the source region to the gate electrode and the distance from the drain region to the gate electrode of the semiconductor layer 208 can be made more uniform, thereby making it possible to make the electric field of the gate electrode applied to the channel formation region more uniform.

[0240] When a metal oxide is used for the semiconductor layer 208, it is more preferable that the impurities released from the insulating layer 110d and the insulating layer 110e contain hydrogen. The hydrogen reacts with oxygen that is bonded to the metal atoms of the metal oxide to form water, which causes oxygen deficiency (V Ｏ ) is formed. Furthermore, oxygen vacancies (V Ｏ ) with hydrogen (V Ｏ H) functions as a donor, generating electrons as carriers. This increases the carrier concentration in the region of the semiconductor layer 208 that is in contact with the insulating layer 110d and the region that is in contact with the insulating layer 110e, thereby reducing the electrical resistance.

[0241] The insulating layer 110d preferably has a region with a higher hydrogen content than the insulating layer 110a. The hydrogen content of the insulating layer 110 can be analyzed by, for example, secondary ion mass spectrometry (SIMS).

[0242] The amount of released hydrogen can be adjusted by differentiating the film formation conditions between the insulating layer 110d and the insulating layer 110a. Specifically, it is preferable to make one or more of the film formation power (film formation power density), film formation pressure, film formation gas type, film formation gas flow rate ratio, film formation temperature, and distance between the substrate and the electrode different between the insulating layer 110d and the insulating layer 110a. For example, by making the film formation power density of the insulating layer 110d lower than the film formation power density of the insulating layer 110a, the hydrogen content in the insulating layer 110d can be made higher than the hydrogen content in the insulating layer 110a. This increases the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d.

[0243] The hydrogen content in the deposition gas used to deposit the insulating layer 110d is preferably higher than the hydrogen content in the deposition gas used to deposit the insulating layer 110a. Specifically, when silicon nitride films or silicon nitride oxide films are deposited as the insulating layer 110d and the insulating layer 110a by a PECVD method, the ratio of the flow rate of ammonia gas to the total flow rate of the deposition gas used to deposit the insulating layer 110d (hereinafter also referred to as the ammonia flow ratio) is preferably higher than the ammonia flow rate of the deposition gas used to deposit the insulating layer 110a. By depositing the insulating layer 110d under conditions with a high ammonia flow ratio, the hydrogen content in the insulating layer 110d can be increased. Furthermore, the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d can be increased.

[0244] It is more preferable that the film density of the insulating layer 110a be higher than that of the insulating layer 110d. This can prevent hydrogen contained in the insulating layer 110d from diffusing into the channel formation region of the semiconductor layer 208 via the insulating layers 110a and 110b. The film density can be evaluated using, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a darker transmission electron (TE) image, whereas a low film density results in a lighter transmission electron (TE) image. Therefore, in a transmission electron (TE) image, the insulating layer 110a may appear darker than the insulating layer 110d. Even if the same material is used for the insulating layers 110d and 110a, the film densities are different, and therefore the boundary between them may be observed as a difference in contrast in a cross-sectional TEM image.

[0245] The insulating layer 110e preferably has a region containing more hydrogen than the insulating layer 110c. The film density of the insulating layer 110c is more preferably higher than that of the insulating layer 110e. For the insulating layers 110c and 110e, the descriptions of the insulating layers 110a and 110d can be referred to.

[0246] Here, the insulating layer 110 is shown to have a stacked structure of three or five layers, but one embodiment of the present invention is not limited to this. The insulating layer 110 preferably includes at least the insulating layer 110b. A structure without one or more of the insulating layer 110d, the insulating layer 110a, the insulating layer 110c, and the insulating layer 110e is also possible. The insulating layer 110 can have a stacked structure of two, four, or six or more layers. Alternatively, the insulating layer 110 can have a single-layer structure.

[0247] The configuration of the insulating layer 110 can be applied to other configuration examples.

[0248] [Opening 141, Opening 143] The top surface shapes of openings 141 and 143 are not limited and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or other polygonal shape, or shapes with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 6A and other figures, the top surface shapes of openings 141 and 143 are preferably circular. By making the top surface shapes of the openings circular, the processing accuracy when forming the openings can be improved, allowing for the formation of openings of finer sizes. Note that, in this specification and other documents, "circular" does not necessarily mean a perfect circle.

[0249] In this specification and the like, the top surface shape of the opening 141 refers to the shape of the top surface end portion of the insulating layer 110 on the opening 141 side. Also, the top surface shape of the opening 143 refers to the shape of the bottom surface end portion of the conductive layer 212b on the opening 143 side.

[0250] As shown in FIG. 6A and other figures, the top shapes of the openings 141 and 143 can be identical or substantially identical to each other. In this case, as shown in FIGS. 6B and 6C and other figures, it is preferable that the bottom edge of the conductive layer 212b on the opening 143 side be identical or substantially identical to the top edge of the insulating layer 110 on the opening 141 side. The bottom surface of the conductive layer 212b refers to the surface on the insulating layer 110 side. The top surface of the insulating layer 110 refers to the surface on the conductive layer 212b side. The top shapes of the openings 141 and 143 can also be configured to not be identical to each other. When the top shapes of the openings 141 and 143 are circular, the openings 141 and 143 can also be concentric. Alternatively, the openings 141 and 143 can be configured not to be concentric.

[0251] 9A and 9B, the channel length and the channel width of the transistor 200 will be described. Here, a region of the semiconductor layer 208 in contact with the insulating layer 110b will be described as a channel formation region. FIG. 9A is a top view of the semiconductor device 20.

[0252] In FIG. 9B , the channel length L of the transistor 200 is indicated by a dashed double-headed arrow. The channel length L of the transistor 200 corresponds to the length of the side surface of the insulating layer 110b on the opening 141 side in a cross-sectional view. That is, the channel length L is determined by the thickness T110 of the insulating layer 110b and the angle θ110 between the side surface of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Therefore, the channel length L can be set to a value smaller than the minimum exposure dimension of the exposure tool, thereby enabling the realization of a fine-sized transistor. Specifically, it is possible to realize a transistor with an extremely short channel length that could not be realized using conventional exposure tools for mass production of flat panel displays (e.g., minimum dimensions of approximately 2 μm or 1.5 μm). Furthermore, it is also possible to realize a transistor with a channel length of less than 10 nm without using the extremely expensive exposure tools used in cutting-edge LSI technology.

[0253] The channel length L may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L may be 100 nm or more and 1 μm or less.

[0254] By shortening the channel length L, the on-state current of the transistor 200 can be increased. By using the transistor 200, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0255] The channel length L can be controlled by adjusting the thickness T110 and angle θ110 of the insulating layer 110b.

[0256] The thickness T110 of the insulating layer 110b may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. In FIG. 9B , the thickness T110 is indicated by a solid double-headed arrow. The thickness T110 may be the shortest distance between the surface on which the insulating layer 110b is to be formed (here, the top surface of the insulating layer 110a) and the top surface of the insulating layer 110b in a cross-sectional view.

[0257] When the angle θ110 is 90 degrees or less, the channel length L can be increased as the angle θ110 is smaller, and the channel length L can be decreased as the angle θ110 is larger.

[0258] 9B and other drawings, the angle θ110 is shown as being less than 90 degrees; however, one embodiment of the present invention is not limited to this. The angle θ110 can be set to 90 degrees or approximately 90 degrees. This can shorten the channel length L of the transistor 200.

[0259] 6B and the like show a structure in which the shape of the side surface of the insulating layer 110 on the opening 141 side is straight in a cross-sectional view, but one embodiment of the present invention is not limited to this. In a cross-sectional view, the shape of the side surface of the insulating layer 110 on the opening 141 side can be curved. Alternatively, a structure can be used in which the shape of the side surface includes both a straight region and a curved region.

[0260] Here, the conductive layer 212b is preferably not provided inside the opening 141. Specifically, the conductive layer 212b preferably does not have a region in contact with the side surface of the insulating layer 110 on the opening 141 side. If the conductive layer 212b is also provided inside the opening 141, the channel length L of the transistor 200 becomes shorter than the length of the side surface of the insulating layer 110b, which may make it difficult to control the channel length L. Therefore, it is preferable that the top shape of the opening 143 coincides with the top shape of the opening 141 or that the opening 143 encompasses the opening 141 in a top view (also referred to as a plan view).

[0261] 9A and 9B, the width D141 of the opening 141 is indicated by a two-dot chain line with a double arrow. FIG. 9A shows an example in which the top surface shape of the opening 141 is circular. In this case, the width D141 corresponds to the diameter of the circle, and the channel width W of the transistor 200 is the length of the circumference of the circle. In other words, the channel width W is π×D141. In this way, when the top surface shape of the opening 141 is circular, a transistor with a smaller channel width W can be realized compared to other shapes.

[0262] The width D141 of the opening 141 may vary in the depth direction. For example, the width D141 of the opening 141 may be an average value of the diameter at the highest point, the diameter at the lowest point, and the diameter at the midpoint between these three points of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view. Alternatively, the diameter of the opening 141 may be any of the diameter at the highest point, the diameter at the lowest point, or the diameter at the midpoint between these three points of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view.

[0263] When the opening 141 is formed using lithography, the width D141 of the opening 141 is equal to or greater than the minimum exposure dimension of the exposure device. The width D141 can be, for example, 20 nm or greater, 50 nm or greater, 100 nm or greater, 200 nm or greater, 300 nm or greater, 400 nm or greater, or 500 nm or greater, and can be less than 5 μm, 4.5 μm or less, 4 μm or less, 3.5 μm or less, 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, or 1 μm or less.

[0264] Note that although the example in which the region of the semiconductor layer 208 in contact with the insulating layer 110b functions as a channel formation region has been described here, one embodiment of the present invention is not limited to this. The region of the semiconductor layer 208 in contact with the insulating layer 110a may also function as a channel formation region. Similarly, the region in contact with the insulating layer 110c may also function as a channel formation region.

[0265] 10A and 10B are cross-sectional views of a semiconductor device 20B according to one embodiment of the present invention. For a top view of the semiconductor device 20B, see FIG. 6A. FIG. 10A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 6A, and FIG. 10B is a cross-sectional view of a cut surface taken along dashed line B1-B2 in FIG. 6A.

[0266] The semiconductor device 20B includes a transistor 200, an insulating layer 110, and an insulating layer 109. The semiconductor device 20B differs from the semiconductor device 20 shown in FIG.

[0267] The insulating layer 109 is located between the substrate 102 and the conductive layer 212a. The insulating layer 109 is provided on the substrate 102, the conductive layer 212a is provided on the insulating layer 109, and the insulating layer 110 is provided on the conductive layer 212a. The insulating layer 109 has regions in contact with the lower surface of the conductive layer 212a and the lower surface of the insulating layer 110. The conductive layer 212a has regions in contact with the insulating layer 109 and the insulating layer 110 and sandwiched therebetween. The insulating layer 110 has regions in contact with the upper and side surfaces of the conductive layer 212a, the upper surface of the insulating layer 109, the side surface of the semiconductor layer 208, the lower surface of the conductive layer 212b, and the lower surface of the insulating layer 206.

[0268] The insulating layer 109 preferably has a barrier property. The insulating layer 109 is preferably made of a material through which impurities (for example, water and hydrogen) contained in the substrate 102 do not easily diffuse. This can prevent impurities from diffusing from the substrate 102 to the transistor 200.

[0269] The description of the barrier film can be referred to for the insulating layer 109. For example, the insulating layer 109 can be formed using one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing aluminum, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, for example, the insulating layer 109 can be formed using one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0270] The insulating layer 109 is preferably made of a material that releases impurities (for example, water and hydrogen) that reduce the electrical resistance of the semiconductor layer 208. The insulating layer 109 can be made of the same material as can be used for the insulating layers 110d and 110e. For example, the insulating layer 109 can preferably be made of silicon nitride containing hydrogen or silicon nitride oxide containing hydrogen.

[0271] The impurities released from the insulating layer 109 diffuse into a region of the conductive layer 212a that is in contact with the insulating layer 109. The impurities diffused into the conductive layer 212a also diffuse into a region of the semiconductor layer 208 that is in contact with the conductive layer 212a. This reduces the electrical resistance of the region of the semiconductor layer 208 that is in contact with the conductive layer 212a, that is, one of the source region and the drain region. This allows a transistor with a large on-state current to be obtained, thereby enabling a semiconductor device that operates at high speed.

[0272] When a metal oxide is used for the semiconductor layer 208, it is more preferable that the impurities released from the insulating layer 109 contain hydrogen. Hydrogen diffused from the insulating layer 109 to the semiconductor layer 208 through the conductive layer 212a increases the carrier concentration in the region of the semiconductor layer 208 that is in contact with the conductive layer 212a, and can reduce the electrical resistance of one of the source region and the drain region.

[0273] The insulating layer 109 is preferably made of a material that releases impurities that reduce the electrical resistance of the conductive layer 212a. This can reduce the electrical resistance of the conductive layer 212a. For example, when a metal oxide is used for the conductive layer 212a, the impurities preferably contain hydrogen. This increases the carrier concentration of the conductive layer 212a, thereby reducing the electrical resistance. Furthermore, the conductive layer 212a can function as a wiring, thereby providing a semiconductor device with low wiring resistance. Note that the impurities that reduce the electrical resistance of the conductive layer 212a may be the same as or different from the impurities that reduce the electrical resistance of the semiconductor layer 208.

[0274] The materials that can be used for the conductive layer 212a are as described above. Note that the conductive layer 212a is preferably one that easily transmits impurities and one that is less likely to adsorb impurities.

[0275] The insulating layer 110a has a region in contact with the top surface of the insulating layer 109 and the top surface and side surfaces of the conductive layer 212a, which can suppress diffusion of impurities contained in the insulating layer 109 and the conductive layer 212a into the channel formation region of the semiconductor layer 208 through the insulating layer 110b.

[0276] The insulating layer 109 preferably has a region containing more hydrogen than the insulating layer 110a. The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109. For the insulating layer 109, the descriptions of the insulating layers 110d and 110e can be referred to.

[0277] Note that impurities released from the insulating layer 109 may diffuse into the channel formation region via the conductive layer 212a and one of the source region and the drain region of the semiconductor layer 208. However, oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 208 that is in contact with the insulating layer 110b, and therefore oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, enabling a transistor with both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0278] 10A and other drawings show the insulating layer 110 having a four-layer structure including insulating layers 110a, 110b, 110c, and 110e, but one embodiment of the present invention is not limited to this. For example, the insulating layer 110 can have a five-layer structure including insulating layers 110d, 110a, 110b, 110c, and 110e. Alternatively, the insulating layer 110 can have a three-layer structure including insulating layers 110a, 110b, and 110c.

[0279] The structure of the insulating layer 109 shown here can also be applied to other structure examples.

[0280] 11A shows a top view of a semiconductor device 30 according to one embodiment of the present invention. FIG. 11B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 11A , and FIG. 11C shows a cross-sectional view of the cut surface taken along dashed dotted line A3-A4 in FIG.

[0281] The semiconductor device 30 includes a transistor 300. The transistor 300 includes a conductive layer 180 over a substrate 102, an insulating layer 182 over the conductive layer 180, a semiconductor layer 184 over the insulating layer 182, and conductive layers 186a and 186b over the semiconductor layer 184. The conductive layer 180 has a region overlapping with the semiconductor layer 184 with the insulating layer 182 interposed therebetween. The conductive layer 180 functions as a gate electrode of the transistor 300, and the insulating layer 182 functions as a gate insulating layer. The conductive layer 186a functions as one of a source electrode and a drain electrode of the transistor 300, and the conductive layer 186b functions as the other of the source electrode and drain electrode.

[0282] The semiconductor layer 184 can be formed using the materials listed for the semiconductor layer 108. For the semiconductor layer 184, the description of the semiconductor layer 108 can be referred to. For the semiconductor layer 184, indium oxide can be suitably used, for example.

[0283] The conductive layer 186a and the conductive layer 186b have regions in contact with the semiconductor layer 184. A region of the semiconductor layer 184 in contact with the conductive layer 186a functions as one of the source region and the drain region. A region of the semiconductor layer 184 in contact with the conductive layer 186b functions as the other of the source region and the drain region. A region of the semiconductor layer 184 that overlaps with the conductive layer 180 with the insulating layer 182 interposed therebetween functions as a channel formation region.

[0284] In the region where the semiconductor layer 184 and the conductive layer 180 overlap, the shortest distance between the source region and the drain region is the channel length L of the transistor 300 (see FIG. 11B). Also, the width of the region where the semiconductor layer 184 and the conductive layer 180 overlap in a direction perpendicular to the channel length direction is the channel width W of the transistor 300 (see FIG. 11C).

[0285] The transistor 300 is a so-called bottom-gate transistor having a gate electrode below the semiconductor layer 184. In addition, conductive layers 186a and 186b functioning as a source electrode and a drain electrode are provided over the semiconductor layer 184. The transistor 300 can be referred to as a bottom-gate top-contact (BGTC) transistor.

[0286] The BGTC transistor can reduce the number of masks used in manufacturing the transistor, thereby reducing the manufacturing cost of the semiconductor device.

[0287] Note that there may be a recess in a region of the semiconductor layer 184 that does not overlap with either the conductive layer 186a or the conductive layer 186b. For example, the conductive layers 186a and 186b can be formed by depositing a conductive film that will become the conductive layer 186a and the conductive layer 186b over the semiconductor layer 184 and processing the conductive film. When processing the conductive film, part of the semiconductor layer 184 is removed, and thus a recess may be formed in the semiconductor layer 184.

[0288] An insulating layer 188 is provided over the transistor 300, and an insulating layer 189 is provided over the insulating layer 188. The insulating layer 188 and the insulating layer 189 function as protective layers for the transistor 300. The insulating layer 188 has a region between the conductive layer 186a and the conductive layer 186b that overlaps with the conductive layer 180 with the semiconductor layer 184 and the insulating layer 182 interposed therebetween. The insulating layer 188 preferably contains oxygen because it has a region in contact with the channel formation region. The insulating layer 188 can preferably use one or more of an oxide and an oxynitride. The insulating layer 188 can preferably use the materials listed for the insulating layer 110b. The insulating layer 189 preferably functions as a barrier film. By providing a barrier film, diffusion of impurities from the outside into the transistor can be effectively suppressed, resulting in a highly reliable semiconductor device. The above description can be referred to for the barrier film. Note that the insulating layer 188 can also function as a barrier film.

[0289] The insulating layer 182 has a region in contact with the semiconductor layer 184. When a metal oxide is used for the semiconductor layer 184, at least a part of the region of the insulating layer 182 in contact with the semiconductor layer 184 preferably contains oxygen in order to improve the interface characteristics between the semiconductor layer 184 and the insulating layer 182. Specifically, the region of the insulating layer 182 in contact with the channel formation region of the semiconductor layer 184 preferably contains oxygen. One or more of an oxide and an oxynitride can be preferably used for the region of the insulating layer 182 in contact with the channel formation region of the semiconductor layer 184. The same applies to the insulating layer 188. For example, the insulating layer 182 and the insulating layer 188 each preferably contain silicon and oxygen. Silicon oxide or silicon oxynitride can be preferably used for the insulating layer 182 and the insulating layer 188.

[0290] 12A and 12B show examples of a structure different from those shown in FIGS. 11A to 11C . FIGS. 12A and 12B are cross-sectional views of a semiconductor device 30A according to one embodiment of the present invention. For a top view of the semiconductor device 30A, refer to FIG. 11A . FIG. 12A is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 11A , and FIG. 12B is a cross-sectional view of a cut surface taken along dashed dotted line A3-A4 in FIG.

[0291] The semiconductor device 30A includes a transistor 300A. The transistor 300A differs from the transistor 300 mainly in that the insulating layer 182 has a stacked structure.

[0292] 12A and 12B show an example in which the insulating layer 182 includes an insulating layer 182a and an insulating layer 182b on the insulating layer 182a.

[0293] The insulating layer 182b has a region in contact with the semiconductor layer 184. As described above, the insulating layer 182b in contact with the semiconductor layer 184 preferably contains oxygen.

[0294] The insulating layer 182a located on the conductive layer 180 side preferably functions as a barrier film. By providing the barrier film, it is possible to suppress diffusion of components (e.g., metals) contained in the conductive layer 180 or the substrate 102 into the transistor, thereby providing a highly reliable semiconductor device. The above description of the barrier film can be referred to. The insulating layer 182a preferably contains nitrogen.

[0295] The insulating layer 182a preferably contains silicon and nitrogen, and the insulating layer 182b preferably contains silicon and oxygen. For example, silicon nitride can be preferably used for the insulating layer 182a, and silicon oxynitride can be preferably used for the insulating layer 182b.

[0296] The configuration of the insulating layer 182 shown here can also be applied to other configuration examples.

[0297] 13A to 13C show examples of structures different from those shown in FIGS. 11A to 11C . Fig. 13A is a top view of a semiconductor device 30B according to one embodiment of the present invention. Fig. 13B is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in Fig. 13A , and Fig. 13C is a cross-sectional view of a cut surface taken along dashed dotted line A3-A4 in Fig. 13A .

[0298] The semiconductor device 30B includes a transistor 300B. The transistor 300B differs from the transistor 300 mainly in that the transistor 300B includes a conductive layer 185.

[0299] The conductive layer 185 is provided over the insulating layer 188. The conductive layer 185 functions as a back gate electrode of the transistor 300B. The conductive layer 185 is provided so as to overlap with the conductive layer 180 with the semiconductor layer 184 interposed therebetween. The conductive layer 185 is preferably provided so as to cover the entire channel formation region. This can enhance the effect of making an electric field generated outside the transistor less likely to act on the channel formation region (also referred to as an electric field shielding effect). The insulating layer 188 functions as a back gate insulating layer of the transistor 300B.

[0300] The structure of the conductive layer 185 shown here can also be applied to other structure examples.

[0301] 14A and 14B are cross-sectional views of a semiconductor device 30C according to one embodiment of the present invention. For a top view of the semiconductor device 30C, see FIG. 11A. FIG. 14A is a cross-sectional view of the cut surface taken along dashed line A1-A2 in FIG. 11A, and FIG. 14B is a cross-sectional view of the cut surface taken along dashed line A3-A4 in FIG.

[0302] The semiconductor device 30C includes a transistor 300C. The transistor 300C differs from the transistor 300 shown in FIG.

[0303] The insulating layer 187 is provided over the semiconductor layer 184. The insulating layer 187 has a region overlapping with the conductive layer 180 with the semiconductor layer 184 and the insulating layer 182 interposed therebetween. Part of the conductive layer 186a and part of the conductive layer 186b are provided over the insulating layer 187.

[0304] The insulating layer 187 functions as a channel protective film that protects the channel formation region when the conductive layers 186a and 186b are formed. The insulating layer 187 is provided over the semiconductor layer 184, and a conductive film that will become the conductive layers 186a and 186b is formed on the insulating layer 187. The conductive film is then processed to form the conductive layers 186a and 186b. Since the channel formation region is not exposed during the formation and processing of the conductive film, damage to the channel formation region can be suppressed. Therefore, a transistor with favorable electrical characteristics can be obtained. Note that a transistor having a channel protective film (e.g., the transistor 300C) can be referred to as a channel protective transistor. On the other hand, a transistor without a channel protective film (e.g., the transistors 300 to 300B) can be referred to as a channel-etched transistor.

[0305] 15A and 15B show examples of a structure different from those shown in FIGS. 14A and 14B . FIG. 15A is a top view of a semiconductor device 30D according to one embodiment of the present invention. FIG. 15B is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 15A . For a cross-sectional view of a cut surface taken along dashed dotted line A3-A4, refer to FIG. 14B .

[0306] The semiconductor device 30D includes a transistor 300D. The transistor 300D differs from the transistor 300C shown in FIG. 14A and other drawings mainly in that the insulating layer 187 has an opening 181a and an opening 181b.

[0307] The insulating layer 187 has openings 181a and 181b that reach the semiconductor layer 184. Conductive layers 186a and 186b are provided so as to cover the openings 181a and 181b. The conductive layer 186a has a region in contact with the semiconductor layer 184 in the opening 181a, and the conductive layer 186b has a region in contact with the semiconductor layer 184 in the opening 181b.

[0308] The insulating layer 187 has a region in contact with the semiconductor layer 184. At least a part of the region of the insulating layer 187 in contact with the semiconductor layer 184 preferably contains oxygen. For example, the insulating layer 187 preferably contains silicon and oxygen. Silicon oxide or silicon oxynitride can be suitably used for the insulating layer 187.

[0309] The configuration of the insulating layer 187 shown here can also be applied to other configuration examples.

[0310] 16A shows a top view of a semiconductor device 30E according to one embodiment of the present invention. FIG. 16B shows a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 16A. FIG. 11C shows a cross-sectional view taken along dashed dotted line A3-A4.

[0311] The semiconductor device 30E includes a transistor 300E. The transistor 300E differs from the transistor 300 shown in FIG. 11B and the like mainly in that the conductive layer 186a and the conductive layer 186b are located between the semiconductor layer 184 and the insulating layer 182.

[0312] The transistor 300E is a so-called bottom-gate transistor. The semiconductor layer 184 is provided over the conductive layers 186a and 186b, which function as a source electrode and a drain electrode. The transistor 300E can be referred to as a bottom-gate bottom-contact (BGBC) transistor.

[0313] Since the semiconductor layer 184 is formed after the conductive layers 186a and 186b are formed, damage to the semiconductor layer 184 can be prevented when the conductive layers 186a and 186b are formed.

[0314] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0315] A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that the description of the materials and formation methods of the elements described above may be omitted.

[0316] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. CVD methods include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0317] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0318] When processing a thin film that constitutes a semiconductor device, a lithography method or the like can be used. Alternatively, the thin film can be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film can be directly formed by a film formation method using a shielding mask such as a metal mask.

[0319] There are two typical lithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0320] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other examples include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0321] The thin film can be etched by one or more of dry etching, wet etching, and sandblasting.

[0322] 2A to 2C , a cross-sectional view taken along dashed line A1-A2 in FIG. 2B and a cross-sectional view taken along dashed line B1-B2 in FIG. 2C are shown side by side.

[0323] First, a conductive film to be the conductive layer 103 is formed over the substrate 102, and then processed to form the conductive layer 103. The conductive film can be formed by a sputtering method.

[0324] Subsequently, the insulating layer 105 is formed on the conductive layer 103 and the substrate 102 (FIG. 17A). The insulating layer 105 can be preferably formed by sputtering or PECVD.

[0325] Next, a metal oxide film 108f that will become the semiconductor layer 108 is formed on the insulating layer 105 (FIG. 17B). The metal oxide film 108f is provided in contact with the upper surface of the insulating layer 105.

[0326] The metal oxide film 108f is preferably formed by sputtering using a metal target or a metal oxide target. Alternatively, the metal oxide film 108f is preferably formed by ALD. The ALD method allows easy control of the film formation rate, and thus allows thin films to be formed with a high yield. Therefore, the ALD method is particularly suitable when the metal oxide film 108f is thin. Alternatively, the CVD method can be used to form the metal oxide film 108f.

[0327] When forming the metal oxide film 108f, an inert gas (for example, helium gas, argon gas, xenon gas, or the like) can be used.

[0328] The metal oxide film 108f is preferably formed under conditions that result in low crystallinity of the metal oxide film 108f. By performing heat treatment after forming the metal oxide film 108f with low crystallinity to crystallize it, the grain size of the crystal grains can be increased. Here, if the number of crystal grains contained in the metal oxide film 108f increases at the stage of forming the metal oxide film 108f, the grain size of the crystal grains after the heat treatment may become small. Therefore, it is preferable that the number of crystal grains contained in the metal oxide film 108f is small and the crystallinity of the metal oxide film 108f is low at the stage of forming the metal oxide film 108f.

[0329] It is preferable to use hydrogen gas when forming the metal oxide film 108f. This can reduce the number of crystal grains generated during the formation of the metal oxide film 108f, resulting in a metal oxide film 108f with low crystallinity. A mixture of hydrogen gas and an inert gas can be used when forming the metal oxide film 108f. For example, the ratio of the flow rate of hydrogen gas to the total film formation gas when forming the metal oxide film 108f (hereinafter also referred to as the hydrogen flow rate ratio) is preferably greater than 0% and less than 20%, more preferably greater than 0% and less than 15%, and even more preferably greater than 0% and less than 10%. The hydrogen flow rate ratio when forming the metal oxide film 108f is not limited to the above-mentioned range.

[0330] By using oxygen gas when forming the metal oxide film 108f, it is possible to prevent oxygen vacancies from occurring in the metal oxide film 108f. Furthermore, oxygen can be supplied into the insulating layer 105 when forming the metal oxide film 108f. This allows oxygen to be supplied to the semiconductor layer 108 in a later step, and oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ H can be reduced. When forming the metal oxide film 108f, a mixture of oxygen gas and an inert gas can be used. On the other hand, if the ratio of the flow rate of oxygen gas to the total film formation gas when forming the metal oxide film 108f (hereinafter also referred to as the oxygen flow rate ratio) is high, the number of crystal grains contained in the metal oxide film 108f may increase when the metal oxide film 108f is formed. The oxygen flow rate ratio when forming the metal oxide film 108f is preferably higher than 0% and not higher than 10%, more preferably higher than 0% and not higher than 5%, and even more preferably higher than 0% and not higher than 3%. By setting the oxygen flow rate ratio within the above range, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ This can reduce H and also lower the crystallinity of the metal oxide film 108f. Note that the oxygen flow rate ratio in the formation of the metal oxide film 108f is not limited to the above range.

[0331] A mixture of hydrogen gas, oxygen gas, and an inert gas can be used as the deposition gas for the metal oxide film 108f. Typically, oxygen gas, hydrogen gas, and argon gas can be suitably used as the deposition gas for the metal oxide film 108f. The oxygen flow rate ratio and the hydrogen flow rate ratio are preferably set in the above-mentioned ranges. This can reduce the crystallinity of the metal oxide film 108f and increase the grain size of the crystal grains after the heat treatment. In addition, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ It is possible to reduce H. The oxygen flow rate ratio and the hydrogen flow rate ratio in the formation of the metal oxide film 108f are not limited to the above ranges.

[0332] The substrate temperature during deposition of the metal oxide film 108f is preferably low. This can reduce the crystallinity of the metal oxide film 108f. The substrate temperature during deposition of the metal oxide film 108f is preferably room temperature (e.g., 25°C) or higher and 150°C or lower, more preferably room temperature or higher and 100°C or lower, further preferably room temperature or higher and 80°C or lower, and further preferably room temperature or higher and 50°C or lower. In particular, it is preferable to deposit the metal oxide film 108f at room temperature or without heating the substrate. Note that the substrate temperature during deposition of the metal oxide film 108f is not limited to the above-mentioned range.

[0333] When the ALD method is used, it is preferable to use a film formation method such as a thermal ALD method or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it not only exhibits high coverage but also allows low-temperature film formation.

[0334] The metal oxide film 108f can be formed by, for example, an ALD method using a precursor containing a constituent metal element and an oxidizing agent.

[0335] For example, when forming an indium oxide film, a precursor containing indium can be used, such as triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]indium.

[0336] Oxidizing agents include, for example, ozone, oxygen, hydrogen peroxide, and water.

[0337] The composition of the resulting film can be controlled by adjusting one or more of the types of source gases, the flow rate ratio of the source gases, the time for which the source gases are flowed, and the order in which the source gases are flowed. By adjusting these, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these, it is possible to form a metal oxide film 108f whose composition changes continuously.

[0338] Before forming the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 105 and a treatment for supplying oxygen into the insulating layer 105. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２ By performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO), oxygen can be supplied to the insulating layer 105. When plasma treatment is performed in an atmosphere containing nitrous oxide gas, oxygen can be supplied while organic substances on the surface of the insulating layer 105 are suitably removed. After such treatment, it is preferable to form a metal oxide film 108f successively without exposing the surface of the insulating layer 105 to the air.

[0339] Next, the metal oxide film 108f is processed into an island shape to form a metal oxide layer 108F (FIG. 17C). When indium oxide is used for the semiconductor layer 108, the metal oxide film 108f and the metal oxide layer 108F can be called an indium oxide layer or an indium oxide film.

[0340] The metal oxide layer 108F can be preferably formed by wet etching. At this time, a part of the insulating layer 105 in a region that does not overlap with the metal oxide layer 108F may be etched and thinned. Note that, in etching the metal oxide film 108f, by using a material with a high selectivity for the insulating layer 105, it is possible to prevent the thickness of the insulating layer 105 from becoming thin.

[0341] Subsequently, heat treatment is performed. The heat treatment crystallizes the metal oxide layer 108F, and the semiconductor layer 108 is formed (FIG. 17D). The temperature, atmosphere, and apparatus used in the heat treatment can be determined by referring to the above description.

[0342] The semiconductor layer 108 can be obtained by forming a metal oxide film 108f with low crystallinity, processing the metal oxide film 108f into an island shape, and then crystallizing the metal oxide film 108f by heat treatment. This allows the grain size of crystal grains contained in the semiconductor layer 108 to be increased. Furthermore, since the metal oxide film 108f can be processed into an island shape while still having low crystallinity, processing is facilitated, and productivity of the semiconductor device can be improved. Note that one embodiment of the present invention is not limited thereto. The semiconductor layer 108 can also be formed by forming a metal oxide film 108f with low crystallinity, crystallizing the film by heat treatment, and processing the film into an island shape.

[0343] By the heat treatment, oxygen can also be supplied from the insulating layer 105 to the metal oxide film 108f or the semiconductor layer 108. In this case, it is more preferable to perform the heat treatment before processing into the semiconductor layer 108.

[0344] Note that the heat treatment is not performed here, and can be performed in a subsequent step. In addition, a subsequent step in which heat is applied (for example, a film formation step) may also serve as the heat treatment.

[0345] Subsequently, an insulating film 106f that will become the insulating layer 106 is formed to cover the semiconductor layer 108 and the insulating layer 105 (FIG. 17E). The insulating film 106f can be formed by, for example, PECVD, sputtering, or ALD.

[0346] When an oxide semiconductor is used for the semiconductor layer 108, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. When the insulating layer 106 has a function of suppressing oxygen diffusion, oxygen is prevented from being released from the semiconductor layer 108, and oxygen vacancies (V Ｏ ) can be suppressed from increasing. Furthermore, oxygen contained in the semiconductor layer 108 is prevented from diffusing into the conductive layer 104 through the insulating layer 106, and the conductive layer 104 can be prevented from being oxidized. As a result, a transistor can be provided that exhibits favorable electrical characteristics and is highly reliable.

[0347] By increasing the temperature during the formation of the insulating film 106f, it is possible to obtain a gate insulating layer with fewer defects. However, if the temperature during the formation of the insulating film 106f is high, oxygen is released from the semiconductor layer 108, and oxygen vacancies and V in the semiconductor layer 108 occur. Ｏ H may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating film 106f within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0348] Before forming the insulating film 106f, plasma treatment can be performed on the surface of the semiconductor layer 108. The plasma treatment can reduce impurities such as water adsorbed to the surface of the semiconductor layer 108. This can reduce impurities at the interface between the semiconductor layer 108 and the insulating layer 106, thereby achieving a highly reliable transistor. This is particularly suitable for the case where the surface of the semiconductor layer 108 is exposed to the air between the formation of the semiconductor layer 108 and the formation of the insulating film 106f. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. Furthermore, the plasma treatment and the formation of the insulating film 106f are preferably performed successively without exposure to the air.

[0349] After the insulating film 106f is formed, oxygen can be supplied to the insulating film 106f. For example, ion implantation or plasma treatment can be used as a method for supplying oxygen. For the plasma treatment, an apparatus that converts gas into plasma using high-frequency power can be suitably used. Examples of the apparatus that converts gas into plasma using high-frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The plasma treatment is preferably performed in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N ２ O), nitrogen dioxide (NO ２ The plasma treatment is preferably performed in an atmosphere containing one or more of oxygen, carbon monoxide, and carbon dioxide. The amount of oxygen supplied can be adjusted by, for example, the power and treatment time in the plasma treatment.

[0350] A film 139 is preferably formed over the insulating film 106f (FIG. 17F). The film 139 can be formed by a sputtering method. By forming the film 139 in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 106f.

[0351] The conductivity of the film 139 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 139. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, ITO, or ITSO can be used as the film 139.

[0352] The film 139 is preferably formed using an oxide material containing one or more elements that are the same as those of the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108.

[0353] When forming the film 139, the amount of oxygen supplied to the insulating film 106f can be increased by increasing the oxygen flow rate of the film formation gas introduced into the treatment chamber of the film formation apparatus or the oxygen partial pressure in the treatment chamber. The oxygen flow rate or oxygen partial pressure is, for example, preferably 50% to 100%, more preferably 60% to 100%, even more preferably 70% to 100%, still more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate to 100% and the oxygen partial pressure as close to 100% as possible.

[0354] By forming the film 139 by sputtering in an oxygen-containing atmosphere in this manner, oxygen can be supplied to the insulating film 106f and oxygen can be prevented from being released from the insulating film 106f during the formation of the film 139. As a result, a large amount of oxygen can be trapped in the insulating film 106f. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by subsequent heat treatment. As a result, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0355] Heat treatment is preferably performed after the film 139 is formed. By performing heat treatment after the film 139 is formed, oxygen can be effectively supplied from the film 139 to the insulating film 106f.

[0356] The temperature of the heat treatment is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 450°C or lower, further preferably 250°C or higher and 450°C or lower, further preferably 300°C or higher and 450°C or lower, further preferably 300°C or higher and 400°C or lower, and further preferably 350°C or higher and 400°C or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. Dry air (CDA) can be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower. Using an atmosphere with as low a content of hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being taken into the insulating film 106f as much as possible. The heat treatment can be performed in an oven, an RTA apparatus, or the like.

[0357] After the film 139 is formed or after the heat treatment, oxygen can be further supplied to the insulating film 106f through the film 139. As a method for supplying oxygen, for example, ion implantation or plasma treatment can be used. Regarding the plasma treatment, the above description can be referred to, and therefore detailed description thereof will be omitted.

[0358] Next, the film 139 is removed. By removing the film 139, the insulating film 106f is exposed. There is no particular limitation on the method for removing the film 139, but wet etching can be suitably used. By using wet etching, etching of the insulating film 106f can be suppressed when the film 139 is removed. This prevents the thickness of the insulating film 106f from becoming thin, and allows the thickness of the insulating layer 106 to be uniform.

[0359] The process of supplying oxygen to the insulating film 106f is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied to the insulating film 106f by ion implantation or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 106f, and then oxygen can be supplied to the insulating film 106f through the film. The film is preferably removed after supplying oxygen. The film that suppresses oxygen desorption can be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0360] Next, the conductive layer 104 is formed on the insulating film 106f (FIG. 18A). The conductive film that becomes the conductive layer 104 can be preferably formed by, for example, sputtering, thermal CVD (including MOCVD), or ALD.

[0361] Next, using the conductive layer 104 as a mask, an impurity 190 is supplied (also referred to as adding or injecting) to the semiconductor layer 108. As a result, a region 108P and a region 108Q are formed in a region of the semiconductor layer 108 that does not overlap with the conductive layer 104 ( FIG. 18B ). At this time, it is preferable to determine the conditions for supplying the impurity in consideration of the material and thickness of the conductive layer 104 that serves as the mask so that the impurity 190 is not supplied to the region of the semiconductor layer 108 that overlaps with the conductive layer 104 as much as possible. As a result, a channel formation region with a sufficiently reduced impurity concentration can be formed in the region of the semiconductor layer 108 that overlaps with the conductive layer 104.

[0362] 18B schematically illustrates, with arrows, how the impurity 190 is supplied to the semiconductor layer 108. Note that although FIG. 18B illustrates a structure in which the impurity 190 is supplied to the semiconductor layer 108 through the insulating film 106f, one embodiment of the present invention is not limited to this. For example, in the transistor 100D illustrated in FIG. 4C , after the insulating layer 106 and the conductive layer 104 are formed, the impurity can be supplied to the semiconductor layer 108 using the conductive layer 104 as a mask. At this time, the impurity is supplied to the regions 108P and 108Q without passing through the insulating layer 106. The impurity is supplied to the regions 108R and 108S through the insulating layer 106.

[0363] Note that a resist mask is formed over the conductive film that is to be the conductive layer 104, and the conductive film is processed using the resist mask, so that the conductive layer 104 can be formed. Then, by using the resist mask and the conductive layer 104 as masks, impurities 190 are supplied to the semiconductor layer 108, so that the regions 108P and 108Q can be formed. After that, the resist mask is removed.

[0364] Subsequently, an insulating film 195f that will become the insulating layer 195 is formed to cover the conductive layer 104, the insulating layer 106, and the semiconductor layer 108 (FIG. 18C). The insulating film 195f can be preferably formed by PECVD.

[0365] If the deposition temperature of the insulating film 195f is too high, impurities contained in the regions 108P and 108Q may diffuse into the peripheral portion including the channel formation region of the semiconductor layer 108. In addition, the electrical resistance of the regions 108P and 108Q may increase. Therefore, it is preferable to determine the deposition temperature of the insulating film 195f in consideration of the diffusion of impurities.

[0366] The deposition temperature of the insulating film 195f is, for example, 150° C. to 400° C., preferably 180° C. to 360° C., and more preferably 200° C. to 250° C. By depositing the insulating film 195f at a low temperature, a transistor with good electrical characteristics can be obtained even if the channel length is short.

[0367] After the insulating film 195f is formed, heat treatment can be performed. The heat treatment can sometimes reduce the electrical resistance of the regions 108P and 108Q. The above description can be referred to for the heat treatment, and detailed description thereof will be omitted. Note that if the temperature of the heat treatment is too high (for example, 500° C. or higher), impurities may diffuse into the channel formation region, which may result in degradation of the electrical characteristics and reliability of the transistor.

[0368] Note that this heat treatment does not necessarily have to be performed. Alternatively, the heat treatment may be omitted and may serve as a heat treatment to be performed in a later step. Furthermore, if there is a process in a later step in which heat is applied (for example, a film formation step), this heat treatment may serve as the heat treatment.

[0369] Next, portions of the insulating films 195f and 106f are removed to form openings 147a and 147b that reach the regions 108P and 108Q (FIG. 18D). This forms the insulating layers 195 and 106. The openings 147a and 147b can be formed by, for example, dry etching.

[0370] Subsequently, conductive layers 112a and 112b are formed to cover the openings 147a and 147b (FIG. 18E).

[0371] Subsequently, an insulating layer 218 is formed over the insulating layer 195, the conductive layer 112a, and the conductive layer 112b (FIGS. 2B and 2C). The insulating layer 218 can be formed by a PECVD method.

[0372] Through the above steps, the semiconductor device 10A of one embodiment of the present invention can be manufactured.

[0373] 19A to 22B, a cross-sectional view taken along dashed dotted line A1-A2 and a cross-sectional view taken along dashed dotted line B1-B2 shown in FIG.

[0374] First, the insulating layer 109 is formed over the substrate 102. The insulating layer 109 can be formed by a sputtering method or a PECVD method.

[0375] Next, a conductive film to be the conductive layer 212a is formed over the insulating layer 109 and processed to form the conductive layer 212a (FIG. 19A). The conductive film can be formed by a sputtering method.

[0376] Subsequently, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 212a (FIG. 19B).

[0377] The insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to form the insulating film 110bf without exposing the surface of the insulating film 110af to the atmosphere. This can prevent impurities from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic substances. For example, after forming the insulating film 110af, it is preferable to form the insulating film 110bf consecutively using the same device.

[0378] The substrate temperature during deposition of the insulating film 110af and the insulating film 110bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, further preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature during deposition of the insulating film 110af and the insulating film 110bf within the above-mentioned range, the amount of impurities (e.g., water and hydrogen) released from the insulating film 110af and the insulating film 110bf can be reduced, and diffusion of the impurities into the semiconductor layer 208 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0379] Since the insulating films 110af and 110bf are formed before the semiconductor layer 208, there is no need to worry about oxygen being desorbed from the semiconductor layer 208 due to heat applied when the insulating films 110af and 110bf are formed.

[0380] After the insulating films 110af and 110bf are formed, heat treatment can be performed. By performing the heat treatment, impurities (for example, water and hydrogen) can be removed from the insulating films 110af and the insulating films 110bf and from their surfaces.

[0381] After the insulating film 110bf is formed, oxygen can be supplied to the insulating film 110bf. The above description can be referred to for the method of supplying oxygen.

[0382] After the insulating film 110bf is formed, nitrogen can be supplied to the insulating film 110bf. The nitrogen supply method can be referred to the description of the oxygen supply method described above. As a nitrogen supply method, plasma treatment in an atmosphere containing nitrogen can be suitably used. For example, nitrogen, dinitrogen monoxide (N ２ O), and nitrogen dioxide (NO ２ The amount of nitrogen supplied can be adjusted by, for example, the power and processing time in the plasma processing.

[0383] In the insulating layer (here, the insulating film 110bf or the later insulating layer 110b), nitrogen reacts with oxygen to form nitrogen oxide (NO Ｘ , X is a real number greater than 0). ２ O, NO and NO ２ In the insulating layer, the nitrogen oxide forms a level, which is located within the band gap of the metal oxide. ２ The transition level at which the charge of the indium oxide changes between a 0 state and a -1 state is located within the band gap of indium oxide. Therefore, when nitrogen oxide diffuses to the interface between the insulating layer and the semiconductor layer having the metal oxide or near the interface, the level traps electrons. As a result, the trapped electrons remain at the interface between the insulating layer and the semiconductor layer or near the interface, and the threshold voltage of the transistor can be increased in the positive direction. This allows a normally-off transistor to be obtained, resulting in a semiconductor device with low power consumption.

[0384] Increasing the amount of nitrogen oxide can increase the threshold voltage to the positive side. However, if the amount of nitrogen oxide is too large, the threshold voltage may fluctuate greatly when a positive potential (positive bias) is applied to the gate of the transistor, which may result in reduced reliability. Therefore, it is preferable to use a nitrogen oxide amount within a range that does not affect reliability.

[0385] The amount of nitrogen oxides can be evaluated, for example, by measuring the amount of desorption in thermal desorption spectrometry (TDS) or the amount of electron spin in electron spin resonance (ESR). In TDS, NO (m / z (also referred to as mass-to-charge ratio) = 30), N ２ O (m / z=44), and NO ２ The amount of NO (m / z = 46) desorbed can be evaluated. ２ In some cases, it may be difficult to quantify the amount of NO and N released. ２ By evaluating the amount of O released, ２ In ESR, the amount of NO can be evaluated. ２ Since the N atom has 7 electrons and the O atom has 8 electrons, the ESR signal derived from NO ２ The molecule has an open-shell structure. Therefore, the neutral NO ２ Since the molecule has a lone electron, it can be measured by ESR. １４ Since N has a nuclear spin of 1, １４ The peak of the ESR signal related to N is split into three. At this time, the split width of the ESR signal is the hyperfine coupling constant.

[0386] The order of the treatment for supplying oxygen and the treatment for supplying nitrogen is not particularly limited. Oxygen can be supplied after nitrogen is supplied. Nitrogen can also be supplied after oxygen is supplied. Alternatively, oxygen and nitrogen can be supplied in the same treatment. For example, oxygen and nitrogen can be supplied by performing a plasma treatment in an atmosphere containing nitrogen and oxygen. For example, dinitrogen monoxide (N２ By carrying out a plasma treatment using nitrogen oxides, nitrogen oxides can be efficiently produced, which is preferable.

[0387] After the insulating film 110bf is formed, the plasma treatment can be performed without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can improve productivity. Specifically, after the insulating film 110bf is formed in the PECVD apparatus, N ２ O plasma treatment can be performed.

[0388] Next, it is preferable to form a film 139 on the insulating film 110bf (FIG. 19D). In FIG. 19C, the solid arrows schematically show how oxygen is supplied to the insulating film 110bf. The above description of the film 139 can be referred to.

[0389] Heat treatment is preferably performed after the film 139 is formed. By performing heat treatment after the film 139 is formed, oxygen can be effectively supplied from the film 139 to the insulating film 110bf. For the heat treatment, refer to the above description.

[0390] After the film 139 is formed or after the above-described heat treatment, oxygen can be further supplied to the insulating film 110bf through the film 139. The above description can be referred to for the method of supplying oxygen.

[0391] Next, the film 139 is removed ( FIG. 19E ). There is no particular limitation on the method for removing the film 139, but wet etching is preferably used. By using wet etching, etching of the insulating film 110bf can be suppressed when removing the film 139. This prevents the thickness of the insulating film 110bf from becoming thin, and allows the thickness of the insulating layer 110b to be made uniform.

[0392] For the treatment of supplying oxygen to the insulating film 110bf, the description of the treatment of supplying oxygen to the insulating film 106f can be referred to.

[0393] Next, an insulating film 110cf that will become the insulating layer 110c and an insulating film 110ef that will become the insulating layer 110e are formed on the insulating film 110bf ( FIG. 20A ). The description of the formation of the insulating film 110cf and the insulating film 110ef can be referred to, and therefore detailed description thereof will be omitted.

[0394] Next, a conductive film 212bf that will become the conductive layer 212b is formed on the insulating film 110ef (FIG. 20B). The conductive film 212bf can be formed by a sputtering method.

[0395] Next, the conductive film 212bf is processed to form a conductive layer 212b (FIG. 20C). The conductive layer 212b will later become the conductive layer 212b. For example, wet etching can be suitably used to form the conductive layer 212b.

[0396] Subsequently, a part of the conductive layer 212b is removed to form the conductive layer 212b having the opening 143. The conductive layer 212b can be preferably formed by wet etching.

[0397] Subsequently, parts of the insulating films 110af, 110bf, and 110cf are removed to form the insulating layer 110 having an opening 141 ( FIG. 20D ). The opening 141 is provided in a region overlapping with the opening 143. The formation of the opening 141 exposes the conductive layer 212a. The insulating layer 110 can be preferably formed by dry etching.

[0398] The opening 141 can be formed using, for example, the resist mask used to form the opening 143. Specifically, a resist mask is formed over the conductive layer 212b, part of the conductive layer 212b is removed using the resist mask to form the opening 143, and part of the insulating films 110af, 110bf, and 110cf is removed using the resist mask to form the opening 141. The opening 141 can also be formed using a resist mask different from the resist mask used to form the opening 143.

[0399] Subsequently, a metal oxide film 208f to be the semiconductor layer 208 is formed so as to cover the openings 141 and 143 (FIG. 21A). The metal oxide film 208f is provided in contact with the upper and side surfaces of the conductive layer 212b, the upper and side surfaces of the insulating layer 110, and the upper surface of the conductive layer 212a.

[0400] For the formation of the metal oxide film 208f, the description of the metal oxide film 108f can be referred to.

[0401] Before forming the metal oxide film 208f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２ By performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO), oxygen can be supplied to the insulating layer 110. When plasma treatment is performed in an atmosphere containing nitrous oxide gas, oxygen can be supplied while organic substances on the surface of the insulating layer 110 are suitably removed. After such treatment, it is preferable to form a metal oxide film 208f successively without exposing the surface of the insulating layer 110 to the air.

[0402] Next, the metal oxide film 208f is processed into an island shape to form a metal oxide layer 208F (FIG. 21B). For the formation of the metal oxide layer 208F, the description regarding the formation of the metal oxide layer 108F can be referred to.

[0403] Subsequently, heat treatment is performed. The heat treatment crystallizes the metal oxide layer 208F, and the semiconductor layer 208 is formed ( FIG. 21C ). The heat treatment can reduce defects in the semiconductor layer 208. Furthermore, the heat treatment can remove hydrogen and water contained in the semiconductor layer 208 or adsorbed on the surface thereof. For the heat treatment, the description of the heat treatment for the metal oxide layer 108F can be referred to.

[0404] By the heat treatment, oxygen can also be supplied from the insulating layer 110b to the metal oxide film 208f or the semiconductor layer 208. In this case, it is more preferable to perform the heat treatment before processing into the semiconductor layer 208.

[0405] Note that the heat treatment is not performed here, and can be performed in a subsequent step. In addition, a subsequent step in which heat is applied (for example, a film formation step) may also serve as the heat treatment.

[0406] Next, the insulating layer 206 is formed to cover the semiconductor layer 208, the conductive layer 212b, and the insulating layer 110 ( FIG. 22A ). The insulating layer 206 can be formed by, for example, a PECVD method, a sputtering method, or an ALD method. For the formation of the insulating layer 206, the description of the insulating film 106f and the insulating layer 106 can be referred to.

[0407] Before forming the insulating layer 206, plasma treatment can be performed on the surface of the semiconductor layer 208. The plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 208. Therefore, impurities at the interface between the semiconductor layer 208 and the insulating layer 206 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable when the surface of the semiconductor layer 208 is exposed to the air during the period from the formation of the semiconductor layer 208 to the formation of the insulating layer 206. For details about the plasma treatment, refer to the above description.

[0408] Subsequently, a conductive layer 204 is formed over the insulating layer 206 (FIG. 22B). The conductive film that becomes the conductive layer 204 can be preferably formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method.

[0409] Subsequently, an insulating layer 218 is formed on the insulating layer 206 and the conductive layer 204 (FIGS. 10A and 10B).

[0410] Through the above steps, the semiconductor device 20B of one embodiment of the present invention can be manufactured.

[0411] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0412] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0413] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (IGZO) and zinc oxide.

[0414] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 23A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 23B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0415] As shown by the arrows in Figure 23B, IGZO tends to have higher hole mobility as the carrier concentration increases. On the other hand, as shown by the arrows in Figure 23A, indium oxide tends to have higher hole mobility as the carrier concentration decreases (see Non-Patent Document 2). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 23A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 23A.

[0416] 23A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10１４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0417] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the electrical resistivity can be increased to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0418] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of such an element include titanium, aluminum, tantalum, tungsten, tin, silicon, germanium, zirconium, hafnium, antimony, and magnesium. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0419] In this way, indium oxide, a region with a low carrier concentration is used as a channel formation region of a transistor, and a region with a high carrier concentration is used as a source region and a drain region of the transistor. In other words, indium oxide is an oxide capable of valence electron control. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that is not usually conceived. By using this technical concept, a transistor with high mobility, low off-current, and normally off operation can be realized.

[0420] Next, an indium oxide film to be used in a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains).

[0421] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 23C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0422] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0423] As shown in FIG. 23C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or, as mentioned above, reacts with oxygen contained in the film and is released as water molecules.

[0424] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0425] Single crystal indium oxide (here, In ２ O ３), and single-crystal silicon (Si) have effective masses shown in Table 1. As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide for a transistor, a transistor with high field-effect mobility and a transistor with high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to provide a transistor with higher field-effect mobility and lower off-state current than a transistor using silicon in a channel formation region (hereinafter also referred to as a Si transistor).

[0426]

[0427] It is preferable to provide a seed layer so as to be in contact with at least a part of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals whose lattice constant is small (also called lattice mismatch) with that of indium oxide. This can improve the crystallinity of the indium oxide film.

[0428] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa=((L １ -L ２ ) / L ２ ) × 100, where L １is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0429] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0430] Here, the crystal of indium oxide has, for example, a cubic structure (bixbyite type), and is YSZ (Zr ０．９ Y ０．１ O １．９５ The indium oxide crystal has, for example, a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0431] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ type structure, or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0432] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0433] Embodiment 3 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0434] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used as a display unit for electronic devices having relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0435] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type AR device.

[0436] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter also referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0437] The display device of this embodiment may have a function as a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection target such as a finger can be applied to the display device.

[0438] Examples of sensor types include a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0439] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0440] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that an in-cell touch panel is a type in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element and an opposing substrate.

[0441] <Configuration Example 1 of Display Device> FIG. 24 shows a perspective view of a display device 50A.

[0442] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 24, the substrate 152 is indicated by a dashed line.

[0443] The display device 50A includes a display portion 162, a connection portion 140, a circuit portion 164, a conductive layer 165, etc. Fig. 24 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 24 can also be said to be a display module including the display device 50A, an IC, and an FPC.

[0444] The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140. FIG. 24 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162. The connection portion 140 connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

[0445] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0446] Various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexer circuit, and a logic circuit can be used for the circuit portion 164. A transistor, a capacitor, or the like can be used for the circuit portion 164. The transistors included in the circuit portion 164 can be formed in the same process as the transistors included in the pixel circuit.

[0447] The conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the conductive layer 165 from the outside through the FPC 172 or are input to the conductive layer 165 from the IC 173.

[0448] 24 shows an example in which an IC 173 is provided on a substrate 151 by a COG method. The IC 173 may be, for example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit. The display device 50A and the display module may be configured without an IC. The IC may also be mounted on an FPC by a COF method or the like.

[0449] The semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 162 and the circuit portion 164 of the display device 50A. An oxide semiconductor (OS) can be suitably used for a channel formation region of a transistor included in the display device. By using an OS transistor, the display device can have low power consumption. Furthermore, the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all of the transistors included in the display device can be OS transistors. By using OS transistors for all of the transistors included in the display device in this manner, an effect of reducing manufacturing costs can be obtained.

[0450] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0451] The display section 162 is an area in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 201. Fig. 24 shows an enlarged view of one pixel 201.

[0452] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0453] 24 includes a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. Note that the number of sub-pixels included in one pixel is not particularly limited.

[0454] Each of the sub-pixels 11R, 11G, and 11B includes a display element and a pixel circuit that controls the driving of the display element.

[0455] Various elements can be used as the display element, including, for example, a liquid crystal element and a light-emitting element. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements that employ a microcapsule method, an electrophoresis method, an electrowetting method, or an electronic liquid powder (registered trademark) method, etc. Furthermore, a QLED (Quantum-dot LED) that uses a light source and color conversion technology using quantum dot materials may also be used.

[0456] Examples of quantum dot materials used in the color conversion layer include Group 14 elements, Group 15 elements, Group 16 elements, compounds consisting of multiple Group 14 elements, compounds of an element belonging to Groups 4 to 14 and a Group 16 element, compounds of a Group 2 element and a Group 16 element, compounds of a Group 13 element and a Group 15 element, compounds of a Group 13 element and a Group 17 element, compounds of a Group 14 element and a Group 15 element, compounds of a Group 11 element and a Group 17 element, iron oxides, titanium oxides, chalcogenide spinels, and various semiconductor clusters.

[0457] Specifically, cadmium selenide, cadmium sulfide, cadmium telluride, zinc selenide, zinc oxide, zinc sulfide, zinc telluride, mercury sulfide, mercury selenide, mercury telluride, indium arsenide, indium phosphide, gallium arsenide, gallium phosphide, indium nitride, gallium nitride, indium antimonide, gallium antimonide, aluminum phosphide, aluminum arsenide, aluminum antimonide, lead selenide, lead telluride, lead sulfide, indium selenide, telluride Indium, indium sulfide, gallium selenide, arsenic sulfide, arsenic selenide, arsenic telluride, antimony sulfide, antimony selenide, antimony telluride, bismuth sulfide, bismuth selenide, bismuth telluride, silicon, silicon carbide, germanium, tin, selenium, tellurium, boron, carbon, phosphorus, boron nitride, boron phosphide, boron arsenide, aluminum nitride, aluminum sulfide, barium sulfide, barium selenide, barium telluride, calcium sulfide, calcium selenide Calcium, calcium telluride, beryllium sulfide, beryllium selenide, beryllium telluride, magnesium sulfide, magnesium selenide, germanium sulfide, germanium selenide, germanium telluride, tin sulfide, tin selenide, tin telluride, lead oxide, copper fluoride, copper chloride, copper bromide, copper iodide, copper oxide, copper selenide, nickel oxide, cobalt oxide, cobalt sulfide, iron oxide, iron sulfide, manganese oxide, molybdenum sulfide, vanadium oxide, tungsten oxide, tungsten oxide Examples of the quantum dots include tantalum, titanium oxide, zirconium oxide, silicon nitride, germanium nitride, aluminum oxide, barium titanate, a compound of selenium, zinc, and cadmium, a compound of indium, arsenic, and phosphorus, a compound of cadmium, selenium, and sulfur, a compound of cadmium, selenium, and tellurium, a compound of indium, gallium, and arsenic, a compound of indium, gallium, and selenium, a compound of indium, selenium, and sulfur, a compound of copper, indium, and sulfur, and combinations thereof. Also, so-called alloy-type quantum dots, whose composition is expressed in any ratio, may be used.

[0458] Examples of quantum dot structures include core, core-shell, and core-multishell types. Furthermore, quantum dots have a high proportion of surface atoms, making them highly reactive and prone to aggregation. To prevent quantum dot aggregation and improve their dispersibility in a dispersion medium, it is preferable that a protective agent be attached to the surface of the quantum dots or that protective groups be provided. This can reduce reactivity and improve electrical stability.

[0459] Since the band gap of quantum dots increases as their size decreases, their size can be adjusted appropriately to obtain light of the desired wavelength. As the size decreases, the emission of quantum dots shifts toward the blue side, i.e., toward higher energy, so by changing the size of the quantum dots, the emission wavelength can be adjusted across the wavelength ranges of the ultraviolet, visible, and infrared spectrums. The size (diameter) of the quantum dots is, for example, 0.5 nm or more and 20 nm or less, preferably 1 nm or more and 10 nm or less. Furthermore, the narrower the size distribution of the quantum dots, the narrower the emission spectrum, and the more excellent the color purity of the light emitted. Furthermore, the shape of the quantum dots is not particularly limited and may be spherical, rod-shaped, disc-shaped, or other shapes. Quantum rods, which are rod-shaped quantum dots, have the function of emitting directional light.

[0460] The color conversion layer can be formed by a droplet ejection method (for example, an inkjet method), a coating method, an imprint method, various printing methods (screen printing, offset printing), etc. A color conversion film such as a quantum dot film may also be used.

[0461] When processing a film to be used as a color conversion layer, it is preferable to use a photolithography method. Photolithography methods include a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is removed, and a method in which a photosensitive thin film is formed, and then the thin film is processed into a desired shape by exposure and development. For example, an island-shaped color conversion layer can be formed by forming a thin film using a material in which quantum dots are mixed into a photoresist, and processing the thin film using a photolithography method.

[0462] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0463] Examples of modes that can be used in display devices using liquid crystal elements include vertical alignment (VA) mode, Fringe Field Switching (FFS) mode, In-Plane-Switching (IPS) mode, Twisted Nematic (TN) mode, Axially Symmetric Aligned Micro-cell (ASM) mode, Optically Compensated Birefringence (OCB) mode, Ferroelectric Liquid Crystal (FLC) mode, Anti-Ferroelectric Liquid Crystal (AFLC) mode, and Electrically Compensated Birefringence (ECB) mode. Examples of the VA mode include a Multi-Domain Vertical Alignment (MVA) mode, a Patterned Vertical Alignment (PVA) mode, and an Advanced Super View (ASV) mode.

[0464] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, and the like, depending on the conditions. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material, and the type can be selected depending on the mode or design to be applied.

[0465] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), semiconductor lasers, etc. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0466] Examples of light-emitting substances that the light-emitting element has include fluorescent substances (fluorescent materials), phosphorescent substances (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF materials), and inorganic compounds (quantum dot materials, etc.).

[0467] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0468] One of a pair of electrodes included in the light-emitting element functions as an anode, and the other electrode functions as a cathode.

[0469] Note that the display device of one embodiment of the present invention may be any of a top-emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type that emits light toward a substrate on which a light-emitting element is formed, and a dual-emission type that emits light to both sides.

[0470] The semiconductor device of one embodiment of the present invention includes a transistor with high on-state current. An oxide semiconductor (OS) can be preferably used for a channel formation region of the transistor, thereby enabling the transistor to have low off-state current. The semiconductor device of one embodiment of the present invention can be preferably used for one or both of the display portion 162 and the circuit portion 164. Furthermore, the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all of the transistors included in the display device can be OS transistors. By using OS transistors for all of the transistors included in the display device, it is possible to reduce manufacturing costs.

[0471] Figure 25A shows an example of a cross section of the display device 50A when cutting a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion.

[0472] 25A includes transistors 205D, 205R, 205G, and 205B, a light-emitting element 130R, a light-emitting element 130G, and a light-emitting element 130B between a substrate 151 and a substrate 152. The light-emitting element 130R is a display element included in the sub-pixel 11R that emits red light, the light-emitting element 130G is a display element included in the sub-pixel 11G that emits green light, and the light-emitting element 130B is a display element included in the sub-pixel 11B that emits blue light.

[0473] The display device 50A employs an SBS structure, which allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in the selection of materials and configurations and facilitating improvements in brightness and reliability.

[0474] The display device 50A is a top emission type, which allows transistors and the like to be arranged overlapping the light emitting region of the light emitting element, thereby enabling a higher pixel aperture ratio than a bottom emission type.

[0475] The transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B are all formed over a substrate 151. These transistors can be manufactured using the same process. Figure 25A shows a configuration example in which the transistor 200 shown in Figure 6B and the like is used as the transistor 205R, the transistor 205G, the transistor 205B, and the transistor 205D. Note that the transistors 205D, the transistor 205R, the transistor 205G, and the transistor 205B may have different structures.

[0476] In this embodiment, an example in which OS transistors are used as the transistors 205D, 205R, 205G, and 205B will be described. The transistors according to one embodiment of the present invention can be used as the transistors 205D, 205R, 205G, and 205B. That is, the display device 50A includes the transistor according to one embodiment of the present invention in both the display portion 162 and the circuit portion 164. By using the transistor according to one embodiment of the present invention in the display portion 162, the pixel size can be reduced, and a high-resolution display device can be obtained. Furthermore, by using the transistor according to one embodiment of the present invention in the circuit portion 164, the area occupied by the circuit portion 164 can be reduced, and the frame can be narrowed. The description of the previous embodiment can be referred to for the transistor according to one embodiment of the present invention.

[0477] Specifically, the transistors 205D, 205R, 205G, and 205B each include a conductive layer 204 that functions as a gate, an insulating layer 206 that functions as a gate insulating layer, conductive layers 212a and 212b that function as a source and a drain, a semiconductor layer 208 containing metal oxide, and an insulating layer 110. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film.

[0478] Note that the transistor included in the display device of this embodiment is not limited to the transistor of one embodiment of the present invention. For example, the display device may include a combination of the transistor of one embodiment of the present invention and a transistor having another structure.

[0479] The display device of this embodiment may include, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor. The transistor included in the display device of this embodiment may be either a top-gate transistor or a bottom-gate transistor. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0480] The display device of this embodiment may have a Si transistor.

[0481] To increase the emission luminance of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between its source and drain than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

[0482] When a transistor operates in a saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage, thereby controlling the amount of current flowing to a light-emitting element. This allows a pixel circuit to have a larger number of gray levels.

[0483] In terms of the saturation of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to a light-emitting element, even when the current-voltage characteristics of the light-emitting element vary. In other words, when an OS transistor operates in a saturation region, the change in the source-drain current is small even when the source-drain voltage is changed, and therefore the light-emitting luminance of the light-emitting element can be stabilized.

[0484] The transistors included in the circuit portion 164 and the transistors included in the display portion 162 may have the same structure or different structures. The transistors included in the circuit portion 164 may all have the same structure or may have two or more types. Similarly, the transistors included in the display portion 162 may all have the same structure or may have two or more types.

[0485] All the transistors in the display portion 162 may be OS transistors, or all the transistors in the display portion 162 may be Si transistors, or some of the transistors in the display portion 162 may be OS transistors and the rest may be Si transistors. Silicon may be single crystal silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon. Polycrystalline silicon may be low-temperature polysilicon (LTPS), for example. A transistor using LTPS in a channel formation region (hereinafter also referred to as an LTPS transistor) has high field-effect mobility and can operate at high speed.

[0486] For example, by using both an LTPS transistor and an OS transistor in the display portion 162, a display device with low power consumption and high driving capability can be realized. A structure in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO. Note that a more preferable example is a structure in which an OS transistor is used as a transistor that functions as a switch for controlling conduction / non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.

[0487] For example, one of the transistors included in the display portion 162 functions as a transistor for controlling a current flowing to a light-emitting element and can also be called a driving transistor. One of the source and drain of the driving transistor is connected to a pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor as the driving transistor. This can increase the current flowing to the light-emitting element in the pixel circuit.

[0488] On the other hand, another transistor included in the display portion 162 functions as a switch for controlling pixel selection / non-selection and can also be referred to as a selection transistor. The gate of the selection transistor is connected to a gate line, and one of the source and drain is connected to a source line (signal line). An OS transistor is preferably used as the selection transistor. This allows the gradation of a pixel to be maintained even when the frame frequency is significantly low (for example, 1 fps or less). Therefore, power consumption can be reduced by stopping the driver when displaying a still image. Furthermore, by using a transistor with high field-effect mobility (for example, an IO transistor) as the selection transistor, the frame frequency (also referred to as a frame rate) during display can be increased, resulting in a display device with high display quality.

[0489] Tables 2 and 3 show a comparison of configurations that can be applied to the backplane of a display device.

[0490] Table 2 shows a structure using an LTPS transistor (referred to as "LTPS"), a structure using LTPO (referred to as "LTPO"), a structure using a transistor having IGZO in a semiconductor layer (referred to as "IGZO"), and a structure using an OS transistor with high field-effect mobility (referred to as "High-μ OS"). Examples of High-μ OS include transistors whose semiconductor layer contains a material with a high indium content, and a typical example is a transistor using crystalline indium oxide.

[0491]

[0492] Table 2 shows high resolution, high luminance, high frame rate, narrow bezel, low power consumption, and low cost. As shown in Table 2, compared to LTPS, LTPO, IGZO, and High-μ OS using metal oxides can achieve high resolution and low power consumption. Furthermore, IGZO and High-μ OS do not require a laser crystallization process for the semiconductor layer, and can therefore be produced at low cost. In particular, High-μ OS can achieve high luminance, high frame rate operation, and a narrow bezel.

[0493]

[0494] Table 3 shows a configuration using an LTPS transistor (denoted as "LTPS"), a configuration using LTPO (denoted as "LTPO"), a configuration using a transistor having IGZO in a semiconductor layer (denoted as "IGZO"), and a configuration using a transistor having crystalline indium oxide in a semiconductor layer (denoted as "Crystal IO"). Note that in Table 3, a check mark means applicable, and NA means not applicable (Not Applicable).

[0495] Table 3 shows the electrical characteristics of a transistor (FET characteristics), including the channel length, field-effect mobility, reliability, on-state current, and off-state current, at which good electrical characteristics can be obtained. As shown in Table 3, compared to LTPS, LTPO, IGZO, and Crystal IO, which use metal oxides, have very low off-state currents. Furthermore, IGZO and Crystal IO can achieve normally-off characteristics even in transistors with a short channel length of 2 μm. In particular, Crystal IO has a field-effect mobility of typically 50 cm ２ / Vs or more 100cm ２ / Vs or less. Crystal IO also has an on-current equal to or greater than that of LTPS, and is highly reliable.

[0496] Table 3 shows, as productivity, the size of the glass substrate applicable to mass production (Substrate size), whether or not a laser crystallization process of the semiconductor layer is performed (Laser crystallization), and the number of masks (Compared with LTPS). IGZO and Crystal IO do not require a laser crystallization process and can be applied to large (e.g., G8.5) glass substrates. Furthermore, compared to LTPO, IGZO and Crystal IO require fewer masks, which allows for fewer processes.

[0497] Table 3 shows the display panel specifications, including power consumption, bezel, high frame rate driving, and low frame rate driving. Crystal IO has a large on-current, which allows for narrow bezels and high frame rate driving. Furthermore, Crystal IO has a small off-current, which allows for low power consumption and low frame rate driving.

[0498] As described above, a transistor including crystalline indium oxide can achieve excellent electrical characteristics and high reliability. Furthermore, by using a transistor including crystalline indium oxide, a display device with high performance and high display quality can be obtained. Furthermore, productivity of the display device can be improved. Therefore, a transistor including crystalline indium oxide can be suitably used for the backplane of a display device.

[0499] An insulating layer 218 is provided to cover the transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided over the insulating layer 218. The above description of the insulating layer 218 can be referred to.

[0500] The insulating layer 235 preferably functions as a planarization layer, and is preferably an organic insulating film. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins. The insulating layer 235 may also have a laminated structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This prevents recesses from being formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Alternatively, recesses may be formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Note that the pixel electrodes 111R, 111G, and 111B may be collectively referred to as pixel electrodes 111.

[0501] On the insulating layer 235, the light emitting elements 130R, 130G, and 130B are provided.

[0502] The light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in Fig. 25A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0503] The light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in Fig. 25A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0504] The light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in Fig. 25A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0505] 25A, the EL layers 113R, 113G, and 113B are all shown with the same thickness, but this is not limited thereto. The EL layers 113R, 113G, and 113B may have different thicknesses. For example, it is preferable to set the thickness of the EL layers 113R, 113G, and 113B so that the optical path length is such that the light emitted by each layer is intensified. This allows for a microcavity structure to be realized, and the color purity of the light emitted from each light-emitting element to be improved.

[0506] The pixel electrode 111R is connected to the conductive layer 212b of the transistor 205R in an opening provided in the insulating layer 206, the insulating layer 218, and the insulating layer 235. Similarly, the pixel electrode 111G is connected to the conductive layer 212b of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 212b of the transistor 205B.

[0507] Ends of each of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237. The insulating layer 237 functions as a partition wall. The insulating layer 237 can be formed in a single layer structure or a stacked layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the materials that can be used for the insulating layer 218 and the insulating layer 235 can be used for the insulating layer 237. The insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.

[0508] The insulating layer 237 is provided at least in the display unit 162. The insulating layer 237 may be provided not only in the display unit 162 but also in the connection unit 140 and the circuit unit 164. Furthermore, the insulating layer 237 may be provided up to the edge of the display device 50A.

[0509] The common electrode 115 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 115 shared by the plurality of light-emitting elements is connected to a conductive layer 123 provided in the connection portion 140. For the conductive layer 123, it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.

[0510] In a display device according to one embodiment of the present invention, a conductive film that transmits visible light is preferably used for the pixel electrode and the common electrode, which are electrodes from which light is extracted, and a conductive film that reflects visible light is preferably used for the electrode from which light is not extracted.

[0511] A conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0512] Materials for forming the pair of electrodes of a light-emitting element can include metals, alloys, electrically conductive compounds, and mixtures thereof. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these metals in combination. Other examples of such materials include ITO, ITSO, indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Other examples of such materials include aluminum alloys, such as an aluminum-nickel-lanthanum alloy (Al-Ni-La), and silver-magnesium alloys and silver-palladium-copper alloys (Ag-Pd-Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not exemplified above, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these, and graphene.

[0513] The light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode). By having the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0514] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the electrical resistivity of these electrodes is 1×10 −２ Preferably, it is Ωcm or less.

[0515] The EL layers 113R, 113G, and 113B are each provided in an island shape. In FIG. 25A , the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap. When forming island-shaped EL layers using a fine metal mask, the ends of adjacent EL layers may overlap as shown in FIG. 25A , but this is not limited to this. That is, adjacent EL layers may not overlap but may be spaced apart. Furthermore, the display device may have both regions where adjacent EL layers overlap and regions where adjacent EL layers do not overlap but are spaced apart.

[0516] Each of the EL layers 113R, 113G, and 113B includes at least a light-emitting layer. The light-emitting layer includes one or more light-emitting materials. As the light-emitting material, a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a material that emits near-infrared light can also be used as the light-emitting material.

[0517] The light-emitting material may include a fluorescent material, a phosphorescent material, a TADF material, and a quantum dot material.

[0518] Quantum dot materials include colloidal quantum dots, alloy quantum dots, core-shell quantum dots, and core quantum dots. Quantum dot materials containing elements from groups 2 and 16, 13 and 15, 13 and 17, 11 and 17, or 14 and 15 can also be used. Quantum dot materials containing elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), and aluminum (Al) can also be used.

[0519] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole-transport properties (hole-transport material) and a substance with high electron-transport properties (electron-transport material) can be used. Furthermore, as the one or more organic compounds, a bipolar substance (a substance with high electron-transport properties and hole-transport properties) or a TADF material can be used.

[0520] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. This configuration allows efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, energy transfer becomes smooth and light emission can be achieved efficiently. This configuration allows for high efficiency, low-voltage operation, and a long lifetime of the light-emitting element.

[0521] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a hole-transporting material (hole-transporting layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing an electron-transporting material (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer).In addition, the EL layer may include one or both of a bipolar substance and a TADF material.

[0522] The light-emitting element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting element can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0523] The light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. The tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer injects electrons into one of the two light-emitting units and holes into the other. The tandem structure allows the light-emitting element to emit light with high brightness. Furthermore, the tandem structure can reduce the current required to achieve the same brightness compared to a single structure, thereby improving reliability. The tandem structure can also be called a stack structure.

[0524] In Figure 25A, when light-emitting elements with a tandem structure are used, it is preferable that EL layer 113R has a structure having multiple light-emitting units that emit red light, EL layer 113G has a structure having multiple light-emitting units that emit green light, and EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0525] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. For example, a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements. In FIG. 25A , the space between the substrates 152 and 151 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided so as not to overlap with the light-emitting elements. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 142.

[0526] The protective layer 131 is preferably provided in at least the display portion 162 and is provided so as to cover the entire display portion 162. The protective layer 131 is preferably provided so as to cover not only the display portion 162 but also the connection portion 140 and the circuit portion 164. The protective layer 131 is also preferably provided up to the edge of the display device 50A. Meanwhile, in the connection portion 197, a region where the protective layer 131 is not provided is generated in order to connect the FPC 172 and the conductive layer 166.

[0527] By providing the protective layer 131 on the light emitting elements 130R, 130G, and 130B, the reliability of the light emitting elements can be improved.

[0528] The protective layer 131 can have a single layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 131 does not matter. The protective layer 131 can be formed using at least one of an insulating film, a semiconductor film, and a conductive film.

[0529] The protective layer 131 has an inorganic film, which prevents the common electrode 115 from being oxidized, suppresses impurities (moisture, oxygen, etc.) from entering the light-emitting element, and so on, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.

[0530] The protective layer 131 preferably includes one or more inorganic insulating layers. The protective layer 131 can be made of a material that can be used for the insulating layer 110. In particular, the protective layer 131 is preferably made of a nitride or a nitride oxide, and more preferably made of a nitride.

[0531] The protective layer 131 may be an inorganic film containing ITO, In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, IGZO, or the like. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 115. The inorganic film may further contain nitrogen.

[0532] When light emitted from the light-emitting element is extracted through the protective layer 131, it is preferable that the protective layer 131 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0533] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 131. By using such a stacked structure, impurities (water, oxygen, etc.) can be prevented from entering the EL layer side.

[0534] Furthermore, the protective layer 131 may have an organic film. For example, the protective layer 131 may have both an organic film and an inorganic film. Examples of organic films that can be used for the protective layer 131 include the organic insulating films that can be used for the insulating layer 235.

[0535] A connection portion 197 is provided in a region of the substrate 151 where the substrate 152 does not overlap. In the connection portion 197, the conductive layer 165 is connected to the FPC 172 via the conductive layer 166 and the connection layer 242. FIG. 25A illustrates an example in which the conductive layer 165 is a conductive layer obtained by processing the same conductive film as the conductive layer 212b. An example in which the conductive layer 166 is a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B is illustrated. The connection portion between the conductive layer 165 and the conductive layer 166 can have the same structure as the connection portion between the pixel electrode 111 and the conductive layer 212b. Specifically, FIG. 25A illustrates an example in which an opening is provided above the conductive layer 165, and the conductive layer 166 is in contact with the upper surface of the conductive layer 165 through the opening. The conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection portion 197 and the FPC 172 to be connected via the connection layer 242 .

[0536] The display device 50A is a top-emission type. Light emitted by the light-emitting elements is emitted toward the substrate 152. The substrate 152 is preferably made of a material that is highly transparent to visible light. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0537] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 facing the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, in the circuit section 164, and the like.

[0538] A colored layer such as a color filter may be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. When a color filter is provided over the light-emitting element, the color purity of light emitted from the pixel can be increased.

[0539] The colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges. For example, a red (R) color filter that transmits light in the red wavelength range, a green (G) color filter that transmits light in the green wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range can be used. Each colored layer can be made of one or more of a metal material, a resin material, a pigment, and a dye. The colored layers are formed at desired positions by a printing method, an inkjet method, an etching method using photolithography, or the like.

[0540] Various optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 151). Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be arranged on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO ｘ The surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ ), polyester-based materials, or polycarbonate-based materials may also be used. Note that it is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0541] The substrate 151 and the substrate 152 can each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. When a flexible material is used for the substrate 151 and the substrate 152, the flexibility of the display device can be increased, and a flexible display can be realized. Furthermore, a polarizing plate may be used for at least one of the substrates 151 and 152.

[0542] Substrate 151 and substrate 152 can be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of substrate 151 and substrate 152 can be made of glass having a thickness sufficient to provide flexibility.

[0543] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has low birefringence (it can also be said that the amount of birefringence is small). Examples of films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0544] The adhesive layer 142 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as epoxy resin, is preferable. Alternatively, a two-component resin may be used. Alternatively, an adhesive sheet or the like may be used.

[0545] The connection layer 242 may be an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0546] <Configuration Example 2 of Display Device> Figure 25B shows an example of a cross section of the display unit 162 of the display device 50B. The display device 50B differs from the display device 50A mainly in that a light-emitting element having a common EL layer 113 and a colored layer (such as a color filter) are used for each subpixel of each color. The configuration shown in Figure 25B can be combined with the region including the FPC 172, the circuit portion 164, the stacked structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection portion 140, and the end portion configuration shown in Figure 25A. Note that in the following description of the display device, descriptions of parts similar to those of the display device described above may be omitted.

[0547] A display device 50B shown in FIG. 25B includes light-emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.

[0548] The light emitting element 130R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emitted from the light emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0549] The light emitting element 130G has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. Light emitted from the light emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0550] The light emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. Light emitted from the light emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0551] The light-emitting elements 130R, 130G, and 130B each share the EL layer 113 and the common electrode 115. The configuration in which the subpixels of each color are provided with a common EL layer 113 can reduce the number of manufacturing steps compared to the configuration in which the subpixels of each color are provided with different EL layers.

[0552] 25B emit white light. The white light emitted by the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0553] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, light-emitting layers can be selected such that the emission colors of the two light-emitting layers have a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer have a complementary color relationship, a configuration in which the light-emitting element as a whole emits white light can be obtained. Furthermore, when three or more light-emitting layers are used to obtain white light emission, the emission colors of the three or more light-emitting layers can be combined to form a configuration in which the light-emitting element as a whole emits white light.

[0554] The EL layer 113 preferably includes, for example, a light-emitting layer having a light-emitting substance that emits blue light and a light-emitting layer having a light-emitting substance that emits visible light with a wavelength longer than blue. The EL layer 113 preferably includes, for example, a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably includes, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

[0555] A tandem structure is preferably used for the light-emitting element emitting white light. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light, in this order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and red light, and a light-emitting unit that emits blue light, in this order, or the like can be applied. For example, the number of stacked light-emitting units and the order of colors can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, and the number of stacked light-emitting layers in light-emitting unit X and the order of colors can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R. Furthermore, another layer can be provided between the two light-emitting layers.

[0556] By applying a microcavity structure, a light emitting element configured to emit white light may emit light of a specific wavelength such as red, green, or blue that is intensified.

[0557] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in FIG. 25B emit blue light. In this case, the EL layer 113 includes one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. Furthermore, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, a color conversion layer can be provided between the light-emitting element 130R or light-emitting element 130G and the substrate 152 to convert the blue light emitted by the light-emitting element 130R or light-emitting element 130G into light with a longer wavelength, thereby extracting red or green light. The above-mentioned description of the color conversion layer can be referred to. Specifically, the color conversion layer can be formed using the various quantum dot materials described above. Furthermore, it is preferable to provide a colored layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a colored layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. A portion of the light emitted by the light-emitting element may be transmitted directly without being converted by the color conversion layer. By extracting the light that has transmitted through the color conversion layer via the colored layer, light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light emitted by the sub-pixel.

[0558] <Configuration Example 3 of Display Device> A display device 50C shown in FIG. 26 is different from the display device 50A mainly in that it includes a conductive layer 234p, a conductive layer 234a, a conductive layer 234b, and an insulating layer 239.

[0559] An insulating layer 239 is provided over the insulating layer 235, and the light-emitting elements 130R, 130G, and 130B are provided over the insulating layer 239.

[0560] The conductive layer 234p is provided to cover the openings provided in the insulating layer 206, the insulating layer 218, and the insulating layer 235. The conductive layer 234p is in contact with the conductive layer 212b included in the transistor 205R in the openings and is connected to the conductive layer 212b.

[0561] An insulating layer 239 is provided over the conductive layer 234p and the insulating layer 235. The insulating layer 239 can be formed using any of the materials listed for the insulating layer 235.

[0562] The pixel electrode 111R is provided so as to cover an opening provided in the insulating layer 239. The pixel electrode 111R is in contact with the conductive layer 234p in the opening and is connected to the conductive layer 234p. In other words, the pixel electrode 111R is connected to the conductive layer 212b via the conductive layer 234p. The same applies to the pixel electrodes 111G and 111B.

[0563] The conductive layer 234a is provided to cover the openings provided in the insulating layer 206, the insulating layer 218, and the insulating layer 235. The conductive layer 234a is in contact with and connected to the conductive layer 165 in the openings.

[0564] The conductive layer 166 is provided to cover the opening provided in the insulating layer 239. The conductive layer 166 is in contact with and connected to the conductive layer 234a in the opening. That is, the conductive layer 166 is connected to the conductive layer 165 through the conductive layer 234a.

[0565] 26 shows a structure in which the circuit portion 164 includes a conductive layer 234b. Note that the conductive layer 234b can be connected to the transistor 205D.

[0566] The conductive layer 234p, the conductive layer 234a, and the conductive layer 234b each function as a wiring. The conductive layer 234p, the conductive layer 234a, and the conductive layer 234b are provided in a layer different from the conductive layer 212a, the conductive layer 212b, and the conductive layer 204. Therefore, wiring can be arranged in each layer, which increases the degree of freedom in layout and enables the area occupied by the circuit to be reduced.

[0567] The conductive layers 234p, 234a, and 234b can be formed using the same materials as those for the conductive layers 212a, 212b, and 204. The conductive layers 234p, 234a, and 234b can be formed in the same process. For example, conductive films that will become the conductive layers 234p, 234a, and 234b are formed and then processed to form the conductive layers 234p, 234a, and 234b.

[0568] <Configuration Example 4 of Display Device> A display device 50D illustrated in FIG. 27 is different from the display device 50C mainly in that the configuration of the transistor 100A illustrated in FIG. 2B and the like is applied to the transistors 205R, 205G, 205B, and 205D.

[0569] The conductive layer 234p is provided to cover the openings provided in the insulating layer 218 and the insulating layer 235. The conductive layer 234p is in contact with the conductive layer 112b of the transistor 205R in the openings and is connected to the conductive layer 112b. The pixel electrode 111R is connected to the conductive layer 112b through the conductive layer 234p. The same applies to the connection between the pixel electrode 111G and the transistor 205G and the connection between the pixel electrode 111B and the transistor 205B.

[0570] The conductive layer 234a is provided so as to cover the openings provided in the insulating layer 218 and the insulating layer 235. The conductive layer 234a is in contact with the conductive layer 165 in the openings and is connected to the conductive layer 165. The conductive layer 166 is connected to the conductive layer 165 through the conductive layer 234a. Figure 27 shows an example in which the conductive layer 165 is obtained by processing the same conductive film as the conductive layers 112a and 112b.

[0571] By using a TGSA transistor, the parasitic capacitance between the source electrode and the gate electrode and between the drain electrode and the gate electrode can be reduced, and therefore, degradation of display quality due to the parasitic capacitance can be suppressed.

[0572] <Configuration Example 5 of Display Device> A display device 50E shown in FIG. 28 is different from the display device 50C mainly in that the configuration of the transistor 300B shown in FIG. 13B and the like is applied to the transistor 205R, the transistor 205G, the transistor 205B, and the transistor 205D.

[0573] The conductive layer 234p is provided to cover the openings provided in the insulating layers 188, 189, and 235. The conductive layer 234p is in contact with the conductive layer 186b of the transistor 205R in the openings and is connected to the conductive layer 186b. The pixel electrode 111R is connected to the conductive layer 186b through the conductive layer 234p. The same applies to the connection between the pixel electrode 111G and the transistor 205G and the connection between the pixel electrode 111B and the transistor 205B.

[0574] The conductive layer 234a is provided so as to cover the openings provided in the insulating layer 188, the insulating layer 189, and the insulating layer 235. The conductive layer 234a is in contact with the conductive layer 165 in the openings and is connected to the conductive layer 165. The conductive layer 166 is connected to the conductive layer 165 through the conductive layer 234a. Figure 28 shows an example in which the conductive layer 165 is obtained by processing the same conductive film as the conductive layers 186a and 186b.

[0575] By using a BGTC transistor, the number of masks used for manufacturing the transistor can be reduced, which leads to a reduction in the manufacturing cost of the display device.

[0576] <Configuration Example 6 of Display Device> A display device 50F shown in FIG. 29 differs from the display device 50B mainly in that it is a bottom-emission type display device.

[0577] Light emitted from the light-emitting element is emitted toward the substrate 151. A material that is highly transparent to visible light is preferably used for the substrate 151. On the other hand, the light-transmitting property of a material used for the substrate 152 does not matter.

[0578] 29 shows an example in which the light-shielding layer 117 is provided over the substrate 151, the insulating layer 153 is provided over the light-shielding layer 117, and the transistors 205D, 205R (not shown), 205G, and 205B are provided over the insulating layer 153. In addition, the coloring layers 132R, 132G, and 132B are provided over the insulating layer 218, and the insulating layer 235 is provided over the coloring layers 132R, 132G, and 132B.

[0579] The light emitting element 130R overlapping the colored layer 132R includes a pixel electrode 111R, an EL layer 113, and a common electrode 115.

[0580] The light emitting element 130G overlapping the colored layer 132G includes a pixel electrode 111G, an EL layer 113, and a common electrode 115.

[0581] The light emitting element 130B overlapping the colored layer 132B has a pixel electrode 111B, an EL layer 113 and a common electrode 115.

[0582] The pixel electrodes 111R, 111G, and 111B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom-emission display device, a metal or the like with low electrical resistivity can be used for the common electrode 115, which can suppress voltage drops caused by the electrical resistance of the common electrode 115 and achieve high display quality.

[0583] By using the transistor of one embodiment of the present invention, the area occupied by a pixel circuit can be reduced; therefore, in a display device with a bottom emission structure, the aperture ratio of a pixel can be increased or the size of the pixel can be reduced.

[0584] <Configuration Example 7 of Display Device> A display device 50G shown in FIG. 30A differs from the display device 50A mainly in that it includes a light receiving element 130S.

[0585] The display device 50G has a light-emitting element and a light-receiving element in each pixel. In the display device 50G, it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device using an organic EL element.

[0586] In the display device 50G, in which pixels have a light-emitting element and a light-receiving element, the pixels have a light-receiving function, so that the contact or proximity of an object can be detected while displaying an image. Therefore, the display unit 162 has one or both of an imaging function and a sensing function in addition to the image display function. For example, in addition to displaying an image using all of the sub-pixels of the display device 50G, some of the sub-pixels can emit light as a light source, other sub-pixels can perform light detection, and the remaining sub-pixels can display an image.

[0587] Therefore, there is no need to provide a light receiving unit and a light source separately from the display device 50G, and the number of components in the electronic device can be reduced. For example, there is no need to provide a separate biometric authentication device or a capacitive touch panel for scrolling, etc. Therefore, by using the display device 50G, it is possible to provide an electronic device with reduced manufacturing costs.

[0588] When a light receiving element is used as an image sensor, the display device 50G can capture an image using the light receiving element. For example, the image sensor can capture an image for personal authentication using a fingerprint, palm print, iris, pulse shape (including vein shape and artery shape), face, or the like. ...

Claims

a semiconductor layer, a first conductive layer, and a first insulating layer; the first insulating layer is located on the semiconductor layer; the first conductive layer has a region overlapping with the semiconductor layer via the first insulating layer, the semiconductor layer comprises crystalline indium oxide; the thickness of the semiconductor layer is 1 nm or more and 10 nm or less; the semiconductor layer has crystal grains, The semiconductor device, wherein the grain size of the crystal grains is 0.3 μm or more. 　 In claim 1, a second conductive layer and a third conductive layer; the semiconductor layer has a first region and a second region that do not overlap with the first conductive layer; the first region and the second region each have a first element; the first element is one or more of hydrogen, boron, and phosphorus; the second conductive layer has a region in contact with the first region, The third conductive layer has a region in contact with the second region. 　 a transistor and a first insulating layer; the transistor includes a semiconductor layer, a first conductive layer, and a second conductive layer; the first insulating layer is located on the first conductive layer; the second conductive layer is located on the first insulating layer; the first insulating layer and the second conductive layer have openings that reach the first conductive layer; the semiconductor layer has a region in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, and an upper surface and a side surface of the second conductive layer; the semiconductor layer comprises crystalline indium oxide; the thickness of the semiconductor layer is 1 nm or more and 10 nm or less; the semiconductor layer has crystal grains, The semiconductor device, wherein the grain size of the crystal grains is 0.3 μm or more. 　 In claim 3, a second insulating layer; the second insulating layer has a region in contact with a lower surface of the first conductive layer; the first insulating layer has a third insulating layer and a fourth insulating layer on the third insulating layer; the second insulating layer comprises silicon, nitrogen, and hydrogen; the third insulating layer comprises silicon and nitrogen; the fourth insulating layer includes silicon and oxygen; The semiconductor device, wherein the second insulating layer has a region having a higher hydrogen content than the third insulating layer. 　 forming an indium oxide layer; heat treatment to increase the crystallinity of the indium oxide layer to form a semiconductor layer; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer; The method for manufacturing a semiconductor device, wherein the temperature of the heat treatment is 400° C. or higher and 670° C. or lower. 　 In claim 5, The method for manufacturing a semiconductor device, wherein the indium oxide layer is formed by a sputtering method using oxygen gas, hydrogen gas, and argon gas. 　 In claim 5 or claim 6, supplying a first element to the semiconductor layer using the gate electrode as a mask; The method for manufacturing a semiconductor device, wherein the first element is one or more of hydrogen, boron, and phosphorus. 　 forming a first conductive layer; forming a first insulating film on the first conductive layer; forming a second conductive layer on the first insulating film, the second conductive layer having a first opening in a region overlapping the first conductive layer; removing a region of the first insulating film that overlaps with the first opening, and forming a first insulating layer having a second opening that reaches the first conductive layer; forming an indium oxide layer in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, and an upper surface and a side surface of the second conductive layer; a heat treatment is performed to increase the crystallinity of the indium oxide layer to form a semiconductor layer; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer; The method for manufacturing a semiconductor device, wherein the temperature of the heat treatment is 400° C. or higher and 670° C. or lower. 　 In claim 8, The method for manufacturing a semiconductor device, wherein the indium oxide layer is formed by a sputtering method using oxygen gas, hydrogen gas, and argon gas.

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