Semiconductor device and method for manufacturing same

Abstract

This semiconductor device comprises a first sacrificial layer (101), a second sacrificial layer (102), a third sacrificial layer (103), a device structure (104), and a protective layer (105). The first sacrificial layer (101) is formed from InAlAs, the second sacrificial layer (102) is formed from InGaAs, and the third sacrificial layer (103) is formed from any of InAlAs, InAlGaAs, and InAlAsP. The device structure (104) is composed of an InP-based compound semiconductor, has a semiconductor layer made of InP as the lowermost layer thereof, and is formed on the third sacrificial layer (103). The protective layer (105) is formed so as to cover the device structure.

Description

Semiconductor device and manufacturing method thereof

[0001] The present invention relates to semiconductor devices and methods for manufacturing the same.

[0002] The integration of compound optical semiconductors and silicon photonics optical circuits is progressing toward higher speeds, larger capacities, and smaller sizes of optical transceivers for optical communications. For example, low-loss optical coupling is achieved between compound semiconductors (especially InP-based semiconductors) used to fabricate lasers and optical modulators and silicon photonics by adiabatically transitioning the optical mode using a tapered waveguide structure. This heterogeneous integration technology, which combines compound semiconductors and silicon photonics, has attracted attention and is enabling the realization of compact, high-performance optical integrated circuits.

[0003] In particular, among heterogeneous integration technologies, the transfer printing method (also known as the microtransfer printing method) has attracted attention as a technology that can integrate completed compound optical semiconductors and silicon photonics optical circuits with high positional accuracy, high throughput, and low cost (Non-Patent Document 1).

[0004] For example, as shown in FIG. 3A , epitaxial crystal growth is used to form a first sacrificial layer 302 and a second sacrificial layer 303 on an original substrate 301, and a semiconductor layer 310 for forming a device is laminated on the second sacrificial layer 303. Next, the semiconductor layer 310 is processed to form a device structure 304 as shown in FIG. 3B , a protective layer 305 covering the device structure 304 is formed, and a tether resist layer 306 having leg portions 306 a is formed. The protective layer 305 is formed so that the surface of the second sacrificial layer 303 is exposed around it. The tether resist layer 306 is formed so that the leg portions 306 a reach the exposed surface of the original substrate 301 on the sides of the first sacrificial layer 302 and the second sacrificial layer 303.

[0005] Next, the first sacrificial layer 302 and the second sacrificial layer 303 are removed by selective wet etching, leaving the device structure 304 supported by the legs 306 on the original substrate 301, as shown in Fig. 3C. Thereafter, as shown in Fig. 3D, the device structure 304 supported by the legs 306 on the original substrate 301 is picked up from the original substrate 301 using a transfer stamp 307 and transferred onto a mounting substrate.

[0006] In this transfer technique, the sacrificial layer is generally made of a material that has selectivity, meaning that the etching rate of the wet etching etchant is large relative to the semiconductor material that constitutes the device structure. For InP-based materials used in compound semiconductor devices, InGaAs or InAlAs is generally used. It is also known to use FeCl3 (iron (III) chloride) as an etchant.

[0007] In Non-Patent Document 1, since the flatness of the back surface of the device structure (the surface of the device structure on the sacrificial layer side) after the sacrificial layer (release layer) is removed depends on the etching time of the sacrificial layer, a thin second sacrificial layer 303 made of InGaAs is stacked on a first sacrificial layer 302 made of InAlAs.

[0008] By using a sacrificial layer consisting of an InAlAs layer and an InGaAs layer, the difference in etching rate between InGaAs and InAlAs and the difference in etching rate with respect to the surface orientation can be utilized to reduce the time required to remove the sacrificial layer below the InP-based device structure, and the flatness of the back surface of the InP-based device structure can be improved.

[0009] Camiel Op de Beeck et al., "Heterogeneous III-V on silicon nitride amplifiers and lasers via microtransfer printing", Optica, vol. 7, issue 5, pp. 386-393, 2020.Y. Maeda et al., "Micro-transfer-printed InP-based Membrane Photonic Devices on Thin-film Lithium Niobate Platform", Journal of Lightwave Technology, DOI:10.1109 / JLT.2024.3366579, 2024.HS Yoon et al., "Dry Gate Recessed InGaAs / InAlAs / InP HEMTs Using CH4 / H2 Inductively Coupled Plasma", Journal of the Korean Physical Society, vol. 39, pp. S275-S278, 2001.

[0010] On the other hand, in the manufacture of InP-based device structures, dry etching is used as shown in Non-Patent Document 2. For example, as shown in Non-Patent Document 3, the etching rate for ICP-RIE with an optimized supply ratio of CH4 gas and H2 gas is 8 nm / min for InGaAs and 0.15 nm / min for InAlAs.

[0011] Therefore, when the sacrificial layer made of the InAlAs layer and the InGaAs layer is used, the InGaAs layer constituting the sacrificial layer is likely to be over-etched during dry etching in the fabrication of the device structure. If such over-etching occurs, a void will be formed immediately below the device structure 304 when the protective layer 305 is formed, as shown in Figures 3B and 3C.

[0012] This void remains even after transfer, resulting in a separation between the surface of the mounting substrate and the back surface of the device structure 304. For example, when optical elements formed in the device structure 304 are optically connected to optical waveguides formed in the mounting substrate by transfer, this will lead to an increase in optical coupling loss. Furthermore, the presence of the void may adversely affect mechanical reliability.

[0013] As mentioned above, conventional transfer printing methods have the problem of forming a gap between the backside of the device structure and the transferred substrate.

[0014] The present invention has been made to solve the above problems, and has as its object to suppress the formation of voids between the back surface of the device structure and the transferred substrate.

[0015] The semiconductor device according to the present invention comprises: a first sacrificial layer made of InAlAs and formed on a substrate made of InP; a second sacrificial layer made of InGaAs and stacked on the first sacrificial layer; a third sacrificial layer made of any of InAlAs, InAlGaAs, and InAlAsP and stacked on the second sacrificial layer; a device structure formed on the third sacrificial layer, the bottom layer of which is a semiconductor layer made of an InP-based compound semiconductor and made of InP; a protective layer formed to cover the device structure; and a substrate exposure region formed around a portion of the periphery of the device structure covered with the protective layer, where the substrate is exposed.

[0016] The semiconductor device and its manufacturing method according to the present invention includes a first step of sequentially forming and stacking a first sacrificial layer made of InAlAs, a second sacrificial layer made of InGaAs, and a third sacrificial layer made of InAlAs on a substrate made of InP; a second step of forming a device structure made of an InP-based compound semiconductor, with a semiconductor layer made of InP as the bottom layer, on the third sacrificial layer in a state in which the surface of the third sacrificial layer around the device structure is exposed; a third step of forming a protective layer on the third sacrificial layer in a state in which the surface of the third sacrificial layer is exposed around the device structure; and a third step of removing a portion of the third sacrificial layer, the second sacrificial layer, and the first sacrificial layer around the protective layer to expose the surface of the substrate. a fourth step of forming a substrate exposed region covered with the protective layer; a fifth step of forming a tether resist layer covering the protective layer and having legs that reach the substrate exposed region on the sides of the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer in the substrate exposed region; a sixth step of removing the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer from the sides of the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer that are exposed around the legs by wet etching using iron (III) chloride as a mask, thereby leaving the device structure supported on the substrate by the legs; and a seventh step of removing the device structure supported on the substrate by the legs and having the protective layer formed thereon from the substrate using a transfer stamp.

[0017] As described above, according to the present invention, the first sacrificial layer made of InAlAs, the second sacrificial layer made of InGaAs, and the third sacrificial layer made of any of InAlAs, InAlGaAs, and InAlAsP are used, so that the formation of voids between the back surface of the device structure and the transferred substrate can be suppressed.

[0018] FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. FIG. 2A is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2B is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2C is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2D is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2E is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2F is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2G is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 3A is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a conventional method for manufacturing a semiconductor device. FIG. 3B is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a conventional method for manufacturing a semiconductor device. FIG. 3C is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a conventional method for manufacturing a semiconductor device. FIG. 3D is a cross-sectional view showing a state of a semiconductor device in the middle of a process for explaining a conventional semiconductor device manufacturing method.

[0019] A semiconductor device according to an embodiment of the present invention will now be described with reference to Fig. 1. The semiconductor device includes a first sacrificial layer 101, a second sacrificial layer 102, a third sacrificial layer 103, a device structure 104, and a protective layer 105.

[0020] The first sacrificial layer 101 is made of InAlAs and is formed on a substrate 110 made of InP. The first sacrificial layer 101 may have a thickness of, for example, 450 nm. The second sacrificial layer 102 is made of InGaAs and is stacked on the first sacrificial layer 101. The second sacrificial layer 102 may have a thickness of, for example, 50 nm. The third sacrificial layer 103 is made of any of InAlAs, InAlGaAs, and InAlAsP and is stacked on the second sacrificial layer 102. The third sacrificial layer 103 may have a thickness of, for example, 10 to 20 nm.

[0021] The device structure 104 is made of an InP-based compound semiconductor, with a semiconductor layer made of InP as the bottom layer, and is formed on the third sacrificial layer 103. A protective layer 105 is formed to cover the device structure.

[0022] In addition, in this semiconductor device, a substrate exposed region 111 where the substrate 110 is exposed is formed in a part of the periphery of the device structure 104 covered with the protective layer 105 .

[0023] According to the embodiment described above, the third sacrificial layer 103 made of InAlAs is provided on the second sacrificial layer 102 made of InGaAs, so that the second sacrificial layer 102 made of InGaAs is not exposed by dry etching in the manufacture of the device structure 104. As a result, over-etching of the sacrificial layer can be prevented, and the occurrence of voids directly below the device structure 104 can be prevented when the protective layer 105 is formed.

[0024] A method for manufacturing a semiconductor device according to an embodiment of the present invention will now be described with reference to FIGS. 2A to 2G.

[0025] First, as shown in FIG. 2A , a first sacrificial layer 101 made of InAlAs, a second sacrificial layer 102 made of InGaAs, and a third sacrificial layer 103 made of InAlAs are sequentially formed and stacked on an InP substrate 110 (first step). For example, the first sacrificial layer 101 is formed by epitaxially growing InAlAs on the InP substrate 110, whose main surface is a (100) plane. Subsequently, the second sacrificial layer 102 is formed by epitaxially growing InGaAs on the first sacrificial layer 101. Subsequently, the third sacrificial layer 103 is formed by epitaxially growing InAlAs on the second sacrificial layer 102. These crystal growth processes can be performed by known crystal growth methods such as metalorganic vapor phase epitaxy and molecular beam epitaxy.

[0026] 2B , a device structure 104 made of an InP-based compound semiconductor and having an InP semiconductor layer as the bottom layer is formed on the third sacrificial layer 103 in a state where the surface of the third sacrificial layer 103 around the device structure 104 is exposed (second step). In this step (second step), the device structure 104 is fabricated by an etching process that selectively etches InP relative to InAlAs, thereby exposing the surface of the third sacrificial layer 103 around the device structure 104. For example, this process can be performed by dry etching using inductively coupled plasma (ICP) using CH gas and H gas.

[0027] Next, as shown in FIG. 2C, a protective layer 105 that covers the device structure 104 is formed on the third sacrificial layer 103 with the surface of the third sacrificial layer 103 exposed to the periphery (third step).

[0028] Next, as shown in FIG. 2D , a portion of the third sacrificial layer 103, the second sacrificial layer 102, and the first sacrificial layer 101 around the protective layer 105 is removed to form a substrate exposed region 111 where the surface of the substrate 110 is exposed (fourth step).

[0029] 2E , a tether resist (tether) layer 106 is formed to cover the protective layer 105 and to have legs 106 a that reach the substrate exposed region 111 on the sides of the first sacrificial layer 101, the second sacrificial layer 102, and the third sacrificial layer 103 in the substrate exposed region 111 (step 5). In this way, the semiconductor device according to the embodiment can further include a tether resist layer 106 that covers the protective layer 105 and to have legs 106 a that reach the substrate exposed region 111 on the sides of the first sacrificial layer 101, the second sacrificial layer 102, and the third sacrificial layer 103 in the substrate exposed region 111.

[0030] Next, as shown in FIG. 2F , wet etching using iron (III) chloride is performed using the tether resist layer 106 as a mask to remove the first sacrificial layer 101, the second sacrificial layer 102, and the third sacrificial layer 103 from the side surfaces of the first sacrificial layer 101, the second sacrificial layer 102, and the third sacrificial layer 103 that are exposed around the leg portions 106 a. This removal leaves the device structure 104 supported on the substrate 110 by the leg portions 106 a (step 6). In this step (step 6), the first sacrificial layer 101, the second sacrificial layer 102, and the third sacrificial layer 103 are removed to expose the entire lower surface of the lowest semiconductor layer of the device structure 104 that faces the substrate 110.

[0031] Next, as shown in FIG. 2G, the device structure 104, which is supported on the substrate 110 by the legs 106a and on which the protective layer 105 is formed, is removed from the substrate 110 using a transfer stamp 107 (seventh step).

[0032] Here, the thickness of the third sacrificial layer 103 can be made sufficiently thick relative to the amount of over-etching in the dry etching for forming the device structure 104, and can be made sufficiently thinner than the second sacrificial layer 102. For example, in dry etching by ICP using CH gas and H gas, the etching rate of InAlAs is about 0.15 nm / min. Therefore, in the etching for forming the device structure 104, the third sacrificial layer 103 around the device structure 104 is hardly etched.

[0033] Furthermore, by thinning the third sacrificial layer 103 as described above, the addition of the third sacrificial layer 103 hardly increases the time required for removing the first sacrificial layer 101, the second sacrificial layer 102, and the third sacrificial layer 103 in the sixth step.

[0034] In wet etching using iron (III) chloride, the first sacrificial layer 101 and the second sacrificial layer 102 are etched isotropically. Furthermore, because the first sacrificial layer 101 is thicker than the second sacrificial layer 102 and has a larger surface area exposed to the etchant, the first sacrificial layer 101 is etched away first, and the resulting opening allows etching of the second sacrificial layer 102. Because the second sacrificial layer 102 is thin, the etching process is completed in a relatively short time. Furthermore, if the third sacrificial layer 103 is kept thin as described above, its effect on the removal of the entire sacrificial layer is small. Therefore, the etching rate for wet etching when removing the entire sacrificial layer can be determined by the first sacrificial layer 101 and the second sacrificial layer 102. Therefore, the back surface flatness of the device structure 104 after the sacrificial layer removal can be sufficiently ensured.

[0035] Here, InAlAs is cited as an example of the material constituting the third sacrificial layer 103, but the material is not limited to this. The third sacrificial layer 103 can be made of a material that has a sufficiently low etching rate for known dry etching methods for InP and that can be etched with FeCl3, and materials such as InAlGaAs and InAlAsP are also applicable. The thickness of each sacrificial layer can be such that the third sacrificial layer is smaller than the second sacrificial layer and smaller than the third sacrificial layer.

[0036] As described above, according to the embodiment of the present invention, the first sacrificial layer made of InAlAs, the second sacrificial layer made of InGaAs, and the third sacrificial layer made of any of InAlAs, InAlGaAs, and InAlAsP are used, so that it is possible to suppress the formation of voids between the back surface of the device structure and the transferred substrate. According to the embodiment of the present invention, the suppression of void formation after transfer can be expected to improve the quality and reliability of the compound semiconductor device structure, the flatness of the back surface of the device structure, and the resulting yield.

[0037] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.

[0038] 101...first sacrificial layer, 102...second sacrificial layer, 103...third sacrificial layer, 104...device structure, 105...protective layer, 110...substrate, 111...exposed substrate region.

Claims

1. A semiconductor device comprising: a first sacrificial layer made of InAlAs and formed on a substrate made of InP; a second sacrificial layer made of InGaAs and laminated on the first sacrificial layer; a third sacrificial layer made of any of InAlAs, InAlGaAs, and InAlAsP and laminated on the second sacrificial layer; a device structure made of an InP-based compound semiconductor and having a semiconductor layer made of InP as the bottom layer formed on the third sacrificial layer; a protective layer formed to cover the device structure; and a substrate exposed region formed in a portion of the periphery of the device structure covered with the protective layer, where the substrate is exposed.

2. A semiconductor device according to claim 1, further comprising a tether resist layer covering said protective layer and having legs in said exposed substrate region that reach said exposed substrate region on the sides of said first sacrificial layer, said second sacrificial layer, and said third sacrificial layer.

3. A first step of sequentially forming and stacking a first sacrificial layer made of InAlAs, a second sacrificial layer made of InGaAs, and a third sacrificial layer made of InAlAs on a substrate made of InP; a second step of forming a device structure made of an InP-based compound semiconductor, with a semiconductor layer made of InP as the bottom layer, on the third sacrificial layer in a state where the surface of the third sacrificial layer around the device structure is exposed; a third step of forming a protective layer on the third sacrificial layer, covering the device structure in a state where the surface of the third sacrificial layer is exposed around the periphery; a fourth step of removing a part of the third sacrificial layer, the second sacrificial layer, and the first sacrificial layer around the protective layer to form a substrate exposed region where the surface of the substrate is exposed; and a fifth step of forming a tether resist layer covering the protective layer, and having legs that reach the substrate exposed region on the sides of the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer in the substrate exposed region. a sixth step of removing the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer from side surfaces of the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer that are exposed around the legs by wet etching using the tether resist layer as a mask, thereby leaving the device structure supported on the substrate by the legs; and a seventh step of removing the device structure, which is supported on the substrate by the legs and has the protective layer formed thereon, from the substrate using a transfer stamp.

4. A method for manufacturing a semiconductor device according to claim 3, wherein the second step exposes the surface of the third sacrificial layer around the device structure by etching the InP selectively with respect to the InAlAs.

5. A method for manufacturing a semiconductor device according to claim 4, wherein the etching process in the second step is a dry etching process using CH4 gas and H2 gas.

6. A method for manufacturing a semiconductor device according to any one of claims 3 to 5, wherein in the sixth step, the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer are removed to expose the entire lower surface of the lowest semiconductor layer of the device structure that faces the substrate.

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