Amplification device and amplification method, amplification system, comparison device, and ad conversion device

Abstract

Provided is an amplification device or the like having low current consumption and low offset as compared with conventional technology. A control circuit of a dynamic-type amplification device executes: a sampling operation in which a load circuit and a current source are connected to a differential amplifier, each input terminal and each inverting output terminal of the differential amplifier are short-circuited and then opened, and each input voltage and an error of the differential amplifier are held in each sampling capacitor, thereby cancelling the error of the differential amplifier; a reset operation in which the load circuit and the current source are disconnected, and each inverting output terminal is connected to a fixed potential; and an amplification operation in which the differential amplifier is connected to the current source, each inverting output terminal of the differential amplifier is set to high impedance, and each output capacitor of the differential amplifier is integrated by either charging or discharging according to each input voltage of the differential amplifier, thereby amplifying a difference between the input voltages after the sampling operation.

Description

Amplification device, amplification method, amplification system, comparison device, and AD conversion device

[0001] The present invention relates to an amplifier device and an amplification method suitable for, for example, a low-power AD converter, an amplifier system including the amplifier device, a comparison device including the amplifier device, and an AD converter including the comparison device.

[0002] FIG. 36 is a circuit diagram showing the configuration of a double tail latch type comparator according to the first prior art.

[0003] The configuration of the double-tail latch type comparator in Fig. 36 is the configuration reported in Non-Patent Document 1, and since the publication of Non-Patent Documents 2 and 3, which applied it to successive approximation type AD converters, it has been widely used in low-power AD converters up to the present because it is suitable for low-power operation. This double-tail latch type comparator is composed of a two-stage amplifier consisting of a dynamic type first-stage preamplifier and a post-stage latch, where a MOS transistor M １０１ ~M １１１ Here, the "dynamic" type refers to a comparator that does not perform comparison operation all the time, but rather controls the comparison phase and reset phase by a clock signal.

[0004] The first-stage dynamic preamplifier in Figure 36 is a differential voltage amplification stage that amplifies and outputs the input differential voltage. Its operation differs from that of a normal amplifier in that it operates dynamically. When the clock signal Clk is at L level, it is in the reset phase, and the output voltages (Out+, Out-) are precharged to the power supply. After that, the clock Clk is set to H level to transition to the comparison phase, in which the differential output voltage is discharged according to the input voltage difference, amplifying the input voltage. The discharge time is the integration time of the input differential voltage, and the integral gain is the gain of the dynamic amplifier.

[0005] The rear-stage latch section in Figure 36 is called a "regenerative latch," a configuration widely used in comparators in AD converters and sense amplifiers in memory readout circuits. When the clock signal Clk is at L level, it is in the reset phase, and resetting is achieved by setting the output voltage to ground potential. The clock Clk is then set to H level to transition to the comparison phase, where the input voltage is amplified by the differential input transistor section, and the output voltage amplitude is further amplified rail-to-rail to a CMOS logic level or higher through positive feedback of the output voltage.

[0006] In AD converters, comparators are used as quantizers. An ideal comparator would output a logic level of H or L depending on whether the input differential voltage is positive or negative. However, in reality, an offset occurs due to manufacturing process variations in the input and load differential pairs. This comparator offset not only appears in the AD conversion result, but also degrades linearity because it is dependent on the input common voltage. To reduce the offset, it is necessary to increase the size of the input and load differential pairs and reduce pair variations. Increasing the size increases the area and parasitic capacitance, making high-speed operation more difficult, and there is a trade-off in that the charge and discharge current required for control and drive increases, resulting in increased current consumption.

[0007] In particular, in successive approximation AD converters, the comparator input becomes high impedance because a capacitive DA converter is connected to the comparator. Increasing the size of the input differential pair leads to (1) signal attenuation due to increased comparator input capacitance, (2) degradation of linearity due to the voltage dependence of the comparator input capacitance, and (3) an increase in kickback noise that affects the input via parasitic capacitance between the input and output of the first-stage preamplifier when transitioning from the reset phase to the comparison phase. Furthermore, because the offset and input capacitance are temperature dependent, the performance trade-off with increasing size is severe. To reduce these effects, high-resolution AD converters often employ a differential configuration, and a configuration with an offset cancellation mechanism is adopted for the entire AD converter or the comparator.

[0008] Patent Document 1 discloses a double-tail latch type comparator with offset calibration, which self-calibrates the offset without increasing the input differential pair of the comparator in the AD converter, and as shown in Patent Document 1, various methods for comparator offset correction have been proposed.

[0009] Fig. 37 is a circuit diagram showing the configuration of a successive approximation type AD converter using a comparator with auto-zero according to Prior Art 2. This successive approximation type AD converter was reported in Non-Patent Document 4 for use in CMOS image sensors. In Fig. 37, this comparator has a three-stage configuration in which a latch A103 is connected to a two-stage preamplifier with auto-zero described as A101 and A102. The capacitive DA converter also has a power-saving mode in which only the latch portion operates by operating the capacitive DA converter at low resolution, turning off the two-stage preamplifier of the comparator, and turning on switches SW106 and SW107.

[0010] During normal operation, first, SW101 to SW104 are turned on before AD conversion, and then SW101 and SW102 are turned off, so that the offset of the first-stage preamplifier is stored in C101 and the SAR type DA converter with its polarity reversed so that it is canceled by the output voltage of the first-stage preamplifier. As a result, the offset of the first-stage preamplifier is canceled by 1 / (A101+1) in input conversion, assuming that the gain is A101. Next, by turning off SW103 and SW104, the remaining offset of the first-stage preamplifier stored in capacitors C103 and C104 is removed, and the offset of the subsequent-stage preamplifier is also canceled by being stored with its polarity reversed, similar to the first-stage preamplifier. Finally, the offset of the first-stage preamplifier is removed, and the offset of the subsequent-stage preamplifier is reduced to 1 / (A101(A102+1)) in input conversion, assuming that the gain is A102.

[0011] In this way, shorting the input and output of an amplifier, then opening them, and storing the offset by reversing the polarity of the capacitance connected to the input of the amplifier so that the offset is canceled at the output of the amplifier is called "input offset storage."Furthermore, connecting the input of the amplifier to a fixed potential, shorting one end of a capacitance connected to the output of the amplifier to the fixed potential on the side not connected to the amplifier, then opening it, and storing the offset in a capacitance connected to the output so that the other end of the capacitance is output and the offset is removed is called "output offset storage."

[0012] In the first-stage preamplifier, offset is removed by input offset storage and output offset storage, and in the second-stage preamplifier, offset is canceled by input offset storage. Note that the offset of the latch section is reduced to 1 / (A101 x A102) due to the gain of the first-stage preamplifier when converted into input. During AD conversion, a comparison operation is performed with the offset of the second-stage preamplifier canceled. In addition, a pixel reset voltage is input as the input voltage of the AD converter before AD conversion, and a signal voltage is input during AD conversion, thereby performing correlated double sampling (CDS).

[0013] JP 2010-109937 A JP 2001-244759 A JP 2007-318457 A JP 2011-228799 A

[0014] D. Schinkel et al., "A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup + Hold Time," ISSCC Dig. Tech. Papers, pp.314-315, Feb. 2007.M. van Elzakker et al., "A 1.9μW 4.4fJ / Conversion-step 10b 1MS / s charge-redistribution ADC", IEEE ISSCC Dig. Tech. Papers, Feb. 2008.M. van Elzakker et al., "A 10-bit Charge-redistribution ADC consuming 1.9μW at 1MS / s", IEEE JSSC, vol.45, no.5, pp.1007-1015, May 2010. S. Saiko et al., "Study on an Event-Detection CMOS Image Sensor Using Deep Learning (2) - Low-Resolution A / D Converter with Low-Power Operation," ITE Technical Report, Vol. 45, No. 21, Aug. 2021. B. Razavi, "The Strong ARM Latch [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, Spring, vol. 7, no. 2, pp. 12-17, 2015.

[0015] In power-saving mode, the two-stage preamplifier with auto-zero is bypassed and operates only as a latch, and no steady-state current flows, enabling low-power operation. However, the following issues remain: (1) There is a large offset due to the lack of auto-zero. (2) The latch is directly connected to the comparator input, resulting in large kickback noise. (3) Linearity degradation occurs due to the parasitic capacitance of the mode selector switches SW106 and SW107 connected to the comparator input. (4) The comparator input impedance is different from that during normal operation, resulting in a difference in the signal transfer function. (5) The clamp voltage of the comparator input in correlated double sampling (CDS) changes from that during normal operation.

[0016] In a system in which multiple AD converters are connected in parallel, such as the image sensor application in Non-Patent Document 4, it is possible to perform offset correction as in Patent Document 1, but because an offset correction circuit is required for each AD converter, a comparator with auto-zero that does not have a correction circuit and can perform correlated double sampling (CDS) and offset cancellation in the analog domain is often used.

[0017] The double-tail latch dynamic comparator described above has the problem that, in order to reduce the offset, the input differential pair must be enlarged or a correction circuit must be added. Furthermore, the comparator with auto-zero function has the problem that it is difficult to reduce current consumption because a steady current flows in the preamplifier. Similar problems exist in Patent Documents 2 to 4.

[0018] An object of the present invention is to solve the above problems and to provide an amplifier device and an amplification method that consume less current and have a lower offset than conventional techniques, an amplifier system including the amplifier device, a comparison device including the amplifier device, and an AD conversion device including the comparison device.

[0019] an amplifier according to one aspect of the present invention, comprising: a differential amplifier having first and second input terminals and first and second inverting output terminals; first and second sampling capacitors connected to the first and second input terminals of the differential amplifier, respectively; first and second switches short-circuiting the first and second input terminals and the first and second inverting output terminals of the differential amplifier, respectively; and a control circuit for controlling the operation of the amplifier, wherein the differential amplifier comprises: an input differential pair including a pair of transistors; a current source; a third switch inserted between the source of the input differential pair and the current source; and first and second output capacitors connected to the first and second inverting output terminals of the differential amplifier, respectively; the amplifier comprises: a load circuit connected to the first and second inverting output terminals of the differential amplifier; fourth and fifth switches connecting the first and second inverting output terminals of the differential amplifier to a predetermined fixed potential; and sixth and seventh switches for connecting or disconnecting the load circuit from the first and second inverting output terminals of the differential amplifier, (1) a sampling operation that controls the third switch and the sixth and seventh switches to connect the differential amplifier to the load circuit and the current source, controls the first and second switches to short-circuit and then open the first and second input terminals and the first and second inverting output terminals of the differential amplifier, and holds the first and second input voltages and the error of the differential amplifier in the first and second sampling capacitors, thereby canceling out the error of the differential amplifier; (2) a reset operation that, after the sampling operation, controls the third switch and the sixth and seventh switches to disconnect the load circuit from the current source, and controls the fourth and fifth switches to connect the first and second inverting output terminals to a fixed potential; (3) after the reset operation, controls the third switch to connect the differential amplifier to the current source, and holds the first and second inverting output terminals of the differential amplifierand an amplifying operation of amplifying the difference between the second input voltage and the first input voltage after the sampling operation by setting the first and second output capacitors of the differential amplifier to a high impedance and integrating by either charging or discharging the first and second input voltages of the differential amplifier.

[0020] Therefore, according to the amplifier device of the present invention, a dynamic amplifier device is operated as an amplifier during auto-zero mode, the offset of the input differential pair is stored in the input capacitance, and the offset is cancelled during comparison operation to perform dynamic operation, thereby making it possible to provide an amplifier device or the like that consumes less current and has a lower offset than conventional technology.

[0021] 17 is a circuit diagram showing an example configuration of a dynamic amplifier circuit 1 with input offset storage according to a first embodiment. It is a circuit diagram showing a detailed configuration of the differential amplifier section 2 of FIG. 1. It is a circuit diagram showing a configuration of a load circuit 3A according to a modified example of the load circuit 3 of FIG. 1. It is a timing chart of each signal showing the operation of the dynamic amplifier circuit 1 of FIG. 1. It is a block diagram showing a single-ended configuration for explaining an error of the differential amplifier section 2 of FIG. 1. It is a circuit diagram showing the configuration of a differential amplifier section 2A according to a modified example. It is a timing chart of each signal showing the operation of the differential amplifier section 2A of FIG. 6. It is a circuit diagram showing the configuration of an offset adjustment circuit 5 according to a second embodiment. It is a circuit diagram showing the configuration of the variable resistance circuit of FIG. 8. It is a block diagram showing an example configuration of a dynamic amplifier circuit 1B according to the second embodiment. It is a flowchart showing an offset comparison process executed by the control circuit 10B of FIG. 10. It is a flowchart showing an offset correction process executed by the control circuit 10B of FIG. 10. It is a flowchart showing an offset correction process which is a first modified example of the offset correction process of FIG. 12. It is a flowchart showing an offset correction process which is a second modified example of the offset correction process of FIG. 12. It is a flowchart showing an offset correction process which is a third modified example of the offset correction process of FIG. 12. It is a timing chart of each signal showing the operation of a dynamic amplifier circuit 1C (FIG. 17) according to a third embodiment. 20 is a circuit diagram showing an example of the configuration of a dynamic amplifier circuit 1C according to embodiment 3. FIG. 17 is a circuit diagram showing a detailed configuration of the differential amplifier section 2C of FIG. 17. FIG. 18 is a timing chart of each signal showing the operation of the differential amplifier section 2C of FIG. 17. FIG. 20 is a circuit diagram showing an example of the configuration of a strong-arm latch type dynamic comparison circuit 2D with input offset storage according to embodiment 4. FIG. 21 is a timing chart of each signal showing the operation of the dynamic comparison circuit 2D of FIG. 20. FIG. 21 is a circuit diagram showing an example of the configuration of a double-tail latch type comparison circuit with input offset storage according to embodiment 5. FIG. 22 is a circuit diagram showing an example of the configuration of a comparison circuit according to embodiment 6. FIG. 23 is a timing chart of each signal showing the operation of the comparison circuit of FIG. 23. FIG. 24 is a circuit diagram showing an example of the configuration of a dynamic amplifier circuit according to embodiment 7. FIG. 25 is a circuit diagram showing an example of the configuration of a comparison circuit according to embodiment 8.27 is a timing chart of each signal showing operation in a normal mode in the comparison circuit of FIG. 26. FIG. 28 is a timing chart of each signal showing operation in a low-power operation mode in the comparison circuit of FIG. 26. FIG. 29 is a flowchart showing signal amplification processing executed by the control circuit 10 of the dynamic amplifier circuit 1 of FIG. 1. FIG. 30 is a circuit diagram showing an example of the configuration of a successive approximation type AD converter according to a ninth embodiment. FIG. 31 is a circuit diagram showing an example of the configuration of a successive approximation type AD converter according to a tenth embodiment. FIG. 32 is a circuit diagram showing an example of the configuration of a successive approximation type AD converter according to an eleventh embodiment. FIG. 33 is a circuit diagram showing an example of the configuration of an AD converter according to a twelfth embodiment. FIG. 34 is a circuit diagram showing an example of the configuration of an AD converter according to a thirteenth embodiment. FIG. 35 is a circuit diagram showing an example of the configuration of an AD converter according to a fourteenth embodiment. FIG. 36 is a circuit diagram showing the configuration of a double-tail latch type comparator according to conventional example 1. FIG. 37 is a circuit diagram showing the configuration of a successive approximation type AD converter using a comparator with auto-zero according to conventional example 2.

[0022] Hereinafter, embodiments and modifications of the present invention will be described with reference to the drawings, in which the same or similar components are designated by the same reference numerals.

[0023] 1 is a circuit diagram showing an example of the configuration of a dynamic amplifier circuit 1 with input offset storage according to the first embodiment. In FIG. 1, the dynamic amplifier circuit 1 with input offset storage includes a differential amplifier section 2 and an input voltage V ｐ , V ｍ and a sampling capacitor C for sampling the offset of the differential amplifier section 2. ｓｐ , C ｓｍ and a switch SW short-circuiting the amplifier input and inverting output to store the offset voltage at the input. ａｚｐｍ , SW ａｚｍｐ and switch SW ａｚｐｍ , SW ａｚｍｐ and a control circuit 10 that controls the operation of the differential amplifier section 2.

[0024] In FIG. 1, the input voltage V ｐ is the sampling capacitor C ｓｐ is input to the non-inverting input terminal of the differential amplifier unit 2 via ｍ is the sampling capacitor Cｓｍ The inverting output terminal of the differential amplifier section 2 is connected to the switch SW ａｚｐｍ The non-inverting input terminal of the differential amplifier section 2 is connected to the switch SW ａｚｍｐ is connected to the inverting input terminal via the switch SW ａｚｐｍ , SW ａｚｍｐ is controlled to be on or off by an auto-zero control signal AZ from the control circuit 10, and the switch SW ａｚｐｍ , SW ａｚｍｐ is turned on, while the switch SW ａｚｐｍ , SW ａｚｍｐ is turned off.

[0025] The control circuit 10 generates control signals DPAEN and DPACK to control the operation of the differential amplifier section 2. The control signal DPAEN is an enable signal for the dynamic amplifier operation of the differential amplifier section 2, and is a control signal for switching the load on and off during auto-zero. The control signal DPACK is a control signal for switching the reset / amplification operation of the differential amplifier section 2. The CK input to the control circuit 10 is a clock signal for dynamic operation for controlling the reset operation at L level and the amplification operation at H level. The input voltage to the non-inverting input terminal of the differential amplifier section 2 is V ｉｐ and the input voltage of the inverting input terminal is V ｉｍ In addition, the output voltage from the inverting input terminal of the differential amplifier unit 2 is V ｏｍ The output voltage from the non-inverting input terminal is V ｏｐ Let's say.

[0026] FIG. 2 is a circuit diagram showing a detailed configuration of the differential amplifier unit 2 of FIG.

[0027] In FIG. 2, the differential amplifier section 2 has: (1) an input voltage V ｉｐ , V ｉｍ The input differential pair MOS transistors M １ , M ２ (2) Input differential pair MOS transistor M １ , M ２Switch SW ｔａｉｌ The tail current I connected via ｔａｉｌ a tail current source I ｔａｉｌ (3) Input differential pair MOS transistor M １ , M ２ (4) a load circuit 3 connected to each drain of the output voltage V ｏｐ , V ｏｍ A switch SW is provided between each output terminal from which the signal is output and the power supply voltage VDD, and is controlled by a control signal / DPACK. ｏｐ , SW ｏｍ (5) Output voltage V ｏｐ , V ｏｍ output load capacitor C connected to each output terminal ＬＰ , C ＬＭ and

[0028] When the control signal DPAEN is at H level or the inverted control signal / DPAEN is at L level, the switch SW ｏｐ , SW ｏｍ On the other hand, when the control signal DPAEN is at L level or the inverted control signal / DPAEN is at H level, the switch SW ｏｐ , SW ｏｍ When the control signal DPACK is at H level or the inverted control signal / DPACK is at L level, the switch SW ｌｏａｄ１ , SW ｌｏａｄ２ , SW ｔａｉｌ On the other hand, when the control signal DPACK is at L level or the inverted control signal / DPACK is at H level, the switch SW ｌｏａｄ１ , SW ｌｏａｄ２ , SW ｔａｉｌ Turn off.

[0029] Here, the tail current source I ｔａｉｌ On / off is by switch SW ｔａｉｌ Without using the tail current source I ｔａｉｌ In the example of FIG. 2, the load circuit 3 includes a PMOS transistor M １１ , M １２ and a switch SW controlled by control signals / DPAEN and DPAEN. ｌｏａｄ１, SW ｌｏａｄ２ The present invention is configured to include the following.

[0030] 3 is a circuit diagram showing the configuration of a load circuit 3A according to a modification of the load circuit 3 shown in FIG. 2. In addition to the example shown in FIG. 2, the load circuit 3 may have a configuration that is folded back via a current source, a resistor, a diode-connected MOS transistor, and a current mirror circuit. As shown in FIG. 3, a switch SW ｌｏａｄ１ , SW ｌｏａｄ２ MOS transistor M １１ , M １２ Alternatively, the drain of the transistor 10 may be connected in series to the drain of the transistor 10.

[0031] 4 is a timing chart of each signal showing the operation of the dynamic amplifier circuit 1 of FIG. ｐ and V ｍ are the initial voltages V ｐｉｎｉｔ , V ｍｉｎｉｔ For example, when used in differential amplification, both voltages (V ｐｉｎｉｔ =V ｍｉｎｉｔ ) to the input common voltage V ｃｍ Or the reference voltage V ｒｅｆ Alternatively, the pixel reset voltage V may be set to a divided or multiplied voltage or a fixed potential such as VSS. ｒｓｔ The initial voltage V ｐｉｎｉｔ and the input voltage V ｍ is the reference voltage V that is within the input range depending on the DA conversion circuit used. ｒｅｆ The initial voltage V ｍｉｎｉｔ In FIG. 4, the input voltage V ｐ , V ｍ The hatched portion indicates a transition portion of the input voltage before and after.

[0032] Next, the auto-zero control signal AZ is set to H level, and each input terminal of the differential amplifier unit 2 and its corresponding inverted output terminal are short-circuited, and each input terminal is clamped to each inverted output voltage including the offset error. The control signal DPAEN is set to L level, and the control signal DPACK is set to H level to cause the differential amplifier unit 2 to perform an amplification operation, and the input voltage V of the differential amplifier unit 2 is ｉｐ , Vｉｍ After the output voltage is settled to the inverted output voltage with the output terminals shorted, the auto-zero control signal AZ is set to L level, and the sampling capacitor C ｓｐ , C ｓｍ Then, the polarity of the input voltage V ｐ , V ｍ V ｐ１ , V ｍ１ For example, when using differential amplification, the differential signal is set to the input voltage V ｐ , V ｍ When used in a single-ended AD conversion circuit, the input voltage V ｐ , V ｍ The input signal V ｓｉｇ is applied to the other side, and the output voltage V of the DA conversion circuit is applied to the other side. ｄａｃ is applied.

[0033] This results in an initial voltage V ｐｉｎｉｔ , V ｍｉｎｉｔ and input voltage V ｐ１ , V ｐ２ , V ｍ１ , V ｍ２ The difference between these two is input to the differential amplifier 2, and correlated double sampling (CDS) is performed to cancel out the error components that are correlated with each other. In the example of the PMOS current mirror load circuit 3, the clamp voltage of the CDS is １１ , M １２ The gate-source voltage is

[0034] Next, the control signal DPAEN is set to H level to turn off the load circuit 3 so that it has high impedance with respect to the output terminal. Then, the control signal DPACK is set to L level to precharge and reset the output terminal from the power supply voltage VDD. After that, the control signal DPACK is set to H level to reset the differential output voltage V ｏｍ , V ｏｐ is discharged according to the input voltage difference, ｉｐ , V ｉｍ Amplify.

[0035] The discharge time during the H level period of the control signal DPACK is the integral time Tｉｎｔ The integral gain is the gain a of the dynamic amplifier circuit 1. ｉｎｄ Then, the discharge current I ｏ is the transconductance g of the input differential pair ｍｄ It is expressed by the following equation using

[0036] I ｏ = g ｍｄ ×V ｉｎｄ

[0037] Output voltage V after integral time has elapsed ｏｄ is expressed by the following equation:

[0038] V ｏｄ =I ｏ ×T ｉｎｔ / C Ｌ

[0039] Here, C Ｌ is the load capacitance. Therefore, the gain a is expressed by the following equation.

[0040] a = V ｏｄ / V ｉｎｄ = g ｍｄ / C Ｌ ×T ｉｎｔ

[0041] However, the output common voltage V ｏｃｏｍ is the tail current I ｔａｉｌ It is expressed by the following equation using

[0042] V ｏｃｏｍ = VDD-I ｔａｉｌ / (2 x C Ｌ ) x t

[0043] Here, the power supply voltage VDD drops over time, and when it reaches near the ground level, the gain cannot be obtained. For this reason, the H level width of the control signal DPACK may be adjusted according to the load capacitance, or the output common voltage V ｏｃｏｍ The tail current source I ｔａｉｌ is the input differential pair of MOS transistors M １ , M ２This is used to equalize the offset voltage by making the gate-source voltage equal to that during auto-zero, thereby maximizing the amount of offset cancellation. Also, if a decrease in the frequency band in which errors are canceled in CDS can be tolerated and high impedance can be maintained at both input terminals of the differential amplifier unit 2, the reset and amplification operations may be repeated by setting the control signal DPACK to L level / H level from the second time onwards, as shown in Figure 4.

[0044] 5 is a block diagram showing a single-ended configuration for explaining the error of the differential amplifier unit 2 in FIG. 1. For offset error analysis, FIG. 5 shows a model in which the input is grounded and an input-referred offset error is introduced into the amplifier. When the auto-zero control signal AZ is at H level, the input-referred error of the differential amplifier unit 2 in the amplifying operation is e, and its voltage gain is Av=A, then the amplifier input voltage V during auto-zero is ｉａｚ is expressed by the following equation:

[0045] V ｉａｚ =V ｏａｚ = -A × (V ｉａｚ +e) =-A / (1+A)×e

[0046] After that, the auto-zero control signal AZ is set to L level, and the sampling capacitance C ｓ The offset error component during the amplification operation in auto-zero mode is stored in the input differential pair MOS transistor M １ , M ２ and the load circuit 3, and are calculated as follows: １ , M ２ As the input-referred offset error, e = e ｏｓｄｉｆｆ and the gain of the differential amplifier unit 2 during the amplification operation in dynamic operation is a, the output voltage V ｏｏｓｄｉｆｆ is expressed by the following equation:

[0047] V ｏｏｓｄｉｆｆ = -a × (V ｉａｚ +e ｏｓｄｉｆｆ ) =-a / (1+A)×e ｏｓｄｉｆｆ

[0048] Its input-equivalent offset voltage Vｉｒｏｓｄｉｆｆ is expressed by the following equation:

[0049] V ｉｒｏｓｄｉｆｆ =V ｏｏｓｄｉｆｆ / (-a) =1 / (1+A)×e ｏｓｄｉｆｆ

[0050] The amplifier operation during auto-zero cancels the error component of the input differential pair to 1 / (1+A). Next, the input-converted offset error of the differential pair load circuit 3 during auto-zero is expressed as e = e ｏｓｌｏａｄ Then, since no load is used during dynamic operation at the time of comparison and no error is included, the output voltage V ｏｏｓｌｏａｄ is expressed by the following equation:

[0051] V ｏｏｓｌｏａｄ = -a x V ｉａｚ =a×A / (1+A)×e ｏｓｌｏａｄ

[0052] Its input-equivalent offset voltage V ｉｒｏｓｌｏａｄ is expressed by the following equation:

[0053] V ｉｒｏｓｌｏａｄ =V ｏｏｓｌｏａｄ / (-a １ ) =-A / (1+A)×e ｏｓｌｏａｄ

[0054] The offset component of the differential pair load at AZ stored in the input of the differential amplifier section 2 is not canceled. The input-equivalent offset voltage V of the entire dynamic amplifier ｉｒｏｓ is the input differential pair of MOS transistors M １ , M ２ The offsets of the load circuits 3 and 4 are caused by mismatch components of the differential pairs and vary independently, and are therefore expressed as the square root of the sum of squares as shown in the following equation.

[0055]

[0056] From the above, the error of the dynamic amplifier circuit 1 according to this embodiment is １ , M ２ Since the offset error due to the load circuit 3 is cancelled, it can be seen that the offset error is determined by the load circuit 3 in the auto-zero state.１ , M ２ In comparison, increasing the size of the differential amplifier does not increase the input capacitance of the differential amplifier unit 2, and there is little trade-off with input capacitance-induced characteristics such as signal attenuation and increased kickback noise, making it easier to reduce offset by increasing the size. Also, even when an offset correction circuit is attached to the output stage, the size of the correction circuit can be easily reduced.

[0057] As described above, the dynamic amplifier circuit 1 according to this embodiment can reduce the offset without increasing the size of the input differential pair MOS transistors. Furthermore, even when an offset correction circuit is used, the scale of the circuit can be reduced.

[0058] 29 is a flowchart showing the signal amplification process executed by the control circuit 10 of the dynamic amplifier circuit 1 shown in FIG. ｓｐ , C ｓｍ The offset is then stored in the buffer, and then dynamically amplified by an integral action.

[0059] In FIG. 29, first, in step S31, the differential amplifier input / output switch SW ａｚｐｍ , SW ａｚｍｐ By turning on the input voltage V ｐ , V ｍ and its inverted output voltage, V ｏｍ , V ｏｐ The output voltage V of the differential amplifier section 2 is ｏｍ , V ｏｐ The inverted error voltages −Ve1 and −Ve2 are output from the capacitors C ｓｐ , C ｓｍ via the input voltage V ｐ , V ｍ The first voltage V1 and the second voltage V2 are input as follows.

[0060] Next, in step S32, the switch SW ａｚｐｍ , SW ａｚｍｐBy turning off the differential amplifier 2 and opening the input / output terminals, the potential difference between the inverted error voltages −Ve1, −Ve2 and the input voltages V1, V2 is ｓｐ , C ｓｍ Each of them is held in

[0061] Then, in step S33, the input voltage V ｐ and V ｍ The third voltage V3 and the fourth voltage V4 are input as the differential amplifier section 2, and the input differential pair transistors M １ , M ２ , tail current source I ｔａｉｌ , the switch SW ｔａｉｌ By turning off the tail current source I ｔａｉｌ The current supply to the switch SW ｌｏａｄ１ , SW ｌｏａｄ２ By turning off the switch SW ｏｐ , Sw ｏｍ By turning on the output terminal, the output load capacitance is reset by connecting the output terminal to a predetermined fixed potential.

[0062] Then, in step S34, the switch SW ｔａｉｌ By turning on the MOS transistor M １ , M ２ Operate the switch SW ｏｐ , SW ｏｍ By turning off the MOS transistors M, the output terminals set to a fixed potential are opened, and the input voltages V3-Ve1-V1 and V4-Ve2-V2 of the differential amplifier section 2 are applied to the input differential pair MOS transistors M. １ , M ２ The voltage is converted to a current by -Ve1 and -Ve2, and the error occurring in the differential amplifier 2 is cancelled out by the converted currents of the -Ve1 and -Ve2 terms. The output load capacitance is charged or discharged with the converted currents and integrated for amplification.

[0063] As described above, in the signal amplification process according to this embodiment, by performing the auto-zero operation before the reset / amplify operation, the offset can be reduced without increasing the size of the input MOS transistor.

[0064] 6 is a circuit diagram showing the configuration of a differential amplifier unit 2A according to a modified example, which is characterized in that the NMOS input differential amplifier unit is changed to a PMOS input differential amplifier unit as compared to the differential amplifier unit 2 shown in FIG.

[0065] FIG. 7 is a timing chart of each signal showing the operation of the differential amplifier section 2A of FIG.

[0066] In FIG. 7, similar to the operation in FIG. 4, first, the input voltage V ｐ and V ｍ The initial voltage V ｐｉｎｉｔ , V ｍｉｎｉｔ Next, the auto-zero control signal AZ is set to H level to short-circuit the input terminal and inverted output terminal of the differential amplifier unit 2A, and each input terminal is clamped to each inverted output voltage. The control signal DPAEN is set to L level, and the control signal DPACK is set to H level to amplify the differential amplifier unit 2A, and after the input voltage has settled, the auto-zero control signal AZ is set to L level to cancel the offset of the differential amplifier unit 2A at the output terminal. ｓｐ , C ｓｍ Then, the polarity of the input voltage V ｐ , V ｍ are the input voltage V ｐ１ , V ｍ１ Next, the control signal DPAEN is set to H level, turning off the load circuit 3 so that it has high impedance with respect to the output terminal. Then, the control signal DPACK is set to L level, discharging the output terminal to ground and resetting it. After that, the control signal DPACK is set to H level, and the differential output voltage is charged in accordance with the input voltage difference, thereby amplifying the input voltage.

[0067] As described above, by changing the differential amplifier unit 2A from an NMOS input differential amplifier to a PMOS input differential amplifier, the input voltage range and the output voltage range can be changed.

[0068] (Embodiment 2) Fig. 8 is a circuit diagram showing the configuration of an offset adjustment circuit 5 according to embodiment 2. Fig. 8 shows a configuration in which an offset adjustment circuit 5 is added to the load circuit 3 of Fig. 2. The offset adjustment circuit 5 is configured by inserting variable resistance circuits VR1 and VR2 on the power supply voltage VDD side of the differential pair load. A control signal OSCTRL is a digital control signal for offset adjustment.

[0069] 9 is a circuit diagram showing the configuration of the variable resistance circuits VR1 and VR2 in FIG. 8. In FIG. 9, the variable resistance circuits VR1 and VR2 are ｕ This can be easily realized by switching the unit resistance value with a switch. ｕ As a result, the resistance value R ｕ The resistance value can be adjusted from 0.01 to 4Ru. The type of resistor used may be either a polysilicon resistor or an on-resistance of a MOS transistor, depending on the configuration of the load circuit 3 and the bias current value.

[0070] 10 is a block diagram showing a configuration example of a dynamic amplifier circuit 1B according to the second embodiment. In FIG. 10, the dynamic amplifier circuit 1B is characterized in that an offset adjustment circuit is added to the dynamic amplifier circuit 1 of FIG. 1. The offset adjustment circuit includes: (1) a sampling capacitor C ｓｐ The voltage input to the input voltage V ｐ and the input common voltage V ｃｍ and the sampling capacitor C ｓｍ The voltage input to the input voltage V ｍ and the input common voltage V ｃｍ Input signal selector switch SW ｉｎｐ , SW ｉｎｍ (2) Output voltage V ｏｍ , V ｏｐ and output a comparison result signal to the control circuit 10B, (3) a comparator 12 that compares the differential amplifier unit 2 and the offset adjustment circuit, and (4) a memory 11 connected to the control circuit 10B. The differences will be explained below.

[0071] In FIG. 10, the input signal changeover switch SWｉｎｐ , SW ｉｎｍ is the control signal SSW from the control circuit 10B ｉｎｐ , S.S.W. ｉｎｍ Based on this, the capacitor C ｓｐ , C ｓｍ Connect one end of each to the input common voltage V ｃｍ Here, the input common voltage V ｃｍ may be at ground level or another potential as long as each differential input terminal is short-circuited. Comparator 12 compares the positive or negative offset of the amplifier differential output voltage of differential amplifier unit 2 and outputs a comparison result signal to control circuit 10B. Control circuit 10B adjusts the offset of differential amplifier unit 2 based on the comparison result signal of comparator 12. Memory 11 stores the offset correction value (calibration value) from control circuit 10B and outputs it to control circuit 10B.

[0072] 11 is a flowchart showing the offset comparison process executed by the control circuit 10B of FIG. 10. The offset correction is performed by the differential pair of MOS transistors M １ , M ２ When the load resistance becomes unbalanced due to a mismatch in the impedance of the load circuit 3, the load resistance value is the differential pair MOS transistor M １ , M ２ The control circuit 10B compares the offsets of the output voltages of the differential amplifier unit 2 so as to balance with the impedance of the differential amplifier unit 2, and adjusts the offset adjustment resistors based on the comparison result signal, thereby adjusting the offsets of the output voltages of the differential amplifier unit 2 so as to approach zero. The offset comparison process in the offset correction is carried out by connecting each differential input terminal of the differential amplifier unit 2 to the input signal changeover switch SW ｉｎｐ , SW ｉｎｍ In a state where the voltages are set to the same potential, the amplifiers are amplified by dynamic operation from auto-zero as in normal operation, and the differential output voltages are compared by the comparator 12.

[0073] In step S1 of FIG. 11, first, the control signal DPAEN is set to L level, the control signal DPACK is set to H level, and the differential amplifier unit 2 is operated. ａｚｐｍ , SW ａｚｍｐ By turning on the input voltage Vｉｐ , V ｉｍ Each terminal and its inverted output voltage V ｏｍ , V ｏｐ The output voltage V of the differential amplifier section 2 is ｏｍ , V ｏｐ The inverted error voltages −Ve1 and −Ve2 are output as the capacitors C ｓｐ , C ｓｍ Each of the terminals is connected to an input signal changeover switch S ｗｉｎｐ , S ｗｉｎｍ The common voltage V ｃｍ Connect to.

[0074] Next, in step S2, the switch SW ａｚｐｍ , SW ａｚｍｐ By turning off the differential amplifier 2 and opening the input / output terminals, the inverted error voltages -Ve1 and -Ve2 and the common voltage V ｃｍ The potential difference between the capacitor C ｓｐ , C ｓｍ Each of them is held in

[0075] Then, in step S3, the control signal DPAEN is set to H level, and the control signal DPACK is set to L level to reset the differential amplifier unit 2. After that, in step S4, the control signal DPACK is set to H level, and the inverted error voltages −Ve1 and −Ve2 of the differential amplifier unit 2 are input to the input differential pair MOS transistors M １ , M ２ The voltage-current conversion is performed by the differential amplifier 2, and the error components that are not canceled out among the error components generated in the differential amplifier 2 are amplified by charging or discharging the output load capacitance with the converted current and integrating it to produce the output voltage V ｏｐ , V ｏｍ Output as

[0076] Finally, in step S5, the comparator 12 compares the differential output voltage V ｏｐ and V ｏｍ Here, if the noise of the comparator 12 is large, the number of offset comparison processes may be increased, and the comparison result signals may be integrated to perform majority decision according to the number of comparisons, thereby improving the comparison accuracy.

[0077] Fig. 12 is a flowchart showing the offset correction process executed by the control circuit 10B of Fig. 10. In the offset correction process of Fig. 12, the offset adjustment value OSCTRL is incremented or decremented to perform the offset correction process.

[0078] 12, first, the control circuit 10B sets the offset adjustment value OSCTRL to 0 and initializes the offset comparison count N to 0. Next, in step S12, an offset comparison process is performed, and in step S13, the control circuit 10B determines whether N>0 or the comparison result of the comparison result signal is different from the previous comparison result, and based on the comparison result of step S14, the value of the offset adjustment value OSCTRL is incremented by +1 or decremented by -1 to update it (S15, S16). Thereafter, in step S17, the offset comparison count N is incremented by +1, and the offset adjustment value OSCTRL and the comparison result are saved in memory 11.

[0079] Then, similarly, the process returns to step S12, where an offset comparison process is performed, and the processes of steps S14 to S17, S12, and S13 are repeated until the comparison result of step S13 becomes YES, which indicates that the offset correction has been completed. After the offset correction process is completed, the differential amplifier unit 2 operates using the offset correction value stored in the memory 11.

[0080] Fig. 13 is a flowchart showing an offset correction process that is a first variation of the offset correction process of Fig. 12. The offset correction process of Fig. 13 differs from the offset correction process of Fig. 12 in the following respects: (1) It includes a process of step S11A instead of step S11. (2) It includes processes of steps S12, S13, S16, and S17. The differences will be described below.

[0081] 13, in step S11A, the offset adjustment value OSCTRL is set to the minimum value, and the offset comparison count is initialized to 0. Next, the processes of steps S12, S13, S16, and S17 are executed. As a result, the resistance control value based on the offset adjustment value OSCTRL is incremented from the minimum value, and the offset correction process is executed.

[0082] Fig. 14 is a flowchart showing an offset correction process that is a second variation of the offset correction process of Fig. 12. The offset correction process of Fig. 14 differs from the offset correction process of Fig. 12 in the following respects: (1) Instead of step S11, it includes processing of step S11B. (2) It includes processing of steps S12, S13, S15, and S17. The differences will be described below.

[0083] 14, in step S11B, the offset adjustment value OSCTRL is set to the maximum value, and the number of offset comparisons is initialized to 0. Next, the processes of steps S12, S13, S15, and S17 are executed. As a result, the resistance control value based on the offset adjustment value OSCTRL is decremented from the maximum value, and the offset correction process is executed.

[0084] Fig. 15 is a flowchart showing an offset correction process which is a third modification of the offset correction process of Fig. 12. The offset correction process of Fig. 15 is a correction process using a binary search.

[0085] 15, the control circuit 10B sets the offset adjustment value OSCTRL to 0 and initializes the offset comparison count N to 0. Here, the range of the offset adjustment value OSCTRL is -α≦OSCTRL<α, where α is a positive integer. Next, in step S22, an offset comparison process is performed, and in step S23, V ｏｐ >V ｏｍ If the result is YES, the process proceeds to step S24, and if the result is NO, the process proceeds to step S25. Here, based on the comparison result of step S23, the offset adjustment value OSCTRL is sequentially divided into two parts for the range α by +α / 2. Ｎ＋１ Increment by or -α / 2 Ｎ＋１(S24, S25). Thereafter, in step S26, the offset comparison count N is incremented by +1, and the offset adjustment value OSCTRL and the comparison result are stored in memory 11 (S26). Subsequently, similarly, the offset comparison process of step S22 is performed, and the offset adjustment value OSCTRL is updated until the offset comparison count N exceeds the number of bits of the offset adjustment value OSCTRL (S27), thereby performing offset correction.

[0086] As described above, the dynamic amplifier circuit 1B including the offset correction circuit according to the second embodiment can correct the offset of the load circuit 3 relative to the differential pair of MOS transistors. Here, the offset correction process using increment or decrement has a simple configuration, allowing for a small circuit size. Furthermore, the offset correction process using binary search requires fewer comparisons than a search using increment or decrement, allowing for faster correction.

[0087] 16 is a timing chart of each signal showing the complete dynamic operation of a dynamic amplifier circuit 1C (FIG. 17) according to embodiment 3. Also, FIG. 17 is a circuit diagram showing an example of the configuration of the dynamic amplifier circuit 1C according to embodiment 3, and FIG. 18 is a circuit diagram showing the detailed configuration of a differential amplifier section 2C of FIG. 17.

[0088] The dynamic amplifier circuit 1C of Figures 16 to 18 is characterized in that, by changing the control signal in embodiment 1 or 2, the operating mode can be switched between a fully dynamic operating mode for low current consumption operation and an amplifier mode with auto-zero that does not perform dynamic operation for high-precision operation.

[0089] 16, in order to reduce current consumption during fully dynamic operation, the control signal DPAEN is set to H level and the control signal DPACK is fixed to L level during the auto-zero period in Fig. 4, thereby resetting the differential amplifier unit 2C. Therefore, auto-zero is not performed and only CDS is performed.

[0090] Here, as shown in FIG. 17, in order to change the clamp voltage during CDS, the clamp voltage V for CDS is controlled by the control signal LPM from the control circuit 10C during full dynamic operation. ｃｌａｍｐ Switch SW for connecting to ｉｐｍｍ , SW ｉｐｍｐ Auto-zero switch SW ａｚｐｍ , SW ａｚｍｐ In addition, when the clamp voltage during CDS is set to the output voltage of the differential amplifier section 2C during full dynamic operation, the changeover switch SW ｉｐｍｍ , SW ｉｐｍｐ The configuration of FIG. 1 may be used, omitting the tail current source I ｔａｉｌ The operation is the same as in FIG. 4 except that the tail current source I ｔａｉｌ The amount of current of the tail current source I ｔａｉｌ In parallel with the switch SW ｉｐｍｔａｉｌ may be inserted and turned on and bypassed by the control signal LPM during full dynamic operation.

[0091] 19 is a timing chart of each signal showing the operation of the differential amplifier unit 2C of FIG. 17 without dynamic operation. Compared to the differential amplifier unit 2 of FIG. 2, the dynamic operation clock CK is set to L level, the control signal DPAEN is set to L level, and the control signal DPACK is fixed to H level, so that the differential amplifier unit 2C operates as a normal amplifier with auto-zero function without dynamic operation. In this way, the operating mode can be switched simply by changing the control signals.

[0092] As described above, according to the third embodiment, in a fully dynamic operation, the error of the amplifier differential pair cannot be canceled as compared to the first or second embodiment, but the current consumption can be reduced by stopping the amplifier operation during auto-zero.

[0093] In the normal auto-zero unmode without dynamic operation, current consumption increases compared to the first or second embodiment, but the offset or low-frequency error of the load circuit 3 can be canceled, allowing the differential amplifier unit 2C to be used with high precision. Furthermore, since the input impedance does not change significantly when switching between operation modes, the difference in signal transfer function can be reduced. Furthermore, the clamp voltage in the CDS does not change when switching between modes.

[0094] As described above, according to the third embodiment, the optimum current consumption and accuracy for the system can be selected by switching between an operation mode with low power consumption and low accuracy, or a mode with high power consumption and high accuracy using a control signal.

[0095] 20 is a circuit diagram showing a configuration example of a strong-arm latch type dynamic comparison circuit 2D with input offset storage according to a fourth embodiment. The dynamic comparison circuit 2D of FIG. 20 includes the following components in the output stage of the dynamic amplifier circuit 1: (1) a MOS transistor M ２１ , M ２２ , M ３１ , M ３２ (2) a latch circuit 22 configured to output a comparison result voltage of the input differential voltages; and (3) a reset switch SW for resetting the latch circuit 22. ｌａｔｍ , SW ｌａｔｐ (3) A switch SW for disconnecting the latch circuit 22 from the output terminal of the dynamic amplifier circuit 1 during auto-zero. ｏｍ , SW ｏｐ It is characterized by the addition of and.

[0096] The dynamic comparison circuit 2D of FIG. 20 uses a sampling capacitor C ｓｐ , C ｓｍ , switch SW ａｚｐｍ , SW ａｚｍｐ , and the load circuit 3 during auto-zero, the tail current source I ｔａｉｌ It has a configuration in which the following is added.

[0097] In the dynamic comparison circuit 2D configured as described above, the above components are added to the output stage of the dynamic amplifier circuit 1, but the above components may also be added to the output stage of the dynamic amplifier circuits 1B and 1C according to embodiments 2 and 3. In this case, the offset correction circuit does not require an additional comparator because the configuration in Figure 20 itself serves as a comparator. Also, the voltage input latch circuit 22 in Figure 20 may be added instead of the comparator 12 in the dynamic amplifier circuit 1B according to embodiment 2.

[0098] FIG. 21 is a timing chart of each signal showing the operation of the dynamic comparison circuit 2D of FIG.

[0099] In FIG. 21, during auto-zero, the dynamic amplifier circuit 1 operates in the same sequence as in FIG. 4, and the added latch circuit 22 is disconnected from the output stage of the differential amplifier section 2 when the clock CK is at L level, and its output voltage (comparison result voltage) V ｏｌａｔｐ , V ｏｌａｔｍ is reset to the power supply voltage VDD. Then, the operation shifts to dynamic operation, and in the reset phase, both the differential amplifier unit 2 and the latch circuit 22 are reset so that their output voltages become the power supply voltage VDD. In the next amplification phase, the output voltage V ｏｐ , V ｏｍ is amplified by the discharge of the differential current, and when it is discharged to a differential voltage (VDD-Vth) (where Vth is a predetermined threshold voltage), the output voltage V of the latch circuit 22 ｏｌａｔｐ , V ｏｌａｔｍ The comparison operation is performed by further amplifying the output amplitude to a rail-to-rail CMOS logic level or higher through a positive feedback operation by the amplifier. In addition, in order to ensure an amplification time so as to increase the gain of the dynamic amplifier circuit 1 during dynamic operation, the rising timing of the clock CK that controls the latch circuit 22 during amplification may be delayed from the control signal DPACK.

[0100] As described above, according to the dynamic comparison circuit 2D of the fourth embodiment, a sampling capacitor C ｓｐ , C ｓｍ , switch SW ａｚｐｍ , SW ａｚｍｐ , and the load circuit 3 during auto-zero, the tail current source I ｔａｉｌ By adding this, the offset can be reduced without increasing the size of the input differential pair. Also, if an offset correction circuit is used, the size of the circuit can be reduced.

[0101] 22 is a circuit diagram showing a configuration example of a double-tail latch type comparator circuit with input offset storage according to embodiment 5. The comparator circuit in FIG. 22 is characterized in that it uses the dynamic amplifier circuit 1 in FIG. 1 as a first-stage preamplifier and adds a voltage input latch circuit 23 in the subsequent stage.

[0102] Here, the dynamic amplifier circuit 1B or 1C of FIG. 10 or FIG. 17 may be used as the first-stage preamplifier. In the offset correction circuit of FIG. 10, the configuration of FIG. 22 itself serves as a comparison circuit, so no additional comparison circuit is required. Also, the voltage input latch circuit 23 of FIG. 22 may be added instead of the comparator 12 of FIG. 10. Furthermore, the voltage input latch circuit 23 may have any configuration as long as it has a differential input, and the above-mentioned strong-arm latch (see Non-Patent Document 5) or a regenerative latch at the subsequent stage of the double-tail latch type comparison circuit of Non-Patent Document 1 may be used.

[0103] According to the comparison circuit configured as above, the first-stage preamplifier operates in the same sequence as the dynamic amplifier circuit 1 of FIG. 1, and the added voltage input latch circuit 23 is reset when the clock CK is at the L level. Then, the operation shifts to dynamic operation, and in the reset phase, both the dynamic amplifier circuit 1 and the voltage input latch circuit 23 are reset. In the next amplification phase, the output voltage V of the dynamic amplifier circuit 1 is ｏｐ , V ｏｍis amplified by the discharge of the difference current, and when it is discharged to the operating threshold voltage of the downstream voltage input latch circuit 23, the comparison operation is performed by further amplifying the output amplitude to a rail-to-rail CMOS logic level or higher through the positive feedback operation of the voltage input latch circuit 23. Note that, as in the fourth embodiment, in order to ensure an amplification time so that the gain of the dynamic amplifier circuit 1 during dynamic operation is large, the rising timing of the clock CK that controls the voltage input latch circuit 23 during amplification may be delayed from the control signal DPACK.

[0104] As described above, the comparator circuit according to the fifth embodiment can reduce the offset in a widely used double-tail latch type comparator circuit without increasing the size of the input differential pair. Furthermore, even when an offset correction circuit is used, the scale of the circuit can be reduced.

[0105] 23 is a circuit diagram showing a configuration example of a comparison circuit according to embodiment 6. The comparison circuit in Fig. 23 is characterized in that the dynamic amplifier circuit 1 in Fig. 1 is used as a first-stage preamplifier, and the dynamic comparison circuit 2D in Fig. 20 is connected to the subsequent stage to form a preamplifier by cascading the dynamic amplifier circuits 1 in two stages, and a comparison circuit including a latch circuit 22 in the final stage is configured.

[0106] Although the comparator circuit of Fig. 23 uses the dynamic amplifier circuit 1 of Fig. 1, it may also use the dynamic amplifier circuit 1B or 1C of Fig. 10 or 17. Also, although the dynamic comparator circuit 2D of Fig. 20 is used, it may also use the double tail latch type comparator circuit of Fig. 22.

[0107] 24 is a timing chart of each signal showing the operation of the comparison circuit of FIG. 23. The subscript "1" of the control signals indicates the control signal within the dynamic amplifier circuit 1 of the first-stage preamplifier, and the subscript "2" indicates the control signal within the subsequent-stage dynamic comparison circuit 2D. That is, in the dynamic amplifier circuit 1 of the first-stage preamplifier, the control circuit 10 outputs the auto-zero control signal AZ1, the control signal DPAEN1, and the control signal DPACK1. In the subsequent-stage dynamic comparison circuit 2D, the control circuit 10 of the dynamic amplifier circuit 1 within the dynamic comparison circuit 2D outputs the auto-zero control signal AZ2, the control signal DPAEN2, and the control signal DPACK2. Here, the rising timing of the control signal DPACK2 and the control clock CK of the latch circuit 22 is delayed from the control signal DPACK1 so that the comparison operation does not occur before the amplification operation of the first stage.

[0108] 24, first, the auto-zero control signal AZ1 to the dynamic amplifier circuit 1 in the first stage and the auto-zero control signal AZ2 to the dynamic amplifier circuit 1 in the dynamic comparison circuit 2D in the second stage are set to H level to short-circuit the input terminal and inverting output terminal of the internal differential amplifier section 2, the control signals DPAEN1 and DPAEN2 are set to L level, and the control signals DPACK1 and DPACK2 are set to H level to amplify the first and second stage differential amplifier sections 2. Next, the auto-zero control signal AZ1 is set to L level, and the offset of the first stage is canceled in the same way as the dynamic amplifier circuit 1 in FIG. 1. Next, the control signal DPAEN1 is set to H level, and the control signal DPACK1 is set to L level to reset the first stage differential amplifier section 2. If the first stage dynamic amplifier circuit 1 does not perform a reset here, the sampling capacitor C in the second stage ｓｐ , C ｓｍHowever, since the gain differs between auto-zero and amplification and the offset is not removed, output offset storage is not performed and the first-stage differential amplifier unit 2 is reset. Next, the auto-zero control signal AZ2 is set to L level, which cancels the offset in the subsequent stages as well as the first stage. Next, the control signal DPAEN2 is set to H level and the control signal DPACK2 is set to L level to reset the subsequent-stage differential amplifier unit 2. Thereafter, the first-stage amplification operation and the subsequent-stage comparison operation are performed in the same manner as in Figures 1 and 20.

[0109] As described above, the comparison circuit according to the sixth embodiment allows the optimum current consumption and accuracy for the system to be selected by switching between low power consumption and low accuracy and high power consumption and high accuracy in the initial and subsequent stages using a control signal. Compared to the dynamic comparison circuit of FIG. 20 according to the fourth embodiment and the double-tail latch comparison circuit of FIG. 22 according to the fifth embodiment, the comparison circuit according to the sixth embodiment can improve accuracy by cascading auto-zero in the initial and subsequent stages. While the comparison circuit of FIG. 23 is added to the output stage of the dynamic amplifier circuit 1 as a comparison circuit, any one of the dynamic amplifier circuits 1, 1B, and 1C according to the first to third embodiments may be cascaded to the output of the dynamic amplifier circuit 1 of FIG. 23 instead of the comparison circuit to operate as an amplifier.

[0110] 25 is a circuit diagram showing an example of the configuration of a dynamic amplifier circuit according to a seventh embodiment. The dynamic amplifier circuit of FIG. 25 is characterized by being configured by adding a preamplifier circuit with input offset storage to the front stage of the dynamic amplifier circuit of FIG. 1. Here, the preamplifier circuit includes a known differential amplifier 1P (which, unlike the dynamic amplifier circuit 1 of FIG. 1, does not have an operation changeover switch based on the control signals DPAEN and DPACK, but does have an auto-zero control signal AZP), a sampling capacitor C ｓｐ , C ｓｍ and amplifier input / output short-circuit switch SW ａｚｐｍ , SW ａｚｍｐThe control circuit 10D generates an auto-zero control signal AZP to control the auto-zero timing of the added preamplifier.

[0111] In the dynamic amplifier circuit configured as described above, first, the auto-zero control signal AZP of the differential amplifier 1P (preamplifier) ​​and the auto-zero control signal AZ of the subsequent dynamic amplifier circuit 1 are set to H level to short-circuit the input terminal and the inverted output terminal of each amplifier. Next, the control signal DPAEN of the subsequent dynamic amplifier circuit 1 is set to L level and the control signal DPACK is set to H level to cause the subsequent dynamic amplifier circuit 1 to perform an amplification operation. Next, the auto-zero control signal AZP of the differential amplifier 1P (preamplifier) ​​is set to L level to cancel the offset of the differential amplifier 1P by input offset storage. Furthermore, the auto-zero control signal AZ of the subsequent dynamic amplifier circuit 1 is set to L level to cancel the capacitor C ｓｐ and C ｓｍ The remaining offset of the differential amplifier 1P stored in is removed by the output offset storage, and at the same time, the input offset storage of the subsequent stage is also performed, thereby canceling the offset of the subsequent stage. After that, the differential amplifier 1P, which is the first-stage preamplifier, continues its amplification operation, and the dynamic amplifier circuit 1 performs an amplification or comparison operation after being reset in the same way as in Figure 4.

[0112] As described above, according to the seventh embodiment, the remaining load offset in the dynamic amplifier circuit 1 of Fig. 1 can be reduced to 1 / gain in input conversion by the differential amplifier 1P, which is the preamplifier in the preceding stage, thereby eliminating the need for offset correction in the dynamic amplifier circuit 1 in the following stage. Furthermore, compared to the case where differential amplifiers are cascaded, current consumption can be reduced by dynamically operating the amplifier in the following stage.

[0113] Although the dynamic amplifier circuit of FIG. 25 uses the dynamic amplifier circuit 1 of FIG. 1, the dynamic amplifier circuit 1B or 1C of FIG. 10 or FIG. 17, or the comparison circuit of FIG. 20, FIG. 22 or FIG. 23 may also be used. When the latter comparison circuit is used, the entire circuit becomes a comparison circuit. Also, a preamplifier circuit with output offset storage may be used instead of the preamplifier circuit with input offset storage in the first stage, and the capacitor C ｓｐ , C ｓｍ and amplifier input / output short-circuit switch SW ａｚｐｍ , SW ａｚｍｐ may be used both as an offset storage capacitor and an offset sampling switch in the output section of the preamplifier circuit with output offset storage.

[0114] 26 is a circuit diagram showing an example of the configuration of a comparison circuit according to embodiment 8. The comparison circuit of FIG. 26 is characterized in that (1) a differential amplifier 1PA, which is a preamplifier with input offset storage, is added to the subsequent stage of the dynamic amplifier circuit 1 of FIG. 1, and (2) a voltage input latch circuit 23 that operates in accordance with a clock CK is connected to the subsequent stage. The differences will be described below.

[0115] 26, a differential amplifier 1PA with input offset storage is provided in the differential amplifier 1P in the previous stage of FIG. 25, and is provided with a low power consumption mode changeover switch SW which operates based on a control signal LPM. ｌｐｍｐｍ , SW ｌｐｍｍｐ A selector switch SW ｌｐｍｐｍ , SW ｌｐｍｍｐ By turning on the 2nd stage amplifier, it is bypassed in low power consumption mode. Also, in the differential amplifier 1PA, in order to clarify that the elements and input voltage are different from other stages, C ｓｐ２ , C ｓｍ２ , SW ａｚｐｍ２ , SW ａｚｍｐ２ , AZ2,V ｉｐ２ , V ｉｍ２Here, the control signal LPM is a signal that enables the low power consumption mode, and when it is at H level, it turns off the operation of the differential amplifier 1PA and sets the output terminal to high impedance, and the switch SW ｌｐｍｐｍ , SW ｌｐｍｍｐ By turning on the control signal AZ2, the second stage differential amplifier 1PA is bypassed. The control circuit 10E generates the control signal AZ2 and the control signal LPM to control the preamplifier 1PA with the added input offset storage.

[0116] 27 is a timing chart of each signal showing the operation in normal mode (LPM=L) in the comparison circuit of FIG. 26. Here, the suffix "1" is added to the auto-zero control signal AZ to clarify that it is a control signal within the dynamic amplifier circuit 1 in the first stage.

[0117] 27, the control signal DPAEN of the first-stage dynamic amplifier circuit 1 is set to L level, and the control signal DPACK is fixed to H level, thereby preventing dynamic operation and operating as a normal amplifier with auto-zero. First, the auto-zero control signals AZ1 and AZ2 are set to H level, shorting the input terminals and their inverting output terminals of each amplifier. Next, the auto-zero control signal AZ1 is set to L level, canceling the offset of the first-stage dynamic amplifier circuit 1. Next, the auto-zero control signal AZ2 is set to L level, eliminating any offset remaining in the first-stage dynamic amplifier circuit 1, and similarly to the first stage, canceling the offset of the second-stage differential amplifier 1PA. Thereafter, the voltage input latch circuit 23 in the subsequent stage performs reset and comparison operations in response to the clock CK.

[0118] FIG. 28 is a timing chart of each signal showing the operation of the comparison circuit of FIG. 26 in the low power consumption operation mode (LPM=H).

[0119] 28, in the low power consumption mode, the output terminal of the second-stage differential amplifier 1PA is in a high-impedance state, turning off its operation and bypassing the differential amplifier 1PA, as compared with FIG. 27. The operation of other parts is the same as that of the comparison circuit of FIG. 22 of the fifth embodiment.

[0120] The comparator circuit according to the eighth embodiment configured as described above can selectively switch between a first operation mode with low power consumption and low accuracy and a second operation mode with high power consumption and high accuracy using the control signal LPM, thereby enabling optimal current consumption and accuracy for the circuit system. Furthermore, since the input impedance does not change significantly when the operation mode is switched, differences in the signal transfer function can be reduced. Furthermore, the clamp voltage in the CDS circuit does not change when the mode is switched.

[0121] 30 is a circuit diagram showing a configuration example of a successive approximation type AD converter according to embodiment 9. The successive approximation type AD converter of FIG. 30 includes: (1) a comparison circuit 33 according to embodiment 4; (2) a successive approximation type control logic circuit (SAR control logic circuit) 34 connected in the subsequent stage of the comparison circuit 33; and (3) a sampling capacitor C ｓｍ The present invention is configured to include a capacitance DA conversion circuit 40 that replaces the

[0122] Here, the capacitance DA conversion circuit 40 may be of a charge scaling type as in Non-Patent Document 5, or may be of another type. When the capacitance DA conversion circuit 40 is of a charge scaling type, a plurality of capacitors C ｏ ~C ｎ and each capacitor C ０ ~C ｎ is the reference voltage V ｒｅｆｐ or V ｒｅｆｍ A plurality of n+1 switches SW ０ ~SW ｎ and switch SW ０ ~SW ｎ and a control circuit 10F that controls the reference voltage V ｒｅｆｐ , V ｒｅｆｍ is V ｒｅｆｐ >V ｒｅｆｍ is.

[0123] In FIG. 30, the input voltage V ｐ As a fixed potential V ｒ, and each input terminal of the differential amplifier unit 2 and each inverting output terminal thereof are short-circuited and then opened, thereby ｓｐ A fixed potential V is input to one end of ｒ and sampling capacitor C ｓｐ A clamp voltage V including an offset error voltage of the differential amplifier unit 2 is applied to the other end of ｃｌａｍｐ and the capacitance DA conversion circuit 40. ｏ ~C ｎ The control circuit 10F supplies a reference voltage V ｒｅｆｐ and the output voltage V of the capacitance DA conversion circuit 40 iｍ The clamp voltage V including the offset error voltage of the differential amplifier unit 2 is ｃｌａｍｐ and the plurality of capacitors C ｏ ~C ｎ The clamp voltage V ｃｌａｍｐ is the output voltage including the offset error voltage when each input terminal and each inverting output terminal of the differential amplifier unit 2 are short-circuited during auto-zero. ｒ is the pixel reset voltage V shown in the background art. ｒｓｔ and common voltage V ｃｍ Alternatively, the control circuit 10F may be set to ｏ ~C ｎ The voltage to be set is determined by the voltage across a plurality of capacitors C ｏ ~C ｎ Each reference voltage V ｒｅｆｐ , V ｒｅｆｍ Either of the above may be set.

[0124] Next, the input voltage V ｐ and the signal voltage V ｓiｇ is input and the comparator circuit 33 is reset. After that, the control circuit 10F outputs the DA conversion voltage V ｄａｃ is the voltage (V ｒｅｆｐ -V ｒｅｆｍ ) / 2, and the input voltage V ｉｐ , V ｉｍare V ｃｌａｍｐ +V ｓiｇ -V ｒ , V ｃｌａｍｐ -V ｄａｃ Here, the DA conversion voltage V ｄａｃ is the reference voltage V controlled by the control circuit 10F ｒｅｆｐ , V ｒｅｆｍ Next, the comparator circuit 33 compares the input voltage V ｉｐ , V ｉｍ Then, the SAR control logic circuit 34 compares the comparison reference voltage of the comparison circuit 33 for the conversion of the next bit based on the conversion result of the MSB, and outputs the DA conversion voltage V of the capacitive DA conversion circuit 40 via the control circuit 10F. ｄａｃ voltage (V ｒｅｆｐ -V ｒｅｆｍ ) / 2 ± (V ｒｅｆｐ -V ｒｅｆｍ ) / 4. Thereafter, the reset operation, comparison operation, and DA conversion voltage V of the capacitive DA conversion circuit 40 are performed in the same manner up to the least significant bit LSB. ｄａｃ is updated, and the input voltage V of the differential amplifier unit 2 is ｉｐ and V ｉｍ are equal, that is, the DA conversion voltage V ｄａｃ is a fixed potential V ｒ and signal voltage V ｓiｇ The input voltage V of the CDS is the difference iｎ =V ｒ -V ｓiｇ The SAR control logic circuit 34 performs AD conversion processing by sequentially performing binary search based on the comparison result so that the result is equal to

[0125] As described above, according to the AD conversion device of the ninth embodiment, the characteristic trade-off of the input differential pair of the comparison circuit 33 is alleviated, allowing for a smaller size and a smaller input capacitance, thereby reducing signal attenuation at the input terminal of the comparison circuit 33 and reducing kickback noise of the comparison circuit 33. Furthermore, similar to the eighth embodiment, by selectively switching the operation mode of the comparison circuit 33 depending on the desired accuracy, it is possible to select the optimum current consumption and accuracy for the circuit system. If high accuracy is not required, the offset correction circuit required for a successive approximation type AD conversion circuit using a dynamic comparison circuit can be eliminated.

[0126] In the above-described ninth embodiment, the comparison circuit 33 according to the fourth embodiment may be replaced with the comparison circuit according to the fifth embodiment, the comparison circuit according to the sixth embodiment, the comparison circuit according to the modified example of the seventh embodiment, or the comparison circuit according to the eighth embodiment.

[0127] 31 is a circuit diagram showing a configuration example of a successive approximation type AD converter according to a tenth embodiment. The successive approximation type AD converter of FIG. 31 differs from the successive approximation type AD converter of FIG. 30 in the following points: (1) The input voltage Vin is applied to the capacitive DA converter circuit 41 through a switch SW ０ ~SW ｎ (2) The input voltage V of the comparison circuit 33 is input via ｐ common voltage V ｃｍ The differences are explained below.

[0128] 31, by short-circuiting and then opening each of the input terminals and the inverting output terminals of the differential amplifier section 2, the sampling capacitor C ｓｐ The common voltage V ｃｍ and sampling capacitor C ｓｐ A clamp voltage V including an offset error voltage of the differential amplifier unit 2 is applied to the other end of ｃｌａｍｐ and simultaneously sample the input voltage V ｉｎ is connected to the capacitance DA conversion circuit 41 via the switch SW ０ ~SW ｎ and the capacitance DA conversion circuit 41 includes a plurality of capacitors Cｏ ~C ｎ The input voltage V ｉｎ and the output voltage V of the capacitance DA conversion circuit 41 iｍ The clamp voltage V including the offset error voltage of the differential amplifier unit 2 is ｃｌａｍｐ and the plurality of capacitors C ｏ ~C ｎ Simultaneous sampling is performed on the input signal V ｉｎ Sampling is performed simultaneously.

[0129] Next, the control circuit 10G controls the plurality of capacitors C ｏ ~C ｎ is the switch SW ０ ~SW ｎ By controlling the input voltage V ｉｎ After that, the control circuit 10G controls the capacitance DA conversion circuit 41 to output the DA conversion voltage V ｄａｃ is the voltage (V ｒｅｆｐ -V ｒｅｆｍ ) / 2, and the input voltage V ｉｐ , V ｉｍ are V ｃｌａｍｐ , V ｃｌａｍｐ -V ｉｎ +V ｄａｃ After auto-zero, the input common voltage V ｃｍ at another fixed potential V ｓｈｉｆｔ and connect to the input voltage V ｉｐ V ｃｌａｍｐ -V ｃｍ +V ｓｈｉｆｔ The input range of the AD conversion device may be changed by changing the comparison voltage as follows. Thereafter, the comparison operation and the update of the capacitive DA conversion circuit 41 are performed in the same manner as in the ninth embodiment, and the input voltage V ｉｎ is the DA conversion voltage V ｄａｃ The SAR control logic circuit 34 performs AD conversion processing by sequentially performing binary search based on the comparison result so that the result is equal to

[0130] As described above, in the AD conversion device according to the tenth embodiment, the input voltage and the input voltage of the reference voltage of the DA conversion circuit 41 are the same, so that the transfer functions up to the input terminals of the comparison circuit 33 are equal, and it is possible to reduce the gain error of the AD conversion device.

[0131] 32 is a circuit diagram showing a configuration example of a successive approximation type AD converter according to an eleventh embodiment. The successive approximation type AD converter of FIG. 32 differs from the successive approximation type AD converter of FIG. 31 in the following points: (1) In the successive approximation type AD converter of FIG. 31, the sampling capacitor C ｓｐ The input circuit on the input side is replaced with a capacitance DA conversion circuit 41 to provide differentiation. The differences will be described below.

[0132] In FIG. 32, as in the tenth embodiment, the input voltage V ｉｎｍ , V ｉｎｐ In each of the capacitance DA conversion circuits 41 and the comparison circuit 33 connected to the ｉｎｍ , V ｉｎｐ , and each capacitance DA conversion circuit 41 is sampled at the same time to supply the input voltage V ｉｎｍ , V ｉｎｐ Then, the DA conversion voltages V of the respective capacitive DA conversion circuits 41 are ｄａｃｐ , V ｄａｃｍ is the voltage (V ｒｅｆｐ -V ｒｅｆｍ ) / 2, and the input voltage V ｉｐ , V ｉｍ are V ｃｌａｍｐ -V ｉｎｍ +V ｄａｃｐ , V ｃｌａｍｐ -V ｉｎｐ +V ｄａｃｍ Thereafter, the comparison operation and updating of each capacitance DA conversion circuit 41 are performed in the same manner as in the tenth embodiment, and V ｉｎｍ -V ｄａｃｐ and V ｉｎｐ -V ｄａｃｍ is equal to the differential input voltage V ｉｎｐ -V ｉｎｍ is the differential output V of each capacitive DA conversion circuit 41 ｄａｃｐ -V ｄａｃｍ The SAR control logic circuit 34 performs AD conversion processing by sequentially performing binary search based on the comparison result so that the result is equal to

[0133] As described above, the successive approximation type AD converter according to the eleventh embodiment can eliminate common mode signals by differentiating the circuit configuration, thereby increasing resistance to disturbances caused by fluctuations in the power supply voltage VDD, ground, reference voltage, etc. Furthermore, the input signal voltage at each input terminal of the comparator circuit 33 is doubled by differentiation, thereby increasing the signal-to-noise ratio (SNR).

[0134] 33 is a circuit diagram showing a configuration example of an AD converter according to a twelfth embodiment. The AD converter of FIG. 33 differs from the successive approximation type AD converter of FIG. 30 in the following points: (1) a control logic circuit 35 in place of the successive approximation type control logic circuit 34; and (2) a sampling capacitor C of the comparison circuit 33 in place of the capacitive DA conversion circuit 40. ｓｍ (3) the input voltage V of the comparison circuit 33 ｍ and a DA conversion circuit 42 provided in the front stage of the side. The differences will be explained below.

[0135] In FIG. 33, (1) the plurality of capacitors C ｏ ~C ｎ Instead, the sampling capacitor C ｓｍ (2) the output voltage of the capacitive DA conversion circuit 42 is used instead of the DA conversion voltage of the capacitive DA conversion circuit 40, and (3) AD conversion is performed as in the ninth embodiment shown in Fig. 30. The search algorithm may be a binary search as in the ninth embodiment, or may be a search performed by incrementing and decrementing from the minimum and maximum values.

[0136] The AD converter configured as above can use a DA converter circuit of another type instead of the capacitive DA converter circuit, and has the same effects as those of the ninth embodiment shown in FIG.

[0137] In the above-described embodiment 12, the comparison circuit 33 according to embodiment 4 may be replaced with the comparison circuit according to embodiment 5, the comparison circuit according to embodiment 6, the comparison circuit according to a modified example of embodiment 7, or the comparison circuit according to embodiment 8.

[0138] 34 is a circuit diagram showing a configuration example of an AD conversion device according to a thirteenth embodiment. The AD conversion device of FIG. 34 differs from the AD conversion device of FIG. 31 in the following points: (1) a control logic circuit 35 in place of the successive approximation type control logic circuit 34, and (2) a sampling capacitor C ｓｍ and the DA conversion circuit 42, and (3) the input voltage V of the comparison circuit 33 ｍ On the side, the control signal SSW ｉｎ and the input voltage V ｍ , the output voltage V of the DA conversion circuit 42 ｄａｃ and input voltage V ｉｎ A switch SW selectively switches between ｉｎ The differences will be explained below.

[0139] In FIG. 34, (1) the plurality of capacitors C ｏ ~C ｎ , switch SW ０ ~SW ｎ Instead of these, sampling capacitors C ｓｍ and switch SW ｉｎ (2) The DA conversion voltage V of the capacitive DA conversion circuit 41 ｄａｃ Instead, the output voltage V of the DA conversion circuit 42 ｄａｃ (3) A / D conversion is performed in the same manner as in the tenth embodiment shown in Fig. 31. The search algorithm may be a binary search as in the tenth embodiment, or may be a search performed by incrementing and decrementing from the minimum and maximum values.

[0140] The AD converter configured as above can use a DA converter circuit of another type instead of the capacitive DA converter circuit, and has the same effects as those of the tenth embodiment shown in FIG.

[0141] In the above-described embodiment 13, the comparison circuit 33 according to embodiment 4 may be replaced with the comparison circuit according to embodiment 5, the comparison circuit according to embodiment 6, the comparison circuit according to a modified example of embodiment 7, or the comparison circuit according to embodiment 8.

[0142] 35 is a circuit diagram showing a configuration example of an AD conversion device according to a fourteenth embodiment. The AD conversion device of FIG. 35 has the following features compared to the AD conversion device of the eleventh embodiment shown in FIG. 32: (1) a control logic circuit 35 in place of the successive approximation type control logic circuit 34; and (2) an input voltage V ｉｎｍ The sampling capacitance C of the comparison circuit 33 in place of the capacitance DA conversion circuit 41 on the ｓｐ and a DA conversion circuit 42; (3) an input voltage V ｉｎｐ The sampling capacitance C of the comparison circuit 33 in place of the capacitance DA conversion circuit 41 on the ｓｍ and the DA conversion circuit 42, and (4) the input voltage V of the comparison circuit 33 ｐ On the side, the control signal SSW ｉｎｍ and the input voltage V ｐ As the input voltage V ｐ The output voltage V of the DA conversion circuit 42 on the ｄａｃｐ and input voltage V ｉｎｍ A switch SW selectively switches between ｉｎｍ (4) The input voltage V of the comparison circuit 33 ｍ On the side, the control signal SSW ｉｎｐ and the input voltage V ｍ As the input voltage V ｍ The output voltage V of the DA conversion circuit 42 on the ｄａｃｍ and input voltage V ｉｎｐ A switch SW selectively switches between ｉｎｐ The differences will be explained below.

[0143] In FIG. 35, (1) the input voltage V ｉｎｍ The plurality of capacitors C ｏ ~C ｎ , switch SW ０ ~SW ｎ Instead of these, sampling capacitors C ｓｐ , switch SW ｉｎｍ (2) Input voltage V ｉｎｐ The plurality of capacitors C ｏ ~C ｎ , switch SW ０ ~SW ｎInstead of these, sampling capacitors C ｓｍ , switch SW ｉｎｐ (3) The DA conversion voltage V of each capacitive DA conversion circuit 41 ｄａｃｐ、 V ｄａｃｍ Instead of the output voltage V ｄａｃｐ、 V ｄａｃｍ (4) A / D conversion is performed in the same manner as in the eleventh embodiment shown in Fig. 32. The search algorithm may be a binary search as in the tenth embodiment, or may be a search performed by incrementing and decrementing from the minimum and maximum values.

[0144] The AD converter configured as above can use a DA converter circuit of another type instead of the capacitive DA converter circuit, and has the same effects as those of the eleventh embodiment shown in FIG.

[0145] In the above-described fourteenth embodiment, the comparison circuit 33 according to the fourth embodiment may be replaced with the comparison circuit according to the fifth embodiment, the comparison circuit according to the sixth embodiment, the comparison circuit according to a modified example of the seventh embodiment, or the comparison circuit according to the eighth embodiment.

[0146] (Modifications) In the above embodiment, MOS transistors are used, but the present invention is not limited to this, and other types of transistors such as bipolar transistors may also be used.

[0147] As described above in detail, the amplifier device according to the present invention can provide an amplifier device that consumes less current and has a lower offset than conventional techniques, a comparison device including the amplifier device, and an AD conversion device including the comparison device. The amplifier device is suitable for semiconductor devices equipped with multi-channel AD converters such as column-parallel AD converters.

[0148] 1 Dynamic amplifier circuit 1P, 1PA Differential amplifier 2, 2A to 2C Differential amplifier section 2D Dynamic comparison circuit 3, 3A Load circuit 4 Adder 5 Offset adjustment circuit 10, 10A to 10G Control circuit 11 Memory 12 Comparator 22 Latch circuit 23 Voltage input latch circuit 33 Comparison circuit 34 SAR control logic circuit 35 Control logic circuit 40 Capacitive DA conversion circuit 41 Capacitive DA conversion circuit 42 DA conversion circuit Cｓｐ , C ｓｍ , C ＬＰ , C ＬＭ , C ｓ , C ｓｐ２ , C ｓｍ２ , C ０ ~C ｎ , Capacitor I ｔａｉｌ Tail current source M １ ~M ３２ MOS transistor SW ａｚｐｍ , SW ａｚｍｐ , SW ｌｏａｄ１ , SW ｌｏａｄ２ , SW ｔａｉｌ , SW ｉｎ , SW ｉｎｐ , SW ｉｎｍ , SW ｉｎｐ , SW ｉｎｍ , SW ｉｐｍｐ , SW ｉｐｍｍ , SW ｉｐｔａｉｌ , SW ｌａｔｐ , SW ｌａｔｍ , SW ｏｍ , SW ｏｐ , SW ａｚｐｍ２ , SW ａｚｍｐ２ , SW ｌｐｍｐｍ , SW ｌｐｍｍｐ , SW ０ ~SW ｎ switch

Claims

1. An amplifying device comprising: a differential amplifier having first and second input terminals and first and second inverting output terminals; first and second sampling capacitors connected to the first and second input terminals of the differential amplifier, respectively; first and second switches short-circuiting the first and second input terminals and the first and second inverting output terminals of the differential amplifier, respectively; and a control circuit for controlling the operation of the amplifying device, wherein the differential amplifier comprises: an input differential pair including a pair of transistors; a current source; a third switch inserted between the source of the input differential pair and the current source; and first and second output capacitors connected to the first and second inverting output terminals of the differential amplifier, respectively; the amplifying device comprises: a load circuit connected to the first and second inverting output terminals of the differential amplifier; fourth and fifth switches connecting the first and second inverting output terminals of the differential amplifier to a predetermined fixed potential; and sixth and seventh switches for connecting or disconnecting the load circuit from the first and second inverting output terminals of the differential amplifier, and the control circuit (1) a sampling operation that controls the third switch and the sixth and seventh switches to connect the load circuit and the current source to the differential amplifier, controls the first and second switches to short-circuit the first and second input terminals and the first and second inverting output terminals of the differential amplifier and then open them, and holds the first and second input voltages and the error of the differential amplifier in the first and second sampling capacitors, thereby canceling out the error of the differential amplifier; (2) a reset operation that controls the third switch and the sixth and seventh switches to disconnect the load circuit and the current source after the sampling operation, and controls the fourth and fifth switches to connect the first and second inverting output terminals to a fixed potential; (3) after the reset operation, controlling the third switch to connect the differential amplifier to the current source, setting the first and second inverting output terminals of the differential amplifier to high impedance, and integrating the first and second output capacitors of the differential amplifier by either charging or discharging according to the first and second input voltages of the differential amplifier, thereby amplifying the difference between the second input voltage and the first input voltage after the sampling operation;An amplification device that performs the above.

2. The amplifier device according to claim 1, wherein the load circuit further comprises a variable resistance circuit.

3. The amplifier according to claim 2, further comprising: a comparator that compares first and second inverted output voltages from the first and second inverted output terminals of the differential amplifier and outputs a comparison result signal; the control circuit calibrates the offset voltage of the differential amplifier by adjusting the variable resistor circuit based on the comparison result signal of the comparator, and outputs a calibrated value; and the amplifier further comprises a storage device that saves the calibrated value from the control circuit and reads out the calibrated value after the calibration.

4. The amplifier device according to any one of claims 1 to 3, wherein the control circuit switches to at least one of the following operations after the operation from the sampling operation to the integration: (1) performing the reset operation of the differential amplifier during the sampling operation and performing an amplification operation from the sampling operation to the integration, or (2) performing an amplification operation during the sampling operation and after the sampling operation, connecting the load circuit and the current source and amplifying the first and second input voltages.

5. A comparison device comprising: the amplifying device according to any one of claims 1 to 3; and a differential latch circuit connected to the first and second inverted output terminals of the differential amplifier, for comparing the first and second inverted output voltages from the first and second inverted output terminals of the differential amplifier, and for outputting a comparison result voltage.

6. The comparison device according to claim 5, wherein, after the operation from the sampling operation to the integration, the control circuit switches to at least one of the following operations: (1) performing the reset operation of the differential amplifier during the sampling operation and performing an amplification operation from the sampling operation to the integration, and (2) performing an amplification operation during the sampling operation and after the sampling operation, connecting the load circuit and the current source and amplifying the first and second input voltages.

7. A comparison device comprising: an amplifier device according to any one of claims 1 to 3; and a comparison device according to claim 5 connected downstream of the amplifier device.

8. An amplification system comprising: an amplifier according to any one of claims 1 to 3; and another amplifier according to any one of claims 1 to 3 connected downstream of the amplifier.

9. An amplification system comprising: an amplifier device according to any one of claims 1 to 3; and a preamplifier connected in front of the amplifier device.

10. A comparison device comprising: the comparison device according to claim 5; and a preamplifier connected in a stage preceding the amplification device.

11. A comparison device comprising: a first amplifying device as defined in any one of claims 1 to 3; a second amplifying device connected downstream of said first amplifying device and including a differential amplifier; and a differential latch circuit connected to first and second inverting output terminals of the differential amplifier of said second amplifying device, for comparing first and second inverted output voltages from the first and second inverting output terminals of said differential amplifier and outputting a comparison result voltage, wherein said control circuit further comprises switch means for switching whether or not to bypass said second amplifying device.

12. An AD conversion device comprising: the comparison device according to claim 5; a capacitive DA conversion circuit provided in place of the second sampling capacitor, which converts a digital input signal into a predetermined analog output voltage and outputs it to the second input terminal of the differential amplifier; and a successive approximation control logic circuit which generates the digital input signal that controls the capacitive DA conversion circuit based on a comparison result voltage of the comparison device, wherein the AD conversion device holds an input voltage in the first sampling capacitor, and the comparison device compares the input voltages of the differential amplifier and outputs a comparison result voltage.

13. An AD conversion device comprising: the comparison device according to claim 5; a capacitive DA conversion circuit provided in place of the second sampling capacitor, which holds the potential difference between the second inverted output voltage of the differential amplifier during the sampling operation and the input voltage as a hold voltage, converts a digital input signal to a predetermined analog output voltage based on the input voltage, adds the hold voltage and the analog output voltage, and outputs the sum to the second input terminal of the differential amplifier; and a successive approximation control logic circuit which generates the digital input signal to control the capacitive DA conversion circuit based on the comparison result voltage of the comparison device, wherein the AD conversion device holds the first inverted output voltage of the differential amplifier during the sampling operation in the first sampling capacitor, and the comparison device compares the input voltages of the differential amplifier and outputs the comparison result voltage.

14. An AD conversion device comprising: the comparison device according to claim 5; first and second capacitive DA conversion circuits which, instead of the first and second sampling capacitors, hold the potential differences between the first and second inverted output voltages of the differential amplifier during the sampling operation and the first and second input voltages as first and second holding voltages, respectively, convert the first and second digital input signals to predetermined first and second analog voltages based on the input voltages, add the first and second analog voltages and the first and second held voltages, and output the sum to the first and second input terminals of the differential amplifier, respectively; and a successive approximation control logic circuit which generates the first and second digital input signals that control the first and second capacitive DA conversion circuits based on the comparison result voltage of the comparison device, wherein the comparison device compares the input voltages of the differential amplifier and outputs the comparison result voltage.

15. An AD conversion device comprising: the comparison device according to claim 5; a DA conversion circuit that converts a digital input signal into a predetermined analog output voltage and outputs it to the comparison device; and a control logic circuit that generates the digital input signal that controls the DA conversion circuit based on the comparison result voltage of the comparison device, wherein the comparison device compares the input voltage with the analog output voltage of the DA conversion circuit and outputs the comparison result voltage.

16. An AD conversion device comprising: the comparison device according to claim 5; a DA conversion circuit that converts a digital input signal into a predetermined analog output voltage and outputs it to the comparison device; and a control logic circuit that generates the digital input signal to control the DA conversion circuit based on the comparison result voltage of the comparison device, wherein the AD conversion device holds in the first sampling capacitor a first inverted output voltage of the differential amplifier during the sampling operation, and holds in the second sampling capacitor a potential difference between the second inverted output voltage of the differential amplifier during the sampling operation and an input voltage, and the comparison device compares the input voltages of the differential amplifier and outputs a comparison result voltage.

17. An AD conversion device comprising: the comparison device of claim 5; first and second DA conversion circuits that convert first and second digital input signals into predetermined first and second analog output voltages, respectively, and output them to the comparison device; and a control logic circuit that generates the first and second digital input signals that control the first and second DA conversion circuits based on the first and second comparison result voltages of the comparison device, wherein the AD conversion device holds in the first sampling capacitor a potential difference between a first inverted output voltage and a first input voltage of the differential amplifier during the sampling operation, and holds in the second sampling capacitor a potential difference between a second inverted output voltage and a second input voltage of the differential amplifier during the sampling operation, and the comparison device compares the input voltages of the differential amplifier and outputs a comparison result voltage.

18. An amplification method for an amplifier comprising: a differential amplifier having first and second input terminals and first and second inverting output terminals; first and second sampling capacitors connected to the first and second input terminals of the differential amplifier, respectively; first and second switches short-circuiting the first and second input terminals and the first and second inverting output terminals of the differential amplifier, respectively; and a control circuit for controlling the operation of the amplifier, wherein the differential amplifier comprises: an input differential pair including a pair of transistors; a current source; a third switch inserted between the source of the input differential pair and the current source; and first and second output capacitors connected to the first and second inverting output terminals of the differential amplifier, respectively; the amplifier comprises: a load circuit connected to the first and second inverting output terminals of the differential amplifier; fourth and fifth switches connecting the first and second inverting output terminals of the differential amplifier to a predetermined fixed potential; and sixth and seventh switches for connecting or disconnecting the load circuit from the first and second inverting output terminals of the differential amplifier; (1) controlling the third switch and the sixth and seventh switches to connect the load circuit and the current source to the differential amplifier, controlling the first and second switches to short-circuit and then open the first and second input terminals and the first and second inverting output terminals of the differential amplifier, and holding the first and second input voltages and the error of the differential amplifier in the first and second sampling capacitors, thereby executing a sampling operation to cancel the error of the differential amplifier; (2) after the sampling operation, controlling the third switch and the sixth and seventh switches to disconnect the load circuit and the current source, and executing a reset operation to control the fourth and fifth switches to connect the first and second inverting output terminals to a fixed potential;(3) after the reset operation, controlling the third switch to connect the differential amplifier to the current source, setting the first and second inverting output terminals of the differential amplifier to high impedance, and integrating the first and second output capacitors of the differential amplifier by either charging or discharging according to the first and second input voltages of the differential amplifier, thereby performing an amplification operation to amplify the difference between the second input voltage and the first input voltage after the sampling operation.

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