Solid-state imaging element

Abstract

[Problem] To suppress noise. [Solution] A solid-state imaging element according to the present invention comprises: a photoelectric conversion unit that converts light into electric charge; a storage unit that temporarily stores the electric charge; a transfer unit that transfers the electric charge to the storage unit; and a plurality of selection transistors that are connected between the storage unit and each of a plurality of vertical signal lines, and that select whether to output a signal based on the electric charge stored in the storage unit.

Description

solid-state imaging device

[0001] FIELD An embodiment of the present disclosure relates to a solid-state imaging device.

[0002] In general, imaging elements such as CMOS (Complementary Metal Oxide Semiconductor) image sensors and CCD (Charge Coupled Device) sensors are widely used in digital still cameras, digital video cameras, etc. Improvements in the characteristics of imaging elements, such as an expansion of the dynamic range, are desired (see, for example, Patent Document 1).

[0003] International Publication No. 2019 / 082614

[0004] However, in FD accumulation, if the dynamic range is expanded by increasing the capacity, there is a possibility that noise will increase.

[0005] Therefore, the present disclosure provides a solid-state imaging device that can suppress noise.

[0006] In order to solve the above problems, according to the present disclosure, there is provided a solid-state imaging element including: a photoelectric conversion unit that converts light into electric charges; a storage unit that temporarily stores the electric charges; a transfer unit that transfers the electric charges to the storage unit; and a plurality of selection transistors that are connected between the storage unit and each of a plurality of vertical signal lines and that select whether or not to output a signal based on the electric charges stored in the storage unit.

[0007] A signal based on the charge stored in the storage section may be read out during a shutter period via a first vertical signal line corresponding to a first selection transistor.

[0008] A signal based on the charge stored in the storage section may be read out during a read period via a second vertical signal line different from the first vertical signal line, which corresponds to a second selection transistor different from the first selection transistor.

[0009] The charges in the storage section may not be reset during the period from when they are read out via the first vertical signal line until when they are read out via the second vertical signal line.

[0010] The image sensor may further include a signal processing unit that processes signals read out via the plurality of vertical signal lines.

[0011] The signal processing unit may perform analog-to-digital (AD) conversion on each of the signals read out via the vertical signal lines and store the converted signals.

[0012] The signal processing unit may perform CDS (Correlated Double Sampling) based on signals read out via the plurality of vertical signal lines.

[0013] The storage device may include a plurality of the storage units and a plurality of the transfer units, wherein at least one of the plurality of storage units is a capacitive element.

[0014] The capacitive element may be a MIM (Metal Insulator Metal) capacitive element.

[0015] The device may include a plurality of the storage units and a plurality of the transfer units, wherein the plurality of storage units are connected in series and store charges transferred from the photoelectric conversion unit and charges overflowing from the photoelectric conversion unit.

[0016] The pixel may include three of the storage sections and a plurality of the transfer sections, and may read out charges from the photoelectric conversion sections at each of high conversion efficiency, medium conversion efficiency, and low conversion efficiency.

[0017] The pixel may include a plurality of pixels, each of which has the photoelectric conversion unit, the storage unit, and two of the selection transistors respectively corresponding to two of the vertical signal lines provided for each pixel column.

[0018] The image sensor may include a plurality of pixels, wherein the plurality of selection transistors of a first pixel correspond to a first signal line group including a plurality of the vertical signal lines, and the plurality of selection transistors of a second pixel in the same pixel column but a different pixel row relative to the first pixel correspond to a second signal line group including a plurality of the vertical signal lines different from the first signal line group, and signals of the first pixel and the second pixel may be read out in parallel.

[0019] The pixel may further include an amplifying transistor that amplifies a signal based on the charge stored in the storage section and outputs the amplified signal to the plurality of selection transistors, and the amplifying transistor and the plurality of selection transistors may be connected by an active region.

[0020] The image sensor may further include an amplifying transistor that amplifies a signal based on the charge stored in the storage section and outputs the amplified signal to the plurality of selection transistors, and the amplifying transistor and the plurality of selection transistors may be connected via wiring.

[0021] 1 is a diagram showing an example of the configuration of an embodiment of an imaging device to which the present technology is applied; FIG. 2 is a diagram showing an example of the circuit configuration of a pixel; FIG. 3 is a diagram showing an example of an electric charge according to a comparative example; FIG. 4 is a diagram showing an example of an electric charge according to the first embodiment; FIG. 5 is a circuit diagram showing an example of the configuration of a pixel according to the first embodiment; FIG. 6 is a timing chart showing an example of the operation of a pixel according to the comparative example; FIG. 7 is a timing chart showing an example of the operation of a pixel according to the first embodiment; FIG. 8 is a layout diagram showing an example of the planar configuration of a pixel according to the second embodiment; FIG. 9 is a layout diagram showing an example of the planar configuration of a pixel according to the third embodiment; FIG. 10 is a circuit diagram showing an example of the configuration of a pixel according to the fourth embodiment; FIG. 11 is a schematic diagram showing an example of the overall configuration of an electronic device; FIG. 12 is a block diagram showing an example of the schematic configuration of a vehicle control system; FIG. 13 is an explanatory diagram showing an example of the installation positions of an outside vehicle information detection unit and an imaging unit.

[0022] Hereinafter, an embodiment of a solid-state imaging device will be described with reference to the drawings. The following description will focus on the main components of the solid-state imaging device, but the solid-state imaging device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0023] <Configuration Example of Imaging Device> FIG. 1 shows a configuration example of an embodiment of an imaging device (solid-state imaging element) to which the present technology is applied.

[0024] 1 includes a pixel array section 3 in which pixels 2 are arranged in a two-dimensional array, and a peripheral circuit section around the pixel array section 3. The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

[0025] The pixel 2 includes a photodiode as a photoelectric conversion element and a plurality of pixel transistors, such as a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor, and is configured as a MOS transistor.

[0026] The control circuit 8 receives an input clock and data instructing the operation mode and the like, and outputs data such as internal information of the imaging device 1. That is, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. The control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0027] The vertical drive circuit 4 is configured by, for example, a shift register, selects a predetermined pixel drive line 10, supplies a pulse for driving the pixels 2 to the selected pixel drive line 10, and drives the pixels 2 row by row. That is, the vertical drive circuit 4 selects and scans each pixel 2 in the pixel array unit 3 row by row in the vertical direction, and supplies a pixel signal based on a signal charge generated in the photoelectric conversion unit of each pixel 2 according to the amount of received light to the column signal processing circuit 5 through the vertical signal line 9.

[0028] The column signal processing circuits 5 are arranged for each column of pixels 2, and perform signal processing such as noise removal for each pixel column on signals output from one row of pixels 2. For example, the column signal processing circuits 5 perform signal processing such as CDS (Correlated Double Sampling) or DDS (Double Data Sampling) for removing fixed pattern noise specific to each pixel, and AD conversion.

[0029] The horizontal drive circuit 6 is configured, for example, by a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in turn, causing each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 11.

[0030] The output circuit 7 processes and outputs signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 11. The output circuit 7 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 13 exchanges signals with the outside.

[0031] The imaging device 1 configured as above is a CMOS image sensor called a column AD type, in which a column signal processing circuit 5 that performs CDS processing or DDS processing and AD conversion processing is arranged for each pixel column.

[0032] <Example of Pixel Circuit Configuration> A description will be given of the configuration of a unit pixel provided in the pixel array section 3. The unit pixel provided in the pixel array section 3 is configured, for example, as shown in Fig. 2. In Fig. 2, parts corresponding to those in Fig. 1 are assigned the same reference numerals, and their description will be omitted as appropriate.

[0033] Pixel 2, which is a unit pixel, has a photoelectric conversion section 51, a first transfer transistor 52, a first FD (Floating Diffusion) section 53, a second transfer transistor 54, a second FD section 55, a third transfer transistor 56, a third FD section 57, an MIM (Metal-Insulator-Metal) capacitance element 58, a reset transistor 59, an amplification transistor 60, and a selection transistor 61.

[0034] For example, a plurality of drive lines are wired for each pixel row as pixel drive lines 10 for the pixels 2. Then, a drive signal TG, a drive signal FDG, a drive signal FCG, a drive signal RST, and a drive signal SEL are supplied from the vertical drive circuit 4 via the plurality of drive lines to the first transfer transistor 52, the second transfer transistor 54, the third transfer transistor 56, the reset transistor 59, and the selection transistor, respectively.

[0035] These drive signals are pulse signals that are active when high (for example, power supply voltage VDD) and inactive when low (for example, negative potential). That is, when each of the drive signals TG to SEL is at a high level, the transistor to which it is supplied is in a conductive state, i.e., an ON state, and when each drive signal is at a low level, the transistor to which it is supplied is in a non-conductive state, i.e., an OFF state.

[0036] The photoelectric conversion unit 51 is made of, for example, a PN junction photodiode, and receives incident light, performs photoelectric conversion, and accumulates the resulting electric charge.

[0037] The first transfer transistor 52 is provided between the photoelectric conversion unit 51 and the first FD unit 53, and a drive signal TG is supplied to the gate electrode of the first transfer transistor 52. When this drive signal TG becomes high level, the first transfer transistor 52 is turned on, and the charge stored in the photoelectric conversion unit 51 is transferred to the first FD unit 53 via the first transfer transistor 52.

[0038] The first FD section 53, the second FD section 55, and the third FD section 57 are each a floating diffusion region called a floating diffusion, and function as a storage section that temporarily stores transferred charges and charges that overflow from the photoelectric conversion section 51. The third FD section 57 is connected to an MIM capacitance element 58, and is configured so that the MIM capacitance element 58 functions as the third FD section 57.

[0039] The second transfer transistor 54 is provided between the first FD section 53 and the second FD section 55, and a drive signal FDG is supplied to the gate electrode of the second transfer transistor 54. When this drive signal FDG becomes high level, the second transfer transistor 54 is turned on, and the charge from the first FD section 53 is transferred to the second FD section 55 via the second transfer transistor 54.

[0040] By turning on the second transfer transistor 54, the region where charges are accumulated becomes the combined region of the first FD section 53 and the second FD section 53, and it is possible to switch the conversion efficiency when converting the charges generated in the photoelectric conversion section into voltage. The second transfer transistor 54 functions as a conversion efficiency switching transistor that switches the conversion efficiency.

[0041] The third transfer transistor 56 is provided between the second FD section 55 and the third FD section 57, and a drive signal FCG is supplied to the gate electrode of the third transfer transistor 56. When this drive signal FCG becomes high level, the third transfer transistor 56 is turned on, and the charge from the second FD section 55 is transferred to the third FD section 57 via the third transfer transistor 56.

[0042] By turning on the third transfer transistor 56, the region in which charges are accumulated becomes the combined region of the first FD section 53, the second FD section 55, and the third FD section 57, and it is possible to switch the conversion efficiency when converting the charges generated in the photoelectric conversion section into voltage. The third transfer transistor 56 functions as a conversion efficiency switching transistor that switches the conversion efficiency.

[0043] The third FD section 57 is connected to an MIM capacitance element 58. The third FD section 57 is connected to the MIM capacitance element 58, which can achieve high capacitance without sacrificing the area of ​​the Si (silicon) substrate surface on which pixel transistors are arranged, and has a larger capacitance than the first FD section 53 and the second FD section 55.

[0044] The reset transistor 59 is connected between the power supply VDD and the third FD section 57, and a drive signal RST is supplied to the gate electrode of the reset transistor 59. When the drive signal RST is set to a high level, the reset transistor 59 is turned on and the potential of the third FD section 57 is reset to the level of the power supply voltage VDD.

[0045] The amplifying transistor 60 has a gate electrode connected to the first FD section 53 and a drain connected to a power supply VDD, and serves as an input section of a readout circuit, a so-called source follower circuit, that reads out a signal corresponding to the charge held in the first FD section 53. That is, the amplifying transistor 60 has a source connected to the vertical signal line 9 via the selection transistor 61, and thereby forms a source follower circuit together with a constant current source (not shown) connected to one end of the vertical signal line 9.

[0046] The selection transistor 61 is connected between the source of the amplification transistor 60 and the vertical signal line 9, and a drive signal SEL is supplied to the gate electrode of the selection transistor 61. When the drive signal SEL is set to a high level, the selection transistor 61 is turned on and the pixel 2 is placed in a selected state. As a result, the pixel signal output from the amplification transistor 60 is output to the vertical signal line 9 via the selection transistor 61.

[0047] In the following, when each drive signal is in an active state, i.e., at a high level, it is also referred to as the drive signal being on, and when each drive signal is in an inactive state, i.e., at a low level, it is also referred to as the drive signal being off.

[0048] The pixel 2 shown in Figure 2 includes a first FD section 53, a second FD section 55, and a third FD section 57 (MIM capacitance element 58), and these FD sections are connected in series, so that the conversion efficiency when converting the charge generated in the photoelectric conversion section into a voltage can be switched between three levels.

[0049] The high conversion efficiency (HCG) is composed of the first FD section 53. The medium conversion efficiency (MCG) is composed of (the first FD section 53 + the second FD section 55). The low conversion efficiency (LCG) is composed of (the first FD section 53 + the second FD section 55 + the third FD section 57 (= the MIM capacitance element 58)).

[0050] When the first transfer transistor 52 is turned on, the charge accumulated in the photoelectric conversion unit 51 is received by the first FD unit 53 (high conversion efficiency) or (first FD unit 53 + second FD unit 55) (medium conversion efficiency) and output.

[0051] At times of high illuminance, the charge accumulated in the photoelectric conversion section 51 overflows beyond the first transfer transistor 52 to the first FD section 53 side, and is accumulated in the first FD section 53, the second FD section 55, and the third FD section 57 (MIM capacitance element 58).

[0052] When the received light amount is a small signal, a high conversion efficiency is achieved in which charge is accumulated in the first FD section 53, and when the received light amount is a large signal, a low conversion efficiency is achieved in which charge is accumulated in (first FD section 53 + second FD section 55 + third FD section 57 (= MIM capacitance element 58)). Here, an intermediate conversion efficiency is further provided between the high conversion efficiency and the low conversion efficiency, and a conversion efficiency is provided in which charge is accumulated in (first FD section 53 + second FD section 55).

[0053] The electric charges that have overflowed the photoelectric conversion unit 51 and accumulated in the first FD unit 53, the second FD unit 55, and the third FD unit 57 are received by (the first FD unit 53 + the second FD unit 55 + the third FD unit 57 (= MIM capacitance element 58)) together with the electric charges accumulated in the photoelectric conversion unit 51 and are output.

[0054] The readouts of the high conversion efficiency, medium conversion efficiency, and low conversion efficiency signals are each AD converted separately, and which readout signal to use is determined based on the amount of each readout signal. At the junction between the high conversion efficiency signal and the medium conversion efficiency signal, or the junction between the medium conversion efficiency signal and the low conversion efficiency signal, the two readout signals may be blended and used. By using the blended signal, image quality degradation at the junction is suppressed.

[0055] In this way, by providing three FD sections, it is possible to achieve a high conversion efficiency of 160uV / e, a medium conversion efficiency of 80uV / e, and a low conversion efficiency of 10uV / e, thereby achieving a configuration that uses three conversion efficiencies. This makes it possible to suppress the S / N step at the connecting section.

[0056] <Capacitance Element> Although the description will be continued using the MIM capacitance element 58 as an example here, other capacitance elements may be used instead of the MIM capacitance element. For example, it may be a MOM (Metal Oxide Metal) capacitance element, a poly-poly capacitance element (a capacitance element in which both opposing electrodes are made of polysilicon), or an additional capacitance including a parasitic capacitance formed by wiring.

[0057] <Noise> Image sensors using LOFIC (Lateral Overflow Integration Capacitor) and MIM (Metal / Insulator / Metal) capacitance elements 58 for floating diffusion (FD) detect signals using DDS drive as the difference between the FD voltage when overflowing into the FD and the FD voltage after FD reset. In this case, compared to CDS drive, kTC noise, or kTC noise, occurs because variations in the reset level after resetting cannot be canceled out. It is known that kTC noise increases in proportion to √kT / C, and in DDS drive, this noise occurs twice. Therefore, when switching from CDS to DDS drive, a decrease in S / N ratio known as a transition step occurs, and if this value is large, it significantly degrades image quality. In addition to kTC noise, the transition step also includes circuit noise and FD dark current.

[0058] Here, if we consider further expanding the dynamic range, it will be necessary to further increase the capacity of the MIM capacitance element 58. However, since the kTC noise mentioned above is inversely proportional to C, the noise in terms of voltage will improve, but in reality, the conversion efficiency will also decrease, so the noise in terms of the number of electrons will worsen by a factor of √2.

[0059] In other words, if the capacitance of the MIM element 58 is increased to widen the dynamic range, the kTC noise worsens, and the connecting S / N also deteriorates accordingly, resulting in a problem that the image quality does not improve.

[0060] Fig. 3 is a diagram showing an example of charge according to a comparative example. Fig. 3 is a diagram showing overflow driving using an MIM capacitance element 58 in the case of low conversion efficiency (LCG). Fig. 3 also shows DDS driving by FD accumulation.

[0061] First, after the shutter is closed, the FD voltage is accumulated in the charge accumulation region. Note that the charge accumulation region at low conversion efficiency is the combined region of the first FD section 53, the second FD section 55, and the third FD section 57, as described above.

[0062] Thereafter, during the accumulation period, the FD dark current and signal charge are accumulated in the charge accumulation region.

[0063] After that, after the accumulation period ends, the transfer transistor 52 is turned on, so that the charge accumulated in the photoelectric conversion unit 51 (PD: Photo Diode) is transferred to the charge accumulation region.

[0064] Thereafter, the transfer transistor 52 is turned off, and the charge stored in the charge storage region is read out. That is, D-phase data is acquired during the D-phase period.

[0065] Thereafter, during the MIM reset period, the reset transistor 59 is turned on, thereby resetting the charge stored in the charge storage region including the MIM capacitance element 58.

[0066] Thereafter, during the P-phase period, the FD voltage (P-phase data) stored in the charge storage region is acquired.

[0067] If the FD voltage after shutter release and the FD voltage after MIM reset do not match, kTC noise will occur. In other words, with LCG, CDS drive is difficult and kTC noise cannot be canceled. Also, FD dark current cannot be canceled.

[0068] As shown in Figure 3, in DDS drive operation, P-phase data is acquired after D-phase data and the difference is observed, so kTC noise occurs due to differences in the FD reset level. In other words, kTC noise occurs when the FD voltage after shutter release does not match the FD voltage after MIM reset. In conventional CDS drive, this noise is canceled because the difference between P-phase data and D-phase data can be acquired for the FD after reset. This noise is called kTC noise. In LCG, CDS drive is difficult and kTC noise cannot be canceled. When attempting to increase the saturation signal level, the larger the MIM capacitance (C), the worse the electron count tends to be. It is known that there is a trade-off between increasing C and expanding the dynamic range.

[0069] 4 is a diagram showing an example of charges according to the first embodiment, illustrating overflow driving and noise removal driving using an MIM capacitance element 58 in the case of low conversion efficiency (LCG).

[0070] First, after the shutter is closed, the FD voltage stored in the charge storage region is acquired as P-phase data.

[0071] Thereafter, during the accumulation period, the FD dark current and signal charge are accumulated in the charge accumulation region.

[0072] After that, after the accumulation period ends, the transfer transistor 52 is turned on, so that the charge accumulated in the photoelectric conversion unit 51 is transferred to the charge accumulation region.

[0073] Thereafter, the transfer transistor 52 is turned off, and the charge stored in the charge storage region is read out. That is, D-phase data is acquired during the D-phase period.

[0074] The reason DDS drive is necessary is because FD accumulation is used. In other words, as shown in Figure 4, if P-phase data is acquired at the shutter timing and that data is stored, the difference can be taken at the D-phase timing, making it possible to achieve CDS drive even with FD accumulation. In this case, the kTC noise generated in the FD section can be canceled, so even if C is enlarged, the kTC noise does not worsen, and the trade-off can be avoided.

[0075] Furthermore, normally the CDS period would be longer, which could have the effect of worsening the FD dark current, but since it is originally intended to be driven by DDS, this effect can be suppressed.

[0076] FIG. 5 is a circuit diagram showing an example of the configuration of the pixel 2 according to the first embodiment.

[0077] The selection transistor 61 includes a plurality of selection transistors connected between the FD section and each of the plurality of vertical signal lines, and selects whether or not to output a signal based on the charge accumulated in the FD section. More specifically, the selection transistor 61 includes, for example, two selection transistors 611 and 612.

[0078] The vertical signal line 9 includes, for example, two vertical signal lines 91 and 92. The selection transistor 611 is connected between the source of the amplification transistor 60 and the vertical signal line 91, and a drive signal SEL1 is supplied to the gate electrode of the selection transistor 611. The selection transistor 612 is connected between the source of the amplification transistor 60 and the vertical signal line 92, and a drive signal SEL2 is supplied to the gate electrode of the selection transistor 612. The vertical signal line 91 is, for example, a vertical signal line for a read timing line, and the vertical signal line 92 is, for example, a vertical signal line dedicated to shutter timing.

[0079] FIG. 5 is a circuit diagram of this embodiment, in which the selection transistor 61 is branched into two systems from the amplification transistor 60 to the selection transistor 61.

[0080] To achieve the driving of this embodiment, it is necessary to provide multiple selection transistors 61 for one amplification transistor 60, as shown in Figure 5. When acquiring a signal at the shutter timing, other rows are at the read timing, so if the same vertical signal line 9 (VSL wiring) is used, the signal cannot be acquired. Therefore, two selection transistors 61 connected to the amplification transistor 60 are provided. The driving proposed in this embodiment can be achieved by dividing the selection transistors into one 611 that is driven at the read timing and one 612 that is driven at the shutter timing.

[0081] FIG. 6A is a timing chart showing an example of the operation of pixel 2 according to the comparative example.

[0082] 6A shows a timing chart of the pixel 2 according to the comparative example shown in FIG. 2. Therefore, one vertical signal line 9 is provided for the pixel 2.

[0083] The upper part of Fig. 6A shows a timing chart for shutter timing. Drive signals SSEL, SRST, SFCG, SFDG, and STG represent the drive signals SEL, RST, FCG, FDG, and TG at the shutter timing. The lower part of Fig. 6A shows read timing. Drive signals RSEL, RRST, RFCG, RFDG, and RTG represent the drive signals SEL, RST, FCG, FDG, and TG at the read timing.

[0084] First, the shutter timing will be described. Since the drive signal SSEL is in the OFF state, the selection transistor 61 is in the OFF state.

[0085] When the shutter is operated, the voltage MIMVDD supplied to the MIM capacitance element 58, the drive signal SRST supplied to the reset transistor 59, the drive signal SFCG supplied to the third transfer transistor 56, the drive signal SFDG supplied to the second transfer transistor 54, and the drive signal STG supplied to the first transfer transistor 52 are turned on. Each drive signal is turned on for a predetermined period and then turned off.

[0086] Next, the read timing will be described. Since the drive signal RSEL is in the ON state, the selection transistor 61 is in the ON state.

[0087] When the exposure time has elapsed, an MCG (medium conversion efficiency) reset period is provided, followed by an HCG (high conversion efficiency) reset period. From the point when the HCG (high conversion efficiency) reset period begins, the supply voltage VDD to the MIM capacitance element 58 is turned on.

[0088] Before the start of the MCG reset period, the drive signal FDG is turned on for a predetermined period. MCG (medium conversion efficiency) is a case in which the first FD section 53 and the second FD section 55 are used, and during the MCG reset period, the first FD section 53 and the second FD section 55 are reset. The drive signal RSEL is turned on, thereby resetting the MCG. In other words, the P-phase data of the MCG is read out. After the MCG reset, the drive signal RFDG is turned off, thereby resetting the HCG. In other words, the P-phase data of the HCG is read out.

[0089] When readout from the photodiode (PD) begins, the drive signal RTG supplied to the first transfer transistor 52 is turned on for a predetermined period. Readout from the photodiode is performed by CDS (correlated double sampling) drive. CDS drive resets the FD to a predetermined potential and reads out the predetermined potential as a reset potential, then transfers the signal charge accumulated in the PD to the FD and reads out the signal charge of the FD as a signal level.

[0090] As will be described later, after reading from the photodiode by CDS driving, reading from the photodiode and the MIM capacitance element 58 by DDS (double data sampling) driving is performed. DDS driving is a driving method in which the signal charge held or accumulated in the FD is read out as a signal level, and then the FD is reset to a predetermined potential and the predetermined potential is read out as a reset level.

[0091] Since the readout from the PD is performed by CDS drive, as described above, an MCG reset period and an HCG reset period are provided, and a reset signal at the time of medium conversion efficiency and a reset signal at the time of high conversion efficiency are acquired during each period. The reset potential at this time is the potential MINVDD.

[0092] Then, the HCG readout period begins. For a predetermined time before the HCG readout period begins, the drive signal RTG is turned on, the first transfer transistor 52 is turned on, and charges are transferred from the photoelectric conversion unit 51 to the first FD unit 53.

[0093] When the drive signal RTG is returned to OFF, the HCG (high conversion efficiency) readout period begins. During the HGC readout period, the selection transistor 61 is in an ON state. Since the high conversion efficiency is formed in the first FD section 53, during the HGC readout period, the charge accumulated in the first FD section 53 is read out. In other words, the D-phase data of the HCG is read out.

[0094] The drive signal RFDG is turned on to turn on the second transfer transistor 54. By turning on the second transfer transistor 54, a state is created in which charges flow through the first FD section 53 and the second FD section 55.

[0095] After that, the MCG (medium conversion efficiency) readout period starts. When the MCG readout period starts, the selection transistor 61 is in the on state, and the charges stored in the first FD section 53 and the second FD section 55 are read out. In other words, the D-phase data of the MCG is read out.

[0096] After the MCG readout period ends, the drive signal RFCG is turned on. Since the drive signal RFDG is maintained in the on state, the second transfer transistor 54 and the third transfer transistor 56 are turned on, and charges are transferred to the first FD portion 53, the second FD portion 55, and the third FD portion 57 (MIM capacitance element 58).

[0097] Thereafter, the LCG (low conversion efficiency) readout period begins. Since the low conversion efficiency is formed by (the first FD section 53 + the second FD section 55 + the third FD section 57 (the MIM capacitance element 58)), during the LCG readout period, the charges stored in (the first FD section 53 + the second FD section 55 + the third FD section 57 (the MIM capacitance element 58)) are read out. In other words, the D-phase data of the LCG is read out.

[0098] Since reading from the PD and MIM capacitance element 58 is performed by DDS driving, a signal is read out during an LCG readout period, and then an LCG reset period is provided during which a reset signal is read out.

[0099] At the end of the LCG readout period, the drive signal RRST is turned on for a predetermined time, turning on the reset transistor 59 and resetting the first FD section 53, the second FD section 55, and the third FD section 57. The reset potential at this time is the potential VDD.

[0100] After that, the reset signal is read out during the LCG reset period. That is, the P-phase data of the LCG is read out. During the LCG reset period, the drive signals RSEL, RFCG, and RFDG are in an on state.

[0101] When the LCG reset period ends, the drive signal RSEL is returned to off. By performing this series of operations, a signal during HCG (high conversion efficiency), a signal during MCG (medium conversion efficiency), and a signal during LCG (low conversion efficiency) are read out.

[0102] According to the configuration and operation of the pixel 2 as described above, Qs (amount of saturated charge) can be increased by overflow driving using the MIM capacitance element 58 as the capacitance element.

[0103] FIG. 6B is a timing chart showing an example of the operation of the pixel 2 according to the first embodiment.

[0104] 6B shows a timing chart of the pixel 2 according to the first embodiment shown in Fig. 5. Therefore, two vertical signal lines 91 and 92 are provided for a certain pixel 2. The vertical signal line 91 is, for example, a vertical signal line for a read timing line, and the vertical signal line 92 is, for example, a vertical signal line dedicated to shutter timing.

[0105] 6B shows that, for two pixels 2 in the same pixel column but different pixel rows, for example, the shutter timing of the upper pixel 2 and the read timing of the lower pixel 2 are performed simultaneously. In the other pixels 2 in the same pixel column, the selection transistors 611 and 612 are in the off state. Also, in one pixel 2, the read timing is performed after the shutter timing.

[0106] Furthermore, "P phase / D phase" shown in FIG. 6B indicates that P phase data is acquired at the shutter timing, and D phase data is acquired at the read timing.

[0107] The upper part of Fig. 6B shows shutter timing. Drive signals SSEL, SRST, SFCG, SFDG, and STG represent drive signals SEL2, RST, FCG, FDG, and TG at shutter timing. The lower part of Fig. 6B shows read timing. Drive signals RSEL, RRST, RFCG, RFDG, and RTG represent drive signals SEL1, RST, FCG, FDG, and TG at read timing.

[0108] First, the difference in shutter timing from Fig. 6A will be described. Since the drive signal SSEL, that is, the drive signal SEL2, is in the ON state, the selection transistor 612 is in the ON state.

[0109] After the shutter operation, the drive signal SFDG is turned on to turn on the second transfer transistor 54. The drive signal SFDG is turned on at the same timing as the drive signal RFDG is turned on at the read timing, for example.

[0110] Thereafter, the drive signal SFCG is turned on. Since the drive signal SFDG is maintained in the on state, the second transfer transistor 54 and the third transfer transistor 56 are turned on, and charge is transferred to the first FD portion 53, the second FD portion 55, and the third FD portion 57 (MIM capacitance element 58). The drive signal SFCG is turned on, for example, at the same timing as the drive signal RFCG is turned on during the read timing.

[0111] Also, for example, the drive signal STG is turned on at the same timing as the drive signal SFCG is turned on, and after a predetermined period, the drive signal STG is turned off.

[0112] Thereafter, the drive signal SRST is turned on for a predetermined time, turning on the reset transistor 59 and resetting the first FD section 53, the second FD section 55, and the third FD section 57. The reset potential at this time is the potential VDD.

[0113] After that, the reset signal is read out during the LCG reset period, that is, the P-phase data of the LCG is read out.

[0114] When the LCG reset period ends, the drive signal SSEL, that is, the drive signal SEL2, is turned back to OFF.

[0115] In this way, the P-phase data of the LCG shown in FIG. 4 is acquired during the LCG reset period at the shutter timing.

[0116] Next, the difference in read timing from Fig. 6A will be described. Since the drive signal RSEL, that is, the drive signal SEL1, is in the ON state, the selection transistor 611 is in the ON state.

[0117] 6B, there is no LCG reset period after the LCG read period in the read timing. Therefore, the drive signal RRST does not need to be turned on after the LCG read period. Also, after the LCG read period, that is, after the D-phase data of the LCG is acquired, the drive signals RFDG and RFCG are turned off.

[0118] In the drive timing shown in FIG. 6B, the drive signal SSEL (drive signal SEL2) is turned on at the shutter timing, and the final reset for acquiring P-phase data at the shutter timing shown in FIG. 6A is omitted.

[0119] Therefore, a signal based on the charge accumulated in the FD section is read out during the shutter period via the vertical signal line 92 corresponding to the selection transistor 612. During the read period, a signal based on the charge accumulated in the FD section is read out via a vertical signal line 91 other than the vertical signal line 92, which corresponds to a selection transistor 611 other than the selection transistor 612. The charge in the FD section is not reset during the period from when it is read out via the vertical signal line 92 to when it is read out via the vertical signal line 91.

[0120] As described above, according to the first embodiment, the multiple selection transistors 611 and 612 are connected between the storage unit (FD unit) and each of the multiple vertical signal lines 91 and 92, and select whether or not to output a signal based on the charge stored in the storage unit. This branches the circuit at the selection transistors 611 and 612, making it possible to acquire necessary signal data according to the timing. As a result, noise can be suppressed.

[0121] By acquiring P-phase data during the shutter period and storing that data, CDS driving becomes possible even with FD accumulation. This makes it possible to prevent kTC noise from worsening even if C is increased to expand the dynamic range. In other words, noise can be suppressed.

[0122] Furthermore, in the first embodiment, CDS driving is possible in a configuration that is premised on reading out the signal of the MIM capacitance element 58 by DDS driving.

[0123] Second Embodiment Fig. 7 is a layout diagram showing an example of the planar configuration of a pixel 2 according to a second embodiment. Fig. 7 is a plan view of the surface of a silicon substrate on which transistors are arranged. In the second embodiment, details of the layout of the pixel 2 will be described.

[0124] A gate electrode TG of the first transfer transistor 52 is formed near the center of the pixel 2, and a gate electrode FDG of the second transfer transistor 54 is formed on the left side of the gate electrode TG in the drawing. A first FD portion 53 (not shown) formed of an N+ diffusion layer is provided in the silicon substrate between the gate electrodes TG and FDG.

[0125] A gate electrode FCG of a third transfer transistor 56 is formed above the second transfer transistor 54 in the drawing. A second FD portion 55 is provided between the second transfer transistor 54 and the third transfer transistor 56. A gate electrode RST of a reset transistor 59 is formed on the right side of the third transfer transistor 56 in the drawing. A third FD portion 57 is formed between the third transfer transistor 56 and the reset transistor 59, and a via (wiring) connected to an MIM capacitance element 58 is formed.

[0126] A gate electrode AMP of the amplifier transistor 60 is formed below the reset transistor 59 in the drawing. A gate electrode SEL1 of the select transistor 611 and a gate electrode SEL2 of the select transistor 612 are formed on the left side of the amplifier transistor 60 in the drawing. A VSS region 72 (not shown) made of a P+ diffusion layer is formed on the lower left side in the drawing.

[0127] A branch is made from the amplifying transistor 60 in the active region and connected to two selection transistors 611 and 612 .

[0128] As in the second embodiment, the amplifier transistor 60 and the selection transistors 611 and 612 may be connected by the active area (AA). In this case, the same effects as in the first embodiment can be obtained.

[0129] <Third Embodiment> Fig. 8 is a layout diagram showing an example of the planar configuration of a pixel 2 according to a third embodiment. Fig. 8 is a plan view of the surface of a silicon substrate on which transistors are arranged. In the third embodiment, details of the layout will be described. In the third embodiment, the configuration of the selection transistor and its periphery is different from that of the second embodiment.

[0130] Two island-shaped active regions are provided corresponding to the selection transistors 611 and 612. The two island-shaped active regions are electrically connected to the amplifier transistor 60 through wiring including vias and the like.

[0131] As in the third embodiment, the active area (AA) may be divided, and the amplification transistor 60 may be connected to the selection transistors 611 and 612 via wiring. In this case, too, the same effects as in the first embodiment can be obtained.

[0132] 9 is a circuit diagram showing an example of the configuration of a pixel 2 according to a fourth embodiment. The fourth embodiment differs from the first embodiment in that simultaneous readout of other rows is performed.

[0133] A signal line group 9G2 is further provided, which is different from the signal line group 9G1 that is the vertical signal lines 9. Like the signal line group 9G1, the signal line group 9G2 includes two vertical signal lines 91 and 92. The vertical signal line 91 is, for example, a vertical signal line for use as a read timing line, and the vertical signal line 92 is, for example, a vertical signal line dedicated to shutter timing.

[0134] The selection transistor 61 of a certain pixel 2 is connected to a signal line group 9G1. Other pixels 2 in the same pixel column are connected to a signal line group 9G2 that is different from the signal line group 9G1. The signals of the certain pixel 2 and the other pixels 2 are read out in parallel. This enables simultaneous readout of the certain pixel 2 and the other pixels 2 (simultaneous readout of other rows). As a result, readout can be performed in a shorter time.

[0135] 9 shows two signal line groups 9G1 and 9G2, but three or more signal line groups including vertical signal lines dedicated to read timing and vertical signal lines dedicated to shutter timing may be provided.

[0136] As in the fourth embodiment, in order to simultaneously read out other rows, a plurality of combinations of two systems of select transistors and vertical signal lines may be provided. In this case, the same effects as those of the first embodiment can be obtained. Note that the fourth embodiment may be combined with the second or third embodiment.

[0137] <Application Example to Electronic Device> FIG. 10 is a block diagram showing a configuration example of a camera 2000 as an electronic device to which the present technology is applied.

[0138] The camera 2000 includes an optical unit 2001 including a lens group and the like, an imaging device 2002 to which the imaging device 1 described above or the like (hereinafter referred to as the imaging device 1, etc.) is applied, and a DSP (Digital Signal Processor) circuit 2003, which is a camera signal processing circuit. The camera 2000 also includes a frame memory 2004, a display unit 2005, a recording unit 2006, an operation unit 2007, and a power supply unit 2008. The DSP circuit 2003, the frame memory 2004, the display unit 2005, the recording unit 2006, the operation unit 2007, and the power supply unit 2008 are connected to one another via a bus line 2009.

[0139] The optical unit 2001 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging device 2002. The imaging device 2002 converts the amount of incident light formed on the imaging surface by the optical unit 2001 into an electrical signal on a pixel-by-pixel basis and outputs the signal as a pixel signal.

[0140] The display unit 2005 is formed of a panel display device such as a liquid crystal panel or an organic EL panel, and displays moving images or still images captured by the imaging device 2002. The recording unit 2006 records the moving images or still images captured by the imaging device 2002 on a recording medium such as a hard disk or semiconductor memory.

[0141] An operation unit 2007, under the operation of a user, issues operation commands for various functions of the camera 2000. A power supply unit 2008 appropriately supplies various types of power to the DSP circuit 2003, frame memory 2004, display unit 2005, recording unit 2006, and operation unit 2007 as operating power sources.

[0142] As described above, by using the imaging device 1 described above as the imaging device 2002, it is possible to expect to obtain a good image.

[0143] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0144] FIG. 11 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0145] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 11, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0146] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0147] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0148] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0149] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0150] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0151] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0152] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0153] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0154] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 11, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0155] FIG. 12 is a diagram showing an example of the installation position of the imaging unit 12031.

[0156] In FIG. 12, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0157] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0158] 12 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0159] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0160] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0161] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0162] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0163] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the imaging device 1 shown in FIG. 1 or the like can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, noise can be suppressed, thereby enabling safer vehicle driving.

[0164] The present technology may have the following configurations: (1) A solid-state imaging device comprising: a photoelectric conversion unit that converts light into electric charges; a storage unit that temporarily stores the electric charges; a transfer unit that transfers the electric charges to the storage unit; and a plurality of selection transistors connected between the storage unit and each of a plurality of vertical signal lines and that select whether to output a signal based on the electric charges stored in the storage unit. (2) The solid-state imaging device according to (1), in which the signal based on the electric charges stored in the storage unit is read out during a shutter period via a first vertical signal line corresponding to a first selection transistor. (3) The solid-state imaging device according to (2), in which the signal based on the electric charges stored in the storage unit is read out during a read period via a second vertical signal line different from the first vertical signal line that corresponds to a second selection transistor different from the first selection transistor. (4) The solid-state imaging device according to (3), in which the electric charges in the storage unit are not reset during a period from when they are read out via the first vertical signal line to when they are read out via the second vertical signal line. (5) The solid-state imaging device according to any one of (1) to (4), further comprising a signal processing unit that processes signals read out via the plurality of vertical signal lines. (6) The solid-state imaging device according to (5), wherein the signal processing unit performs AD (Analog to Digital) conversion on each of the signals read out via the plurality of vertical signal lines and stores the converted signals. (7) The solid-state imaging device according to (5) or (6), wherein the signal processing unit performs CDS (Correlated Double Sampling) based on the signals read out via the plurality of vertical signal lines. (8) The solid-state imaging device according to any one of (1) to (7), comprising: a plurality of the storage units; and a plurality of the transfer units, wherein at least one of the plurality of storage units is a capacitance element. (9) The solid-state imaging device according to (8), wherein the capacitance element is a MIM (Metal Insulator Metal) capacitance element.(10) The solid-state imaging device according to any one of (1) to (9), comprising: a plurality of the storage units; and a plurality of the transfer units, wherein the plurality of storage units are connected in series and store charges transferred from the photoelectric conversion units and charges overflowing from the photoelectric conversion units. (11) The solid-state imaging device according to any one of (1) to (10), comprising: three of the storage units; and a plurality of the transfer units, wherein charges are read out from the photoelectric conversion units at high conversion efficiency, medium conversion efficiency, and low conversion efficiency. (12) The solid-state imaging device according to any one of (1) to (11), comprising: a plurality of pixels, each of the pixels having: the photoelectric conversion unit; the storage unit; and two selection transistors respectively corresponding to two of the vertical signal lines provided for each pixel column. (13) The solid-state imaging device according to any one of (1) to (12), comprising a plurality of pixels, wherein the plurality of selection transistors of a first pixel correspond to a first signal line group including a plurality of the vertical signal lines, and the plurality of selection transistors of a second pixel in the same pixel column but a different pixel row relative to the first pixel correspond to a second signal line group including a plurality of the vertical signal lines different from the first signal line group, and signals from the first pixel and the second pixel are read out in parallel. (14) The solid-state imaging device according to any one of (1) to (13), further comprising an amplifier transistor that amplifies a signal based on charges accumulated in the storage section and outputs the signal to the plurality of selection transistors, wherein the amplifier transistor and the plurality of selection transistors are connected by an active region. (15) The solid-state imaging device according to any one of (1) to (13), further comprising an amplifier transistor that amplifies a signal based on charges accumulated in the storage section and outputs the signal to the plurality of selection transistors, wherein the amplifier transistor and the plurality of selection transistors are connected via wiring.

[0165] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0166] 1 Imaging device, 5 Column signal processing circuit, 9 Vertical signal line, 91 Vertical signal line, 92 Vertical signal line, 9G1 Signal line group, 9G2 Signal line group, 51 Photoelectric conversion unit, 52 Transfer transistor, 53 First FD unit, 54 Second transfer transistor, 55 Second FD unit, 56 Third transfer transistor, 57 Third FD unit, 58 MIM capacitance element, 60 Amplifying transistor, 61 Selection transistor, 611 Selection transistor, 612 Selection transistor

Claims

1. A solid-state imaging device comprising: a photoelectric conversion unit that converts light into electric charges; a storage unit that temporarily stores the electric charges; a transfer unit that transfers the electric charges to the storage unit; and a plurality of selection transistors connected between the storage unit and each of a plurality of vertical signal lines, each of which selects whether to output a signal based on the electric charges stored in the storage unit.

2. The solid-state imaging device according to claim 1, wherein a signal based on the charge stored in said storage section is read out during a shutter period via a first vertical signal line corresponding to a first selection transistor.

3. A solid-state imaging device as described in claim 2, wherein a signal based on the charge stored in the storage section is read out during a read period via a second vertical signal line different from the first vertical signal line, which corresponds to a second selection transistor different from the first selection transistor.

4. A solid-state imaging device according to claim 3, wherein the charge in the storage section is not reset during the period from when it is read out via the first vertical signal line until it is read out via the second vertical signal line.

5. The solid-state imaging device according to claim 1, further comprising a signal processing unit that processes signals read out via the plurality of vertical signal lines.

6. The solid-state imaging device according to claim 5, wherein the signal processing section performs AD (Analog to Digital) conversion on each of the signals read out via the plurality of vertical signal lines and stores the converted signals.

7. The solid-state imaging device according to claim 5, wherein the signal processing section performs CDS (Correlated Double Sampling) based on signals read out via the plurality of vertical signal lines.

8. A solid-state imaging device according to claim 1, comprising: a plurality of said storage sections; and a plurality of said transfer sections, wherein at least one of said plurality of storage sections is a capacitive element.

9. The solid-state imaging device according to claim 8, wherein the capacitance element is a MIM (Metal Insulator Metal) capacitance element.

10. A solid-state imaging device according to claim 1, comprising a plurality of said storage sections and a plurality of said transfer sections, said plurality of storage sections being connected in series and storing electric charges transferred from said photoelectric conversion section and electric charges overflowing from said photoelectric conversion section.

11. A solid-state imaging device according to claim 1, comprising three of the storage sections and a plurality of the transfer sections, wherein charges are read out from the photoelectric conversion sections at high conversion efficiency, medium conversion efficiency, and low conversion efficiency.

12. A solid-state imaging device according to claim 1, comprising a plurality of pixels, each of said pixels having: said photoelectric conversion section; said storage section; and two of said selection transistors respectively corresponding to two of said vertical signal lines provided for each pixel column.

13. The solid-state imaging device according to claim 1, comprising a plurality of pixels, wherein the plurality of selection transistors of a first pixel correspond to a first signal line group including a plurality of the vertical signal lines, and the plurality of selection transistors of a second pixel in the same pixel column but a different pixel row relative to the first pixel correspond to a second signal line group including a plurality of the vertical signal lines different from the first signal line group, and wherein signals of the first pixel and the second pixel are read out in parallel.

14. The solid-state imaging device according to claim 1, further comprising an amplifying transistor that amplifies a signal based on the charge stored in the storage section and outputs the signal to the plurality of selection transistors, wherein the amplifying transistor and the plurality of selection transistors are connected by an active region.

15. The solid-state imaging device according to claim 1, further comprising an amplifying transistor that amplifies a signal based on the charge stored in the storage section and outputs the signal to the plurality of selection transistors, the amplifying transistor and the plurality of selection transistors being connected via wiring.

Images