High-voltage electric power supply

Abstract

A resonance circuit 5 comprises: a resonance capacitor Cr that is connected in series to a primary winding N1; a resonance inductance Lr that is connected in series with the resonance capacitor Cr; a winding capacity Cp1; and a winding capacity Cp2. The resonance frequency of the resonance circuit 5 includes a first resonance frequency that is based on the resonance capacitor Cr and the resonance inductance Lr, and a second resonance frequency that is greater than the first resonance frequency on the basis of the resonance capacitor Cr, the resonance inductance Lr, and the winding capacities Cp1 and Cp2. An inverter control circuit 4 controls the inverter at a first driving frequency that follows the first resonance frequency in the case of a heavy load, and controls the inverter at a second driving frequency that is greater than the first driving frequency and is between the first resonance frequency and the second resonance frequency in the case of a light load.

Description

High Voltage Power Supply

[0001] This application claims priority to Japanese Patent Application No. 2024-104833, filed on June 28, 2024, and incorporates by reference the entire contents of said Japanese application.

[0002] High-voltage power supplies having an inverter and a resonant circuit are known (see, for example, Patent Document 1). In the high-voltage power supply described in Patent Document 1, the drive frequency of the inverter is switched depending on the magnitude of the output voltage. Specifically, the mode is switched between a fundamental resonant mode in which the inverter is controlled so that the frequency of a resonant current supplied from the inverter to the resonant circuit roughly matches the drive frequency of the inverter, and an N-fold resonant mode in which the inverter is controlled so that the frequency of the resonant current is N (a natural number plus 1) times the drive frequency of the inverter.

[0003] JP 2016-12397 A

[0004] In a high-voltage power supply, the resonant frequency of a resonant circuit can fluctuate as the load current supplied to the load increases. If the drive frequency of the inverter cannot keep up with the fluctuations in the resonant frequency of the resonant circuit, a surge can occur, for example, when the inverter's switching elements start up. The surge can cause damage to the switching elements and be a source of radiated electromagnetic field noise. Therefore, there is a need for a high-voltage power supply that can suppress the occurrence of surges and stably drive the inverter even when the resonant frequency fluctuates.

[0005] An object of the present disclosure is to provide a high-voltage power supply that can stably drive an inverter.

[0006] A high-voltage power supply according to one aspect of the present disclosure is [1] "comprising: a power supply circuit that generates a DC voltage; an inverter connected to the power supply circuit and that converts the DC voltage into an AC voltage; an inverter control circuit connected to the inverter and that controls the inverter; and a resonant circuit connected between the inverter and a load and that boosts the AC voltage to drive the load, wherein the resonant circuit comprises a transformer including a primary winding and a secondary winding insulated from the primary winding and connected to the load; a capacitor connected in series with the primary winding between the inverter and the primary winding; a resonant inductance connected in series with the capacitor; a first parasitic capacitance present in parallel with the primary winding of the transformer; and a second parasitic capacitance present in parallel with the secondary winding of the transformer. and a second parasitic capacitance present in parallel with the capacitor, wherein the resonant circuit has a first resonant frequency based on the capacitor and the resonant inductance, and a second resonant frequency higher than the first resonant frequency based on the capacitor, the resonant inductance, the first parasitic capacitance, and the second parasitic capacitance, wherein the inverter control circuit controls the inverter at a first drive frequency that follows the first resonant frequency when the load is heavy and an electrical parameter representing the magnitude of the load exceeds a threshold, and controls the inverter at a second drive frequency that is higher than the first drive frequency and between the first resonant frequency and the second resonant frequency when the load is light and the electrical parameter is equal to or less than the threshold.

[0007] In the high-voltage power supply described in [1] above, a capacitor is provided between the inverter and the primary winding, connected in series with the primary winding. This allows for the determination of a first resonant frequency based on the capacitor and a resonant inductance, such as a leakage inductance between the primary and secondary windings that is not involved in the transformer coupling, and a second resonant frequency higher than the first resonant frequency based on the capacitor, the resonant inductance, and the first and second parasitic capacitances of the transformer, and allows for the resonant frequency to be varied within a predicted range. Furthermore, in the case of a heavy load in which the electrical parameter exceeds a threshold, the inverter control circuit controls the inverter at a first drive frequency that tracks the first resonant frequency. Additionally, in the case of a light load in which the electrical parameter is equal to or less than the threshold, the inverter control circuit controls the inverter at a second drive frequency between the first and second resonant frequencies. This allows for the magnitude of the electrical parameter to be used as an index for determining the load magnitude, and for the inverter to be driven in response to fluctuations in the resonant frequency due to fluctuations in the load magnitude. Therefore, even when the resonant frequency fluctuates, surges are prevented and the inverter can be driven stably with low loss.

[0008] A high-voltage power supply according to one aspect of the present disclosure may be [2] "the high-voltage power supply according to [1], wherein, in the case of a heavy load in which the electrical parameter exceeds the threshold, the inverter control circuit synchronizes the phase of the signal controlling the inverter with the phase of the output current of the inverter and sets the first drive frequency so that the phase of the output current of the inverter lags the phase of the signal controlling the inverter." In this case, the deviation between the period of the signal controlling the inverter and the period of the inverter output current is suppressed, making it easier to reliably cause the first drive frequency to track the first resonant frequency. This makes it possible to suppress the occurrence of surges due to the deviation between the first drive frequency and the first resonant frequency. Furthermore, because the phase of the output current lags the phase of the signal controlling the inverter, the phase of the output current lags the phase of the inverter output voltage, and the current has negative polarity when the semiconductor switch is turned on (i.e., current flows through a diode inside the high-side semiconductor switch and does not flow inside the low-side semiconductor switch), thereby achieving soft switching.

[0009] A high-voltage power supply according to one aspect of the present disclosure may be [3] "the high-voltage power supply according to [1] or [2], wherein, under a light load condition in which the electrical parameter is equal to or less than the threshold value, the inverter control circuit sets the second drive frequency so that a half-cycle length of the second drive frequency is longer than a full cycle length of the inverter's output current and the phase of the inverter's output current lags behind the phase of a signal controlling the inverter." Under a light load condition, the waveform of the inverter's output current tends to be distorted due to the influence of parasitic capacitance. In this case, for example, if the second drive frequency is set so that the phase of the signal controlling the inverter is synchronized with the phase of the inverter's output current, the inverter will be driven in accordance with the distortion of the inverter's output current waveform, which may increase inverter loss or cause a through current. Therefore, in the high-voltage power supply, the second drive frequency is set so that a half-cycle length of the second drive frequency is longer than a full cycle length of the inverter's output current. This allows the inverter to be driven stably even under a light load condition. Furthermore, the phase of the output current lags behind the phase of the signal controlling the inverter, thereby achieving soft switching.

[0010] A high-voltage power supply according to one aspect of the present disclosure may be [4] "the high-voltage power supply according to any one of [1] to [3], wherein the inverter control circuit controls the inverter at the first drive frequency, regardless of the magnitude of the load, from immediately after the start of operation until the load voltage supplied to the load reaches a voltage threshold value." In this case, by controlling the inverter at the first drive frequency immediately after the high-voltage power supply is turned on, it is possible to make the load voltage reach the voltage threshold value in a shorter time.

[0011] A high-voltage power supply according to one aspect of the present disclosure may be [5] "the high-voltage power supply according to any one of [1] to [4], wherein the capacitance value of the capacitor is set so that the second resonant frequency is between two and three times the first resonant frequency." In this case, by setting the second resonant frequency to between two and three times the first resonant frequency, a seamless transition of the resonant frequency between the second resonant frequency and the first resonant frequency can be facilitated, and the occurrence of a surge due to a difference between the drive frequency and the resonant frequency can be further easily suppressed.

[0012] A high-voltage power supply according to one aspect of the present disclosure may be [6] "the high-voltage power supply according to any one of [1] to [5], wherein the electrical parameter is the magnitude of the load current supplied to the load." In this case, the magnitude of the load can be directly determined by using the magnitude of the load current as an index.

[0013] A high-voltage power supply according to one aspect of the present disclosure may be [7] "the high-voltage power supply according to any one of [1] to [6], wherein the electrical parameter is the length of a half cycle of the output current of the inverter." In this case, the load size can be determined by utilizing the fact that the frequency of the output current varies due to a change in resonant frequency that occurs with an increase in the load size.

[0014] A high-voltage power supply according to one aspect of the present disclosure may be [8] "the high-voltage power supply according to any one of [1] to [7], wherein, when the load is light and the electrical parameter is equal to or less than the threshold value, the inverter control circuit sets the second drive frequency to a frequency corresponding to a period that is an even multiple of a half-period of the length of the output current of the inverter." In this case, it becomes easier to suppress the influence of distortion of the waveform of the output current of the inverter when the load is light.

[0015] A high-voltage power supply according to one aspect of the present disclosure may be [9] "the high-voltage power supply according to any one of [1] to [8], wherein the inverter control circuit further includes a comparator for comparing the electrical parameter with the threshold value, the comparator having hysteresis." In this case, the comparator having hysteresis can reduce chattering of the output of the comparator.

[0016] According to the present disclosure, it is possible to provide a high-voltage power supply that can stably drive an inverter.

[0017] FIG. 1 is a block diagram showing a high-voltage power supply according to an embodiment of the present disclosure. FIG. 2 is a block diagram showing an inverter control circuit shown in FIG. 1. FIG. 3 is a diagram for explaining the behavior of the inverter output current under a heavy load. FIG. 4 is a diagram for explaining the behavior of the inverter output current under a light load. FIG. 5 is a diagram showing a control operation flow of the inverter control circuit shown in FIG. 1. FIG. 6 is a diagram for explaining a first drive signal generated under a heavy load. FIG. 7 is a diagram for explaining a second drive signal generated under a light load. FIG. 8 is a diagram showing an example of frequency-output gain characteristics in a resonant circuit. FIG. 9 is a diagram showing an example of frequency-output current phase characteristics in a resonant circuit. FIG. 10 is a diagram showing an example of load current-resonant circuit output gain characteristics in the present disclosure and a comparative example. FIG. 11 is a diagram showing an example of load current-drive frequency characteristics in the present disclosure and a comparative example. FIG. 12 is a diagram showing a control operation flow of a first modified inverter control circuit. FIG. 13 is a diagram for explaining the start-up mode and normal mode shown in FIG. 12. FIG. 14 is a block diagram showing an inverter control circuit according to a second modified example. FIG. 15 is a diagram showing a control operation flow of the inverter control circuit shown in FIG. 14. FIG. 16 is a block diagram showing an inverter control circuit according to a third modification. FIG. 17 is a graph showing measurement results of conversion efficiency. FIG. 18 is a circuit diagram showing a high-voltage power supply according to the second embodiment. FIG. 19 is a block diagram showing an outline of the overall configuration of a current detection circuit. FIG. 20 is a circuit diagram showing a specific example of the internal configuration of a current sensor circuit. FIG. 21 is a circuit diagram showing another specific example of the internal configuration of a current sensor circuit. FIG. 22 is a circuit diagram showing a specific example of the internal configuration of a detection output circuit. FIG. 23 is a circuit diagram showing a specific example of the internal configuration of an amplifier circuit and a maximum value detection circuit. FIG. 24 is a circuit diagram showing a specific example of the internal configuration of a first gain control circuit. FIG. 25 is a circuit diagram showing a specific example of the internal configuration of a second gain control circuit. FIG. 26 is a circuit diagram showing a specific example of the internal configuration of a state memory circuit. FIG. 27 is a circuit diagram showing a specific example of the internal configuration of a detection timing generation circuit. FIG. 28 is a graph showing example time waveforms of an output current, a control signal, and an inverter resonant current signal. FIG. 29 is a block diagram showing the overall configuration of a current detection circuit according to another example configuration.Fig. 30 is a circuit diagram showing specific examples of an adder circuit, an amplifier circuit, and a maximum value detection circuit. Fig. 31 is a block diagram showing a schematic configuration of an amplitude control circuit. Fig. 32 is a diagram showing conceptually the function of the amplitude control circuit. Fig. 33 is a circuit diagram showing a specific example of the internal configuration of an attenuation circuit. Fig. 34 is a circuit diagram showing a specific example of the internal configuration of an amplifier circuit.

[0018] Hereinafter, a preferred embodiment of a high-voltage power supply according to an embodiment of the present disclosure will be described in detail with reference to the drawings.

[0019] First Embodiment Fig. 1 is a block diagram showing a high-voltage power supply 1 according to an embodiment of the present disclosure. The high-voltage power supply 1 is a power supply circuit for supplying a high voltage to a load. In the following embodiments and modifications, an X-ray tube will be used as an example of the load of the high-voltage power supply 1. In addition to X-ray tubes, the high-voltage power supply 1 can also be applied to, for example, an electron beam irradiation device.

[0020] The high-voltage power supply 1 includes an AC / DC converter 2, an inverter 3, an inverter control circuit 4, a resonant circuit 5, and a rectifier circuit 6. An X-ray tube 7 is connected to the output side of the rectifier circuit 6.

[0021] The AC / DC conversion unit 2 is a functional unit that converts an AC voltage generated in the AC power supply AP into a DC voltage. In other words, the AC / DC conversion unit 2 is a power supply circuit that supplies a DC voltage to the inverter 3. The AC / DC conversion unit 2 is, for example, a switching-type AC / DC converter. In this case, the AC / DC conversion unit 2 may include a switching element (not shown) and a DC voltage control circuit 21 for controlling the magnitude of the DC voltage output from the AC / DC conversion unit 2. The DC voltage control circuit 21 may detect the magnitude of a load voltage supplied to the X-ray tube 7, which is a load. The DC voltage control circuit 21 may then control the phase angle of the switching element so that the magnitude of the load voltage approaches the set voltage Vset.

[0022] The inverter 3 is a functional unit that converts the DC voltage generated by the AC / DC conversion unit 2 into an AC voltage. The inverter 3 has a configuration in which two leg circuits 31 and 32 are connected in parallel. The leg circuit 31 is a circuit in which a semiconductor switch S1 and a semiconductor switch S2 are connected in series. The leg circuit 32 is a circuit in which a semiconductor switch S3 and a semiconductor switch S4 are connected in series. In the example of FIG. 1, the semiconductor switches S1 to S4 are configured by MOSFETs. The semiconductor switches S1 to S4 may also be configured by, for example, insulated gate bipolar transistors (IGBTs).

[0023] The output terminal 3a of the inverter 3 is disposed at the midpoint of the leg circuit 31 (a point between the semiconductor switches S1 and S2), and the output terminal 3b is disposed at the midpoint of the leg circuit 32 (a point between the semiconductor switches S3 and S4). A resonant circuit 5 is connected to the output terminals 3a and 3b.

[0024] The inverter control circuit 4 is a functional unit that generates a drive signal for controlling the inverter 3. The inverter control circuit 4 is connected to the inverter 3. Specifically, the inverter control circuit 4 is connected to each of the semiconductor switches S1 to S4. The inverter control circuit 4 receives an inverter resonant current signal Ic1, which indicates the magnitude of the output current Ia of the inverter 3 and is generated by a current detection element CT1. The magnitude of the inverter resonant current signal Ic1 corresponds to the magnitude of the output current Ia. The inverter control circuit 4 receives a load current signal Id, which indicates the magnitude of the load current Ib supplied to the X-ray tube 7 and is generated by a current detection element CT2. The magnitude of the load current signal Id corresponds to the magnitude of the load current Ib. The inverter control circuit 4 determines the magnitude of the load based on the load current signal Id. In this embodiment, the electrical parameter indicating the magnitude of the load is the magnitude of the load current signal Id. The inverter control circuit 4 generates a drive signal based on the inverter resonant current signal Ic1 of the inverter 3. The current detection elements CT1 and CT2 may be current transformers or power resistors.

[0025] The resonant circuit 5 is a functional unit that boosts the AC voltage output from the inverter 3 to generate a load voltage for driving the X-ray tube 7. The resonant circuit 5 is connected between the inverter 3 and the X-ray tube 7, which is a load. The resonant circuit 5 includes a transformer TR including a primary winding N1 and a secondary winding N2 insulated from the primary winding N1, and a resistor R1 and a resonant capacitor Cr connected between one end N1a of the primary winding N1 of the transformer TR and the output terminal 3a of the inverter 3. The resonant capacitor Cr is connected in series with the resistor R1. The resonant capacitor Cr is also connected in series with the primary winding N1. The secondary winding N2 of the transformer TR is connected to the X-ray tube 7, which is a load, via a rectifier circuit 6. The resistor R1 functions, for example, as a DC resistor on the primary winding N1 side of the resonant circuit 5.

[0026] The transformer TR includes multiple parasitic components. The transformer TR includes a resonant inductance Lr (parasitic inductance). The resonant inductance Lr is a leakage inductance of the transformer TR. The resonant inductance Lr exists in the primary winding N so as to be connected in series with the resonant capacitor Cr. The resonant inductance Lr may include an external inductor connected in series with the resonant capacitor Cr. The transformer TR includes an excitation inductance Lp and a winding capacitance Cp1 (first parasitic capacitance) that exist in parallel with the primary winding N1 between one end N1a and the other end N1b of the primary winding N1. The transformer TR includes a winding capacitance Cp2 (second parasitic capacitance) that exists in parallel with the secondary winding N2 between one end N2a and the other end N2b of the secondary winding N2.

[0027] The rectifier circuit 6 is a functional unit that converts the AC voltage boosted in the resonant circuit 5 into a DC voltage and supplies it to the X-ray tube 7. The rectifier circuit 6 is connected to the resonant circuit 5 via a resistor R2. The resistor R2 is connected between one end N2a of the secondary winding N2 and the rectifier circuit 6, and they are connected in series with each other. The rectifier circuit 6 includes a rectifier diode unit 61 and a smoothing capacitor 62. The rectifier diode unit 61 is composed of, for example, four bridge-connected diodes. The AC voltage boosted in the resonant circuit 5 is rectified by the rectifier diode unit 61 and smoothed by the smoothing capacitor 62, thereby being converted into a DC voltage. The resistor R2 functions, for example, as a DC resistor on the secondary winding N2 side of the resonant circuit 5. The rectifier diode unit 61 may be composed of, for example, a multi-stage series diode and capacitor group, as typified by a Cockcroft-Walton boost system. In this case, the smoothing capacitor 62 may be composed of a group of capacitors connected in series with each other.

[0028] Fig. 2 is a block diagram showing the inverter control circuit 4 shown in Fig. 1. The inverter control circuit 4 has a comparator 41, a load state determination unit 42, an output current detection circuit 43, a half-period measurement unit 44, a heavy load drive signal generation unit 45, and a light load drive signal generation unit 46.

[0029] The comparator 41 receives a load current signal Id. The comparator 41 compares the magnitude of the load current signal Id with a threshold Iref, thereby comparing the load current Ib with the threshold. If the magnitude of the load current signal Id is greater than the threshold Iref (if the load current Ib is greater than the threshold), the comparator 41 outputs a high-level signal to the load state determination unit 42. If the magnitude of the load current signal Id is smaller than the threshold Iref (if the load current Ib is smaller than the threshold), the comparator 41 outputs a low-level signal to the load state determination unit 42. The value of the high-level signal is, for example, the power supply voltage value of the comparator 41, and the value of the low-level signal is, for example, the reference potential GND. The comparator 41 may have hysteresis. In this case, the comparator 41 may, for example, use a value obtained by adding a predetermined value to the threshold value Iref as the threshold value for transitioning from a low level to a high level, and may use a value obtained by subtracting a predetermined value from the threshold value Iref as the threshold value for transitioning from a high level to a low level.

[0030] The inverter resonant current signal Ic1 is input to the output current detection circuit 43. The output current detection circuit 43 generates an offset threshold Vos proportional to the magnitude of the inverter resonant current signal Ic1, and generates a synchronization signal Sz1, which is a pulse wave synchronized with the inverter resonant current signal Ic1, based on the offset threshold Vos and the inverter resonant current signal Ic1. The output current detection circuit 43 outputs the generated synchronization signal Sz1 to the load state determination unit 42.

[0031] The output current detection circuit 43 includes a level shifter 431, a full-wave rectifier circuit 433, a comparator 432, and an offset threshold power supply 434. The inverter resonant current signal Ic1 is input to the level shifter 431. The level shifter 431 sets an offset threshold Vos proportional to the magnitude of the inverter resonant current signal Ic1. The offset threshold Vos is, for example, a positive DC voltage proportional to the magnitude of the inverter resonant current signal Ic1. The level shifter 431 instructs the offset threshold power supply 434 of the set offset threshold Vos. The offset threshold power supply 434 generates the offset threshold Vos based on the instruction and outputs it to the comparator 432.

[0032] The level shifter 431 outputs the inverter resonant current signal Ic1 as is to the full-wave rectifier circuit 433. The full-wave rectifier circuit 433 full-wave rectifies the inverter resonant current signal Ic1. Specifically, the full-wave rectifier circuit 433 rectifies the negative current component of the inverter resonant current signal Ic1 to convert it into a positive voltage. The full-wave rectifier circuit 433 outputs a full-wave rectified signal Ic2, which is obtained by full-wave rectifying the inverter resonant current signal Ic1, to the comparator 432.

[0033] The comparator 432 compares the offset threshold value Vos with the full-wave rectified signal Ic2 to detect the phase of the full-wave rectified signal Ic2 and generate the synchronization signal Sz1. For example, the comparator 432 generates a one-shot pulse at the point where the offset threshold value Vos intersects with the full-wave rectified signal Ic2, thereby generating the synchronization signal Sz1.

[0034] Here, an example of an amplifier within the level shifter 431 will be described. The peak value of the inverter resonant current signal Ic1 varies by approximately two orders of magnitude across the entire load range. The output range of the amplifier within the level shifter 431 is limited to the power supply range of the control system. Therefore, it may be difficult to achieve appropriate phase detection corresponding to the range of the output current Ia across the entire load range with a fixed gain amplifier within the level shifter 431. Therefore, the gain of the amplifier within the level shifter 431 may be adjusted using a variable gain circuit or the like that varies the gain according to the inverter resonant current signal Ic1. One example is a method in which the gain is varied continuously or stepwise in a feedforward manner according to the magnitude of the inverter resonant current signal Ic1. In this method, the amplifier within the level shifter 431 may switch its gain amplification factor according to the magnitude of the inverter resonant current signal Ic1. Another example is an AGC (Auto Gain Control) that keeps the maximum value of the inverter resonant current signal Ic1 output from the level shifter 431 constant. The AGC may, for example, clamp the maximum value of the inverter resonant current signal Ic1 and control it so that the maximum value is kept constant using an error amplifier. The gain may be varied by either analog or digital means. If the gain is varied by analog means, the feedback circuit constant that sets the amplifier gain inside the level shifter 431 may be configured using an element such as a Cds or a photocoupler. On the other hand, if the gain is varied by digital means, the gain may be adjusted by appropriate arithmetic processing after AD conversion, and then DA conversion may be performed again.

[0035] The output current detection circuit 43 outputs the synchronization signal Sz1 to the load state determination unit 42 and the half-period measurement unit 44 .

[0036] The half-period measuring unit 44 receives a synchronization signal Sz1 from the output current detection circuit 43. The half-period measuring unit 44 measures the length between pulses in the synchronization signal Sz1 as a half-period of the output current Ia. The half-period measuring unit 44 outputs a half-period signal Cy representing the length of the measured half-period of the output current Ia to the load state determining unit 42.

[0037] A signal indicating the magnitude of the load current Ib is input to the load state determination unit 42 from the comparator 41. When a high-level signal is input from the comparator 41, the load state determination unit 42 determines that the load current Ib is large and a heavy load exists. On the other hand, when a low-level signal is input from the comparator 41, the load state determination unit 42 determines that the load current Ib is small and a light load exists.

[0038] The load condition determination unit 42 receives a synchronization signal Sz1 from the output current detection circuit 43. The load condition determination unit 42 receives a half-period signal Cy from the half-period measurement unit 44. If the load condition determination unit 42 determines that the load is heavy, it outputs the synchronization signal Sz1 and the half-period signal Cy to the heavy load drive signal generation unit 45. If the load condition determination unit 42 determines that the load is light, it generates a synchronization signal Sz2 from the synchronization signal Sz1. The length of one period of the synchronization signal Sz2 is longer than the length of one period of the synchronization signal Sz1. Details will be described later. The load condition determination unit 42 outputs the synchronization signal Sz2 and the half-period signal Cy to the light load drive signal generation unit 46.

[0039] When the load condition determination unit 42 determines that the load is heavy, the heavy load drive signal generation unit 45 receives a synchronization signal Sz1 and a half-period signal Cy from the load condition determination unit 42. The heavy load drive signal generation unit 45 generates a first drive signal Sd1 based on the synchronization signal Sz1 and the half-period signal Cy. The heavy load drive signal generation unit 45 generates four first drive signals Sd1 to drive the semiconductor switches S1 to S4, respectively. The frequency of the first drive signal Sd1 is the first drive frequency. When the load condition determination unit 42 determines that the load is light, the light load drive signal generation unit 46 receives a synchronization signal Sz2 and a half-period signal Cy from the load condition determination unit 42. The light load drive signal generation unit 46 generates a second drive signal Sd2 based on the synchronization signal Sz2 and the half-period signal Cy. The light load drive signal generating unit 46 generates four second drive signals Sd2 to drive the semiconductor switches S1 to S4, respectively. The frequency of the second drive signals Sd2 is the second drive frequency.

[0040] In the example of FIG. 2 , a multiplexer 8 is provided between the inverter control circuit 4 and the inverter 3. The load condition determination unit 42 outputs, for example, a switching signal SC1 according to the load condition to the multiplexer 8. The multiplexer 8 may switch the drive signal to be output to the inverter 3 between a first drive signal Sd1 and a second drive signal Sd2 according to the switching signal SC1. When the load condition determination unit 42 determines that the load is heavy, the multiplexer 8 outputs the first drive signal Sd1 to the inverter 3. When the load condition determination unit 42 determines that the load is light, the multiplexer 8 outputs the second drive signal Sd2 to the inverter 3.

[0041] Here, the relationship between the load magnitude (heavy load or light load) and the resonant frequency of the resonant circuit 5 will be described. The resonant frequency of the resonant circuit 5 changes as the load magnitude changes. FIG. 3 illustrates an example of the output current when the load state determination unit 42 determines that the load is heavy. In the case of a heavy load, the waveform of the output current Ia is close to a sine wave. In the case of a heavy load, the resonant frequency becomes a first resonant frequency Fr1 calculated based on equation (1): Fr1=1 / (2×π×SQRT(Cr×Lr))...(1) In equation (1), SQRT represents the square root. As shown in equation (1), the first resonant frequency Fr1 is determined by the resonant capacitor Cr and the resonant inductance Lr. In the case of a heavy load, the values ​​of multiple parasitic components other than the resonant inductance Lr are clamped at both ends of the winding capacitance Cp1 by the output DC voltage, approaching a short circuit in terms of AC. As a result, the values ​​of the multiple parasitic components other than the resonant inductance Lr are relatively small compared to the values ​​of the resonant capacitor Cr and the resonant inductance Lr, so the influence of the multiple parasitic components other than the resonant inductance Lr on the first resonant frequency Fr1 can be ignored.

[0042] FIG. 4 is a diagram showing an example of a change in output current when the load state determination unit 42 determines that the load is light. FIG. 4 shows, as an example, how the output current Ia changes from Ia1 to Ia5 as the load increases. Under a light load, the waveform of the output current Ia exhibits a damped oscillation within a half inverter drive cycle, resulting in a distorted waveform due to a high resonant frequency caused by the influence of the winding capacitances Cp1 and Cp2. The distortion of the waveform of the output current Ia tends to improve as the resonant frequency gradually decreases with increasing load. Under a light load, the resonant frequency is the second resonant frequency Fr2 calculated based on equation (2): Fr2 = 1 / (2 × π × SQRT(Cz × Lr)) (2). In equation (2), SQRT denotes square root. In equation (2), Cz is the combined series capacitance of the resonant capacitor Cr and the winding capacitances Cp1 and Cp2, and is calculated as in equation (3): Cz = Cr × (Cp1 + Cp2) / (Cr + Cp1 + Cp2) (3) As shown in equations (2) and (3), the second resonant frequency Fr2 is determined by the resonant capacitor Cr, the resonant inductance Lr, and the winding capacitances Cp1 and Cp2. However, as the load increases, the influence of the winding capacitances Cp1 and Cp2 gradually decreases because both ends of the winding capacitance Cp1 are clamped by the output DC voltage. In the example of FIG. 4 , of the output currents Ia1 to Ia5, the output current Ia1 is most influenced by the winding capacitances Cp1 and Cp2, and the output current Ia5 is least influenced by the winding capacitances Cp1 and Cp2. The value of the magnetizing inductance Lp is relatively large compared to the values ​​of the resonant capacitor Cr, the resonant inductance Lr, and the winding capacitances Cp1 and Cp2, so the effect of the magnetizing inductance Lp on the second resonant frequency Fr2 is negligible.

[0043] The second resonant frequency Fr2 changes as the output current Ia changes from the output current Ia1 to the output current Ia5. The second resonant frequency Fr2 is greater than the first resonant frequency Fr1. The second resonant frequency Fr2 is, for example, two to three times the first resonant frequency Fr1. Specifically, the capacitance value of the resonant capacitor Cr is set so that the second resonant frequency Fr2 is two to three times the first resonant frequency Fr1. When adjusting the first resonant frequency Fr1 and the second resonant frequency Fr2, it is difficult to adjust the value of the parasitic component of the transformer TR. Therefore, the value of the parasitic component of the transformer TR is determined in advance, and the capacitance value of the resonant capacitor Cr is set so that the first resonant frequency Fr1 and the second resonant frequency Fr2 become desired values.

[0044] Next, the control operation of the inverter control circuit 4 will be described. FIG. 5 is a diagram showing a control operation flow MT1 of the inverter control circuit 4. The control operation flow MT1 is started, for example, when a user starts operation of the high-voltage power supply 1 (e.g., when the power is turned on). In the following description, FIGS. 6 and 7 will be referred to as appropriate. FIG. 6 is a diagram for explaining the first drive signal Sd1 generated under heavy load conditions. Parts (a) to (e) of FIG. 6 are diagrams showing the signal waveforms of the inverter resonant current signal Ic1, full-wave rectified signal Ic2, synchronization signal Sz1, half-cycle signal Cy, and first drive signal Sd1 corresponding to the output current Ia, respectively.

[0045] First, the output current detection circuit 43 generates an offset threshold Vos (step ST1). In step ST1, the level shifter 431 sets an offset threshold Vos proportional to the magnitude of the inverter resonant current signal Ic, and the offset threshold power supply 434 generates the offset threshold Vos. Next, the full-wave rectifier circuit 433 full-wave rectifies the inverter resonant current signal Ic1 (step ST2). The output current Ia shown in part (a) of FIG. 6 has a waveform close to a sine wave. As shown in part (b) of FIG. 6, the level shifter 431 sets the offset threshold Vos, which is a positive DC voltage. Meanwhile, the full-wave rectifier circuit 433 rectifies the negative current component of the inverter resonant current signal Ic1 to a positive voltage, generating a full-wave rectified signal Ic2. Steps ST1 and ST2 may be performed first, or simultaneously.

[0046] Next, the comparator 432 compares the offset threshold Vos with the full-wave rectified signal Ic2 to generate a synchronization signal Sz1 (step ST3). As shown in part (c) of FIG. 6, the comparator 432 generates a one-shot pulse at the point where the offset threshold Vos intersects with the full-wave rectified signal Ic2, thereby generating the synchronization signal Sz1. Because the offset threshold Vos is offset toward the positive voltage side relative to the zero-crossing point of the output current Ia, the phase of the synchronization signal Sz1 is shifted from the phase of the output current Ia. As shown in parts (b) and (c) of FIG. 6, the phase of the output current Ia lags behind the phase of the synchronization signal Sz1 by a delay phase Δφ.

[0047] Next, as shown in part (d) of FIG. 6 , the half-period measurement unit 44 measures the length between pulses in the synchronization signal Sz1 to generate a half-period signal Cy (step ST4). The length of the half-period signal Cy corresponds to the length of a half-period of the output current Ia. A counter, for example, is used to measure the half-period. The counter may be a direct counter or a reciprocal counter. In this embodiment, the half-period signal Cy is an analog signal. In the example of FIG. 6 , the magnitude of the half-period signal Cy gradually increases as the counter value increases. The half-period signal Cy is reset for each pulse of the synchronization signal Sz1. The half-period signal Cy may be, for example, a digital signal expressed in decimal notation, or a signal converted to a voltage value by DA conversion and then threshold-processed by a comparator. Steps ST1 to ST4 described above are performed as common processing steps under both heavy and light loads.

[0048] Next, the load state determination unit 42 determines whether the magnitude of the load current signal Id is equal to or less than the threshold value Iref (i.e., whether the magnitude of the load current Ib is equal to or less than the threshold value) (step ST5). First, a heavy load will be described, in which the magnitude of the load current signal Id exceeds the threshold value Iref (if the magnitude of the load current Ib exceeds the threshold value, step ST5: NO). The heavy load drive signal generation unit 45 sets the first drive frequency Fd1 of the first drive signal Sd1 to synchronize with the synchronization signal Sz1 (step ST6). As shown in part (e) of FIG. 6, the phase of the first drive signal Sd1 matches the phase of the synchronization signal Sz1. This sets the phase of the output current Ia to lag behind the phase of the first drive signal Sd1. The heavy load drive signal generation unit 45 generates the first drive signal Sd1 so that the first drive signal Sd1 rises from low to high in synchronization with the pulse of the synchronization signal Sz1 rising from low to high. The heavy load drive signal generator 45 generates the first drive signal Sd1 so that the first drive signal Sd1 falls from high to low in synchronization with the next pulse in the synchronization signal Sz1 rising from low to high, causing the first drive frequency Fd1 to follow the first resonant frequency Fr1 with the phase of the inverter output current Ia lagging behind the phase of the first drive signal Sd1 by the delay phase Δφ.

[0049] Under a heavy load, the pulse period of the synchronization signal Sz1 may be approximately constant. Therefore, fluctuations in the length of the half-cycle may be smaller than under a light load, and fluctuations in the magnitude of the half-cycle signal Cy may also tend to be smaller. However, even under a heavy load, the first resonant frequency Fr1 varies depending on the magnitude of the load, and the length of the half-cycle may also increase in accordance with the fluctuations in the first resonant frequency Fr1. However, in the inverter control circuit 4 of the present disclosure, the phase of the output current Ia is set to lag the phase of the first drive signal Sd1, and the first drive frequency Fd1 is made to follow the first resonant frequency Fr1, thereby suppressing a sudden increase in gain in the resonant circuit 5. This allows the inverter 3 to be driven stably, which, for example, leads to suppression of hunting when the magnitude of the DC voltage input to the inverter 3 from the AC / DC conversion unit 2 is changed.

[0050] Next, the heavy load drive signal generator 45 sets a dead time based on the half-period signal Cy and the input voltage to the inverter 3 (the voltage input from the AC / DC converter 2) (step ST7). Here, the dead time is the time from when the semiconductor switch S1 in the leg circuit 31 stops until when the semiconductor switch S2 starts, or the time from when the semiconductor switch S2 stops until when the semiconductor switch S1 starts. Dead times are similarly set for the semiconductor switches S3 and S4 in the leg circuit 32.

[0051] The ideal dead time is set to a length that achieves soft switching. In the inverter 3, after the semiconductor switch S1 stops, the excitation current of the transformer TR charges the output capacitance of the semiconductor switch S1 and discharges the output capacitance of the semiconductor switch S2. Then, when the excitation current of the transformer TR conducts the diode inside the semiconductor switch S2, the semiconductor switch S2 is driven to the ON state. In this way, soft switching is achieved. The ideal dead time is set, for example, to the time from when the semiconductor switch S1 stops until the output capacitance of the semiconductor switch S2 is completely discharged. However, the magnitude of the excitation current of the transformer TR may vary depending on the magnitude of the load. Therefore, the optimal dead time may vary depending on the magnitude of the load. Therefore, the heavy load drive signal generator 45 sets the dead time according to the length of the half cycle of the output current Ia based on the half-cycle signal Cy and the magnitude of the input voltage to the inverter 3. The heavy load drive signal generator 45 may store a lookup table that associates the length of the half cycle of the output current Ia with the dead time. Alternatively, the heavy load drive signal generating unit 45 may calculate the dead time using a function with the length of the half cycle of the output current Ia as a variable and the dead time as a target value.

[0052] After setting the first drive frequency Fd1 and the dead time, the heavy load drive signal generating unit 45 controls the inverter 3 at the first drive frequency Fd1 (step ST8).

[0053] Next, we will explain the light load situation, where the magnitude of the load current signal Id is equal to or less than the threshold value Iref (step ST5: YES if the magnitude of the load current Ib is equal to or less than the threshold value). FIG. 7 is a diagram for explaining the second drive signal Sd2 generated under a light load situation. Parts (a) to (f) of FIG. 7 are diagrams respectively showing the signal waveforms of the inverter resonant current signal Ic1, full-wave rectified signal Ic2, synchronization signal Sz1, synchronization signal Sz2, half-period signal Cy, and second drive signal Sd2 corresponding to the output current Ia. As shown in part (a) of FIG. 7, the waveform of the output current Ia is distorted. The waveform of the output current Ia is similar to the waveform of the output current Ia1 in FIG. 4. In the light load situation, as shown in parts (b) and (c) of FIG. 7, the full-wave rectified signal Ic2 is distorted, and the pulse period of the synchronization signal Sz1 may become irregular. Therefore, the fluctuation in the length of the half cycle is larger than that under a heavy load, and the fluctuation in the magnitude of the half cycle signal Cy shown in part (e) of Fig. 7 also tends to be larger. As with under a heavy load, the phase of the output current Ia lags behind the phase of the synchronization signal Sz1 by a delay phase Δφ.

[0054] The light-load drive signal generator 46 sets the second drive frequency Fd2 so that the length of half a cycle of the second drive frequency Fd2 is longer than the length of one cycle of the output current Ia (step ST9). The light-load drive signal generator 46 sets the second drive frequency Fd2 of the second drive signal Sd2, as shown in part (f) of FIG. 7 , for example, using the following procedure. The light-load drive signal generator 46 generates a synchronization signal Sz2 from the synchronization signal Sz1, as shown in part (d) of FIG. 7 . The light-load drive signal generator 46 sets the synchronization signal Sz2 so that the cycle length of the synchronization signal Sz2 is an integer multiple or greater than the cycle length of the synchronization signal Sz1. Here, the integer may be an even number greater than or equal to 2, or an odd number greater than or equal to 3. In the example of FIG. 7 , the synchronization signal Sz2 is set so that the cycle length of the synchronization signal Sz2 is three times the cycle length of the synchronization signal Sz1 (the length of three pulse cycles of the synchronization signal Sz1). However, the phase of the synchronization signal Sz2 coincides with the phase of the synchronization signal Sz1.

[0055] The light-load drive signal generator 46 then sets the second drive frequency Fd2 of the second drive signal Sd2 to synchronize with the synchronization signal Sz2. This sets the second drive frequency Fd2 to a frequency corresponding to a period that is at least an integer multiple of the length of a half period of the output current Ia. In the example of FIG. 7 , the light-load drive signal generator 46 sets the length of a half period of the second drive frequency Fd2 to three times the length of the half period of the output current Ia (the length of three pulse periods of the synchronization signal Sz1). As shown in part (f) of FIG. 7 , the phase of the second drive signal Sd2 matches the phase of the second synchronization signal Sz2. This sets the second drive frequency Fd2 so that the phase of the output current Ia lags behind the phase of the second drive signal Sd2.

[0056] As shown in Fig. 4, when the load is light, the length of the half cycle of the output current Ia varies depending on the magnitude of the load. Therefore, the second drive frequency Fd2 varies depending on the magnitude of the load. The variation range is between 10% and 20%.

[0057] The light-load drive signal generator 46 may store a lookup table that associates the length of a half cycle of the output current Ia with the second drive frequency Fd2. Alternatively, the light-load drive signal generator 46 may use a function in which the length of a half cycle of the output current Ia is a variable and the second drive frequency Fd2 is a target value. The second drive frequency Fd2 is set to a frequency that is greater than the first resonant frequency Fr1 and less than the second resonant frequency Fr2 (a frequency between the first resonant frequency Fr1 and the second resonant frequency Fr2). The second drive frequency Fd2 may be greater than or the same as the first drive frequency Fd1.

[0058] Next, the light-load drive signal generator 46 sets a dead time for the second drive signal Sd2 based on the half-cycle signal Cy (step ST10). The method for setting the dead time is the same as in step ST7. However, because the length of the half cycle of the output current Ia fluctuates significantly under light load conditions, the light-load drive signal generator 46 may set the dead time by, for example, multiplying a function with the length of the half cycle of the output current Ia as a variable and the dead time as a target value by a coefficient for correcting for fluctuations in the length of the half cycle of the output current Ia.

[0059] After setting the second drive frequency Fd2 and the dead time, the light load drive signal generating unit 46 controls the inverter 3 at the second drive frequency Fd2 (step ST11).

[0060] Finally, the inverter control circuit 4 determines whether a predetermined condition is satisfied (step ST12). The predetermined condition may be, for example, whether a predetermined time has elapsed since the high-voltage power supply 1 started operating, or whether the user has stopped the high-voltage power supply 1. If it is determined that the predetermined condition is satisfied (step ST12: YES), the series of control operation flows ends. On the other hand, if it is determined that the predetermined condition is not satisfied (step ST12: NO), the control operation flow MT1 returns to step ST1.

[0061] [Operation and Effect] The high-voltage power supply 1 is provided with a resonant capacitor Cr connected in series to the primary winding N1 between the inverter 3 and the primary winding N1. This makes it possible to previously determine a first resonant frequency Fr1 based on the resonant inductance Lr and the capacitor, such as the leakage inductance between the primary and secondary windings that is not involved in the coupling of the resonant capacitor Cr and the transformer TR, and a second resonant frequency Fr2 that is higher than the first resonant frequency Fr1 based on the resonant capacitor Cr, the resonant inductance Lr of the transformer TR, and the first parasitic capacitance (winding capacitance Cp1) and second parasitic capacitance (winding capacitance Cp2) of the transformer TR (if the rectifier diode section 61 is a Cockcroft-Walton boost system, this is the total capacitance including the parasitic capacitances present inside the Cockcroft-Walton circuit), and to vary the resonant frequency within an expected range. Furthermore, in the case of a heavy load in which the load current Ib exceeds the threshold value (i.e., in the case of a heavy load in which the load current signal Id exceeds the threshold value Iref), the inverter control circuit 4 controls the inverter 3 at a first drive frequency Fd1 that follows the first resonant frequency Fr1. In the case of a light load in which the load current Ib is equal to or less than the threshold value (i.e., in the case of a light load in which the load current signal Id is equal to or less than the threshold value Iref), the inverter control circuit 4 controls the inverter 3 at a second drive frequency Fd2 that is between the first resonant frequency Fr1 and the second resonant frequency Fr2. This allows the magnitude of the load current Ib to be used as an index for determining the magnitude of the load, and even if the resonant frequency fluctuates due to fluctuations in the magnitude of the load, the inverter 3 can be driven in response to the fluctuation. Therefore, even if the resonant frequency fluctuates, surges can be prevented and the inverter 3 can be driven stably with low loss.

[0062] When the load current Ib exceeds the threshold value (when the load current signal Id exceeds the threshold value Iref), the inverter control circuit 4 synchronizes the phase of the first drive signal Sd1 controlling the inverter 3 with the phase of the output current Ia of the inverter 3 (in other words, the phase of the inverter resonant current signal Ic1) and sets the first drive frequency Fd1 so that the phase of the output current Ia lags the phase of the first drive signal Sd1. In this case, the deviation between the period of the first drive signal Sd1 controlling the inverter 3 and the period of the output current Ia (inverter resonant current signal Ic1) of the inverter 3 is suppressed, making it easier to reliably cause the first drive frequency Fd1 to track the first resonant frequency Fr1. This makes it possible to suppress surges caused by the deviation between the first drive frequency Fd1 and the first resonant frequency Fr1. Furthermore, since the phase of the output current Ia lags behind the phase of the first drive signal Sd1, the phase of the output current Ia lags behind the phase of the output voltage of the inverter 3, and the current has negative polarity when the semiconductor switch is turned on (i.e., current flows through the diode of the low-side semiconductor switch S2, but does not flow through the diode of the high-side semiconductor switch S1), soft switching can be achieved.

[0063] In the case of a light load where the load current Ib is equal to or less than a threshold value (a light load where the load current signal Id is equal to or less than a threshold value Iref), the inverter control circuit 4 sets the second drive frequency Fd2 so that the length of half a cycle of the second drive frequency Fd2 is longer than the length of one cycle of the output current Ia of the inverter 3 (in other words, the length of one cycle of the inverter resonant current signal Ic1) and the phase of the output current Ia of the inverter 3 lags the phase of the second drive signal Sd2. In the case of a light load, the waveform of the output current Ia of the inverter 3 tends to be distorted due to the influence of the winding capacitances Cp1 and Cp2 (if the rectifier diode unit 61 is of a Cockcroft-Walton boost type, this is the total capacitance including the parasitic capacitance present in the Cockcroft-Walton circuit). In this case, for example, if the second drive frequency Fd2 is set so that the phase of the second drive signal Sd2 controlling the inverter 3 is synchronized with the phase of the output current Ia of the inverter 3, the inverter 3 will be driven in accordance with the distortion of the waveform of the output current Ia of the inverter 3, which may increase loss in the inverter 3 or cause a through current. Therefore, in the high-voltage power supply 1, the second drive frequency Fd2 is set so that the length of a half cycle of the second drive frequency Fd2 is longer than the length of one cycle of the output current Ia (inverter resonant current signal Ic1) of the inverter 3. This allows the inverter 3 to be driven stably even under light loads. Furthermore, since the phase of the output current Ia lags the phase of the second drive signal Sd2, soft switching can be achieved, similar to under heavy loads.

[0064] The capacitance value of the resonant capacitor Cr is set so that the second resonant frequency Fr2 is between two and three times the first resonant frequency Fr1. In this case, by setting the second resonant frequency Fr2 to be between two and three times the first resonant frequency Fr1, a seamless transition of the resonant frequency between the second resonant frequency Fr2 and the first resonant frequency Fr1 can be facilitated, and the occurrence of surges due to a mismatch between the drive frequency and the resonant frequency can be further easily suppressed.

[0065] The electrical parameter is the magnitude of the load current Ib supplied to the load (in other words, the magnitude of the load current signal Id). In this case, the magnitude of the load can be directly determined by using the magnitude of the load current Ib (load current signal Id) as an index.

[0066] When the load current Ib is a light load equal to or less than the threshold value (when the load current signal Id is a light load equal to or less than the threshold value Iref), the inverter control circuit 4 sets the second drive frequency Fd2 so that the second drive frequency Fd2 corresponds to a period that is an even multiple or greater than the length of a half period of the output current Ia of the inverter 3 (in other words, the length of a half period of the inverter resonant current signal Ic1). In this case, it becomes easier to suppress the effects of distortion in the waveform of the output current Ia of the inverter 3 under light load conditions.

[0067] The inverter control circuit 4 further includes a comparator 41 for comparing the load current Ib with a threshold value (comparing the load current signal Id with the threshold value Iref), and the comparator 41 has hysteresis. In this case, the hysteresis of the comparator 41 can reduce chattering of the output of the comparator 41.

[0068] The effect of the inverter control circuit 4 switching the control method of the inverter 3 depending on the load will be described in more detail. FIG. 8 is a diagram showing an example of the frequency-output gain characteristics of the resonant circuit 5. FIG. 9 is a diagram showing an example of the phase characteristics of the frequency-output current Ia of the resonant circuit 5. The examples of FIGS. 8 and 9 show the characteristics obtained when the magnitude of the load current signal Id is expressed as a relative value to the maximum load current and the magnitude of the load current is gradually reduced from 1. The heavy load region HR is the region where the relative value of the load current signal Id is between 1 and 0.1, and the light load region LR is the region where the relative value of the load current signal Id is between 0.0625 and 0.00049. The first resonant frequency Fr1 is set to 28.4 kHz, and the second resonant frequency Fr2 is set to 74 kHz. As shown in FIG. 8, in the light load region LR, the output gain at the second resonant frequency Fr2 increases sharply. The output gain at the second resonant frequency Fr2 differs by 40 dB (100 times) from the output gain at the first resonant frequency Fr1. As shown in FIG. 9 , the phase fluctuation increases as the load current decreases. Due to the characteristics of the resonant circuit 5, it is difficult to achieve stable control, for example, when a method is adopted in which the drive frequency is set so that the phase of the drive signal controlling the inverter 3 is synchronized with the phase of the output current Ia of the inverter 3 over the entire load range. In contrast, the inverter control circuit 4 of the present disclosure controls the inverter 3 at a first drive frequency Fd1 that follows the first resonant frequency Fr1 when the load current signal Id is heavy and exceeds the threshold value Iref. When the load current signal Id is light and not exceeding the threshold value Iref, the inverter 3 is controlled at a second drive frequency Fd2 between the first resonant frequency Fr1 and the second resonant frequency Fr2. Furthermore, since the phase of the output current Ia lags behind the phase of the first drive signal Sd1 by a delay phase Δφ, stable soft switching can be achieved between the first resonant frequency Fr1 and the second resonant frequency Fr2.

[0069] FIG. 10 shows an example of the load current Ib vs. output gain characteristics of the resonant circuit 5 for a method of switching the control mode of the inverter 3 according to the load using the inverter control circuit 4 of the present disclosure, and a comparative example of a method of setting the drive frequency so that the phase of the drive signal controlling the inverter 3 is synchronized with the phase of the inverter 3's output current Ia across the entire load range. FIG. 11 shows an example of the load current Ib vs. drive frequency characteristics for each of the above methods. As shown in FIG. 10 , the inverter control circuit 4 of the present disclosure limits gain fluctuations to approximately 4 dB across the entire load range, while the comparative example shows a difference of up to approximately 40 dB between the light load region LR and the heavy load region HR. As shown in FIG. 11 , the inverter control circuit 4 of the present disclosure drives the inverter 3 at a drive frequency near the first resonant frequency Fr1, which is the series resonance point, at the maximum load current, and also drives the inverter 3 at a drive frequency near the first resonant frequency Fr1 in the light load region LR. In contrast, the comparative example shows a large difference between the drive frequency in the light load region LR and the drive frequency in the heavy load region HR. From the above, it can be said that the inverter control circuit 4 is capable of much more efficient and stable control since both the gain and the drive frequency are stable over the entire load range compared to the comparative example.

[0070] [First Modification] Although the embodiments of the present disclosure have been described above, the present disclosure is not necessarily limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present disclosure.

[0071] 12 is a diagram showing a control operation flow MT2 according to a first modified example of the inverter control circuit 4. The control operation flow MT2 is started, for example, when the user starts the operation of the high-voltage power supply 1 (for example, when the power is turned on).

[0072] The inverter control circuit 4 measures the magnitude of the load voltage supplied to the X-ray tube 7, which is the load, immediately after the high-voltage power supply 1 starts operating (step ST21). The magnitude of the load voltage may be measured after reducing the load voltage using, for example, a transformer or a voltage-dividing resistor. The inverter control circuit 4 then determines whether the load voltage has reached a voltage threshold (step ST22). If the load voltage has reached the voltage threshold (step ST22: YES), the inverter control circuit 4 controls the inverter 3 in normal mode (step ST23). Here, normal mode refers to control according to the control operation flow MT1.

[0073] On the other hand, if the load voltage has not reached the voltage threshold (step ST22: NO), the inverter control circuit 4 controls the inverter 3 in the start-up mode (step ST24). FIG. 13 is a diagram illustrating the start-up mode and the normal mode. Parts (a) to (d) of FIG. 13 respectively show the signal waveforms of the load voltage Vb, the load current Ib, the first drive signal Sd1, and the second drive signal Sd2. From immediately after the start of operation until the load voltage Vb shown in part (a) of FIG. 13 reaches the voltage threshold Vth, the inverter control circuit 4 drives the inverter 3 with the first drive signal Sd1 shown in part (c) of FIG. 13 and controls the inverter 3 at the first drive frequency Fd1, regardless of the load magnitude (start-up mode). In the example of FIG. 13 , from immediately after the start of operation until the load voltage Vb reaches the voltage threshold Vth, the inverter control circuit 4 controls the inverter 3 with the first drive signal Sd1, even though the load current Ib shown in part (b) of FIG. 13 is equal to or less than the current threshold Ith. The magnitude of the load current Ib being equal to or less than the current threshold Ith corresponds to the magnitude of the load current signal Id being equal to or less than the threshold Iref. Similarly, the magnitude of the load current Ib exceeding the current threshold Ith corresponds to the magnitude of the load current signal Id exceeding the threshold Iref. After the load voltage Vb reaches the voltage threshold Vth, the inverter control circuit 4 switches the drive signal according to the magnitude of the load (normal mode). In the example of FIG. 13 , when the magnitude of the load current Ib is equal to or less than the current threshold Ith, the inverter control circuit 4 controls the inverter 3 with the second drive signal Sd2 shown in part (d) of FIG. 13 . When the magnitude of the load current Ib exceeds the current threshold Ith, the inverter control circuit 4 controls the inverter 3 with the first drive signal Sd1.

[0074] In control operation flow MT2, the inverter control circuit 4 controls the inverter 3 at the first drive frequency Fd1 from immediately after starting operation until the load voltage Vb supplied to the load reaches the voltage threshold Vth, regardless of the magnitude of the load. In this case, by controlling the inverter 3 at the first drive frequency Fd1 immediately after turning on the high-voltage power supply 1, it is possible to make the load voltage Vb reach the voltage threshold Vth in a shorter time.

[0075] [Second Modification] FIG. 14 is a block diagram showing an inverter control circuit 4A according to a second modification. Only the differences from the inverter control circuit 4 will be described. In the second modification, the electrical parameter representing the magnitude of the load is the length of a half cycle of the output current Ia. In the inverter control circuit 4A, a half-cycle signal Cy representing the length of a half cycle of the output current Ia is input to a comparator 41 from a half-cycle measurement unit 44. The comparator 41 compares the magnitude of the half-cycle signal Cy with a threshold IrefA. If the magnitude of the half-cycle signal Cy is greater than the threshold IrefA, the comparator 41 outputs a high-level signal to the load condition determination unit 42. If the magnitude of the half-cycle signal Cy is less than the threshold IrefA, the comparator 41 outputs a low-level signal to the load condition determination unit 42.

[0076] FIG. 15 shows a control operation flow MT3 of the inverter control circuit 4A. Instead of step ST5 in the control operation flow MT1, the control operation flow MT3 determines the load size in step ST13. If the length of the half cycle of the output current Ia exceeds the threshold (step ST13: NO), the heavy-load drive signal generator 45 generates a synchronization signal Sz1 so that the output current Ia is in a lagging phase and sets the first drive frequency Fd1 to synchronize with the synchronization signal Sz1 (step ST6). On the other hand, if the length of the half cycle of the output current Ia is equal to or less than the threshold (step ST13: YES), the light-load drive signal generator 46 sets the second drive frequency Fd2 so that the length of the half cycle of the second drive frequency Fd2 is longer than the length of one cycle of the output current Ia (step ST9).

[0077] 3 and 4, the length of the half cycle of the output current Ia is different in the case of a light load and in the case of a heavy load. When the electrical parameter is the length of the half cycle of the output current Ia, the load size can be determined by utilizing the fact that the frequency of the output current Ia varies due to the change in the resonant frequency that occurs with an increase in the load size.

[0078] [Third Modification] Instead of setting the first drive frequency Fd1 so as to synchronize with the synchronization signal Sz1, the heavy load drive signal generation unit 45 may generate the first drive signal Sd1 using PLL (Phased Locked Loop) control. FIG. 16 is a block diagram showing a heavy load drive signal generation unit 45B according to the third modification. The heavy load drive signal generation unit 45B includes a phase difference detection unit 451, a differentiator 452, a delay reference value output unit 453, a PI compensator 454, and a VCO circuit 455. The phase difference detection unit 451 receives the synchronization signal Sz1 from the output current detection circuit 43. The phase difference detection unit 451 regards the pulse interval in the synchronization signal Sz1 as the phase of the output current Ia and calculates the phase difference Pd between the phase of the output current Ia and the phase of the first drive signal Sd1 output from the VCO circuit 455. The differentiator 452 outputs the difference between the phase difference Pd and the delay reference value Pref output from the delay reference value output unit 453 to the PI compensator 454. The magnitude of the voltage output by the PI compensator 454 decreases when the phase difference Pd is smaller than the delay reference value Pref and increases when the phase difference Pd is larger than the delay reference value Pref. The output of the PI compensator 454 is input to the VCO circuit 455. The VCO circuit 455 changes the frequency it outputs depending on the magnitude of the voltage input from the PI compensator 454 to generate a first drive signal Sd1. The VCO circuit 455 lowers the frequency (first drive frequency Fd1) when the phase difference Pd is smaller than the delay reference value Pref and raises the frequency (first drive frequency Fd1) when the phase difference Pd is larger than the delay reference value Pref. In this way, the heavy load drive signal generating section 45B generates the first drive signal Sd1 in a state where a delay reference value is set between the phase of the output current Ia and the phase of the first drive signal Sd1.

[0079] In step ST9, the light-load drive signal generator 46 may fix the second drive frequency Fd2 even when the length of the half cycle of the output current Ia changes depending on the magnitude of the load. For example, if the amount of change in the length of the half cycle of the output current Ia is small compared to the amount of change in the magnitude of the load, the light-load drive signal generator 46 may fix the second drive frequency Fd2.

[0080] In the control operation flows MT1, MT2, and MT3 described above, when comparing the magnitude relationship of two numerical values, either of the two criteria of "greater than or equal to" and "greater than" can be used, or either of the two criteria of "less than or equal to" and "less than" can be used.

[0081] [Experimental Example] The load power conversion efficiency was measured when the control operation flow MT1 shown in FIG. 5 was applied to the high-voltage power supply 1 shown in FIG. 1 (hereinafter referred to as the embodiment method). FIG. 17 is a graph showing the measurement results of the conversion efficiency. In the graph of FIG. 17, the horizontal axis represents the magnitude of the load current Ib, and the vertical axis represents the conversion efficiency. Here, the conversion efficiency is a percentage value obtained by dividing the input power generated in the AC / DC converter 2 by the load power supplied to the load (the product of the load voltage and the load current). FIG. 17 also shows a graph using a comparative example of a high-voltage power supply 1 shown in FIG. 1 without the resonant capacitor Cr. For the high-voltage power supply of the comparative example, the first drive frequency Fd1 and the second drive frequency Fd2 were not switched depending on the magnitude of the load current Ib, but a fixed drive frequency was used. As shown in FIG. 17, in the embodiment method, the conversion efficiency is unlikely to decrease even when the magnitude of the load current Ib increases. In the embodiment method, when the magnitude of the load current Ib is 0.225 A, the conversion efficiency is 80% or more. In contrast, in the comparative example, the conversion efficiency tends to decrease as the magnitude of the load current Ib increases. In the comparative example, the conversion efficiency is 20% when the magnitude of the load current Ib is 0.075 A. As described above, the embodiment method can significantly reduce power loss compared to the comparative example.

[0082] Second Embodiment Next, a high-voltage power supply according to a second embodiment of the present disclosure will be described. FIG. 18 is a circuit diagram showing a high-voltage power supply 1A according to the second embodiment. The high-voltage power supply 1A includes a current detection circuit CT3 instead of the current detection element CT1 of the first embodiment. The current detection circuit CT3 outputs an inverter resonant current signal Ic1. The high-voltage power supply 1A further includes an amplitude control circuit CT4. The amplitude control circuit CT4 adjusts the amplitude of the inverter resonant current signal Ic1 to a predetermined value to generate an inverter resonant current signal Ic3. The inverter control circuit 4 detects the phase angle of the output current Ia based on the inverter resonant current signal Ic3, and controls the inverter 3 based on the phase angle and the magnitude of the output current Ia obtained from the inverter resonant current signal Ic1. The other configuration of the high-voltage power supply 1A is similar to that of the high-voltage power supply 1 according to the first embodiment.

[0083] 19 is a block diagram showing an outline of the overall configuration of the current detection circuit CT3. The current detection circuit CT3 is a circuit for detecting the magnitude (amount of current) of the output current Ia flowing through a certain current path CP. As shown in FIG. 19, the current detection circuit CT3 includes current sensor circuits 10A to 10E, a detection output circuit 20, an amplifier circuit 30, a maximum value detection circuit 40, a first gain control circuit 50, a second gain control circuit 60, a state memory circuit 70, and a detection timing generation circuit 80.

[0084] The current path CP includes multiple (five in the illustrated example) current paths CP1 to CP5 connected in parallel. The output current Ia is split into the current paths CP1 to CP5 and then merges back into a single current. Current sensor circuits 10A to 10E are provided for each of the current paths CP1 to CP5.

[0085] The current detection range of the current sensor circuit 10A has a first upper limit. In one example, the first upper limit is 5 amperes. The lower limit of the current detection range is, for example, 0 amperes. The current sensor circuit 10A generates a detection signal Se1 corresponding to the magnitude of the shunted output current Ia within the current detection range. Furthermore, the current sensor circuit 10A holds the magnitude of the detection signal Se1 and outputs a hold signal Sh1 indicating the magnitude of the held detection signal Se1.

[0086] The current detection range of the current sensor circuit 10B has a second upper limit value that is greater than the first upper limit value. In one example, the second upper limit value is 10 amperes. The lower limit value of the current detection range is, for example, 0 amperes. The current sensor circuit 10B generates a detection signal Se2 that corresponds to the magnitude of the shunted output current Ia within the current detection range. Furthermore, the current sensor circuit 10B holds the magnitude of the detection signal Se2 and outputs a hold signal Sh2 that indicates the magnitude of the held detection signal Se2.

[0087] The current detection range of the current sensor circuit 10C has a third upper limit value that is greater than the second upper limit value. In one example, the third upper limit value is 20 amperes. The lower limit value of the current detection range is, for example, 0 amperes. The current sensor circuit 10C generates a detection signal Se3 that corresponds to the magnitude of the shunted output current Ia within the current detection range. Furthermore, the current sensor circuit 10C holds the magnitude of the detection signal Se3 and outputs a hold signal Sh3 that indicates the magnitude of the held detection signal Se3.

[0088] The current detection range of the current sensor circuit 10D has a fourth upper limit value that is greater than the third upper limit value. In one example, the fourth upper limit value is 30 amperes. The lower limit value of the current detection range is, for example, 0 amperes. The current sensor circuit 10D generates a detection signal Se4 that corresponds to the magnitude of the shunted output current Ia within the current detection range. Furthermore, the current sensor circuit 10D holds the magnitude of the detection signal Se4 and outputs a hold signal Sh4 that indicates the magnitude of the held detection signal Se4.

[0089] The current detection range of the current sensor circuit 10E has a fifth upper limit value that is greater than the fourth upper limit value. In one example, the fifth upper limit value is 50 amperes. The lower limit value of the current detection range is, for example, 0 amperes. The current sensor circuit 10E generates a detection signal Se5 that corresponds to the magnitude of the shunted output current Ia within the current detection range. Furthermore, the current sensor circuit 10E holds the magnitude of the detection signal Se5 and outputs a hold signal Sh5 that indicates the magnitude of the held detection signal Se5.

[0090] The detection output circuit 20 includes an adder circuit 23 and a signal amplifier circuit 22. The adder circuit 23 multiplies the detection signal Se1 by a first coefficient, the detection signal Se2 by a second coefficient, the detection signal Se3 by a third coefficient, the detection signal Se4 by a fourth coefficient, and the detection signal Se5 by a fifth coefficient, and then adds the detection signals Se1 to Se5 to generate a sum signal Sa1. The second coefficient is smaller than the first coefficient, the third coefficient is smaller than the second coefficient, the fourth coefficient is smaller than the third coefficient, and the fifth coefficient is smaller than the fourth coefficient. The group of values ​​consisting of the first to fifth coefficients is inversely proportional to the group of values ​​consisting of the first to fifth upper limit values. For example, if the first to fifth upper limit values ​​are 5 amperes, 10 amperes, 20 amperes, 30 amperes, and 50 amperes, respectively, examples of the first to fifth coefficients are 1.0, 0.5, 0.25, 0.17, and 0.1, respectively.

[0091] The signal amplifier circuit 22 amplifies the sum signal Sa1 with a gain that is variable in stages. The gain of the signal amplifier circuit 22 is set in stages so that the gain decreases as the output current Ia increases. The number of gain stages is the same as the number of current sensor circuits 10A to 10E (five in this example). The detection output circuit 20 outputs the sum signal Sa1 amplified by the signal amplifier circuit 22 as an inverter resonant current signal Ic1 that indicates the magnitude of the output current Ia.

[0092] The amplifier circuit 30 amplifies the sum signal Sa1 output from the adder circuit 23. The maximum value detection circuit 40 detects the maximum value of the sum signal Sa1 after amplification by the amplifier circuit 30. The maximum value detection circuit 40 outputs a signal Sb indicating the maximum value of the sum signal Sa1.

[0093] The first gain control circuit 50 switches the gain of the signal amplifier circuit 22 when the output current Ia increases. The first gain control circuit 50 switches the gain of the signal amplifier circuit 22 so that the gain of the signal amplifier circuit 22 decreases in stages. That is, when the detection signal Se1 exceeds a predetermined threshold (e.g., a value corresponding to 80% of the upper limit of the current detection range of the current sensor circuit 10A), the first gain control circuit 50 outputs a control signal Su1 for switching the gain of the signal amplifier circuit 22 so that the gain of the signal amplifier circuit 22 decreases. When the detection signal Se2 exceeds a predetermined threshold (e.g., a value corresponding to 80% of the upper limit of the current detection range of the current sensor circuit 10B), the first gain control circuit 50 outputs a control signal Su2 for switching the gain of the signal amplifier circuit 22 so that the gain of the signal amplifier circuit 22 decreases further. The first gain control circuit 50 also outputs control signals Su3 and Su4 to switch the gain of the signal amplifier circuit 22 so that the gain of the signal amplifier circuit 22 becomes even smaller when the detection signal Se3 exceeds a predetermined threshold value (for example, a value equivalent to 80% of the upper limit value of the current detection range of the current sensor circuit 10C) and when the detection signal Se4 exceeds a predetermined threshold value (for example, a value equivalent to 80% of the upper limit value of the current detection range of the current sensor circuit 10D).

[0094] In the illustrated example, the first gain control circuit 50 determines the timing to reduce the gain of the signal amplifier circuit 22 based on whether the hold signals Sh1 to Sh4, instead of the detection signals Se1 to Se4, exceed a predetermined threshold. The first gain control circuit 50 also constantly stores the gain switching state of the signal amplifier circuit 22 (the gain value of the signal amplifier circuit 22). The predetermined threshold values ​​for the hold signals Sh1 to Sh4 are set to values ​​corresponding to the upper limit of the current detection range of each of the current sensor circuits 10A to 10D, or to values ​​slightly smaller than the upper limit.

[0095] The second gain control circuit 60 switches the gain of the signal amplifier circuit 22 when the output current Ia drops. The second gain control circuit 60 switches the gain of the signal amplifier circuit 22 so that the gain of the signal amplifier circuit 22 increases stepwise at multiple timings based on the magnitude of the addition signal Sa1 and the gain switching state of the signal amplifier circuit 22 stored in the first gain control circuit 50. To achieve this, the second gain control circuit 60 outputs control signals Sv1 to Sv4. The multiple timings are, for example, timings when the magnitude of the output current Ia falls below the upper limit of the current detection range of each of the current sensor circuits 10A to 10D, or timings slightly later than those timings. The magnitude of the addition signal Sa1 can be obtained from the signal Sb output from the maximum value detection circuit 40.

[0096] Based on the control signals Su1 to Su4 output from the first gain control circuit 50 and the control signals Sv1 to Sv4 output from the second gain control circuit 60, the state memory circuit 70 generates control signals Sx1 to Sx4 for switching a switch (described later) that determines the gain of the signal amplifier circuit 22. The state memory circuit 70 outputs the control signals Sx1 to Sx4 and holds the control signals Sx1 to Sx4 as long as there is no change in the control signals Su1 to Su4 and the control signals Sv1 to Sv4.

[0097] The detection timing generation circuit 80 generates and outputs a detection timing signal Sz that indicates one cycle of the sinusoidal output current Ia. For example, the detection timing generation circuit 80 detects the timing at which the output current Ia changes from a negative current to a positive current, or the timing at which the output current Ia changes from a positive current to a negative current, and generates the detection timing signal Sz.

[0098] Next, a specific example of the circuit configuration of the current detection circuit CT3 will be described. FIG. 20 is a circuit diagram showing a specific example of the internal configuration of the current sensor circuits 10A to 10E. The current sensor circuits 10A to 10E have the same internal configuration. As shown in FIG. 20, each of the current sensor circuits 10A to 10E includes a current detector 11A including a Hall element, an offset power supply 12, a buffer 13, and a signal hold circuit 14. Note that an AC source 15 in the figure simulates the source of the output current Ia, and a resistor 16 simulates the load resistance.

[0099] In each of the current sensor circuits 10A to 10E, a resistor 10a and a resistor 10b are provided in series in each of the current paths CP1 to CP5 to limit the current. A current detector 11A is provided in each of the current paths CP1 to CP5 between the resistors 10a and 10b. The current detector 11A detects the flow of AC current in a non-contact manner and outputs a corresponding voltage signal Va. The voltage signal Va from the current detector 11A is input to a buffer 13, and the amplified voltage signal Va is output from each of the current sensor circuits 10A to 10E as detection signals Se1 to Se5, respectively.

[0100] The signal holding circuit 14 receives the voltage signal Va from the current detector 11A. The signal holding circuit 14 includes a diode bridge 141 and a capacitor 142. The voltage signal Va is input to one input terminal of the diode bridge 141, and an offset voltage from the offset power supply 12 is input to the other input terminal. The diode bridge 141 rectifies the voltage signal Va using the offset voltage as a reference potential. The capacitor 142 holds (peak-holds) the voltage value of the rectified voltage signal Va and generates holding signals Sh1 to Sh5.

[0101] The charge in the capacitor 142 is reset by a switch 143 connected in parallel to the capacitor 142. The switch 143 resets the capacitor 142 in response to a reset signal Sr input to a control terminal from a detection timing generation circuit 80 (described later). This allows the capacitor 142 to prepare for signal holding (peak detection) in the next cycle.

[0102] A switch 144 is provided on the path of the holding signals Sh1 to Sh5 output from the capacitor 142. The conductive state of the switch 144 is controlled by a synchronization signal Sy input from outside the current sensor circuits 10A to 10E via an amplifier 145. The switch 144 is periodically turned on, and at that time, the holding signals Sh1 to Sh5 are output from the current sensor circuits 10A to 10E, respectively.

[0103] 21 is a circuit diagram showing another specific example of the internal configuration of current sensor circuits 10A to 10E. In this example, each of current sensor circuits 10A to 10E has a current detector 11B including a current transformer instead of current detector 11A shown in FIG. 20. Also, offset power supply 12 is omitted, and a reference potential is input to the other input terminal of diode bridge 141.

[0104] FIG. 22 is a circuit diagram showing a specific example of the internal configuration of the detection output circuit 20. As described above, the detection output circuit 20 includes an adder circuit 23 and a signal amplifier circuit 22. The adder circuit 23 multiplies the detection signals Se1 to Se5 output from the current sensor circuits 10A to 10E by first to fifth coefficients, respectively, and then adds the detection signals Se1 to Se5. The adder circuit 23 includes a plurality of resistors 231 to 235 corresponding to the current sensor circuits 10A to 10E, a feedback resistor 236, and an operational amplifier 237. The detection signals Se1 to Se5 from the current sensor circuits 10A to 10E are input to one end of each of the resistors 231 to 235. The other end of each of the resistors 231 to 235 is connected to one input terminal of the operational amplifier 237. An offset voltage is input to the other input terminal of the operational amplifier 237 from an offset power supply 238. The feedback resistor 236 is connected between one input terminal and the output terminal of the operational amplifier 237. The resistance values ​​of the resistors 231 to 235 correspond to the first to fifth coefficients, respectively. For example, if the feedback resistor 236 is 10 kΩ and the first to fifth coefficients are 1.0, 0.5, 0.25, 0.17, and 0.1, respectively, the resistances of the resistors 231 to 235 are 10 kΩ, 20 kΩ, 40 kΩ, 60 kΩ, and 100 kΩ, respectively. The sum signal Sa1 is output from the output terminal of the operational amplifier 237.

[0105] The signal amplifier circuit 22 is an inverting amplifier circuit with a variable feedback resistance value. The signal amplifier circuit 22 includes multiple feedback resistors 221 to 225, a resistor 226, and an operational amplifier 227. The resistor 226 is connected between the output terminal of the operational amplifier 237 and one input terminal of the operational amplifier 227. An offset voltage is input to the other input terminal of the operational amplifier 227 from an offset power supply 238. The feedback resistors 221 to 225 are connected in parallel with each other between one input terminal of the operational amplifier 227 and the output terminal of the operational amplifier 227. Furthermore, switches Q1 to Q4 are connected in series with the feedback resistors 221 to 224, respectively, between the feedback resistors 221 to 224 and one input terminal (or output terminal) of the operational amplifier 227. The connection state of each of the switches Q1 to Q4 is controlled by control signals Sx1 to Sx4, respectively. The magnitude of the feedback resistance changes depending on the control signals Sx1 to Sx4, thereby changing the gain of the signal amplifier circuit 22. In one example, the resistance values ​​of the feedback resistors 221 to 225 are equal to each other. The inverter resonant current signal Ic1 is output from the output terminal of the operational amplifier 227.

[0106] 23 is a circuit diagram showing a specific example of the internal configuration of the amplifier circuit 30 and the maximum value detection circuit 40. The amplifier circuit 30 has an operational amplifier 33, a feedback resistor 34, and an offset power supply 35. The feedback resistor 34 is connected between one input terminal of the operational amplifier 33 and the output terminal of the operational amplifier 33. The addition signal Sa1 is input to one input terminal of the operational amplifier 33, and an offset voltage from the offset power supply 35 is input to the other input terminal of the operational amplifier 33.

[0107] The maximum value detection circuit 40 receives the amplified sum signal Sa1 from the amplifier circuit 30. The maximum value detection circuit 40 includes a diode bridge 401 and a capacitor 402. The amplified sum signal Sa1 is input to one input terminal of the diode bridge 401, and a reference potential is input to the other input terminal. The diode bridge 401 rectifies the amplified sum signal Sa1. The capacitor 402 holds (peak-holds) the voltage value of the rectified amplified sum signal Sa1 and generates a signal Sb indicating the maximum value of the sum signal Sa1.

[0108] The charge in the capacitor 402 is reset by a switch 403 connected in parallel to the capacitor 402. The switch 403 resets the capacitor 402 in response to a reset signal Sr input to a control terminal from a detection timing generation circuit 80, which will be described later. This allows the capacitor 402 to prepare for voltage holding (peak detection) in the next cycle.

[0109] A switch 404 is provided on the path of the signal Sb output from the capacitor 402. The conductive state of the switch 404 is controlled by a detection timing signal (sample-and-hold signal) Sz input from a detection timing generation circuit 80 (described later) via an amplifier 405. The detection timing signal Sz indicates the timing at which the output current Ia, which is an AC current, transitions from positive to negative. Therefore, the switch 404 is made conductive every cycle of the output current Ia, and at that time, a signal Sb is output from the maximum value detection circuit 40.

[0110] 24 is a circuit diagram showing a specific example of the internal configuration of first gain control circuit 50. First gain control circuit 50 has multiple circuit portions 51A to 51E corresponding to current sensor circuits 10A to 10E, respectively. Of these, circuit portions 51A to 51D have the same configuration.

[0111] The circuit portions 51A to 51E receive the hold signals Sh1 to Sh5 from the current sensor circuits 10A to 10E, respectively. Each of the hold signals Sh1 to Sh5 is input to one input terminal of a comparator 52. A threshold voltage Vth1 is input to the other input terminal of the comparator 52. The threshold voltage Vth1 is generated by a constant voltage source 53 and set to a voltage corresponding to the predetermined threshold value described above. The threshold voltages Vth1 of the circuit portions 51A to 51E may be equal to each other. Note that, in order to suppress oscillation of the control signal when changing the gain of the signal amplifier circuit 22, the threshold voltage Vth1 is forcibly set to the reference potential (low level) by a switch 54.

[0112] The output signal from the comparator 52 is held by the D flip-flop 55. The timing at which the D flip-flop 55 holds the output signal from the comparator 52 is controlled by a detection timing signal Sz input from the detection timing generation circuit 80.

[0113] Each of the circuit portions 51A to 51D has a narrow pulse generation circuit 56. The narrow pulse generation circuit 56 reduces the pulse width of the output signal from the D flip-flop 55 to generate the control signals Su1 to Su4. In the narrow pulse generation circuit 56, the output signal from the D flip-flop 55 is input to one input terminal of a logical product circuit 561. The output signal from the D flip-flop 55 is delayed by a resistor 562 and a capacitor 563, and a signal whose logic is inverted by an inverter 564 is input to the other input terminal of the logical product circuit 561. As a result, the logical product circuit 561 outputs control signals Su1 to Su4 with narrow pulse widths.

[0114] 25 is a circuit diagram showing a specific example of the internal configuration of the second gain control circuit 60. The second gain control circuit 60 has a plurality of circuit portions 61A to 61D corresponding to the current sensor circuits 10A to 10D, respectively. The circuit portions 61A to 61D have the same configuration.

[0115] Each of the circuit portions 61A-61D receives a signal Sb from the maximum value detection circuit 40. The signal Sb represents the magnitude of the sum signal Sa1. The signal Sb is input to one input terminal of a comparator 69. A threshold voltage Vth2 is input to the other input terminal of the comparator 69. The threshold voltage Vth2 is generated by a constant voltage source 63. As described above, the threshold voltage Vth2 is set to a voltage corresponding to, for example, the timing when the magnitude of the output current Ia falls below the upper limit of the current detection range of each of the current sensor circuits 10A-10D, or a timing slightly later than that timing. Therefore, the threshold voltages Vth2 of the circuit portions 61A-61D are different from each other. To suppress oscillation of the control signal when changing the gain of the signal amplifier circuit 22, the threshold voltage Vth2 is forced to a constant voltage V1 (high level) by a switch 64. The switch 64 is controlled by the control signals Sx1-Sx4, respectively, input via an amplifier 65. The logic of each of the control signals Sx 1 to Sx 4 is inverted by an inverter 66 and then input to a control terminal of the switch 64 .

[0116] The output signal from the comparator 69 is held by the D flip-flop 68. The timing at which the D flip-flop 68 holds the output signal from the comparator 69 is controlled by a detection timing signal Sz input from a detection timing generation circuit 80.

[0117] Each of the circuit portions 61A to 61D has a narrow pulse generation circuit 67. The narrow pulse generation circuit 67 reduces the pulse width of the output signal from a D flip-flop 68 to generate the control signals Sv1 to Sv4. In the narrow pulse generation circuit 67, the output signal from the D flip-flop 68 is input to one input terminal of a logical product circuit 671. The output signal from the D flip-flop 68 is delayed by a resistor 672 and a capacitor 673, and a signal whose logic is inverted by an inverter 674 is input to the other input terminal of the logical product circuit 671. As a result, the logical product circuit 671 outputs control signals Sv1 to Sv4 with narrow pulse widths.

[0118] 26 is a circuit diagram showing a specific example of the internal configuration of the state memory circuit 70. The state memory circuit 70 has a plurality of RS flip-flops 71A to 71D corresponding to the current sensor circuits 10A to 10D, respectively. Control signals Su1 to Su4 are input to one input terminal of each of the RS flip-flops 71A to 71D from the first gain control circuit 50. Control signals Sv1 to Sv4 are input to the other input terminal of each of the RS flip-flops 71A to 71D from the second gain control circuit 60, respectively. The RS flip-flops 71A to 71D generate control signals Sx1 to Sx4, respectively, based on the control signals Su1 to Su4, respectively, and the control signals Sv1 to Sv4, respectively.

[0119] 27 is a circuit diagram showing a specific example of the internal configuration of the detection timing generation circuit 80. The detection timing generation circuit 80 receives the detection signal Se1 from the current sensor circuit 10A. Alternatively, a separate current sensor circuit with lower sensitivity than the current sensor circuits 10A to 10E may be provided, and the detection timing generation circuit 80 may receive the detection signal from that current sensor circuit.

[0120] The detection signal Se1 is input to one input terminal of the comparator 81. A threshold voltage Vth3 is input to the other input terminal of the comparator 81. The threshold voltage Vth3 defines the reference potential (0 V) of the detection signals Se1 to Se5.

[0121] The detection timing generation circuit 80 includes a narrow pulse generation circuit 82. The narrow pulse generation circuit 82 reduces the pulse width of the output signal from the comparator 81 to generate the detection timing signal Sz. In the narrow pulse generation circuit 82, the output signal from the comparator 81 is input to one input terminal of a logical product circuit 821. The output signal from the comparator 81 is delayed by a resistor 822 and a capacitor 823, and a signal whose logic is inverted by an inverter 824 is input to the other input terminal of the logical product circuit 821. As a result, the logical product circuit 821 outputs a detection timing signal Sz with a small pulse width. The detection timing signal Sz is output from the detection timing generation circuit 80, and its logic is inverted by an inverter 83 before being input to one input terminal of the logical product circuit 84.

[0122] The detection timing generation circuit 80 further includes a pulse generation circuit 85. The pulse generation circuit 85 pulses the output signal from the comparator 81 to generate an internal pulse signal Sp. In the pulse generation circuit 85, the output signal from the comparator 81 is input to one input terminal of a logical product circuit 851. The output signal from the comparator 81 is delayed by a resistor 852 and a capacitor 853, and a signal whose logic is inverted by an inverter 854 is input to the other input terminal of the logical product circuit 851. The delay time at this time is longer than the delay time of the narrow pulse generation circuit 82. As a result, the logical product circuit 851 outputs an internal pulse signal Sp. The internal pulse signal Sp is input to the other input terminal of the logical product circuit 84. The logical product circuit 84 outputs the logical product of the detection timing signal Sz, whose logic has been inverted, and the internal pulse signal Sp as a reset signal Sr.

[0123] 28 is a graph showing example time waveforms of the output current Ia, control signals Su1 to Su4, control signals Sv1 to Sv4, control signals Sx1 to Sx4, and inverter resonant current signal Ic1 in the current detection circuit CT3 of this embodiment. Note that the control signals Su1 to Su4 are negative logic, and the control signals Sv1 to Sv4 and control signals Sx1 to Sx4 are positive logic.

[0124] As shown in FIG. 28, while the output current Ia is rising, the control signal Su1 first turns on, and simultaneously the control signal Sv1 turns off (timing T1 in the figure). This causes the control signal Sx1 to turn on, and the gain of the signal amplifier circuit 22 is switched to a smaller value. As the output current Ia continues to rise, the control signal Su2 turns on, and simultaneously the control signal Sv2 turns off (timing T2 in the figure). This causes the control signal Sx2 to turn on, and the gain of the signal amplifier circuit 22 is switched to an even smaller value. As the output current Ia continues to rise, the control signal Su3 turns on, and simultaneously the control signal Sv3 turns off (timing T3 in the figure). This causes the control signal Sx3 to turn on, and the gain of the signal amplifier circuit 22 is switched to an even smaller value. As the output current Ia continues to rise, the control signal Su4 turns on, and simultaneously the control signal Sv4 turns off (timing T4 in the figure). This switches the control signal Sx4 to the ON state, further reducing the gain of the signal amplifier circuit 22. When the output current Ia drops, the control signals Su1 to Su4, Sv1 to Sv4, and Sx1 to Sx4 return to the OFF state when the output current Ia falls below the current value corresponding to timings T1 to T4 or a value close to that value.

[0125] 29 is a block diagram showing the overall configuration of a current detection circuit CT3A according to another configuration example. The current detection circuit CT3A differs from the current detection circuit CT3 in that it includes an adder circuit 90, but is the same as the current detection circuit CT3 in other respects.

[0126] The adder circuit 90 adds the detection signals Se1 to Se5 to generate the sum signal Sa2. At this time, the detection signals Se1 to Se5 may all be multiplied by the same coefficient. The amplifier circuit 30 in this configuration example amplifies the sum signal Sa2 output from the adder circuit 90, rather than the sum signal Sa1 output from the adder circuit 23. The maximum value detection circuit 40 detects the maximum value of the sum signal Sa2 after amplification by the amplifier circuit 30. The maximum value detection circuit 40 outputs a signal Sb indicating the maximum value of the sum signal Sa2.

[0127] 30 is a circuit diagram showing a specific example of the adder circuit 90, amplifier circuit 30, and maximum value detection circuit 40 of this configuration example. The configuration of the adder circuit 90 is the same as that of the adder circuit 23, except that the resistance values ​​of the resistors 231 to 235 corresponding to the current sensor circuits 10A to 10E, respectively, are equal to each other.

[0128] Next, a specific configuration example of the amplitude control circuit CT4 will be described. FIG. 31 is a block diagram schematically illustrating the configuration of the amplitude control circuit CT4. The amplitude control circuit CT4 is electrically connected to the current detection circuit CT3 and receives the inverter resonant current signal Ic1. The amplitude control circuit CT4 adjusts the amplitude of the inverter resonant current signal Ic1 to a predetermined range. FIG. 32 is a diagram conceptually illustrating the function of the amplitude control circuit CT4. The amplitude of the inverter resonant current signal Ic1 (input signal) input to the amplitude control circuit CT4 changes depending on the magnitude of the output current Ia. The figure shows an example in which the amplitude of the inverter resonant current signal Ic1 gradually increases. The amplitude control circuit CT4 controls the amplitude of this inverter resonant current signal Ic1 to be a constant value regardless of the passage of time. The figure also shows an inverter resonant current signal Ic3 (output signal) that is kept constant. In other words, the inverter resonant current signal Ic3 has an amplitude Aout that remains constant regardless of time.

[0129] Referring again to FIG. 31 , the amplitude control circuit CT4 includes an attenuation circuit 104, an amplifier circuit 105, and an error signal generation circuit 110. The attenuation circuit 104 attenuates the amplitude of the inverter resonant current signal Ic1 to generate a signal Sf1. The amplifier circuit 105 is provided downstream of the attenuation circuit 104 and receives the signal Sf1. The amplifier circuit 105 amplifies the signal Sf1 to generate a signal Sf2. The signal Sf2 is output from the amplitude control circuit CT4 as the inverter resonant current signal Ic3. The error signal generation circuit 110 is provided downstream of the amplifier circuit 105 and generates an error signal Sf5 indicating the difference between the amplitude of the signal Sf2 and a predetermined width. The attenuation circuit 104 adjusts the attenuation amount of the amplitude of the signal Sf1 based on the error signal Sf5. The amplifier circuit 105 adjusts the amplification gain of the signal Sf2 based on the error signal Sf5.

[0130] The error signal generating circuit 110 includes an amplitude detection circuit 106, a peak detection circuit 107, and an error amplifier 108. The amplitude detection circuit 106 includes a diode and full-wave rectifies the signal Sf2 to generate a DC signal Sf3, which is a pulsating voltage corresponding to the amplitude of the signal Sf2. The peak detection circuit 107 is provided downstream of the amplitude detection circuit 106 and includes a smoothing capacitor. It smooths the DC signal Sf3 to generate a DC signal Sf4, which is a smooth DC voltage. The voltage value of the DC signal Sf4 indicates the amplitude of the signal Sf2. The error amplifier 108 is provided downstream of the peak detection circuit 107. The error amplifier 108 generates an error signal Sf5 indicating the difference between the DC signal Sf4 and a predetermined voltage value. The error amplifier 108 is configured to include, for example, a subtractor using an operational amplifier.

[0131] The amplitude control circuit CT4 further includes a signal amplitude detection circuit 109. The signal amplitude detection circuit 109 generates an amplitude signal Sf6 that indicates the amplitude of the output current Ia. The amplitude control circuit CT4 provides the generated amplitude signal Sf6 to the attenuation circuit 104. The attenuation circuit 104 is configured to operate when the amplitude signal Sf6 exceeds a threshold, i.e., when the amplitude of the output current Ia is greater than the threshold, and not operate when the amplitude signal Sf6 does not exceed the threshold, i.e., when the amplitude of the output current Ia is smaller than the threshold.

[0132] The amplitude control circuit CT4 of this embodiment includes multiple voltage control circuits configured to conduct in both positive and negative directions, and automatically controls the gain of the inverter resonant current signal Ic1 by individually changing the conductance (gm) of each voltage control circuit in accordance with the amplitude of the input inverter resonant current signal Ic1.

[0133] 33 is a circuit diagram showing a specific example of the internal configuration of the attenuation circuit 104. The attenuation circuit 104 is configured to attenuate the amplitude of the inverter resonant current signal Ic1. The attenuation circuit 104 includes a first FET 410, a second FET 420, an isolation amplifier 430, a switch 440, a comparator 450, a constant voltage source 460, a constant voltage source 470, a first resistor 482, a second resistor 483, and resistors 481 and 484. The first FET 410 and the second FET 420 constitute one stage of the multi-stage voltage control circuit described above. The resistor 481 is provided on the wiring 4b that propagates the inverter resonant current signal Ic1. The inverter resonant current signal Ic1 reaches a node Na on the wiring 4b via the resistor 481.

[0134] The first FET 410 and the second FET 420 are connected in series between the node Na and the constant potential line 4c and are connected back-to-back. At least one of the first FET 410 and the second FET 420 is a MOSFET or a JFET. In the illustrated example, the first FET 410 and the second FET 420 are configured as N-type MOSFETs, and the source terminal of the first FET 410 and the source terminal of the second FET 420 are connected to each other. In the illustrated example, the first FET 410 includes a plurality of Darlington-connected FETs 411 and 412. Similarly, the second FET 420 includes a plurality of Darlington-connected FETs 421 and 422. This is not limited to the illustrated example, and only one of the first FET 410 and the second FET 420 may include a plurality of Darlington-connected FETs. At least one of the first FET 410 and the second FET 420 may be configured as a single FET.

[0135] The constant potential line 4c is connected to the reference potential GND via the constant voltage source 470. As a result, the constant potential line 4c maintains a constant potential determined by the constant voltage source 470 and offset from the reference potential GND.

[0136] The first resistor element 482 is connected in series with the first FET 410 and the second FET 420, and has one end connected to the source terminal of the first FET 410. The second resistor element 483 is connected in series with the first FET 410 and the second FET 420, and has one end connected to the source terminal of the second FET 420. The other end of the first resistor element 482 and the other end of the second resistor element 483 are connected to each other via node Nb.

[0137] The resistance value between the source and drain of the first FET 410 and the second FET 420 changes depending on the magnitude of the gate signal Sc1 input to the gate terminals of the first FET 410 and the second FET 420. In other words, the conductance of the series circuit including the first FET 410 and the second FET 420 changes depending on the magnitude of the gate signal Sc1 input to the gate terminals of the first FET 410 and the second FET 420. The amplitude of the inverter resonant current signal Ic1 is attenuated depending on the resistance value or conductance, and the signal Sf1 is generated.

[0138] A gate signal Sc1 based on the error signal Sf5 is input to the gate terminals of the first FET 410 and the second FET 420. Specifically, the isolation amplifier 430 generates the gate signal Sc1, which is a voltage signal, and applies the gate signal Sc1 between the other end (node ​​Nb) of the first resistor element 482 and the gate terminal of the first FET 410, and between the other end (node ​​Nb) of the second resistor element 483 and the gate terminal of the second FET 420. The isolation amplifier 430 receives the error signal Sf5 from the error signal generation circuit 110 and generates the gate signal Sc1 from the error signal Sf5. Therefore, the amplitude of the signal Sf1 is determined by the error signal Sf5.

[0139] A resistive element 484 is provided on the path along which the error signal Sf5 propagates to the isolation amplifier 430. The error signal Sf5 is provided to the isolation amplifier 430 via the resistive element 484. One end of a switch 440 is connected to a node Nc between the resistive element 484 and the isolation amplifier 430. The other end of the switch 440 is connected to the reference potential GND. When the switch 440 is in a non-connected state, the error signal Sf5 is provided to the isolation amplifier 430. Therefore, in this case, the attenuation circuit 104 performs an attenuation operation. On the other hand, when the switch 440 is in a connected state, the error signal Sf5 flows to the reference potential GND through the switch 440 and is not provided to the isolation amplifier 430. Therefore, in this case, the attenuation circuit 104 does not perform an attenuation operation.

[0140] The state of switch 440 is controlled by the output voltage from comparator 450. A predetermined threshold voltage is input to one input terminal of comparator 450 from constant voltage source 460. An amplitude signal Sf6 is input to the other input terminal of comparator 450 from signal amplitude detection circuit 109 (see FIG. 31 ). Comparator 450 compares amplitude signal Sf6 with the threshold voltage, and when amplitude signal Sf6 exceeds the threshold voltage, it puts switch 440 in a non-connected state, and when amplitude signal Sf6 does not exceed the threshold voltage, it puts switch 440 in a connected state.

[0141] 34 is a circuit diagram showing a specific example of the internal configuration of the amplifier circuit 105. The amplifier circuit 105 amplifies the amplitude of the signal Sf1 in accordance with the gain to generate the signal Sf2. The amplifier circuit 105 has an operational amplifier 51, a signal input terminal 501, and a gain determination circuit 502. The signal input terminal 501 is connected to the wiring 4b (see FIG. 33) and receives the signal Sf1. One input terminal of the operational amplifier 51 is connected to the signal input terminal 501, and the signal Sf1 is input via the signal input terminal 501. The output terminal of the operational amplifier 51 is feedback-connected to one input terminal via a feedback resistor 581.

[0142] The gain determination circuit 502 determines the gain of the amplifier circuit 105 for the signal Sf1. The gain determination circuit 502 includes a third FET 52, a fourth FET 53, an isolation amplifier 504, a constant voltage source 470, a third resistor element 582, and a fourth resistor element 583. The third FET 52 and the fourth FET 53 constitute another stage of the above-mentioned multi-stage voltage control circuit. The constant voltage source 470 is shared with the attenuation circuit 104.

[0143] The third FET 52 and the fourth FET 53 are connected in series between a node Nd between the other input terminal of the operational amplifier 51 and the feedback resistor 581 and the constant potential line 503, and are connected back-to-back to each other. At least one of the third FET 52 and the fourth FET 53 is a MOSFET or a JFET. In the illustrated example, the third FET 52 and the fourth FET 53 are configured as N-type MOSFETs, and the source terminal of the third FET 52 and the source terminal of the fourth FET 53 are connected to each other. In the illustrated example, the third FET 52 includes a plurality of Darlington-connected FETs 521 and 522. Similarly, the fourth FET 53 includes a plurality of Darlington-connected FETs 531 and 532. This is not limited to the illustrated example, and only one of the third FET 52 and the fourth FET 53 may include a plurality of Darlington-connected FETs. At least one of the third FET 52 and the fourth FET 53 may be configured as a single FET.

[0144] The constant potential line 503 is connected to the reference potential GND via the constant voltage source 470. As a result, the constant potential line 503 maintains a constant potential that is determined by the constant voltage source 470 and is offset from the reference potential GND.

[0145] The third resistor element 582 is connected in series with the third FET 52 and the fourth FET 53, and has one end connected to the source terminal of the third FET 52. The fourth resistor element 583 is connected in series with the third FET 52 and the fourth FET 53, and has one end connected to the source terminal of the fourth FET 53. The other end of the third resistor element 582 and the other end of the fourth resistor element 583 are connected to each other via a node Ne.

[0146] The resistance between the source and drain of the third FET 52 and the fourth FET 53 changes depending on the magnitude of the gate signal Sc2 input to the gate terminals of the third FET 52 and the fourth FET 53. In other words, the conductance of the series circuit including the third FET 52 and the fourth FET 53 changes depending on the magnitude of the gate signal Sc2 input to the gate terminals of the third FET 52 and the fourth FET 53. The gain of the amplifier circuit 105 changes depending on the resistance or conductance.

[0147] A gate signal Sc2 based on the error signal Sf5 is input to the gate terminals of the third FET 52 and the fourth FET 53. Specifically, the isolation amplifier 504 generates the gate signal Sc2, which is a voltage signal, and applies the gate signal Sc2 between the other end (node ​​Ne) of the third resistor element 582 and the gate terminal of the third FET 52, and between the other end (node ​​Ne) of the fourth resistor element 583 and the gate terminal of the fourth FET 53. The isolation amplifier 504 receives the error signal Sf5 from the error signal generation circuit 110 and generates the gate signal Sc2 from the error signal Sf5. Therefore, the amplitude of the signal Sf2 is determined by the error signal Sf5.

[0148] While the principles of the present invention have been illustrated and described in preferred embodiments, it will be recognized by those skilled in the art that the present invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the particular constructions disclosed herein. We therefore claim all modifications and variations that come within the scope and spirit of the following claims.

[0149] 1...High voltage power supply, 3...Inverter, 4, 4A...Inverter control circuit, 5...Resonant circuit, 41...Comparator, Cp1, Cp2...Winding capacitance (parasitic capacitance), Cr...Resonant capacitor (capacitor), Fd1...First drive frequency, Fd2...Second drive frequency, Fr1...First resonant frequency, Fr2...Second resonant frequency, Ib...Load current, Ia...Output current, Lr...Resonant inductance (parasitic inductance), N1...Primary winding, TR...Transformer, Vb...Load voltage, Iref, IrefA...Threshold value, Vth...Voltage threshold value.

Claims

1. A power supply circuit that generates a DC voltage, an inverter connected to the power supply circuit and converting the DC voltage into an AC voltage, an inverter control circuit connected to the inverter and controlling the inverter, and a resonant circuit connected between the inverter and a load and boosting the AC voltage to drive the load, wherein the resonant circuit has: a transformer including a primary winding and a secondary winding insulated from the primary winding and connected to the load, a capacitor connected in series to the primary winding between the inverter and the primary winding, a resonant inductance connected in series with the capacitor, a first parasitic capacitance present in parallel with the primary winding of the transformer, and a second parasitic capacitance present in parallel with the secondary winding of the transformer, and the resonant frequency of the resonant circuit includes: a first resonant frequency based on the capacitor and the resonant inductance, and a second resonant frequency higher than the first resonant frequency based on the capacitor, the resonant inductance, the first parasitic capacitance, and the second parasitic capacitance, a high-voltage power supply that controls the inverter at a first drive frequency that follows the first resonant frequency when the load is heavy and the electrical parameter representing the magnitude of the load exceeds a threshold value; and that controls the inverter at a second drive frequency that is higher than the first drive frequency and between the first resonant frequency and the second resonant frequency when the load is light and the electrical parameter is equal to or less than the threshold value.

2. The high-voltage power supply according to claim 1, wherein the inverter control circuit, in the case of a heavy load in which the electrical parameter exceeds the threshold value, sets the one drive frequency so that the phase of the signal controlling the inverter is synchronized with the phase of the output current of the inverter and the phase of the output current of the inverter lags behind the phase of the signal controlling the inverter.

3. A high-voltage power supply according to claim 1 or 2, wherein the inverter control circuit sets the second drive frequency so that, in the case of a light load in which the electrical parameter is equal to or less than the threshold value, the length of a half cycle of the second drive frequency is longer than the length of one cycle of the output current of the inverter, and the phase of the output current of the inverter lags the phase of the signal controlling the inverter.

4. A high-voltage power supply according to any one of claims 1 to 3, wherein the inverter control circuit controls the inverter at the first drive frequency, regardless of the magnitude of the load, from immediately after operation starts until the load voltage supplied to the load reaches a voltage threshold.

5. A high-voltage power supply according to any one of claims 1 to 4, wherein the capacitance value of the capacitor is set so that the second resonant frequency is between two and three times the first resonant frequency.

6. A high-voltage power supply according to any one of claims 1 to 5, wherein the electrical parameter is the magnitude of the load current supplied to the load.

7. A high-voltage power supply according to any one of claims 1 to 6, wherein the electrical parameter is the length of a half cycle of the output current of the inverter.

8. A high-voltage power supply according to any one of claims 1 to 7, wherein the inverter control circuit sets the second drive frequency so that, when the load is light and the electrical parameter is equal to or less than the threshold value, the second drive frequency corresponds to a period that is at least an even multiple of the length of half the period of the output current of the inverter.

9. A high-voltage power supply according to any one of claims 1 to 8, wherein the inverter control circuit further comprises a comparator for comparing the electrical parameter with the threshold value, the comparator having hysteresis.

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