Pixel, driving method of pixel, and electronic device comprising pixel

Abstract

This pixel comprises: a first-1 light-emission control transistor including a first semiconductor pattern and a first light-emission control gate electrode overlapping a first-1 light-emission control channel region of the first semiconductor pattern; a second-1 light-emission control transistor including a second semiconductor pattern and a second light-emission control gate electrode overlapping a second-1 light-emission control channel region of the second semiconductor pattern; a first light-emission control signal line transmitting a first light-emission control signal and connected to the first light-emission control gate electrode; a second light-emission control signal line transmitting a second light-emission control signal and connected to the second light-emission control gate electrode; a first light-emitting element connected to the first-1 light-emission control transistor and emitting light of a first color; and a second light-emitting element connected to the second-1 light-emission control transistor and emitting light of a second color.

Description

Pixel, method of driving pixel, and electronic device including pixel

[0001] The present disclosure relates to a pixel, a method of driving a pixel, and an electronic device including a pixel.

[0002] Light-emitting devices (e.g., Micro LEDs) can generate light by receiving an electric current. In order for the light-emitting device to generate light with optimal efficiency, the current density of the injected current (e.g., A / cm) must be 2 It is necessary to appropriately adjust the units (expressed in units such as etc.).

[0003] The present disclosure provides a pixel with improved luminous efficiency and a method for driving the same.

[0004] A pixel according to embodiments of the present disclosure includes a first-first light-emitting control transistor including a first semiconductor pattern and a first light-emitting control gate electrode overlapping a first-first light-emitting control channel region of the first semiconductor pattern; a second-first light-emitting control transistor including a second semiconductor pattern and a second light-emitting control gate electrode overlapping a second-first light-emitting control channel region of the second semiconductor pattern; a first light-emitting control signal line transmitting a first light-emitting control signal and connected to the first light-emitting control gate electrode; a second light-emitting control signal line transmitting a second light-emitting control signal and connected to the second light-emitting control gate electrode; a first light-emitting element connected to the first-first light-emitting control transistor and emitting light of a first color; and a second light-emitting element connected to the second-first light-emitting control transistor and emitting light of a second color.

[0005] In one embodiment, the pixel may further include a first anode electrode connected to a second terminal of the first-first light-emitting control transistor; a second anode electrode connected to a second terminal of the second-first light-emitting control transistor and spaced apart from the first anode electrode; and a cathode electrode spaced apart from the first and second anode electrodes.

[0006] In one embodiment, the first light-emitting element may be connected between the first anode electrode and the cathode electrode, and the second light-emitting element may be connected between the second anode electrode and the cathode electrode.

[0007] In one embodiment, the first light-emitting element may include a 1-1 semiconductor layer having a first polarity, a 1-2 semiconductor layer having a second polarity, and a first active layer interposed between the 1-1 semiconductor layer and the 1-2 semiconductor layer, and the second light-emitting element may include a 2-1 semiconductor layer having the first polarity, a 2-2 semiconductor layer having the second polarity, and a second active layer interposed between the 2-1 semiconductor layer and the 2-2 semiconductor layer.

[0008] In one embodiment, the material constituting the first active layer may be different from the material constituting the second active layer.

[0009] In one embodiment, the pixel may further include a first-second light-emitting control transistor including the first light-emitting control gate electrode overlapping the first semiconductor pattern and the first-second light-emitting control channel region of the first semiconductor pattern; and a second-second light-emitting control transistor including the second light-emitting control gate electrode overlapping the second semiconductor pattern and the second-second light-emitting control channel region of the second semiconductor pattern.

[0010] In one embodiment, the pixel may further include a first driving transistor connected between a first terminal of the 1-1 light-emitting control transistor and a second terminal of the 1-2 light-emitting control transistor, the first driving transistor including a first driving gate electrode overlapping the first semiconductor pattern and a first driving channel region of the first semiconductor pattern; and a second driving transistor connected between a first terminal of the 2-1 light-emitting control transistor and a second terminal of the 2-2 light-emitting control transistor, the second driving transistor including a second driving gate electrode overlapping the second semiconductor pattern and a second driving channel region of the second semiconductor pattern.

[0011] In one embodiment, the channel length of the first drive channel region may be smaller than the channel length of the second drive channel region, and the channel width of the first drive channel region may be larger than the channel width of the second drive channel region.

[0012] In one embodiment, the pixel may further include a first data line transmitting a first data signal; a second data line transmitting a second data signal; a first data write transistor connected between a first terminal of the first driving transistor and the first data line, the first data write transistor including a first data write gate electrode overlapping the first semiconductor pattern and a first data write channel region of the first semiconductor pattern; and a second data write transistor connected between a first terminal of the second driving transistor and the second data line, the second data write transistor including a second data write gate electrode overlapping the second semiconductor pattern and a second data write channel region of the second semiconductor pattern.

[0013] In one embodiment, the channel width of the 1-1 light-emitting control channel region of the first semiconductor pattern may be greater than the channel width of the 2-1 light-emitting control channel region of the second semiconductor pattern.

[0014] In one embodiment, the resistance of conductive regions adjacent to the 1-1 light-emitting control channel region of the first semiconductor pattern may be less than the resistance of conductive regions adjacent to the 2-1 light-emitting control channel region of the second semiconductor pattern.

[0015] In one embodiment, the channel width of the 1-2 light-emitting control channel region of the first semiconductor pattern may be greater than the channel width of the 2-2 light-emitting control channel region of the second semiconductor pattern.

[0016] In one embodiment, the resistance of the conductive regions adjacent to the 1-2 light-emitting control channel region of the first semiconductor pattern may be less than the resistance of the conductive regions adjacent to the 2-2 light-emitting control channel region of the second semiconductor pattern.

[0017] In one embodiment, the first light emitting control signal line and the second light emitting control signal line may be arranged on the same layer.

[0018] In one embodiment, each of the first and second light emitting control signal lines may overlap the first and second semiconductor patterns.

[0019] In one embodiment, the pixel may further include a third-first light-emitting control transistor including a third semiconductor pattern and a third light-emitting control gate electrode overlapping a third-first light-emitting control channel region of the third semiconductor pattern; and a third light-emitting element connected to the third-first light-emitting control transistor and emitting light of a third color. The third light-emitting control gate electrode may be connected to the second light-emitting control signal line.

[0020] In one embodiment, the third light-emitting control gate electrode may be formed integrally with the second light-emitting control gate electrode.

[0021] In one embodiment, the second semiconductor pattern and the third semiconductor pattern may have a planar shape that is symmetrical to each other.

[0022] In one embodiment, the light of the first color may be red light having a peak wavelength of about 610 nm to about 650 nm, the light of the second color may be green light having a peak wavelength of about 500 nm to about 540 nm, and the light of the third color may be blue light having a peak wavelength of about 440 nm to about 480 nm.

[0023] A method for driving a pixel according to embodiments provides a method for driving a pixel, the method comprising: a first-first light-emitting control transistor including a first semiconductor pattern and a first light-emitting control gate electrode overlapping a first-first light-emitting control channel region of the first semiconductor pattern; a second-first light-emitting control transistor including a second semiconductor pattern and a second light-emitting control gate electrode overlapping a second-first light-emitting control channel region of the second semiconductor pattern; a first light-emitting control signal line transmitting a first light-emitting control signal and connected to the first light-emitting control gate electrode; a second light-emitting control signal line transmitting a second light-emitting control signal and connected to the second light-emitting control gate electrode; a first light-emitting element connected to the first-first light-emitting control transistor and emitting light of a first color; and a second light-emitting element connected to the second-first light-emitting control transistor and emitting light of a second color. The driving method includes the step of outputting the second light emission control signal at a turn-on level to the second light emission control signal line during a first period, and outputting the first light emission control signal at a turn-on level to the first light emission control signal line during a second period within the first period, wherein the second period is shorter than the first period.

[0024] An electronic device according to embodiments includes a display panel, the display panel including a plurality of pixels, one of the plurality of pixels including: a first-first light-emitting control transistor including a first semiconductor pattern and a first light-emitting control gate electrode overlapping a first-first light-emitting control channel region of the first semiconductor pattern; a second-first light-emitting control transistor including a second semiconductor pattern and a second light-emitting control gate electrode overlapping a second-first light-emitting control channel region of the second semiconductor pattern; a first light-emitting control signal line transmitting a first light-emitting control signal and connected to the first light-emitting control gate electrode; a second light-emitting control signal line transmitting a second light-emitting control signal and connected to the second light-emitting control gate electrode; a first light-emitting element connected to the first-first light-emitting control transistor and emitting light of a first color; and a second light-emitting element connected to the second-first light-emitting control transistor and emitting light of a second color, wherein the first and second light-emitting control signal lines overlap the first and second semiconductor patterns, respectively.

[0025] In one embodiment, the electronic device may include a smartwatch, a mobile phone, a smart phone, a portable computer, a tablet computer, a watch phone, an automotive display, smart glasses, a portable multimedia player, a navigation device, an ultra-mobile personal computer, a head-mounted display device, a virtual reality device, a mixed reality device, or an augmented reality device.

[0026] According to embodiments of the present disclosure, a first light-emitting element of a first sub-pixel can emit light based on a first light-emitting control signal transmitted through a first light-emitting control signal line, and a second light-emitting element of a second sub-pixel can emit light based on a second light-emitting control signal transmitted through a second light-emitting control signal line separate from the first light-emitting control signal line.

[0027] Accordingly, the first light-emitting control signal suitable for the optimal driving characteristics of the first light-emitting element can be set, and the second light-emitting control signal suitable for the optimal driving characteristics of the second light-emitting element can be set separately from the first light-emitting control signal.

[0028] Therefore, the luminous efficiency of the pixel can be improved.

[0029] FIG. 1 is a block diagram illustrating a display device according to embodiments of the present disclosure.

[0030] FIG. 2 is a block diagram for explaining one of the sub-pixels included in the display device of FIG. 1.

[0031] FIG. 3 is a plan view for explaining a display panel constituting the display device of FIG. 1.

[0032] FIG. 4 is a cross-sectional view illustrating one embodiment of the display panel of FIG. 3.

[0033] FIG. 5 is a cross-sectional view illustrating another embodiment of the display panel of FIG. 3.

[0034] FIG. 6 is a circuit diagram for explaining one embodiment of one of the pixels included in the display panel of FIG. 3.

[0035] FIG. 7 is a cross-sectional view illustrating one embodiment of a pixel circuit layer included in the pixel of FIG. 6.

[0036] Figures 8 to 14 are plan views for explaining the pixel circuit layer of Figure 7.

[0037] Fig. 15 is a cross-sectional view taken along line XA-XA' of Fig. 14.

[0038] Fig. 16 is a cross-sectional view taken along line XB-XB' of Fig. 14.

[0039] FIG. 17 is a cross-sectional view illustrating another embodiment of a pixel circuit layer included in the pixel of FIG. 6.

[0040] Figures 18 to 24 are plan views for explaining the pixel circuit layer of Figure 17.

[0041] Figure 25 is a cross-sectional view taken along line XC-XC' of Figure 24.

[0042] Figure 26 is a cross-sectional view taken along the line XD-XD' of Figure 24.

[0043] FIG. 27 is a plan view illustrating one embodiment of one of the pixels included in the display panel of FIG. 3.

[0044] Figure 28 is a cross-sectional view taken along line I1-I1' of Figure 27.

[0045] Figure 29 is a cross-sectional view taken along line I2-I2' of Figure 27.

[0046] Figure 30 is a cross-sectional view taken along line I3-I3' of Figure 27.

[0047] Figure 31 is a cross-sectional view taken along line J1-J1' of Figure 27.

[0048] FIG. 32 is a timing diagram for explaining a driving method for driving pixels according to embodiments of the present disclosure.

[0049] Figure 33 is a drawing for explaining the effects according to the pixel and its driving method of the present disclosure.

[0050] Figure 34 is a block diagram illustrating a display system according to one embodiment.

[0051] Figures 35 to 38 are perspective views illustrating application examples of the display system of Figure 34.

[0052] Hereinafter, embodiments according to the present disclosure will be described in detail with reference to the attached drawings. It should be noted that in the following description, only the parts necessary for understanding the operation according to the present disclosure will be described, and the description of other parts will be omitted so as not to obscure the gist of the present disclosure. Furthermore, the present disclosure is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments described herein are provided to explain the technical concepts and scope of the present disclosure in such a detailed manner that those skilled in the art to which the present disclosure pertains can easily practice them.

[0053] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case where it is "directly connected" but also the case where it is "indirectly connected" with another element in between. The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the present disclosure. Throughout the specification, when a part is said to "comprise" a certain element, this does not exclude other elements unless specifically stated to the contrary, but rather means that it can include other elements. "At least one of X, Y, and Z," and "at least one selected from the array consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Herein, "and / or" includes any combination of one or more of the configurations.

[0054] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Accordingly, a "first component" may refer to a "second component" within the scope disclosed herein.

[0055] Spatially relative terms, such as "below," "above," and the like, may be used for descriptive purposes to describe one element or feature in relation to other elements or features as depicted in the drawings. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacturing, in addition to the orientation depicted in the drawings. For example, if a device depicted in the drawings is turned over, elements depicted as being positioned "below" other elements or features would instead be positioned "above" the other elements or features. Thus, in one embodiment, the term "below" can encompass both above and below. Furthermore, the device may be oriented in other orientations (e.g., rotated 90 degrees or in other directions), and the spatially relative terms used herein are to be interpreted accordingly.

[0056] Various embodiments are described with reference to drawings illustrating ideal embodiments. Accordingly, it is to be understood that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes depicted, but rather to encompass, for example, variations in shapes resulting from manufacturing processes. Likewise, the shapes depicted in the drawings may not depict the actual shapes of areas of the device, and the present embodiments are not limited thereto.

[0057] Additionally, any numerical range disclosed and / or cited in this disclosure is intended to include all subranges of the same numerical precision contained within the cited range. For example, a range of "1.0 to 10.0" is intended to include all subranges between (and including) the cited minimum value of 1.0 and the cited maximum value of 10.0, for example, 2.4 to 7.6, where the minimum value is greater than or equal to 1.0 and the maximum value is less than or equal to 10.0. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations contained therein, and any minimum numerical limitation recited herein is intended to include all upper numerical limitations contained therein. Accordingly, Applicants reserve the right to amend this disclosure, including claims, to explicitly recite all subranges contained within the ranges explicitly recited herein. Since all such ranges are inherently set forth in this disclosure, it is reasonable to amend to explicitly recite such subranges.

[0058] Those skilled in the art will understand, in light of the entire disclosure, that suitable features of each of the various embodiments of the present disclosure may be partially or wholly combined or combined with one another, and may be technically interconnected and operated in various suitable ways, and that each embodiment may be implemented independently of one another or may be implemented in connection with one another in any suitable manner, unless otherwise stated or implied.

[0059] FIG. 1 is a block diagram illustrating a display device according to embodiments of the present disclosure.

[0060] Referring to FIG. 1, the display device (DD) may include a display panel (DP), a gate driver (120), a data driver (130), a voltage generator (140), and a controller (150).

[0061] The display panel (DP) may include sub-pixels (SP). The sub-pixels (SP) may be connected to a gate driver (120) via first to m-th gate lines (GL1 to GLm). The sub-pixels (SP) may be connected to a data driver (130) via first to n-th data lines (DL1 to DLn).

[0062] Sub-pixels (SP) can generate light of two or more colors. For example, each sub-pixel (SP) can generate light of red, green, blue, cyan, magenta, yellow, etc.

[0063] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). For example, the pixel (PXL) can include three sub-pixels as illustrated in FIG. 1. The pixel (PXL) can emit light of various colors and various luminances depending on the combination of light emitted from the sub-pixels included in the pixel (PXL).

[0064] The gate driver (120) may be connected to the sub-pixels (SP) arranged in the row direction through the first to m-th gate lines (GL1 to GLm). The gate driver (120) may output gate signals to the first to m-th gate lines (GL1 to GLm) in response to a gate control signal (GCS). In embodiments, the gate control signal (GCS) may include a start signal indicating the start of each frame, and / or a horizontal synchronization signal.

[0065] The gate driver (120) may be disposed on one side of the display panel (DP). However, the present disclosure is not limited thereto. For example, the gate driver (120) may be divided into two or more drivers that are physically and / or logically separated, and such drivers may be disposed on one side of the display panel (DP) and the other side of the display panel (DP) opposite to the one side. In this way, the gate driver (120) may be disposed around the display panel (DP) in various forms according to embodiments.

[0066] The data driver (130) may be connected to sub-pixels (SP) arranged in the column direction through the first to nth data lines (DL1 to DLn). The data driver (130) may receive image data (IMGD) and a data control signal (DCS) from the controller (150). The data driver (130) may operate in response to the data control signal (DCS). In embodiments, the data control signal (DCS) may include a source start signal, a source shift clock, a source output enable signal, and the like.

[0067] The data driver (130) can receive voltages from the voltage generator (140). The data driver (130) can apply data signals having grayscale voltages corresponding to the image data (IMGD) to the first to n-th data lines (DL1 to DLn) using the received voltages. When a gate signal is applied to each of the first to m-th gate lines (GL1 to GLm), the data signals corresponding to the image data (IMGD) can be applied to the data lines (DL1 to DLn). Accordingly, the sub-pixels (SP) can generate light corresponding to the data signals, and the display panel (DP) can display an image.

[0068] In embodiments, the gate driver (120) and the data driver (130) may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0069] The voltage generator (140) can operate in response to a voltage control signal (VCS) from the controller (150). The voltage generator (140) can be configured to generate a plurality of voltages and provide the generated voltages to components of the display device (DD), such as the gate driver (120), the data driver (130), and the controller (150). The voltage generator (140) can receive an input voltage from the outside of the display device (DD) and generate a plurality of voltages by regulating the received voltage.

[0070] A voltage generator (140) can generate a first power voltage and a second power voltage. The generated first and second power voltages can be provided to the sub-pixels (SP) through power lines (PL). In other embodiments, at least one of the first and second power voltages can be provided from outside the display device (DD).

[0071] In addition, the voltage generator (140) can provide various voltages and / or signals. For example, the voltage generator (140) can provide one or more initialization voltages applied to the sub-pixels (SP). For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels (SP), a reference voltage (e.g., a predetermined reference voltage) can be applied to the first to n-th data lines (DL1 to DLn), and the voltage generator (140) can generate the reference voltage and transmit it to the data driver (130). For example, during a display operation for displaying an image on the display panel (DP), common pixel control signals can be applied to the sub-pixels (SP), and the voltage generator (140) can generate the pixel control signals. In embodiments, the voltage generator (140) can provide pixel control signals to the sub-pixels (SP) through the pixel control lines (PXCL). Although FIG. 1 illustrates that the pixel control lines (PXCL) are connected between the voltage generator (140) and the display panel (DP), the present disclosure is not limited thereto. For example, the pixel control lines (PXCL) may be connected between the gate driver (120) and the display panel (DP). In this case, pixel control signals may be transmitted from the voltage generator (140) to the pixel control lines (PXCL) through the gate driver (120).

[0072] The controller (150) can control all operations of the display device (DD). The controller (150) can receive input image data (IMG) and a corresponding control signal (CTRL) from the outside. In response to the control signal (CTRL), the controller (150) can provide a gate control signal (GCS), a data control signal (DCS), and a voltage control signal (VCS).

[0073] The controller (150) can convert input image data (IMG) to be suitable for a display device (DD) or a display panel (DP) and output image data (IMGD). In embodiments, the controller (150) can align the input image data (IMG) to be suitable for sub-pixels (SP) in a row unit and output image data (IMGD).

[0074] Two or more components of the data driver (130), the voltage generator (140), and the controller (150) may be mounted on a single integrated circuit. As illustrated in FIG. 1, the data driver (130), the voltage generator (140), and the controller (150) may be included in a driver integrated circuit (DIC). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver (130), the voltage generator (140), and the controller (150) may be provided as a separate component from the driver integrated circuit (DIC).

[0075] Fig. 2 is a block diagram for explaining one of the sub-pixels included in the display device of Fig. 1. In Fig. 2, a sub-pixel (SPij) arranged in the ith row (i is an integer greater than or equal to 1 and less than or equal to m) and the jth column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels (SP) of Fig. 1 is illustrated as an example.

[0076] Referring to FIG. 2, a sub-pixel (SPij) may include a sub-pixel circuit (SPC) and a light-emitting element (LD).

[0077] A light emitting element (LD) may be connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first power supply voltage node (VDDN) may be connected to one of the power supply lines (PL) of FIG. 1 and may receive a first power supply voltage. The second power supply voltage node (VSSN) may be connected to another of the power supply lines (PL) of FIG. 1 and may receive a second power supply voltage. The first power supply voltage may have a higher voltage level than the second power supply voltage.

[0078] A light emitting element (LD) may be connected between an anode electrode (AE) and a cathode electrode (CE). The anode electrode (AE) may be connected to a first power voltage node (VDDN) through a sub-pixel circuit (SPC). For example, the anode electrode (AE) may be connected to the first power voltage node (VDDN) through one or more transistors included in the sub-pixel circuit (SPC). The cathode electrode (CE) may be connected to a second power voltage node (VSSN). The light emitting element (LD) may be configured to emit light according to a current flowing from the anode electrode (AE) to the cathode electrode (CE).

[0079] The sub-pixel circuit (SPC) may be connected to an i-th gate line (GLi) among the first to m-th gate lines (GL1 to GLm) of FIG. 1 and a j-th data line (DLj) among the first to n-th data lines (DL1 to DLn) of FIG. 1. In response to a gate signal received through the i-th gate line (GLi), the sub-pixel circuit (SPC) may control the light-emitting element (LD) to emit light according to a data signal received through the j-th data line (DLj). In embodiments, the sub-pixel circuit (SPC) may be further connected to the pixel control lines (PXCL) of FIG. 1. In this case, the sub-pixel circuit (SPC) may further control the light-emitting element (LD) in response to pixel control signals received through the pixel control lines (PXCL).

[0080] For these operations, a sub-pixel circuit (SPC) may include circuit elements, such as transistors and one or more capacitors.

[0081] The transistors of the sub-pixel circuit (SPC) may include P-type transistors and / or N-type transistors. In embodiments, the transistors of the sub-pixel circuit (SPC) may include MOSFETs (Metal Oxide Silicon Field Effect Transistors). In embodiments, the transistors of the sub-pixel circuit (SPC) may include an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0082] FIG. 3 is a plan view for explaining a display panel constituting the display device of FIG. 1.

[0083] Referring to FIG. 3, a display panel (DP) may include a display area (DA) and a non-display area (NDA). The display panel (DP) may display an image through the display area (DA). The non-display area (NDA) may be positioned along the edge or periphery of the display area (DA).

[0084] A display panel (DP) may include sub-pixels (SP) in a display area (DA). The sub-pixels (SP) may be arranged along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). For example, the sub-pixels (SP) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). As another example, the sub-pixels (SP) may be arranged in a zigzag form along the first direction (DR1) and the second direction (DR2). For example, the sub-pixels (SP) may be arranged in a matrix form along rows and columns along the first direction (DR1) and the second direction (DR2). The arrangement of the sub-pixels (SP) may vary depending on embodiments. The first direction (DR1) may be a row direction, and the second direction (DR2) may be a column direction.

[0085] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). In FIG. 3, the pixel (PXL) is illustrated as including three sub-pixels (SP1, SP2, SP3), but the present disclosure is not limited thereto. For example, the pixel (PXL) may include two sub-pixels. Hereinafter, for the sake of clarity and concise description, it is assumed that the pixel (PXL) includes first to third sub-pixels (SP1, SP2, SP3).

[0086] Each of the first to third sub-pixels (SP1, SP2, SP3) can generate light of one of various colors such as red, green, blue, cyan, magenta, yellow, etc. Hereinafter, for the sake of clarity and concise description, it is assumed that the first sub-pixel (SP1) is configured to generate red color light, the second sub-pixel (SP2) is configured to generate green color light, and the third sub-pixel (SP3) is configured to generate blue color light. Here, the red color light may be light having a peak wavelength in a range from about 610 nm to about 650 nm, the green color light may be light having a peak wavelength in a range from about 500 nm to about 540 nm, and the blue color light may be light having a peak wavelength in a range from about 440 nm to about 480 nm. Hereinafter, the red color may be referred to as the first color, the green color may be referred to as the second color, and the blue color may be referred to as the third color.

[0087] Each of the first to third sub-pixels (SP1, SP2, SP3) may include at least one light-emitting element (LD, see FIG. 2) configured to generate light. In embodiments, the light-emitting elements of the first to third sub-pixels (SP1, SP2, PS3) may generate light of different colors. For example, the first light-emitting element of the first sub-pixel (SP1) may be configured to generate light of a first color, the second light-emitting element of the second sub-pixel (SP2) may be configured to generate light of a second color, and the third light-emitting element of the third sub-pixel (SP3) may be configured to generate light of a third color.

[0088] As a display panel (DP), a self-luminous display panel such as a light-emitting diode display panel (LED display panel) that uses micro-scale or nano-scale light-emitting diodes as light-emitting elements can be used.

[0089] Components for controlling sub-pixels (SP) may be arranged in the non-display area (NDA). Wires connected to the sub-pixels (SP), for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1, may be arranged in the non-display area (NDA).

[0090] At least one of the gate driver (120), the data driver (130), the voltage generator (140), and the controller (150) of FIG. 1 may be disposed in a non-display area (NDA) of the display panel (DP). In embodiments, the gate driver (120) may be disposed in the non-display area (NDA). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be implemented as a driver integrated circuit (DIC) of FIG. 1 that is separate from the display panel (DP), and the driver integrated circuit (DIC) may be connected to wires disposed in the non-display area (NDA). In other embodiments, the gate driver (120) may be implemented as a single integrated circuit that is separate from the display panel (DP) together with the data driver (130), the voltage generator (140), and the controller (150).

[0091] In embodiments, the display area (DA) may have various shapes. The display area (DA) may have a closed-loop shape including straight and / or curved edges. For example, the display area (DA) may have shapes such as a polygon, a circle, a semicircle, or an ellipse.

[0092] In some embodiments, the display panel (DP) may have a flat display surface. In other embodiments, the display panel (DP) may have an at least partially rounded display surface.

[0093] In embodiments, the display panel (DP) may be bendable, foldable, or rollable. In such cases, the display panel (DP) and / or the substrate of the display panel (DP) may include materials having flexible properties.

[0094] FIG. 4 is a cross-sectional view illustrating one embodiment of the display panel of FIG. 3.

[0095] Referring to FIG. 4, the display panel (DP) may include a substrate (SUB), and a pixel circuit layer (PCL), a display element layer (DPL), and a light functional layer (LFL) that are sequentially laminated in a third direction (DR3) intersecting the first and second directions (DR1, DR2) on the substrate (SUB).

[0096] The substrate (SUB) may be made of an insulating material such as glass or resin. For example, the substrate (SUB) may include a glass substrate. As another example, the substrate (SUB) may include a polyimide (PI) substrate. As another example, the substrate (SUB) may include a silicon wafer substrate formed using a semiconductor process.

[0097] In embodiments, the substrate (SUB) may be made of a flexible material that is bendable or foldable, and may have a single-layer structure or a multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the present disclosure is not limited thereto.

[0098] A pixel circuit layer (PCL) may be disposed on a substrate (SUB). The pixel circuit layer (PCL) may include insulating layers and semiconductor patterns and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may function as circuit elements, wirings, etc.

[0099] The circuit elements of the pixel circuit layer (PCL) may include a sub-pixel circuit (SPC, see FIG. 2) of each of the sub-pixels (SP) of FIG. 3. In other words, the circuit elements of the pixel circuit layer (PCL) may be provided as transistors and one or more capacitors of the sub-pixel circuit (SPC).

[0100] The wiring of the pixel circuit layer (PCL) may include wiring connected to sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may include various signal lines and / or voltage lines necessary to drive the display element layer (DPL).

[0101] A display element layer (DPL) may be disposed on a pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements of sub-pixels (SP).

[0102] A light-functional layer (LFL) may be disposed on the display element layer (DPL). The light-functional layer (LFL) may include light-scattering patterns having scattering particles and / or a color filter layer including color filters. The color filter may selectively transmit light of a specific wavelength (or, a specific color). In embodiments, the light-functional layer (LFL) may be omitted.

[0103] A window may be provided on the light functional layer (LFL) to protect the exposed surface (or upper surface) of the display panel (DP). The window may protect the display panel (DP) from external impact. The window may be bonded to the light functional layer (LFL) via an optically transparent adhesive (or bonding) member. The window may have a multilayer structure including a glass substrate, a plastic film, and / or a plastic substrate. This multilayer structure may be formed through a continuous process or an bonding process using an adhesive layer. All or a portion of the window may be flexible.

[0104] FIG. 5 is a cross-sectional view illustrating another embodiment of the display panel of FIG. 3.

[0105] Referring to FIG. 5, the display panel (DP') may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), an input sensing layer (ISL), and a light function layer (LFL). The substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) may be described substantially the same as described with reference to FIG. 4. Therefore, redundant descriptions are omitted.

[0106] The input sensing layer (ISL) can detect a user's input on the upper surface (or display surface) of the display panel (DP'). The input sensing layer (ISL) may include configurations suitable for detecting an external object, such as a user's hand or pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0107] FIG. 6 is a circuit diagram for explaining one embodiment of one of the pixels included in the display panel of FIG. 3.

[0108] Referring to FIG. 6, a pixel (PXL) may include first to third sub-pixels (SP1, SP2, and SP3). A first sub-pixel (SP1) may include a first sub-pixel circuit (SPC1) and a first light-emitting element (LD1) connected to the first sub-pixel circuit (SPC1). A second sub-pixel (SP2) may include a second sub-pixel circuit (SPC2) and a second light-emitting element (LD2) connected to the second sub-pixel circuit (SPC2). A third sub-pixel (SP3) may include a third sub-pixel circuit (SPC3) and a third light-emitting element (LD3) connected to the third sub-pixel circuit (SPC3).

[0109] A pixel (PXL) may include signal lines connected to first to third sub-pixel circuits (SPC1, SPC2, SPC3). The signal lines may include first to third data lines (DL1, DL2, DL3), first to fourth gate lines (GWL, GCL, GIL, GBL), first and second emission control signal lines (EML1, EML2), a bias control line (VBL), an initialization line (VINTL), an anode initialization line (VAINTL), and a first power line (ELVDDL). Here, the first power line (ELVDDL) may be connected to a first power voltage node (VDDN, see FIG. 2) or a power line (PL, see FIG. 1) connected thereto, and may receive a first power voltage (ELVDD).

[0110] Below, a first sub-pixel (SP1) including a first sub-pixel circuit (SPC1) and a first light-emitting element (LD1) connected thereto will be described.

[0111] The first sub-pixel circuit (SPC1) may include first to eighth transistors (T1a, T2a, T3a, T4a, T5a, T6a, T7a, T8a), a first storage capacitor (CSTa), and a first boosting capacitor (CBSTa).

[0112] The first transistor (T1a) may be a driving transistor, and the second to eighth transistors (T2a, T3a, T4a, T5a, T6a, T7a, T8a) may be switching transistors. Depending on the type of transistor (P type or N type) and / or operating conditions, the first terminal of each of the first to eighth transistors (T1a, T2a, T3a, T4a, T5a, T6a, T7a, T8a) may be a source terminal or a drain terminal, and the second terminal may be a terminal different from the first terminal. For example, when the first terminal is a source terminal, the second terminal may be a drain terminal. Hereinafter, the source terminal and the drain terminal may be referred to interchangeably as a source electrode and a drain electrode.

[0113] In one embodiment, the third and fourth transistors (T3a, T4a) may be N-type transistors, and the first to second and fifth to eighth transistors (T1a, T2a, T5a, T6a, T7a, T8a) may be P-type transistors. However, the present disclosure is not limited thereto. Those skilled in the art will be able to easily design a circuit composed of various combinations of P-type transistors and N-type transistors by changing the polarity of the voltage applied to the gate electrode.

[0114] In one embodiment, the P-type transistor may be a polysilicon semiconductor transistor. The channel of the polysilicon semiconductor transistor may include a polysilicon semiconductor. The polysilicon semiconductor transistor may be, for example, a low-temperature polysilicon (LTPS) thin-film transistor. The polysilicon semiconductor transistor has high electron mobility and thus fast driving characteristics.

[0115] In one embodiment, the N-type transistor may be an oxide semiconductor transistor. The channel of the oxide semiconductor transistor may include an oxide semiconductor. The oxide semiconductor transistor may be, for example, a low-temperature polycrystalline oxide (LTPO) thin film transistor. The oxide semiconductor transistor has lower charge mobility than a polysilicon semiconductor transistor. Therefore, the amount of leakage current generated in the turn-off state of the oxide semiconductor transistor may be smaller than that of the polysilicon semiconductor transistor.

[0116] A first transistor (T1a) may be connected between a first power line (ELVDDL) and a first anode electrode (AE1). The first transistor (T1a) may be connected to the first power line (ELVDDL) via a fifth transistor (T5a) and to the first anode electrode (AE1) via a sixth transistor (T6a). The first transistor (T1a) may include a gate electrode connected to a second node (N2a), a first terminal connected to the first node (N1a), and a second terminal connected to a third node (N3a). The first transistor (T1a) may receive a first data signal (DATA1) according to a switching operation of the second transistor (T2a) and supply a first driving current to the first anode electrode (AE1).

[0117] In one embodiment, the first transistor (T1a) may be referred to as a first driving transistor, and the gate electrode of the first transistor (T1a) may be referred to as a first driving gate electrode.

[0118] The second transistor (T2a) may be connected between the first data line (DL1) and the first node (N1a). The second transistor (T2a) may include a gate electrode connected to the first gate line (GWL), a first terminal connected to the first data line (DL1), and a second terminal connected to the first node (N1a). The second transistor (T2a) may be turned on in response to a first gate signal (GW) received through the first gate line (GWL), and may perform a switching operation to transmit the first data signal (DATA1) received through the first data line (DL1) to the first node (N1a).

[0119] In one embodiment, the second transistor (T2a) may be referred to as a first data write transistor.

[0120] A third transistor (T3a) may be connected between a second node (N2a) and a third node (N3a). The third transistor (T3a) may include a gate electrode connected to a second gate line (GCL), a first terminal connected to the second node (N2a), and a second terminal connected to the third node (N3a). The third transistor (T3a) may be turned on in response to a second gate signal (GC) received through the second gate line (GCL) to diode-connect the first transistor (T1a), thereby compensating for a threshold voltage of the first transistor (T1a).

[0121] In one embodiment, the third transistor (T3a) may be referred to as a first diode transistor.

[0122] The fourth transistor (T4a) may be connected between the second node (N2a) and the initialization line (VINTL). The fourth transistor (T4a) may include a gate electrode connected to the third gate line (GIL), a first terminal connected to the second node (N2a), and a second terminal connected to the initialization line (VINTL). The fourth transistor (T4a) may be turned on according to a third gate signal (GI) received through the third gate line (GIL) to transmit the initialization voltage (VINT) to the gate electrode of the first transistor (T1a), thereby initializing the gate electrode of the first transistor (T1a).

[0123] In one embodiment, the fourth transistor (T4a) may be referred to as a first initialization transistor.

[0124] The fifth transistor (T5a) may be connected between the first power line (ELVDDL) and the first node (N1a). The fifth transistor (T5a) may include a gate electrode connected to the first light emission control signal line (EML1), a first terminal connected to the first power line (ELVDDL), and a second terminal connected to the first node (N1a).

[0125] The sixth transistor (T6a) may be connected between the third node (N3a) and the first anode electrode (AE1). The sixth transistor (T6a) may include a gate electrode connected to the first light emission control signal line (EML1), a first terminal connected to the third node (N3a), and a second terminal connected to the first anode electrode (AE1).

[0126] The fifth and sixth transistors (T5a, T6a) are simultaneously turned on in response to the first light emission control signal (EM1) received through the first light emission control signal line (EML1), and accordingly, a first driving current can be provided to the first anode electrode (AE1).

[0127] In one embodiment, the sixth transistor (T6a) may be referred to as a 1-1 light-emitting control transistor, and the fifth transistor (T5a) may be referred to as a 1-2 light-emitting control transistor.

[0128] The seventh transistor (T7a) may be connected between the first anode electrode (AE1) and the anode initialization line (VAINTL). The seventh transistor (T7a) may include a gate electrode connected to the fourth gate line (GBL), a first terminal connected to the anode initialization line (VAINTL), and a second terminal connected to the first anode electrode (AE1). The seventh transistor (T7a) may be turned on according to the fourth gate signal (GB) received through the fourth gate line (GBL) to transmit the anode initialization voltage (VAINT) to the first anode electrode (AE1), thereby initializing the first anode electrode (AE1).

[0129] In one embodiment, the seventh transistor (T7a) may be referred to as a first anode initialization transistor.

[0130] The eighth transistor (T8a) may be connected between the first node (N1a) and the bias control line (VBL). The eighth transistor (T8a) may include a gate electrode connected to the fourth gate line (GBL), a first terminal connected to the bias control line (VBL), and a second terminal connected to the first node (N1a). The eighth transistor (T8a) may be turned on according to the fourth gate signal (GB) received through the fourth gate line (GBL) to apply a bias voltage (VB) to the first terminal of the first transistor (T1a), thereby presetting a voltage suitable for a subsequent operation of the first transistor (T1a) to the first terminal of the first transistor (T1a).

[0131] In one embodiment, the eighth transistor (T8a) may be referred to as a first bias transistor.

[0132] The first storage capacitor (CSTa) may include a first electrode and a second electrode. The first electrode of the first storage capacitor (CSTa) may be connected to a gate electrode (e.g., a second node (N2a)) of the first transistor (T1a), and the second electrode may be connected to a first power line (ELVDDL). The first storage capacitor (CSTa) may store and maintain a voltage corresponding to a voltage difference between the first power line (ELVDDL) and the gate electrode of the first transistor (T1a), thereby maintaining a voltage applied to the gate electrode of the first transistor (T1a).

[0133] The first boosting capacitor (CBSTa) may include a first electrode and a second electrode. The first electrode of the first boosting capacitor (CBSTa) may be connected to the first gate line (GWL), and the second electrode may be connected to the gate electrode of the first transistor (T1a). The first boosting capacitor (CBSTa) may play a role in improving black visibility by compensating for a voltage applied to the gate electrode of the first transistor (T1a) when the first gate signal (GW) transitions from a turn-on level to a turn-off level.

[0134] The first light-emitting element (LD1) may be connected between the first anode electrode (AE1) and the cathode electrode (CE). The first light-emitting element (LD1) may include a micro-scale or nano-scale light-emitting diode. In one embodiment, the first light-emitting element (LD1) may be configured to generate light of a first color.

[0135] The cathode electrode (CE) can be connected to a second power voltage node (VSSN, see FIG. 2) or a power line (PL, see FIG. 1) connected thereto, and can receive a second power voltage (ELVSS).

[0136] Below, a second sub-pixel (SP2) including a second sub-pixel circuit (SPC2) and a second light-emitting element (LD2) connected thereto will be described.

[0137] In explaining the second sub-pixel circuit (SPC2) included in the second sub-pixel (SP2), the differences compared to the first sub-pixel circuit (SPC1) will be explained, and any omitted parts will be replaced with the previous content.

[0138] The second sub-pixel circuit (SPC2) may include first to eighth transistors (T1b, T2b, T3b, T4b, T5b, T6b, T7b, T8b), a second storage capacitor (CSTb), and a second boosting capacitor (CBSTb).

[0139] The first transistor (T1b) may be connected to the first power line (ELVDDL) via the fifth transistor (T5b) and to the second anode electrode (AE2) via the sixth transistor (T6b). The first transistor (T1b) may include a gate electrode connected to the second node (N2b), a first terminal connected to the first node (N1b), and a second terminal connected to the third node (N3b). The first transistor (T1b) may receive a second data signal (DATA2) according to a switching operation of the second transistor (T2b) and supply a second driving current to the second anode electrode (AE2).

[0140] In one embodiment, the first transistor (T1b) may be referred to as a second driving transistor, and the gate electrode of the first transistor (T1b) may be referred to as a second driving gate electrode.

[0141] The second transistor (T2b) may be connected between the second data line (DL2) and the first node (N1b). The second transistor (T2b) may include a gate electrode connected to the first gate line (GWL), a first terminal connected to the second data line (DL2), and a second terminal connected to the first node (N1b). The second transistor (T2b) may be turned on in response to a first gate signal (GW) received through the first gate line (GWL) and may perform a switching operation to transmit a second data signal (DATA2) received through the second data line (DL2) to the first node (N1b).

[0142] In one embodiment, the second transistor (T2b) may be referred to as a second data write transistor.

[0143] A third transistor (T3b) may be connected between the second node (N2b) and the third node (N3b). The third transistor (T3b) may include a gate electrode connected to the second gate line (GCL), a first terminal connected to the second node (N2b), and a second terminal connected to the third node (N3b).

[0144] In one embodiment, the third transistor (T3b) may be referred to as a second diode transistor.

[0145] The fourth transistor (T4b) may be connected between the second node (N2b) and the initialization line (VINTL). The fourth transistor (T4b) may include a gate electrode connected to the third gate line (GIL), a first terminal connected to the second node (N2b), and a second terminal connected to the initialization line (VINTL).

[0146] In one embodiment, the fourth transistor (T4b) may be referred to as a second initialization transistor.

[0147] The fifth transistor (T5b) may be connected between the first power line (ELVDDL) and the first node (N1b). The fifth transistor (T5b) may include a gate electrode connected to the second light emission control signal line (EML2), a first terminal connected to the first power line (ELVDDL), and a second terminal connected to the first node (N1b).

[0148] The sixth transistor (T6b) may be connected between the third node (N3b) and the second anode electrode (AE2). The sixth transistor (T6b) may include a gate electrode connected to the second light emission control signal line (EML2), a first terminal connected to the third node (N3b), and a second terminal connected to the second anode electrode (AE2).

[0149] The fifth and sixth transistors (T5b, T6b) are turned on simultaneously in response to a second light emission control signal (EM2) received through a second light emission control signal line (EML2), and accordingly, a second driving current can be provided to the second anode electrode (AE2).

[0150] In one embodiment, the sixth transistor (T6b) may be referred to as a 2-1 light-emitting control transistor, and the fifth transistor (T5b) may be referred to as a 2-2 light-emitting control transistor.

[0151] The seventh transistor (T7b) may be connected between the second anode electrode (AE2) and the anode initialization line (VAINTL). The seventh transistor (T7b) may include a gate electrode connected to the fourth gate line (GBL), a first terminal connected to the anode initialization line (VAINTL), and a second terminal connected to the second anode electrode (AE2).

[0152] In one embodiment, the seventh transistor (T7b) may be referred to as a second anode initialization transistor.

[0153] The eighth transistor (T8b) may be connected between the first node (N1b) and the bias control line (VBL). The eighth transistor (T8b) may include a gate electrode connected to the fourth gate line (GBL), a first terminal connected to the bias control line (VBL), and a second terminal connected to the first node (N1b).

[0154] In one embodiment, the eighth transistor (T8b) may be referred to as a second bias transistor.

[0155] The second storage capacitor (CSTb) may include a first electrode and a second electrode. The first electrode of the second storage capacitor (CSTb) may be connected to the gate electrode of the first transistor (T1b), and the second electrode may be connected to the first power line (ELVDDL).

[0156] The second boosting capacitor (CBSTb) may include a first electrode and a second electrode. The first electrode of the second boosting capacitor (CBSTb) may be connected to the first gate line (GWL), and the second electrode may be connected to the gate electrode of the first transistor (T1b).

[0157] The second light-emitting element (LD2) may be connected between the second anode electrode (AE2) and the cathode electrode (CE). The second light-emitting element (LD2) may include a micro-scale or nano-scale light-emitting diode. In one embodiment, the second light-emitting element (LD2) may be configured to generate light of a second color.

[0158] Below, a third sub-pixel (SP3) including a third sub-pixel circuit (SPC3) and a third light-emitting element (LD3) connected thereto will be described.

[0159] In explaining the third sub-pixel circuit (SPC3) included in the third sub-pixel (SP3), the explanation will be focused on the differences compared to the first sub-pixel circuit (SPC1), and the omitted parts will be replaced with the previous content.

[0160] The third sub-pixel circuit (SPC3) may include first to eighth transistors (T1c, T2c, T3c, T4c, T5c, T6c, T7c, T8c), a first storage capacitor (CSTc), and a boosting capacitor (CBSTc).

[0161] The first transistor (T1c) may be connected to the first power line (ELVDDL) via the fifth transistor (T5c) and to the third anode electrode (AE3) via the sixth transistor (T6c). The first transistor (T1c) may include a gate electrode connected to the second node (N2c), a first terminal connected to the first node (N1c), and a second terminal connected to the third node (N3c). The first transistor (T1c) may receive a third data signal (DATA3) according to a switching operation of the second transistor (T2c) and supply a third driving current to the third anode electrode (AE3).

[0162] In one embodiment, the first transistor (T1c) may be referred to as a third driving transistor, and the gate electrode of the first transistor (T1c) may be referred to as a third driving gate electrode.

[0163] The second transistor (T2c) may be connected between the third data line (DL3) and the first node (N1c). The second transistor (T2c) may include a gate electrode connected to the first gate line (GWL), a first terminal connected to the third data line (DL3), and a second terminal connected to the first node (N1c). The second transistor (T2c) may be turned on in response to a first gate signal (GW) received through the first gate line (GWL) and may perform a switching operation to transmit a third data signal (DATA3) received through the third data line (DL3) to the first node (N1c).

[0164] In one embodiment, the second transistor (T2c) may be referred to as a third data write transistor.

[0165] A third transistor (T3c) may be connected between a second node (N2c) and a third node (N3c). The third transistor (T3c) may include a gate electrode connected to a second gate line (GCL), a first terminal connected to the second node (N2c), and a second terminal connected to the third node (N3c).

[0166] In one embodiment, the third transistor (T3c) may be referred to as a third diode transistor.

[0167] A fourth transistor (T4c) may be connected between a second node (N2c) and an initialization line (VINTL). The fourth transistor (T4c) may include a gate electrode connected to a third gate line (GIL), a first terminal connected to the second node (N2c), and a second terminal connected to the initialization line (VINTL).

[0168] In one embodiment, the fourth transistor (T4c) may be referred to as a third initialization transistor.

[0169] The fifth transistor (T5c) may be connected between the first power line (ELVDDL) and the first node (N1c). The fifth transistor (T5c) may include a gate electrode connected to the second light emission control signal line (EML2), a first terminal connected to the first power line (ELVDDL), and a second terminal connected to the first node (N1c).

[0170] The sixth transistor (T6c) may be connected between the third node (N3c) and the third anode electrode (AE3). The sixth transistor (T6c) may include a gate electrode connected to the second light emission control signal line (EML2), a first terminal connected to the third node (N3c), and a second terminal connected to the third anode electrode (AE3).

[0171] The fifth and sixth transistors (T5c, T6c) are simultaneously turned on in response to the second light emission control signal (EM2) received through the second light emission control signal line (EML2), and accordingly, a third driving current can be provided to the third anode electrode (AE3).

[0172] In one embodiment, the sixth transistor (T6c) may be referred to as the 3-1 light-emitting control transistor, and the fifth transistor (T5c) may be referred to as the 3-2 light-emitting control transistor.

[0173] The seventh transistor (T7c) may be connected between the third anode electrode (AE3) and the anode initialization line (VAINTL). The seventh transistor (T7c) may include a gate electrode connected to the fourth gate line (GBL), a first terminal connected to the anode initialization line (VAINTL), and a second terminal connected to the third anode electrode (AE3).

[0174] In one embodiment, the seventh transistor (T7c) may be referred to as a third anode initialization transistor.

[0175] The eighth transistor (T8c) may be connected between the first node (N1c) and the bias control line (VBL). The eighth transistor (T8c) may include a gate electrode connected to the fourth gate line (GBL), a first terminal connected to the bias control line (VBL), and a second terminal connected to the first node (N1c).

[0176] In one embodiment, the eighth transistor (T8c) may be referred to as a third bias transistor.

[0177] The third storage capacitor (CSTc) may include a first electrode and a second electrode. The first electrode of the third storage capacitor (CSTc) may be connected to the gate electrode of the first transistor (T1c), and the second electrode may be connected to the first power line (ELVDDL).

[0178] The third boosting capacitor (CBSTc) may include a first electrode and a second electrode. The first electrode of the third boosting capacitor (CBSTc) may be connected to the first gate line (GWL), and the second electrode may be connected to the gate electrode of the first transistor (T1c).

[0179] The third light-emitting element (LD3) may be connected between the third anode electrode (AE3) and the cathode electrode (CE). The third light-emitting element (LD3) may include a micro-scale or nano-scale light-emitting diode. In one embodiment, the third light-emitting element (LD3) may be configured to generate light of a third color.

[0180] FIG. 7 is a cross-sectional view illustrating one embodiment of a pixel circuit layer included in the pixel of FIG. 6.

[0181] Referring to FIG. 7, a pixel circuit layer (PCL) may be disposed on a substrate (SUB). The pixel circuit layer (PCL) may include a semiconductor pattern layer (ACT), a first insulating layer (INL1), a first gate conductive layer (GAT1), a second insulating layer (INL2), a second gate conductive layer (GAT2), a third insulating layer (INL3), an oxide semiconductor pattern layer (OACT), a fourth insulating layer (INL4), a third gate conductive layer (GAT3), a fifth insulating layer (INL5), a first SD conductive layer (SD1), a first via insulating layer (VIA1), a second SD conductive layer (SD2), and a second via insulating layer (VIA2) that are sequentially stacked in a third direction (DR3).

[0182] The first to third gate conductive layers (GAT1, GAT2, GAT3) and the first and second SD conductive layers (SD1, SD2) may include a conductive material. For example, the first to third gate conductive layers (GAT1, GAT2, GAT3) and the first and second SD conductive layers (SD1, SD2) may each independently have a single-layer structure or a multi-layer structure including copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and / or an alloy thereof.

[0183] The semiconductor pattern layer (ACT) may include a silicon semiconductor. For example, the semiconductor pattern layer (ACT) may include a polysilicon semiconductor (e.g., LTSP). Alternatively, the oxide semiconductor pattern layer (OACT) may include an oxide semiconductor (e.g., LTPO).

[0184] The first to fifth insulating layers (INL1, INL2, INL3, INL4, INL5) may be provided to electrically isolate the semiconductor pattern layer (ACT), the oxide semiconductor pattern layer (OACT), the first to third gate conductive layers (GAT1, GAT2, GAT3), and the first SD conductive layer (SD1). In this case, two or more components of the semiconductor pattern layer (ACT), the oxide semiconductor pattern layer (OACT), the first to third gate conductive layers (GAT1, GAT2, GAT3), and the first SD conductive layer (SD1) may be connected to each other through contact holes formed in the first to fifth insulating layers (INL1, INL2, INL3, INL4, INL5), as needed.

[0185] The first to fifth insulating layers (INL1, INL2, INL3, INL4, INL5) may include an inorganic insulating material. For example, the first to fifth insulating layers (INL1, INL2, INL3, INL4, INL5) may each independently include a metal oxide such as silicon oxide, silicon nitride, silicon oxynitride, and / or aluminum oxide. The first to fifth insulating layers (INL1, INL2, INL3, INL4, INL5) may each independently have a single-layer structure or a multi-layer structure.

[0186] First and second via insulation layers (VIA1, VIA2) may be provided to electrically isolate the first and second SD conductive layers (SD1, SD2). In this case, the first and second SD conductive layers (SD1, SD2) may be connected to each other through contact holes formed in the first and second via insulation layers (VIA1, VIA2), as needed.

[0187] The first and second via insulating layers (VIA1, VIA2) may include an insulating material. For example, the first and second via insulating layers (VIA1, VIA2) may include an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or aluminum oxide. The organic insulating layer may include, for example, an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and / or a benzocyclobutene resin.

[0188] Figures 8 to 14 are plan views for explaining the pixel circuit layer of Figure 7.

[0189] Referring to Figure 8, patterns implemented as a semiconductor pattern layer (ACT) are illustrated.

[0190] The semiconductor pattern layer (ACT) may include first to third semiconductor patterns (ACT1, ACT2, ACT3).

[0191] The first semiconductor pattern (ACT1) may be arranged in an area where the first sub-pixel circuit (SPC1) is provided. The second semiconductor pattern (ACT2) may be arranged in an area where the second sub-pixel circuit (SPC2) is provided. The third semiconductor pattern (ACT3) may be arranged in an area where the third sub-pixel circuit (SPC3) is provided.

[0192] The first semiconductor pattern (ACT1) may include first to second and fifth to eighth channel regions (CH1a, CH2a, CH5a, CH6a, CH7a, CH8a). The first to second and fifth to eighth channel regions (CH1a, CH2a, CH5a, CH6a, CH7a, CH8a) may be regions doped with impurities at a relatively low concentration, or may be regions that are substantially not doped with impurities. That is, the first to second and fifth to eighth channel regions (CH1a, CH2a, CH5a, CH6a, CH7a, CH8a) may be regions exhibiting semiconductor properties. The first to second and fifth to eighth channel regions (CH1a, CH2a, CH5a, CH6a, CH7a, CH8a) can function as channels of the first to second and fifth to eighth transistors (T1a, T2a, T5a, T6a, T7a, T8a) of the first sub-pixel circuit (SPC1).

[0193] In one embodiment, the first channel region (CH1a) may be referred to as a first driving channel region, the second channel region (CH2a) may be referred to as a first data writing channel region, the fifth channel region (CH5a) may be referred to as a first-second emission control channel region, and the sixth channel region (CH6a) may be referred to as a first-first emission control channel region.

[0194] Regions other than the first to second and fifth to eighth channel regions (CH1a, CH2a, CH5a, CH6a, CH7a, CH8a) in the first semiconductor pattern (ACT1) may be regions doped with impurities and thus conductive. These regions may function as terminals of transistors or as wirings connecting them to each other.

[0195] One region (S1a) adjacent to the first channel region (CH1a) can function as a first terminal of the first driving transistor (T1a), and the other region (D1a) can function as a second terminal of the first driving transistor (T1a).

[0196] One region (S2a) adjacent to the second channel region (CH2a) can function as a first terminal of a first data writing transistor (T2a), and the other region (D2a) can function as a second terminal of the first data writing transistor (T2a).

[0197] One region (S5a) adjacent to the fifth channel region (CH5a) can function as a first terminal of the first-second light-emitting control transistor (T5a), and the other region (D5a) can function as a second terminal of the first-second light-emitting control transistor (T5a).

[0198] One region (S6a) adjacent to the sixth channel region (CH6a) can function as a first terminal of the first-first light-emitting control transistor (T6a), and the other region (D6a) can function as a second terminal of the first-first light-emitting control transistor (T6a).

[0199] An area (S7a) adjacent to the seventh channel area (CH7a) can function as a first terminal of a first anode initialization transistor (T7a), and another area (D7a) can function as a second terminal of the first anode initialization transistor (T7a).

[0200] An area (S8a) adjacent to the eighth channel area (CH8a) can function as a first terminal of a first bias transistor (T8a), and another area (D8a) can function as a second terminal of the first bias transistor (T8a).

[0201] The second semiconductor pattern (ACT2) may include first to second and fifth to eighth channel regions (CH1b, CH2b, CH5b, CH6b, CH7b, CH8b). The first to second and fifth to eighth channel regions (CH1b, CH2b, CH5b, CH6b, CH7b, CH8b) may be regions exhibiting semiconductor properties. The first to second and fifth to eighth channel regions (CH1b, CH2b, CH5b, CH6b, CH7b, CH8b) may function as channels of the first to second and fifth to eighth transistors (T1b, T2b, T5b, T6b, T7b, T8b) of the second sub-pixel circuit (SPC2).

[0202] In one embodiment, the first channel region (CH1b) may be referred to as a second driving channel region, the second channel region (CH2b) may be referred to as a second data writing channel region, the fifth channel region (CH5b) may be referred to as a 2-2 emission control channel region, and the sixth channel region (CH6b) may be referred to as a 2-1 emission control channel region.

[0203] Regions other than the first to second and fifth to eighth channel regions (CH1b, CH2b, CH5b, CH6b, CH7b, CH8b) in the second semiconductor pattern (ACT2) may be conductive regions. These regions may function as terminals of the transistors or wirings connecting them to each other.

[0204] One region (S1b) adjacent to the first channel region (CH1b) can function as a first terminal of a second driving transistor (T1b), and the other region (D1b) can function as a second terminal of the first driving transistor (T1b).

[0205] A region (S2b) adjacent to the second channel region (CH2b) can function as a first terminal of a second data writing transistor (T2b), and another region (D2b) can function as a second terminal of the second data writing transistor (T2b).

[0206] One region (S5b) adjacent to the fifth channel region (CH5b) can function as a first terminal of the second-second light-emitting control transistor (T5b), and the other region (D5b) can function as a second terminal of the second-second light-emitting control transistor (T5b).

[0207] One region (S6b) adjacent to the sixth channel region (CH6b) can function as a first terminal of the second-first light-emitting control transistor (T6b), and the other region (D6b) can function as a second terminal of the second-first light-emitting control transistor (T6b).

[0208] One region (S7b) adjacent to the seventh channel region (CH7b) can function as a first terminal of a second anode initialization transistor (T7b), and the other region (D7b) can function as a second terminal of the second anode initialization transistor (T7b).

[0209] One region (S8b) adjacent to the eighth channel region (CH8b) can function as a first terminal of a second bias transistor (T8b), and the other region (D8b) can function as a second terminal of the second bias transistor (T8b).

[0210] The third semiconductor pattern (ACT3) may include first to second and fifth to eighth channel regions (CH1c, CH2c, CH5c, CH6c, CH7c, CH8c). The first to second and fifth to eighth channel regions (CH1c, CH2c, CH5c, CH6c, CH7c, CH8c) may be regions exhibiting semiconductor properties. The first to second and fifth to eighth channel regions (CH1c, CH2c, CH5c, CH6c, CH7c, CH8c) may function as channels of the first to second and fifth to eighth transistors (T1c, T2c, T5c, T6c, T7c, T8c) of the third sub-pixel circuit (SPC3).

[0211] In one embodiment, the first channel region (CH1c) may be referred to as a third driving channel region, the second channel region (CH2c) may be referred to as a third data writing channel region, the fifth channel region (CH5c) may be referred to as a third-second emission control channel region, and the sixth channel region (CH6c) may be referred to as a third-first emission control channel region.

[0212] Regions other than the first to second and fifth to eighth channel regions (CH1c, CH2c, CH5c, CH6c, CH7c, CH8c) in the third semiconductor pattern (ACT3) may be conductive regions. These regions may function as terminals of the transistors or as wirings connecting them to each other.

[0213] A region (S1c) adjacent to the first channel region (CH1c) can function as a first terminal of a third driving transistor (T1c), and another region (D1c) can function as a second terminal of the third driving transistor (T1c).

[0214] A region (S2c) adjacent to the second channel region (CH2c) can function as a first terminal of a third data writing transistor (T2c), and another region (D2c) can function as a second terminal of the third data writing transistor (T2c).

[0215] A region (S5c) adjacent to the fifth channel region (CH5c) can function as a first terminal of a third-second light-emitting control transistor (T5c), and another region (D5c) can function as a second terminal of the third-second light-emitting control transistor (T5c).

[0216] One region (S6c) adjacent to the sixth channel region (CH6c) can function as a first terminal of the third-first light-emitting control transistor (T6c), and the other region (D6c) can function as a second terminal of the third-first light-emitting control transistor (T6c).

[0217] A region (S7c) adjacent to the seventh channel region (CH7c) can function as a first terminal of a third anode initialization transistor (T7c), and another region (D7c) can function as a second terminal of the third anode initialization transistor (T7c).

[0218] An area (S8c) adjacent to the eighth channel area (CH8c) can function as a first terminal of a third bias transistor (T8c), and another area (D8c) can function as a second terminal of the third bias transistor (T8c).

[0219] In one embodiment, the channel length of the first channel region (CH1a) of the first semiconductor pattern (ACT1) may be smaller than the channel length of the first channel region (CH1b) of the second semiconductor pattern (ACT2) and smaller than the channel length of the first channel region (CH1c) of the third semiconductor pattern (ACT3).

[0220] Additionally, the channel width of the first channel region (CH1a) of the first semiconductor pattern (ACT1) may be larger than the channel width of the first channel region (CH1b) of the second semiconductor pattern (ACT2) and may be larger than the channel width of the first channel region (CH1c) of the third semiconductor pattern (ACT3).

[0221] Here, the term 'channel length' may be defined as the shortest distance between conductive regions (e.g., S1a and D1a) adjacent to a channel region (e.g., CH1a) when the channel region is interposed between conductive regions (e.g., S1a and D1a). For example, the channel length of the first channel region (CH1a) of the first semiconductor pattern (ACT1) may be the length of the first channel region (CH1a) in the first direction (DR1).

[0222] The term "channel width" may refer to the width of a channel region (e.g., CH1a) in a direction intersecting the aforementioned "channel length." For example, the channel width of the first channel region (CH1a) of the first semiconductor pattern (ACT1) may refer to the width of the first channel region (CH1a) in the second direction (DR2).

[0223] As the channel length and channel width of the first channel region (CH1a) of the first semiconductor pattern (ACT1) satisfy the aforementioned conditions, the intensity of the first driving current provided to the first anode electrode (AE1) can increase. Accordingly, the light-emitting efficiency of the first light-emitting element (LD1) can be further improved. More details will be described later with reference to FIGS. 32 and 33.

[0224] In one embodiment, the channel width of the fifth channel region (CH5a) of the first semiconductor pattern (ACT1) may be larger than the channel width of the fifth channel region (CH5b) of the second semiconductor pattern (ACT2) and may be larger than the channel width of the fifth channel region (CH5c) of the third semiconductor pattern (ACT3). Here, the channel width of the fifth channel region (CH5a) of the first semiconductor pattern (ACT1) may be the width of the fifth channel region (CH5a) in the first direction (DR1), as defined above, and the channel width of the fifth channel region (CH5b) of the second semiconductor pattern (ACT2) and the channel width of the fifth channel region (CH5c) of the third semiconductor pattern (ACT3) may also be defined similarly.

[0225] As the channel width of the fifth channel region (CH5a) of the first semiconductor pattern (ACT1) satisfies the above-described condition, the resistance of the path through which the first driving current flows in the first sub-pixel circuit (SPC1) can be relatively reduced. In this case, especially when the intensity of the first driving current provided to the first anode electrode (AE1) is relatively large as described above, the driving efficiency of the first sub-pixel (SP1) can be improved.

[0226] In one embodiment, the channel width of the sixth channel region (CH6a) of the first semiconductor pattern (ACT1) may be larger than the channel width of the sixth channel region (CH6b) of the second semiconductor pattern (ACT2) and may be larger than the channel width of the sixth channel region (CH6c) of the third semiconductor pattern (ACT3). In this case, especially when the intensity of the first driving current provided to the first anode electrode (AE1) is relatively large as described above, the driving efficiency of the first sub-pixel (SP1) may be improved.

[0227] In one embodiment, the resistance of the conductive regions (S5a, D5a) adjacent to the fifth channel region (CH5a) of the first semiconductor pattern (ACT1) may be smaller than the resistance of the conductive regions (S5b, D5b) adjacent to the fifth channel region (CH5b) of the second semiconductor pattern (ACT2) and may be smaller than the resistance of the conductive regions (S5c, D5c) adjacent to the fifth channel region (CH5c) of the third semiconductor pattern (ACT3). For example, the width of each of the conductive regions (S5a, D5a) adjacent to the fifth channel region (CH5a) of the first semiconductor pattern (ACT1) in the first direction (DR1) may be provided to be relatively large. In this case, particularly when the intensity of the first driving current provided to the first anode electrode (AE1) as described above is relatively large, the driving efficiency of the first sub-pixel (SP1) may be improved.

[0228] In one embodiment, the resistance of the conductive regions (S6a, D6a) adjacent to the sixth channel region (CH6a) of the first semiconductor pattern (ACT1) may be smaller than the resistance of the conductive regions (S6b, D6b) adjacent to the sixth channel region (CH6b) of the second semiconductor pattern (ACT2) and may be smaller than the resistance of the conductive regions (S6c, D6c) adjacent to the sixth channel region (CH6c) of the third semiconductor pattern (ACT3). For example, the width of each of the conductive regions (S6a, D6a) adjacent to the sixth channel region (CH6a) of the first semiconductor pattern (ACT1) in the first direction (DR1) may be provided to be relatively large. In this case, particularly when the intensity of the first driving current provided to the first anode electrode (AE1) as described above is relatively large, the driving efficiency of the first sub-pixel (SP1) may be improved.

[0229] Referring to FIG. 9, patterns implemented as a first gate conductive layer (GAT1) and a semiconductor pattern layer (ACT) described with reference to FIG. 8 are illustrated.

[0230] The first gate conductive layer (GAT1) may include a first gate line (GWL), a fourth gate line (GBL), a first gate electrode pattern (G1), and a light emission control gate electrode pattern (GP).

[0231] The first gate line (GWL) can overlap the first to third semiconductor patterns (ACT1, ACT2, ACT3) in a plane.

[0232] A portion of the first gate line (GWL) that overlaps the second channel region (CH2a) of the first semiconductor pattern (ACT1) in a plane can function as a gate electrode of the first data writing transistor (T2a). A portion of the first gate line (GWL) that overlaps the second channel region (CH2b) of the second semiconductor pattern (ACT2) in a plane can function as a gate electrode of the second data writing transistor (T2b). A portion of the first gate line (GWL) that overlaps the second channel region (CH2c) of the third semiconductor pattern (ACT3) in a plane can function as a gate electrode of the third data writing transistor (T2c).

[0233] The fourth gate line (GBL) can overlap the first to third semiconductor patterns (ACT1, ACT2, ACT3) in a plane.

[0234] A portion of the fourth gate line (GBL) that overlaps the seventh channel region (CH7a) of the first semiconductor pattern (ACT1) in a plane can function as a gate electrode of the first anode initialization transistor (T7a). A portion of the fourth gate line (GBL) that overlaps the seventh channel region (CH7b) of the second semiconductor pattern (ACT2) in a plane can function as a gate electrode of the second anode initialization transistor (T7b). A portion of the fourth gate line (GBL) that overlaps the seventh channel region (CH7c) of the third semiconductor pattern (ACT3) in a plane can function as a gate electrode of the third anode initialization transistor (T7c).

[0235] The first gate electrode pattern (G1) may include a first driving gate electrode (G1a), a second driving gate electrode (G1b), and a third driving gate electrode (G1c).

[0236] The first driving gate electrode (G1a) can overlap with the first semiconductor pattern (ACT1) in a plane. A portion of the first driving gate electrode (G1a) that overlaps with the first channel region (CH1a) of the first semiconductor pattern (ACT1) in a plane can function as a gate electrode of the first driving transistor (T1a).

[0237] The second driving gate electrode (G1b) can overlap with the second semiconductor pattern (ACT2) in a plane. The portion of the second driving gate electrode (G1b) that overlaps with the first channel region (CH1b) of the second semiconductor pattern (ACT2) in a plane can function as a gate electrode of the second driving transistor (T1b).

[0238] The third driving gate electrode (G1c) can overlap with the third semiconductor pattern (ACT3) in a plane. The portion of the third driving gate electrode (G1c) that overlaps with the first channel region (CH1c) of the third semiconductor pattern (ACT3) in a plane can function as a gate electrode of the third driving transistor (T1c).

[0239] The light-emitting control gate electrode pattern (GP) may include a first light-emitting control gate electrode (GPa), a second light-emitting control gate electrode (GPb), and a third light-emitting control gate electrode (GPc).

[0240] The first light-emitting control gate electrode (GPa) can overlap with the first semiconductor pattern (ACT1) in a plane. A portion of the first light-emitting control gate electrode (GPa) that overlaps with the fifth channel region (CH5a) of the first semiconductor pattern (ACT1) in a plane can function as a gate electrode of the first-second light-emitting control transistor (T5a). A portion of the first light-emitting control gate electrode (GPa) that overlaps with the sixth channel region (CH6a) of the first semiconductor pattern (ACT1) in a plane can function as a gate electrode of the first-first light-emitting control transistor (T6a).

[0241] The second light-emitting control gate electrode (GPb) can overlap the second semiconductor pattern (ACT2) in a plane. A portion of the second light-emitting control gate electrode (GPb) that overlaps the fifth channel region (CH5b) of the second semiconductor pattern (ACT2) in a plane can function as a gate electrode of the 2-2 light-emitting control transistor (T5b). A portion of the second light-emitting control gate electrode (GPb) that overlaps the sixth channel region (CH6b) of the second semiconductor pattern (ACT2) in a plane can function as a gate electrode of the 2-1 light-emitting control transistor (T6b).

[0242] The third light-emitting control gate electrode (GPc) can overlap with the third semiconductor pattern (ACT3) in a plane. A portion of the third light-emitting control gate electrode (GPc) that overlaps with the fifth channel region (CH5c) of the third semiconductor pattern (ACT3) in a plane can function as a gate electrode of the third-second light-emitting control transistor (T6c). A portion of the third light-emitting control gate electrode (GPc) that overlaps with the sixth channel region (CH6c) of the third semiconductor pattern (ACT3) in a plane can function as a gate electrode of the third-first light-emitting control transistor (T6c).

[0243] Referring to FIG. 10, patterns implemented as a second gate conductive layer (GAT2) and a semiconductor pattern layer (ACT) and a first gate conductive layer (GAT1) described with reference to FIGS. 8 and 9 are illustrated.

[0244] The second gate conductive layer (GAT2) may include a 3-1 gate line (GIL1), a 2-1 gate line (GCL1), a first horizontal power line (ELVDDL1), and an anode initialization line (VAINTL).

[0245] The 3-1 gate line (GIL1) can define a 3rd gate line (GIL) together with the 3-2 gate line (GIL2, see FIG. 12) described later. The 3-1 gate line (GIL1) can transmit a 3rd gate signal (GI).

[0246] The 2-1 gate line (GCL1) can define a second gate line (GCL) together with the 2-2 gate line (GCL2, see FIG. 12) described later. The 2-1 gate line (GCL1) can transmit a second gate signal (GC).

[0247] The first horizontal power line (ELVDDL1) can define a first power line (ELVDDL) together with the first vertical power line (ELVDDL2, see FIG. 14) described later. The first horizontal power line (ELVDDL1) can transmit a first power voltage (ELVDD).

[0248] The first horizontal power line (ELVDDL1) may overlap the first driving gate electrode (G1a) in a plane to form a first storage capacitor (CSTa). In this case, the first driving gate electrode (G1a) may function as a first electrode of the first storage capacitor (CSTa), and a portion of the first horizontal power line (ELVDDL1) that overlaps the first driving gate electrode (G1a) in a plane may function as a second electrode of the first storage capacitor (CSTa).

[0249] The first horizontal power line (ELVDDL1) may overlap the second driving gate electrode (G1b) in a plane to form a second storage capacitor (CSTb). In this case, the second driving gate electrode (G1b) may function as a first electrode of the second storage capacitor (CSTb), and the portion of the first horizontal power line (ELVDDL1) that overlaps the second driving gate electrode (G1b) in a plane may function as a second electrode of the second storage capacitor (CSTb).

[0250] The first horizontal power line (ELVDDL1) may overlap the third driving gate electrode (G1c) in a plane to form a third storage capacitor (CSTc). In this case, the third driving gate electrode (G1c) may function as a first electrode of the third storage capacitor (CSTc), and a portion of the first horizontal power line (ELVDDL1) that overlaps the third driving gate electrode (G1c) in a plane may function as a second electrode of the third storage capacitor (CSTc).

[0251] The first horizontal power line (ELVDDL1) may include first to third openings (OPN1, OPN2, OPN3). The first opening (OPN1) may overlap the first driving gate electrode (G1a) in a plane, thereby exposing a portion of the first driving gate electrode (G1a). The second opening (OPN2) may overlap the second driving gate electrode (G1b) in a plane, thereby exposing a portion of the second driving gate electrode (G1b). The third opening (OPN3) may overlap the third driving gate electrode (G1c) in a plane, thereby exposing a portion of the third driving gate electrode (G1c).

[0252] Referring to FIG. 11, patterns implemented with an oxide semiconductor pattern layer (OACT) and the semiconductor pattern layer (ACT) and first and second gate conductive layers (GAT1, GAT2) described with reference to FIGS. 8 to 10 are illustrated.

[0253] The oxide semiconductor pattern layer (OACT) may include first to third oxide semiconductor patterns (OACT1, OACT2, OACT3).

[0254] The first oxide semiconductor pattern (OACT1) may be arranged in an area where the first sub-pixel circuit (SPC1) is provided. The second oxide semiconductor pattern (OACT2) may be arranged in an area where the second sub-pixel circuit (SPC2) is provided. The third oxide semiconductor pattern (OACT3) may be arranged in an area where the third sub-pixel circuit (SPC3) is provided.

[0255] The first oxide semiconductor pattern (OACT1) may include third and fourth channel regions (CH3a, CH4a). The third and fourth channel regions (CH3a, CH4a) may be regions exhibiting semiconductor properties. The third and fourth channel regions (CH3a, CH4a) may function as channels of the third and fourth transistors (T3a, T4a) of the first sub-pixel circuit (SPC1).

[0256] The third channel region (CH3a) may overlap a portion of the second-first gate line (GCL1) in a planar manner. In this case, the portion of the second-first gate line (GCL1) may function as a bottom gate electrode of the first diode transistor (T3a).

[0257] The fourth channel region (CH4a) may overlap a portion of the 3-1 gate line (GIL1) in a planar manner. In this case, the portion of the 3-1 gate line (GCL1) may function as a bottom gate electrode of the first initialization transistor (T4a).

[0258] Regions other than the third and fourth channel regions (CH3a, CH4a) in the first oxide semiconductor pattern (OACT1) may be conductive regions. These regions may function as terminals of transistors or as wiring connecting them to each other.

[0259] A region (S3a) adjacent to the third channel region (CH3a) can function as a first terminal of a first diode transistor (T3a), and another region (D3a) can function as a second terminal of the first diode transistor (T3a).

[0260] A region (S4a) adjacent to the fourth channel region (CH4a) can function as a first terminal of a first initialization transistor (T4a), and another region (D4a) can function as a second terminal of the first initialization transistor (T4a).

[0261] The second oxide semiconductor pattern (OACT2) may include third and fourth channel regions (CH3b, CH4b). The third and fourth channel regions (CH3b, CH4b) may be regions exhibiting semiconductor properties. The third and fourth channel regions (CH3b, CH4b) may function as channels of the third and fourth transistors (T3b, T4b) of the second sub-pixel circuit (SPC2).

[0262] The third channel region (CH3b) may overlap a portion of the second-first gate line (GCL1) in a planar manner. In this case, the portion of the second-first gate line (GCL1) may function as a bottom gate electrode of the second diode transistor (T3b).

[0263] The fourth channel region (CH4b) may overlap a portion of the 3-1 gate line (GIL1) in a planar manner. In this case, the portion of the 3-1 gate line (GIL1) may function as a bottom gate electrode of the second initialization transistor (T4b).

[0264] Regions other than the third and fourth channel regions (CH3b, CH4b) in the second oxide semiconductor pattern (OACT2) may be conductive regions. These regions may function as terminals of transistors or as wiring connecting them to each other.

[0265] A region (S3b) adjacent to the third channel region (CH3b) can function as a first terminal of a second diode transistor (T3b), and another region (D3b) can function as a second terminal of the second diode transistor (T3b).

[0266] A region (S4b) adjacent to the fourth channel region (CH4b) can function as a first terminal of a second initialization transistor (T4b), and another region (D4b) can function as a second terminal of the second initialization transistor (T4b).

[0267] The third oxide semiconductor pattern (OACT3) may include third and fourth channel regions (CH3c, CH4c). The third and fourth channel regions (CH3c, CH4c) may be regions exhibiting semiconductor properties. The third and fourth channel regions (CH3c, CH4c) may function as channels of the third and fourth transistors (T3c, T4c) of the third sub-pixel circuit (SPC3).

[0268] The third channel region (CH3c) may overlap a portion of the second-first gate line (GCL1) in a plane. In this case, the portion of the second-first gate line (GCL1) may function as a bottom gate electrode of the third diode transistor (T3c).

[0269] The fourth channel region (CH4c) may overlap a portion of the third-first gate line (GIL1) in a planar manner. In this case, the portion of the third-first gate line (GIL1) may function as a bottom gate electrode of the third initialization transistor (T4c).

[0270] Regions other than the third and fourth channel regions (CH3c, CH4c) in the third oxide semiconductor pattern (OACT3) may be conductive regions. These regions may function as terminals of transistors or as wiring connecting them to each other.

[0271] A region (S3c) adjacent to a third channel region (CH3c) can function as a first terminal of a third diode transistor (T3c), and another region (D3c) can function as a second terminal of the third diode transistor (T3c).

[0272] A region (S4c) adjacent to the fourth channel region (CH4c) can function as a first terminal of a third initialization transistor (T4c), and another region (D3c) can function as a second terminal of the third initialization transistor (T4c).

[0273] Referring to FIG. 12, patterns implemented as a third gate conductive layer (GAT3), a semiconductor pattern layer (ACT), first and second gate conductive layers (GAT1, GAT2), and an oxide semiconductor pattern layer (OACT) described with reference to FIGS. 8 to 11 are illustrated.

[0274] The third gate conductive layer (GAT3) may include a third-second gate line (GIL2), a second-second gate line (GCL2), and a bias control line (VBL).

[0275] The third-second gate line (GIL2) can overlap the first to third oxide semiconductor patterns (OACT1, OACT2, OACT3) in a plane. The third-second gate line (GIL2) can transmit a third gate signal (GI).

[0276] A portion of the 3-2 gate line (GIL2) that overlaps the fourth channel region (CH4a) of the first oxide semiconductor pattern (OACT1) in a plane can function as an upper gate electrode of the first initialization transistor (T4a). A portion of the 3-2 gate line (GIL2) that overlaps the fourth channel region (CH4b) of the second oxide semiconductor pattern (OACT2) in a plane can function as an upper gate electrode of the second initialization transistor (T4b). A portion of the 3-2 gate line (GIL2) that overlaps the fourth channel region (CH4c) of the third oxide semiconductor pattern (OACT3) in a plane can function as an upper gate electrode of the third initialization transistor (T4c).

[0277] The second-second gate line (GCL2) can overlap the first to third oxide semiconductor patterns (OACT1, OACT2, OACT3) in a plane. The second-second gate line (GCL2) can transmit a second gate signal (GC).

[0278] A portion of the 2-2 gate line (GCL2) that overlaps the third channel region (CH3a) of the first oxide semiconductor pattern (OACT1) in a plane can function as an upper gate electrode of the first diode transistor (T3a). A portion of the 2-2 gate line (GCL2) that overlaps the third channel region (CH3b) of the second oxide semiconductor pattern (OACT2) in a plane can function as an upper gate electrode of the second diode transistor (T3b). A portion of the 2-2 gate line (GCL2) that overlaps the third channel region (CH3c) of the third oxide semiconductor pattern (OACT3) in a plane can function as an upper gate electrode of the third diode transistor (T3c).

[0279] Referring to FIG. 13, patterns implemented as a first SD conductive layer (SD1), a semiconductor pattern layer (ACT), first to third gate conductive layers (GAT1, GAT2, GAT3), and an oxide semiconductor pattern layer (OACT) described with reference to FIGS. 8 to 12 are illustrated.

[0280] The first SD conductive layer (SD1) may include an initialization line (VINTL), a first emission control signal line (EML1), a second emission control signal line (EML2), and first to seventh bridge electrodes (BR1, BR2, BR3, BR4, BR5, BR6, BR7).

[0281] An initialization line (VINTL) can be connected to the first to third oxide semiconductor patterns (OACT1, OACT2, OACT3) through contact holes. Through the initialization line (VINTL), an initialization voltage (VINT) can be transmitted to a second terminal (D4a) of a first initialization transistor (T4a), a second terminal (D4b) of a second initialization transistor (T4b), and a second terminal (D4c) of a third initialization transistor (T4c).

[0282] The first light emission control signal line (EML1) can be connected to the first light emission control gate electrode (GPa) through a contact hole.

[0283] The second light emission control signal line (EML2) can be connected to the second and third light emission control gate electrodes (GPb, GPc) through contact holes.

[0284] The first bridge electrode (BR1) may include a first-first bridge electrode (BR1a), a first-second bridge electrode (BR1b), and a first-third bridge electrode (BR1c).

[0285] The first-first bridge electrode (BR1a) can be connected to the first semiconductor pattern (ACT1) through a contact hole. The first-first bridge electrode (BR1a) can be connected to the first terminal (S2a) of the first data write transistor (T2a).

[0286] The first-second bridge electrode (BR1b) can be connected to the second semiconductor pattern (ACT2) through a contact hole. The first-second bridge electrode (BR1b) can be connected to the first terminal (S2b) of the second data writing transistor (T2b).

[0287] The first-third bridge electrode (BR1c) can be connected to the third semiconductor pattern (ACT3) through a contact hole. The first-third bridge electrode (BR1c) can be connected to the first terminal (S2c) of the third data writing transistor (T2c).

[0288] The second bridge electrode (BR2) may include a second-first bridge electrode (BR2a), a second-second bridge electrode (BR2b), and a second-third bridge electrode (BR2c).

[0289] The second-first bridge electrode (BR2a) can be connected to the first oxide semiconductor pattern (OACT1) and the first driving gate electrode (G1a) through contact holes. The first terminal (S3a) of the first diode transistor (T3a), the first terminal (S4a) of the first initialization transistor (T4a), and the first driving gate electrode (G1a) can be connected to each other through the second-first bridge electrode (BR2a).

[0290] The second-second bridge electrode (BR2b) can be connected to the second oxide semiconductor pattern (OACT2) and the second driving gate electrode (G1b) through contact holes. The first terminal (S3b) of the second diode transistor (T3b), the first terminal (S4b) of the second initialization transistor (T4b), and the second driving gate electrode (G1b) can be connected to each other through the second-second bridge electrode (BR2b).

[0291] The second-third bridge electrode (BR2c) can be connected to the third oxide semiconductor pattern (OACT3) and the third driving gate electrode (G1c) through contact holes. The first terminal (S3c) of the third diode transistor (T3c), the first terminal (S4c) of the third initialization transistor (T4c), and the third driving gate electrode (G1c) can be connected to each other through the second-third bridge electrode (BR2c).

[0292] The second-first bridge electrode (BR2a) may overlap the first gate line (GWL) in a plane to form a first boosting capacitor (CBSTa). In this case, the first gate line (GWL) may function as a first electrode of the first boosting capacitor (CBSTa), and the second-first bridge electrode (BR2a) may function as a second electrode of the first boosting capacitor (CBSTa).

[0293] The second-second bridge electrode (BR2b) may overlap the first gate line (GWL) in a plane to form a second boosting capacitor (CBSTb). In this case, the first gate line (GWL) may function as a first electrode of the second boosting capacitor (CBSTb), and the second-second bridge electrode (BR2b) may function as a second electrode of the second boosting capacitor (CBSTb).

[0294] The second-third bridge electrode (BR2c) may overlap the first gate line (GWL) in a plane to form a third boosting capacitor (CBSTc). In this case, the first gate line (GWL) may function as a first electrode of the third boosting capacitor (CBSTc), and the second-third bridge electrode (BR2c) may function as a second electrode of the third boosting capacitor (CBSTc).

[0295] The third bridge electrode (BR3) may include a third-first bridge electrode (BR3a), a third-second bridge electrode (BR3b), and a third-third bridge electrode (BR3c).

[0296] The third-first bridge electrode (BR3a) can be connected to the first oxide semiconductor pattern (OACT1) and the first semiconductor pattern (ACT1) through contact holes. The second terminal (D3a) of the first diode transistor (T3a) can be connected to the second terminal (D1a) of the first driving transistor (T1a) through the third-first bridge electrode (BR3a).

[0297] The third-second bridge electrode (BR3b) can be connected to the second oxide semiconductor pattern (OACT2) and the second semiconductor pattern (ACT2) through contact holes. The second terminal (D3b) of the second diode transistor (T3b) can be connected to the second terminal (D1b) of the second driving transistor (T1b) through the third-second bridge electrode (BR3b).

[0298] The third-third bridge electrode (BR3c) can be connected to the third oxide semiconductor pattern (OACT3) and the third semiconductor pattern (ACT3) through contact holes. The second terminal (D3c) of the third diode transistor (T3c) can be connected to the second terminal (D1c) of the third driving transistor (T1c) through the third-third bridge electrode (BR3c).

[0299] The fourth bridge electrode (BR4) may include a fourth-first bridge electrode (BR4a), a fourth-second bridge electrode (BR4b), and a fourth-third bridge electrode (BR4c).

[0300] The 4-1 bridge electrode (BR4a) can be connected to the first semiconductor pattern (ACT1) and the first horizontal power line (ELVDDL1) through contact holes. The first power voltage (ELVDD) can be transmitted to the first terminal (S5a) of the 1-2 light-emitting control transistor (T5a) through the 4-1 bridge electrode (BR4a).

[0301] The 4-2 bridge electrode (BR4b) can be connected to the second semiconductor pattern (ACT2) and the first horizontal power line (ELVDDL1) through contact holes. The first power voltage (ELVDD) can be transmitted to the first terminal (S5b) of the 2-2 light-emitting control transistor (T5b) through the 4-2 bridge electrode (BR4b).

[0302] The 4-3 bridge electrode (BR4c) can be connected to the third semiconductor pattern (ACT3) and the first horizontal power line (ELVDDL1) through contact holes. The first power voltage (ELVDD) can be transmitted to the first terminal (S5c) of the 3-2 light-emitting control transistor (T5c) through the 4-3 bridge electrode (BR4c).

[0303] The fifth bridge electrode (BR5) may include a fifth-first bridge electrode (BR5a), a fifth-second bridge electrode (BR5b), and a fifth-third bridge electrode (BR5c).

[0304] The 5-1 bridge electrode (BR5a) can be connected to the first semiconductor pattern (ACT1) and the bias control line (VBL) through contact holes. A bias voltage (VB) can be transmitted to the first terminal (S8a) of the first bias transistor (T8a) through the 5-1 bridge electrode (BR5a).

[0305] The 5-2 bridge electrode (BR5b) can be connected to the second semiconductor pattern (ACT2) and the bias control line (VBL) through contact holes. A bias voltage (VB) can be transmitted to the first terminal (S8b) of the second bias transistor (T8b) through the 5-2 bridge electrode (BR5b).

[0306] The 5-3 bridge electrode (BR5c) can be connected to the third semiconductor pattern (ACT3) and the bias control line (VBL) through contact holes. A bias voltage (VB) can be transmitted to the first terminal (S8c) of the third bias transistor (T8c) through the 5-3 bridge electrode (BR5c).

[0307] The sixth bridge electrode (BR6) may include a 6-1st bridge electrode (BR6a), a 6-2nd bridge electrode (BR6b), and a 6-3rd bridge electrode (BR6c).

[0308] The 6-1 bridge electrode (BR6a) can be connected to the first semiconductor pattern (ACT1) and the anode initialization line (VAINTL) through contact holes. The anode initialization voltage (VAINT) can be transmitted to the first terminal (S7a) of the first anode initialization transistor (T7a) through the 6-1 bridge electrode (BR6a).

[0309] The 6-2 bridge electrode (BR6b) can be connected to the second semiconductor pattern (ACT2) and the anode initialization line (VAINTL) through contact holes. The anode initialization voltage (VAINT) can be transmitted to the first terminal (S7b) of the second anode initialization transistor (T7b) through the 6-2 bridge electrode (BR6b).

[0310] The 6-3 bridge electrode (BR6c) can be connected to the third semiconductor pattern (ACT3) and the anode initialization line (VAINTL) through contact holes. The anode initialization voltage (VAINT) can be transmitted to the first terminal (S7c) of the third anode initialization transistor (T7c) through the 6-3 bridge electrode (BR6c).

[0311] The seventh bridge electrode (BR7) may include a 7-1st bridge electrode (BR7a), a 7-2nd bridge electrode (BR7b), and a 7-3rd bridge electrode (BR7c).

[0312] The 7-1 bridge electrode (BR7a) can be connected to the first semiconductor pattern (ACT1) through a contact hole. The 7-1 bridge electrode (BR7a) can be connected to the second terminal (D6a) of the 1-1 light-emitting control transistor (T6a) and the second terminal (D7a) of the first anode initialization transistor (T7a).

[0313] The 7-2 bridge electrode (BR7b) can be connected to the second semiconductor pattern (ACT2) through a contact hole. The 7-2 bridge electrode (BR7b) can be connected to the second terminal (D6b) of the 2-1 light-emitting control transistor (T6b) and the second terminal (D7b) of the second anode initialization transistor (T7b).

[0314] The 7-3 bridge electrode (BR7c) can be connected to the third semiconductor pattern (ACT3) through a contact hole. The 7-3 bridge electrode (BR7c) can be connected to the second terminal (D6c) of the 3-1 light-emitting control transistor (T6c) and the second terminal (D7c) of the second anode initialization transistor (T7c).

[0315] Referring to FIG. 14, patterns implemented as a second SD conductive layer (SD2), a semiconductor pattern layer (ACT), first to third gate conductive layers (GAT1, GAT2, GAT3), an oxide semiconductor pattern layer (OACT), and a first SD conductive layer (SD1) described with reference to FIGS. 8 to 13 are illustrated.

[0316] The second SD conductive layer (SD2) may include a data line (DL), a first vertical power line (ELVDDL2), and an anode bridge electrode (ABR).

[0317] The data line (DL) may include a first data line (DL1), a second data line (DL2), and a third data line (DL3).

[0318] A first data line (DL1) can be connected to a first-first bridge electrode (BR1a) through a contact hole. A first data signal (DATA1) can be transmitted to a first terminal (S2a) of a first data write transistor (T2a) through the first data line (DL1) and the first-first bridge electrode (BR1a) connected thereto.

[0319] A second data line (DL2) can be connected to the first-second bridge electrode (BR1b) through a contact hole. A second data signal (DATA2) can be transmitted to the first terminal (S2b) of the second data write transistor (T2b) through the second data line (DL2) and the first-second bridge electrode (BR1b) connected thereto.

[0320] A third data line (DL3) can be connected to a first-third bridge electrode (BR1c) through a contact hole. A third data signal (DATA3) can be transmitted to a first terminal (S2c) of a third data write transistor (T2c) through the third data line (DL3) and the first-third bridge electrode (BR1c) connected thereto.

[0321] The first vertical power line (ELVDDL2) can transmit the first power voltage (ELVDD). The first vertical power line (ELVDDL2) can include a first-first vertical power line (ELVDDL2a), a first-second vertical power line (ELVDDL2b), and a first-third vertical power line (ELVDDL2c).

[0322] The first-first vertical power line (ELVDDL2a) can be connected to the first horizontal power line (ELVDDL1) through a contact hole in an area where the first sub-pixel circuit (SPC1) is provided. The first-second vertical power line (ELVDDL2b) can be connected to the first horizontal power line (ELVDDL1) through a contact hole in an area where the second sub-pixel circuit (SPC2) is provided. The first-third vertical power line (ELVDDL2c) can be connected to the first horizontal power line (ELVDDL1) through a contact hole in an area where the third sub-pixel circuit (SPC3) is provided.

[0323] The anode bridge electrode (ABR) may include a first anode bridge electrode (ABRa), a second anode bridge electrode (ABRb), and a third anode bridge electrode (ABRc).

[0324] The first anode bridge electrode (ABRa) can be connected to the 7-1 bridge electrode (BR7a) through a contact hole. The first anode bridge electrode (ABRa) can be connected to the first anode electrode (AE1).

[0325] The second anode bridge electrode (ABRb) can be connected to the 7-2 bridge electrode (BR7b) through a contact hole. The second anode bridge electrode (ABRb) can be connected to the second anode electrode (AE2).

[0326] The third anode bridge electrode (ABRc) can be connected to the 7-3 bridge electrode (BR7c) through a contact hole. The third anode bridge electrode (ABRc) can be connected to the third anode electrode (AE3).

[0327] Fig. 15 is a cross-sectional view taken along line XA-XA' of Fig. 14. Fig. 16 is a cross-sectional view taken along line XB-XB' of Fig. 14.

[0328] Referring to FIGS. 15 and 16, the first light emission control signal line (EML1) can be connected to the first light emission control gate electrode (GPa), and the second light emission control signal line (EML2) can be connected to the second and third light emission control gate electrodes (GPb, GPc).

[0329] The first light emission control signal line (EML1) may not be connected to the second and third light emission control gate electrodes (GPb, GPc), and the second light emission control signal line (EML2) may not be connected to the first light emission control gate electrode (GPa).

[0330] Accordingly, in order to match the optimal driving characteristics of the first to third sub-pixels (SP1, SP2, SP3), it is possible to transmit a first light emission control signal (EM1) to the first sub-pixel circuit (SPC1) through the first light emission control signal line (EML1), and to transmit a second light emission control signal (EM2) different from the first light emission control signal (EM1) to the second and third sub-pixel circuits (SPC2, SPC3) through the second light emission control signal line (EML2).

[0331] FIG. 17 is a cross-sectional view illustrating another embodiment of a pixel circuit layer included in the pixel of FIG. 6.

[0332] Hereinafter, in explaining another embodiment of a pixel circuit layer (PCL), the differences compared to the embodiment of a pixel circuit layer (PCL) explained with reference to FIG. 7 will be explained, and the omitted parts will be replaced with the previous content.

[0333] Referring to FIG. 17, the pixel circuit layer (PCL) may include a semiconductor pattern layer (ACT'), a first insulating layer (INL1), a first gate conductive layer (GAT1'), a second insulating layer (INL2), a second gate conductive layer (GAT2'), a third insulating layer (INL3), an oxide semiconductor pattern layer (OACT'), a fourth insulating layer (INL4), a third gate conductive layer (GAT3'), a fifth insulating layer (INL5), a first SD conductive layer (SD1'), a first via insulating layer (VIA1), a second SD conductive layer (SD2'), and a second via insulating layer (VIA2) that are sequentially stacked in a third direction (DR3).

[0334] The first to third gate conductive layers (GAT1', GAT2', GAT3') and the first and second SD conductive layers (SD1', SD2') may include a conductive material. The semiconductor pattern layer (ACT') may include a silicon semiconductor (e.g., LTPS). The oxide semiconductor pattern layer (OACT') may include an oxide semiconductor (e.g., LTPO). If necessary, two or more components among the first to third gate conductive layers (GAT1', GAT2', GAT3'), the first and second SD conductive layers (SD1', SD2'), the semiconductor pattern layer (ACT'), and the oxide semiconductor pattern layer (OACT') may be connected to each other through contact holes formed in the first to fifth insulating layers (INL1, INL2, INL3, INL4, INL5) and the first and second via insulating layers (VIA1, VIA2).

[0335] FIGS. 18 to 24 are plan views for explaining the pixel circuit layer of FIG. 17. Hereinafter, in explaining the pixel circuit layer of FIG. 17, differences compared to the pixel circuit layer explained with reference to FIGS. 7 to 16 will be mainly explained, and parts that are omitted will be replaced with the previous content.

[0336] Referring to FIG. 18, patterns implemented as a semiconductor pattern layer (ACT') are illustrated.

[0337] The semiconductor pattern layer (ACT') may include first to third semiconductor patterns (ACT1', ACT2', ACT3').

[0338] The first semiconductor pattern (ACT1') may be arranged in an area where the first sub-pixel circuit (SPC1') is provided. The second semiconductor pattern (ACT2') may be arranged in an area where the second sub-pixel circuit (SPC2') is provided. The third semiconductor pattern (ACT3') may be arranged in an area where the third sub-pixel circuit (SPC3') is provided.

[0339] The first semiconductor pattern (ACT1') may include first to second and fifth to eighth channel regions (CH1a, CH2a, CH5a, CH6a, CH7a, CH8a). The first to second and fifth to eighth channel regions (CH1a, CH2a, CH5a, CH6a, CH7a, CH8a) may function as channels of the first to second and fifth to eighth transistors (T1a, T2a, T5a, T6a, T7a, T8a) included in the first sub-pixel circuit (SPC1').

[0340] Regions other than the first to second and fifth to eighth channel regions (CH1a, CH2a, CH5a, CH6a, CH7a, CH8a) in the first semiconductor pattern (ACT1') may be regions doped with impurities and thus conductive. These regions may function as terminals of transistors or as wirings connecting them to each other.

[0341] The second semiconductor pattern (ACT2') may include first to second and fifth to eighth channel regions (CH1b, CH2b, CH5b, CH6b, CH7b, CH8b). The first to second and fifth to eighth channel regions (CH1b, CH2b, CH5b, CH6b, CH7b, CH8b) may function as channels of the first to second and fifth to eighth transistors (T1b, T2b, T5b, T6b, T7b, T8b) included in the second sub-pixel circuit (SPC2').

[0342] Regions other than the first to second and fifth to eighth channel regions (CH1b, CH2b, CH5b, CH6b, CH7b, CH8b) in the second semiconductor pattern (ACT2') may be conductive regions. These regions may function as terminals of transistors or wirings connecting them to each other.

[0343] The third semiconductor pattern (ACT3') may include first to second and fifth to eighth channel regions (CH1c, CH2c, CH5c, CH6c, CH7c, CH8c). The first to second and fifth to eighth channel regions (CH1c, CH2c, CH5c, CH6c, CH7c, CH8c) may function as channels of the first to second and fifth to eighth transistors (T1c, T2c, T5c, T6c, T7c, T8c) included in the third sub-pixel circuit (SPC3').

[0344] Regions other than the first to second and fifth to eighth channel regions (CH1c, CH2c, CH5c, CH6c, CH7c, CH8c) in the third semiconductor pattern (ACT3') may be conductive regions. These regions may function as terminals of transistors or wirings connecting them to each other.

[0345] The description of the channel width and channel length described with reference to FIG. 8 can be substantially equally applied to the semiconductor pattern layer (ACT') illustrated in FIG. 18.

[0346] The semiconductor pattern layer (ACT') illustrated in FIG. 18 may have a form in which the second semiconductor pattern (ACT2') and the third semiconductor pattern (ACT3') are substantially symmetrical to each other, unlike the semiconductor pattern layer (ACT) described with reference to FIG. 8. That is, the semiconductor pattern layer (ACT') constituting the second and third sub-pixel circuits (SPC2', SPC3') may be implemented in a flip type.

[0347] Referring to FIG. 19, patterns implemented as a first gate conductive layer (GAT1') and a semiconductor pattern layer (ACT') described with reference to FIG. 18 are illustrated.

[0348] The first gate conductive layer (GAT1') may include a first gate line (GWL'), a fourth gate line (GBL'), a first gate electrode pattern (G1'), and a light emission control gate electrode pattern (GP').

[0349] The first gate line (GWL') and the fourth gate line (GBL') can be described in the same manner as the first gate line (GWL) and the fourth gate line (GBL) described with reference to Fig. 9. Therefore, description of overlapping content is omitted.

[0350] The first gate electrode pattern (G1') may include a first driving gate electrode (G1a'), a second driving gate electrode (G1b'), and a third driving gate electrode (G1c'). The first gate electrode pattern (G1') may be described in the same manner as the first gate electrode pattern (G1) described with reference to FIG. 9. Therefore, description of overlapping content is omitted.

[0351] The light-emitting control gate electrode pattern (GP') may include a first light-emitting control gate electrode (GPa') and a second light-emitting control gate electrode (GPb').

[0352] The first light emission control gate electrode (GPa') can be described in the same manner as the first light emission control gate electrode (GPa) described with reference to Fig. 9. Therefore, description of overlapping content is omitted.

[0353] The second light-emitting control gate electrode (GPb') can overlap the second and third semiconductor patterns (ACT2', ACT3') in a plane.

[0354] A portion of the second light-emitting control gate electrode (GPb') that overlaps the fifth channel region (CH5b) of the second semiconductor pattern (ACT2') in a plane can function as a gate electrode of the second-second light-emitting control transistor (T5b).

[0355] A portion of the second light-emitting control gate electrode (GPb') that overlaps the sixth channel region (CH6b) of the second semiconductor pattern (ACT2') in a plane can function as a gate electrode of the second-first light-emitting control transistor (T6b).

[0356] The portion of the second light-emitting control gate electrode (GPb') that overlaps the fifth channel region (CH5c) of the third semiconductor pattern (ACT3') in a plane can function as a gate electrode of the third-second light-emitting control transistor (T6c).

[0357] The portion of the second light-emitting control gate electrode (GPb') that overlaps the 6-channel region (CH6c) of the third semiconductor pattern (ACT3') in the plane can function as a gate electrode of the third-first light-emitting control transistor (T6c).

[0358] Referring to FIG. 20, patterns implemented as a second gate conductive layer (GAT2') and a semiconductor pattern layer (ACT') and a first gate conductive layer (GAT1') described with reference to FIGS. 18 and 19 are illustrated.

[0359] The second gate conductive layer (GAT2') may include a 3-1 gate line (GIL1'), a 2-1 gate line (GCL1'), a first horizontal power line (ELVDDL1'), and an anode initialization line (VAINTL').

[0360] The 3-1 gate line (GIL1'), the 2-1 gate line (GCL1'), and the anode initialization line (VAINTL') can be described in the same manner as the 3-1 gate line (GIL1), the 2-1 gate line (GCL1), and the anode initialization line (VAINTL) described with reference to Fig. 10. Therefore, description of overlapping content is omitted.

[0361] The first horizontal power line (ELVDDL1') can be described in the same manner as the first horizontal power line (ELVDDL1) described with reference to Fig. 10. For example, the first horizontal power line (ELVDDL1') can overlap the first gate electrode pattern (G1') in a plane to form first to third storage capacitors (CSTa, CSTb, CSTc). The first horizontal power line (ELVDDL1') can include first to third openings (OPN1', OPN2', OPN3') that overlap the first to third driving gate electrodes (G1a', G1b', G1c') in a plane.

[0362] Referring to FIG. 21, patterns implemented with an oxide semiconductor pattern layer (OACT') and the semiconductor pattern layer (ACT') and first and second gate conductive layers (GAT1', GAT2') described with reference to FIGS. 18 to 20 are illustrated.

[0363] The oxide semiconductor pattern layer (OACT') may include first to third oxide semiconductor patterns (OACT1', OACT2', OACT3').

[0364] The first oxide semiconductor pattern (OACT1') may be arranged in an area where the first sub-pixel circuit (SPC1') is provided. The second oxide semiconductor pattern (OACT2') may be arranged in an area where the second sub-pixel circuit (SPC2') is provided. The third oxide semiconductor pattern (OACT3') may be arranged in an area where the third sub-pixel circuit (SPC3') is provided.

[0365] The first oxide semiconductor pattern (OACT1') may include third and fourth channel regions (CH3a, CH4a). The third and fourth channel regions (CH3a, CH4a) may function as channels of the third and fourth transistors (T3a, T4a) of the first sub-pixel circuit (SPC1').

[0366] Regions other than the third and fourth channel regions (CH3a, CH4a) in the first oxide semiconductor pattern (OACT1') may be conductive regions. These regions may function as terminals of transistors or wiring connecting them to each other.

[0367] The second oxide semiconductor pattern (OACT2') may include third and fourth channel regions (CH3b, CH4b). The third and fourth channel regions (CH3b, CH4b) may function as channels of the third and fourth transistors (T3b, T4b) of the second sub-pixel circuit (SPC2').

[0368] Regions other than the third and fourth channel regions (CH3b, CH4b) in the second oxide semiconductor pattern (OACT2') may be conductive regions. These regions may function as terminals of transistors or as wiring connecting them to each other.

[0369] The third oxide semiconductor pattern (OACT3') may include third and fourth channel regions (CH3c, CH4c). The third and fourth channel regions (CH3c, CH4c) may function as channels of the third and fourth transistors (T3c, T4c) of the third sub-pixel circuit (SPC3').

[0370] Regions other than the third and fourth channel regions (CH3c, CH4c) in the third oxide semiconductor pattern (OACT3') may be conductive regions. These regions may function as terminals of transistors or as wiring connecting them to each other.

[0371] The oxide semiconductor pattern layer (OACT') illustrated in FIG. 21 may have a form in which the second oxide semiconductor pattern (OACT2') and the third oxide semiconductor pattern (OACT3') are substantially symmetrical to each other, unlike the oxide semiconductor pattern layer (OACT) described with reference to FIG. 11. That is, the oxide semiconductor pattern layer (OACT') constituting the second and third sub-pixel circuits (SPC2', SPC3') may be implemented in a flip type.

[0372] Referring to FIG. 22, patterns implemented as a third gate conductive layer (GAT3'), a semiconductor pattern layer (ACT'), first and second gate conductive layers (GAT1', GAT2'), and an oxide semiconductor pattern layer (OACT') described with reference to FIGS. 18 to 21 are illustrated.

[0373] The third gate conductive layer (GAT3') may include a third-second gate line (GIL2'), a second-second gate line (GCL2'), and a bias control line (VBL').

[0374] The 3-2 gate line (GIL2'), the 2-2 gate line (GCL2'), and the bias control line (VBL') can be described in the same manner as the 3-2 gate line (GIL2), the 2-2 gate line (GCL2), and the bias control line (VBL) described with reference to Fig. 11. Therefore, description of overlapping content is omitted.

[0375] Referring to FIG. 23, patterns implemented as a first SD conductive layer (SD1'), a semiconductor pattern layer (ACT'), first to third gate conductive layers (GAT1', GAT2', GAT3'), and an oxide semiconductor pattern layer (OACT') described with reference to FIGS. 18 to 22 are illustrated.

[0376] The first SD conductive layer (SD1') may include an initialization line (VINTL'), a first emission control signal line (EML1'), a second emission control signal line (EML2'), and first to seventh bridge electrodes (BR1', BR2', BR3', BR4', BR5', BR6', BR7').

[0377] The initialization line (VINTL') can be explained in the same way as the initialization line (VINTL) explained with reference to Fig. 13. Therefore, explanation of overlapping content is omitted.

[0378] The first light emission control signal line (EML1') can be connected to the first light emission control gate electrode (GPa') through a contact hole.

[0379] The second light emission control signal line (EML2') can be connected to the second light emission control gate electrode (GPb') through a contact hole.

[0380] The first bridge electrode (BR1') may include a first-first bridge electrode (BR1a'), a first-second bridge electrode (BR1b'), and a first-third bridge electrode (BR1c'). The first bridge electrode (BR1') may be described in the same manner as the first bridge electrode (BR1) described with reference to FIG. 13. Therefore, description of overlapping content is omitted.

[0381] The second bridge electrode (BR2') may include a second-first bridge electrode (BR2a'), a second-second bridge electrode (BR2b'), and a second-third bridge electrode (BR2c'). The second bridge electrode (BR2') may be described in the same manner as the second bridge electrode (BR2) described with reference to FIG. 13. For example, the second-first bridge electrode (BR2a'), the second-second bridge electrode (BR2b'), and the second-third bridge electrode (BR2c') may overlap the first gate line (GWL') in a plane to form first to third boosting capacitors (CBSTa, CBSTb, CBSTc). Hereinafter, descriptions of overlapping contents are omitted.

[0382] The third bridge electrode (BR3') may include a third-first bridge electrode (BR3a'), a third-second bridge electrode (BR3b'), and a third-third bridge electrode (BR3c'). The third bridge electrode (BR3') may be described in the same manner as the third bridge electrode (BR3) described with reference to FIG. 13. Therefore, description of overlapping content is omitted.

[0383] The fourth bridge electrode (BR4') may include a fourth-first bridge electrode (BR4a') and a fourth-second bridge electrode (BR4b').

[0384] The 4-1 bridge electrode (BR4a') can be described in the same manner as the 4-1 bridge electrode (BR4a) described with reference to Fig. 13. Therefore, description of overlapping content is omitted.

[0385] The 4-2 bridge electrode (BR4b') can be connected to the second semiconductor pattern (ACT2'), the third semiconductor pattern (ACT3'), and the first horizontal power line (ELVDDL1') through contact holes. The first power voltage (ELVDDL) can be transmitted to the first terminal (S5b) of the 2-2 light-emitting control transistor (T5b) and the first terminal (S5c) of the 3-2 light-emitting control transistor (T5c) through the 4-2 bridge electrode (BR4b').

[0386] The fifth bridge electrode (BR5') may include the fifth-first bridge electrode (BR5a'), the fifth-second bridge electrode (BR5b'), and the fifth-third bridge electrode (BR5c'). The fifth bridge electrode (BR5') may be described in the same manner as the fifth bridge electrode (BR5) described with reference to FIG. 13. Therefore, description of overlapping content is omitted.

[0387] The sixth bridge electrode (BR6') may include a sixth-first bridge electrode (BR6a') and a sixth-second bridge electrode (BR6b').

[0388] The 6-1 bridge electrode (BR6a') can be described in the same manner as the 6-1 bridge electrode (BR6a) described with reference to Fig. 13. Therefore, description of overlapping content is omitted.

[0389] The 6-2 bridge electrode (BR6b') can be connected to the second semiconductor pattern (ACT2'), the third semiconductor pattern (ACT3'), and the anode initialization line (VAINTL') through contact holes. The anode initialization voltage (VAINT) can be transmitted to the first terminal (S7b) of the second anode initialization transistor (T7b) and the first terminal (S7c) of the third anode initialization transistor (T7c) through the 6-2 bridge electrode (BR6b').

[0390] The seventh bridge electrode (BR7') may include the seventh-first bridge electrode (BR7a'), the seventh-second bridge electrode (BR7b'), and the seventh-third bridge electrode (BR7c'). The seventh bridge electrode (BR7') may be described in the same manner as the seventh bridge electrode (BR7) described with reference to FIG. 13. Therefore, description of overlapping content is omitted.

[0391] Referring to FIG. 24, patterns implemented as a second SD conductive layer (SD2'), a semiconductor pattern layer (ACT') described with reference to FIGS. 18 to 23, first to third gate conductive layers (GAT1', GAT2', GAT3'), an oxide semiconductor pattern layer (OACT'), and a first SD conductive layer (SD1') are illustrated.

[0392] The second SD conductive layer (SD2') may include a data line (DL'), a first vertical power line (ELVDDL2'), and an anode bridge electrode (ABR').

[0393] The data line (DL') may include a first data line (DL1'), a second data line (DL2'), and a third data line (DL3'). The data line (DL') may be described in the same manner as the data line (DL) described with reference to FIG. 14. Therefore, description of overlapping content is omitted.

[0394] The first vertical power line (ELVDDL2') can transmit the first power voltage (ELVDD). The first vertical power line (ELVDDL2') can include a first-first vertical power line (ELVDDL2a') and a first-second vertical power line (ELVDDL2b').

[0395] The first-first vertical power line (ELVDDL2a') can be connected to the first horizontal power line (ELVDDL1') through a contact hole in an area where the first sub-pixel circuit (SPC1') is provided.

[0396] The first-second vertical power line (ELVDDL2b') may be connected to the first horizontal power line (ELVDDL1') through a contact hole in an area where the second sub-pixel circuit (SPC2') is provided, and may be connected to the first horizontal power line (ELVDDL1') through another contact hole in an area where the third sub-pixel circuit (SPC3') is provided.

[0397] The anode bridge electrode (ABR') may include a first anode bridge electrode (ABRa'), a second anode bridge electrode (ABRb'), and a third anode bridge electrode (ABRc'). The anode bridge electrode (ABR') may be described in the same manner as the first anode bridge electrode (ABR) described with reference to FIG. 14. Therefore, description of overlapping content is omitted.

[0398] Fig. 25 is a cross-sectional view taken along line XC-XC' of Fig. 24. Fig. 26 is a cross-sectional view taken along line XD-XD' of Fig. 24.

[0399] Referring to FIGS. 25 and 26, the first light emission control signal line (EML1') may be connected to the first light emission control gate electrode (GPa'), and the second light emission control signal line (EML2') may be connected to the second light emission control gate electrode (GPb').

[0400] The first light emission control signal line (EML1') may not be connected to the second light emission control gate electrode (GPb'), and the second light emission control signal line (EML2') may not be connected to the first light emission control gate electrode (GPa').

[0401] Accordingly, in order to match the optimal driving characteristics of the first to third sub-pixels (SP1, SP2, SP3), it is possible to transmit a first light emission control signal (EM1) to the first sub-pixel circuit (SPC1') through a first light emission control signal line (EML1'), and to transmit a second light emission control signal (EM2) different from the first light emission control signal (EM1) to the second and third sub-pixel circuits (SPC2', SPC3') through a second light emission control signal line (EML2').

[0402] FIG. 27 is a plan view illustrating one embodiment of one of the pixels included in the display panel of FIG. 3.

[0403] Referring to FIG. 27, a pixel (PXL) may include first to third sub-pixels (SP1, SP2, SP3). The first to third sub-pixels (SP1, SP2, SP3) may be arranged in a first direction (DR1). However, the arrangement of the first to third sub-pixels (SP1, SP2, SP3) is not limited thereto. The first to third sub-pixels (SP1, SP2, SP3) may be arranged in various ways according to embodiments. For example, the first to third sub-pixels (SP1, SP2, SP3) may be arranged in a zigzag pattern.

[0404] First to third anode electrodes (AE1, AE2, AE3) may be respectively disposed in the first to third sub-pixels (SP1, SP2, SP3). The first anode electrode (AE1) may be connected to the first sub-pixel circuit (SPC1) (or SPC1') of the first sub-pixel (SP1). The second anode electrode (AE2) may be connected to the second sub-pixel circuit (SPC2) (or SPC2') of the second sub-pixel (SP2). The third anode electrode (AE3) may be connected to the third sub-pixel circuit (SPC3) (or SPC3') of the third sub-pixel (SP3).

[0405] The cathode electrode (CE) may be spaced apart from the first to third anode electrodes (AE1, AE2, AE3). In one embodiment, the cathode electrode (CE) may be arranged on the same layer as the first to third anode electrodes (AE1, AE2, AE3). In this case, the cathode electrode (CE) may be spaced apart from the first to third anode electrodes (AE1, AE2, AE3) in the second direction (DR2).

[0406] In one embodiment, the cathode electrode (CE) extends in the first direction (DR1) and can be used as a common electrode for the pixel (PXL) and other pixels adjacent to the pixel (PXL). Although not shown, the cathode electrode (CE) extends in the second direction (DR2) as well as the first direction (DR1) and can be used as a common electrode for all of the sub-pixels (SP) of FIG. 3. In this way, the cathode electrode (CE) can have various shapes.

[0407] First to third light-emitting elements (LD1, LD2, LD3) may be disposed on first to third anode electrodes (AE1, AE2, AE3) and a cathode electrode (CE). The first light-emitting element (LD1) may be electrically connected to the first anode electrode (AE1) and the cathode electrode (CE). The first light-emitting element (LD1) may be provided as a light-emitting element connected to the first sub-pixel circuit (SPC1) (or SPC1') of the first sub-pixel (SP1). The second light-emitting element (LD2) may be electrically connected to the second anode electrode (AE2) and the cathode electrode (CE). The second light-emitting element (LD2) may be provided as a light-emitting element connected to the second sub-pixel circuit (SPC2) (or SPC2') of the second sub-pixel (SP2). The third light-emitting element (LD3) may be electrically connected to the third anode electrode (AE3) and the cathode electrode (CE). The third light-emitting element (LD3) may be provided as a light-emitting element connected to the third sub-pixel circuit (SPC3) (or SPC3') of the third sub-pixel (SP3).

[0408] The first to third light-emitting elements (LD1, LD2, LD3) may be inorganic light-emitting diodes including inorganic light-emitting materials.

[0409] Fig. 28 is a cross-sectional view taken along line I1-I1' of Fig. 27. Fig. 28 is a cross-sectional view for explaining the first sub-pixel.

[0410] Referring to FIGS. 27 and 28, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0411] The pixel circuit layer (PCL) may be described in the same manner as described with reference to FIGS. 6 to 26. For example, the pixel circuit layer (PCL) may include various components constituting the first sub-pixel circuit (SPC1) (or SPC1').

[0412] The display element layer (DPL) may include a first anode electrode (AE1), a cathode electrode (CE), a bank layer (BNK), a first-first reflective electrode (RFE1a), a first-second reflective electrode (RFE2a), a first light-emitting element (LD1), an overcoat layer (OCL), and a passivation layer (PSV).

[0413] The first anode electrode (AE1) may be disposed on the pixel circuit layer (PCL). The first anode electrode (AE1) may be connected to the first anode bridge electrode (ABRa) (or ABRa') through a contact hole.

[0414] The cathode electrode (CE) may be disposed on the pixel circuit layer (PCL). The cathode electrode (CE) may be spaced apart from the first anode electrode (AE1). The cathode electrode (CE) may transmit a second power supply voltage (ELVSS).

[0415] A bank layer (BNK) may be disposed on a first anode electrode (AE1) and a cathode electrode (CE). The bank layer (BNK) may have a first pixel opening (OP1) exposing portions of the first anode electrode (AE1) and the cathode electrode (CE). A first light-emitting element (LD1) may be disposed within the first pixel opening (OP1) of the bank layer (BNK). In this way, the bank layer (BNK) may be provided as a pixel defining film that defines an area in which the first light-emitting element (LD1) is positioned.

[0416] The bank layer (BNK) may be configured to include a light-blocking material, thereby preventing light mixing between adjacent sub-pixels. In some embodiments, the bank layer (BNK) may include an organic material. For example, the bank layer (BNK) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0417] A first-first reflective electrode (RFE1a) may be disposed on an exposed portion of a first anode electrode (AE1) and a side surface of a bank layer (BNK) adjacent thereto. A first-second reflective electrode (RFE2a) may be disposed on an exposed portion of a cathode electrode (CE) and a side surface of a bank layer (BNK) adjacent thereto. The first-first reflective electrode (RFE1a) and the first-second reflective electrode (RFE2a) may include conductive materials suitable for reflecting light. Accordingly, the light emission efficiency of the first light-emitting element (LD1) may be improved. In one embodiment, the first-first reflective electrode (RFE1a) and the first-second reflective electrode (RFE2a) may include aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and / or an alloy of two or more materials selected therefrom. However, the present disclosure is not limited thereto.

[0418] The first light-emitting element (LD1) may include a first-first semiconductor layer (10a), a first active layer (MQW1), a first-second semiconductor layer (20a), a first insulating film (30a), a first-first bonding electrode (BDE1a), and a first-second bonding electrode (BDE2a).

[0419] The first-first semiconductor layer (10a) may be configured to provide holes. The first-first semiconductor layer (10a) may have a first polarity. For example, the first-first semiconductor layer (10a) may include at least one p-type semiconductor layer. For example, the first-first semiconductor layer (10a) may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and / or indium nitride (InN), and may be a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or the like. However, the material constituting the first-first semiconductor layer (10a) is not limited thereto, and various other materials may constituting the first-first semiconductor layer (10a). In one embodiment of the present disclosure, the first-first semiconductor layer (10a) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or p-type dopant).

[0420] The first active layer (MQW1) may be disposed on the 1-1 semiconductor layer (10a). The first active layer (MQW1) may be interposed between the 1-1 semiconductor layer (10a) and the 1-2 semiconductor layer (20a) to provide a region where electrons and holes recombine. As electrons and holes recombine in the first active layer (MQW1), they transition to a lower energy level, and light having a corresponding wavelength may be generated. The first active layer (MQW1) may be formed in a single or multiple quantum well structure. When the first active layer (MQW1) is formed in a multiple quantum well structure, units including a barrier layer, a strain reinforcement layer, and a well layer may be repeatedly stacked to form the first active layer (MQW1). However, the first active layer (MQW1) is not limited to the above-described structure.

[0421] In one embodiment, the first active layer (MQW1) may be configured to generate light of a first color. In this case, the first active layer (MQW1) may include a material suitable for generating light of the first color. For example, the first active layer (MQW1) may be formed of Al Z1 A barrier layer composed of GaInP and Al Z2 It may include a well layer composed of GaInP (Z1>Z2).

[0422] The first-second semiconductor layer (20a) may be disposed on the first active layer (MQW1). The first-second semiconductor layer (20a) may be configured to provide electrons. The first-second semiconductor layer (20a) may have a second polarity different from the first polarity. For example, the first-second semiconductor layer (20a) may include at least one n-type semiconductor layer. For example, the first-second semiconductor layer (20a) may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and / or indium nitride (InN), and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the first-second semiconductor layer (20a) is not limited thereto, and various other materials may also constituting the first-second semiconductor layer (20a). In one embodiment of the present disclosure, the first-second semiconductor layer (20a) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or n-type dopant).

[0423] The first-first bonding electrode (BDE1a) may be bonded and fixed on the first anode electrode (AE1). The first-first bonding electrode (BDE1a) may be connected to the first-first semiconductor layer (10a) and the first-first reflective electrode (RFE1a). Through the first-first bonding electrode (BDE1a), the first-first semiconductor layer (10a) and the first anode electrode (AE1) may be electrically connected. In one embodiment, the first-first bonding electrode (BDE1a) may include a eutectic metal.

[0424] The first-second bonding electrode (BDE2a) may be bonded and fixed on the cathode electrode (CE). The first-second bonding electrode (BDE2a) may be connected to the first-second semiconductor layer (20a) and the first-second reflective electrode (RFE2a). Through the first-second bonding electrode (BDE2a), the first-second semiconductor layer (20a) and the cathode electrode (CE) may be electrically connected. In one embodiment, the first-second bonding electrode (BDE2a) may include a eutectic metal.

[0425] The first insulating film (30a) can cover at least a portion of the outer circumferential surface of the light-emitting laminate composed of the sequentially stacked first semiconductor layer (10a), the first active layer (MQW1), and the first-second semiconductor layer (20a). The first insulating film (30a) is interposed between the first-second bonding electrode (BDE2a) and the first active layer (MQW1), and between the first-second bonding electrode (BDE2a) and the first-first semiconductor layer (10a), thereby preventing an electrical short circuit that may occur when the first-second bonding electrode (BDE2a) comes into contact with the first active layer (MQW1) and the first-first semiconductor layer (10a). The first insulating film (30a) can have a single-layer structure or a multi-layer structure including a transparent insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0426] An overcoat layer (OCL) may be disposed within a first pixel opening (OP1) in which a first-first reflective electrode (RFE1a), a first-second reflective electrode (RFE2a), and a first light-emitting element (LD1) are disposed. The overcoat layer (OCL) may fix the first light-emitting element (LD1) bonded to the first-first reflective electrode (RFE1a) and the first-second reflective electrode (RFE2a) so as not to move. In addition, the overcoat layer (OCL) may protect components disposed below the overcoat layer (OCL) from foreign substances such as dust and moisture. The overcoat layer (OCL) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) may include epoxy, but the present disclosure is not limited thereto.

[0427] A passivation layer (PSV) may be disposed on the bank layer (BNK) and the overcoat layer (OCL). The passivation layer (PSV) may protect components disposed under the passivation layer (PSV). In one embodiment, the passivation layer (PSV) may not be disposed on the upper surface of the first light-emitting element (LD1). The passivation layer (PSV) may include an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, a metal oxide such as silicon oxide, silicon nitride, silicon oxynitride, and / or aluminum oxide. The organic insulating layer may include, for example, an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and / or a benzocyclobutene resin.

[0428] The light function layer (LFL) may include a capping layer (CPL) and a color filter layer (CFL).

[0429] A capping layer (CPL) may be disposed on the display element layer (DPL). The capping layer (CPL) may serve to protect components under the capping layer (CPL), such as the first light-emitting element (LD1), from external moisture and humidity. In one embodiment, the capping layer (CPL) may include a metal oxide, such as silicon nitride, silicon oxide, silicon oxynitride, and / or aluminum oxide. However, the material of the capping layer (CPL) is not limited thereto.

[0430] The color filter layer (CFL) may include a first color filter (CF1) and light blocking patterns (LBP). The first color filter (CF1) may selectively transmit light in a desired wavelength range. For example, the first color filter (CF1) may selectively transmit light of a first color having a peak wavelength in a range of about 610 nm to about 650 nm. The light blocking patterns (LBP) may include at least one of various types of light-blocking materials.

[0431] Fig. 29 is a cross-sectional view taken along line I2-I2' of Fig. 27. Fig. 29 is a cross-sectional view for explaining the second sub-pixel.

[0432] In explaining the second sub-pixel (SP2), the explanation will be focused on the differences compared to the first sub-pixel (SP1) described with reference to FIG. 28, and the omitted parts will be replaced with the previous content.

[0433] Referring to FIG. 27 and FIG. 29, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0434] The pixel circuit layer (PCL) may be described in the same manner as described with reference to FIGS. 6 to 26. For example, the pixel circuit layer (PCL) may include various components constituting the second sub-pixel circuit (SPC2) (or SPC2').

[0435] The display element layer (DPL) may include a second anode electrode (AE2), a cathode electrode (CE), a bank layer (BNK), a second-first reflective electrode (RFE1b), a second-second reflective electrode (RFE2b), a second light-emitting element (LD2), an overcoat layer (OCL), and a passivation layer (PSV).

[0436] The second anode electrode (AE2) may be disposed on the pixel circuit layer (PCL). The second anode electrode (AE2) may be connected to the second anode bridge electrode (ABRb) (or, ABRb') through a contact hole. The second anode electrode (AE2) may be spaced apart from the cathode electrode (CE).

[0437] A bank layer (BNK) may be disposed on the second anode electrode (AE2) and the cathode electrode (CE). The bank layer (BNK) may have a second pixel opening (OP2) exposing portions of the second anode electrode (AE2) and the cathode electrode (CE). A second light-emitting element (LD2) may be disposed within the second pixel opening (OP2) of the bank layer (BNK).

[0438] A second-first reflective electrode (RFE1b) may be disposed on an exposed portion of the second anode electrode (AE2) and a side surface of the bank layer (BNK) adjacent thereto. A second-second reflective electrode (RFE2b) may be disposed on an exposed portion of the cathode electrode (CE) and a side surface of the bank layer (BNK) adjacent thereto. The second-first reflective electrode (RFE1b) and the second-second reflective electrode (RFE2b) may include a conductive material suitable for reflecting light.

[0439] The second light-emitting element (LD2) may include a second-first semiconductor layer (10b), a second active layer (MQW2), a second-second semiconductor layer (20b), a second insulating film (30b), a second-first bonding electrode (BDE1b), and a second-second bonding electrode (BDE2b).

[0440] The second-first semiconductor layer (10b) may be configured to provide holes. The second-first semiconductor layer (10b) may have a first polarity. For example, the second-first semiconductor layer (10b) may include at least one p-type semiconductor layer. In one embodiment of the present disclosure, the second-first semiconductor layer (10b) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or p-type dopant).

[0441] The second active layer (MQW2) may be disposed on the second-first semiconductor layer (10b). The second active layer (MQW2) may be interposed between the second-first semiconductor layer (10b) and the second-second semiconductor layer (20b) to provide a region where electrons and holes recombine. As electrons and holes recombine in the second active layer (MQW2), they transition to a lower energy level, and light having a corresponding wavelength may be generated. The second active layer (MQW2) may be formed as a single or multiple quantum well structure.

[0442] In one embodiment, the second active layer (MQW2) may be configured to generate light of a second color. In this case, the second active layer (MQW2) may include a material suitable for generating light of the second color. For example, the material constituting the second active layer (MQW2) may be different from the material constituting the first active layer (MQW1). For example, the second active layer (MQW2) may include a barrier layer composed of GaN and a well layer composed of InGaN.

[0443] The second-second semiconductor layer (20b) may be disposed on the second active layer (MQW2). The second-second semiconductor layer (20b) may be configured to provide electrons. The second-second semiconductor layer (20b) may have a second polarity. For example, the second-second semiconductor layer (20b) may include at least one n-type semiconductor layer. In one embodiment of the present disclosure, the second-second semiconductor layer (20b) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or n-type dopant).

[0444] The second-first bonding electrode (BDE1b) may be bonded and fixed on the second anode electrode (AE2). The second-first bonding electrode (BDE1b) may be connected to the second-first semiconductor layer (10b) and the second-first reflective electrode (RFE1b). Through the second-first bonding electrode (BDE1b), the second-first semiconductor layer (10b) and the second anode electrode (AE2) may be electrically connected. In one embodiment, the second-first bonding electrode (BDE1b) may include a eutectic metal.

[0445] The second-second bonding electrode (BDE2b) may be bonded and fixed on the cathode electrode (CE). The second-second bonding electrode (BDE2b) may be connected to the second-second semiconductor layer (20b) and the second-second reflective electrode (RFE2b). Through the second-second bonding electrode (BDE2b), the second-second semiconductor layer (20b) and the cathode electrode (CE) may be electrically connected. In one embodiment, the second-second bonding electrode (BDE2b) may include a eutectic metal.

[0446] The second insulating film (30b) can cover at least a portion of the outer circumferential surface of the light-emitting laminate composed of the sequentially stacked 2-1 semiconductor layer (10b), the second active layer (MQW2), and the 2-2 semiconductor layer (20b). The second insulating film (30b) is interposed between the 2-2 bonding electrode (BDE2b) and the second active layer (MQW2), and between the 2-2 bonding electrode (BDE2b) and the 2-1 semiconductor layer (10b), thereby preventing an electrical short circuit that may occur when the 2-2 bonding electrode (BDE2b) comes into contact with the second active layer (MQW2) and the 2-1 semiconductor layer (10b). The second insulating film (30b) can include a transparent insulating material, and can have a single-layer structure or a multi-layer structure.

[0447] An overcoat layer (OCL) may be disposed within a second pixel opening (OP2) in which a second-first reflective electrode (RFE1b), a second-second reflective electrode (RFE2b), and a second light-emitting element (LD2) are disposed. The overcoat layer (OCL) may fix the second light-emitting element (LD2) bonded to the second-first reflective electrode (RFE1b) and the second-second reflective electrode (RFE2b) so as not to move.

[0448] A passivation layer (PSV) may be placed on the bank layer (BNK) and the overcoat layer (OCL).

[0449] The light function layer (LFL) may include a capping layer (CPL) and a color filter layer (CFL).

[0450] A capping layer (CPL) may be disposed on the display element layer (DPL). The capping layer (CPL) may serve to protect components under the capping layer (CPL), such as the second light-emitting element (LD2), from external moisture and humidity.

[0451] The color filter layer (CFL) may include a second color filter (CF2) and light blocking patterns (LBP). The second color filter (CF2) may selectively transmit light within a desired wavelength range. For example, the second color filter (CF2) may selectively transmit light of a second color having a peak wavelength in a range of about 500 nm to about 540 nm.

[0452] Fig. 30 is a cross-sectional view taken along line I3-I3' of Fig. 27. Fig. 30 is a cross-sectional view for explaining the third sub-pixel.

[0453] In explaining the third sub-pixel (SP3), the explanation will be focused on the differences compared to the first sub-pixel (SP1) described with reference to FIG. 28, and the omitted parts will be replaced with the previous content.

[0454] Referring to FIG. 27 and FIG. 30, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0455] The pixel circuit layer (PCL) may be described in the same manner as described with reference to FIGS. 6 to 26. For example, the pixel circuit layer (PCL) may include various components constituting the third sub-pixel circuit (SPC3) (or SPC3').

[0456] The display element layer (DPL) may include a third anode electrode (AE3), a cathode electrode (CE), a bank layer (BNK), a third-first reflective electrode (RFE1c), a third-second reflective electrode (RFE2c), a third light-emitting element (LD3), an overcoat layer (OCL), and a passivation layer (PSV).

[0457] The third anode electrode (AE3) may be disposed on the pixel circuit layer (PCL). The third anode electrode (AE3) may be connected to the third anode bridge electrode (ABRc) (or ABRc') through a contact hole. The third anode electrode (AE3) may be spaced apart from the cathode electrode (CE).

[0458] A bank layer (BNK) may be disposed on the third anode electrode (AE3) and the cathode electrode (CE). The bank layer (BNK) may have a third pixel opening (OP3) exposing portions of the third anode electrode (AE3) and the cathode electrode (CE). A third light-emitting element (LD3) may be disposed within the third pixel opening (OP3) of the bank layer (BNK).

[0459] A third-first reflective electrode (RFE1c) may be disposed on an exposed portion of the third anode electrode (AE3) and a side surface of the bank layer (BNK) adjacent thereto. A third-second reflective electrode (RFE2c) may be disposed on an exposed portion of the cathode electrode (CE) and a side surface of the bank layer (BNK) adjacent thereto. The third-first reflective electrode (RFE1c) and the third-second reflective electrode (RFE2c) may include a conductive material suitable for reflecting light.

[0460] The third light-emitting element (LD3) may include a third-1 semiconductor layer (10c), a third active layer (MQW3), a third-2 semiconductor layer (20c), a third insulating film (30c), a third-1 bonding electrode (BDE1c), and a third-2 bonding electrode (BDE2c).

[0461] The third-first semiconductor layer (10c) may be configured to provide holes. The third-first semiconductor layer (10c) may have a first polarity. For example, the third-first semiconductor layer (10c) may include at least one p-type semiconductor layer. In one embodiment of the present disclosure, the third-first semiconductor layer (10c) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or p-type dopant).

[0462] The third active layer (MQW3) may be disposed on the third-first semiconductor layer (10c). The third active layer (MQW3) may be interposed between the third-first semiconductor layer (10c) and the third-second semiconductor layer (20c) to provide a region where electrons and holes recombine. As electrons and holes recombine in the third active layer (MQW3), they transition to a lower energy level, and light having a corresponding wavelength may be generated. The third active layer (MQW3) may be formed as a single or multiple quantum well structure.

[0463] In one embodiment, the third active layer (MQW3) may be configured to generate light of a third color. In this case, the third active layer (MQW3) may include a material suitable for generating light of the third color. For example, the material constituting the third active layer (MQW3) may be different from the material constituting the first active layer (MQW1). For example, the third active layer (MQW3) may include a barrier layer composed of GaN and a well layer composed of InGaN.

[0464] The third-second semiconductor layer (20c) may be disposed on the third active layer (MQW3). The third-second semiconductor layer (20c) may be configured to provide electrons. The third-second semiconductor layer (20c) may have a second polarity. For example, the third-second semiconductor layer (20c) may include at least one n-type semiconductor layer. In one embodiment of the present disclosure, the third-second semiconductor layer (20c) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or n-type dopant).

[0465] The third-first bonding electrode (BDE1c) may be bonded and fixed on the third anode electrode (AE3). The third-first bonding electrode (BDE1c) may be connected to the third-first semiconductor layer (10c) and the third-first reflective electrode (RFE1c). Through the third-first bonding electrode (BDE1c), the third-first semiconductor layer (10c) and the third anode electrode (AE3) may be electrically connected. In one embodiment, the third-first bonding electrode (BDE1c) may include a eutectic metal.

[0466] The third-second bonding electrode (BDE2c) may be bonded and fixed on the cathode electrode (CE). The third-second bonding electrode (BDE2c) may be connected to the third-second semiconductor layer (20c) and the third-second reflective electrode (RFE2c). Through the third-second bonding electrode (BDE2c), the third-second semiconductor layer (20c) and the cathode electrode (CE) may be electrically connected. In one embodiment, the third-second bonding electrode (BDE2c) may include a eutectic metal.

[0467] The third insulating film (30c) can cover at least a portion of the outer circumferential surface of the light-emitting laminate composed of the sequentially stacked third-first semiconductor layer (10c), the third active layer (MQW3), and the third-second semiconductor layer (20c). The third insulating film (30c) is interposed between the third-second bonding electrode (BDE2c) and the third active layer (MQW3), and between the third-second bonding electrode (BDE2c) and the third-first semiconductor layer (10c), thereby preventing an electrical short circuit that may occur when the third-second bonding electrode (BDE2c) comes into contact with the third active layer (MQW3) and the third-first semiconductor layer (10c). The third insulating film (30c) can include a transparent insulating material, and can have a single-layer structure or a multi-layer structure.

[0468] An overcoat layer (OCL) may be disposed within a third pixel opening (OP3) in which a third-first reflective electrode (RFE1c), a third-second reflective electrode (RFE2c), and a third light-emitting element (LD3) are disposed. The overcoat layer (OCL) may fix the third light-emitting element (LD3) bonded to the third-first reflective electrode (RFE1c) and the third-second reflective electrode (RFE2c) so as not to move.

[0469] A passivation layer (PSV) may be placed on the bank layer (BNK) and the overcoat layer (OCL).

[0470] The light function layer (LFL) may include a capping layer (CPL) and a color filter layer (CFL).

[0471] The capping layer (CPL) may be disposed on the display element layer (DPL). The capping layer (CPL) may serve to protect components under the capping layer (CPL), such as the third light-emitting element (LD3), from external moisture and humidity.

[0472] The color filter layer (CFL) may include a third color filter (CF3) and light blocking patterns (LBP). The third color filter (CF3) may selectively transmit light within a desired wavelength range. For example, the third color filter (CF3) may selectively transmit light of a third color having a peak wavelength of about 440 nm or more and about 480 nm or less.

[0473] Figure 31 is a cross-sectional view taken along line J1-J1' of Figure 27.

[0474] Below, description of content that overlaps with the content explained with reference to FIGS. 28 to 30 is omitted.

[0475] Referring to FIGS. 27 and 31, the color filter layer (CFL) may include first to third color filters (CF1, CF2, CF3) and light blocking patterns (LBP).

[0476] Light blocking patterns (LBP) may be arranged between the first to third color filters (CF1, CF2, CF3). It can be understood that the light emitting areas of the first to third sub-pixels (SP1, SP2, SP3) are defined by the light blocking patterns (LBP). For example, an area overlapping the light blocking patterns (LBP) may be a non-light emitting area, and an area not overlapping the light blocking patterns (LBP) may be a light emitting area.

[0477] In one embodiment, each of the light blocking patterns (LBP) may be provided in the form of a multilayer in which at least two of the first to third color filters (CF1, CF2, CF3) overlap. For example, each of the light blocking patterns (LBP) may be formed by overlapping the first to third color filters (CF1, CF2, CF3). For another example, the light blocking pattern between the first and second color filters (CF1, CF2) among the light blocking patterns (LBP) may be formed as a multilayer in which the first and second color filters (CF1, CF2) overlap, the light blocking pattern between the second and third color filters (CF2, CF3) among the light blocking patterns (LBP) may be formed as a multilayer in which the second and third color filters (CF2, CF3) overlap, and the light blocking pattern between the first color filter (CF1) among the light blocking patterns (LBP) and the third color filters (CF3) of neighboring sub-pixels may be formed as a multilayer in which the first and third color filters (CF1, CF3) overlap.

[0478] FIG. 32 is a timing diagram for explaining a driving method for driving pixels according to embodiments of the present disclosure.

[0479] Referring to FIG. 6 and FIG. 32, a first light emission control signal (EM1) at a turn-off level (high level) is applied to a first light emission control signal line (EML1), and a second light emission control signal (EM2) at a turn-off level (high level) is applied to a second light emission control signal line (EML2), whereby the fifth and sixth transistors (T5a, T5b, T5c, T6a, T6b, T6c) of the first to third sub-pixel circuits (SPC1, SPC2, SPC3) are turned off, and the pixel (PXL) is in a non-light emitting state.

[0480] Next, when a third gate signal (GI) of a turn-on level (high level) is applied to the third gate line (GIL), the fourth transistors (T4a, T4b, T4c) of the first to third sub-pixel circuits (SPC1, SPC2, SPC3) are turned on. Accordingly, an initialization voltage (VINT) is applied to the second nodes (N2a, N2b, N2c). The initialization voltage (VINT) may be a relatively low voltage and may on-bias the first transistors (T1a, T1b, T1c).

[0481] Next, when a second gate signal (GC) of a turn-on level (high level) is applied to the second gate line (GCL), the third transistors (T3a, T3b, T3c) of the first to third sub-pixel circuits (SPC1, SPC2, SPC3) are turned on. Then, when a first gate signal (GW) of a turn-on level (low level) is applied to the first gate line (GWL), the second transistors (T2a, T2b, T2c) of the first to third sub-pixel circuits (SPC1, SPC2, SPC3) are turned on.

[0482] Accordingly, the first data signal (DATA1) of the first data line (DL1) can be applied to the second node (N2a) of the first sub-pixel circuit (SPC1) through the second transistor (T2a), the first transistor (T1a), and the third transistor (T3a) which are turned on. At this time, the voltage of the second node (N2a) can be a first compensation voltage obtained by subtracting the threshold voltage of the first transistor (T1a) from the first data signal (DATA1), i.e., the first data voltage. The first storage capacitor (CSTa) can maintain the difference between the first power voltage (ELVDD) and the first compensation voltage.

[0483] In addition, the second data signal (DATA2) of the second data line (DL2) may be applied to the second node (N2b) of the second sub-pixel circuit (SPC2) through the second transistor (T2b), the first transistor (T1b), and the third transistor (T3b) that are turned on. At this time, the voltage of the second node (N2b) may be a second compensation voltage obtained by subtracting the threshold voltage of the first transistor (T1b) from the second data signal (DATA2), i.e., the second data voltage. The second storage capacitor (CSTb) may maintain the difference between the first power voltage (ELVDD) and the second compensation voltage.

[0484] In addition, a third data signal (DATA3) of a third data line (DL3) may be applied to a second node (N2c) of a third sub-pixel circuit (SPC3) through a second transistor (T2c), a first transistor (T1c), and a third transistor (T3c) that are turned on. At this time, the voltage of the second node (N2c) may be a third compensation voltage obtained by subtracting the threshold voltage of the first transistor (T1c) from the third data signal (DATA3), i.e., the third data voltage. The third storage capacitor (CSTc) may maintain a difference between the first power supply voltage (ELVDD) and the third compensation voltage.

[0485] Next, when a fourth gate signal (GB) of a turn-on level (low level) is applied to the fourth gate line (GBL), the seventh and eighth transistors (T7a, T7b, T7c, T8a, T8b, T8c) of the first to third sub-pixel circuits (SPC1, SPC2, SPC3) are turned on. As the seventh transistors (T7a, T7b, T7c) are turned on, an anode initialization voltage (VAINT) is applied to the first to third anode electrodes (AE1, AE2, AE3), and the first to third light-emitting elements (LD1, LD2, LD3) can be initialized with a charge amount corresponding to a voltage difference between the anode initialization voltage (VAINT) and the second power supply voltage (ELVSS). Additionally, as the eighth transistors (T8a, T8b, T8c) are turned on, the voltage of the first nodes (N1a, N1b, N1c) of the first to third sub-pixel circuits (SPC1, SPC2, SPC3) can be set to the bias voltage (VB).

[0486] Next, at a first time point (TP1), a second light-emitting control signal (EM2) of a turn-on level (low level) is applied to the second light-emitting control signal line (EML2), thereby turning on the fifth and sixth transistors (T5b, T5c, T6b, T6c) of the second and third sub-pixel circuits (SPC2, SPC3). Accordingly, a path of a driving current flowing from the first power voltage (ELVDD) to the second power voltage (ELVSS) via the fifth and sixth transistors (T5b, T5c, T6b, T6c) and the second and third light-emitting elements (LD2, LD3) is formed. Accordingly, the second light-emitting element (LD2) can emit light with a brightness corresponding to the amount of the second driving current, and the third light-emitting element (LD3) can emit light with a brightness corresponding to the amount of the third driving current.

[0487] Next, at a second time point (TP2) after the first time point (TP1), the first light-emitting control signal (EM1) at a turn-on level (low level) is applied to the first light-emitting control signal line (EML1), thereby turning on the fifth and sixth transistors (T5a, T6a) of the first sub-pixel circuit (SPC1). Accordingly, a path of a driving current flowing from the first power voltage (ELVDD) to the second power voltage (ELVSS) via the fifth and sixth transistors (T5a, T6a) and the first light-emitting element (LD1) is formed. Accordingly, the first light-emitting element (LD1) can emit light with a brightness corresponding to the amount of the first driving current.

[0488] Next, at a third time point (TP3) after the second time point (TP2), the first and second light-emitting control signals (EM1, EM2) at a turn-off level (high level) are applied to the first and second light-emitting control signal lines (EML1, EML2), thereby turning off the fifth and sixth transistors (T5a, T5b, T5c, T6a, T6b, T6c) of the first to third sub-pixel circuits (SPC1, SPC2, SPC3). Accordingly, light emission of the first to third light-emitting elements (LD1, LD2, LD3) can be terminated.

[0489] In one embodiment, a period during which a second light emission control signal (EM2) at a turn-on level (low level) is output to a second light emission control signal line (EML2) may be referred to as a first period (P1). A period during which a first light emission control signal (EM1) at a turn-on level (low level) is output to a first light emission control signal line (EML1) may be referred to as a second period (P2). For example, the first period (P1) may be a period from a first time point (TP1) to a third time point (TP3), and the second period (P2) may be a period from a second time point (TP2) to a third time point (TP3).

[0490] In one embodiment, the second period (P2) may be a period within the first period (P1), and the second period (P2) may be shorter than the first period (P1). In this case, the current density of the first driving current provided to the first light-emitting element (LD1) in the second period (P2) may be relatively large. For example, the current density of the first driving current provided to the first light-emitting element (LD1) in the second period (P2) may be greater than the current density of the second driving current provided to the second light-emitting element (LD2) in the first period (P1). For example, the current density of the first driving current provided to the first light-emitting element (LD1) in the second period (P2) may be greater than the current density of the third driving current provided to the third light-emitting element (LD3) in the first period (P1).

[0491] Figure 33 is a drawing for explaining the effects according to the pixel and its driving method of the present disclosure.

[0492] Referring to Fig. 33, first to third graphs (GRP1, GRP2, GRP3) are illustrated. In Fig. 33, the X-axis represents current density, and the Y-axis represents the relative value of luminous efficiency. Here, luminous efficiency refers to the external quantum efficiency (EQE) of the light-emitting element.

[0493] The first graph (GRP1) shows the current density dependence of the luminous efficiency of the first light-emitting element (LD1). The second graph (GRP2) shows the current density dependence of the luminous efficiency of the second light-emitting element (LD2). The third graph (GPR3) shows the current density dependence of the luminous efficiency of the third light-emitting element (LD3).

[0494] As described with reference to FIGS. 28 to 30, the first to third light-emitting elements (LD1, LD2, LD3) can be configured to generate light of different colors. The first light-emitting element (LD1) can be configured to be suitable for generating light of a first color. The second light-emitting element (LD2) can be configured to be suitable for generating light of a second color. The third light-emitting element (LD3) can be configured to be suitable for generating light of a third color. For example, the first light-emitting element (LD1) can include a first active layer (MQW1) that generates light of a first color, the second light-emitting element (LD2) can include a second active layer (MQW2) that generates light of a second color, and the third light-emitting element (LD3) can include a third active layer (MQW3) that generates light of a third color.

[0495] In this case, as shown in the first to third graphs (GRP1, GRP2, GRP3), the optimal current density for the first light-emitting element (LD1) to exhibit maximum luminous efficiency (or luminous efficiency adjacent thereto) may be different from the optimal current density for the second light-emitting element (LD2) to exhibit maximum luminous efficiency (or luminous efficiency adjacent thereto) and the optimal current density for the third light-emitting element (LD3) to exhibit maximum luminous efficiency (or luminous efficiency adjacent thereto).

[0496] The optimal current density for the first light-emitting element (LD1) to exhibit maximum luminous efficiency (or luminous efficiency close thereto) may be greater than the optimal current density for the second light-emitting element (LD2) to exhibit maximum luminous efficiency (or luminous efficiency close thereto).

[0497] The optimal current density for the first light-emitting element (LD1) to exhibit maximum luminous efficiency (or luminous efficiency close thereto) may be greater than the optimal current density for the third light-emitting element (LD3) to exhibit maximum luminous efficiency (or luminous efficiency close thereto).

[0498] The optimal current density for the second light-emitting element (LD2) to exhibit maximum luminous efficiency (or luminous efficiency close thereto) may be substantially similar to the optimal current density for the third light-emitting element (LD3) to exhibit maximum luminous efficiency (or luminous efficiency close thereto).

[0499] In the present disclosure, as described with reference to FIGS. 6 to 31, by providing the first light-emitting control signal line (EML1) (or EML1') and the second light-emitting control signal line (EML2) (or EML2') as separate components, a first driving current having a relatively high current density can be provided to the first light-emitting element (LD1), and second and third driving currents having relatively low current densities can be provided to the second and third light-emitting elements (LD2, LD3), respectively. Accordingly, the light-emitting efficiency of a pixel (PXL) including the first to third light-emitting elements (LD1, LD2, LD3) emitting light of different colors can be improved.

[0500] Figure 34 is a block diagram illustrating a display system according to one embodiment.

[0501] Referring to FIG. 34, the display system (1000) may include a processor (1100) and a display device (1200).

[0502] The processor (1100) can perform various tasks and calculations. In embodiments, the processor (1100) may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor (1100) can be connected to other components of the display system (1000) via a bus system and control them.

[0503] The processor (1100) can transmit image data (IMG) and a control signal (CTRL) to the display device (1200). The display device (1200) can display an image based on the image data (IMG) and the control signal (CTRL). The display device (1200) can be configured similarly to the display device (DD) described with reference to FIG. 1. In this case, the image data (IMG) and the control signal (CTRL) can be provided as the input image data (IMG) and the control signal (CTRL) of FIG. 1, respectively.

[0504] The display system (1000) may include a computing system that provides an image display function, such as a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer, a watch phone, an automotive display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. In addition, the display system (1000) may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0505] Figures 35 to 38 are perspective views illustrating application examples of the display system of Figure 34.

[0506] Referring to FIG. 35, the display system (1000) of FIG. 34 can be applied to a smart watch (2000) including a display unit (2100) and a strap unit (2200).

[0507] The smartwatch (2000) may be a wearable electronic device. For example, the smartwatch (2000) may have a structure in which a strap portion (2200) is attached to the user's wrist. Here, a display system (1000) and / or a display device (1200) may be applied to the display portion (2100), so that image data including time information may be provided to the user.

[0508] Referring to FIG. 36, the display system (1000) of FIG. 34 may be applied to an automotive display system (3000). Here, the automotive display system (3000) may include a computing system provided inside and / or outside a vehicle to provide image data.

[0509] For example, the display system (1000) and / or the display device (1200) may be applied to at least one of an infotainment panel (3100), a cluster (3200), a co-driver display (3300), a head-up display (3400), a side mirror display (3500), and a rear seat display (3600) provided in a vehicle.

[0510] Referring to FIG. 37, the display system (1000) of FIG. 34 can be applied to smart glasses (4000). The smart glasses (4000) may be a wearable electronic device that can be worn on a user's head. For example, the smart glasses (4000) may be a wearable device for augmented reality.

[0511] Smart glasses (4000) may include a frame (4100) and a lens unit (4200). The frame (4100) may include a housing (4110) that supports the lens unit (4200) and a leg unit (4120) for a user to wear. The leg unit (4120) is connected to the housing (4110) via a hinge and may be folded or unfolded relative to the housing (4110).

[0512] The frame (4100) may be equipped with a battery, a touch pad, a microphone, a camera, etc. In addition, the frame (4100) may be equipped with a projector that outputs light, a processor that controls light signals, etc.

[0513] The lens unit (4200) may include an optical member that transmits or reflects light. For example, the lens unit (4200) may include glass, transparent synthetic resin, or the like.

[0514] In order for the user's eyes to recognize visual information, the lens unit (4200) can reflect an image by an optical signal transmitted from the projector of the frame (4100) onto the rear surface of the lens unit (4200) (e.g., the surface facing the user's eyes). For example, the user can recognize visual information such as the time and date displayed on the lens unit (4200). At this time, the projector and / or the lens unit (4200) may be a type of display device. The display device (1200) may be applied to the projector and / or the lens unit (4200).

[0515] Referring to FIG. 38, the display system (1000) of FIG. 34 can be applied to a head-mounted display device (5000).

[0516] The head-mounted display device (5000) may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device (5000) may be a wearable device for virtual reality or mixed reality.

[0517] A head-mounted display device (5000) may include a head-mounted band (5100) and a display device storage case (5200). The head-mounted band (5100) may be connected to the display device storage case (5200). The head-mounted band (5100) may include horizontal bands and / or vertical bands for securing the head-mounted display device (5000) to a user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper portion of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band (5100) may be implemented in the form of eyeglass frames, helmets, etc.

[0518] The display device storage case (5200) can store the display system (1000) and / or the display device (1200).

[0519] Although the present disclosure has been described with reference to the above embodiments, it will be understood by those skilled in the art that various modifications and changes can be made to the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the claims below.

Claims

1. A 1-1 light-emitting control transistor including a first semiconductor pattern and a first light-emitting control gate electrode overlapping a 1-1 light-emitting control channel region of the first semiconductor pattern; A second-first light-emitting control transistor including a second semiconductor pattern and a second light-emitting control gate electrode overlapping a second-first light-emitting control channel region of the second semiconductor pattern; A first light emission control signal line that transmits a first light emission control signal and is connected to the first light emission control gate electrode; A second light emission control signal line that transmits a second light emission control signal and is connected to the second light emission control gate electrode; A first light-emitting element connected to the first-first light-emitting control transistor and emitting light of a first color; and A pixel connected to the second-1 light-emitting control transistor and including a second light-emitting element that emits light of a second color.

2. In paragraph 1, A first anode electrode connected to the second terminal of the first-first light-emitting control transistor; A second anode electrode connected to the second terminal of the second-1 light-emitting control transistor and spaced apart from the first anode electrode; and A pixel further comprising a cathode electrode spaced apart from the first and second anode electrodes.

3. In paragraph 2, The first light-emitting element is connected between the first anode electrode and the cathode electrode, The second light-emitting element is a pixel connected between the second anode electrode and the cathode electrode.

4. In paragraph 1, The first light-emitting element includes a first-first semiconductor layer having a first polarity, a first-second semiconductor layer having a second polarity, and a first active layer interposed between the first-first semiconductor layer and the first-second semiconductor layer. A pixel, wherein the second light-emitting element comprises a 2-1 semiconductor layer having the first polarity, a 2-2 semiconductor layer having the second polarity, and a second active layer interposed between the 2-1 semiconductor layer and the 2-2 semiconductor layer.

5. In paragraph 4, The material constituting the first active layer is different from the material constituting the second active layer.

6. In paragraph 1, A first-second light-emitting control transistor including the first semiconductor pattern and the first light-emitting control gate electrode overlapping the first-second light-emitting control channel region of the first semiconductor pattern; and A pixel further comprising a second-second light-emitting control transistor including the second semiconductor pattern and the second light-emitting control gate electrode overlapping the second-second light-emitting control channel region of the second semiconductor pattern.

7. In paragraph 6, A first driving transistor connected between a first terminal of the first-first light-emitting control transistor and a second terminal of the first-second light-emitting control transistor, the first driving transistor including a first driving gate electrode overlapping the first semiconductor pattern and the first driving channel region of the first semiconductor pattern; and A pixel further comprising a second driving transistor connected between a first terminal of the second-1 light-emitting control transistor and a second terminal of the second-2 light-emitting control transistor, the second driving transistor including a second driving gate electrode overlapping the second semiconductor pattern and the second driving channel region of the second semiconductor pattern.

8. In paragraph 7, The channel length of the first driving channel region is smaller than the channel length of the second driving channel region, A pixel in which the channel width of the first driving channel region is greater than the channel width of the second driving channel region.

9. In paragraph 8, A first data line transmitting a first data signal; A second data line transmitting a second data signal; A first data write transistor connected between a first terminal of the first driving transistor and the first data line, the first data write gate electrode overlapping the first semiconductor pattern and the first data write channel region of the first semiconductor pattern; and A pixel further comprising a second data write transistor connected between the first terminal of the second driving transistor and the second data line, the second data write gate electrode overlapping the second semiconductor pattern and the second data write channel region of the second semiconductor pattern.

10. In paragraph 6, A pixel in which the channel width of the 1-1 light-emitting control channel region of the first semiconductor pattern is greater than the channel width of the 2-1 light-emitting control channel region of the second semiconductor pattern.

11. In paragraph 10, A pixel, wherein the resistance of the conductive regions adjacent to the 1-1 light emitting control channel region of the first semiconductor pattern is smaller than the resistance of the conductive regions adjacent to the 2-1 light emitting control channel region of the second semiconductor pattern.

12. In paragraph 10, A pixel in which the channel width of the 1-2 light emitting control channel region of the first semiconductor pattern is greater than the channel width of the 2-2 light emitting control channel region of the second semiconductor pattern.

13. In paragraph 12, A pixel, wherein the resistance of the conductive regions adjacent to the 1-2 light emitting control channel region of the first semiconductor pattern is smaller than the resistance of the conductive regions adjacent to the 2-2 light emitting control channel region of the second semiconductor pattern.

14. In paragraph 1, A pixel in which the first light emission control signal line and the second light emission control signal line are arranged on the same layer.

15. In paragraph 1, A pixel, wherein each of the first and second light emitting control signal lines overlaps the first and second semiconductor patterns.

16. In paragraph 1, A third-first light-emitting control transistor including a third semiconductor pattern and a third light-emitting control gate electrode overlapping with a third-first light-emitting control channel region of the third semiconductor pattern; and Further comprising a third light-emitting element connected to the above-mentioned 3-1 light-emitting control transistor and emitting light of a third color, The pixel, wherein the third light emission control gate electrode is connected to the second light emission control signal line.

17. In paragraph 16, A pixel in which the third light-emitting control gate electrode is formed integrally with the second light-emitting control gate electrode.

18. In paragraph 17, The second semiconductor pattern and the third semiconductor pattern have a planar shape that is symmetrical to each other, the pixel.

19. In paragraph 16, The light of the above first color is red color light having a peak wavelength of 610 nm or more and 650 nm or less, The above second color light is green color light having a peak wavelength of 500 nm or more and 540 nm or less, The light of the third color is a pixel that is blue color light having a peak wavelength of 440 nm or more and 480 nm or less.

20. As a method of driving pixels, The above pixel is, A first-first light-emitting control transistor including a first semiconductor pattern and a first light-emitting control gate electrode overlapping a first-first light-emitting control channel region of the first semiconductor pattern; A second-first light-emitting control transistor including a second semiconductor pattern and a second light-emitting control gate electrode overlapping a second-first light-emitting control channel region of the second semiconductor pattern; A first light emission control signal line that transmits a first light emission control signal and is connected to the first light emission control gate electrode; A second light emission control signal line that transmits a second light emission control signal and is connected to the second light emission control gate electrode; A first light-emitting element connected to the first-first light-emitting control transistor and emitting light of a first color; and A second light-emitting element connected to the second-1 light-emitting control transistor and emitting light of a second color, The above driving method is, A step of outputting the second light emitting control signal at a turn-on level to the second light emitting control signal line during a first period, and outputting the first light emitting control signal at a turn-on level to the first light emitting control signal line during a second period within the first period, A method of driving a pixel, wherein the second period is shorter than the first period.

21. A display panel comprising: a plurality of pixels; and one of the plurality of pixels: A first-first light-emitting control transistor including a first semiconductor pattern and a first light-emitting control gate electrode overlapping a first-first light-emitting control channel region of the first semiconductor pattern; A second-first light-emitting control transistor including a second semiconductor pattern and a second light-emitting control gate electrode overlapping a second-first light-emitting control channel region of the second semiconductor pattern; A first light emission control signal line that transmits a first light emission control signal and is connected to the first light emission control gate electrode; A second light emission control signal line that transmits a second light emission control signal and is connected to the second light emission control gate electrode; A first light-emitting element connected to the first-first light-emitting control transistor and emitting light of a first color; and A second light-emitting element connected to the second-1 light-emitting control transistor and emitting light of a second color, An electronic device wherein the first and second light emitting control signal lines overlap the first and second semiconductor patterns, respectively.

22. In claim 21, the electronic device comprises a smart watch, a mobile phone, a smart phone, a portable computer, a tablet computer, a watch phone, an automotive display, smart glasses, a portable multimedia player, a navigation device, an ultra mobile personal computer, a head-mounted display device, a virtual reality device, a mixed reality device, or an augmented reality device.

Images