Display device and electronic device

Abstract

This display device comprises a display element layer disposed on a substrate, wherein the display element layer includes: an anode electrode and a cathode electrode on the substrate; an overcoat pattern disposed on the anode electrode; a light-emitting element disposed on the overcoat pattern and including a first end adjacent to the overcoat pattern and a second end spaced apart from the first end; a first transparent electrode layer disposed on the overcoat pattern and electrically connecting the anode electrode and the first end of the light-emitting element; at least one insulating layer disposed on the first transparent electrode layer and the cathode electrode; and a second transparent electrode layer disposed on the at least one insulating layer and electrically connecting the cathode electrode and the second end of the light-emitting element.

Description

Display devices and electronic devices

[0001] The present invention relates to a display device and an electronic device.

[0002] Display devices are becoming increasingly important with the advancement of multimedia. In response, the use of display devices such as liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs), and inorganic light-emitting diodes (ILDs) is increasing. In particular, research is actively underway on micro LEDs, which offer faster response times and higher brightness compared to conventional LEDs.

[0003] The above-described content is only intended to help understand the background technology for the technical ideas of the present invention, and therefore cannot be understood as content corresponding to prior art known to those skilled in the art in the technical field of the present invention.

[0004] Embodiments of the present invention provide a display device with improved display quality and a method for manufacturing the same. For example, the display device can improve display quality by increasing contact stability by increasing the contact area between a light-emitting element and a transparent electrode layer connected to an anode electrode.

[0005] A display device according to an embodiment of the present invention includes a substrate extending in a first direction and a second direction intersecting the first direction, a display element layer disposed on the substrate in a third direction intersecting the first and second directions, the display element layer including an anode electrode and a cathode electrode spaced apart from each other in the second direction on the substrate, an overcoat pattern disposed on the anode electrode, a light-emitting element disposed on the overcoat pattern and including a first end adjacent to the overcoat pattern and a second end spaced apart from the first end in the third direction, a first transparent electrode layer disposed on the overcoat pattern and electrically connecting the anode electrode and the first end of the light-emitting element, at least one insulating layer disposed on the first transparent electrode layer and the cathode electrode, and a second transparent electrode layer disposed on the at least one insulating layer and electrically connecting the cathode electrode and the second end of the light-emitting element.

[0006] The second transparent electrode layer may be in contact with the second end of the light-emitting element and may be electrically connected to the cathode electrode through a contact hole penetrating the at least one insulating layer.

[0007] The above contact hole can overlap the above cathode electrode.

[0008] The contact hole may be spaced apart from the light-emitting element in the second direction without overlapping with the light-emitting element.

[0009] The first transparent electrode layer may be in contact with the overcoat pattern and the first end of the light-emitting element, and the second transparent electrode layer may be in contact with the second end of the light-emitting element.

[0010] The above overcoat pattern may be disposed between the anode electrode and the first end of the light-emitting element.

[0011] The first end of the light emitting element can be in contact with the overcoat pattern.

[0012] The at least one insulating layer may include a first insulating layer disposed on the anode electrode and the cathode electrode, respectively, and a second insulating layer disposed on the first insulating layer.

[0013] The above first insulating layer can be in contact with the above first transparent electrode layer.

[0014] The light emitting element has a side surface disposed between the first end and the second end, and the second insulating layer can be in contact with the side surface of the light emitting element.

[0015] The first and second transparent electrode layers are spaced apart from each other in the third direction with at least one insulating layer therebetween, and may include the same material.

[0016] A bank further comprising openings disposed on the anode electrode and the cathode electrode, the openings exposing a portion of each of the anode electrode and the cathode electrode, wherein a portion of the anode electrode and the first transparent electrode layer can be in contact with each other at any one of the openings of the bank.

[0017] According to another embodiment of the present invention, a display device includes a substrate extending in a first direction and a second direction intersecting the first direction, a display element layer disposed on the substrate in a third direction intersecting the first and second directions, the display element layer including an anode electrode disposed on the substrate, an overcoat pattern disposed on the anode electrode, a light-emitting element disposed on the overcoat pattern, the light-emitting element including a first end adjacent to the overcoat pattern and a second end spaced apart from the first end in the third direction, a first transparent electrode layer disposed on the overcoat pattern and electrically connecting the anode electrode and the first end of the light-emitting element, at least one insulating layer disposed on the first transparent electrode layer, and a cathode electrode disposed on the at least one insulating layer and connected to the second end of the light-emitting element, wherein the first transparent electrode layer is in contact with the first end of the light-emitting element.

[0018] The first transparent electrode layer can be in contact with the first end of the light-emitting element and the overcoat pattern.

[0019] The above overcoat pattern may be disposed between the anode electrode and the first end of the light-emitting element.

[0020] The first end of the light emitting element can be in contact with the overcoat pattern.

[0021] An electronic device according to an embodiment of the present invention includes a display device and a substrate, wherein the display device includes a display element layer according to claim 1, and the display element layer is disposed on the substrate.

[0022] The electronic device may be at least one of a smartwatch, a mobile phone, a smart phone, a portable computer, a tablet PC, a watch phone, an automotive display, a smart glass, a PMP, a navigation device, an UMPC, a head-mounted display device, a virtual reality device, a mixed reality geek device, and an augmented reality device.

[0023] According to embodiments of the present invention, a display device with improved display quality and a method for manufacturing the same are provided.

[0024] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in the present specification.

[0025] Figure 1 is a block diagram showing an embodiment of a display device.

[0026] FIG. 2 is a block diagram showing an embodiment of one of the sub-pixels of FIG. 1.

[0027] FIG. 3 is a plan view showing an embodiment of the display panel of FIG. 1.

[0028] Fig. 4 is a cross-sectional view showing an embodiment of the display panel of Fig. 3.

[0029] FIG. 5 is a cross-sectional view showing another embodiment of the display panel of FIG. 3.

[0030] FIG. 6 is a plan view showing an embodiment of one of the pixels of FIG. 3.

[0031] Figure 7 is a cross-sectional view taken along lines Ⅰ to Ⅰ' of Figure 6.

[0032] Figure 8 is a cross-sectional view taken along line Ⅱ to Ⅱ' of Figure 6.

[0033] FIG. 9 is a plan view showing another embodiment of one of the pixels of FIG. 3.

[0034] FIG. 10 is a plan view showing another embodiment of one of the pixels of FIG. 3.

[0035] Fig. 11 is a cross-sectional view taken along line Ⅲ to Ⅲ' of Fig. 10.

[0036] Fig. 12 is a cross-sectional view taken along line Ⅳ to Ⅳ' of Fig. 10.

[0037] Figure 13 is a flowchart showing a method for manufacturing a display device according to an embodiment of the present invention.

[0038] Figures 14 to 23 are drawings showing an example of a method for manufacturing the display device of Figure 13.

[0039] Fig. 24 is a block diagram showing an embodiment of a display system.

[0040] Figures 25 to 28 are perspective views showing application examples of the display system of Figure 24.

[0041] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the portions necessary for understanding the operation of the present invention will be described, and the description of other portions will be omitted so as not to obscure the gist of the present invention. Furthermore, the present invention is not limited to the embodiments described herein and may be embodied in other forms. However, the embodiments described herein are provided to explain the technical idea of ​​the present invention in sufficient detail to enable those of ordinary skill in the art to easily practice it.

[0042] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case where it is "directly connected" but also the case where it is "indirectly connected" with another element in between. The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the present invention. Throughout the specification, when a part is said to "comprise" a certain element, this does not mean that other elements are excluded, but that other elements can be further included, unless specifically stated to the contrary. "At least one of X, Y, and Z", and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ). Here, "and / or" includes any combination of one or more of the configurations.

[0043] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Accordingly, a "first component" may refer to a "second component" within the scope disclosed herein.

[0044] Spatially relative terms, such as "below," "above," and the like, may be used for descriptive purposes to describe one element or feature in relation to other elements or features as depicted in the drawings. Spatially relative terms are intended to encompass different orientations during use, operation, and / or manufacturing, in addition to the orientation depicted in the drawings. For example, if a device depicted in the drawings is turned over, elements depicted as being positioned "below" other elements or features are now positioned "above" the other elements or features. Thus, in one embodiment, the term "below" may encompass both above and below. Furthermore, the device may be oriented in other orientations (e.g., rotated 90 degrees or in other directions), and the spatially relative terms used herein are to be interpreted accordingly.

[0045] Various embodiments are described with reference to drawings schematically illustrating ideal embodiments. Accordingly, it is to be understood that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes depicted, but rather to encompass, for example, variations in shapes resulting from manufacturing processes. Likewise, the shapes depicted in the drawings may not depict the actual shapes of areas of the device, and the present embodiments are not limited thereto.

[0046] Figure 1 is a block diagram showing an embodiment of a display device.

[0047] Referring to FIG. 1, the display device (DD) may include a display panel (DP), a gate driver (120), a data driver (130), a voltage generator (140), and a controller (150).

[0048] A display panel (DP) may include sub-pixels (SP). The sub-pixels (SP) may be connected to a gate driver (120) via first to m-th gate lines (GL1 to GLm). The sub-pixels (SP) may be connected to a data driver (130) via first to n-th data lines (DL1 to DLn).

[0049] The sub-pixels (SP) can generate light of two or more colors. For example, each of the sub-pixels (SP) can generate light of red, green, blue, cyan, magenta, yellow, etc.

[0050] Two or more sub-pixels among the sub-pixels (SP) can constitute one pixel (PXL). For example, the pixel (PXL) can include three sub-pixels as illustrated in FIG. 1. In this way, the pixel (PXL) can emit light of various colors and various luminances depending on the combination of light emitted from the sub-pixels included therein.

[0051] The gate driver (120) may be connected to the sub-pixels (SP) arranged in the row direction through the first to m-th gate lines (GL1 to GLm). The gate driver (120) may output gate signals to the first to m-th gate lines (GL1 to GLm) in response to a gate control signal (GCS). In embodiments, the gate control signal (GCS) may include a start signal indicating the start of each frame, a horizontal synchronization signal, and the like.

[0052] The gate driver (120) may be arranged on one side of the display panel (DP). However, embodiments are not limited thereto. For example, the gate driver (120) may be divided into two or more drivers that are physically and / or logically separated, and such drivers may be arranged on one side of the display panel (DP) and the other side of the display panel (DP) opposite to the one side. In this way, the gate driver (120) may be arranged around the display panel (DP) in various forms according to embodiments.

[0053] The data driver (130) can be connected to the sub-pixels (SP) arranged in the column direction through the first to nth data lines (DL1 to DLn). The data driver (130) can receive image data (DATA) and a data control signal (DCS) from the controller (150). The data driver (130) can operate in response to the data control signal (DCS). In embodiments, the data control signal (DCS) can include a source start signal, a source shift clock, a source output enable signal, etc.

[0054] The data driver (130) can receive voltages from the voltage generator (140). The data driver (130) can use the received voltages to apply data signals having grayscale voltages corresponding to image data (DATA) to the first to n-th data lines (DL1 to DLn). When a gate signal is applied to each of the first to m-th gate lines (GL1 to GLm), data signals corresponding to the image data (DATA) can be applied to the data lines (DL1 to DLn). Accordingly, the sub-pixels (SP) can generate light corresponding to the data signals, and the display panel (DP) can display an image.

[0055] In embodiments, the gate driver (120) and data driver (130) may include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0056] The voltage generator (140) can operate in response to a voltage control signal (VCS) from the controller (150). The voltage generator (140) can be configured to generate a plurality of voltages and provide the generated voltages to components of the display device (DD), such as the gate driver (120), the data driver (130), and the controller (150). The voltage generator (140) can generate a plurality of voltages by receiving an input voltage from the outside of the display device (DD) and regulating the received voltage.

[0057] A voltage generator (140) can generate a first power voltage and a second power voltage. The generated first and second power voltages can be provided to the sub-pixels (SP) through power lines (PL). In other embodiments, at least one of the first and second power voltages can be provided from outside the display device (DD).

[0058] In addition, the voltage generator (140) can provide various voltages and / or signals. For example, the voltage generator (140) can provide one or more initialization voltages applied to the sub-pixels (SP). For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels (SP), a predetermined reference voltage can be applied to the first to n-th data lines (DL1 to DLn), and the voltage generator (140) can generate the reference voltage and transmit it to the data driver (130). For example, during a display operation for displaying an image on the display panel (DP), common pixel control signals can be applied to the sub-pixels (SP), and the voltage generator (140) can generate the pixel control signals. In embodiments, the voltage generator (140) can provide pixel control signals to the sub-pixels (SP) through the pixel control lines (PXCL). Although FIG. 1 illustrates that the pixel control lines (PXCL) are connected between the voltage generator (140) and the display panel (DP), embodiments are not limited thereto. For example, the pixel control lines (PXCL) may be connected between the gate driver (120) and the display panel (DP). In this case, pixel control signals may be transmitted from the voltage generator (140) to the pixel control lines (PXCL) through the gate driver (120).

[0059] The controller (150) can control all operations of the display device (DD). The controller (150) can receive input image data (IMG) and a corresponding control signal (CTRL) from the outside. In response to the control signal (CTRL), the controller (150) can provide a gate control signal (GCS), a data control signal (DCS), and a voltage control signal (VCS).

[0060] The controller (150) can convert input image data (IMG) to be suitable for a display device (DD) or a display panel (DP) and output image data (DATA). In embodiments, the controller (150) can output image data (DATA) by aligning the input image data (IMG) to be suitable for sub-pixels (SP) in a row unit.

[0061] Two or more components of the data driver (130), the voltage generator (140), and the controller (150) may be mounted on a single integrated circuit. As illustrated in FIG. 1, the data driver (130), the voltage generator (140), and the controller (150) may be included in a driver integrated circuit (DIC). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver (130), the voltage generator (140), and the controller (150) may be provided as a separate component from the driver integrated circuit (DIC).

[0062] Fig. 2 is a block diagram showing an embodiment of one of the sub-pixels of Fig. 1. In Fig. 2, a sub-pixel (SPij) arranged in the ith row (i is an integer greater than or equal to 1 and less than or equal to m) and the jth column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels (SP) of Fig. 1 is exemplarily illustrated.

[0063] Referring to FIG. 2, a sub-pixel (SPij) may include a sub-pixel circuit (SPC) and a light-emitting element (LD).

[0064] A light emitting element (LD) may be connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first power supply voltage node (VDDN) may be connected to one of the power supply lines (PL) of FIG. 1 and may receive a first power supply voltage. The second power supply voltage node (VSSN) may be connected to another of the power supply lines (PL) of FIG. 1 and may receive a second power supply voltage. The first power supply voltage may have a higher voltage level than the second power supply voltage.

[0065] A light emitting element (LD) may be connected between an anode electrode (AE) and a cathode electrode (CE). The anode electrode (AE) may be connected to a first power voltage node (VDDN) through a sub-pixel circuit (SPC). For example, the anode electrode (AE) may be connected to the first power voltage node (VDDN) through one or more transistors included in the sub-pixel circuit (SPC). The cathode electrode (CE) may be connected to a second power voltage node (VSSN). The light emitting element (LD) may be configured to emit light according to a current flowing from the anode electrode (AE) to the cathode electrode (CE).

[0066] The sub-pixel circuit (SPC) may be connected to the i-th gate line (GLi) among the first to m-th gate lines (GL1 to GLm) of FIG. 1 and to the j-th data line (DLj) among the first to n-th data lines (DL1 to DLn) of FIG. 1. In response to a gate signal received through the i-th gate line (GLi), the sub-pixel circuit (SPC) may control the light-emitting element (LD) to emit light according to a data signal received through the j-th data line (DLj). In embodiments, the sub-pixel circuit (SPC) may be further connected to the pixel control lines (PXCL) of FIG. 1. In this case, the sub-pixel circuit (SPC) may further control the light-emitting element (LD) in response to pixel control signals received through the pixel control lines (PXCL).

[0067] For these operations, a sub-pixel circuit (SPC) may include circuit elements, such as transistors and one or more capacitors.

[0068] The transistors of the sub-pixel circuit (SPC) may include P-type transistors and / or N-type transistors. In embodiments, the transistors of the sub-pixel circuit (SPC) may include MOSFETs (Metal Oxide Silicon Field Effect Transistors). In embodiments, the transistors of the sub-pixel circuit (SPC) may include an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0069] FIG. 3 is a plan view showing an embodiment of the display panel of FIG. 1.

[0070] Referring to FIG. 3, a display panel (DP) may include a display area (DA) and a non-display area (NDA). The display panel (DP) may display an image through the display area (DA). The non-display area (NDA) may be positioned around the display area (DA).

[0071] A display panel (DP) may include sub-pixels (SP) in a display area (DA). The sub-pixels (SP) may be arranged along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). For example, the sub-pixels (SP) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). As another example, the sub-pixels (SP) may be arranged in a zigzag form along the first direction (DR1) and the second direction (DR2). The arrangement of the sub-pixels (SP) may vary depending on the embodiments. The first direction (DR1) may be a row direction, and the second direction (DR2) may be a column direction.

[0072] Among a plurality of sub-pixels (SP), two or more sub-pixels can constitute one pixel (PXL). In FIG. 3, the pixel (PXL) is illustrated as including three sub-pixels (SP1 to SP3), but embodiments are not limited thereto. For example, the pixel (PXL) may include two sub-pixels. Hereinafter, for convenience of explanation, it is assumed that the pixel (PXL) includes first to third sub-pixels (SP1 to SP3).

[0073] Each of the first to third sub-pixels (SP1 to SP3) can generate light of one of various colors, such as red, green, blue, cyan, magenta, yellow, etc. Hereinafter, for clarity and concise explanation, it is assumed that the first sub-pixel (SP1) is configured to generate red color light, the second sub-pixel (SP2) is configured to generate green color light, and the third sub-pixel (SP3) generates blue color light.

[0074] Each of the first to third sub-pixels (SP1 to SP3) may include at least one light-emitting element configured to generate light. In embodiments, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate light of the same color. For example, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate blue light. In other embodiments, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate light of different colors. For example, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate red light, green light, and blue light, respectively.

[0075] As a display panel (DP), a self-luminous display panel such as a light-emitting diode display panel (LED display panel) that uses micro-scale or nano-scale light-emitting diodes as light-emitting elements, or an organic light-emitting display panel (OLED panel) that uses organic light-emitting diodes as light-emitting elements, can be used.

[0076] Components for controlling sub-pixels (SP) may be arranged in the non-display area (NDA). Wires connected to the sub-pixels (SP), for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), power lines (PL), and pixel control lines (PXCL) of FIG. 1, may be arranged in the non-display area (NDA).

[0077] At least one of the gate driver (120), the data driver (130), the voltage generator (140), and the controller (150) of FIG. 1 may be disposed in a non-display area (NDA) of the display panel (DP). In embodiments, the gate driver (120) may be disposed in the non-display area (NDA). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be implemented as a driver integrated circuit (DIC) of FIG. 1 that is separate from the display panel (DP), and the driver integrated circuit (DIC) may be connected to wires disposed in the non-display area (NDA). In other embodiments, the gate driver (120) may be implemented as a single integrated circuit that is separate from the display panel (DP) together with the data driver (130), the voltage generator (140), and the controller (150).

[0078] In embodiments, the display area (DA) may have various shapes. The display area (DA) may have the shape of a closed loop including straight and / or curved edges. For example, the display area (DA) may have shapes such as a polygon, a circle, a semicircle, or an ellipse.

[0079] In some embodiments, the display panel (DP) may have a flat display surface. In other embodiments, the display panel (DP) may have an at least partially rounded display surface. In some embodiments, the display panel (DP) may be bendable, foldable, or rollable. In such cases, the display panel (DP) and / or the substrate of the display panel (DP) may include materials having flexible properties.

[0080] Fig. 4 is a cross-sectional view showing an embodiment of the display panel of Fig. 3.

[0081] Referring to FIG. 4, the display panel (DP) may include a substrate (SUB), and a pixel circuit layer (PCL), a display element layer (DPL), and a light functional layer (LFL) sequentially laminated in a third direction (DR3) intersecting the first and second directions (DR1, DR2) on the substrate (SUB).

[0082] The substrate (SUB) may be made of an insulating material such as glass or resin. For example, the substrate (SUB) may include a glass substrate. As another example, the substrate (SUB) may include a polyimide (PI) substrate. As yet another example, the substrate (SUB) may include a silicon wafer substrate formed using a semiconductor process.

[0083] In embodiments, the substrate (SUB) may be made of a flexible material that is bendable or foldable, and may have a single-layer structure or a multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0084] A pixel circuit layer (PCL) may be arranged on a substrate (SUB). The pixel circuit layer (PCL) may include insulating layers and semiconductor patterns and conductive patterns arranged between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may function as circuit elements, wirings, etc.

[0085] The circuit elements of the pixel circuit layer (PCL) may include a sub-pixel circuit (SPC, see FIG. 2) of each of the sub-pixels (SP) of FIG. 3. In other words, the circuit elements of the pixel circuit layer (PCL) may be provided as transistors and one or more capacitors of the sub-pixel circuit (SPC).

[0086] The wiring of the pixel circuit layer (PCL) may include wiring connected to sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may include various signal lines and / or voltage lines necessary to drive the display element layer (DPL).

[0087] A display element layer (DPL) may be arranged on a pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements of sub-pixels (SP).

[0088] A light-functional layer (LFL) may be disposed on a display element layer (DPL). The light-functional layer (LFL) may include light-converting patterns having color-converting particles and / or scattering particles. For example, the color-converting particles may include quantum dots. The quantum dots may change the wavelength (or color) of light emitted from the display element layer (DPL). The light-functional layer (LFL) may further include light-scattering patterns having scattering particles. In embodiments, the light-converting patterns and the light-scattering patterns may be omitted.

[0089] The light function layer (LFL) may further include a color filter layer including color filters. The color filter may selectively transmit light of a specific wavelength (or color). In embodiments, the color filter layer may be omitted.

[0090] A window may be provided on a light-functional layer (LFL) to protect an exposed surface (or upper surface) of a display panel (DP). The window may protect the display panel (DP) from external impact. The window may be bonded to the light-functional layer (LFL) via an optically transparent adhesive (or bonding) member. The window may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. This multilayer structure may be formed through a continuous process or an bonding process using an adhesive layer. All or a portion of the window may be flexible.

[0091] FIG. 5 is a cross-sectional view showing another embodiment of the display panel of FIG. 3.

[0092] Referring to FIG. 5, the display panel (DP') may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), an input sensing layer (ISL), and a light function layer (LFL). The substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) are configured similarly to the substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) described with reference to FIG. 4, respectively. Hereinafter, redundant descriptions are omitted.

[0093] An input sensing layer (ISL) can detect user input on the upper surface (or display surface) of a display panel (DP'). The input sensing layer (ISL) may include configurations suitable for detecting external objects, such as a user's hand or pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0094] FIG. 6 is a plan view showing an embodiment of one of the pixels of FIG. 3.

[0095] Referring to FIG. 6, a pixel (PXL) may include first to third sub-pixels (SP1 to SP3). The first to third sub-pixels (SP1 to SP3) may be arranged in a first direction (DR1). However, the arrangement of the pixel (PXL) is not limited thereto and may vary depending on embodiments. For example, the first to third sub-pixels (SP1 to SP3) may be arranged in a zigzag pattern.

[0096] First to third anode electrodes (AE1 to AE3) may be respectively disposed in the first to third sub-pixels (SP1 to SP3). The first anode electrode (AE1) may be provided as an anode electrode (AE, see FIG. 2) connected to a sub-pixel circuit (SPC, see FIG. 2) of the first sub-pixel (SP1). The second anode electrode (AE2) may be provided as an anode electrode (AE) connected to a sub-pixel circuit (SPC) of the second sub-pixel (SP2). The third anode electrode (AE3) may be provided as an anode electrode (AE) connected to a sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0097] The cathode electrode (CE) may be spaced apart from the first to third anode electrodes (AE1 to AE3). The cathode electrode (CE) may be arranged at the same height as the first to third anode electrodes (AE1 to AE3). The cathode electrode (CE) may be spaced apart from the first to third anode electrodes (AE1 to AE3) in a second direction (DR2). In embodiments, the cathode electrode (CE) may extend in the first direction (DR1) and be used as a common electrode for the first to third sub-pixels (SP1 to SP3). Although not shown, the cathode electrode (CE) may extend in the second direction (DR2) as well as the first direction (DR1) and be used as a common electrode for all of the sub-pixels (SP) of FIG. 3. The cathode electrode (CE) can be used as a common electrode for the pixel (PXL) and other pixels adjacent to the pixel (PXL). As such, the cathode electrode (CE) can have various shapes.

[0098] One or more first light-emitting elements (LD1_1, LD1_2), one or more second light-emitting elements (LD2_1, LD2_2) (or, LD2_1'' and LD2_2''), and one or more third light-emitting elements (LD3_1, LD3_2) (or, LD3_2'') may be arranged on the first to third anode electrodes (AE1 to AE3). The first light-emitting elements (LD1) may be connected to the first anode electrode (AE1). The second light-emitting elements (LD2) may be connected to the second anode electrode (AE2). The third light-emitting elements (LD3) may be connected to the third anode electrode (AE3). When multiple light-emitting elements are provided in each sub-pixel, each anode electrode may have a shape extending in a specific direction, such as the second direction (DR2), and the light-emitting elements connected thereto may be arranged in the same direction.

[0099] The first light-emitting elements (LD1) may be provided as the light-emitting elements (LD) of FIG. 2 included in the first sub-pixel (SP1). The second light-emitting elements (LD2) may be provided as the light-emitting elements (LD) of FIG. 2 included in the second sub-pixel (SP2). The third light-emitting elements (LD3) may be provided as the light-emitting elements (LD) of FIG. 2 included in the third sub-pixel (SP3). When a plurality of light-emitting elements are provided in one sub-pixel, the plurality of light-emitting elements may be connected in parallel between the anode electrode and the cathode electrode and provided as the light-emitting elements (LD) of FIG. 2.

[0100] The first light-emitting elements (LD1), the second light-emitting elements (LD2), and the third light-emitting elements (LD3) may be inorganic light-emitting diodes including inorganic light-emitting materials. However, embodiments are not limited thereto, and for example, organic light-emitting diodes may be used.

[0101] Figure 7 is a cross-sectional view taken along lines Ⅰ to Ⅰ' of Figure 6.

[0102] Referring to FIGS. 6 and 7, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged on a substrate (SUB).

[0103] The substrate (SUB) can extend in a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). A pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be arranged on the substrate (SUB) in a third direction (DR3) intersecting the first and second directions (DR1, DR2).

[0104] A pixel circuit layer (PCL) may include insulating layers, semiconductor patterns, and conductive patterns stacked on a substrate (SUB). The insulating layers may include a buffer layer (BFL), one or more interlayer insulating layers (ILD), and one or more passivation layers (PSV1, PSV2). The semiconductor patterns and conductive patterns may be positioned between the insulating layers. The conductive patterns may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0105] As described with reference to FIG. 2, each of the first to third sub-pixels (SP1 to SP3) may include a sub-pixel circuit (SPC, see FIG. 2) including transistors and one or more capacitors. Semiconductor patterns and conductive patterns of the pixel circuit layer (PCL) may function as transistors and capacitors of the sub-pixel circuit (SPC). In addition, the conductive patterns of the pixel circuit layer (PCL) may further function as wirings, for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) of FIG. 1.

[0106] A buffer layer (BFL) may be disposed on one surface of a substrate (SUB). The buffer layer (BFL) may prevent impurities from diffusing into circuit elements and wirings included in a pixel circuit layer (PCL). The buffer layer (BFL) may include an inorganic insulating layer including an inorganic material. In embodiments, the buffer layer (BFL) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The buffer layer (BFL) may be provided as a single layer or multiple layers. When the buffer layer (BFL) is provided as multiple layers, each layer may be formed of the same material or different materials.

[0107] In embodiments, one or more barrier layers may be disposed between the substrate (SUB) and the buffer layer (BFL). Each of the barrier layers may comprise polyimide.

[0108] On a buffer layer (BFL), first to third transistors (T_SP1 to T_SP3) corresponding to first to third sub-pixels (SP1 to SP3) may be arranged, respectively. The first transistor (T_SP1) may be any one of the transistors of the sub-pixel circuit (SPC) included in the first sub-pixel (SP1). The second transistor (T_SP1) may be any one of the transistors of the sub-pixel circuit (SPC) included in the second sub-pixel (SP2). The third transistor (T_SP3) may be any one of the transistors of the sub-pixel circuit (SPC) included in the third sub-pixel (SP3). Each of the first to third transistors (T_SP1 to T_SP3) may be understood as a transistor connected to an anode electrode among the transistors of the corresponding sub-pixel.

[0109] A first transistor (T_SP1) may include a semiconductor pattern (SCP), a gate electrode (GE), a first terminal (ET1), and a second terminal (ET2). The first terminal (ET1) may be either a source electrode or a drain electrode, and the second terminal (ET2) may be the other of the source electrode and the drain electrode. For example, the first terminal (ET1) may be a source electrode, and the second terminal (ET2) may be a drain electrode.

[0110] A semiconductor pattern (SCP) may be disposed on a buffer layer (BFL). The semiconductor pattern (SCP) may include a first contact region contacting a first terminal (ET1) and a second contact region contacting a second terminal (ET2). A region between the first contact region and the second contact region may be a channel region. The channel region may overlap with a gate electrode (GE) of the first transistor (T_SP1). The channel region may be a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities. As the impurity, for example, a p-type impurity may be used, but embodiments are not limited thereto.

[0111] The semiconductor pattern (SCP) may include any one of various types of semiconductors, for example, an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, a low temperature poly silicon semiconductor, and an oxide semiconductor.

[0112] Interlayer insulating layers (ILDs) may be sequentially stacked on a semiconductor pattern (SCP). The interlayer insulating layers (ILDs) may be inorganic insulating layers including an inorganic material. For example, each of the interlayer insulating layers (ILDs) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). However, the interlayer insulating layers (ILDs) are not limited thereto. For example, any one of the interlayer insulating layers (ILDs) may include an organic insulating layer including an organic material.

[0113] Interlayer insulating layers (ILDs) can electrically isolate conductive patterns and / or semiconductor patterns disposed between the interlayer insulating layers (ILDs). For example, the interlayer insulating layers (ILDs) can include a gate insulating layer (GI) disposed on a semiconductor pattern (SCP). The gate insulating layer (GI) can be disposed between the semiconductor pattern (SCP) and the gate electrode (GE) such that the semiconductor pattern (SCP) is spaced apart from the gate electrode (GE). In embodiments, the gate insulating layer (GI) can be provided over the entire surface of the semiconductor pattern (SCP) and the buffer layer (BFL) to cover the semiconductor pattern (SCP) and the buffer layer (BFL). As the number of layers required for the conductive patterns and / or semiconductor patterns increases, the number of interlayer insulating layers (ILDs) can increase.

[0114] A gate electrode (GE) may be disposed on a gate insulating layer (GI). The gate electrode (GE) may overlap a channel region of a semiconductor pattern (SCP). In embodiments, the gate electrode (GE) may be provided as a single layer including at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In embodiments, the gate electrode (GE) may be provided as a multilayer including at least one material selected from the group consisting of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag), which are low-resistance materials.

[0115] The first and second terminals (ET1, ET2) may be disposed on interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) may contact a semiconductor pattern (SCP) through contact holes penetrating the interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) may contact first and second contact areas of the semiconductor pattern (SCP), respectively. Each of the first and second terminals (ET1, ET2) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0116] Although the first and second terminals (ET1, ET2) are illustrated as separate electrodes electrically connected to the semiconductor pattern (SCP), embodiments are not limited thereto. In embodiments, the first terminal (ET1) may be a first contact region adjacent to one side of a channel region of the semiconductor pattern (SCP), and the second terminal (ET2) may be a second contact region adjacent to the other side of the channel region. In this case, the first terminal (ET1) may be electrically connected to the light emitting element (LD) via a connecting means, such as a bridge electrode, disposed on at least one of the interlayer insulating layers (ILD).

[0117] In embodiments, the first transistor (T_SP1) may be formed of a low-temperature polysilicon transistor. However, embodiments are not limited thereto. For example, the first transistor (T_SP1) may also be formed of an oxide semiconductor transistor. In embodiments, the sub-pixel circuit of each sub-pixel may include transistors of different types. For example, the first transistor (T_SP1) may be formed of a low-temperature polysilicon transistor, and the other transistors of the first sub-pixel (SP1) may be formed of oxide semiconductor transistors. In this case, the oxide semiconductor of the oxide semiconductor transistor may be formed on any one of the interlayer insulating layers (ILD) other than the insulating layer on which the semiconductor pattern (SCP) of the first transistor (T_SP1) is formed.

[0118] In the embodiments, the first transistor (T_SP1) is described as a transistor having a top gate structure, but the embodiments are not limited thereto. For example, the first transistor (T_SP1) may be a transistor having a bottom gate structure. In addition, the structure of the first transistor (T_SP1) may be changed in various ways.

[0119] Each of the second and third transistors (T_SP2, T_SP3) can be configured similarly to the first transistor (T_SP1). Hereinafter, redundant descriptions are omitted.

[0120] At least some of the various wirings of the display panel (DP) and / or display device (DD) may be further arranged on the interlayer insulating layers (ILD).

[0121] A first passivation layer (PSV1) may be disposed on the first to third transistors (T_SP1 to T_SP3). The passivation layer may also be referred to as a protective layer or a via layer. The first passivation layer (PSV1) protects components disposed thereunder and may provide a flat upper surface.

[0122] First to third connection patterns (CP1 to CP3) may be arranged on a first passivation layer (PSV1). The first to third connection patterns (CP1 to CP3) may penetrate the first passivation layer (PSV1) and be connected to first terminals (ET1) of the first to third transistors (T_SP1 to T_SP3), respectively. The first to third connection patterns (CP1 to CP3) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0123] At least some of the various wirings of the display panel (DP) and / or the display device (DD) may be further arranged on the first passivation layer (PSV1).

[0124] A second passivation layer (PSV2) may be disposed on the first to third connection patterns (CP1 to CP3) and the first passivation layer (PSV1). The first passivation layer (PSV1) may protect components disposed thereunder and provide a flat upper surface.

[0125] Each of the first and second passivation layers (PSV1, PSV2) may include an inorganic insulating layer including an inorganic material and / or an organic insulating layer including an organic material. The inorganic insulating layer may include, for example, at least one of a metal oxide such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The organic insulating layer may include, for example, at least one of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0126] The first and second passivation layers (PSV1, PSV2) may comprise the same material as one of the interlayer insulating layers (ILD), but embodiments are not limited thereto. Each of the first and second passivation layers (PSV1, PSV2) may be provided as a single layer, but may also be provided as multiple layers.

[0127] A display element layer (DPL) may be disposed on the second passivation layer (PSV2). The display element layer (DPL) may include first to third anode electrodes (AE1 to AE3), a first bank (BNK1), first to third light-emitting elements (LD1_1 to LD3_1), first to third overcoat patterns (OCP1 to OCP3), at least one insulating layer (INS), a cathode electrode (CE), first and second transparent electrode layers (ITO1, ITO2), and a capping layer (CPL).

[0128] On the pixel circuit layer (PCL), first to third anode electrodes (AE1 to AE3) can be arranged on the first to third sub-pixels (SP1 to SP3), respectively.

[0129] The first anode electrode (AE1) may be electrically connected to the first connection electrode (CP1) through a contact hole penetrating the second passivation layer (PSV2). The second anode electrode (AE2) may be electrically connected to the second connection electrode (CP2) through another contact hole penetrating the second passivation layer (PSV2). The third anode electrode (AE3) may be electrically connected to the third connection electrode (CP3) through another contact hole penetrating the second passivation layer (PSV2). In this way, the first to third anode electrodes (AE1 to AE3) may be electrically connected to the first to third transistors (T_SP1 to T_SP3), respectively.

[0130] A first bank (BNK1) may be disposed on the first to third anode electrodes (AE1 to AE3). The first bank (BNK1) may have first openings (OP1) exposing portions of the first to third anode electrodes (AE1 to AE3). First to third light-emitting elements (LD1_1 to LD3_1) may be disposed in the first openings (OP1) of the first bank (BNK1). In this way, the first bank (BNK1) may be provided as a pixel defining film that defines areas where the first to third light-emitting elements (LD1 to LD3) are positioned.

[0131] The first bank (BNK1) is configured to include a light-shielding material to prevent light mixing between adjacent sub-pixels. In embodiments, the first bank (BNK1) may include an organic material. For example, the first bank (BNK1) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0132] First to third reflective electrodes (RFE1 to RFE3) may be disposed on the exposed portions of the first to third anode electrodes (AE1 to AE3). Although not illustrated in FIG. 7, in order to further improve light emission efficiency, the first to third reflective electrodes (RFE1 to RFE3) may be disposed so as to extend further to the side of the first bank (BNK1) adjacent to the first openings (OP1). The first to third reflective electrodes (RFE1 to RFE3) may include conductive materials suitable for reflecting light. Accordingly, the light emission efficiency of the first to third light-emitting elements (LD1_1 to LD3_1) may be improved. In embodiments, the first to third reflective electrodes (RFE1 to RFE3) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0133] The first light-emitting element (LD1_1) may include a first semiconductor layer (11), an active layer (12), a second semiconductor layer (13), and an auxiliary layer (15). The first light-emitting element (LD1_1) may include a light-emitting laminate in which the auxiliary layer (15), the first semiconductor layer (11), the active layer (12), and the second semiconductor layer (13) are sequentially laminated.

[0134] The first light-emitting element (LD1_1) may include a bonding electrode (BDE1_1). The bonding electrode (BDE1_1) may be an end portion of the first light-emitting element (LD1_1) opposite to the third direction (DR3) and may be adjacent to the first overcoat pattern (OCP1). The first end portion (EPT1) of the first light-emitting element (LD1_1) may refer to the bonding electrode (BDE1_1) adjacent to the first overcoat pattern (OCP1). For example, the first end portion (EPT1) of the first light-emitting element (LD1_1) may include at least one of a side surface (EPT1_SS) and a lower surface of the bonding electrode (BDE1_1). The bonding electrode (BDE1_1) may include a eutectic metal. The bonding electrode (BDE1_1) may be connected to the second semiconductor layer (13).

[0135] The first semiconductor layer (11) may be configured to provide electrons to the active layer (12). The first semiconductor layer (11) may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer (11) may include any one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the first semiconductor layer (11) is not limited thereto, and various other materials may also constitute the first semiconductor layer (11). In one embodiment of the present invention, the first semiconductor layer (11) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant). According to an embodiment, the first semiconductor layer (11) may form an n-type semiconductor layer together with the auxiliary layer (15).

[0136] The active layer (12) may be a region where electrons and holes recombine. As electrons and holes recombine in the active layer (12), they transition to a lower energy level, and light having a corresponding wavelength may be generated. The active layer (12) may be formed as a single or multiple quantum well structure. When the active layer (12) is formed as a multiple quantum well structure, units including a barrier layer, a strain reinforcing layer, and a well layer may be repeatedly stacked to form the active layer (12). However, embodiments of the active layer (12) are not limited thereto.

[0137] The second semiconductor layer (13) can provide holes to the active layer (12). The second semiconductor layer (13) can be spaced apart from the first semiconductor layer (11) with the active layer (12) therebetween. The second semiconductor layer (13) can include a semiconductor layer of a different type from the first semiconductor layer (11). For example, the second semiconductor layer (13) can include at least one p-type semiconductor layer. For example, the second semiconductor layer (13) can include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and can be a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc. However, the material constituting the second semiconductor layer (13) is not limited to this, and various other materials may also constitute the second semiconductor layer (13). In one embodiment of the present invention, the second semiconductor layer (13) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant).

[0138] The auxiliary layer (15) may include a gallium nitride (GaN) semiconductor material that is not doped with impurities, and may form an n-type semiconductor layer together with the first semiconductor layer (11). The auxiliary layer (15) may be an end portion of the first light-emitting element (LD1_1) in the third direction (DR3) and may be adjacent to the capping layer (CPL). The second end (EPT2) of the first light-emitting element (LD1_1) may be spaced apart from the first end (EPT1) of the first light-emitting element (LD1_1) in the third direction (DR3). The second end (EPT2) of the first light-emitting element (LD1_1) may refer to the auxiliary layer (15) adjacent to the capping layer (CPL). For example, the second end (EPT2) of the first light-emitting element (LD1_1) may include an upper surface of the auxiliary layer (15).

[0139] The first light-emitting element (LD1_1) may further include an insulating film (14) covering a side surface (SPT) of the light-emitting stack. The side surface (SPT) may be disposed between a first end (EPT1) and a second end (EPT2) of the first light-emitting element (LD1_1). The insulating film (14) may prevent an electrical short circuit that may occur when the active layer (12) comes into contact with a conductive material other than the first and second semiconductor layers (11, 13). The insulating film (14) may include a transparent insulating material. The insulating film (14) may be configured to expose the bonding electrode (BDE1_1). The insulating film (14) may be configured to expose the second end (EPT2).

[0140] First to third overcoat patterns (OCP1 to OCP3) may be arranged within the first openings (OP1) in which the first to third light-emitting elements (LD1_1 to LD3_1) are arranged. The first to third overcoat patterns (OCP1 to OCP3) may be arranged on the first to third reflective electrodes (RFE1 to RFE3). The first to third overcoat patterns (OCP1 to OCP3) may fix the first to third light-emitting elements (LD1_1 to LD3_1) so as not to move. In addition, the first to third overcoat patterns (OCP1 to OCP3) may protect components arranged thereunder from foreign substances such as dust and moisture. For example, the first to third overcoat patterns (OCP1 to OCP3) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the first to third overcoat patterns (OCP1 to OCP3) may include epoxy, but embodiments are not limited thereto.

[0141] In embodiments, the first overcoat pattern (OCP1) may be disposed between the first end (EPT1) of the first light-emitting element (LD1_1) and the first anode electrode (AE1). The first overcoat pattern (OCP1) may be disposed between the first end (EPT1) of the first light-emitting element (LD1_1) and the first reflective electrode (RFE1). The first overcoat pattern (OCP1) may be in contact with the first end (EPT1) of the first light-emitting element (LD1_1). The second overcoat pattern (OCP2) may be disposed between the first end (EPT1) of the second light-emitting element (LD2_1) and the second anode electrode (AE2). The second overcoat pattern (OCP2) may be disposed between the first end (EPT1) of the second light-emitting element (LD2_1) and the second reflective electrode (RFE2). The second overcoat pattern (OCP2) may be in contact with the first end (EPT1) of the second light-emitting element (LD2_1). And, the third overcoat pattern (OCP3) may be disposed between the first end (EPT1) of the third light-emitting element (LD3_1) and the third anode electrode (AE3). The third overcoat pattern (OCP3) may be disposed between the first end (EPT1) of the third light-emitting element (LD3_1) and the third anode electrode (AE3). The third overcoat pattern (OCP3) may be in contact with the first end (EPT1) of the third light-emitting element (LD3_1).

[0142] A first transparent electrode layer (ITO1) may be disposed on the first to third overcoat patterns (OCP1 to OCP3). The first transparent electrode layer (ITO1) may be in contact with the first to third overcoat patterns (OCP1 to OCP3). The first transparent electrode layer (ITO1) may be in contact with a portion of the first to third anode electrodes (AE1 to AE3) exposed by the first openings (OP1). The first transparent electrode layer (ITO1) may be in contact with a first end (EPT1) of each of the first to third light-emitting elements (LD1_1 to LD3_1). For example, the first transparent electrode layer (ITO1) may be in contact with a side surface (EPT1_SS) of each of the bonding electrodes (BDE1_1 to BDE3_1). Additionally, the first transparent electrode layer (ITO1) may also be in contact with a portion of the side surface (SPT) disposed between the first end (EPT1) and the second end (EPT2) of each of the first to third light-emitting elements (LD1_1 to LD3_1).

[0143] The first transparent electrode layer (ITO1) can electrically connect the first end (EPT1) of the first light-emitting element (LD1_1) and the first anode electrode (AE1). The first transparent electrode layer (ITO1) can electrically connect the first end (EPT1) of the second light-emitting element (LD2_1) and the second anode electrode (AE2). The first transparent electrode layer (ITO1) can electrically connect the first end (EPT1) of the third light-emitting element (LD3_1) and the third anode electrode (AE3). For example, the bonding electrodes (BDE1_1 to BDE3_1) can be electrically connected to the first to third anode electrodes (AE1 to AE3) through the first transparent electrode layer (ITO1) in contact with each side surface (EPT1_SS).

[0144] In embodiments, the first transparent electrode layer (ITO1) may be configured to be substantially transparent or translucent to satisfy a predetermined light transmittance. In embodiments, the first transparent electrode layer (ITO1) may include at least one of various transparent conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. However, the material of the first transparent electrode layer (ITO1) is not limited thereto.

[0145] At least one insulating layer (INS) may be disposed on the first bank (BNK1) and the first transparent electrode layer (ITO1). The at least one insulating layer (INS) may protect components disposed thereunder and provide a flat upper surface. The at least one insulating layer (INS) may include the same material as one of the first and second passivation layers (PSV1, PSV2), but embodiments are not limited thereto.

[0146] At least one insulating layer (INS) may include a first insulating layer (INS1) and a second insulating layer (INS2). The first insulating layer (INS1) may be disposed on the first to third anode electrodes (AE1 to AE3) and the cathode electrode (CE, see FIG. 6), respectively. The second insulating layer (INS2) may be disposed on the first insulating layer (INS1). For example, the first insulating layer (INS1) may be in contact with the first transparent electrode layer (ITO1). The second insulating layer (INS2) may be in contact with the side surface (SPT) of each of the first to third light-emitting elements (LD1_1 to LD3_1).

[0147] In this way, by forming the first insulating layer (INS1) on the first to third anode electrodes (AE1 to AE3), the bonding reliability of the first to third light-emitting elements (LD1_1 to LD3_1) can be improved. Specifically, when bonding the first to third light-emitting elements (LD1_1 to LD3_1) on the first to third overcoat patterns (OCP1 to OCP3), more free alignment can be possible.

[0148] In embodiments, at least one insulating layer (INS) may not overlap the first to third light-emitting elements (LD1_1 to LD3_1). The first to third light-emitting elements (LD1_1 to LD3_1) may protrude into the light-functional layer (LFL). The first to third light-emitting elements (LD1_1 to LD3_1) may be at least partially positioned within the second openings (OP2) of the second bank (BNK2). For example, the height of the second end (EPT2) of each of the first to third light-emitting elements (LD1_1 to LD3_1) from the substrate (SUB) may be higher than the lowermost end (RBE) of the reflective layer (RFL). Accordingly, light emitted from the first to third light-emitting elements (LD1_1 to LD3_1) may be provided to the light-functional layer (LFL) at a relatively high rate.

[0149] A second transparent electrode layer (ITO2) may be disposed on at least one insulating layer (INS). The second transparent electrode layer (ITO2) may be spaced apart from the first transparent electrode layer (ITO1) in a third direction (DR3) with at least one insulating layer (INS) interposed therebetween. The second transparent electrode layer (ITO2) may be in contact with the second insulating layer (INS2).

[0150] A second transparent electrode layer (ITO2) may be disposed on the first to third light-emitting elements (LD1_1 to LD3_1). The second transparent electrode layer (ITO2) may be in contact with a second end (EPT2) of each of the first to third light-emitting elements (LD1_1 to LD3_1). The second transparent electrode layer (ITO2) may be connected to a cathode electrode (CE) through a contact hole (CTH, see FIG. 8) penetrating at least one insulating layer (INS). The second transparent electrode layer (ITO2) may electrically connect the second end (EPT2) of each of the first to third light-emitting elements (LD1_1 to LD3_1) and the cathode electrode (CE). For example, the auxiliary layer (15) of each of the first to third light-emitting elements (LD1_1 to LD3_1) may be electrically connected to the cathode electrode (CE) through the second transparent electrode layer (ITO2) connected to the upper surface of the auxiliary layer (15). Accordingly, the first to third light-emitting elements (LD1_1 to LD3_1) may be electrically connected between the first to third anode electrodes (AE1 to AE3) and the cathode electrode (CE), respectively.

[0151] In embodiments, the second transparent electrode layer (ITO2) may be configured to be substantially transparent or translucent to satisfy a predetermined light transmittance. In embodiments, the second transparent electrode layer (ITO2) may include the same material as the first transparent electrode layer (ITO1), but embodiments are not limited thereto.

[0152] The remaining first to third light-emitting elements (LD1_2 to LD3_2) of FIG. 6 can also be configured similarly to the first to third light-emitting elements (LD1_1 to LD3_1) of FIG. 7.

[0153] The capping layer (CPL) may be disposed on the second transparent electrode layer (ITO2). The capping layer (CPL) may protect components under the capping layer (CPL), such as the first and second transparent electrode layers (ITO1, ITO2), and the first to third light-emitting elements (LD1_1 to LD3_1), from external moisture and humidity. The capping layer (CPL) may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). However, the material of the capping layer (CPL) is not limited thereto.

[0154] A light functional layer (LFL) may be disposed on a capping layer (CPL). The light functional layer (LFL) may include a second bank (BNK2), a reflective layer (RFL), a third passivation layer (PSV3), first and second light conversion patterns (CCP1, CCP2), a light scattering pattern (LSP), a low-refractive-index layer (LRL), and a color filter layer (CFL).

[0155] A second bank (BNK2) may be disposed on the capping layer (CPL). The second bank (BNK2) may overlap the first bank (BNK1). The second bank (BNK2) may have second openings (OP2) that overlap the first openings (OP1).

[0156] The second bank (BNK2) is configured to include a light-blocking material to prevent light mixing between adjacent pixels and the first to third sub-pixels (SP1 to SP3). In embodiments, the second bank (BNK2) may include an organic material. For example, the second bank (BNK2) may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0157] A reflective layer (RFL) may be disposed on the side surfaces of the second bank (BNK2) adjacent to the second openings (OP2). The reflective layer (RFL) is configured to reflect incident light, thereby improving light emission efficiency. The reflective layer (RFL) may include a material suitable for reflecting light. The reflective layer (RFL) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0158] It can be understood that the light-emitting area (EMA) and the non-light-emitting area (NEMA) for the first to third sub-pixels (SP1 to SP3) are defined by the second bank (BNK2). The area overlapping the second bank (BNK2) may correspond to the non-light-emitting area (NEMA). The area overlapping the second openings (OP2) of the second bank (BNK2) may correspond to the light-emitting area (EMA).

[0159] On the capping layer (CPL), a third passivation layer (PSV3) may be disposed within the second openings (OP2). The third passivation layer (PSV3) may protect components disposed thereunder and provide a flat upper surface. The third passivation layer (PSV3) may include the same material as either of the first and second passivation layers (PSV1, PSV2), but embodiments are not limited thereto.

[0160] On the third passivation layer (PSV3), first and second light conversion patterns (CCP1, CCP2) and a light scattering pattern (LSP) can be arranged within the second openings (OP2).

[0161] The first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may include color conversion particles and / or scattering particles. The color conversion particles may change the wavelength of incident light to convert the incident light into light of a different color. Additionally, the color conversion particles may scatter the incident light. In embodiments, the color conversion particles may be quantum dots. The scattering particles may scatter the incident light.

[0162] In embodiments, the first to third light-emitting elements (LD1_1 to LD3_1) may be configured to emit blue light. In this case, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. The second light conversion pattern (CCP2) may include second color conversion particles (QD2) configured to convert blue light into green light. The light scattering pattern (LSP) may include scattering particles (SCT) that scatter blue light to improve light emission efficiency. Accordingly, the first to third sub-pixels (SP1 to SP3) may be provided as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. In embodiments, at least one of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may further include color conversion particles that convert blue color light into white color light.

[0163] In embodiments, the first to third light-emitting elements (LD1_1 to LD3_1) may be configured to emit red, green, and blue light, respectively. In this case, each of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may include scattering particles (SCT). In this way, the particles included in the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be variously changed depending on the first to third light-emitting elements (LD1_1 to LD3_1).

[0164] In embodiments, the first and second optical conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be omitted.

[0165] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), the first light conversion pattern (CCP1), the second light conversion pattern (CCP2), and the light scattering pattern (LSP). The low-refractive-index layer (LRL) may have a lower refractive index than the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP). The low-refractive-index layer (LRL) may be configured to refract or totally reflect light depending on an incident angle of the light. The low-refractive-index layer (LRL) may provide light that has passed through the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) back to the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP). Accordingly, the light conversion efficiency and light scattering efficiency of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) can be improved. In embodiments, the low refractive index layer (LRL) can be omitted in the area corresponding to the third sub-pixel (SP3).

[0166] A color filter layer (CFL) may be disposed on the low refractive index layer (LRL). The color filter layer (CFL) may include first to third color filters (CF1 to CF3) and light blocking patterns (LBP).

[0167] The first to third color filters (CF1 to CF3) may overlap the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP), respectively. Each of the first to third color filters (CF1 to CF3) may selectively transmit light of a desired wavelength range. When the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. When the second sub-pixel (SP2) is a green sub-pixel, the second color filter (CF2) may include a green color filter. When the third sub-pixel (SP3) is a blue sub-pixel, the third color filter (CF3) may include a blue color filter. The first to third color filters (CF1 to CF3) may have a refractive index higher than that of the low-refractive-index layer (LRL). However, embodiments are not limited thereto, and the first to third color filters (CF1 to CF3) may have a refractive index lower than or equal to that of the low refractive index layer (LRL).

[0168] Light blocking patterns (LBP) may be arranged between the first to third color filters (CF1 to CF3). It may be understood that the light emitting area (or light emitting area) (EMA) and the non-light emitting area (NEMA) for the first to third sub-pixels (SP1 to SP3) are defined by the light blocking patterns (LBP). An area overlapping the light blocking patterns (LBP) may correspond to the non-light emitting area (NEMA). An area not overlapping the light blocking patterns (LBP) may correspond to the light emitting area (EMA).

[0169] In embodiments, the light-blocking patterns (LBP) may include at least one of various types of light-blocking materials. In embodiments, each of the light-blocking patterns (LBP) may be provided in the form of a multilayer in which at least two color filters among the first to third color filters (CF1 to CF3) overlap. For example, each of the light-blocking patterns (LBP) may be formed by overlapping the first to third color filters (CF1 to CF3). As another example, the light-blocking pattern between the first and second color filters (CF1, CF2) among the light-blocking patterns (LBP) may be formed as a multilayer in which the first and second color filters (CF1, CF2) overlap, and the light-blocking pattern between the second and third color filters (CF2, CF3) among the light-blocking patterns (LBP) may be formed as a multilayer in which the second and third color filters (CF2, CF3) overlap. The light blocking pattern between the first color filter (CF1) and the third color filter (CF3) of the neighboring pixel can be formed as a multilayer in which the first and third color filters (CF1, CF3) overlap. In this way, each of the first to third color filters (CF1 to CF3) can extend into the non-emitting area (NEMA) to form light blocking patterns (LBP).

[0170] Figure 8 is a cross-sectional view taken along line Ⅱ to Ⅱ' of Figure 6.

[0171] Referring to FIGS. 6 and 8, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially provided on a substrate (SUB).

[0172] The pixel circuit layer (PCL) and the display element layer (DPL) are described in the same manner as described with reference to FIG. 7. In the pixel circuit layer (PCL), sub-pixel circuits corresponding to the first to third sub-pixels (SP1 to SP3) may be provided, respectively. In the display element layer (DPL), at least one first light-emitting element (LD1_1, LD1_2) corresponding to the first sub-pixel (SP1) may be provided. The first light-emitting elements (LD1_1, LD1_2) may overlap one of the first openings (OP1) of the first bank (BNK1). The first light-emitting elements (LD1_1, LD1_2) may be connected between the cathode electrode (CE) and the transistor (T_SP1) included in the sub-pixel circuit of the first sub-pixel (SP1). Hereinafter, overlapping descriptions are omitted.

[0173] A light functional layer (LFL) may be provided on the display element layer (DPL). The light functional layer (LFL) is described in the same manner as described with reference to FIG. 7. Hereinafter, redundant descriptions are omitted.

[0174] The first anode electrode (AE1) and the cathode electrode (CE) may be arranged on the same layer on the substrate (SUB). The first anode electrode (AE1) and the cathode electrode (CE) may be spaced apart from each other in the second direction (DR2).

[0175] In embodiments, the first anode electrode (AE1) may be electrically connected to the first light-emitting elements (LD1_1, LD1_2) through the first transparent electrode layer (ITO1). For example, the first anode electrode (AE1) may overlap one (OP1_1) of the first openings (OP1) of the first bank (BNK1). A portion of the first anode electrode (AE1) may be exposed through one (OP1_1) of the first openings (OP1) of the first bank (BNK1). A portion of the first anode electrode (AE1) and the first transparent electrode layer (ITO1) may be in contact with each other in one (OP1_1) of the first openings (OP1) of the first bank (BNK1).

[0176] A first transparent electrode layer (ITO1) may be disposed on a first anode electrode (AE1). The first transparent electrode layer (ITO1) connected to the first anode electrode (AE1) may be disposed on a first overcoat pattern (OCP1). The first transparent electrode layer (ITO1) may be in contact with a first end (EPT1) of each of the first light-emitting elements (LD1_1, LD1_2) and the first overcoat pattern (OCP1). The first transparent electrode layer (ITO1) may be in contact with the bonding electrodes (BDE1_1, BDE1_2) of the first light-emitting elements (LD1_1, LD1_2). For example, the first transparent electrode layer (ITO1) may be in contact with side surfaces of the bonding electrodes (BDE1_1, BDE1_2) of the first light-emitting elements (LD1_1, LD1_2). The first anode electrode (AE1) can be electrically connected to the transistor (T_SP1). A voltage applied from the first power voltage node (VDDN) through the transistor (T_SP1) can be transmitted to the first light-emitting elements (LD1_1, LD1_2) through the first transparent electrode layer (ITO1).

[0177] The cathode electrode (CE) can be electrically connected to the first light-emitting elements (LD1_1, LD1_2) through the second transparent electrode layer (ITO2). For example, the cathode electrode (CE) can overlap another one (OP1_2) of the first openings (OP1) of the first bank (BNK1). A portion of the cathode electrode (CE) can be exposed through another one (OP1_2) of the first openings (OP1) of the first bank (BNK1). The cathode electrode (CE) and the second transparent electrode layer (ITO2) in the other one (OP1_2) of the first openings (OP1) of the first bank (BNK1) can be connected through a contact hole (CTH). For example, the contact hole (CTH) can penetrate at least one insulating layer (INS) and overlap the cathode electrode (CE). The contact hole (CTH) can be spaced apart from the first light-emitting elements (LD1_1, LD1_2) in the second direction (DR2) without overlapping with the first light-emitting elements (LD1_1, LD1_2).

[0178] The first transparent electrode layer (ITO1) and the second transparent electrode layer (ITO2) may be arranged on different layers on the substrate (SUB). The first transparent electrode layer (ITO1) and the second transparent electrode layer (ITO2) may be spaced apart from each other in the third direction (DR3). The first transparent electrode layer (ITO1) and the second transparent electrode layer (ITO2) may be spaced apart from each other with at least one insulating layer (INS) interposed therebetween.

[0179] The second transparent electrode layer (ITO2) may be disposed on the first light-emitting elements (LD1_1, LD1_2). The second transparent electrode layer (ITO2) connected to the cathode electrode (CE) may be disposed entirely on the first bank (BNK1), the first light-emitting elements (LD1_1, LD1_2), and at least one insulating layer (INS). The second transparent electrode layer (ITO2) may be in contact with the second end (EPT2) of each of the first light-emitting elements (LD1_1, LD1_2). The second transparent electrode layer (ITO2) may be in contact with the auxiliary layer (15, see FIG. 7) of each of the first light-emitting elements (LD1_1, LD1_2). For example, the second transparent electrode layer (ITO2) may be in contact with the upper surface of the auxiliary layer (15, see FIG. 7) of each of the first light-emitting elements (LD1_1, LD1_2). The cathode electrode (CE) may be electrically connected to the second power voltage node (VSSN) of FIG. 2. The second power voltage applied to the second power voltage node (VSSN) may be transmitted to the first light-emitting elements (LD1_1, LD1_2) through the second transparent electrode layer (ITO2).

[0180] The display element layer (DPL) of the first sub-pixel (SP1) has been described above. Each of the second and third sub-pixels (SP2, SP3) of FIG. 6 may also be configured similarly to the first sub-pixel (SP1), unless otherwise described herein.

[0181] It is assumed that one end of the first light-emitting element is connected to the first anode electrode (AE1) through the first transparent electrode layer (ITO1) and the other end of the first light-emitting element is connected to the cathode electrode (CE) through a third transparent electrode layer disposed on the same layer as the first transparent electrode layer (ITO1) without a contact hole (CTH). In this case, the distance between the first transparent electrode layer (ITO1) and the third transparent electrode layer may be relatively close, which may cause a short between the first transparent electrode layer (ITO1) and the third transparent electrode layer. For example, the first transparent electrode layer (ITO1) and the third transparent electrode layer may be formed using the same photoresist during the manufacturing process, and a portion of the photoresist may not be removed and may remain. If the remaining photoresist exists between the first transparent electrode layer (ITO1) and the third transparent electrode layer, the first transparent electrode layer (ITO1) and the third transparent electrode layer may be unintentionally electrically connected. The closer the distance between the first transparent electrode layer (ITO1) and the third transparent electrode layer, the more likely the first transparent electrode layer (ITO1) and the third transparent electrode layer may be short-circuited. This means that the first anode electrode (AE1) and the cathode electrode (CE) may be unintentionally short-circuited, and thus the operational reliability of the display device may be relatively low.

[0182] According to an embodiment, the second end (EPT2) of each of the first light-emitting elements (LD1_1, LD1_2) may be arranged to face in the opposite direction to the substrate (SUB) and may be connected to the cathode electrode (CE) through the second transparent electrode layer (ITO2) and the contact hole (CTH). For example, a transparent electrode layer that is arranged in the same layer as the first transparent electrode layer (ITO1) and connects the first light-emitting elements (LD1_1, LD1_2) to the cathode electrode (CE) may not be provided. Accordingly, unintentional short-circuiting of the first anode electrode (AE1) and the cathode electrode (CE) is prevented, and thus the display device may have improved operational reliability.

[0183] In addition, the first transparent electrode layer (ITO1) connected to the first anode electrode (AE1) may be arranged to surround the side surfaces of the first ends (EPT1) of each of the first light-emitting elements (LD1_1, LD1_2), and the second transparent electrode layer (ITO2) connected to the cathode electrode (CE) may be arranged on the upper surface of the second ends (EPT1) of each of the first light-emitting elements (LD1_1, LD1_2). Accordingly, the first transparent electrode layer (ITO1) may be formed entirely on the side surfaces of the first ends (EPT1) of each of the first light-emitting elements (LD1_1, LD1_2), thereby increasing the contact area between the first transparent electrode layer (ITO1) connected to the first anode electrode (AE1) and the first light-emitting elements (LD1_1, LD1_2). Accordingly, the display device may have improved stability.

[0184] FIG. 9 is a plan view showing another embodiment of one of the pixels of FIG. 3.

[0185] Referring to FIG. 9, the first pixel (PXL') may include first to third sub-pixels (SP1' to SP3'). Hereinafter, any description overlapping with FIG. 6 is omitted.

[0186] The first to third sub-pixels (SP1' to SP3') may be arranged in a first direction (DR1). First to third anode electrodes (AE1' to AE3') may be arranged in the first to third sub-pixels (SP1' to SP3'), respectively. A cathode electrode (CE) may be arranged in the first to third sub-pixels (SP1' to SP3') in a second direction (DR2) and spaced apart from the first to third anode electrodes (AE1' to AE3'). In other embodiments, the first to third anode electrodes (AE1 to AE3) may be the first to third anode electrodes (AE1' to AE3'), and the first to third anode electrodes (AE1'' to AE3'') may be the first to third anode electrodes (AE1'' to AE3').

[0187] On the first to third anode electrodes (AE1' to AE3'), one or more first light-emitting elements (LD1_1', LD1_2'), one or more second light-emitting elements (LD2_1', LD2_2'), and one or more third light-emitting elements (LD3_1', LD3_2') can be arranged.

[0188] The first light-emitting elements (LD1') may be connected to the first anode electrode (AE1'). The second light-emitting elements (LD2') may be connected to the second anode electrode (AE2'). The third light-emitting elements (LD3') may be connected to the third anode electrode (AE3'). In this way, the first to third anode electrodes (AE1' to AE3') may have a shape extending in the second direction (DR2). Two light-emitting elements may be arranged in the second direction (DR2) on each of the first to third anode electrodes (AE1' to AE3').

[0189] On the first to third anode electrodes (AE1' to AE3'), the first to third light-emitting elements (LD1' to LD3') may have polygonal shapes when viewed in the third direction (DR3). For example, the first to third light-emitting elements (LD1' to LD3') may have rectangular shapes as illustrated in FIG. 9. However, embodiments are not limited thereto.

[0190] The shapes of the first to third light-emitting elements (LD1' to LD3') illustrated in FIGS. 6 and 9 are exemplary, and the embodiments are not limited thereto. Each anode electrode includes one or more light-emitting elements, and each of the light-emitting elements may have various shapes and sizes.

[0191] FIG. 10 is a plan view showing another embodiment of one of the pixels of FIG. 3.

[0192] Referring to FIG. 10, a pixel (PXL'') may include first to third sub-pixels (SP1'' to SP3''). The first to third sub-pixels (SP1'' to SP3'') may be arranged in a first direction (DR1). The pixel (PXL'') may include first to third anode electrodes (AE1'' to AE3''), a cathode electrode (CE''), and first to third light-emitting elements (LD1'' to LD3'').

[0193] The first to third anode electrodes (AE1'' to AE3'') can be described in the same manner as the embodiments of FIG. 6. Hereinafter, overlapping descriptions with respect to the embodiments of FIG. 6 will be omitted, and differences from the above-described embodiments will be mainly described.

[0194] On the first to third anode electrodes (AE1'' to AE3''), the first to third light-emitting elements (LD1'' to LD3'') may have rectangular shapes when viewed in the third direction (DR3). For example, when the first to third light-emitting elements (LD1'' to LD3'') have a rectangular shape, one pair of sides extending in the second direction (DR2) may be longer than the other pair of sides extending in the first direction (DR1). However, embodiments are not limited thereto.

[0195] The cathode electrode (CE'') may be disposed on the first to third light-emitting elements (LD1'' to LD3''). The cathode electrode (CE'') may be disposed spaced apart from the first to third anode electrodes (AE1'' to AE3'') in the third direction (DR3).

[0196] The cathode electrode (CE'') may extend in the second direction (DR2) as well as the first direction (DR1) when viewed in the third direction (DR3), and may be disposed entirely on the first to third sub-pixels (SP1'' to SP3''). For example, a part of the cathode electrode (CE'') may overlap the first to third anode electrodes (AE1'' to AE3'') and the first to third light-emitting elements (LD1'' to LD3''). Another part of the cathode electrode (CE'') may not overlap the first to third anode electrodes (AE1'' to AE3'') and the first to third light-emitting elements (LD1'' to LD3'').

[0197] Fig. 11 is a cross-sectional view taken along line Ⅲ to Ⅲ' of Fig. 10.

[0198] Fig. 12 is a cross-sectional view taken along line Ⅳ to Ⅳ' of Fig. 10.

[0199] Referring to FIGS. 10, 11, and 12, a pixel circuit layer (PCL), a display element layer (DPL''), and a light function layer (LFL) can be sequentially provided on a substrate (SUB).

[0200] The pixel circuit layer (PCL) and the light function layer (LFL) can be described in the same manner as described with reference to FIGS. 7 and 8. The first to third anode electrodes (AE1 to AE3), the first to third reflective electrodes (RFE1 to RFE3), the first to third overcoat patterns (OCP1 to OCP3), the first transparent electrode layer (ITO1), the first to third light-emitting elements (LD1_1'' to LD3_1''), and at least one insulating layer (INS) can be described in the same manner as in the embodiments of FIGS. 7 and 8. Hereinafter, overlapping descriptions with respect to the embodiments of FIGS. 7 and 8 will be omitted, and differences from the above-described embodiments will be mainly described.

[0201] Referring to FIGS. 10 and 11, a cathode electrode (CE'') may be disposed on at least one insulating layer (INS). The cathode electrode (CE'') may be spaced apart from the first to third anode electrodes (AE1 to AE3) in a third direction (DR3). The cathode electrode (CE'') may be spaced apart from the first transparent electrode layer (ITO1) in the third direction (DR3) with at least one insulating layer (INS) interposed therebetween. The cathode electrode (CE'') may be disposed entirely on the second insulating layer (INS2) and may be in contact with the second insulating layer (INS2).

[0202] The cathode electrode (CE'') may be disposed on the first to third light-emitting elements (LD1_1'' to LD3_1''). The cathode electrode (CE'') may be in contact with the second end (EPT2) of each of the first to third light-emitting elements (LD1_1'' to LD3_1''). The cathode electrode (CE'') and the second end (EPT2) of each of the first to third light-emitting elements (LD1_1'' to LD3_1'') may be electrically connected. Accordingly, the auxiliary layer (15) of each of the first to third light-emitting elements (LD1_1'' to LD3_1'') may be electrically connected to the cathode electrode (CE'').

[0203] The cathode electrode (CE'') may be configured to be substantially transparent or translucent to satisfy a predetermined light transmittance. In embodiments, the cathode electrode (CE'') may include at least one of various transparent conductive materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), etc. However, the material of the cathode electrode (CE'') is not limited thereto.

[0204] Referring to FIGS. 10 and 12, the first anode electrode (AE1) and the cathode electrode (CE'') may be arranged in different layers on the substrate (SUB). The first anode electrode (AE1) and the cathode electrode (CE'') may be spaced apart from each other in the third direction (DR3).

[0205] The cathode electrode (CE'') may be disposed on the first light-emitting elements (LD1_1'', LD1_2'') and may be electrically connected thereto. The cathode electrode (CE'') may be disposed entirely on the first bank (BNK1), the first light-emitting elements (LD1_1'', LD1_2''), and at least one insulating layer (INS). For example, the cathode electrode (CE'') may overlap the first light-emitting elements (LD1_1'', LD1_2'') disposed in the first openings (OP1) of the first bank (BNK1). The cathode electrode (CE'') may be disposed directly on the first light-emitting elements (LD1_1'', LD1_2'') and may be in contact with the second end (EPT2) of each of the first light-emitting elements (LD1_1'', LD1_2''). The cathode electrode (CE'') can be in contact with the upper surface of each of the first light-emitting elements (LD1_1'', LD1_2''). For example, the cathode electrode (CE'') can be in contact with the auxiliary layer (15) of each of the first light-emitting elements (LD1_1'', LD1_2'').

[0206] The display element layer (DPL) of the first sub-pixel (SP1'') has been described above. Each of the second and third sub-pixels (SP2'', SP3'') of FIG. 11 can also be configured similarly to the first sub-pixel (SP1''), unless otherwise described herein.

[0207] In this way, when the first to third light-emitting elements (LD1_1'' to LD3_1'') have a relatively large size, the first transparent electrode layer (ITO1) connected to the first to third anode electrodes (AE1 to AE3) is formed to be in contact with the first end (EPT1) of the first to third light-emitting elements (LD1_1'' to LD3_1''), and the cathode electrode (CE'') is formed to be in contact with the second end (EPT2) of the first to third light-emitting elements (LD1_1'' to LD3_1''), thereby increasing the integration area and improving the integration degree.

[0208] Figure 13 is a flowchart showing a method for manufacturing a display device according to an embodiment of the present invention.

[0209] Referring to FIG. 13, a method for manufacturing a display device (DD) according to an embodiment may include a step of forming an anode electrode and a cathode electrode on a substrate (S100), a step of forming a reflective electrode on the anode electrode (S110), a step of forming an overcoat pattern on the anode electrode (S120), a step of arranging a light-emitting element on the overcoat pattern (S130), a step of forming a first transparent electrode layer on the overcoat pattern (S140), a step of forming at least one insulating layer on the first transparent electrode layer and the cathode electrode (S150), and a step of forming a second transparent electrode layer on the at least one insulating layer (S160).

[0210] Figures 14 to 23 are drawings showing an example of a method for manufacturing the display device of Figure 13.

[0211] Fig. 14 is a plan view of the display device in S100 and S110 of Fig. 13. Fig. 15 is a cross-sectional view taken along line II-II' of Fig. 14. Hereinafter, line II-II' of each of Figs. 14, 16, 18, 20, and 21 is understood as a cutting plane line at the same position as line II-II' of Fig. 6.

[0212] Referring to FIGS. 13, 14 and 15, in S100, first to third anode electrodes (AE1 to AE3) and a cathode electrode (CE) can be formed on a substrate (SUB) (or pixel circuit layer (PCL)).

[0213] According to an embodiment, a pixel circuit layer (PCL) on a substrate (SUB) may be formed based on a conventional process for manufacturing a semiconductor device. For example, a conductive layer or an insulating layer included in the pixel circuit layer (PCL) may be formed by a photolithography process. Alternatively, the conductive layer or the insulating layer included in the pixel circuit layer (PCL) may be etched by various methods (wet etching, dry etching, etc.) or deposited by various methods (sputtering, chemical vapor deposition, etc.). However, the embodiments are not limited thereto.

[0214] A first transistor (T_SP1) may be formed on a substrate (SUB), and a buffer layer (BFL), interlayer insulating layers (ILD), a first passivation layer (PSV1), and a second passivation layer (PSV2) may be formed.

[0215] The first transistor (T_SP1) may be any one of the transistors of the sub-pixel circuit included in the first sub-pixel (SP1). The first transistor (T_SP1) may include a semiconductor pattern (SCP), a gate electrode (GE), a first terminal (ET1), and a second terminal (ET2). In addition, a gate insulating layer (GI) may be disposed between the semiconductor pattern (SCP) and the gate electrode (GE). The first transistor (T_SP1) may be electrically connected to the first anode electrode (AE1) through the connection pattern (CP).

[0216] A cathode electrode (CE) may be formed on the pixel circuit layer (PCL). For example, the cathode electrode (CE) may be formed to extend in the first direction (DR1) and cover the first to third sub-pixels (SP1 to SP3).

[0217] First to third anode electrodes (AE1 to AE3) may be formed on the pixel circuit layer (PCL). For example, the first to third anode electrodes (AE1 to AE3) may be formed to be spaced apart from the cathode electrode (CE) in the second direction (DR2). In addition, the first to third anode electrodes (AE1 to AE3) may be formed to be spaced apart from each other in the first direction (DR1) and to be isolated from each other.

[0218] According to an embodiment, the region where the first to third anode electrodes (AE1 to AE3) are formed may correspond to the region where the first to third light-emitting elements (LD1 to LD3, see FIG. 16), overcoat patterns (OCP1 to OCP3, see FIG. 16), and the first transparent electrode layer (ITO1, see FIG. 18) are arranged in subsequent processes.

[0219] A bank (BNK1) may be formed on the substrate (SUB). For example, the bank (BNK1) may have first openings (OP1) formed to surround two or more regions, respectively. The first openings (OP1) may expose a portion of the cathode electrode (CE) and may expose a portion of each of the first to third anode electrodes (AE1 to AE3).

[0220] In S110, first to third reflective electrodes (RFE1 to RFE3) can be formed on a substrate (SUB) (or pixel circuit layer (PCL)).

[0221] According to an embodiment, the first to third reflective electrodes (RFE1 to RFE3) may be formed by a photolithography process. Alternatively, the first to third reflective electrodes (RFE1 to RFE3) may be etched by various methods (wet etching, dry etching, etc.) and may be deposited by various methods (sputtering, chemical vapor deposition, etc.). However, the embodiments are not limited thereto.

[0222] First to third reflective electrodes (RFE1 to RFE3) may be formed on the first to third anode electrodes (AE1 to AE3), respectively. For example, the first to third reflective electrodes (RFE1 to RFE3) may be formed within the first openings (OP1) on the first to third anode electrodes (AE1 to AE3). The first to third reflective electrodes (RFE1 to RFE3) may be in contact with the first to third anode electrodes (AE1 to AE3) and may be electrically connected to each other.

[0223] According to an embodiment, the first to third reflective electrodes (RFE1 to RFE3) may overlap with areas where the first to third light-emitting elements (LD1 to LD3) are arranged in a subsequent process. Accordingly, the first to third reflective electrodes (RFE1 to RFE3) may form a reflective surface for forming a light recycling structure.

[0224] Fig. 16 is a plan view of the display device in S120 and S130 of Fig. 13. Fig. 17 is a cross-sectional view taken along line Ⅱ-Ⅱ' of Fig. 16.

[0225] Referring to FIGS. 13, 16 and 17, in S120, first to third overcoat patterns (OCP1 to OCP3) can be formed on first to third anode electrodes (AE1 to AE3).

[0226] According to an embodiment, the first to third overcoat patterns (OCP1 to OCP3) may be formed on a substrate (SUB) (or pixel circuit layer (PCL)) based on a process such as deposition.

[0227] The first to third overcoat patterns (OCP1 to OCP3) may be formed on the first to third anode electrodes (AE1 to AE3) within the first openings (OP1). The first to third overcoat patterns (OCP1 to OCP3) may extend in the second direction (DR2) and be formed to be spaced apart from each other in the first direction (DR1). In addition, the first to third overcoat patterns (OCP1 to OCP3) may partially cover the first to third anode electrodes (AE1 to AE3). For example, the first overcoat pattern (OCP1) may be arranged to overlap a portion of the first anode electrode (AE1). The second overcoat pattern (OCP2) may be arranged to overlap a portion of the second anode electrode (AE2). The third overcoat pattern (OCP3) may be arranged to overlap a portion of the third anode electrode (AE3).

[0228] In S130, first to third light-emitting elements (LD1 to LD3) can be arranged on first to third overcoat patterns (OCP1 to OCP3).

[0229] According to an embodiment, the first to third light-emitting elements (LD1 to LD3) may be arranged on a substrate (SUB) (or pixel circuit layer (PCL)) by various transfer methods. The first to third light-emitting elements (LD1 to LD3) may be arranged on the first to third overcoat patterns (OCP1 to OCP3), respectively. The first to third light-emitting elements (LD1 to LD3) may overlap the first to third overcoat patterns (OCP1 to OCP3), respectively.

[0230] Each of the first to third light-emitting elements (LD1 to LD3) may include first and second ends (EPT1, EPT2). Here, the first end (EPT1) may refer to a portion of a bonding electrode of each of the first to third light-emitting elements (LD1 to LD3). The second end (EPT2) may be spaced apart from the first end (EPT1) in a third direction (DR3). The second end (EPT2) may refer to a portion of an auxiliary layer of each of the first to third light-emitting elements (LD1 to LD3). For example, the second end (EPT2) of each of the first light-emitting elements (LD1_1 to LD1_2) may be arranged to face upward (e.g., in the third direction (DR3)). Accordingly, the first end (EPT1) of each of the first light-emitting elements (LD1_1 to LD1_2) can be in contact with the first overcoat pattern (OCP1). And the second end (EPT2) of each of the first light-emitting elements (LD1_1 to LD1_2) can be exposed.

[0231] Fig. 18 is a plan view of the display device in S140 of Fig. 13. Fig. 19 is a cross-sectional view taken along line Ⅱ-Ⅱ' of Fig. 18.

[0232] Referring to FIGS. 13, 18, and 19, in S140, a first transparent electrode layer (ITO1) can be formed on the first to third overcoat patterns (OCP1 to OCP3).

[0233] According to an embodiment, a first transparent electrode layer (ITO1) may be formed to overlap each of the first to third anode electrodes (AE1 to AE3). For example, the first transparent electrode layer (ITO1) may overlap a portion of the first overcoat pattern (OCP1) on the first anode electrode (AE1). The first transparent electrode layer (ITO1) may overlap a portion of the second overcoat pattern (OCP2) on the second anode electrode (AE2). The first transparent electrode layer (ITO1) may overlap a portion of the third overcoat pattern (OCP3) on the third anode electrode (AE3).

[0234] In the first openings (OP1), the first transparent electrode layer (ITO1) can be in contact with a portion of the first to third anode electrodes (AE1 to AE3). The first transparent electrode layer (ITO1) can be in contact with the first to third overcoat patterns (OCP1 to OCP3) and the first end (EPT1) of each of the first to third light-emitting elements (LD1 to LD3). For example, the first transparent electrode layer (ITO1) can be in contact with a side surface (EPT1_SS) of each of the bonding electrodes (BDE1_1 to BDE3_1). The first transparent electrode layer (ITO1) can also be in contact with a portion of a side surface (SPT) disposed between the first end (EPT1) and the second end (EPT2) of each of the first to third light-emitting elements (LD1 to LD3).

[0235] The first transparent electrode layer (ITO1) may be electrically connected to the first end (EPT1) of each of the first to third light-emitting elements (LD1 to LD3). For example, the first end (EPT1) of each of the first light-emitting elements (LD1_1, LD1_2) may be electrically connected to the first anode electrode (AE1) through the first transparent electrode layer (ITO1).

[0236] Although not shown in FIGS. 18 and 19, another transparent electrode layer overlapping the cathode electrode (CE) may be additionally formed on the same layer as the first transparent electrode layer (ITO1). However, the other transparent electrode layer may extend in the first direction (DR1) and be arranged across the first to third sub-pixels (SP1 to SP3). In addition, the other transparent electrode layer may be arranged spaced apart from the first transparent electrode layer (ITO1) in the second direction (DR2), so as not to overlap the first to third overcoat patterns (OCP1 to OCP3).

[0237] Fig. 20 is a plan view of the display device in S150 of Fig. 13. Fig. 21 is a cross-sectional view taken along line Ⅱ-Ⅱ' of Fig. 20.

[0238] Referring to FIGS. 13, 20 and 21, in S150, at least one insulating layer (INS) can be formed on the first transparent electrode (ITO1) and the cathode electrode (CE).

[0239] According to an embodiment, at least one insulating layer (INS) may include a first insulating layer (INS1) disposed on the first to third anode electrodes (AE1 to AE3) and the cathode electrode (FE), respectively, and a second insulating layer (INS2) disposed on the first insulating layer (INS1).

[0240] The first insulating layer (INS1) may be disposed in the first openings (OP1) formed by the first bank (BNK1). The first insulating layer (INS1) may be provided within an area surrounded by the first bank (BNK1). For example, the first insulating layer (INS1) may be disposed to overlap each of the first transparent electrode layer (ITO1) and the cathode electrode (CE). The first insulating layer (INS1) may be disposed directly on the first transparent electrode layer (ITO1) and may be in contact with the first transparent electrode layer (ITO1).

[0241] The second insulating layer (INS2) may be entirely disposed on the first insulating layer (INS1). For example, the second insulating layer (INS2) may cover the first insulating layer (INS1) and provide a substantially flat upper surface. The second insulating layer (INS2) may be directly disposed on the first insulating layer (INS1) and may be in contact with the first insulating layer (INS1). The second insulating layer (INS2) may be in contact with the upper surface of the first bank (BNK1) on which the first insulating layer (INS1) is not disposed. In addition, the second insulating layer (INS2) may be in contact with the side surface (SPT) of each of the first light-emitting elements (LD1_1, LD1_2).

[0242] Referring to FIGS. 20 and 21, the first and second insulating layers (INS1, INS2) can be arranged on the first to third anode electrodes (AE1 to AE3) and the cathode electrode (CE) without overlapping with the first to third light-emitting elements (LD1 to LD3).

[0243] According to an embodiment, at least one insulating layer (INS) may be formed on the substrate (SUB) (or pixel circuit layer (PCL)) based on a process such as deposition. For example, after the at least one insulating layer (INS) is formed, an additional etching process may be further performed. For example, the first insulating layer (INS1) may be formed on the first to third anode electrodes (AE1 to AE3) and the cathode electrode (CE), respectively, through an additional etching process using a halftone mask.

[0244] Fig. 22 is a plan view of the display device in S160 of Fig. 13. Fig. 23 is a cross-sectional view taken along line Ⅱ-Ⅱ' of Fig. 22.

[0245] Referring to FIGS. 13, 22, and 23, in S160, a second transparent electrode layer (ITO2) may be formed on at least one insulating layer (INS). For example, the second transparent electrode layer (ITO2) may extend in the second direction (DR2) as well as the first direction (DR1) on the at least one insulating layer (INS). The second transparent electrode layer (ITO2) may be arranged across the first to third sub-pixels (SP1 to SP3) to serve as a common electrode.

[0246] According to an embodiment, a contact hole (CTH) penetrating at least one insulating layer (INS) may be formed. For example, the contact hole (CTH) may overlap the cathode electrode (CE). In addition, the contact hole (CTH) may be spaced apart from the first to third light-emitting elements (LD1 to LD3) in the second direction (DR2) without overlapping with the first to third light-emitting elements (LD1 to LD3).

[0247] Thereafter, the second transparent electrode layer (ITO2) can be connected to the cathode electrode (CE) through the contact hole (CTH). For example, the second transparent electrode layer (ITO2) and the cathode electrode (CE) can be connected by filling the contact hole (CTH) with the same material as the second transparent electrode layer (ITO2).

[0248] In S160, the second end (EPT2) of each of the first light-emitting elements (LD1_1, LD1_2) and the second transparent electrode layer (ITO2) can be in contact. The second transparent electrode layer (ITO2) can be directly disposed on the second end (EPT2) of each of the first light-emitting elements (LD1_1, LD1_2). That is, the cathode electrode (CE) and the first light-emitting elements (LD1_1, LD1_2) can be electrically connected through the second transparent electrode layer (ITO2).

[0249] Afterwards, a capping layer (CPL) covering each layer of the display element layer (DPL) can be formed.

[0250] Fig. 24 is a block diagram showing an embodiment of a display system.

[0251] Referring to FIG. 24, the display system (1000) may include a processor (1100) and a display device (1200).

[0252] The processor (1100) can perform various tasks and calculations. In embodiments, the processor (1100) may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor (1100) can be connected to other components of the display system (1000) via a bus system and control them.

[0253] The processor (1100) can transmit image data (IMG) and a control signal (CTRL) to the display device (1200). The display device (1200) can display an image based on the image data (IMG) and the control signal (CTRL). The display device (1200) can be configured similarly to the display device (1200) described with reference to FIG. 1. In this case, the image data (IMG) and the control signal (CTRL) can be provided as the input image data (IMG) and the control signal (CTRL) of FIG. 1, respectively.

[0254] The display system (1000) may include a computing system that provides an image display function, such as a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer, a watch phone, an automotive display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra mobile personal computer (UMPC), etc. In addition, the display system (1000) may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0255] Figures 25 to 28 are perspective views showing application examples of the display system of Figure 24.

[0256] Referring to FIG. 25, the display system (1000) of FIG. 24 can be applied to a smart watch (2000) including a display portion (2100) and a strap portion (2200).

[0257] The smartwatch (2000) may be a wearable electronic device. For example, the smartwatch (2000) may have a structure in which a strap portion (2200) is attached to the user's wrist. Here, a display system (1000) and / or a display device (1200) may be applied to the display portion (2100), so that image data including time information may be provided to the user.

[0258] Referring to FIG. 26, the display system (1000) of FIG. 24 can be applied to an automotive display system (3000). Here, the automotive display system (3000) can include a computing system provided inside and / or outside a vehicle to provide image data.

[0259] For example, the display system (1000) and / or the display device (1200) may be applied to at least one of an infotainment panel (3100), a cluster (3200), a co-driver display (3300), a head-up display (3400), a side mirror display (3500), and a rear seat display (3600) provided in a vehicle.

[0260] Referring to FIG. 27, the display system (1000) of FIG. 24 can be applied to smart glasses (4000). The smart glasses (4000) may be a wearable electronic device that can be worn on a user's head. For example, the smart glasses (4000) may be a wearable device for augmented reality.

[0261] Smart glasses (4000) may include a frame (4100) and a lens unit (4200). The frame (4100) may include a housing (4110) that supports the lens unit (4200) and a leg unit (4120) for a user to wear. The leg unit (4120) is connected to the housing (4110) via a hinge and may be folded or unfolded relative to the housing (4110).

[0262] The frame (4100) may be equipped with a battery, a touch pad, a microphone, a camera, etc. In addition, the frame (4100) may be equipped with a projector that outputs light, a processor that controls light signals, etc.

[0263] The lens unit (4200) may include an optical member that transmits or reflects light. For example, the lens unit (4200) may include glass, transparent synthetic resin, or the like.

[0264] In order for the user's eyes to recognize visual information, the lens unit (4200) can reflect an image by an optical signal transmitted from the projector of the frame (4100) onto the rear surface of the lens unit (4200) (e.g., the surface facing the user's eyes). For example, the user can recognize visual information such as the time and date displayed on the lens unit (4200). At this time, the projector and / or the lens unit (4200) may be a type of display device. The display device (1200) may be applied to the projector and / or the lens unit (4200).

[0265] Referring to FIG. 28, the display system (1000) of FIG. 24 can be applied to a head-mounted display device (5000).

[0266] The head-mounted display device (5000) may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device (5000) may be a wearable device for virtual reality or mixed reality.

[0267] A head-mounted display device (5000) may include a head-mounted band (5100) and a display device storage case (5200). The head-mounted band (5100) may be connected to the display device storage case (5200). The head-mounted band (5100) may include horizontal bands and / or vertical bands for securing the head-mounted display device (5000) to a user's head. The horizontal band may be configured to surround the side of the user's head, and the vertical band may be configured to surround the upper portion of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band (5100) may be implemented in the form of eyeglass frames, helmets, etc.

[0268] The display device storage case (5200) can store the display system (1000) and / or the display device (1200).

[0269] In the display device according to embodiments of the present invention, the first transparent electrode layer (ITO1) connected to the first to third anode electrodes (AE1 to AE3) is formed to be in contact with the first end (EPT1) of the first to third light-emitting elements (LD1_1 to LD3_1), and the second transparent electrode layer (ITO2) connected to the cathode electrode (CE) is formed to be in contact with the second end (EPT2) of the first to third light-emitting elements (LD1_1 to LD3_1), thereby increasing the contact area and improving stability.

[0270] Although specific embodiments and applications have been described herein, other embodiments and variations may be derived from the above description. Accordingly, the scope of the present invention is not limited to these embodiments, but extends to the claims set forth below, various obvious modifications, and equivalents.

Claims

1. A substrate extending in a first direction and a second direction intersecting the first direction; Including a display element layer arranged on the substrate in a third direction intersecting the first and second directions, The above display element layer, An anode electrode and a cathode electrode spaced apart from each other in the second direction on the substrate; An overcoat pattern disposed on the anode electrode; A light emitting element disposed on the overcoat pattern, the light emitting element including a first end adjacent to the overcoat pattern and a second end spaced apart from the first end in the third direction; A first transparent electrode layer disposed on the overcoat pattern and electrically connecting the anode electrode and the first end of the light-emitting element; At least one insulating layer disposed on the first transparent electrode layer and the cathode electrode; A display device comprising a second transparent electrode layer disposed on at least one insulating layer and electrically connecting the cathode electrode and the second end of the light-emitting element.

2. In paragraph 1, A display device in which the second transparent electrode layer is in contact with the second end of the light-emitting element and is electrically connected to the cathode electrode through a contact hole penetrating at least one insulating layer.

3. In paragraph 2, The above contact hole is a display device overlapping the above cathode electrode.

4. In paragraph 2, A display device in which the contact hole is spaced apart from the light-emitting element in the second direction without overlapping with the light-emitting element.

5. In paragraph 1, The first transparent electrode layer is in contact with the overcoat pattern and the first end of the light-emitting element, A display device in which the second transparent electrode layer is in contact with the second end of the light-emitting element.

6. In paragraph 5, A display device in which the above overcoat pattern is disposed between the anode electrode and the first end of the light-emitting element.

7. In paragraph 6, A display device in which the first end of the light-emitting element is in contact with the overcoat pattern.

8. In paragraph 5, At least one insulating layer, A first insulating layer disposed on each of the anode electrode and the cathode electrode; A display device comprising a second insulating layer disposed on the first insulating layer.

9. In paragraph 8, A display device in which the first insulating layer is in contact with the first transparent electrode layer.

10. In paragraph 8, The light emitting element has a side surface disposed between the first end and the second end, A display device in which the second insulating layer is in contact with the side surface of the light-emitting element.

11. In paragraph 1, A display device wherein the first and second transparent electrode layers are spaced apart from each other in the third direction with at least one insulating layer therebetween and contain the same material.

12. In paragraph 1, Further comprising a bank disposed on the anode electrode and the cathode electrode, the bank having openings exposing a portion of each of the anode electrode and the cathode electrode, A display device in which a portion of the anode electrode and the first transparent electrode layer are in contact with each other in one of the openings of the bank.

13. A substrate extending in a first direction and a second direction intersecting the first direction; Including a display element layer arranged on the substrate in a third direction intersecting the first and second directions, The above display element layer, An anode electrode disposed on the substrate; An overcoat pattern disposed on the anode electrode; A light emitting element disposed on the overcoat pattern, the light emitting element including a first end adjacent to the overcoat pattern and a second end spaced apart from the first end in the third direction; A first transparent electrode layer disposed on the overcoat pattern and electrically connecting the anode electrode and the first end of the light-emitting element; At least one insulating layer disposed on the first transparent electrode layer; and A cathode electrode disposed on at least one insulating layer and connected to the second end of the light emitting element, A display device in which the first transparent electrode layer is in contact with the first end of the light-emitting element.

14. In paragraph 13, A display device in which the first transparent electrode layer is in contact with the first end of the light-emitting element and the overcoat pattern.

15. In paragraph 13, A display device in which the above overcoat pattern is disposed between the anode electrode and the first end of the light-emitting element.

16. In paragraph 13, A display device in which the first end of the light-emitting element is in contact with the overcoat pattern.

17. Display device; and Including the substrate, The above display device includes the display element layer of claim 1, An electronic device in which the display element layer is disposed on the substrate.

18. In paragraph 17, The electronic device is at least one of a smartwatch, a mobile phone, a smart phone, a portable computer, a tablet PC, a watch phone, an automotive display, a smart glass, a PMP, a navigation device, an UMPC, a head-mounted display device, a virtual reality device, a mixed reality device, and an augmented reality device.

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