Semiconductor device and method for manufacturing same

Abstract

The present invention relates to a semiconductor device and a method for manufacturing same. The method for manufacturing the semiconductor device comprises the steps of: forming an epitaxial layer on a substrate; forming a plurality of trenches by etching a part of the epitaxial layer; forming source electrodes and drain electrodes in the plurality of preset trenches; forming a gate electrode and a temperature detection sensor unit at a set position of the epitaxial layer; and forming an insulating layer for insulating the gate electrode and the temperature detection sensor unit.

Description

Semiconductor devices and their manufacturing methods

[0001] The disclosed invention relates to a semiconductor device capable of real-time temperature detection and a method for manufacturing the same.

[0002] As 5G communications services expand, the need for high-power, high-frequency, wideband, and high-efficiency transistors operating in high-speed switching and high-voltage environments is increasing. Gallium nitride (GaN) transistors, which have emerged to meet these demanding performance requirements, are attracting significant attention due to their high-speed switching performance compared to conventional silicon (Si) transistors, making them suitable for ultra-high-speed signal processing. Furthermore, the material's inherent high-voltage characteristics make them suitable for stable application in high-voltage environments.

[0003] High electron mobility transistors (HEMTs) using gallium nitride (GaN) materials can increase electron mobility by utilizing the two-dimensional electron gas (2DEG) generated at the interface between heterogeneous materials such as AlxGaN / GaN, making them suitable for high-speed signal transmission.

[0004] Additionally, it has a band gap voltage that is approximately three times higher than that of silicon (Si) and an insulation breakdown field that is 10 times higher, ensuring stable operation in high temperature environments and high operating voltages.

[0005] Since these high electron mobility transistors have very high output in a single package state, very high heat is generated when the semiconductor device operates. Therefore, in a semiconductor package system including the semiconductor device, heat dissipation measures and a temperature sensor must be separately installed inside the package system to monitor the temperature to prevent such thermal runaway from occurring, thereby controlling excessive temperature rise in the semiconductor package system.

[0006] In this case, due to limitations in the package system design, the temperature sensor is placed far from the gallium nitride (GaN) transistors, which generate high heat, i.e., on the periphery of the package. This package system design structure presents a problem in that it cannot accurately monitor the temperature inside the semiconductor device.

[0007] Specifically, there is a difference between the temperature around the package and the temperature inside the semiconductor device. Since the temperature around the package is monitored, if the temperature inside the semiconductor device exceeds the expected standard, the temperature inside the semiconductor device cannot be accurately measured, resulting in failure cases due to overheating of the system package.

[0008] Accordingly, when configuring a semiconductor package system including semiconductor devices, it is necessary to improve the design structure to accurately measure the temperature within the semiconductor devices.

[0009] One aspect of the disclosed invention is to provide a semiconductor device and a method for manufacturing the same, which includes a real-time temperature detection function, can simultaneously manufacture a temperature detection sensor unit without an additional process step during the manufacturing process of a gallium nitride (GaN) transistor, and can provide an isolation region in a shape that surrounds the lower part of the temperature detection sensor unit.

[0010] A method for manufacturing a semiconductor device according to one aspect of the disclosed invention may include the steps of forming an epi layer on a substrate; etching a portion of the epi layer to form a plurality of trenches; forming a source electrode and a drain electrode in each of the plurality of preset trenches; forming a gate electrode and a temperature detection sensor unit at preset positions of the epi layer; and forming an insulating layer that insulates the gate electrode and the temperature detection sensor unit.

[0011] The method for manufacturing the semiconductor device further includes a step of forming an isolation region at a set position of the epi layer; and in the step of forming the isolation region, the isolation region can be formed in a selected trench among the plurality of trenches with a set shape and volume.

[0012] The above-mentioned isolation region is formed in a shape that surrounds the lower part of the temperature detection sensor unit in the above-mentioned selected trench, and the temperature detection sensor unit can be formed on the above-mentioned isolation region by filling the inside of the above-mentioned selected trench.

[0013] In the step of forming the gate electrode and the temperature detection sensor unit, at least one of nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), iridium (Ir), platinum (Pt), and gold (Au) or an alloy thereof is deposited or plated on the upper portion of the epi layer and then patterned in a set pattern to form the gate electrode and the temperature detection sensor unit simultaneously.

[0014] According to another aspect of the disclosed invention, a semiconductor device comprises: a substrate; an epi layer provided on the substrate; a source electrode provided on the epi layer; a drain electrode provided on the epi layer and spaced apart from the source electrode; a gate electrode provided between the source electrode and the drain electrode on an upper surface of the epi layer; a temperature detection sensor unit provided at a set position on the epi layer and configured to detect temperature; and an insulating layer provided on the epi layer and the gate electrode; wherein a lower portion of the temperature detection sensor unit may be disposed on a position line corresponding to a position of a lower surface of at least one of the source electrode and the drain electrode.

[0015] The semiconductor element may further include an isolation region arranged below the temperature detection sensor unit and formed in a shape that surrounds the temperature detection sensor unit.

[0016] The temperature detection sensor unit may include at least one temperature detection electrode pad; and a temperature detection electrode connected to the temperature detection electrode pad and extending in a set direction.

[0017] The temperature detection electrode may be connected to a plurality of temperature detection electrode pads at one side and the other side, and an intermediate portion between the one side and the other side may extend along the length direction of the source electrode or the drain electrode, adjacent to at least one of the source electrode and the drain electrode.

[0018] The temperature detection electrode may have one side connected to the temperature detection electrode pad, the other side connected to the source electrode, and an intermediate portion between the one side and the other side may extend along the length direction of the source electrode or the drain electrode, adjacent to at least one of the source electrode and the drain electrode.

[0019] According to one aspect of the disclosed invention, the functionality and reliability of the device can be improved by including a real-time temperature detection function.

[0020] In addition, according to one aspect of the disclosed invention, a temperature detection sensor unit can be manufactured simultaneously during the manufacturing process of a gallium nitride (GaN) transistor without an additional process step, thereby detecting the exact temperature of the transistor without increasing the manufacturing cost, thereby providing data in real time to prevent thermal runaway from occurring in a system to which the transistor is applied.

[0021] In addition, according to one aspect of the disclosed invention, a temperature detection sensor unit is formed very close to a two-dimensional electron gas in an ohmic window recess etching process for forming an ohmic electrode, thereby enabling very accurate channel temperature detection.

[0022] In addition, according to one aspect of the disclosed invention, by applying an isolation process that provides an isolation region in a shape that surrounds the lower part of a temperature detection sensor unit, the temperature can be detected in the central region where heat generation is highest in a semiconductor element in which a plurality of gates are formed without interfering with the operation of the transistor.

[0023] In addition, according to one aspect of the disclosed invention, since a separate circuit for temperature detection of the transistor is not required, the size of the transistor including the temperature detection function can be drastically reduced.

[0024] In addition, according to one aspect of the disclosed invention, an additional temperature sensor for temperature monitoring of a system to which a compound semiconductor transistor is applied is not required, thereby reducing costs when implementing the system.

[0025] In addition, according to one aspect of the disclosed invention, since temperature detection is possible in real time during operation of the transistor, external control is possible to prevent thermal runaway of the transistor, thereby ensuring the operational stability of the semiconductor device and greatly improving reliability.

[0026] FIG. 1 is a drawing showing a planar structure of a semiconductor device according to one embodiment of the present invention.

[0027] Figure 2 is a drawing showing a cross-section taken along the dashed line I-I' of Figure 1.

[0028] FIG. 3 is a drawing showing a planar structure of a semiconductor device according to another embodiment of the present invention.

[0029] Figure 4 is a drawing showing a cross-section taken along the dashed line II-II' of Figure 3.

[0030] FIG. 5 is a drawing showing a planar structure of a semiconductor device according to another embodiment of the present invention.

[0031] FIGS. 6A to 6J are drawings showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0032] Throughout the specification, the same reference numerals denote the same components. This specification does not describe all elements of the embodiments, and any content that is general in the technical field to which the disclosed invention belongs or that overlaps between the embodiments is omitted. The terms 'part, module, element, block' used in the specification may be implemented in software or hardware, and depending on the embodiments, multiple 'parts, modules, elements, blocks' may be implemented as a single component, or a single 'part, module, element, block' may include multiple components.

[0033] Throughout the specification, when a part is said to be 'connected' to another part, this includes not only direct connection but also indirect connection, and indirect connection includes connection via a wireless communication network.

[0034] Additionally, when a part is said to 'include' a component, this does not mean that it excludes other components, but rather that it may include other components, unless otherwise specifically stated.

[0035] Throughout the specification, when we say that an element is located 'on' another element, this includes not only cases where the element is in contact with the other element, but also cases where another element exists between the two elements.

[0036] The terms first, second, etc. are used to distinguish one component from another, and the components are not limited by the aforementioned terms.

[0037] Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0038] The identification codes for each step are used for convenience of explanation and do not describe the order of each step. Each step may be performed in a different order than specified unless the context clearly indicates a specific order.

[0039] Hereinafter, the operating principle and embodiments of the disclosed invention will be described with reference to the attached drawings.

[0040] Fig. 1 is a drawing showing a planar structure of a semiconductor device according to one embodiment of the present invention. Fig. 2 is a drawing showing a cross-section taken along dashed-dotted line I-I' of Fig. 1.

[0041] Referring to FIGS. 1 and 2, a semiconductor device according to one embodiment of the present invention may include a substrate (110), an epi layer (120), a plurality of ion implantation regions (130), a source electrode (160), a drain electrode (170), a gate electrode (180), a temperature detection sensor unit (190), a plurality of isolation regions (200), an insulating layer (210), a field plate (240), and a lower conductive layer (320).

[0042] The substrate (110) may be a silicon carbide (SiC) substrate, a silicon (Si) substrate, or a sapphire (Al2O3) substrate.

[0043] The epi layer (120) is a nitride semiconductor layer and may include a first compound semiconductor layer (121) and a second compound semiconductor layer (122) sequentially arranged on top of the substrate (110).

[0044] The first compound semiconductor layer (121) is a buffer layer and may be formed of a layer including gallium nitride (GaN), aluminum gallium nitride (AlGaN), or aluminum nitride (AlN).

[0045] The second compound semiconductor layer (122) is a barrier layer and may be formed of one or more layers including one or more selected from gallium nitride (GaN) and aluminum gallium nitride (AlGaN). For example, the second compound semiconductor layer (122) may be a gallium nitride (GaN) layer, Al x Ga y N(x+y=1) layers, Al x In y N(x+y=1) layer and Al x In y Ga z It can be formed by two or more multilayers among N(x+y+z=1) layers.

[0046] The first compound semiconductor layer (121) can have a channel region (125) formed by a two-dimensional electron gas (2DEG) generated at the top of the first compound semiconductor layer (121) through heterojunction with the second compound semiconductor layer (122).

[0047] The epilayer (120) can be grown on the substrate (110) using various known methods such as MOCVD (Metal-Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), and HVPE (Hydride Vapor Phase Epitaxy). At this time, the growth height of the epilayer (120) can be set to about 0.1 μm to about 5 μm. More preferably, the epilayer (120) can be set to a total thickness of about 2 μm.

[0048] A plurality of ion implantation regions (130) may be provided at a plurality of set positions of the epi layer (120). Specifically, the plurality of ion implantation regions (130) may be arranged at positions corresponding to the source electrode (160) and the drain electrode (170), respectively. For example, the plurality of ion implantation regions (130) may be provided in the epi layer (120) located below each of the source electrode (160) and the drain electrode (170), respectively. At this time, each of the plurality of ion implantation regions (130) may be provided at least in a size corresponding to the area in which each of the source electrode (160) and the drain electrode (170) is in contact with the first compound semiconductor layer (121).

[0049] Additionally, multiple ion implantation regions (130) can be prepared by implanting an n-type dopant into at least a portion of the epi layer (120).

[0050] The source electrode (160) includes a conductive material and may be provided at a set position on the first compound semiconductor layer (121). Here, a portion of the source electrode (160) may be provided inside a trench (140) formed from the second compound semiconductor layer (122) to the first compound semiconductor layer (121). In addition, the source electrode (160) may be disposed on the upper portion of the ion implantation region (130) exposed by the trench (140). In addition, a portion of the area of ​​the source electrode (160) may be in contact with the second compound semiconductor layer (122). The source electrode (160) may be electrically connected to the lower conductive layer (320) formed on the back surface of the substrate (110) and the via hole (310) of the back surface. The lower conductive layer (320) is a metal layer that connects the upper source electrode (160) and the lower ground electrode, and can be prepared by depositing or plating at least one of titanium (Ti) and gold (Au) or an alloy thereof.

[0051] The drain electrode (170) includes a conductive material and may be provided at a set position on the first compound semiconductor layer (121) spaced apart from the source electrode (160). Here, the drain electrode (170) may be provided inside a trench (140) formed so that a portion thereof passes through the second compound semiconductor layer (122) to the first compound semiconductor layer (121). In addition, the drain electrode (170) may be disposed on the upper portion of the ion implantation region (130) exposed by the trench (140). In addition, a portion of the area of ​​the drain electrode (170) may be in contact with the second compound semiconductor layer (122). Here, the area at which the source electrode (160) and the drain electrode (170) are in contact with the second compound semiconductor layer (122) may be the same or different depending on the transistor design. The drain electrode (170) may be connected to a drain pad (174).

[0052] Here, each of the source electrode (160) and the drain electrode (170) may be formed in multiple layers to withstand high current and RF power while lowering the contact resistance. As an example, the source electrode (160) may include a first source electrode layer (161) and a second source electrode layer (162), and the drain electrode (170) may include a first drain electrode layer (171) and a second drain electrode layer (172). At this time, each of the first source electrode layer (161) and the second source electrode layer (162) may include at least one of titanium (Ti), silicon (Si), nickel (Ni), platinum (Pt), and gold (Au) or an alloy thereof. In addition, each of the first drain electrode layer (171) and the second drain electrode layer (172) may include at least one of titanium (Ti), silicon (Si), nickel (Ni), platinum (Pt), and gold (Au) or an alloy thereof.

[0053] A trench (140) may be prepared by etching the epi layer (120) and the ion implantation region (130) until a portion of the ion implantation region (130) remains. At this time, the trench (140) may be prepared corresponding to the positions of the source electrode (160), the drain electrode (170), and the temperature detection sensor unit (190), respectively.

[0054] Meanwhile, when an ohmic contact is formed without being recessed, i.e., without forming a trench (140), the source electrode (160) and the drain electrode (170) are formed at a location far from the channel region (125) through which the two-dimensional electron gas (2DEG) moves, so that the contact resistance may be relatively high. On the other hand, as in the present invention, when an ohmic recess in the shape of a trench (140) is formed in the epi layer (120) and the ion implantation region (130) and the source electrode (160) and the drain electrode (170) are formed as an ohmic contact, the source electrode (160) and the drain electrode (170) may be formed at a location relatively close to the channel region (125) through which the two-dimensional electron gas (2DEG) moves.

[0055] Accordingly, as the contact resistance becomes relatively small, the adhesion between the electrode material forming the source electrode (160) and the drain electrode (170) can be improved.

[0056] The gate electrode (180) includes a conductive material and may be provided on the upper surface of the second compound semiconductor layer (122) between the source electrode (160) and the drain electrode (170). This gate electrode (180) may be connected to a gate pad (184).

[0057] Meanwhile, the temperature detection sensor unit (190) includes a temperature detection electrode pad (191) and a temperature detection electrode (192). Since the temperature detection sensor unit (190) can detect a change in resistance depending on temperature, it can be provided at a set location to detect the temperature when heat is generated in a semiconductor element.

[0058] Specifically, the temperature detection sensor unit (190) may be arranged adjacent to the source electrode (160) or the drain electrode (170). More specifically, the temperature detection sensor unit (190) may be arranged so as to accurately measure the maximum temperature generated at the center of a small unit element (transistor) or a large-area (high-power) transistor having tens of gates arranged. The temperature detection sensor unit (190) may be arranged so as to be located in the center region where heat generation is the highest and close to the channel region (125) through which the two-dimensional electron gas moves. In addition, the temperature detection sensor unit (190) may be arranged at a depth where the lower portion corresponds to the lower portion of at least one of the source electrode (160) and the drain electrode (170).

[0059] For example, the temperature detection sensor unit (190) may be placed in a trench (140) formed to a depth that passes the bonding interface between the first compound semiconductor layer (121) and the second compound semiconductor layer (122). At this time, the lower portion of the temperature detection sensor unit (190) may be placed on a position line that substantially corresponds to the position of the lower surface of at least one of the source electrode (160) and the drain electrode (170). This temperature detection sensor unit (190) may be placed as close as possible to the channel region (125) where the two-dimensional electron gas is trapped, so as to precisely measure the temperature.

[0060] An isolation region (200) may be provided at a set location of the epi layer (120) for isolation between adjacent semiconductor elements. For example, the isolation region (200) may be provided in a set shape and volume in a trench (140) selected among a plurality of set trenches (140) for isolating semiconductor elements.

[0061] An isolation region (200) where a temperature detection sensor unit (190) is positioned can be provided at the bottom of the temperature detection sensor unit (190) so that the temperature detection sensor unit (190) can be protected without electrically affecting the source electrode (160), the drain electrode (170), and the gate electrode (180). At this time, the isolation region (200) can be provided in a shape that surrounds the bottom of the temperature detection sensor unit (190). The isolation region (200) can electrically isolate the temperature detection sensor unit (190) and the channel region (125) while performing an electrical blocking role that blocks the generation of leakage current to the outside of the semiconductor element.

[0062] For example, the isolation region (200) can be expanded by a volume set through an ion implantation process in a part of the epi layer (120) where the trench (140) is formed, thereby blocking the movement of a two-dimensional electron gas in the channel region (125). However, the isolation region (200) can also be prepared through etching of the epi layer (120) as well as through the ion implantation process.

[0063] The insulating layer (210) can insulate and protect each of the source electrode (160), the drain electrode (170), the gate electrode (180), and the temperature detection sensor unit (190) from external force. Specifically, the insulating layer (210) can include a first insulating layer (220) for insulating and protecting each of the source electrode (160), the drain electrode (170), the gate electrode (180), and the temperature detection sensor unit (190), and a second insulating layer (230) for insulating and protecting the field plate (240). The insulating layer (210) can include silicon nitride (SiN), silicon oxide (SiO2), aluminum nitride (AlN), and a nitride or oxide combined therewith.

[0064] The first insulating layer (220) covers the second compound semiconductor layer (122), the gate electrode (180), and the temperature detection sensor unit (190), and can insulate them. The first insulating layer (220) can be provided so that a portion of each of the source electrode (160) and the drain electrode (170) is exposed.

[0065] The second insulating layer (230) covers the first insulating layer (220) and the field plate (240), and can insulate the field plate (240) from the drain electrode (170). The second insulating layer (230) can be provided so that a portion of each of the source electrode (160) and the drain electrode (170) is exposed.

[0066] The field plate (240) may be placed on the upper side of the gate electrode (180) and on the upper side of the second insulating layer (230) to increase the breakdown voltage of the transistor element. In addition, the field plate (240) may be connected to the source electrode (160), although not shown.

[0067] In conventional semiconductor devices, when a lot of heat is generated in the ohmic electrode or the channel region (125) through which the two-dimensional electron gas (2DEG) moves during device operation, it is difficult to directly measure the heat in the ohmic electrode or the channel region (125) due to limitations in the structural design of the semiconductor package system including the semiconductor device. Accordingly, there was a problem in that the heat (SS) generated inside the device could not be precisely monitored.

[0068] In order to solve this problem, the semiconductor device according to one embodiment of the present invention can detect an accurate temperature by allowing the temperature detection electrode (192) of the temperature detection sensor unit (190) to be positioned at a location closest to a location where the most heat is generated or a location where the temperature is the highest, for example, between semiconductor devices in which a plurality of source electrodes (160) and drain electrodes (170) are repeatedly arranged or between transistor cells.

[0069] Specifically, the temperature detection sensor unit (190) may be provided in a trench (140) formed by etching up to the channel region (125). For example, the temperature detection electrode (192) of the temperature detection sensor unit (190) may be placed in a trench (140) formed at a position set through an ohmic window recess etching process for forming at least one of the source electrode (160) and the drain electrode (170), so as to be placed very close to the channel region (125) through which the two-dimensional electron gas moves. Through this, the temperature detection sensor unit (190) may be placed as close as possible to the channel region (125) through which the two-dimensional electron gas (2DEG) moves, and may effectively detect the temperature.

[0070] The temperature detection sensor unit (190) may be formed in a "T" shape or an "I" shape. At this time, as mentioned above, the temperature detection sensor unit (190) may include at least one temperature detection electrode pad (191) positioned at a set position to effectively detect the temperature of the central portion of the semiconductor element, and a temperature detection electrode (192) connected to the temperature detection electrode pad (191) and extending in a uniaxial direction.

[0071] In another embodiment, the temperature detection sensor unit (190) may include at least one temperature detection electrode pad (191) arranged on at least one side of the gate pad (184), as illustrated in FIG. 3, and a temperature detection electrode (192) extending in a set shape from the temperature detection electrode pad (191).

[0072] For example, a temperature detection electrode (192) is connected to a plurality of temperature detection electrode pads (191) arranged on both sides of a gate pad (184) at one side and the other side, and a middle portion between the one side and the other side may be adjacent to at least one of a source electrode (160) and a drain electrode (170) and may extend along the length direction of the source electrode (160) or the drain electrode (170).

[0073] In another embodiment, the temperature detection sensor unit (190) may include at least one temperature detection electrode pad (191) arranged on at least one side of the gate pad (184), as illustrated in FIG. 5, and a temperature detection electrode (192) extending from the temperature detection electrode pad (191) in a set shape and connected to the source electrode (160).

[0074] For example, a temperature detection electrode (192) may have one side connected to one of a plurality of temperature detection electrode pads (191) arranged on both sides of a gate pad (184), the other side connected to one side of a source electrode (160), and an intermediate portion between the one side and the other side may be adjacent to at least one of the source electrode (160) and the drain electrode (170) and may extend along the length direction of the source electrode (160) or the drain electrode (170).

[0075] In addition, the temperature detection sensor unit (190) has a pair (Z) of temperature detection electrodes (192) connected to a source electrode (160) connected to a lower conductive layer (320) through a via hole (310), so that even if one temperature detection electrode (192) is disconnected, another one can replace it and measure resistance.

[0076] The temperature detection sensor unit (190) implemented in various embodiments as described above can directly detect the highest temperature by positioning the temperature detection electrode (192) at the location where the highest heat (SS) is generated in the semiconductor element.

[0077] According to one embodiment of the present invention, a semiconductor device has a temperature detection sensor unit positioned very close to a channel region (125) through which a two-dimensional electron gas moves, so that a very accurate channel temperature can be detected.

[0078] In addition, a semiconductor device according to one embodiment of the present invention provides an isolation region in a shape that surrounds the lower part of a temperature detection sensor unit, so as not to interfere with the operation of the device, and can detect the temperature in a central region where the heat generation of the device is the highest, in which several to dozens or more gates are formed.

[0079] In addition, the semiconductor device according to one embodiment of the present invention does not require a separate external circuit, such as an MMIC (Monolithic Microwave Integrated Circuit), for temperature detection of the transistor, so that the size of the transistor including the temperature detection function can be drastically reduced and miniaturized.

[0080] In addition, a semiconductor device according to one embodiment of the present invention can detect temperature in real time during device operation, thereby enabling external control to prevent thermal runaway of the device, thereby improving stable operation and reliability of the device.

[0081] In addition, the semiconductor device according to one embodiment of the present invention can reduce costs because it does not require an additional temperature sensor for temperature monitoring.

[0082] Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described step by step. The method may include a step of forming an epi layer on a substrate, a step of forming an ion implantation region at a set position of the epi layer, a step of etching a portion of the epi layer and a portion of the ion implantation region to form a plurality of trenches, a step of forming a source electrode and a drain in each of the plurality of preset trenches, a step of forming an isolation region at a set position of the epi layer, a step of forming a gate electrode and a temperature detection sensor unit at a set position of the epi layer, a step of forming a first insulating layer that insulates the gate electrode and the temperature detection sensor unit, a step of forming a field plate on an upper side of the gate electrode, a step of forming a second insulating layer that insulates the field plate, a step of etching a portion of the second insulating layer so that an upper portion of the source electrode and the drain electrode is exposed, and a step of plating or depositing a conductive material on the source electrode and the drain electrode to form a multilayer source electrode and a drain electrode, a step of etching a back surface of the substrate to form a via hole, and a step of forming a lower conductive layer connected to the via hole on the back surface of the substrate.

[0083] Hereinafter, a method for manufacturing a semiconductor device according to another embodiment of the present invention will be described in detail with reference to FIGS. 6A to 6J. Here, redundant descriptions based on the description of the semiconductor device according to one embodiment of the present invention will be omitted.

[0084] FIGS. 6A to 6J are drawings showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0085] First, referring to FIG. 6a, an epi layer (120) can be formed on the upper portion of the substrate (110). Specifically, a first compound semiconductor layer (121) including gallium nitride (GaN) and a second compound semiconductor layer (122) including at least one selected from gallium nitride (GaN) and aluminum gallium nitride (AlGaN) can be sequentially formed on the upper portion of the substrate (110). For example, the second compound semiconductor layer (122) can be formed of a gallium nitride (GaN) layer, an Al x Ga y N(x+y=1) layers, Al x In y N(x+y=1) layer and Al x In y Ga z It can be formed by two or more multilayers among N(x+y+z=1) layers.

[0086] Here, the epi layer (120) can be formed on the upper portion of the substrate (110) at a growth height of about 0.1 μm to about 5 μm using various known methods such as MOCVD (Metal-Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), and HVPE (Hydride Vapor Phase Epitaxy).

[0087] Next, referring to FIG. 6b, a plurality of ion implantation regions (130) can be formed by implanting an n-type dopant at a set location of the epi layer (120). For example, an ion implantation mask pattern can be formed on the upper portion of the epi layer (120) to expose a portion of the epi layer (120), and then Si+ ions can be implanted to form a plurality of ion implantation regions (130). Through this process, a plurality of ion implantation regions (130) can be formed in a set volume in the first compound semiconductor layer (121) and the second compound semiconductor layer (122).

[0088] In addition, after forming a plurality of ion implantation regions (130), an insulating layer (not shown) may be formed on the upper portion of each of the plurality of ion implantation regions (130). For example, an insulating material composed of silicon nitride (SiN), silicon oxide (SiO2), aluminum nitride (AlN), and a nitride or oxide combined therewith may be deposited over the entire surface of the substrate (110) to form an insulating layer (not shown) on the upper portion of each of the plurality of ion implantation regions (130). In addition, the insulating layer (not shown) may include various materials that can reduce surface traps of the epi layer (120) and the plurality of ion implantation regions (130) without exposing the upper portion of the plurality of ion implantation regions (130) and the epi layer (120), and reduce thermal shock due to temperature change. Meanwhile, depending on the process settings, the insulating layer (not shown) may be formed before the formation of multiple ion implantation regions (130) or after the formation of multiple ion implantation regions (130).

[0089] Next, referring to FIG. 6c, a portion of the insulating layer (not shown) may be removed to expose a portion of the epi layer (120). Specifically, in the area where the source electrode (160) and the drain electrode (170) are to be formed among the insulating layer (not shown) deposited on the upper surface of the epi layer (120) and the plurality of ion implantation regions (130), not only a portion of the epi layer (120) but also a portion of the upper portion of each of the plurality of ion implantation regions (130) may be exposed.

[0090] Additionally, a portion of the exposed epi layer (120) and an upper portion of each of the plurality of ion implantation regions (130) may be removed to form a plurality of trenches (140).

[0091] Next, referring to FIG. 6d, one or both of the source electrode (160) and the drain electrode (170) may be formed at a set position among a plurality of trenches (140). For example, at least one of titanium (Ti), silicon (Si), nickel (Ni), platinum (Pt), and gold (Au) or an alloy thereof may be deposited or plated on the upper portion of the epi layer (120) on which a plurality of trenches (140) are formed, and then patterned in a preset pattern to form the source electrode (160) and the drain electrode (170), more specifically, the first source electrode layer (161) and the first drain electrode layer (171). At this time, each of the source electrode (160) and the drain electrode (170) may be formed by filling the interior of the trench (140).

[0092] Additionally, before or after patterning, a heat treatment such as a rapid thermal annealing process may be performed to reduce the electrical contact resistance of the source electrode (160), the drain electrode (170), and the ion implantation region (130).

[0093] Next, referring to FIG. 6e, an isolation region (200) can be formed by etching the epi layer (120) so that a semiconductor element does not generate a leakage current. At this time, the outer portions of the plurality of repeatedly arranged source electrodes (160) and drain electrodes (170) and a selected trench (140) among the plurality of trenches (140) (for example, a trench (140) at a location where a temperature detection sensor unit (190) is to be formed) can also be formed into an isolation region (200) with a set volume through an etching process.

[0094] Next, referring to FIG. 6f, a gate electrode (180) may be formed at a position between a source electrode (160) and a drain electrode (170), and a temperature detection sensor unit (190) may be formed in a trench (140) in which an isolation region (200) is formed. Here, the gate electrode (180) and the temperature detection sensor unit (190) may be formed together.

[0095] Specifically, at least one of nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), iridium (Ir), platinum (Pt), and gold (Au) or an alloy thereof may be deposited or plated over the entire surface of the substrate (110) and then patterned in a preset pattern to simultaneously form the gate electrode (180) and the temperature detection sensor unit (190). At this time, the gate electrode (180) may be formed on the epi layer (120) between the source electrode (160) and the drain electrode (170), and the temperature detection sensor unit (190) may be formed inside the trench (140). The temperature detection sensor unit (190) may be positioned on the isolation region (200) by filling the inside of the trench (140).

[0096] Next, referring to FIG. 6g, a first insulating layer (220) may be formed on the epi layer (120), the gate electrode (180), and the temperature detection sensor unit (190) for protection and insulation. Specifically, a first insulating layer (220) made of a nitride or oxide may be deposited on the epi layer (120), the source electrode (160), the drain electrode (170), the gate electrode (180), and the temperature detection sensor unit (190), and a portion of the first insulating layer (220) may be etched so that an upper portion of the source electrode (160) and the drain electrode (170) is exposed.

[0097] Next, referring to FIG. 6h, a field plate (240) for increasing the breakdown voltage can be formed on the upper portion of the gate electrode (180). Specifically, a conductive material is deposited or plated on the first insulating layer (220) and then patterned in a preset pattern to form the field plate (240) on the first insulating layer (220) corresponding to the upper portion of the gate electrode (180).

[0098] Next, referring to FIG. 6i, a second insulating layer (230) may be formed on the first insulating layer (220) and the field plate (240). Specifically, a second insulating layer (230) made of a nitride or oxide may be deposited on the first insulating layer (220), the source electrode (160), the drain electrode (170), and the field plate (240), and a portion of the second insulating layer (230) may be etched so that an upper portion of the source electrode (160) and the drain electrode (170) is exposed.

[0099] In addition, a predetermined conductive material may be deposited on the upper portion of each of the first source electrode layer (161) of the source electrode (160) and the first drain electrode layer (171) of the drain electrode (170) by plating or electron beam evaporation to form a second source electrode layer (162) and a second drain electrode layer (172). Through this, a source electrode (160) and a drain electrode (170) formed of multiple layers may be formed.

[0100] Next, referring to FIG. 6j, a portion of the back surface of the substrate (110) may be selectively etched to form a via hole (310) that exposes the lower surface of the source electrode (160), and a conductive material may be plated or deposited on the via hole (310) and the back surface of the substrate (110) to form a lower conductive layer (320).

[0101] According to the present invention, the functionality and reliability of a device can be improved by including a real-time temperature detection function. Since the specific effects of the present invention are substantially the same as those described above, a detailed description of the specific effects is omitted for convenience.

[0102] The disclosed embodiments have been described with reference to the attached drawings. Those skilled in the art will understand that the present invention can be implemented in forms other than the disclosed embodiments without altering the technical spirit or essential features of the present invention. The disclosed embodiments are illustrative and should not be construed as limiting.

Claims

1. A step of forming an epi layer on a substrate; A step of forming a plurality of trenches by etching a portion of the above epi layer; A step of forming a source electrode and a drain electrode in each of a plurality of preset trenches; A step of forming a gate electrode and a temperature detection sensor unit at a set position of the above epilayer; and A step of forming an insulating layer that insulates the gate electrode and the temperature detection sensor unit; A method for manufacturing a semiconductor device, comprising:

2. In paragraph 1, The method for manufacturing the above semiconductor device is as follows: further comprising a step of forming an isolation region at a set position of the epi layer; In the step of forming the above isolation area, A method for manufacturing a semiconductor device, wherein the isolation region is formed in a shape and volume set in a trench selected from among the plurality of trenches.

3. In paragraph 2, The above isolation area is, In the above-mentioned selected trench, the lower part of the temperature detection sensor part is formed in a shape that surrounds it, The above temperature detection sensor part is, A method for manufacturing a semiconductor device, wherein the inside of the selected trench is filled and formed on the isolation region.

4. In paragraph 1, In the step of forming the gate electrode and the temperature detection sensor unit, A method for manufacturing a semiconductor device, wherein at least one of nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), iridium (Ir), platinum (Pt), and gold (Au) or an alloy thereof is deposited or plated on the upper portion of the epi layer, and then patterned in a set pattern to simultaneously form the gate electrode and the temperature detection sensor unit.

5. Substrate; An epi layer provided on the above substrate; A source electrode provided on the above epi layer; A drain electrode provided on the epi layer and spaced apart from the source electrode; A gate electrode provided between the source electrode and the drain electrode on the upper surface of the epi layer; A temperature detection sensor unit provided at a set position on the above epi layer and detecting temperature; and Including an insulating layer provided on the epi layer and the gate electrode; The above temperature detection sensor part is, A semiconductor device, wherein the lower portion is positioned on a position line corresponding to the position of the lower surface of at least one of the source electrode and the drain electrode.

6. In paragraph 5, The above semiconductor device, A semiconductor device further comprising an isolation region disposed below the temperature detection sensor unit and formed in a shape that surrounds the temperature detection sensor unit.

7. In paragraph 5, The above temperature detection sensor part is, At least one temperature sensing electrode pad; and A temperature detection electrode connected to the above temperature detection electrode pad and extending in a set direction; A semiconductor device comprising:

8. In paragraph 7, The above temperature detection electrode, A semiconductor device, wherein one side and the other side are respectively connected to a plurality of temperature detection electrode pads, and a middle portion between the one side and the other side is adjacent to at least one of the source electrode and the drain electrode and extends along the length direction of the source electrode or the drain electrode.

9. In paragraph 7, The above temperature detection electrode, A semiconductor device, one side of which is connected to the temperature detection electrode pad, the other side of which is connected to the source electrode, and a middle portion between the one side and the other side extends along the length direction of the source electrode or the drain electrode, adjacent to at least one of the source electrode and the drain electrode.

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