Display panel and display device

Abstract

The display panel and the display device of the present disclosure relate to the technical field of display, and can improve the anode flatness of pixels of different colors, thereby alleviating the display color cast problem of the display panel. The display panel comprises: a substrate layer; a driving backplane disposed on one side of the substrate layer, wherein the driving backplane comprises a pixel circuit, and the driving backplane comprises a plurality of conductive layers; and a light-emitting device layer disposed on the side of the driving backplane away from the substrate layer, wherein the light-emitting device layer comprises a plurality of light-emitting devices, each light-emitting device comprises an anode, and the anode is electrically connected to the pixel circuit; the light-emitting devices include a first light-emitting device, a second light-emitting device, and a third light-emitting device, and the first light-emitting device, the second light-emitting device, and the third light-emitting device are configured to emit light of different colors; the anode of the first light-emitting device comprises at least two first anode sub-blocks, and orthographic projections of the first anode sub-blocks on the substrate layer overlap orthographic projections of at least four conductive layers on the substrate layer.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] In recent years, TFT-LCD (Thin Film Transistor Liquid Crystal Display) and AMOLED (Active Matrix Organic Light Emitting Diode) and other display devices are widely used, and the AMOLED display has the advantages of long service life, high display brightness, large contrast ratio, wide color gamut and the like. The AMOLED display device usually drives the light emitting device to emit light through a driving circuit to form a light emitting pixel, and the driving device of the driving circuit transmits a driving signal to the anode of the light emitting device, and the light emitting device emits light under the driving of the driving signal.

[0003] SUMMARY

[0004] The first aspect of the present disclosure provides a display panel, comprising:

[0005] a substrate layer;

[0006] a driving backplane disposed on one side of the substrate layer, the driving backplane comprising a pixel circuit, the driving backplane comprising a plurality of conductive layers;

[0007] a light emitting device layer disposed on a side of the driving backplane away from the substrate layer, the light emitting device layer comprising a plurality of light emitting devices, the light emitting device comprising an anode, the anode being electrically connected to the pixel circuit;

[0008] The light emitting device comprises a first light emitting device, a second light emitting device and a third light emitting device, the first light emitting device, the second light emitting device and the third light emitting device being used to emit light of different colors.

[0009] The anode of the first light emitting device comprises at least two first anode sub-blocks, and the orthogonal projection of the first anode sub-block on the substrate layer overlaps the orthogonal projection of at least four conductive layers on the substrate layer.

[0010] In some embodiments, the anode of the first light emitting device comprises a first connecting portion, and the at least two first anode sub-blocks are electrically connected through the first connecting portion.

[0011] In some embodiments, the anode of the first light emitting device comprises at least three first anode sub-blocks, and there is no first connecting portion directly connecting between two first anode sub-blocks in the first light emitting device.

[0012] In some embodiments, the first anode sub-blocks in the first light emitting device are sequentially connected end to end through the first connecting portion.

[0013] In some embodiments, the anode of the first light emitting device comprises N first anode sub-blocks, and the N first anode sub-blocks are connected to each other by M first connecting parts, wherein N and M are natural numbers greater than or equal to 3, and 0≤M-N≤2.

[0014] In some embodiments, the first connecting part comprises a first sub-connecting part and a second sub-connecting part, the first sub-connecting part connects two adjacent first anode sub-blocks in a first direction, the second sub-connecting part connects two adjacent first anode sub-blocks in a second direction, and the first direction intersects the second direction.

[0015] The number of the first sub-connecting parts is less than or equal to the number of the second sub-connecting parts.

[0016] In some embodiments, the orthographic projections of at least two first anode sub-blocks on the substrate layer have the same shape and area.

[0017] In some embodiments, in the first light emitting device, two adjacent first anode sub-blocks in the first direction are symmetric about the first sub-connecting part; and / or,

[0018] In the first light emitting device, two adjacent first anode sub-blocks in the second direction are symmetric about the second sub-connecting part.

[0019] In some embodiments, the first light emitting device and the second light emitting device are arranged alternately in a first direction, and the first light emitting device and the third light emitting device are arranged alternately in the first direction.

[0020] The second light emitting device and the third light emitting device are arranged alternately in a second direction, and the first light emitting device is arranged in the second direction.

[0021] The first direction intersects the second direction.

[0022] In some embodiments, the shape of the first anode sub-block of two adjacent first light emitting devices in the second direction is mirror set about the first direction.

[0023] In some embodiments, the first anode sub-block and the pixel circuit are electrically connected by a first anode via hole.

[0024] The first connecting part is arranged in a spacing region between two connected first anode sub-blocks, and the orthographic projection of the first anode via hole on the substrate layer falls within the orthographic projection of the first connecting part on the substrate layer.

[0025] In some embodiments, the anode of the second light emitting device comprises a second anode block, and the anode of the third light emitting device comprises a third anode block.

[0026] The first anode sub-block is electrically connected to the pixel circuit through a first anode via, the second anode block is electrically connected to the pixel circuit through a second anode via, and the third anode block is electrically connected to the pixel circuit through a third anode via.

[0027] The first anode via, the second anode via, and the third anode via are arranged in a first direction in sequence, and the second anode via is arranged between the first anode via and the third anode via.

[0028] In some embodiments, the second anode via is located between two first anode sub-blocks adjacent in a second direction, and the first direction intersects the second direction.

[0029] In some embodiments, the first anode sub-block is arranged between the first anode via and the second anode via adjacent in the first direction, and the first anode sub-block is arranged between the first anode via and the third anode via adjacent in the first direction.

[0030] In some embodiments, a projection of the first anode via on the substrate layer at least partially overlaps a projection of the first anode sub-block on the substrate.

[0031] In some embodiments, the anode of the first light emitting device comprises a first anode extension, the first anode extension is connected to the first anode sub-block, and a projection of the first anode via on the substrate layer falls within a projection of the first anode extension on the substrate layer; and / or,

[0032] The anode of the second light emitting device comprises a second anode extension, the second anode extension is connected to the second anode block, and a projection of the second anode via on the substrate layer falls within a projection of the second anode extension on the substrate layer; and / or,

[0033] The anode of the third light emitting device comprises a third anode extension, the third anode extension is connected to the third anode block, and a projection of the third anode via on the substrate layer falls within a projection of the third anode extension on the substrate layer.

[0034] In some embodiments, the second anode extension is located in a spacing region between the first anode sub-block and the second anode block; and / or,

[0035] The third anode overhang is located in a spacing region between the second anode block and the third anode block; and / or,

[0036] The length extension direction of the second anode overhang intersects the first direction and the second direction, and the first direction intersects the second direction.

[0037] In some embodiments, part of the second anode overhang is located between the first anode sub-blocks adjacent in the second direction.

[0038] In some embodiments, the second anode overhang includes an anode overhang segment and an anode via segment, the anode overhang segment is connected between the anode via segment and the second anode block, and the anode via segment is electrically connected with the pixel circuit through the second anode via;

[0039] The orthographic projection of the second anode via on the substrate layer falls within the orthographic projection of the anode via segment on the substrate layer, the anode overhang segment is located in a spacing region between the first anode sub-blocks adjacent in the first direction and the second anode block, and the anode via segment is located between the first anode sub-blocks adjacent in the second direction.

[0040] In some embodiments, the distance between the second anode block adjacent and the first anode sub-block is less than the length of the anode overhang segment; and / or,

[0041] The length extension direction of the anode overhang segment intersects the first direction and the second direction; and / or,

[0042] The shape of the orthographic projection of the anode via segment on the substrate layer includes a rectangle.

[0043] In some embodiments, the shape of the orthographic projection of the first anode overhang on the substrate layer includes a rectangle; and / or,

[0044] The shape of the orthographic projection of the second anode overhang on the substrate layer includes a rectangle; and / or,

[0045] The shape of the orthographic projection of the third anode overhang on the substrate layer includes a rectangle; and / or,

[0046] The shape of the orthographic projection of the first anode sub-block on the substrate layer includes a rectangle; and / or,

[0047] The shape of the orthographic projection of the first connection part on the substrate layer includes a rectangle; and / or,

[0048] The shape of the orthographic projection of the second anode block on the substrate layer includes a rectangle; and / or,

[0049] The shape of the third anode block in orthographic projection on the substrate layer comprises a rectangle.

[0050] In some embodiments, the anode of the second light emitting device comprises a second anode block, and the anode of the third light emitting device comprises a third anode block;

[0051] The driving backplane comprises a data signal line, the data signal line extends along a second direction, the data signal line is electrically connected with the pixel circuit;

[0052] The orthographic projection of the data signal line on the substrate layer does not overlap with the orthographic projection of the first anode sub-block on the substrate layer; and / or,

[0053] The orthographic projection of the data signal line on the substrate layer does not overlap with the orthographic projection of the second anode block on the substrate layer; and / or,

[0054] The orthographic projection of the data signal line on the substrate layer does not overlap with the orthographic projection of the third anode block on the substrate layer.

[0055] In some embodiments, in the case where the first light emitting device comprises a first connection part, part of the orthographic projection of the data signal line on the substrate layer overlaps with the orthographic projection of one of the first connection parts in the first light emitting device on the substrate layer; and / or,

[0056] Part of the orthographic projection of the data signal line on the substrate layer is located in the interval region between the adjacent first anode sub-blocks in the first light emitting device; and / or,

[0057] In the case where the anode of the second light emitting device comprises a second anode protruding part, part of the orthographic projection of the data signal line on the substrate layer overlaps with the orthographic projection of the second anode protruding part on the substrate layer.

[0058] In some embodiments, the driving backplane comprises a reference signal connection line and a first power supply line, the reference signal connection line and the first power supply line both extend along the second direction, the reference signal connection line is located between the data signal line and the first power supply line, the reference signal connection line and the first power supply line are both electrically connected with the pixel circuit, and the second direction intersects the first direction;

[0059] The reference signal connection line includes a first reference connection segment and a second reference connection segment, the first reference connection segment is connected with the second reference connection segment in the second direction, at least part of the first reference connection segment has a size in the first direction smaller than a size of the second reference connection segment in the first direction, a projection of the first reference connection segment on the substrate layer has no overlap with a projection of the first anode sub-block on the substrate layer, a projection of the second reference connection segment on the substrate layer has overlap with a projection of at least one of the first anode sub-block on the substrate layer; and / or,

[0060] The first power supply line includes a first power supply connection segment and a second power supply connection segment, the first power supply connection segment is connected with the second power supply connection segment in the second direction, at least part of the first power supply connection segment has a size in the first direction smaller than a size of the second power supply connection segment in the first direction, a projection of the first power supply connection segment on the substrate layer has no overlap with a projection of the first anode sub-block on the substrate layer, a projection of the second power supply connection segment on the substrate layer has overlap with a projection of at least one of the first anode sub-block on the substrate layer; and / or, a projection of the first power supply connection segment on the substrate layer has no overlap with a projection of the second anode block on the substrate layer, a projection of the second power supply connection segment on the substrate layer has overlap with a projection of the second anode block on the substrate layer; and / or, a projection of the first power supply connection segment on the substrate layer has no overlap with a projection of the third anode block on the substrate layer, a projection of the second power supply connection segment on the substrate layer has overlap with a projection of the third anode block on the substrate layer.

[0061] In some embodiments, a projection of the reference signal connection line on the substrate layer has no overlap with a projection of the second anode block on the substrate layer; and / or,

[0062] A projection of the reference signal connection line on the substrate layer has no overlap with a projection of the third anode block on the substrate layer.

[0063] In some embodiments, part of the reference signal connection line is located in a spacing region between the adjacent first anode sub-block and the second anode block; and / or,

[0064] Part of the reference signal connection line is located in a spacing region between the adjacent first anode sub-block and the third anode block.

[0065] In some embodiments, the anode of the second light emitting device comprises a second anode extension, the second anode block is connected with the second anode extension, the second anode extension is electrically connected with the pixel circuit through a second anode via, and a projection of the second anode via on the substrate layer falls within a projection of an end of the second anode extension away from the second anode block on the substrate layer.

[0066] A projection of the part of the reference signal connection line on the substrate layer overlaps with a projection of the second anode extension on the substrate layer.

[0067] In some embodiments, a shape of the projection of the second reference connection segment on the substrate layer comprises a rectangle; and / or,

[0068] A shape of the projection of the second power supply connection segment on the substrate layer comprises a rectangle.

[0069] In some embodiments, the light emitting device layer comprises a pixel defining layer and a light emitting layer, the pixel defining layer comprises a plurality of pixel openings, and the light emitting layer is disposed in the pixel openings, a projection of the pixel opening on the substrate layer falls within a projection of the anode on the substrate layer.

[0070] In the case that the projection of the second reference connection segment on the substrate layer overlaps with the projection of the first anode sub-block on the substrate layer, and the projection of the second power supply connection segment on the substrate layer overlaps with the projection of the first anode sub-block on the substrate layer, an overlapping area of the projection of the second reference connection segment on the substrate layer and the projection of the first anode sub-block on the substrate layer is a first area, an overlapping area of the projection of the second power supply connection segment on the substrate layer and the projection of the first anode sub-block on the substrate layer is a second area, an area of the projection of the first anode sub-block on the substrate layer is a third area, an overlapping area of a projection of the pixel opening corresponding to the first anode sub-block on the substrate layer and the projection of the second reference connection segment on the substrate layer is a fourth area, an overlapping area of the projection of the pixel opening corresponding to the first anode sub-block on the substrate layer and the projection of the second power supply connection segment on the substrate layer is a fifth area, and an area of the projection of the pixel opening corresponding to the first anode sub-block on the substrate layer is a sixth area.

[0071] A ratio of the first area to the third area is greater than or equal to 80%, and / or a ratio of the second area to the third area is greater than or equal to 80%; and / or,

[0072] a ratio of the fourth area to the sixth area is greater than or equal to 80%, and / or, a ratio of the fifth area to the sixth area is greater than or equal to 80%; and / or,

[0073] a ratio of a sum of the first area and the second area to the third area is greater than or equal to 80%; and / or,

[0074] a ratio of a sum of the fourth area and the fifth area to the sixth area is greater than or equal to 80%.

[0075] In some embodiments, the driving backplane comprises a reference signal connection line and a first power supply line, the reference signal connection line and the first power supply line both extend along the second direction, the reference signal connection line is located between the data signal line and the first power supply line, and the reference signal connection line and the first power supply line are both electrically connected with the pixel circuit;

[0076] a projection of the reference signal connection line on the substrate layer overlaps with a projection of the first anode sub-block on the substrate layer, and a projection of the first power supply line on the substrate layer overlaps with a projection of the first anode sub-block on the substrate layer;

[0077] a boundary of the projection of the first anode sub-block on the substrate layer partially overlaps with a boundary of the projection of the first power supply line on the substrate layer, wherein the overlapping boundary extends along the second direction; and / or,

[0078] a boundary of the projection of the first anode sub-block on the substrate layer partially overlaps with a boundary of the projection of the reference signal connection line on the substrate layer, wherein the overlapping boundary extends along the second direction.

[0079] In some embodiments, the driving backplane comprises an initial signal connection line and an initial signal line, the initial signal connection line extends along the second direction, the initial signal line extends along a first direction, the initial signal connection line is electrically connected with the initial signal line, the initial signal line is electrically connected with the pixel circuit, and the first direction intersects with the second direction;

[0080] at least part of the projection of the initial signal connection line on the substrate layer does not overlap with the projection of the first anode sub-block on the substrate layer.

[0081] In some embodiments, part of the initial signal connection line is located in the interval region between the adjacent first anode sub-block and the third anode block; and / or,

[0082] Part of the initial signal connection line is located in the interval region between the adjacent first anode sub-block.

[0083] In some embodiments, the driving backplane comprises a plurality of gate signal lines, the plurality of gate signal lines extend along a first direction;

[0084] The second light emitting device comprises a second anode block, and the third light emitting device comprises a third anode block;

[0085] At least part of the gate signal lines has no overlap with the first anode sub-block in the orthographic projection of the substrate layer; and / or,

[0086] The second anode block comprises a second anode opening, and part of the gate signal lines has overlap with the second anode opening in the orthographic projection of the substrate layer; and / or,

[0087] The third anode block comprises a third anode opening, and part of the gate signal lines has overlap with the third anode opening in the orthographic projection of the substrate layer.

[0088] In some embodiments, the first anode sub-block comprises a first anode opening, the anode of the second light emitting device comprises a second anode extension, the second anode extension is connected with the second anode block, and the second anode extension is electrically connected with the pixel circuit through a second anode via hole;

[0089] The first anode opening covers the orthographic projection of the second anode via hole on the substrate layer.

[0090] In some embodiments, the size of the second anode opening in the first direction is greater than or equal to 2 / 3 of the maximum size of the second anode block in the first direction; and / or,

[0091] The size of the third anode opening in the first direction is greater than or equal to 2 / 3 of the maximum size of the third anode block in the first direction.

[0092] In some embodiments, a plurality of the gate signal lines are arranged in the same layer.

[0093] In some embodiments, the gate signal lines comprise a first gate signal line, a second gate signal line, a third gate signal line, a fourth gate signal line and a fifth gate signal line, the first gate signal line, the second gate signal line, the third gate signal line, the fourth gate signal line and the fifth gate signal line are used to electrically connect the gate of different transistors in the pixel circuit respectively, and the second gate signal line and the fifth gate signal line are used to transmit the same gate signal;

[0094] At least two of the first, second, third, fourth and fifth gate signal lines are arranged on different conductive layers, and the gate signal lines are arranged on two conductive layers respectively.

[0095] In some embodiments, the first, second, third and fifth gate signal lines are arranged on the same conductive layer, and the fourth gate signal line is arranged on a different conductive layer from the first gate signal line.

[0096] In some embodiments, a projection of the fourth gate signal line on the substrate layer overlaps with a projection of the first anode sub-block on the substrate layer; and / or,

[0097] a projection of the fourth gate signal line on the substrate layer overlaps with a projection of the second anode sub-block on the substrate layer; and / or,

[0098] a projection of the fourth gate signal line on the substrate layer overlaps with a projection of the third anode sub-block on the substrate layer.

[0099] In some embodiments, the anode of the first light emitting device includes four first anode sub-blocks, which are a first sub-block, a second sub-block, a third sub-block and a fourth sub-block respectively;

[0100] The first sub-block and the second sub-block are arranged along a first direction, the first sub-block and the third sub-block are arranged along a second direction, the third sub-block and the fourth sub-block are arranged along the first direction, and the second sub-block and the fourth sub-block are arranged along the second direction;

[0101] The first gate signal line is located in a spacing region between the first sub-block and the third sub-block, and / or the first gate signal line is located in a spacing region between the second sub-block and the fourth sub-block; and / or,

[0102] The second gate signal line is located in a spacing region between the first sub-block and the third sub-block, and / or the second gate signal line is located in a spacing region between the second sub-block and the fourth sub-block.

[0103] In some embodiments, when the first light emitting device includes a first connecting portion, the first connecting portion includes a first sub-connecting portion and a second sub-connecting portion;

[0104] The first sub-block is connected with the second sub-block through the first sub-connection, the first sub-block is connected with the third sub-block through the second sub-connection, the third sub-block is not provided with the first connection with the fourth sub-block, and the second sub-block is connected with the fourth sub-block through the second sub-connection.

[0105] The orthogonal projection of the first gate signal line on the substrate layer overlaps with the orthogonal projection of the second sub-connection on the substrate layer; and / or,

[0106] The orthogonal projection of the second gate signal line on the substrate layer overlaps with the orthogonal projection of the second sub-connection on the substrate layer.

[0107] In some embodiments, the orthogonal projection of the first gate signal line on the substrate layer overlaps with the orthogonal projection of the third anode opening on the substrate layer; and / or,

[0108] The orthogonal projection of the second gate signal line on the substrate layer overlaps with the orthogonal projection of the third anode opening on the substrate layer; and / or,

[0109] The orthogonal projection of the fifth gate signal line on the substrate layer overlaps with the orthogonal projection of the second anode opening on the substrate layer; and / or,

[0110] The orthogonal projection of the third gate signal line on the substrate layer overlaps with the orthogonal projection of the second anode opening on the substrate layer.

[0111] In some embodiments, the second anode block comprises a second connection and a plurality of second anode sub-blocks, at least two of the second anode sub-blocks are connected through the second connection, the size of the second anode sub-block in a first direction is greater than the size of the second connection in the first direction, and part of the signal lines of the driving backboard are arranged in the interval region between adjacent two second anode sub-blocks; and / or,

[0112] The third anode block comprises a third connection and a plurality of third anode sub-blocks, at least two of the third anode sub-blocks are connected through the third connection, the size of the third anode sub-block in a first direction is greater than the size of the third connection in the first direction, and part of the signal lines of the driving backboard are arranged in the interval region between adjacent two third anode sub-blocks.

[0113] In some embodiments, part of the orthogonal projection of the gate signal line on the substrate layer overlaps with the orthogonal projection of the second connection on the substrate layer; and / or,

[0114] A projection of the gate signal line on the substrate layer overlaps with a projection of the third connecting portion on the substrate layer.

[0115] In some embodiments, the second connecting portion is connected to a main body portion between two ends of the second anode sub-block in the first direction, and at least two second anode openings are formed between at least two second anode sub-blocks; and / or,

[0116] The third connecting portion is connected to a main body portion between two ends of the third anode sub-block in the first direction, and at least two third anode openings are formed between at least two third anode sub-blocks.

[0117] In some embodiments, a shape of a projection of the second anode sub-block on the substrate layer comprises a rectangle; and / or,

[0118] A shape of a projection of the third anode sub-block on the substrate layer comprises a rectangle; and / or,

[0119] A shape of a projection of the second connecting portion on the substrate layer comprises a rectangle; and / or,

[0120] A shape of a projection of the third connecting portion on the substrate layer comprises a rectangle; and / or,

[0121] A shape of a projection of the second anode opening on the substrate layer comprises a rectangle; and / or,

[0122] A shape of a projection of the third anode opening on the substrate layer comprises a rectangle.

[0123] In some embodiments, the driving backplane comprises a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, which are sequentially stacked on one side of the substrate layer;

[0124] The first conductive layer is provided with a plurality of block electrodes and the fourth gate signal line, and the block electrode comprises a gate of a transistor and a plate of a capacitor in the pixel circuit;

[0125] The second conductive layer is provided with a repair line, and the repair line extends along the first direction;

[0126] The third conductive layer is provided with the first gate signal line, the second gate signal line, the third gate signal line, and the fifth gate signal line;

[0127] The fourth conductive layer is provided with an anode connecting electrode, and the anode connecting electrode is electrically connected with the anode of the light emitting device.

[0128] In some embodiments, a projection of the anode connecting electrode on the substrate layer overlaps with a projection of the repair line on the substrate layer.

[0129] In some embodiments, the first conductive layer comprises a data signal line, the data signal line extending along a second direction, the second direction being perpendicular to the first direction.

[0130] In some embodiments, the driving backplane comprises an active layer, the active layer being disposed between the substrate layer and the first conductive layer.

[0131] At least four layers of insulating thin films are disposed between the active layer and the first conductive layer.

[0132] In some embodiments, the first conductive layer comprises a Ti-Al-Ti stack structure.

[0133] In some embodiments, the driving backplane comprises a data signal line, a first power supply line, a first enable signal line, a second enable signal line, a first initial signal line, a second initial signal line, a first reference signal line, and a second reference signal line.

[0134] The pixel circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, and a second capacitor.

[0135] A first electrode of the first transistor is electrically connected with the data signal line, a second electrode of the first transistor is electrically connected with a second node, and a gate of the first transistor is electrically connected with the first gate signal line.

[0136] One end of the second capacitor is electrically connected with the first power supply line, the other end of the second capacitor is electrically connected with the second node, one end of the first capacitor is electrically connected with the second node, and the other end of the first capacitor is electrically connected with a first node.

[0137] A first electrode of the second transistor is electrically connected with the first node, a gate of the second transistor is electrically connected with the fifth gate signal line, and a second electrode of the second transistor is electrically connected with a fourth node.

[0138] A first electrode of the third transistor is electrically connected with a third node, a second electrode of the third transistor is electrically connected with the fourth node, and a gate of the third transistor is electrically connected with the first node.

[0139] A first electrode of the fifth transistor is electrically connected with the first power supply line, a second electrode of the fifth transistor is electrically connected with the third node, and a gate of the fifth transistor is electrically connected with the first enable signal line.

[0140] a gate of the ninth transistor is electrically connected with the fourth gate signal line, a first electrode of the ninth transistor is electrically connected with the second reference signal line, and a second electrode of the ninth transistor is electrically connected with the third node;

[0141] a first electrode of the sixth transistor is electrically connected with the fourth node, a second electrode of the sixth transistor is electrically connected with a fifth node, and a gate of the sixth transistor is electrically connected with the second enable signal line;

[0142] a second electrode of the eighth transistor is electrically connected with the fifth node, a first electrode of the eighth transistor is electrically connected with the second initial signal line, and a gate of the eighth transistor is electrically connected with the fourth gate signal line;

[0143] a first electrode of the fourth transistor is electrically connected with the first node, a second electrode of the fourth transistor is electrically connected with the first initial signal line, and a gate of the fourth transistor is electrically connected with the third gate signal line;

[0144] a first electrode of the seventh transistor is electrically connected with the second node, a second electrode of the seventh transistor is electrically connected with the first reference signal line, and a gate of the seventh transistor is electrically connected with the second gate signal line;

[0145] the fifth node is configured to electrically connect the light emitting device.

[0146] In some embodiments, at least one of the first transistor, the second transistor, the fourth transistor and the seventh transistor comprises a double-gate structure transistor.

[0147] In some embodiments, the pixel circuit comprises a first pixel circuit, a second pixel circuit and a third pixel circuit, the first pixel circuit is electrically connected with the first light emitting device, the second pixel circuit is electrically connected with the second light emitting device, and the third pixel circuit is electrically connected with the third light emitting device.

[0148] a channel width-length ratio of the third transistor of the first pixel circuit is greater than a channel width-length ratio of the third transistor of the second pixel circuit, and the channel width-length ratio of the third transistor of the first pixel circuit is greater than a channel width-length ratio of the third transistor of the third pixel circuit.

[0149] In some embodiments, the driving backplane comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer.

[0150] The second reference signal line, the first enable signal line, the second enable signal line, and the first initial signal line are all arranged on the second conductive layer; and / or,

[0151] The first reference signal line and the second initial signal line are both arranged on the third conductive layer; and / or,

[0152] The first power supply line, the data signal line, the reference signal connection line, and the initial signal connection line are all arranged on the fourth conductive layer.

[0153] In a second aspect, the present disclosure provides a display panel, comprising:

[0154] a substrate layer;

[0155] a driving backplane arranged on one side of the substrate layer, the driving backplane comprising a pixel circuit, a reference signal connection line, and a first power supply line, the reference signal connection line and the first power supply line both being electrically connected with the pixel circuit, the reference signal connection line and the first power supply line both extending along a second direction, the second direction intersecting a first direction;

[0156] a light emitting device layer arranged on a side of the driving backplane away from the substrate layer, the light emitting device layer comprising a plurality of light emitting devices, the light emitting device comprising an anode, the anode being electrically connected with the pixel circuit;

[0157] The reference signal connection line comprises a first reference connection segment and a second reference connection segment, the first reference connection segment and the second reference connection segment being connected in the second direction, at least part of the first reference connection segment in the first direction having a size smaller than that of the second reference connection segment in the first direction, a projection of the first reference connection segment on the substrate layer having no overlap with a projection of the anode on the substrate layer, a projection of the second reference connection segment on the substrate layer having overlap with a projection of at least one of the anodes on the substrate layer; and / or,

[0158] The first power supply line comprises a first power supply connection segment and a second power supply connection segment, the first power supply connection segment and the second power supply connection segment being connected in the second direction, at least part of the first power supply connection segment in the first direction having a size smaller than that of the second power supply connection segment in the first direction, a projection of the first power supply connection segment on the substrate layer having no overlap with a projection of the anode on the substrate layer, a projection of the second power supply connection segment on the substrate layer having overlap with a projection of at least one of the anodes on the substrate layer.

[0159] In some embodiments, the light emitting device layer comprises a pixel defining layer and a light emitting layer, the pixel defining layer comprises a plurality of pixel openings, the light emitting layer is disposed in the pixel openings, a projection of the pixel openings on the substrate layer falls within a projection of the anode on the substrate layer;

[0160] The second reference connection segment has a seventh area of overlap with the projection of the anode on the substrate layer, the second power connection segment has an eighth area of overlap with the projection of the anode on the substrate layer, the anode has a ninth area of projection on the substrate layer, the pixel opening corresponding to the anode has a tenth area of overlap with the projection of the second reference connection segment on the substrate layer, the pixel opening corresponding to the anode has an eleventh area of overlap with the projection of the second power connection segment on the substrate layer, the pixel opening corresponding to the anode has a twelfth area of projection on the substrate layer;

[0161] The ratio of the seventh area to the ninth area is greater than or equal to 80%, and / or the ratio of the tenth area to the twelfth area is greater than or equal to 80%; and / or,

[0162] The ratio of the eighth area to the ninth area is greater than or equal to 80%, and / or the ratio of the eleventh area to the twelfth area is greater than or equal to 80%; and / or,

[0163] The ratio of the sum of the seventh area and the eighth area to the ninth area is greater than or equal to 80%, and / or the ratio of the sum of the tenth area and the eleventh area to the twelfth area is greater than or equal to 80%.

[0164] In some embodiments, the light emitting device comprises a first light emitting device, a second light emitting device, and a third light emitting device, the first light emitting device, the second light emitting device, and the third light emitting device are configured to emit different colors of light;

[0165] The anode of the first light emitting device comprises a first anode block, the anode of the second light emitting device comprises a second anode block, and the anode of the third light emitting device comprises a third anode block;

[0166] The projection of the second reference connection segment on the substrate layer overlaps with the projection of the first anode block on the substrate layer; and / or,

[0167] The projection of the second power connection segment on the substrate layer overlaps with the projection of the first anode block on the substrate layer; and / or,

[0168] a projection of the reference signal connection line on the substrate layer has no overlap with a projection of the second anode block on the substrate layer, and a projection of the second power supply connection segment on the substrate layer has overlap with a projection of the second anode block on the substrate layer; and / or,

[0169] a projection of the reference signal connection line on the substrate layer has no overlap with a projection of the third anode block on the substrate layer, and a projection of the second power supply connection segment on the substrate layer has overlap with a projection of the third anode block on the substrate layer.

[0170] In some embodiments, part of the reference signal connection line is located in a spacing region between the adjacent first anode block and the second anode block; and / or,

[0171] part of the reference signal connection line is located in a spacing region between the adjacent first anode block and the third anode block.

[0172] In some embodiments, the anode of the first light emitting device comprises a first anode block and a first connection part, the first anode block comprises a plurality of first anode sub-blocks, and the first anode sub-blocks are connected through the first connection part;

[0173] a projection of the second reference connection segment on the substrate layer has overlap with a projection of at least one of the first anode sub-blocks on the substrate layer; and / or,

[0174] a projection of the second power supply connection segment on the substrate layer has overlap with a projection of at least one of the first anode sub-blocks on the substrate layer.

[0175] In some embodiments, a boundary of a projection of the first anode sub-block on the substrate layer partially overlaps with a boundary of a projection of the first power supply line on the substrate layer, and the overlapping boundary extends along the second direction; and / or,

[0176] a boundary of a projection of the first anode sub-block on the substrate layer partially overlaps with a boundary of a projection of the reference signal connection line on the substrate layer, and the overlapping boundary extends along the second direction.

[0177] In some embodiments, the first anode block comprises at least three first anode sub-blocks, and there is no first connection part directly connecting between two of the first anode sub-blocks in the first anode block; or,

[0178] the first anode sub-blocks in the first anode block are sequentially connected through the first connection part;

[0179] and / or,

[0180] The first connecting part comprises a first sub-connecting part and a second sub-connecting part, the first sub-connecting part connects two adjacent first anode sub-blocks in a first direction, and the second sub-connecting part connects two adjacent first anode sub-blocks in a second direction, the first direction intersects the second direction.

[0181] The number of the first sub-connecting parts is less than or equal to the number of the second sub-connecting parts.

[0182] In some embodiments, the shape and area of the orthographic projection of at least two first anode sub-blocks on the substrate layer are the same.

[0183] In some embodiments, the anode of the first light-emitting device comprises N first anode sub-blocks, and the N first anode sub-blocks are connected to each other by M first connecting parts, wherein N and M are natural numbers greater than or equal to 3, and 0≤M-N≤2.

[0184] In some embodiments, in the first light-emitting device, two adjacent first anode sub-blocks in the first direction are symmetric about the first sub-connecting part; and / or,

[0185] In the first light-emitting device, two adjacent first anode sub-blocks in the second direction are symmetric about the second sub-connecting part.

[0186] In some embodiments, the first light-emitting device and the second light-emitting device are arranged alternately in a first direction, and the first light-emitting device and the third light-emitting device are arranged alternately in the first direction.

[0187] The second light-emitting device and the third light-emitting device are arranged alternately in a second direction, and the first light-emitting device is arranged in the second direction.

[0188] The first direction intersects the second direction.

[0189] In some embodiments, the shape of the first anode sub-block of two adjacent first light-emitting devices in the second direction is mirror set about the first direction; and / or,

[0190] The minimum distance between the second anode block and the first anode sub-block in the first direction is greater than the minimum distance between the second anode block and the third anode block in the second direction.

[0191] In some embodiments, the shape of the orthographic projection of the second reference connecting segment on the substrate layer comprises a rectangle; and / or,

[0192] A shape of a projection of the second power connection segment on the substrate layer comprises a rectangle; and / or,

[0193] A shape of a projection of the first anode sub-block on the substrate layer comprises a rectangle; and / or,

[0194] A shape of a projection of the first connection portion on the substrate layer comprises a rectangle.

[0195] In some embodiments, the anode of the second light emitting device comprises a second anode extension, the second anode block is connected with the second anode extension, the second anode extension is electrically connected with the pixel circuit through a second anode via, a projection of the second anode via on the substrate layer falls within a projection of an end of the second anode extension away from the second anode block on the substrate layer;

[0196] A projection of part of the reference signal connection line on the substrate layer overlaps with a projection of the second anode extension on the substrate layer.

[0197] In some embodiments, a shape of a projection of the second reference connection segment on the substrate layer comprises a rectangle; and / or,

[0198] A shape of a projection of the second power connection segment on the substrate layer comprises a rectangle.

[0199] In some embodiments, the first anode sub-block is electrically connected with the pixel circuit through a first anode via, the second anode block is electrically connected with the pixel circuit through a second anode via;

[0200] The first connection portion is arranged in an interval region between two first anode sub-blocks connected with each other, a projection of the first anode via on the substrate layer falls within a projection of the first connection portion on the substrate layer; and / or,

[0201] The second anode via is located between two first anode sub-blocks adjacent in the second direction.

[0202] In some embodiments, the first anode sub-block is electrically connected with the pixel circuit through a first anode via, the anode of the first light emitting device comprises a first anode extension, the first anode extension is connected with the first anode sub-block, a projection of the first anode via on the substrate layer falls within a projection of the first anode extension on the substrate layer; and / or,

[0203] The anode of the second light-emitting device comprises a second anode extension, the second anode block is connected with the second anode extension, and a projection of the second anode via hole on the substrate layer falls within a projection of the second anode extension on the substrate layer; and / or,

[0204] The anode of the third light-emitting device comprises a third anode block, the third anode block is electrically connected with the pixel circuit through a third anode via hole, the third light-emitting device comprises a third anode extension, the third anode block is connected with the third anode extension, and a projection of the third anode via hole on the substrate layer falls within a projection of the third anode extension on the substrate layer.

[0205] In some embodiments, the second anode extension is located in a spacing region between the first anode sub-block and the second anode block; and / or,

[0206] The third anode extension is located in a spacing region between the second anode block and the third anode block; and / or,

[0207] The length extension direction of the second anode extension intersects the first direction, the length extension direction of the second anode extension intersects the second direction, and the first direction intersects the second direction.

[0208] In some embodiments, part of the second anode extension is located between the first anode sub-blocks adjacent in the second direction.

[0209] In some embodiments, the second anode extension comprises an anode extension segment and an anode via hole segment, the anode extension segment is connected between the anode via hole segment and the second anode block, and the anode via hole segment is electrically connected with the pixel circuit through the second anode via hole;

[0210] A projection of the second anode via hole on the substrate layer falls within a projection of the anode via hole segment on the substrate layer, the anode extension segment is located in a spacing region between the first anode sub-blocks adjacent in the first direction and the second anode block, and the anode via hole segment is located between two first anode sub-blocks adjacent in the second direction.

[0211] In some embodiments, the distance between the second anode block and the first anode sub-block adjacent is less than the length of the anode extension segment; and / or,

[0212] The length extension direction of the anode extension segment intersects the first direction, and the length extension direction of the anode extension segment intersects the second direction; and / or,

[0213] A shape of a normal projection of the anode via section onto the substrate layer comprises a rectangle.

[0214] In some embodiments, a shape of a normal projection of the first anode overhang onto the substrate layer comprises a rectangle; and / or,

[0215] A shape of a normal projection of the second anode overhang onto the substrate layer comprises a rectangle; and / or,

[0216] A shape of a normal projection of the third anode overhang onto the substrate layer comprises a rectangle; and / or,

[0217] A shape of a normal projection of the first anode sub-block onto the substrate layer comprises a rectangle; and / or,

[0218] A shape of a normal projection of the first connecting portion onto the substrate layer comprises a rectangle; and / or,

[0219] A shape of a normal projection of the second anode block onto the substrate layer comprises a rectangle; and / or,

[0220] A shape of a normal projection of the third anode block onto the substrate layer comprises a rectangle.

[0221] In some embodiments, the driving backplane comprises a data signal line extending along the second direction, the data signal line is electrically connected with the pixel circuit, the reference signal connecting line is located in a region between the first power line and the data signal line;

[0222] A normal projection of the data signal line onto the substrate layer does not overlap with a normal projection of the first anode sub-block onto the substrate layer; and / or,

[0223] A normal projection of the data signal line onto the substrate layer does not overlap with a normal projection of the second anode block onto the substrate layer; and / or,

[0224] A normal projection of the data signal line onto the substrate layer does not overlap with a normal projection of the third anode block onto the substrate layer.

[0225] In some embodiments, a normal projection of part of the data signal line onto the substrate layer overlaps with a normal projection of one of the first connecting portions in the first light emitting device; and / or,

[0226] A normal projection of part of the data signal line onto the substrate layer is located in a spacing region between adjacent first anode sub-blocks in the first light emitting device; and / or,

[0227] The anode of the second light emitting device comprises a second anode protrusion, the second anode protrusion is connected with the second anode block, and a projection of part of the data signal line on the substrate layer overlaps a projection of the second anode protrusion on the substrate layer.

[0228] In some embodiments, the driving backplane comprises an initial signal connection line and an initial signal line, the initial signal connection line extends along the second direction, the initial signal line extends along the first direction, the initial signal connection line is electrically connected with the initial signal line, and the initial signal line is electrically connected with the pixel circuit.

[0229] A projection of at least part of the initial signal connection line on the substrate layer does not overlap a projection of the first anode sub-block on the substrate layer.

[0230] In some embodiments, part of the initial signal connection line is located in a spacing region between adjacent first anode sub-blocks and / or third anode sub-blocks.

[0231] Part of the initial signal connection line is located in a spacing region between adjacent first anode sub-blocks.

[0232] In some embodiments, the driving backplane comprises a gate signal line, the gate signal line extends along the first direction.

[0233] In the case where the first light emitting device comprises a first anode block, a projection of at least part of the gate signal line on the substrate layer does not overlap a projection of the first anode block on the substrate layer; and / or,

[0234] The second anode block comprises a second anode opening, and a projection of part of the gate signal line on the substrate layer overlaps a projection of the second anode opening on the substrate layer; and / or,

[0235] The third anode block comprises a third anode opening, and a projection of part of the gate signal line on the substrate layer overlaps a projection of the third anode opening on the substrate layer; and / or,

[0236] The first anode block comprises a first anode opening, the anode of the second light emitting device comprises a second anode protrusion, the second anode protrusion is connected with the second anode block, and the second anode protrusion is electrically connected with the pixel circuit through a second anode via hole.

[0237] A projection of the first anode opening on the substrate layer covers a projection of the second anode via hole on the substrate layer.

[0238] In some embodiments, a size of the second anode opening in the first direction is greater than or equal to 2 / 3 of a maximum size of the second anode block in the first direction; and / or,

[0239] a size of the third anode opening in the first direction is greater than or equal to 2 / 3 of a maximum size of the third anode block in the first direction.

[0240] In some embodiments, a plurality of the gate signal lines are arranged in the same layer.

[0241] In some embodiments, the gate signal lines include a first gate signal line, a second gate signal line, a third gate signal line, a fourth gate signal line, and a fifth gate signal line, the first gate signal line, the second gate signal line, the third gate signal line, the fourth gate signal line, and the fifth gate signal line are used to electrically connect gates of different transistors in the pixel circuit respectively, the second gate signal line and the fifth gate signal line are used to transmit the same gate signal;

[0242] At least two of the first gate signal line, the second gate signal line, the third gate signal line, the fourth gate signal line, and the fifth gate signal line are arranged in different conductive layers, and the gate signal lines are arranged in two conductive layers respectively.

[0243] In some embodiments, the first gate signal line, the second gate signal line, the third gate signal line, and the fifth gate signal line are arranged in the same conductive layer, and the fourth gate signal line and the first gate signal line are arranged in different conductive layers respectively.

[0244] In some embodiments, a projection of the fourth gate signal line on the substrate layer overlaps with a projection of the first anode block on the substrate layer; and / or,

[0245] a projection of the fourth gate signal line on the substrate layer overlaps with a projection of the second anode block on the substrate layer; and / or,

[0246] a projection of the fourth gate signal line on the substrate layer overlaps with a projection of the third anode block on the substrate layer.

[0247] In some embodiments, the anode of the first light emitting device includes four first anode sub-blocks, which are a first sub-block, a second sub-block, a third sub-block, and a fourth sub-block respectively;

[0248] The first sub-block and the second sub-block are arranged along a first direction, the first sub-block and the third sub-block are arranged along a second direction, the third sub-block and the fourth sub-block are arranged along the first direction, and the second sub-block and the fourth sub-block are arranged along the second direction.

[0249] The first gate signal line is located in a spacing region between the first sub-block and the third sub-block, and / or the first gate signal line is located in a spacing region between the second sub-block and the fourth sub-block.

[0250] The second gate signal line is located in a spacing region between the first sub-block and the third sub-block, and / or the second gate signal line is located in a spacing region between the second sub-block and the fourth sub-block.

[0251] In some embodiments, the first connection part includes a first sub-connection part and a second sub-connection part.

[0252] The first sub-block and the second sub-block are connected through the first sub-connection part, the first sub-block and the third sub-block are connected through the second sub-connection part, the third sub-block and the fourth sub-block are not provided with the first connection part, and the second sub-block and the fourth sub-block are connected through the second sub-connection part.

[0253] The first gate signal line has an overlapping projection on the substrate layer with the second sub-connection part; and / or,

[0254] The second gate signal line has an overlapping projection on the substrate layer with the second sub-connection part.

[0255] In some embodiments, the first gate signal line has an overlapping projection on the substrate layer with the third anode opening; and / or,

[0256] The second gate signal line has no overlapping projection on the substrate layer with the third anode opening; and / or,

[0257] The fifth gate signal line has an overlapping projection on the substrate layer with the second anode opening; and / or,

[0258] The third gate signal line has an overlapping projection on the substrate layer with the second anode opening.

[0259] In some embodiments, the second anode block comprises a second connecting portion and a plurality of second anode sub-blocks, at least two of the second anode sub-blocks are connected by the second connecting portion, a size of the second anode sub-block in a first direction is greater than a size of the second connecting portion in the first direction, and a portion of the signal lines of the driving backplane are arranged in an interval region between two adjacent second anode sub-blocks; and / or,

[0260] the third anode block comprises a third connecting portion and a plurality of third anode sub-blocks, at least two of the third anode sub-blocks are connected by the third connecting portion, a size of the third anode sub-block in a first direction is greater than a size of the third connecting portion in the first direction, and a portion of the signal lines of the driving backplane are arranged in an interval region between two adjacent third anode sub-blocks.

[0261] In some embodiments, a projection of a portion of the gate signal lines on the substrate layer overlaps with a projection of the second connecting portion on the substrate layer; and / or,

[0262] a projection of a portion of the gate signal lines on the substrate layer overlaps with a projection of the third connecting portion on the substrate layer.

[0263] In some embodiments, the second connecting portion is connected to a main body portion between two ends of the second anode sub-block in the first direction, and at least two second anode openings are formed between at least two second anode sub-blocks; and / or,

[0264] the third connecting portion is connected to a main body portion between two ends of the third anode sub-block in the first direction, and at least two third anode openings are formed between at least two third anode sub-blocks.

[0265] In some embodiments, a shape of a projection of the second anode sub-block on the substrate layer comprises a rectangle; and / or,

[0266] a shape of a projection of the third anode sub-block on the substrate layer comprises a rectangle; and / or,

[0267] a shape of a projection of the second connecting portion on the substrate layer comprises a rectangle; and / or,

[0268] a shape of a projection of the third connecting portion on the substrate layer comprises a rectangle; and / or,

[0269] a shape of a projection of the second anode opening on the substrate layer comprises a rectangle; and / or,

[0270] a shape of a projection of the third anode opening on the substrate layer comprises a rectangle.

[0271] In some embodiments, the driving backplane comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, which are sequentially stacked on one side of the substrate layer;

[0272] The first conductive layer is provided with a plurality of block electrodes and the fourth gate signal line, the block electrodes comprising the gate of a transistor and the plate of a capacitor in the pixel circuit;

[0273] The second conductive layer is provided with a repair line, which extends along the first direction;

[0274] The third conductive layer is provided with the first gate signal line, the second gate signal line, the third gate signal line and the fifth gate signal line;

[0275] The fourth conductive layer is provided with an anode connection electrode, which is electrically connected with the anode of the light-emitting device.

[0276] In some embodiments, the anode connection electrode has an overlapping projection on the substrate layer with the repair line.

[0277] In some embodiments, the driving backplane comprises a data signal line, which extends along the second direction, and is provided in the same layer as the fourth gate signal line.

[0278] In some embodiments, the driving backplane comprises an active layer, which is provided between the substrate layer and the conductive layer where the data signal line is located.

[0279] At least four layers of insulating film are provided between the active layer and the conductive layer where the data signal line is located.

[0280] In some embodiments, the first conductive layer comprises a Ti-Al-Ti laminated structure.

[0281] In some embodiments, the driving backplane comprises a data signal line, a first power supply line, a first enable signal line, a second enable signal line, a first initial signal line, a second initial signal line, a first reference signal line and a second reference signal line.

[0282] The pixel circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor and a second capacitor.

[0283] A first electrode of the first transistor is electrically connected with the data signal line, a second electrode of the first transistor is electrically connected with the second node, and a gate of the first transistor is electrically connected with the first gate signal line;

[0284] One end of the second capacitor is electrically connected with the first power supply line, the other end of the second capacitor is electrically connected with the second node, one end of the first capacitor is electrically connected with the second node, and the other end of the first capacitor is electrically connected with the first node;

[0285] A first electrode of the second transistor is electrically connected with the first node, a gate of the second transistor is electrically connected with the fifth gate signal line, and a second electrode of the second transistor is electrically connected with the fourth node;

[0286] A first electrode of the third transistor is electrically connected with the third node, a second electrode of the third transistor is electrically connected with the fourth node, and a gate of the third transistor is electrically connected with the first node;

[0287] A first electrode of the fifth transistor is electrically connected with the first power supply line, a second electrode of the fifth transistor is electrically connected with the third node, and a gate of the fifth transistor is electrically connected with the first enable signal line;

[0288] A gate of the ninth transistor is electrically connected with the fourth gate signal line, a first electrode of the ninth transistor is electrically connected with the second reference signal line, and a second electrode of the ninth transistor is electrically connected with the third node;

[0289] A first electrode of the sixth transistor is electrically connected with the fourth node, a second electrode of the sixth transistor is electrically connected with the fifth node, and a gate of the sixth transistor is electrically connected with the second enable signal line;

[0290] A second electrode of the eighth transistor is electrically connected with the fifth node, a first electrode of the eighth transistor is electrically connected with the second initial signal line, and a gate of the eighth transistor is electrically connected with the fourth gate signal line;

[0291] A first electrode of the fourth transistor is electrically connected with the first node, a second electrode of the fourth transistor is electrically connected with the first initial signal line, and a gate of the fourth transistor is electrically connected with the third gate signal line;

[0292] A first electrode of the seventh transistor is electrically connected with the second node, a second electrode of the seventh transistor is electrically connected with the first reference signal line, and a gate of the seventh transistor is electrically connected with the second gate signal line;

[0293] The fifth node is used for electrically connecting the light emitting device.

[0294] In some embodiments, at least one of the first transistor, the second transistor, the fourth transistor and the seventh transistor comprises a double-gate structure transistor.

[0295] In some embodiments, the pixel circuit comprises a first pixel circuit, a second pixel circuit and a third pixel circuit, the first pixel circuit is electrically connected with the first light emitting device, the second pixel circuit is electrically connected with the second light emitting device, and the third pixel circuit is electrically connected with the third light emitting device.

[0296] The channel width-length ratio of the third transistor of the first pixel circuit is greater than the channel width-length ratio of the third transistor of the second pixel circuit, and the channel width-length ratio of the third transistor of the first pixel circuit is greater than the channel width-length ratio of the third transistor of the third pixel circuit.

[0297] In some embodiments, the second reference signal line, the first enable signal line, the second enable signal line and the first initial signal line are all arranged on the second conductive layer; and / or,

[0298] The first reference signal line and the second initial signal line are both arranged on the third conductive layer; and / or,

[0299] The first power supply line, the data signal line, the reference signal connection line and the initial signal connection line are all arranged on the fourth conductive layer.

[0300] In a third aspect of the present disclosure, a display panel is provided, comprising:

[0301] a substrate layer;

[0302] a driving backplane arranged on one side of the substrate layer, the driving backplane comprising a pixel circuit;

[0303] a light emitting device layer arranged on a side of the driving backplane away from the substrate layer, the light emitting device layer comprising a plurality of light emitting devices, the light emitting device comprising an anode, the anode being electrically connected with the pixel circuit, the light emitting device comprising a first light emitting device, a second light emitting device and a third light emitting device, the first light emitting device, the second light emitting device and the third light emitting device being respectively used for emitting light of different colors;

[0304] the anode of the first light emitting device comprises a first anode block, the anode of the second light emitting device comprises a second anode block and a second anode extension, the second anode extension being connected with the second anode block, the second anode extension being electrically connected with the pixel circuit through a second anode via, and the third light emitting device comprising a third anode block;

[0305] The first anode blocks and the second anode blocks are arranged in a first direction with intervals, the first anode blocks and the third anode blocks are arranged in the first direction alternately, the second anode blocks and the third anode blocks are arranged in a second direction with intervals, the first direction intersects the second direction.

[0306] The second anode via is located in an interval region between two adjacent first anode blocks in the second direction.

[0307] In some embodiments, the first anode blocks and the pixel circuit are electrically connected through first anode vias, the third anode blocks and the pixel circuit are electrically connected through third anode vias; the first anode vias, the second anode vias and the third anode vias are arranged in the first direction in sequence, and the second anode via is arranged between the first anode via and the third anode via.

[0308] In some embodiments, part of the second anode overhangs are located in an interval region between the first anode block and the second anode block adjacent in the first direction.

[0309] In some embodiments, the second anode overhangs include anode overhang segments and anode via segments, the anode overhang segments are connected between the anode via segments and the second anode blocks, and the anode via segments are electrically connected to the pixel circuit through the second anode vias;

[0310] The second anode via is located in an interval region between two adjacent first anode blocks in the second direction.

[0311] In some embodiments, a distance between the second anode block adjacent to the first anode block is less than a length of the anode overhang segment; and / or,

[0312] The length extension direction of the anode overhang segment intersects the first direction and the second direction; and / or,

[0313] The shape of the anode via segment on the substrate layer includes a rectangle.

[0314] In some embodiments, the first anode blocks have a rectangular shape on the substrate layer; and / or,

[0315] The second anode blocks have a rectangular shape on the substrate layer; and / or,

[0316] a shape of a positive projection of the third anode block on the substrate layer comprises a rectangle; and / or,

[0317] a shape of a positive projection of the second anode overhang on the substrate layer comprises a rectangle; and / or,

[0318] a shape of a positive projection of the anode overhang segment on the substrate layer comprises a rectangle; and / or,

[0319] a shape of a positive projection of the anode via segment on the substrate layer comprises a rectangle.

[0320] In some embodiments, the first anode block is electrically connected to the pixel circuit through a first anode via, the first light emitting device comprises a first anode overhang, the first anode overhang is connected to the first anode block, and a positive projection of the first anode via on the substrate layer falls within a positive projection of the first anode overhang on the substrate layer; and / or,

[0321] the third anode block is electrically connected to the pixel circuit through a third anode via, the third light emitting device comprises a third anode overhang, the third anode block is connected to the third anode overhang, and a positive projection of the third anode via on the substrate layer falls within a positive projection of the third anode overhang on the substrate layer.

[0322] In some embodiments, the first anode block comprises a plurality of first anode sub-blocks, the anode of the first light emitting device comprises a first connecting portion, and the first anode sub-blocks are connected through the first connecting portion;

[0323] the second anode via is located between two first anode sub-blocks adjacent in the second direction.

[0324] In some embodiments, the first anode via and the second anode via adjacent in the first direction are separated by the first anode sub-block, and the first anode via and the third anode via adjacent in the first direction are separated by the first anode sub-block.

[0325] In some embodiments, a positive projection of the first anode via on the substrate layer at least partially overlaps with a positive projection of the first anode sub-block on the substrate.

[0326] In some embodiments, the first anode block comprises at least three first anode sub-blocks, and there are two first anode sub-blocks in the first light emitting device between which no first connecting portion is arranged for direct connection.

[0327] In some embodiments, the first anode sub-blocks in the first light emitting device are sequentially connected end to end through the first connecting portion.

[0328] In some embodiments, the anode of the first light emitting device comprises N first anode sub-blocks, and the N first anode sub-blocks are connected to each other by M first connecting parts, wherein N and M are natural numbers greater than or equal to 3, and 0≤M-N≤2.

[0329] In some embodiments, the first connecting part comprises a first sub-connecting part and a second sub-connecting part, the first sub-connecting part connects two adjacent first anode sub-blocks in the first direction, and the second sub-connecting part connects two adjacent first anode sub-blocks in the second direction.

[0330] The number of the first sub-connecting parts is less than or equal to the number of the second sub-connecting parts.

[0331] In some embodiments, the orthographic projections of at least two first anode sub-blocks on the substrate layer have the same shape and area.

[0332] In some embodiments, in the first light emitting device, two adjacent first anode sub-blocks in the first direction are symmetrical about the first sub-connecting part; and / or,

[0333] In the first light emitting device, two adjacent first anode sub-blocks in the second direction are symmetrical about the second sub-connecting part.

[0334] In some embodiments, the first light emitting device and the second light emitting device are arranged alternately in a first direction, and the first light emitting device and the third light emitting device are arranged alternately in the first direction.

[0335] The second light emitting device and the third light emitting device are arranged alternately in a second direction, and the first light emitting device is arranged in the second direction.

[0336] The first direction intersects the second direction.

[0337] In some embodiments, the shape of the first anode sub-block of two adjacent first light emitting devices in the second direction is mirror set about the first direction; and / or,

[0338] The minimum distance between the second anode block and the first anode sub-block in the first direction is greater than the minimum distance between the second anode block and the third anode block in the second direction.

[0339] In some embodiments, the driving backplane comprises a reference signal connecting line and a first power supply line, both of which are electrically connected to the pixel circuit, and both of which extend along the second direction.

[0340] The reference signal connection line includes a first reference connection segment and a second reference connection segment, the first reference connection segment is connected with the second reference connection segment in the second direction, at least part of the first reference connection segment has a size in the first direction smaller than a size of the second reference connection segment in the first direction, a projection of the first reference connection segment on the substrate layer has no overlap with a projection of the first anode block on the substrate layer, and a projection of the second reference connection segment on the substrate layer has overlap with a projection of the first anode block on the substrate layer; and / or,

[0341] The first power supply line includes a first power supply connection segment and a second power supply connection segment, the first power supply connection segment is connected with the second power supply connection segment in the second direction, at least part of the first power supply connection segment has a size in the first direction smaller than a size of the second power supply connection segment in the first direction, a projection of the first power supply connection segment on the substrate layer has no overlap with a projection of the first anode block on the substrate layer, and a projection of the second power supply connection segment on the substrate layer has overlap with a projection of the first anode block on the substrate layer; and / or, a projection of the first power supply connection segment on the substrate layer has no overlap with a projection of the second anode block on the substrate layer, and a projection of the second power supply connection segment on the substrate layer has overlap with a projection of the second anode block on the substrate layer; and / or, a projection of the first power supply connection segment on the substrate layer has no overlap with a projection of the third anode block on the substrate layer, and a projection of the second power supply connection segment on the substrate layer has overlap with a projection of the third anode block on the substrate layer.

[0342] In some embodiments, a projection of the reference signal connection line on the substrate layer has no overlap with a projection of the second anode block on the substrate layer; and / or,

[0343] A projection of the reference signal connection line on the substrate layer has no overlap with a projection of the third anode block on the substrate layer.

[0344] In some embodiments, part of the reference signal connection line is located in a spacing region between the first anode block and the second anode block adjacent to each other; and / or,

[0345] Part of the reference signal connection line is located in a spacing region between the first anode block and the third anode block adjacent to each other.

[0346] In some embodiments, a projection of part of the reference signal connection line on the substrate layer has overlap with a projection of the second anode extension on the substrate layer.

[0347] In some embodiments, a shape of a projection of the second reference connection segment onto the substrate layer comprises a rectangle; and / or,

[0348] a shape of a projection of the second power connection segment onto the substrate layer comprises a rectangle.

[0349] In some embodiments, the light emitting device layer comprises a pixel defining layer and a light emitting layer, the pixel defining layer comprises a plurality of pixel openings, the light emitting layer is disposed in the pixel openings, a projection of the pixel openings onto the substrate layer falls within a projection of the anode onto the substrate layer;

[0350] In the case that the first anode block comprises a plurality of first anode sub-blocks, the first anode sub-blocks are connected through first connection portions;

[0351] a projection of the second reference connection segment onto the substrate layer overlaps with a projection of at least one of the first anode sub-blocks onto the substrate layer; and / or,

[0352] a projection of the second power connection segment onto the substrate layer overlaps with a projection of at least one of the first anode sub-blocks onto the substrate layer;

[0353] an overlapping area of a projection of the second reference connection segment onto the substrate layer and a projection of the first anode sub-block onto the substrate layer is a first area, an overlapping area of a projection of the second power connection segment onto the substrate layer and a projection of the first anode sub-block onto the substrate layer is a second area, an area of a projection of the first anode sub-block onto the substrate layer is a third area, an overlapping area of a projection of the pixel opening corresponding to the first anode sub-block onto the substrate layer and a projection of the second reference connection segment onto the substrate layer is a fourth area, an overlapping area of a projection of the pixel opening corresponding to the first anode sub-block onto the substrate layer and a projection of the second power connection segment onto the substrate layer is a fifth area, an area of a projection of the pixel opening corresponding to the first anode sub-block onto the substrate layer is a sixth area;

[0354] a ratio of the first area to the third area is greater than or equal to 80%, and / or, a ratio of the second area to the third area is greater than or equal to 80%; and / or,

[0355] a ratio of the fourth area to the sixth area is greater than or equal to 80%, and / or, a ratio of the fifth area to the sixth area is greater than or equal to 80%; and / or,

[0356] a ratio of a sum of the first area and the second area to the third area is greater than or equal to 80%; and / or, a ratio of a sum of the fourth area and the fifth area to the sixth area is greater than or equal to 80%.

[0357] In some embodiments, a projection of the reference signal connection line on the substrate layer has no overlap with a projection of the second anode block on the substrate layer, and a projection of the second power supply connection segment on the substrate layer has overlap with a projection of the second anode block on the substrate layer; and / or,

[0358] a projection of the reference signal connection line on the substrate layer has no overlap with a projection of the third anode block on the substrate layer, and a projection of the second power supply connection segment on the substrate layer has overlap with a projection of the third anode block on the substrate layer.

[0359] In some embodiments, a boundary of a projection of the first anode sub-block on the substrate layer partially overlaps with a boundary of a projection of the first power supply line on the substrate layer, wherein the overlapping boundary extends along the second direction; and / or,

[0360] a boundary of a projection of the first anode sub-block on the substrate layer partially overlaps with a boundary of a projection of the reference signal connection line on the substrate layer, wherein the overlapping boundary extends along the second direction.

[0361] In some embodiments, the driving backplane comprises a data signal line extending along the second direction, the data signal line is electrically connected with the pixel circuit, and the reference signal connection line is located in a region between the first power supply line and the data signal line;

[0362] a projection of the data signal line on the substrate layer has no overlap with a projection of the first anode block on the substrate layer; and / or,

[0363] a projection of the data signal line on the substrate layer has no overlap with a projection of the second anode block on the substrate layer; and / or,

[0364] a projection of the data signal line on the substrate layer has no overlap with a projection of the third anode block on the substrate layer.

[0365] In some embodiments, the first anode block comprises a plurality of first anode sub-blocks, the anode of the first light emitting device comprises a first connection portion;

[0366] A portion of the data signal lines has a projection on the substrate layer that overlaps a projection on the substrate layer of the first connection portion in one of the first light emitting devices; and / or,

[0367] A portion of the data signal lines has a projection on the substrate layer that is located between adjacent first anode sub-blocks in the first light emitting device.

[0368] In some embodiments, the driving backplane includes initial signal connection lines and initial signal lines, the initial signal connection lines extend along the second direction, the initial signal lines extend along the first direction, the initial signal connection lines are electrically connected with the initial signal lines, and the initial signal lines are electrically connected with the pixel circuits.

[0369] The first anode block includes a plurality of first anode sub-blocks.

[0370] A portion of the initial signal connection lines is located in a spacing region between adjacent first anode sub-blocks and the third anode block; and / or,

[0371] A portion of the initial signal connection lines is located in a spacing region between two adjacent first anode sub-blocks.

[0372] In some embodiments, the driving backplane includes gate signal lines, and the gate signal lines extend along the first direction.

[0373] The first anode block includes a plurality of first anode sub-blocks, and a projection on the substrate layer of at least a portion of the gate signal lines does not overlap a projection on the substrate layer of the first anode sub-blocks; and / or,

[0374] The second anode block includes a second anode opening, and a projection on the substrate layer of a portion of the gate signal lines overlaps a projection on the substrate layer of the second anode opening; and / or,

[0375] The third anode block includes a third anode opening, and a projection on the substrate layer of a portion of the gate signal lines overlaps a projection on the substrate layer of the third anode opening.

[0376] In some embodiments, a size of the second anode opening in the first direction is greater than or equal to 2 / 3 of a maximum size of the second anode block in the first direction; and / or,

[0377] A size of the third anode opening in the first direction is greater than or equal to 2 / 3 of a maximum size of the third anode block in the first direction.

[0378] In some embodiments, a plurality of the gate signal lines are arranged in the same layer.

[0379] In some embodiments, the gate signal lines include a first gate signal line, a second gate signal line, a third gate signal line, a fourth gate signal line, and a fifth gate signal line, the first gate signal line, the second gate signal line, the third gate signal line, the fourth gate signal line, and the fifth gate signal line are configured to electrically connect the gate of different transistors in the pixel circuit respectively, the second gate signal line and the fifth gate signal line are configured to transmit the same gate signal;

[0380] At least two of the first gate signal line, the second gate signal line, the third gate signal line, the fourth gate signal line, and the fifth gate signal line are disposed on different conductive layers, and the gate signal lines are disposed on two conductive layers respectively.

[0381] In some embodiments, the first gate signal line, the second gate signal line, the third gate signal line, and the fifth gate signal line are disposed on the same conductive layer, and the fourth gate signal line and the first gate signal line are disposed on different conductive layers respectively.

[0382] In some embodiments, the fourth gate signal line has an overlapping projection on the substrate layer with the first anode block; and / or,

[0383] The fourth gate signal line has an overlapping projection on the substrate layer with the second anode block; and / or,

[0384] The fourth gate signal line has an overlapping projection on the substrate layer with the third anode block.

[0385] In some embodiments, the anode of the first light emitting device includes four first anode sub-blocks, which are a first sub-block, a second sub-block, a third sub-block, and a fourth sub-block respectively;

[0386] The first sub-block and the second sub-block are arranged along a first direction, the first sub-block and the third sub-block are arranged along a second direction, the third sub-block and the fourth sub-block are arranged along the first direction, and the second sub-block and the fourth sub-block are arranged along the second direction;

[0387] The first gate signal line is located in the interval region between the first sub-block and the third sub-block, and / or the first gate signal line is located in the interval region between the second sub-block and the fourth sub-block; and / or,

[0388] The second gate signal line is located in the interval region between the first sub-block and the third sub-block, and / or the second gate signal line is located in the interval region between the second sub-block and the fourth sub-block.

[0389] In some embodiments, the first gate signal line has an overlapping projection on the substrate layer with the third anode opening.

[0390] The second gate signal line has an overlapping projection on the substrate layer with the third anode opening.

[0391] The fifth gate signal line has an overlapping projection on the substrate layer with the second anode opening.

[0392] The third gate signal line has an overlapping projection on the substrate layer with the second anode opening.

[0393] In some embodiments, the second anode block comprises a second connecting portion and a plurality of second anode sub-blocks, at least two of the second anode sub-blocks are connected by the second connecting portion, the size of the second anode sub-block in the first direction is greater than the size of the second connecting portion in the first direction, and part of the signal lines of the driving backplate are arranged in the interval region between two adjacent second anode sub-blocks; and / or,

[0394] The third anode block comprises a third connecting portion and a plurality of third anode sub-blocks, at least two of the third anode sub-blocks are connected by the third connecting portion, the size of the third anode sub-block in the first direction is greater than the size of the third connecting portion in the first direction, and part of the signal lines of the driving backplate are arranged in the interval region between two adjacent third anode sub-blocks.

[0395] In some embodiments, part of the gate signal lines has an overlapping projection on the substrate layer with the second connecting portion; and / or,

[0396] Part of the gate signal lines has an overlapping projection on the substrate layer with the third connecting portion.

[0397] In some embodiments, the second connecting portion is connected to the main part between the two ends of the second anode sub-block in the first direction, and at least two second anode openings are formed between at least two second anode sub-blocks; and / or,

[0398] The third connecting part is connected to the main body part between two ends of the third anode sub-block in the first direction, and at least two third anode openings are formed between the at least two third anode sub-blocks.

[0399] In some embodiments, the shape of the second anode sub-block orthogonally projected on the substrate layer comprises a rectangle; and / or,

[0400] The shape of the third anode sub-block orthogonally projected on the substrate layer comprises a rectangle; and / or,

[0401] The shape of the second connecting part orthogonally projected on the substrate layer comprises a rectangle; and / or,

[0402] The shape of the third connecting part orthogonally projected on the substrate layer comprises a rectangle; and / or,

[0403] The shape of the second anode opening orthogonally projected on the substrate layer comprises a rectangle; and / or,

[0404] The shape of the third anode opening orthogonally projected on the substrate layer comprises a rectangle.

[0405] In some embodiments, the driving backplane comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are sequentially stacked on one side of the substrate layer;

[0406] The first conductive layer is provided with a plurality of block electrodes and the fourth gate signal line, the block electrodes comprise the gate of a transistor and the plate of a capacitor in the pixel circuit;

[0407] The second conductive layer is provided with a repair line, the repair line extends along the first direction;

[0408] The third conductive layer is provided with the first gate signal line, the second gate signal line, the third gate signal line and the fifth gate signal line;

[0409] The fourth conductive layer is provided with an anode connecting electrode, the anode connecting electrode is electrically connected with the anode of the light emitting device.

[0410] In some embodiments, the fourth conductive layer comprises a data signal line and a first power line, the data signal line and the first power line both extend along a second direction, the second direction is perpendicular to the first direction; and / or,

[0411] The orthographic projection of the anode connecting electrode on the substrate layer and the orthographic projection of the repair line on the substrate layer overlap.

[0412] In some embodiments, the driving backplane comprises a data signal line extending along the second direction, the data signal line is arranged in the same layer as the fourth gate signal line;

[0413] The driving backplane comprises an active layer arranged between the substrate layer and the conductive layer where the data signal line is arranged;

[0414] At least four layers of insulating thin films are arranged between the active layer and the conductive layer where the data signal line is arranged.

[0415] In some embodiments, the first conductive layer comprises a Ti-Al-Ti stacked structure.

[0416] In some embodiments, the pixel circuit comprises a first pixel circuit, a second pixel circuit and a third pixel circuit, the first pixel circuit is electrically connected with the first light emitting device, the second pixel circuit is electrically connected with the second light emitting device, and the third pixel circuit is electrically connected with the third light emitting device.

[0417] The channel width-length ratio of the driving transistor of the first pixel circuit is greater than the channel width-length ratio of the driving transistor of the second pixel circuit, and the channel width-length ratio of the driving transistor of the first pixel circuit is greater than the channel width-length ratio of the driving transistor of the third pixel circuit.

[0418] In some embodiments, the driving backplane comprises a data signal line, a first power supply line, a first enable signal line, a second enable signal line, a first initial signal line, a second initial signal line, a first reference signal line and a second reference signal line.

[0419] The pixel circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor and a second capacitor.

[0420] The first electrode of the first transistor is electrically connected with the data signal line, the second electrode of the first transistor is electrically connected with a second node, and the gate of the first transistor is electrically connected with the first gate signal line.

[0421] One end of the second capacitor is electrically connected with the first power supply line, the other end of the second capacitor is electrically connected with the second node, one end of the first capacitor is electrically connected with the second node, and the other end of the first capacitor is electrically connected with a first node.

[0422] The first electrode of the second transistor is electrically connected with the first node, the gate of the second transistor is electrically connected with the fifth gate signal line, and the second electrode of the second transistor is electrically connected with a fourth node.

[0423] a first electrode of the third transistor is electrically connected with the third node, a second electrode of the third transistor is electrically connected with the fourth node, and a gate of the third transistor is electrically connected with the first node;

[0424] a first electrode of the fifth transistor is electrically connected with a first power supply line, a second electrode of the fifth transistor is electrically connected with the third node, and a gate of the fifth transistor is electrically connected with a first enable signal line;

[0425] a gate of the ninth transistor is electrically connected with the fourth gate signal line, a first electrode of the ninth transistor is electrically connected with a second reference signal line, and a second electrode of the ninth transistor is electrically connected with the third node;

[0426] a first electrode of the sixth transistor is electrically connected with the fourth node, a second electrode of the sixth transistor is electrically connected with a fifth node, and a gate of the sixth transistor is electrically connected with a second enable signal line;

[0427] a second electrode of the eighth transistor is electrically connected with the fifth node, a first electrode of the eighth transistor is electrically connected with a second initial signal line, and a gate of the eighth transistor is electrically connected with the fourth gate signal line;

[0428] a first electrode of the fourth transistor is electrically connected with the first node, a second electrode of the fourth transistor is electrically connected with a first initial signal line, and a gate of the fourth transistor is electrically connected with the third gate signal line;

[0429] a first electrode of the seventh transistor is electrically connected with the second node, a second electrode of the seventh transistor is electrically connected with a first reference signal line, and a gate of the seventh transistor is electrically connected with the second gate signal line;

[0430] the fifth node is configured to electrically connect the light emitting device.

[0431] In some embodiments, at least one of the first transistor, the second transistor, the fourth transistor and the seventh transistor comprises a dual-gate structure transistor.

[0432] In some embodiments, the second reference signal line, the first enable signal line, the second enable signal line and the first initial signal line are all disposed in the second conductive layer; and / or,

[0433] the first reference signal line and the second initial signal line are both disposed in the third conductive layer; and / or,

[0434] the first power supply line, the data signal line, the reference signal connection line and the initial signal connection line are all disposed in the fourth conductive layer.

[0435] In a fourth aspect, the present disclosure provides a display panel, comprising:

[0436] a substrate layer;

[0437] a driving backplane disposed on one side of the substrate layer, the driving backplane comprising a pixel circuit;

[0438] a light emitting device layer disposed on a side of the driving backplane away from the substrate layer, the light emitting device layer comprising a plurality of light emitting devices, the light emitting device comprising an anode, the anode being electrically connected to the pixel circuit, the light emitting device comprising a first light emitting device, a second light emitting device and a third light emitting device, the first light emitting device, the second light emitting device and the third light emitting device being configured to emit light of different colors, respectively;

[0439] the second anode block of the second light emitting device comprises a second anode opening, a projection of the second anode opening on the substrate layer overlaps with a projection of a part of signal lines of the driving backplane on the substrate layer; and / or,

[0440] the third anode block of the third light emitting device comprises a third anode opening, a projection of the third anode opening on the substrate layer overlaps with a projection of a part of signal lines of the driving backplane on the substrate layer.

[0441] In some embodiments, the first light emitting device comprises a first anode block, the first anode block comprises a first anode opening, the anode of the second light emitting device comprises a second anode extension, the second anode extension is connected to the second anode block, the second anode extension is electrically connected to the pixel circuit through a second anode via;

[0442] a projection of the first anode opening on the substrate layer covers a projection of the second anode via on the substrate layer.

[0443] In some embodiments, the first anode block comprises a plurality of first anode sub-blocks, the first anode sub-block comprises the first anode opening;

[0444] a projection of a part of the second anode extension on the substrate layer falls within a projection of the first anode opening on the substrate layer.

[0445] In some embodiments, the anode of the first light emitting device comprises a first connection part, at least two first anode sub-blocks are electrically connected through the first connection part;

[0446] The anode of the first light-emitting device comprises at least three first anode sub-blocks, and there is no first connection part directly connecting between two of the first anode sub-blocks in the first light-emitting device.

[0447] In some embodiments, the first anode sub-blocks in the first light-emitting device are sequentially connected end to end by the first connection parts.

[0448] In some embodiments, the anode of the first light-emitting device comprises N first anode sub-blocks, and the N first anode sub-blocks are connected to each other by M first connection parts, wherein N and M are natural numbers greater than or equal to 3, and 0≤M-N≤2.

[0449] In some embodiments, the first connection part comprises a first sub-connection part and a second sub-connection part, the first sub-connection part connects two adjacent first anode sub-blocks in a first direction, the second sub-connection part connects two adjacent first anode sub-blocks in a second direction, and the first direction intersects the second direction.

[0450] The number of the first sub-connection parts is less than or equal to the number of the second sub-connection parts.

[0451] In some embodiments, the orthographic projections of at least two first anode sub-blocks on the substrate layer are the same in shape and area.

[0452] In some embodiments, in the first light-emitting device, two adjacent first anode sub-blocks in the first direction are symmetric about the first sub-connection part; and / or,

[0453] In the first light-emitting device, two adjacent first anode sub-blocks in the second direction are symmetric about the second sub-connection part.

[0454] In some embodiments, the first light-emitting devices and the second light-emitting devices are alternately arranged in a first direction, and the first light-emitting devices and the third light-emitting devices are alternately arranged in the first direction.

[0455] The second light-emitting devices and the third light-emitting devices are alternately arranged in a second direction, and the first light-emitting devices are arranged in the second direction.

[0456] The first direction intersects the second direction.

[0457] In some embodiments, the shapes of the first anode sub-blocks of two adjacent first light-emitting devices in the second direction are mirror images about the first direction.

[0458] In some embodiments, the first anode sub-block is electrically connected with the pixel circuit through a first anode via,

[0459] The first connecting part is arranged in a spacing region between the two first anode sub-blocks connected with each other, and a projection of the first anode via on the substrate layer falls within a projection of the first connecting part on the substrate layer.

[0460] In some embodiments, the first anode sub-block is electrically connected with the pixel circuit through a first anode via, the second anode block is electrically connected with the pixel circuit through a second anode via, and the third anode block is electrically connected with the pixel circuit through a third anode via.

[0461] The first anode via, the second anode via and the third anode via are arranged in sequence in the first direction, and the second anode via is arranged between the first anode via and the third anode via.

[0462] In some embodiments, the second anode via is located between two first anode sub-blocks adjacent in a second direction, and the first direction intersects the second direction.

[0463] In some embodiments, the first anode sub-block is arranged between the first anode via and the second anode via adjacent in the first direction, and the first anode sub-block is arranged between the first anode via and the third anode via adjacent in the first direction.

[0464] In some embodiments, a projection of the first anode via on the substrate layer at least partially overlaps with a projection of the first anode sub-block on the substrate.

[0465] In some embodiments, the anode of the first light emitting device comprises a first anode extension part, the first anode extension part is connected with the first anode sub-block, and a projection of the first anode via on the substrate layer falls within a projection of the first anode extension part on the substrate layer; and / or,

[0466] The anode of the second light emitting device comprises a second anode extension part, the second anode extension part is connected with the second anode block, and a projection of the second anode via on the substrate layer falls within a projection of the second anode extension part on the substrate layer; and / or,

[0467] The anode of the third light emitting device comprises a third anode extension part, the third anode extension part is connected with the third anode block, and a projection of the third anode via on the substrate layer falls within a projection of the third anode extension part on the substrate layer.

[0468] In some embodiments, the second anode overhang is located in a spacing region between the first anode sub-block and the second anode block; and / or,

[0469] the third anode overhang is located in a spacing region between the second anode block and the third anode block; and / or,

[0470] a length extension direction of the second anode overhang intersects the first direction, and the length extension direction of the second anode overhang intersects the second direction, the first direction intersects the second direction.

[0471] In some embodiments, part of the second anode overhang is located between the first anode sub-blocks adjacent in the second direction.

[0472] In some embodiments, the second anode overhang includes an anode overhang segment and an anode via segment, the anode overhang segment is connected between the anode via segment and the second anode block, and the anode via segment is electrically connected with the pixel circuit through the second anode via;

[0473] a projection of the second anode via on the substrate layer falls within a projection of the anode via segment on the substrate layer, the anode overhang segment is located in a spacing region between the first anode sub-blocks adjacent in the first direction and the second anode block, and the anode via segment is located between the first anode sub-blocks adjacent in the second direction.

[0474] In some embodiments, a distance between the second anode block adjacent and the first anode sub-block is less than a length of the anode overhang segment; and / or,

[0475] a length extension direction of the anode overhang segment intersects the first direction, and the length extension direction of the anode overhang segment intersects the second direction; and / or,

[0476] a shape of the projection of the anode via segment on the substrate layer includes a rectangle.

[0477] In some embodiments, a shape of the projection of the first anode overhang on the substrate layer includes a rectangle; and / or,

[0478] a shape of the projection of the second anode overhang on the substrate layer includes a rectangle; and / or,

[0479] a shape of the projection of the third anode overhang on the substrate layer includes a rectangle; and / or,

[0480] a shape of the projection of the first anode sub-block on the substrate layer includes a rectangle; and / or,

[0481] The shape of the first connecting portion in orthographic projection on the substrate layer comprises a rectangle; and / or,

[0482] The shape of the second anode block in orthographic projection on the substrate layer comprises a rectangle; and / or,

[0483] The shape of the third anode block in orthographic projection on the substrate layer comprises a rectangle.

[0484] In some embodiments, the second anode block comprises a plurality of second anode sub-blocks, the anode of the second light emitting device comprises a second connecting portion, at least two of the second anode sub-blocks are connected by the second connecting portion, the size of the second anode sub-block in a first direction is greater than the size of the second connecting portion in the first direction, and part of the signal lines of the driving backplate are arranged in the interval region between two adjacent second anode sub-blocks; and / or,

[0485] The third anode block comprises a plurality of third anode sub-blocks, the anode of the third light emitting device comprises a third connecting portion, at least two of the third anode sub-blocks are connected by the third connecting portion, the size of the third anode sub-block in a first direction is greater than the size of the third connecting portion in the first direction, and part of the signal lines of the driving backplate are arranged in the interval region between two adjacent third anode sub-blocks.

[0486] In some embodiments, the second connecting portion connects two second anode sub-blocks in a second direction; and / or,

[0487] The third connecting portion connects two third anode sub-blocks in a second direction; and / or,

[0488] The connection of the second anode sub-block and the second connecting portion is used to form the second anode opening, and the connection of the third anode sub-block and the third connecting portion is used to form the third anode opening.

[0489] The second anode opening comprises a gap hollow with an open mouth and / or a closed hollow with a closed shape, and the third anode opening comprises a gap hollow with an open mouth and / or a closed hollow with a closed shape.

[0490] In some embodiments, the second connecting portion is connected to the main body part between the two ends of the second anode sub-block in the first direction, and at least two second anode openings are formed between at least two second anode sub-blocks; and / or,

[0491] The third connecting portion is connected to the main body part between the two ends of the third anode sub-block in the first direction, and at least two third anode openings are formed between at least two third anode sub-blocks.

[0492] In some embodiments, a size of the second anode opening in the first direction is greater than or equal to 2 / 3 of a maximum size of the second anode block in the first direction; and / or,

[0493] a size of the third anode opening in the first direction is greater than or equal to 2 / 3 of a maximum size of the third anode block in the first direction.

[0494] In some embodiments, the signal lines of the driving backplane include gate signal lines, the gate signal lines extending along a first direction;

[0495] In a case where the first light emitting device includes a first anode block, a footprint of at least part of the gate signal lines on the substrate layer does not overlap with a footprint of the first anode block on the substrate layer; and / or,

[0496] A footprint of part of the gate signal lines on the substrate layer overlaps with footprints of the second anode opening and the third anode opening.

[0497] In some embodiments, a size of the second anode sub-block in the first direction is greater than a size of the second anode sub-block in the second direction; and / or,

[0498] a size of the third anode sub-block in the first direction is greater than a size of the third anode sub-block in the second direction.

[0499] In some embodiments, a shape of a footprint of the second anode sub-block on the substrate layer includes a rectangle; and / or,

[0500] a shape of a footprint of the third anode sub-block on the substrate layer includes a rectangle; and / or,

[0501] a shape of a footprint of the second connection portion on the substrate layer includes a rectangle; and / or,

[0502] a shape of a footprint of the third connection portion on the substrate layer includes a rectangle; and / or,

[0503] a shape of a footprint of the second anode opening on the substrate layer includes a rectangle; and / or,

[0504] a shape of a footprint of the third anode opening on the substrate layer includes a rectangle.

[0505] In some embodiments, the first anode block comprises a plurality of first anode sub-blocks, the anode of the first light emitting device comprises a first connecting portion, at least two of the first anode sub-blocks are connected by the first connecting portion, and part of the gate signal lines are arranged in the interval region between adjacent first anode sub-blocks.

[0506] In some embodiments, a plurality of the gate signal lines are arranged in the same layer.

[0507] In some embodiments, the gate signal lines comprise a first gate signal line, a second gate signal line, a third gate signal line, a fourth gate signal line, and a fifth gate signal line, the first gate signal line, the second gate signal line, the third gate signal line, the fourth gate signal line, and the fifth gate signal line are used to electrically connect the gate of different transistors in the pixel circuit respectively, and the second gate signal line and the fifth gate signal line are used to transmit the same gate signal.

[0508] At least two of the first gate signal line, the second gate signal line, the third gate signal line, the fourth gate signal line, and the fifth gate signal line are arranged in different conductive layers, and the gate signal lines are arranged in two conductive layers respectively.

[0509] In some embodiments, the first gate signal line, the second gate signal line, the third gate signal line, and the fifth gate signal line are arranged in the same conductive layer, and the fourth gate signal line and the first gate signal line are arranged in different conductive layers respectively.

[0510] In some embodiments, the fourth gate signal line has an overlapping projection on the substrate layer with the first anode sub-block, and / or,

[0511] The fourth gate signal line has an overlapping projection on the substrate layer with the second anode block, and / or,

[0512] The fourth gate signal line has an overlapping projection on the substrate layer with the third anode block.

[0513] In some embodiments, the anode of the first light emitting device comprises four first anode sub-blocks, which are a first sub-block, a second sub-block, a third sub-block, and a fourth sub-block respectively.

[0514] The first sub-block and the second sub-block are arranged along a first direction, the first sub-block and the third sub-block are arranged along a second direction, the third sub-block and the fourth sub-block are arranged along the first direction, and the second sub-block and the fourth sub-block are arranged along the second direction.

[0515] The first gate signal line is located in the interval region between the first sub-block and the third sub-block, and / or the first gate signal line is located in the interval region between the second sub-block and the fourth sub-block; and / or,

[0516] The second gate signal line is located in the interval region between the first sub-block and the third sub-block, and / or the second gate signal line is located in the interval region between the second sub-block and the fourth sub-block.

[0517] In some embodiments, the first connection part includes a first sub-connection part and a second sub-connection part;

[0518] The first sub-block and the second sub-block are connected through the first sub-connection part, the first sub-block and the third sub-block are connected through the second sub-connection part, the first connection part is not arranged between the third sub-block and the fourth sub-block, and the second sub-block and the fourth sub-block are connected through the second sub-connection part;

[0519] The first gate signal line has an intersection with the second sub-connection part on the substrate layer; and / or,

[0520] The second gate signal line has an intersection with the second sub-connection part on the substrate layer.

[0521] In some embodiments, the first gate signal line has an intersection with the third anode opening on the substrate layer; and / or,

[0522] The second gate signal line has an intersection with the third anode opening on the substrate layer; and / or,

[0523] The fifth gate signal line has an intersection with the second anode opening on the substrate layer; and / or,

[0524] The third gate signal line has an intersection with the second anode opening on the substrate layer.

[0525] In some embodiments, part of the gate signal line has an intersection with the second connection part on the substrate layer; and / or,

[0526] Part of the gate signal line has an intersection with the third connection part on the substrate layer.

[0527] In some embodiments, the driving backplane comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, which are sequentially stacked on one side of the substrate layer;

[0528] The first conductive layer is provided with a plurality of block electrodes and the fourth gate signal line, the block electrodes comprising the gate of a transistor and the plate of a capacitor in the pixel circuit;

[0529] The second conductive layer is provided with a repair line, which extends along the first direction;

[0530] The third conductive layer is provided with the first gate signal line, the second gate signal line, the third gate signal line and the fifth gate signal line;

[0531] The fourth conductive layer is provided with an anode connecting electrode, which is electrically connected with the anode of the light emitting device.

[0532] In some embodiments, the anode connecting electrode has an overlapping projection on the substrate layer with the repair line.

[0533] In some embodiments, the first conductive layer comprises a data signal line, which extends along a second direction perpendicular to the first direction.

[0534] In some embodiments, the driving backplane comprises an active layer, which is arranged between the substrate layer and the first conductive layer;

[0535] At least four layers of insulating films are arranged between the active layer and the first conductive layer.

[0536] In some embodiments, the first conductive layer comprises a Ti-Al-Ti stacked structure.

[0537] In some embodiments, the driving backplane comprises a data signal line, a first power supply line, a first enable signal line, a second enable signal line, a first initial signal line, a second initial signal line, a first reference signal line and a second reference signal line;

[0538] The pixel circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor and a second capacitor;

[0539] The first electrode of the first transistor is electrically connected with a data signal line, the second electrode of the first transistor is electrically connected with a second node, and the gate of the first transistor is electrically connected with the first gate signal line.

[0540] One end of the second capacitor is electrically connected with the first power supply line, the other end of the second capacitor is electrically connected with the second node, one end of the first capacitor is electrically connected with the second node, the other end of the first capacitor is electrically connected with the first node;

[0541] The first electrode of the second transistor is electrically connected with the first node, the gate of the second transistor is electrically connected with the fifth gate signal line, the second electrode of the second transistor is electrically connected with the fourth node;

[0542] The first electrode of the third transistor is electrically connected with the third node, the second electrode of the third transistor is electrically connected with the fourth node, the gate of the third transistor is electrically connected with the first node;

[0543] The first electrode of the fifth transistor is electrically connected with the first power supply line, the second electrode of the fifth transistor is electrically connected with the third node, the gate of the fifth transistor is electrically connected with the first enable signal line;

[0544] The gate of the ninth transistor is electrically connected with the fourth gate signal line, the first electrode of the ninth transistor is electrically connected with the second reference signal line, the second electrode of the ninth transistor is electrically connected with the third node;

[0545] The first electrode of the sixth transistor is electrically connected with the fourth node, the second electrode of the sixth transistor is electrically connected with the fifth node, the gate of the sixth transistor is electrically connected with the second enable signal line;

[0546] The second electrode of the eighth transistor is electrically connected with the fifth node, the first electrode of the eighth transistor is electrically connected with the second initial signal line, the gate of the eighth transistor is electrically connected with the fourth gate signal line;

[0547] The first electrode of the fourth transistor is electrically connected with the first node, the second electrode of the fourth transistor is electrically connected with the first initial signal line, the gate of the fourth transistor is electrically connected with the third gate signal line;

[0548] The first electrode of the seventh transistor is electrically connected with the second node, the second electrode of the seventh transistor is electrically connected with the first reference signal line, the gate of the seventh transistor is electrically connected with the second gate signal line;

[0549] The fifth node is used for electrically connecting the light emitting device.

[0550] In some embodiments, at least one of the first transistor, the second transistor, the fourth transistor and the seventh transistor comprises a double-gate structure transistor.

[0551] In some embodiments, the pixel circuit includes a first pixel circuit, a second pixel circuit and a third pixel circuit, the first pixel circuit is electrically connected with the first light emitting device, the second pixel circuit is electrically connected with the second light emitting device, and the third pixel circuit is electrically connected with the third light emitting device.

[0552] The channel width-length ratio of the third transistor of the first pixel circuit is greater than the channel width-length ratio of the third transistor of the second pixel circuit, and the channel width-length ratio of the third transistor of the first pixel circuit is greater than the channel width-length ratio of the third transistor of the third pixel circuit.

[0553] In some embodiments, the second reference signal line, the first enable signal line, the second enable signal line and the first initial signal line are all disposed on the second conductive layer; and / or,

[0554] The first reference signal line and the second initial signal line are both disposed on the third conductive layer; and / or,

[0555] The first power supply line, the data signal line, the reference signal connection line and the initial signal connection line are all disposed on the fourth conductive layer.

[0556] In some embodiments, the driving backplane includes a data signal line, the data signal line extends along a second direction, and the data signal line is electrically connected with the pixel circuit.

[0557] The anode of the first light emitting device includes a first anode block, and a projection of the data signal line on the substrate layer does not overlap with a projection of the first anode block on the substrate layer; and / or,

[0558] The projection of the data signal line on the substrate layer does not overlap with a projection of the second anode block on the substrate layer; and / or,

[0559] The projection of the data signal line on the substrate layer does not overlap with a projection of the third anode block on the substrate layer.

[0560] In some embodiments, a part of the projection of the data signal line on the substrate layer overlaps with a projection of one of the first connection portions in the first light emitting device on the substrate layer; and / or,

[0561] A part of the projection of the data signal line on the substrate layer is located in a spacing region between adjacent first anode sub-blocks in the first light emitting device; and / or,

[0562] In a case where the anode of the second light-emitting device includes a second anode overhang, a portion of the data signal line has an overlap with a projection of the second anode overhang on the substrate layer.

[0563] In some embodiments, the driving backplane includes a reference signal connection line and a first power supply line, the reference signal connection line and the first power supply line both extend along the second direction, the reference signal connection line is located between the data signal line and the first power supply line, the reference signal connection line and the first power supply line are both electrically connected with the pixel circuit, and the second direction intersects the first direction.

[0564] The reference signal connection line includes a first reference connection segment and a second reference connection segment, the first reference connection segment and the second reference connection segment are connected in the second direction, at least a portion of the first reference connection segment has a size in the first direction that is smaller than a size of the second reference connection segment in the first direction, a projection of the first reference connection segment on the substrate layer has no overlap with a projection of the first anode block on the substrate layer, and a projection of the second reference connection segment on the substrate layer has an overlap with a projection of the first anode block on the substrate layer; and / or,

[0565] The first power supply line includes a first power supply connection segment and a second power supply connection segment, the first power supply connection segment and the second power supply connection segment are connected in the second direction, at least a portion of the first power supply connection segment has a size in the first direction that is smaller than a size of the second power supply connection segment in the first direction, a projection of the first power supply connection segment on the substrate layer has no overlap with a projection of the first anode block on the substrate layer, and a projection of the second power supply connection segment on the substrate layer has an overlap with a projection of the first anode block on the substrate layer; and / or, a projection of the first power supply connection segment on the substrate layer has no overlap with a projection of the second anode block on the substrate layer, a projection of the second power supply connection segment on the substrate layer has an overlap with a projection of the second anode block on the substrate layer; and / or, a projection of the first power supply connection segment on the substrate layer has no overlap with a projection of the third anode block on the substrate layer, and a projection of the second power supply connection segment on the substrate layer has an overlap with a projection of the third anode block on the substrate layer.

[0566] In some embodiments, a projection of the reference signal connection line on the substrate layer has no overlap with a projection of the second anode block on the substrate layer; and / or,

[0567] A projection of the reference signal connection line on the substrate layer does not overlap with a projection of the third anode block on the substrate layer.

[0568] In some embodiments, part of the reference signal connection line is located in a spacing region between the adjacent first anode sub-block and the second anode block; and / or,

[0569] Part of the reference signal connection line is located in a spacing region between the adjacent first anode sub-block and the third anode block.

[0570] In some embodiments, the anode of the second light emitting device comprises a second anode extension, the second anode block is connected with the second anode extension, the second anode extension is electrically connected with the pixel circuit through a second anode via, and a projection of the second anode via on the substrate layer falls within a projection on the substrate layer of an end of the second anode extension away from the second anode block;

[0571] Part of the reference signal connection line overlaps with a projection of the second anode extension on the substrate layer.

[0572] In some embodiments, a shape of a projection of the second reference connection segment on the substrate layer comprises a rectangle; and / or,

[0573] A shape of a projection of the second power supply connection segment on the substrate layer comprises a rectangle.

[0574] In some embodiments, the light emitting device layer comprises a pixel defining layer and a light emitting layer, the pixel defining layer comprises a plurality of pixel openings, and the light emitting layer is disposed in the pixel openings, a projection of the pixel openings on the substrate layer falls within a projection of the anode on the substrate layer.

[0575] In the case that the second reference connection segment has an overlap with the first anode sub-block on the substrate layer and the second power supply connection segment has an overlap with the first anode sub-block on the substrate layer, an overlapping area of the second reference connection segment on the substrate layer and the first anode sub-block on the substrate layer is a first area, an overlapping area of the second power supply connection segment on the substrate layer and the first anode sub-block on the substrate layer is a second area, an area of the first anode sub-block on the substrate layer is a third area, an overlapping area of the pixel opening corresponding to the first anode sub-block on the substrate layer and the second reference connection segment on the substrate layer is a fourth area, an overlapping area of the pixel opening corresponding to the first anode sub-block on the substrate layer and the second power supply connection segment on the substrate layer is a fifth area, and an area of the pixel opening corresponding to the first anode sub-block on the substrate layer is a sixth area;

[0576] A ratio of the first area to the third area is greater than or equal to 80%, and / or a ratio of the second area to the third area is greater than or equal to 80%; and / or,

[0577] A ratio of the fourth area to the sixth area is greater than or equal to 80%, and / or a ratio of the fifth area to the sixth area is greater than or equal to 80%; and / or,

[0578] A ratio of a sum of the first area and the second area to the third area is greater than or equal to 80%, and / or a ratio of a sum of the fourth area and the fifth area to the sixth area is greater than or equal to 80%.

[0579] In some embodiments, the driving back plate includes a reference signal connection line and a first power supply line, the reference signal connection line and the first power supply line both extend along the second direction, the reference signal connection line is located between the data signal line and the first power supply line, and the reference signal connection line and the first power supply line are both electrically connected to the pixel circuit.

[0580] The reference signal connection line has an overlap with the first anode sub-block on the substrate layer, and the first power supply line has an overlap with the first anode sub-block on the substrate layer.

[0581] A boundary of the first anode sub-block on the substrate layer partially coincides with a boundary of the first power supply line on the substrate layer, and the coinciding boundary extends along the second direction; and / or,

[0582] A boundary of a projection of the first anode sub-block onto the substrate layer partially overlaps with a boundary of a projection of the reference signal connection line onto the substrate layer, wherein the overlapped boundary extends along the second direction.

[0583] In some embodiments, the driving backplane comprises an initial signal connection line extending along the second direction and an initial signal line extending along a first direction, the initial signal connection line is electrically connected with the initial signal line, the initial signal line is electrically connected with the pixel circuit, the first direction intersects with the second direction.

[0584] At least part of the projection of the initial signal connection line onto the substrate layer does not overlap with the projection of the first anode block onto the substrate layer.

[0585] In some embodiments, part of the initial signal connection line is located in the interval region between the adjacent first anode sub-block and the third anode block; and / or,

[0586] Part of the initial signal connection line is located in the interval region between the adjacent first anode sub-block.

[0587] In a fifth aspect, the present disclosure provides a display device, comprising:

[0588] The display panel of any one of the above. BRIEF DESCRIPTION OF DRAWINGS

[0589] FIG. 1 is a schematic structural block diagram of a display panel provided by the present disclosure;

[0590] FIG. 2 is a schematic structural diagram of pixel arrangement of a display panel provided by the present disclosure;

[0591] FIG. 3 is a schematic diagram of a partial cross-sectional structure of a display panel provided by the present disclosure;

[0592] FIG. 4 is a schematic structural diagram of a pixel circuit provided by the present disclosure;

[0593] FIG. 5 is a schematic driving timing diagram of a pixel circuit provided by the present disclosure;

[0594] FIG. 6 is a schematic diagram of a partial planar structure of a display panel provided by the present disclosure;

[0595] FIG. 7 is a schematic diagram of a partial cross-sectional structure of FIG. 6 along the Q1-Q2 direction;

[0596] FIG. 8 is a schematic diagram of a partial planar structure of an active layer provided by the present disclosure;

[0597] Fig. 9 is a partial plan view of the display panel after forming the first conductive layer in Fig. 8;

[0598] Fig. 10 is a partial plan view of a first conductive layer provided by the present disclosure;

[0599] Fig. 11 is a schematic structural view of another pixel circuit provided by the present disclosure;

[0600] Fig. 12 is a partial plan view of the display panel after forming the second conductive layer in Fig. 9;

[0601] Fig. 13 is a partial plan view of a second conductive layer provided by the present disclosure;

[0602] Fig. 14 is a partial plan view of the display panel after etching the via in Fig. 12;

[0603] Fig. 15 is a partial plan view of the display panel after forming the third conductive layer in Fig. 14;

[0604] Fig. 16 is a partial plan view of a third conductive layer provided by the present disclosure;

[0605] Fig. 17 is a partial plan view of the display panel after etching the via in Fig. 15;

[0606] Fig. 18 is a partial plan view of the display panel after forming the fourth conductive layer in Fig. 17;

[0607] Fig. 19 is a partial plan view of a fourth conductive layer provided by the present disclosure;

[0608] Fig. 20 is a signal path schematic view of a pixel circuit in a first stage provided by the present disclosure;

[0609] Fig. 21 is a signal path schematic view of a pixel circuit in a second stage provided by the present disclosure;

[0610] Fig. 22 is a signal path schematic view of a pixel circuit in a third stage provided by the present disclosure;

[0611] Fig. 23 is a signal path schematic view of a pixel circuit in a fourth stage provided by the present disclosure;

[0612] Fig. 24 is a signal path schematic view of a pixel circuit in a fifth stage provided by the present disclosure;

[0613] Fig. 25 is a partial plan view of the display panel after forming the anode in Fig. 19;

[0614] Fig. 26 is a partial cross-sectional view of Fig. 25 along the direction of Q3-Q4;

[0615] FIG. 27 is a schematic diagram of a partial cross-sectional structure of FIG. 25 along a direction of Q5-Q6;

[0616] FIG. 28 is a schematic diagram of a partial planar structure of yet another display panel provided by the present disclosure;

[0617] FIG. 29 is a schematic diagram of a partial planar structure of a display panel after forming an anode in FIG. 28;

[0618] FIG. 30 is a schematic diagram of a partial cross-sectional structure of FIG. 29 along a direction of Q7-Q8;

[0619] FIG. 31 is a schematic diagram of a partial planar structure of another display panel after forming an anode in FIG. 28;

[0620] FIG. 32 is a schematic diagram of a partial planar structure of yet another display panel after forming an anode in FIG. 28;

[0621] FIG. 33 is a schematic diagram of a partial planar structure of still another display panel after forming an anode in FIG. 28;

[0622] FIG. 34 is a schematic diagram of a partial planar structure of a display panel after forming an anode in FIG. 28;

[0623] FIG. 35 is a schematic diagram of a partial planar structure of an anode provided by the present disclosure;

[0624] FIG. 36 is a schematic diagram of a partial cross-sectional structure of FIG. 35 along a direction of Q9-Q10;

[0625] FIG. 37 is a schematic diagram of a partial planar structure of a reference signal connection line and a first power supply line provided by the present disclosure;

[0626] FIG. 38 is a schematic diagram of a partial planar structure of another fourth conductive layer provided by the present disclosure;

[0627] FIG. 39 is a schematic diagram of a partial structure of another display panel provided by the present disclosure;

[0628] FIG. 40 is a schematic diagram of a partial planar structure of yet another display panel provided by the present disclosure;

[0629] FIG. 41 is a schematic diagram of a partial planar structure of yet another fourth conductive layer provided by the present disclosure;

[0630] FIG. 42 is a schematic diagram of a partial planar structure of yet another anode provided by the present disclosure;

[0631] FIG. 43 is a schematic diagram of a partial planar structure of still another display panel provided by the present disclosure;

[0632] FIG. 44 is a schematic diagram of a partial planar structure of still another anode provided by the present disclosure;

[0633] FIG. 45 is a schematic diagram of a partial planar structure of a display panel according to the present disclosure;

[0634] FIG. 46 is a schematic diagram of a partial planar structure of an anode according to the present disclosure;

[0635] FIG. 47 is a schematic diagram of a partial planar structure of another display panel according to the present disclosure;

[0636] FIG. 48 is a schematic diagram of a partial planar structure of another anode according to the present disclosure;

[0637] FIG. 49 is a schematic diagram of a partial planar structure of yet another anode according to the present disclosure;

[0638] FIG. 50 is a schematic diagram of a partial planar structure of yet another display panel according to the present disclosure;

[0639] FIG. 51 is a schematic block diagram of a display device according to the present disclosure.

[0640] The reference signs in the drawings represent as follows: 10 first active connection line, 11 first active layer, 12 second active layer, 13 third active layer, 14 fourth active layer, 15 fifth active layer, 16 sixth active layer, 17 seventh active layer, 18 eighth active layer, 19 ninth active layer, 20 second active connection line, 21 first gate, 22 second gate, 24 fourth gate, 25 fifth gate, 26 sixth gate, 27 seventh gate, 31 first connection part, 31 first enable signal line, 31-1 first light-emitting connection block, 32 first initial signal line, 32-1 first protrusion, 32-2 first initial connection section, 32-3 second initial connection section, 33 second enable signal line, 33-1 second light-emitting connection block, 33-3 second connection section, 34 first reference signal line, 34-1 first reference connection block, 35 second reference signal line, 35-1 second reference connection block, 36 first shielding electrode, 36-1 first extension section, 36-2 first shielding section, 36-3 first shielding end, 36-4 second shielding end, 37 second shielding electrode, 38 third shielding electrode, 39 repair line, 41 first connection electrode, 42 second connection electrode, 43 third connection electrode, 44 fourth connection electrode, 45 fifth connection electrode, 46 sixth connection electrode, 47 seventh connection electrode, 48 eighth connection electrode, 49 ninth connection electrode, 51 data signal line, 52 first power supply line, 52-1 first power supply connection block, 52-2 second power supply connection block, 53 first reference signal connection line, 54 second initial signal connection line, 55 anode connection electrode, 61 first gate signal line, 62 second gate signal line, 63 third gate signal line, 64 fourth gate signal line, 65 fifth gate signal line, 66 first power supply connection line, 66-1 first power supply connection block, 71 first pole plate, 72 second pole plate, 72-1 first protruding part, 73 third pole plate, 73-1 second pole plate connection line, 74 fourth pole plate, 74-1 first pole plate connection line, 74-2 second protruding part, 74-3 third protruding part, 82 second initial signal line, 82-1 second initial connection block, 101 substrate layer, 102 driving back plate, 103 light-emitting device layer, 104 packaging layer, 201 first insulating layer, 202 second insulating layer, 203 third insulating layer, 204 fourth insulating layer, 205 fifth insulating layer, 232 anode via section, 301 first anode via, 302 second anode via, 303 third anode via, 304 first anode opening, 310 first anode block, 311 first anode sub-block, 311 first sub-connection part, 312 first connection part, 313 first sub-connection part, 314 second sub-connection part, 315 first sub-block, 316 second sub-block, 317 third sub-block, 318 fourth sub-block, 319 first anode extension part, 320 second anode block, 321 second anode extension part, 322 anode extension section, 323 anode via section, 324 second anode opening, 325 second anode sub-block, 326 second connection part,330 Third anode block, 331 Third anode protrusion, 332 Third anode opening, 333 Third anode sub-block, 334 Third connecting part, 340 Pixel defining layer, 341 Pixel opening, 342 Second pixel opening, 343 Third pixel opening, 350 Light-emitting layer, 360 Cathode, 400 Pixel defining layer, 521 First power connection segment, 522 Second power connection segment, 531 First reference connection segment, 532 Second reference connection segment, 730 First opening, 740 Second opening, C1 First capacitor, C2 Second capacitor, CL1 First conductive layer, CL2 Second conductive layer, CL3 Third conductive layer, CL4 Fourth conductive layer, D2 Second data signal line, D3 Third data signal line, Dr rth data signal line, E1 First enable signal line, E2 Second enable signal line, E3 Third enable signal line, EL light-emitting device, Eo d Enable signal line, GOA scan drive circuit, h07 seventh dimension, h08 eighth dimension, h1 first width, h2 second width, h3 third width, h4 fourth width, h5 fifth width, h6 sixth width, h7 seventh width, h8 eighth width, K1 first groove, K2 second groove, N1 first node, N2 second node, N3 third node, N4 fourth node, N5 fifth node, Pij pixel circuit, P pixel unit, P1 first sub-pixel, P2 second sub-pixel, P3 third sub-pixel, S1 first scan signal line, S2 second scan signal line, S3 third scan signal line, Sm mth scan signal line, T01 first stage, T02 second stage, T03 third stage, T04 fourth stage, T05 fifth stage, T1 first transistor, T2 second transistor, T3 third transistor, T4 fourth transistor, T5 fifth transistor, T6 mth... Six transistors, T7 seventh transistor, T8 eighth transistor, T9 ninth transistor, V1 first via, V10 tenth via, V11 eleventh via, V12 twelfth via, V13 thirteenth via, V14 fourteenth via, V15 fifteenth via, V16 sixteenth via, V17 seventeenth via, V18 eighteenth via, V19 nineteenth via, V2 second via, V20 twentieth via, V21 twenty-first via, V22 twenty-second via, V26 twenty-sixth via, V3 third via, V31 thirty-first via, V32 thirty-second via, V33 thirty-third via, V34 thirty-fourth via, V35 thirty-fifth via, V36 thirty-sixth via, V4 fourth via, V5 fifth via, V6 sixth via, V7 seventh via, V8 eighth via, V9 ninth via, VDD first power signal, X first direction, Y second direction. , Detailed Implementation

[0641] In order to better understand the technical solutions provided by the embodiments of the present specification, the technical solutions of the embodiments of the present specification will be described in detail below through the accompanying drawings and specific embodiments. It should be understood that the specific features in the embodiments of the present specification and the embodiments are detailed descriptions of the technical solutions of the present specification, and are not limitations of the technical solutions of the present specification. In the case of no conflict, the technical features in the embodiments of the present specification and the embodiments can be combined with each other.

[0642] In this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element. The term "two or more" includes two or more than two.

[0643] In recent years, widely used display devices include TFT-LCD and AMOLED, etc. The AMOLED display has the advantages of long service life, high display brightness, large contrast ratio, wide color gamut, etc. The AMOLED display device usually drives the light-emitting device to emit light through the driving circuit to form a light-emitting pixel. The driver device of the driving circuit transmits a driving signal to the anode of the light-emitting device, and the light-emitting device emits light under the driving of the driving signal. However, in the design of the existing AMOLED display panel, the arrangement of various signal lines below the anode can easily cause the film layer at the position of the anode of the pixel of different colors to have poor flatness, and poor flatness of the anode can easily cause display color deviation problems.

[0644] Therefore, the display panel and the display device provided by the embodiments of the present disclosure can improve the flatness of the anode of the pixel of different colors, and further improve the display color deviation problem of the display panel.

[0645] In a first aspect of the present disclosure, a display panel is provided. FIG. 1 is a schematic structural block diagram of a display panel provided by the present disclosure. As shown in FIG. 1, the display panel includes a plurality of pixel circuits Pij arranged in an array, and the display panel further includes a scan driver, a light-emitting driver, a data driver, and a timing controller. As an example, i and j are both natural numbers, i represents the row number of the pixel circuit, and j represents the column number of the pixel circuit. The scan driver is configured to output a scan signal, and the scan driver can transmit the scan signal to the pixel circuit Pij through a scan signal line. The scan signal line includes a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, and an mth scan signal line Sm. The scan signal is used to drive the pixel circuit Pij in the corresponding row. The light-emitting driver is configured to output a plurality of enable control signals, and the light-emitting driver transmits the enable control signals to the corresponding pixel circuit Pij through an enable signal line. The enable signal line includes a first enable signal line E1, a second enable signal line E2, a third enable signal line E3, and an oth enable signal line Eo. The data driver is configured to output a data signal, and the data driver transmits the data signal to the corresponding pixel circuit Pij through a data signal line. The data signal line includes a first data signal line D1, a second data signal line D2, a third data signal line D3, and an rth data signal line Dr. The timing controller is electrically connected to the scan driver and the data driver, respectively, and the timing controller is configured to control the timing of the scan signal and the data signal. It should be noted that m, o, and r are all natural numbers greater than 0. As an example, m and o can be the same as the total number of rows of the pixel circuit Pij, and r is the same as the number of columns of the pixel circuit Pij.

[0646] In some examples, the timing controller can provide the gray value of the pixel corresponding to the current frame display picture or the next frame display picture and the control timing to the data driver, provide the scan start signal and the clock signal and the like corresponding to the current frame display picture or the next frame display picture to the scan driver, and provide the clock signal and the emission stop signal and the like corresponding to the current frame display picture or the next frame display picture to the light-emitting driver. For example, the data driver can sample the gray value using the clock signal, and apply the data voltage corresponding to the gray value to the data signal line in units of pixel rows to provide the data voltage to the corresponding pixel circuit Pij through the data signal line. Here, the data voltage is the data signal. It should be noted that the data signal also needs to include the timing of applying the data voltage. The scan driver can generate the scan signal using the clock signal and the scan start signal and the like received from the timing controller, and provide the scan signal to the corresponding pixel circuit Pij through the scan signal line. For example, the scan driver can sequentially provide the scan signal with the on level pulse to the scan signal lines S1 to Sm. For example, the light-emitting driver can include a circuit of a shift register, and sequentially transmit the emission stop signal provided in the form of an off level pulse to the next stage circuit under the control of the clock signal.

[0647] FIG. 2 is a schematic structural diagram of pixel arrangement of a display panel provided by the present disclosure. As an example, as shown in FIG. 2, the display panel can include a first sub-pixel P1, a second sub-pixel P2 and a third sub-pixel P3, which can respectively emit light of different colors to realize color picture display. For example, the first sub-pixel P1 can emit red light, the second sub-pixel P2 can emit blue light, and the third sub-pixel P3 can emit green light, which are only illustrative and not as a specific limitation of the embodiments of the present disclosure. The display panel can include a plurality of arrayed pixel units P, each of which includes a first sub-pixel P1, a second sub-pixel P2 and a third sub-pixel P3.

[0648] As an example, each sub-pixel can include a pixel circuit Pij and a light emitting device, and the pixel circuit Pij is used to drive the light emitting device to emit light for picture display. The shape of the light emitting area of the light emitting device can be rectangular, rhombic, pentagonal, hexagonal, circular or elliptical. In the case where one pixel unit P includes three sub-pixels, the light emitting devices corresponding to the three sub-pixels can be arranged in a horizontal single row, a vertical single column or a triangular shape. For example, referring to FIG. 2, each pixel unit P includes three sub-pixels arranged in a horizontal single row, and sub-pixels of the same color are arranged in a vertical single column. In the case where one pixel unit P includes four sub-pixels, the light emitting devices corresponding to the four sub-pixels can be arranged in a horizontal single row, a vertical single column or a rectangular shape. The pixel circuit Pij can be electrically connected to a scan driver, a light emitting driver and a data driver, and the scan driver, the light emitting driver and the data driver are all electrically connected to provide signals to the pixel circuit to control the corresponding light emitting device to emit light or not to emit light. In some examples, the pixel circuit Pij can include a plurality of transistors and at least one capacitor. For example, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T in the pixel circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0649] FIG. 3 is a schematic diagram of a partial cross-sectional structure of a display panel provided by the present disclosure. As shown in FIG. 3, the display panel includes a substrate layer 101, a driving backplane 102, a light emitting device layer 103, and an encapsulation layer 104. The substrate layer 101 can be a flexible substrate or a rigid substrate; the flexible substrate can include polyimide, and the rigid substrate can be transparent glass. The driving backplane 102 can be provided with driving devices, which can include thin film transistors, capacitors, and the like; the encapsulation layer 104 can include organic encapsulation materials, inorganic encapsulation materials, and the like. In combination with FIG. 1, a pixel circuit Pij can be provided in the driving backplane 102. As an example, the light emitting device layer 103 can include an anode, an electron injection layer, an electron transport layer, a light emitting material layer, a hole transport layer, a hole injection layer, and a cathode; the encapsulation layer 104 can include a first inorganic layer, an organic layer, and a second inorganic layer, and the encapsulation layer 104 can protect the light emitting device from being corroded by external water and oxygen. In some examples, the display panel can further include other film layers, such as a touch electrode layer, a filter layer, and the like, which are not specifically limited by the embodiments of the present disclosure.

[0650] In some examples, the light emitting device can be any one of an LED (Light Emitting Diode), an OLED (Organic Light Emitting Diode), a QLED (Quantum Dot Light Emitting Diodes), and a micro-LED, which includes a mini-LED or a micro-LED. For example, the light emitting device can be an OLED, which can emit red light, green light, blue light, white light, or the like under the driving of the corresponding pixel circuit. The color of the light emitted by the light emitting device can be determined as needed. In some examples, the organic light emitting device can include an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting device can be electrically connected to the corresponding pixel circuit, the organic light emitting layer is connected to the anode, and the cathode is connected to the organic light emitting layer. The organic light emitting layer can emit light of a corresponding color under the driving of the anode and the cathode. However, the embodiments are not limited thereto. As an example, the organic light emitting layer can include an EML (Emitting Layer) and any one or more of the following layers: a HIL (Hole Injection Layer), a HTL (Hole Transport Layer), an EBL (Electron Block Layer), a HBL (Hole Block Layer), an ETL (Electron Transport Layer), and an EIL (Electron Injection Layer).

[0651] FIG. 4 is a schematic structural diagram of a pixel circuit provided by the present disclosure. As an example, as shown in FIG. 4, the pixel circuit can be a circuit structure of 9T2C, that is, the pixel circuit can include 9 thin film transistors and 2 capacitors. The pixel circuit can be electrically connected with 13 signal lines, and the 13 signal lines are respectively used for transmitting 13 signals. The signal lines electrically connected with the pixel circuit can include a first gate signal line, a second gate signal line, a third gate signal line, a fourth gate signal line, a data signal line, a first power supply line, a first reference signal line, a second reference signal line, a first initial signal line, a second initial signal line, a first enable signal line, a second enable signal line, and a second power supply line. The first gate signal line is used for transmitting a first gate signal GL1, the second gate signal line is used for transmitting a second gate signal GL2, the third gate signal line is used for transmitting a third gate signal GL3, the fourth gate signal line is used for transmitting a fourth gate signal GL4, the data signal line is used for transmitting a data signal Data, the first power supply line is used for transmitting a first power supply signal VDD, the first reference signal line is used for transmitting a first reference signal Vref1, the second reference signal line is used for transmitting a second reference signal Vref2, the first initial signal line is used for transmitting a first initial signal Vinit1, the second initial signal line is used for transmitting a second initial signal Vinit2, the first enable signal line is used for transmitting a first enable signal EM1, the second enable signal line is used for transmitting a second enable signal EM2, and the cathode line is used for transmitting a second power supply signal VSS. The first gate signal line, the second gate signal line, the third gate signal line, and the fourth gate signal line can be electrically connected with a scan driver, and the first gate signal GL1, the second gate signal GL2, the third gate signal GL3, and the fourth gate signal GL4 can correspond to a scan signal, that is, the first gate signal line, the second gate signal line, the third gate signal line, and the fourth gate signal line can be used for transmitting the scan signal. The first enable signal line and the second enable signal line are both electrically connected with a light-emitting driver, and the enable signals transmitted thereby can control the light-emitting of a light-emitting device.

[0652] As an example, a thin film transistor includes a gate, a first electrode, and a second electrode. The first electrode can be one of a source and a drain, and the second electrode can be the other of the source and the drain. The thin film transistor includes two types, which are P-type and N-type, respectively. For the P-type thin film transistor, when the gate is connected to a low level, the first electrode and the second electrode are connected, and the thin film transistor is turned on. Conversely, the thin film transistor is turned off. For the N-type thin film transistor, when the gate is connected to a high level, the first electrode and the second electrode are connected, and the thin film transistor is turned on. Conversely, the thin film transistor is turned off.

[0653] For example, referring to FIG. 4, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, a second capacitor C2, and a light emitting device EL, which can include a light emitting diode. A first electrode of the first transistor T1 is electrically connected to a data signal line, and is configured to receive a data signal Data. A second electrode of the first transistor T1 is electrically connected to a second node N2. A gate of the first transistor T1 is electrically connected to a first gate signal line, and is configured to receive a first gate signal GL1. One end of the second capacitor C2 is electrically connected to a first power supply line, and the other end is electrically connected to the second node N2, and is configured to receive a first power supply signal VDD. One end of the first capacitor C1 is electrically connected to the second node N2, and the other end is electrically connected to a first node N1. The second capacitor C2 is configured to stabilize a voltage of the second node N2. In combination with the voltage stabilization of the second node N2 and the configuration of the first capacitor C1, the voltage of the first node N1 is stabilized. A first electrode of the second transistor T2 is electrically connected to the first node N1. A second electrode of the second transistor T2 is electrically connected to a fourth node N4. A gate of the second transistor T2 is electrically connected to a fifth gate signal line or a second gate signal line, and is configured to receive a second gate signal GL2. The second gate signal line and the fifth gate signal line can be configured to transmit the second gate signal. A first electrode of the third transistor T3 is electrically connected to a third node N3. A second electrode of the third transistor T3 is electrically connected to the fourth node N4. A gate of the third transistor T3 is electrically connected to the first node N1. A first electrode of the fifth transistor T5 is electrically connected to the first power supply line, and is configured to receive the first power supply signal VDD. A second electrode of the fifth transistor T5 is electrically connected to the third node N3. A gate of the fifth transistor T5 is electrically connected to a first enable signal line, and is configured to receive a first enable signal EM1. A gate of the ninth transistor T9 is electrically connected to a fourth gate signal line. A first electrode of the ninth transistor T9 is electrically connected to a second reference signal line, and is configured to receive a second reference signal Vref2. A second electrode of the ninth transistor T9 is electrically connected to the third node N3. A gate of the sixth transistor T6 is electrically connected to a second enable signal line, and is configured to receive a second enable signal EM2.The second electrode of the eighth transistor T8 is electrically connected with the fifth node N5, the first electrode of the eighth transistor T8 is electrically connected with the second initial signal line, the gate of the eighth transistor T8 is electrically connected with the fourth gate signal line, the first electrode of the eighth transistor T8 is used for inputting the second initial signal Vinit2, and the gate of the eighth transistor T8 is used for inputting the fourth gate signal GL4. The anode of the light emitting device EL is electrically connected with the fifth node N5, the cathode of the light emitting device EL is electrically connected with the cathode line, and the cathode of the light emitting device EL is used for inputting the second power signal VSS. The first electrode of the fourth transistor T4 is electrically connected with the first node N1, the second electrode of the fourth transistor T4 is electrically connected with the first initial signal line, the gate of the fourth transistor T4 is electrically connected with the third gate signal line, the second electrode of the fourth transistor T4 is used for inputting the first initial signal Vinit1, and the gate of the fourth transistor T4 is used for inputting the third gate signal GL3. The third gate signal line is a scanning signal line of the n-3 level scanning driving circuit GOA, n is the row number of the pixel circuit, and 4 < n ≤ m. The first electrode of the seventh transistor T7 is electrically connected with the second node N2, the second electrode of the seventh transistor T7 is electrically connected with the first reference signal line, the gate of the seventh transistor T7 is electrically connected with the second gate signal line or the fifth gate signal line, the second electrode of the seventh transistor T7 is used for inputting the first reference signal Vref1, and the gate of the seventh transistor T7 is used for inputting the second gate signal GL2.

[0654] In some examples, as shown in FIG. 4, different from the 7T1C, the ninth transistor T9 is turned on under the control of the fourth gate signal GL4, and the turned-on ninth transistor T9 can transmit the second reference signal Vref1 to the first electrode of the third transistor T3, so that the reset speed of the first electrode of the third transistor T3 can be improved, and the requirement of low frequency and high brush can be met.

[0655] In some examples, the voltage value of the first power signal VDD is greater than the voltage value of the second power signal VSS, and the second power signal VSS can be provided to the cathode of the light emitting device.

[0656] As shown in FIG. 4, the first transistor T1, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 can be a double-gate structure.

[0657] For example, as shown in FIG. 4, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are all P-type transistors, and the gate low level is turned on. It is only illustrative that the transistors shown in FIG. 4 can also be N-type transistors, which are not specifically limited by the embodiments of the present disclosure.

[0658] FIG. 5 is a schematic driving timing diagram of a pixel circuit provided by the present disclosure. By way of example, in combination with FIG. 4 and FIG. 5, the driving process of the pixel circuit includes the following stages:

[0659] In the first stage T01, the first node N1 is reset. The third gate signal GL3 / GL3(n-3) transmitted through the third gate signal line turns on the fourth transistor T4, and the first initial signal Vinit1 provided by the first initial signal line reaches the first node N1 through the fourth transistor T4. The first initial signal Vinit1 received by the first node N1 controls the third transistor T3 to turn on, and the potential of the first node N1 can be pulled low, thereby resetting the first node N1. Since the fourth transistor T4 and the third transistor T3 are both P-type transistors, the gate is low to turn on, therefore, the third gate signal GL3 has a low amplitude jump square wave in the first stage T01, and the first initial signal Vinit1 provided by the first initial signal line provides a low level in the first stage T01, so the potential of the first node N1 is also low. The reset function of the first node N1 is to clear the voltage value written into the first node N1 in the previous frame of display picture, so as to write the voltage value of the current frame of display picture.

[0660] In the second stage T02, the first electrode and the second electrode of the third transistor T3 and the anode of the light emitting device EL are reset. The fourth gate signal GL4 provided by the fourth gate signal line is low to control the eighth transistor T8 to turn on, so that the second initial signal Vinit2 provided by the second initial signal line is transmitted to the fifth node N5, and the second initial signal received by the fifth node N5 is low, which can reset the anode of the light emitting device EL. At the same time that the eighth transistor T8 is turned on, the ninth transistor T9 is turned on, the second reference signal Vref2 provided by the second reference signal line is transmitted to the third node N3 through the ninth transistor T9, and the third transistor T3 is in an open state in the first stage T01, so the second reference signal Vref2 can reset the first electrode of the third transistor T3, and the second reference signal Vref2 is transmitted to the second electrode of the third transistor T3 through the third transistor T3, i.e. the second reference signal Vref2 is transmitted to the fourth node N4 through the third transistor T3, i.e. the first electrode and the second electrode of the third transistor T3 are reset. The reset of the third transistor T3 and the anode of the light emitting device is to clear the first power signal written into the third transistor T3 and the anode of the light emitting device in the previous frame of display picture, so as to write the voltage value of the current frame of display picture.

[0661] In the third stage T03, the threshold voltage is written and the second node N2 is reset. The low level first enable signal EM1 provided by the first enable signal line controls the fifth transistor T5 to be turned on, the third transistor T3 continues the open state in the second stage T02, and the low level second gate signal GL2 controls the second transistor T2 to be turned on. The first power signal VDD provided by the first power supply line is transmitted to the third node N3 through the fifth transistor T5, the first power signal is transmitted to the fourth node through the third transistor T3, and the first power signal VDD is transmitted to the first node N1 through the second transistor T2, that is, the first power signal VDD is written to the gate of the third transistor T3 until the cut-off voltage VDD+vth of the third transistor T3 is reached, wherein VDD is the voltage value of the first power signal, and vth is the threshold voltage of the third transistor T3. The second gate signal GL2 controls the seventh transistor T7 to be turned on, and the first reference signal Vref1 provided by the first reference signal line is transmitted to the second node N2, and the voltage of the second node N2 becomes the first reference signal Vref1.

[0662] In the fourth stage T04, the data voltage is written. The first gate signal GL1 provided by the first gate signal line controls the first transistor T1 to be turned on, and the data signal Data provided by the data signal line is transmitted to the second node N2 through the first transistor T1, and the data signal Data is written to the second node N2, and the potential of the second node N2 becomes the data signal Data, and the potential change of the second node N2 is Data-Vref1. Based on the jump action of the first capacitor C1 and the second capacitor C2, the potential change of the first node N1 is Data-Vref1, and thus the potential of the first node N1 is: VDD+vth+Data-Vref1. It should be noted that the potential of the first node N1 reaches the cut-off voltage VDD+vth of the third transistor T3 in the third stage T03, and the data signal Data is written to the first node N1 in the fourth stage T04, so that the first node N1 is written with signals through two different time periods in the third stage T03 and the fourth stage T04, which is more conducive to realizing high-frequency refresh.

[0663] In the fifth stage T05, a light emitting stage. Under the control of the low level of the first enable signal EM1 provided by the first enable signal line, the fifth transistor T5 is turned on, and the first power signal VDD provided by the first power supply line is transmitted to the third node N3 through the fifth transistor T5; in the fourth stage T04, the potential of the first node N1 is VDD+vth+Data-Vref1, which can control the third transistor T3 to be turned on, and in the fifth stage T05, the voltage of the first node N1 does not jump, so the third transistor T3 is still turned on, and the first power signal VDD of the third node N3 is transmitted to the fourth node N4 through the third transistor T3; under the control of the low level of the second enable signal EM2 provided by the second enable signal line, the sixth transistor T6 is turned on, and the first power signal VDD of the fourth node N4 is transmitted to the fifth node N5; under the driving of the anode of the light emitting device EL by the first power signal VDD and the driving of the cathode of the light emitting device EL by the second power signal VSS provided by the second power supply line, the light emitting device EL emits light. It should be noted that in the light emitting stage, the potential of the first node N1 is VDD+vth+Data-Vref1, which is brought into the current formula: gs =VDD+vth+Data-Vref1-VDD is brought into the current formula, and the following is obtained: It can be seen that the light emitting current of the light emitting device EL is only related to the first reference signal Vref1 and the data signal Data. It should be noted that I in the current formula is the current flowing through the light emitting device EL, μ p is the dielectric constant, C ox is the gate oxide capacitance, that is, the capacitance of the gate and the oxide layer, and the oxide layer of the gate oxide capacitance can include silicon oxide, is the channel width-length ratio of the transistor, V gs is the gate-source voltage of the transistor, and vth is the threshold voltage.

[0664] The pixel circuit of the present example can improve the hysteresis of the driving transistor and is beneficial to improve the display effect.

[0665] FIG. 6 is a schematic view of a partial plane structure of a display panel provided by the present disclosure. As shown in FIG. 6, the structure of three pixel circuits of the display panel, i.e., a first pixel circuit, a second pixel circuit and a third pixel circuit, is schematically shown in FIG. 6.

[0666] In some examples, the display panel can include a driving backplane disposed on a substrate layer and a light emitting device layer disposed on a side of the driving backplane away from the substrate layer. The driving backplane can include at least a plurality of pixel circuits, and the light emitting device layer can include at least a plurality of light emitting devices. The light emitting device can include at least an anode, a light emitting layer and a cathode, and the anode of the light emitting device can be connected to the corresponding pixel circuit. ​

[0667] In the present disclosure, the pixel circuit refers to a region divided according to the pixel circuit. In some examples, the position of the orthographic projection of the light emitting device on the substrate layer can correspond to the position of the orthographic projection of the pixel circuit on the substrate layer, or the position of the orthographic projection of the light emitting device on the substrate layer can not correspond to the position of the orthographic projection of the pixel circuit on the substrate layer.

[0668] In some examples, the plurality of pixel circuits arranged in sequence along the first direction X can be referred to as row-arranged pixel circuits, and the plurality of pixel circuits arranged in sequence along the second direction Y can be referred to as column-arranged pixel circuits, to form an array-arranged pixel circuit. The first direction X and the second direction Y can intersect, for example, the first direction X can be perpendicular to the second direction Y.

[0669] FIG. 7 is a schematic diagram of a partial cross-sectional structure of FIG. 6 along the Q1-Q2 direction. In some examples, as shown in FIGS. 6 and 7, in a direction perpendicular to the display panel, the driving back plate can include an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence on the substrate layer 101. The first insulating layer 201 can be arranged between the active layer and the first conductive layer, the second insulating layer 202 can be arranged between the first conductive layer and the second conductive layer, the third insulating layer 203 can be arranged between the second conductive layer and the third conductive layer, and the fourth insulating layer 204 can be arranged between the third conductive layer and the fourth conductive layer. In some examples, the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 can be inorganic insulating layers, and the fourth insulating layer 204 can be an organic insulating layer. However, the present embodiment is not limited thereto. In other examples, a buffer layer can be arranged between the substrate layer and the active layer. In other examples, a passivation layer can be further arranged between the third conductive layer and the fourth conductive layer on the side of the fourth insulating layer close to the substrate layer.

[0670] The preparation process of the display panel is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal materials, inorganic materials or transparent conductive materials, and includes coating organic materials, mask exposure and development and the like for organic materials. The deposition can adopt any one or more of sputtering, evaporation and chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate layer made by deposition, coating or other processes. If the "thin film" does not need to be patterned during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs to be patterned during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0671] The "A and B are arranged in the same layer" in the present disclosure refers to that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer refers to the size of the film layer in the direction perpendicular to the display panel. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" refers to that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0672] In some examples, taking three pixel circuits in the nth row of pixel circuits as an example, i.e., taking the first pixel circuit, the second pixel circuit and the third pixel circuit in the nth row of pixel circuits as an example, the preparation process of the display panel of the present embodiment can include the following operations.

[0673] First flow: forming an active layer. The material of the active layer can be a silicon-based semiconductor material, for example, amorphous silicon and polycrystalline silicon; the material of the active layer can also be an oxide semiconductor material, for example, an oxide of indium gallium zinc, etc., such as indium zinc oxide, indium gallium zinc oxide, etc.

[0674] FIG. 8 is a schematic diagram of a partial planar structure of an active layer provided by the present disclosure. In some examples, referring to FIG. 8, an active material thin film is deposited on one side of the substrate layer, and the active material thin film is patterned by a patterning process.

[0675] In some examples, each pixel circuit of the display panel is configured to drive a light emitting device of a sub-pixel, for example, the first pixel circuit can drive a blue light emitting device, the second pixel circuit can be configured to drive a red light emitting device, and the third pixel circuit can drive a green light emitting device. In the case where the pixel unit includes three sub-pixels of red, green and blue, the first pixel circuit, the second pixel circuit and the third pixel circuit can form the pixel circuit of one pixel unit.

[0676] For example, in combination with FIGS. 4 and 8, the active layer of each pixel circuit can include at least: a first active layer 11 of the first transistor T1, a second active layer 12 of the second transistor T2, a third active layer 13 of the third transistor T3, a fourth active layer 14 of the fourth transistor T4, a fifth active layer 15 of the fifth transistor T5, a sixth active layer 16 of the sixth transistor T6, a seventh active layer 17 of the seventh transistor T7, an eighth active layer 18 of the eighth transistor T8, and a ninth active layer 19 of the ninth transistor T9. The general positions of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are each shown in a dashed oval. The respective positions of the first active layer 11, the second active layer 12, the third active layer 13, the fourth active layer 14, the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, the eighth active layer 18, and the ninth active layer 19 are also only generally shown and are not a specific limitation of the embodiments of the present disclosure. Referring to FIG. 8, the first active layer 11 and the seventh active layer 17 can be an integrated structure connected to each other, and the eighth active layer 18, the sixth active layer 16, the second active layer 12, the fourth active layer 14, the third active layer 13, the fifth active layer 15, and the ninth active layer 19 can be an integrated structure connected to each other. The first active layer 11, the second active layer 12, the third active layer 13, the fourth active layer 14, the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, the eighth active layer 18, and the ninth active layer 19 can all be disposed in the same layer and disposed in the active layer.

[0677] In some examples, referring to FIG. 8, the (n-1)th row of pixel circuits is on the side of the nth row of pixel circuits close to the first transistor T1, and the (n+1)th row of pixel circuits is on the side of the nth row of pixel circuits close to the eighth transistor T8, i.e., in way 8, the (n-1)th row of pixel circuits is on the upper side of the nth row of pixel circuits, and the (n+1)th row of pixel circuits is on the lower side of the nth row of pixel circuits. In the nth row of pixel circuits, the first active layer 11 and the seventh active layer 17 can be located on the side of the third active layer 13 close to the (n-1)th row of pixel circuits; the second active layer 12, the fourth active layer 14, the fifth active layer 15, the sixth active layer 16, the eighth active layer 18, and the ninth active layer can all be located on the side of the third active layer 13 close to the (n+1)th row of pixel circuits.

[0678] In some examples, referring to FIG. 8, the first active layer 11 can be located between two seventh active layers 17 of two adjacent pixel circuits in the first direction X, i.e., in the same pixel circuit, the first active layer 11 is located on one side of the seventh active layer 17 in the first direction X. In the same pixel circuit, the second active layer 12 and the fourth active layer 14 can be located on one side of the third active layer 13 in the second direction Y, the sixth active layer 16 can be located on one side of the second active layer 12 away from the third active layer 13, the eighth active layer 18 can be located on one side of the sixth active layer 16 away from the second active layer 12, the fifth active layer 15 can be located on one side of the fourth active layer 14 away from the third active layer 13, and the ninth active layer 19 can be located on one side of the fifth active layer 15 away from the third active layer 13.

[0679] In some examples, referring to FIG. 8, in the same pixel circuit, the seventh active layer 17, the second active layer 12, the sixth active layer 16 and the eighth active layer 18 can be located on the opposite side of the pixel circuit in the first direction X, and the first active layer 11, the fourth active layer 14, the fifth active layer 15 and the ninth active layer 19 can be located on one side of the pixel circuit in the first direction X.

[0680] In some examples, referring to FIG. 8, the fourth active layer 14 and the second active layer 12 can have a shape of approximately "L" letter, the third active layer 13 can have a shape of approximately "C" letter, "n" letter or "j" letter, the first active layer 11 and the seventh active layer 17 can have a shape of approximately "n" letter, and the fifth active layer 15, the sixth active layer 16, the eighth active layer 18 and the ninth active layer 19 can have a shape of approximately "l" letter, i.e., straight line type.

[0681] In some examples, the active layer of the transistor can include a first region, a second region, and a channel region between the first region and the second region, the channel region can be a charge sensing region formed by the overlapping region of the active layer and the gate, the first region can be used to form a first electrode by connecting with an electrode formed by another conductive layer, the second region can be used to form a second electrode by connecting with an electrode formed by another conductive layer, the first electrode can be one of the source and the drain of the transistor, and the second electrode can be the other of the source and the drain. In some examples, referring to FIG. 8, the second region 112 of the first active layer 11 and the second region 172 of the seventh active layer 17 can be connected to each other, i.e., the second region 112 of the first active layer 11 can serve as the second region 172 of the seventh active layer 17, constituting the second node N2 of the pixel circuit. The first region 111 of the first active layer 11 can be located at one side of the channel region of the first active layer 11 close to the third active layer 13, and the first region 171 of the seventh active layer 17 can be located at one side of the channel region of the seventh active layer 17 close to the third active layer 13. The first region 111 of the first active layer 11 and the first region 171 of the seventh active layer 17 can be independently provided. The first region 121 of the second active layer 12 and the second region 142 of the fourth active layer 14 can be connected to each other, i.e., the first region 121 of the second active layer 12 can serve as the second region 142 of the fourth active layer 14, constituting the first node N1 of the pixel circuit. The first region 131 of the third active layer 13, the second region 152 of the fifth active layer 15, and the second region 192 of the ninth active layer 19 can be connected to each other, and the first region 131 of the third active layer 13 can simultaneously serve as the second region 152 of the fifth active layer 15 and the second region 192 of the ninth active layer 19, constituting the third node N3 of the pixel circuit. The second region 132 of the third active layer 13, the second region 122 of the second active layer 12, and the first region 161 of the sixth active layer 16 can be connected to each other, and the second region 132 of the third active layer 13 can simultaneously serve as the second region 122 of the second active layer 12 and the first region 161 of the sixth active layer 16, constituting the fourth node N4 of the pixel circuit. The second region 162 of the sixth active layer 16 and the second region 182 of the eighth active layer 18 can be connected to each other, and the second region 162 of the sixth active layer 16 can serve as the second region 182 of the eighth active layer 18, constituting the fifth node N5 of the pixel circuit. The first region 141 of the fourth active layer 14, the first region 181 of the eighth active layer 18, and the first region 191 of the ninth active layer 19 can be independently provided.

[0682] In some examples, referring to FIG. 8, in at least one unit row, the active layers in the pixel circuits adjacent in the first direction X can be connected to each other. For example, in the nth row of pixel circuits, the active layer of the first pixel circuit can be connected to the active layer of the second pixel circuit, and the active layer of the second pixel circuit can be connected to the active layer of the third pixel circuit. In the nth row of pixel circuits, the active layers of the pixel circuits adjacent in the first direction X can be connected by the first active connection line 10 and the second active connection line 20. For example, the first area 171 of the seventh active layer 17 of the seventh transistor T7 of the pixel circuits adjacent in the first direction X can be connected to each other by the first active connection line 10, and the first area 181 of the eighth active layer 18 can be connected to each other by the second active connection line 20. The first active connection line 10 and the second active connection line 20 can extend at least along the first direction X. The first active connection line 10 can be located on the side of the first active layer 11 close to the third active layer 13, and the second active connection line 20 can be located on the side of the eighth active layer 18 away from the sixth active layer 16.

[0683] In some examples, referring to FIG. 8, the shape of the first active connection line 10 can be a broken line shape with a main part extending along the first direction X, and the whole is a horizontal wire. The first active connection line 10 and the seventh active layer 17 of the plurality of pixel circuits can be an integrated structure connected to each other. Since the first area 171 of the seventh active layer 17 is connected to the first reference signal line formed later, the first active connection line 10 can be multiplexed as the first reference signal line extending along the first direction X, not only can ensure that the first areas 171 of the plurality of seventh active layers 17 in each row of pixel circuits have the same potential, but also the parallel connection of the first active connection line 10 and the first reference signal line arranged in a horizontal wire can reduce the resistance and in turn reduce the voltage drop of the first reference signal, which is beneficial to improve the uniformity of the substrate, avoid display defects of the display panel, and ensure the display effect of the display panel.

[0684] In some examples, referring to FIG. 8, the shape of the second active connection line 20 can be a straight line shape with a main part extending along the first direction X, and the whole is a horizontal wire. The second active connection line 20 and the eighth active layer 18 of the plurality of pixel circuits can be an integrated structure connected to each other. Since the first area 181 of the eighth active layer 18 is connected to the second initial signal line formed later, the second active connection line 20 can be multiplexed as the second initial signal line extending along the first direction X, not only can ensure that the first areas 181 of the plurality of eighth active layers 18 in one unit row have the same potential, but also the parallel connection of the second active connection line 20 arranged in a horizontal wire and the second initial signal line can reduce the wire resistance, which in turn can reduce the voltage drop of the second initial signal, which is beneficial to improve the uniformity of the substrate, avoid display defects of the display panel, and ensure the display effect of the display panel.

[0685] In some examples, referring to FIG. 8, the edges of the two first active connection lines 10 adjacent to each other in the first direction X and the edges of the first region 171 of the seventh active layer 17 can form a first groove K1. The first groove K1 can be configured to accommodate a first protrusion of a second plate of a second capacitor, and is beneficial to increase the setting space of the second capacitor.

[0686] In some examples, referring to FIG. 8, in at least one pixel circuit column, the active layers in the pixel circuits adjacent to each other in the second direction Y can be spaced apart from each other. For example, the active layer of the first pixel circuit of the pixel circuit in the n-1th row and the active layer of the first pixel circuit of the pixel circuit in the nth row can be not connected, and the active layer of the first pixel circuit of the pixel circuit in the n+1th row and the active layer of the first pixel circuit of the pixel circuit in the n+1th row can be not connected.

[0687] Second process: forming a first conductive layer. In some examples, on the side of the active layer away from the substrate layer, a first insulating film and a first conductive film are sequentially deposited, the first conductive film is subjected to a patterning process, a first insulating layer covering the active layer is formed, and a first conductive layer disposed on the first insulating layer is formed.

[0688] FIG. 9 is a partial planar structural schematic diagram of the display panel after the first conductive layer is formed in FIG. 8; and FIG. 10 is a partial planar structural schematic diagram of a first conductive layer provided by the present disclosure. In some examples, the first conductive layer can include a metal material, and the first conductive layer can be used as a first gate metal layer. The patterned first conductive layer can be used to form a gate of a transistor in a pixel circuit or a part of a signal line, etc.

[0689] It should be noted that FIGS. 8, 9 and 10 are structural diagrams schematized from the front of the display panel, and the structural diagrams schematized from the back can be a single-layer structural diagram or a laminated structural diagram from the side of the substrate layer of the display panel, and the structural diagrams schematized from the front can be a single-layer structural diagram or a laminated structural diagram from the side of the first conductive layer of the display panel away from the active layer. Therefore, in the structural diagram schematized from the front of the display panel, the first conductive layer blocks part of the active layer.

[0690] In some examples, the first conductive layer of each pixel circuit in the display panel can at least include: a first gate 21 of a first transistor T1, a second gate 22 of a second transistor T2, a fourth gate 24 of a fourth transistor T4, a fifth gate 25 of a fifth transistor T5, a sixth gate 26 of a sixth transistor T6, a fourth gate signal line 64, a first plate 71 of a first capacitor C1, and a second plate 72 of a second capacitor C2.

[0691] In some examples, the first gate 21 can have a shape of an "L" character, the first gate 21 can be located on the side of the second plate 72 of the second capacitor C2 opposite to the second direction Y, and the region where the first gate 21 overlaps with the first active layer 11 can form a channel region of the first transistor T1. The first gate 21 for forming the channel region can have a shape of a "one" character. The first gate 21 and the first active layer 11 have two independent overlapping regions, and the first transistor T1 can be a transistor with a double-gate structure. The seventh gate 27 can have a shape of a "one" character extending along the first direction X, the seventh gate 27 can be located on the side of the second plate 72 of the second capacitor C2 opposite to the second direction Y, and the region where the seventh gate 27 overlaps with the seventh active layer 17 can form a channel region of the seventh transistor T7. The seventh gate 27 and the seventh active layer 17 have two independent overlapping regions, and the seventh transistor T7 can be a transistor with a double-gate structure. The seventh gate 27 is located on the side of the first gate 21 opposite to the first direction X.

[0692] In some examples, referring to FIG. 9, the overlapping region between the first plate 71 of the first capacitor C1 and the third active layer 13 can form a channel region of the third transistor T3, and the first plate 71 of the first capacitor C1 can serve as a gate of the third transistor T3. The second gate 22 can have a shape of a "T" character, the second gate 22 can be located on the side of the first plate 71 of the first capacitor C1 along the second direction Y, and the region where the second gate 22 overlaps with the second active layer 12 can serve as a gate of the second transistor T2 with a double-gate structure. The fourth gate 24 can have a shape of an "L" character, the fourth gate 24 can be located on the side of the first plate 71 of the first capacitor C1 along the second direction Y, and the region where the fourth gate 24 overlaps with the fourth active layer 14 can serve as a gate of the fourth transistor T4 with a double-gate structure. The fourth gate 24 can be located on the side of the second gate 22 along the first direction X. The fifth gate 25 can have a shape of an "L" character, the fifth gate 25 can be located on the side of the fourth gate 24 away from the first gate 21, the region where the fifth gate 25 overlaps with the fifth active layer 15 can form a channel region of the fifth transistor T5, and the region where the fifth gate 25 overlaps with the fifth active layer 15 can serve as a gate of the fifth transistor T5. The sixth gate 26 can have a shape of a strip extending along the first direction X, the sixth gate 26 can be located on the side of the second gate 22 along the second direction Y, and the region where the sixth gate 26 overlaps with the sixth active layer can serve as a gate of the sixth transistor T6. The sixth gate 26 can be located on the side of the second gate 22 away from the seventh gate 27, and the sixth gate 26 can be located on the side of the fifth gate 25 along the first direction X.

[0693] In some examples, referring to FIG. 9, the fourth gate signal line 64 can have a straight shape with a main body extending along the first direction X, and the fourth gate signal line 64 can be located on one side of the fifth gate 25 and the sixth gate 26 in the second direction Y. An area where the fourth gate signal line 64 overlaps with the eighth active layer 18 can serve as a gate of the eighth transistor T8, and an area where the fourth gate signal line 64 overlaps with the ninth active layer 19 can serve as a gate of the ninth transistor T9. The fourth gate signal line 64 can be used to transmit a fourth gate signal gl4.

[0694] In some examples, the fourth gate signal GL4 transmitted by the fourth gate signal line 64 can control the turn-on and turn-off of the eighth transistor T8 and the ninth transistor T9, which are distinguished from other transistors and are independently controlled by the separate fourth gate signal GL4, so as to adapt to high-brush reset at low frequency and avoid flickering. That is, in the case of reset of the third transistor T3, T8 and T9 are synchronously turned on, so as to avoid flickering of a display image.

[0695] For example, referring to FIG. 10, the first conductive layer can only have one horizontal wire, that is, the fourth gate signal line 64, and the first conductive layer at other positions is in the shape of a gate. The fewer the horizontal wires of the first conductive layer, the more compact the layout of the pixel circuit can be, and the flexibility of transistor control can be improved.

[0696] In some examples, referring to FIG. 4 and FIG. 9, the first plate 71 of the first capacitor C1 can have a rectangular shape, and the corners of the rectangular shape can be chamfered. The orthographic projection of the first plate 71 of the first capacitor C1 on the substrate layer can at least partially overlap with the orthographic projection of the third active layer 13 of the third transistor T3 on the substrate layer. The first plate 71 of the first capacitor C1 can simultaneously serve as the lower plate of the first capacitor C1 and the gate of the third transistor T3. The second plate 72 of the second capacitor C2 can have a rectangular shape, and the corners of the rectangular shape can be chamfered. The second plate 72 of the second capacitor C2 can be located on the side of the first plate 71 of the first capacitor C1 in the opposite direction of the second direction Y, and the second plate 72 of the second capacitor C2 can be located between the first gate 21 and the first plate 71 of the first capacitor C1. The orthographic projection of the second plate 72 of the second capacitor C2 on the substrate layer can not overlap with the orthographic projection of the active layer on the substrate layer. The second plate 72 of the second capacitor C2 can serve as the lower plate of the second capacitor C2. The side of the second plate 72 of the second capacitor C2 close to the seventh gate 27 is provided with a first protruding portion 72-1, which can have a substantially rectangular shape. One end of the first protruding portion 72-1 is connected with the second plate 72, and the other end can extend toward the seventh gate 27 and extend into the first recess K1. The second plate 72 and the first protruding portion 72-1 can be an integrated structure connected with each other.

[0697] In some examples, in combination with FIG. 4 and FIG. 9, the first plate 71 of the first capacitor C1 at the edge of the first direction X can be substantially aligned with the second plate 72 of the second capacitor C2 at the edge of the first direction X in the second direction Y, and the first plate 71 of the first capacitor C1 at the edge of the reverse side of the first direction X can be substantially aligned with the second plate 72 of the second capacitor C2 at the edge of the reverse side of the first direction X in the second direction Y. The first protrusion 72-1 at the edge of the first direction X can be flush with the second plate 72 of the second capacitor C2 at the edge of the first direction X in the second direction Y. The shape of the integrated structure formed by the second plate 72 and the first protrusion 72-1 can be substantially "L" shaped.

[0698] In some examples, the area of the first plate 71 of the first capacitor C1 and the second plate 72 of the second capacitor C2 in the orthographic projection on the substrate layer can be the same, or can be different. For example, the area of the second plate 72 of the second capacitor C2 in the orthographic projection on the substrate layer can be smaller than the area of the first plate 71 of the first capacitor C1 in the orthographic projection on the substrate layer.

[0699] In some examples, after forming the first conductive layer pattern, the active layer can be conductorized using the first conductive layer as a shield. The active layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the ninth transistor T9. The active layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the first active layer 11 to the ninth active layer 19, the first active connection line 10 and the second active connection line 20 can all be conductorized.

[0700] FIG. 11 is a schematic structural diagram of another pixel circuit provided by the present disclosure. As shown in FIG. 11, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, a second capacitor C2, and a light emitting device EL. The light emitting device EL may, for example, include a light emitting diode. Two first transistors T1 are connected in series. A first electrode of one first transistor T1 is electrically connected to a data signal Data, and a second electrode is electrically connected to a first electrode of the other first transistor T1. A second electrode of the other first transistor T1 is electrically connected to a second node N2. The gates of the two first transistors T1 are electrically connected to a first gate signal line, i.e., both are connected to the first gate signal GL1. A coupling capacitor exists between the two first transistors T1. One end of the coupling capacitor is between the two first transistors T1, and the other end is located on a second reference signal line, i.e., the other end can be connected to the second reference signal Vref2. The coupling capacitor can function as a voltage stabilizer. One end of the second capacitor C2 is electrically connected to a first power supply line and can be connected to a first power supply signal VDD. The other end is electrically connected to the second node N2. One end of the first capacitor C1 is electrically connected to the second node N2, and the other end is electrically connected to a first node N1. The second capacitor C2 can stabilize the voltage of the second node N2. In combination with the voltage stabilization of the second node N2 and the setting of the first capacitor C1, the voltage of the first node N1 can be stabilized. Two second transistors T2 are connected in series. A first electrode of one second transistor T2 is electrically connected to the first node N1, and a second electrode is electrically connected to a first electrode of the other second transistor T2. A second electrode of the other second transistor T2 is electrically connected to a fourth node N4. The gates of the two second transistors T2 are electrically connected to a fifth gate signal line. A coupling capacitor exists between the two second transistors T2. One end of the coupling capacitor is between the two second transistors T2, and the other end is located on the first power supply line, i.e., the other end can be connected to the first power supply signal. A first electrode of the third transistor T3 is electrically connected to a third node N3. A second electrode of the third transistor T3 is electrically connected to the fourth node N4. The gate of the third transistor T3 is electrically connected to the first node N1. A first electrode of the fifth transistor T5 is electrically connected to the first power supply line. A second electrode of the fifth transistor T5 is electrically connected to the third node N3. The gate of the fifth transistor T5 is electrically connected to a first enable signal line. The gate of the ninth transistor T9 is electrically connected to a fourth gate signal line. A first electrode of the ninth transistor T9 is electrically connected to the second reference signal line. A first electrode of the sixth transistor T6 is electrically connected to the fourth node N4. A second electrode of the sixth transistor T6 is electrically connected to a fifth node N5. The gate of the sixth transistor T6 is electrically connected to a second enable signal line.The second electrode of the eighth transistor T8 is electrically connected with the fifth node N5, the first electrode of the eighth transistor T8 is electrically connected with the second initial signal line, and the gate of the eighth transistor T8 is electrically connected with the fourth gate signal line. The anode of the light emitting device EL is electrically connected with the fifth node N5, and the cathode is electrically connected with the cathode line. Two fourth transistors T4 are connected in series, the first electrode of one fourth transistor T4 is electrically connected with the first node N1, and the second electrode is electrically connected with the first electrode of the other fourth transistor T4; the second electrode of the other fourth transistor T4 is electrically connected with the first initial signal line, the gate of the fourth transistor T4 is electrically connected with the third gate signal line, and the third gate signal line is the gate signal line of the n-3 level scanning driving circuit GOA, where n is the row number of the pixel circuit, and 4 < n ≤ m. There is a coupling capacitor between the two fourth transistors T4, one end of the coupling capacitor is between the two fourth transistors T4, and the other end is on the first power supply line. Two seventh transistors T7 are connected in series, the first electrode of one seventh transistor T7 is electrically connected with the second node N2, and the second electrode is electrically connected with the first electrode of the other seventh transistor T7; the second electrode of the other seventh transistor T7 is electrically connected with the first reference signal line, and the gate of the seventh transistor T7 is electrically connected with the second gate signal line. There is a coupling capacitor between the two seventh transistors T7, one end of the coupling capacitor is between the two seventh transistors T7, and the other end is on the second reference signal line.

[0701] For example, referring to FIG. 11, the two first transistors T1 connected in series can be regarded as a double-gate structure transistor; the two second transistors T2 connected in series can be regarded as a double-gate structure transistor; the two fourth transistors T4 connected in series can be regarded as a double-gate structure transistor; and the two seventh transistors T7 connected in series can be regarded as a double-gate structure transistor. The double-gate structure first transistor T1, the double-gate structure second transistor T2, the double-gate structure fourth transistor T4, and the double-gate structure seventh transistor T7 can control the leakage of the first node N1 and the second node N2, thereby reducing the leakage of the first node N1 and the second node N2.

[0702] In some examples, in combination with FIGS. 9 and 11, the first gate 21 and the first active layer 11 have two overlapping regions, the first gate 21 and the first active layer 11 can form a gate, and the first transistor T1 can be a double-gate structure transistor. The seventh gate 27 and the seventh active layer 17 have two overlapping regions, and the seventh transistor T7 can be a double-gate structure transistor. The second gate 22 and the second active layer 12 have two overlapping regions, and the second transistor T2 can be a double-gate structure transistor. The fourth gate 24 and the fourth active layer 14 have two overlapping regions, and the fourth transistor T4 can be a double-gate structure transistor. The third transistor T3, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 can be single-gate structure transistors.

[0703] The third process: forming a second conductor layer. In some examples, on one side of the patterned substrate layer of the first conductive layer, a second insulating film and a second conductive film are sequentially deposited, the second conductive film is patterned by a patterning process, and a second insulating layer covering the first conductive layer and a second conductive layer disposed on one side of the second insulating layer of the patterned substrate layer are sequentially formed.

[0704] FIG. 12 is a partial planar structure schematic diagram of the display panel after the second conductive layer is formed in FIG. 9; and FIG. 13 is a partial planar structure schematic diagram of a second conductive layer provided by the present disclosure.

[0705] In some examples, the second conductive layer can include a metal material, and the second conductive layer can serve as a second gate metal layer.

[0706] In some examples, the second conductive layer of each pixel circuit in the display panel can at least include: a first enable signal line 31, a first initial signal line 32, a second enable signal line 33, a repair line 39, a second reference signal line 35, a first shielding electrode 36, a second shielding electrode 37, a third shielding electrode 38, a third plate 73 of a first capacitor, and a fourth plate 74 of a second capacitor.

[0707] In some examples, the first enable signal line 31, the first initial signal line 32, the second enable signal line 33, the repair line 39, and the second reference signal line 35 can have a linear shape with a main body portion extending along the first direction X. The first enable signal line 31, the first initial signal line 32, the second enable signal line 33, and the repair line 39 can be located between the first gate 21 and the fourth gate signal line 64, and the second reference signal line 35 can be located on the side of the fourth gate 24 in the opposite direction of the second direction Y.

[0708] In some examples, the repair line 39 can repair the anode, and the repair signal provided by the repair line 39 can repair the dark spot to a bright spot, or the repair line 39 can provide a repair signal to control the dark spot to be repaired to a constant bright state. The dark spot is more easily recognized by the human eye than the bright spot, so repairing the dark spot to the bright spot can play a role in picture repair. The repair line 39 can be used as a redundant anode, and the embodiments of the present disclosure are not limited in this regard.

[0709] In some examples, the first enable signal line 31 can be located on one side of the first gate 21 of the pixel circuit in the second direction Y, the second enable signal line 33 can be located on one side of the first enable signal line 31 in the second direction Y, and the repair line 39 can be located on one side of the second enable signal line 33 in the second direction Y, that is, the second enable signal line 33 can be located between the first enable signal line 31 and the repair line 39, and the first initial signal line 32 can be located between the second enable signal line 33 and the first enable signal line 31.

[0710] In some examples, the first enable signal line 31 can be provided with a first light-emitting connecting block 31-1 on one side close to the second enable signal line 33, the first light-emitting connecting block 31-1 can be provided in each pixel circuit, a first end of the first light-emitting connecting block 31-1 is connected with the first enable signal line 31, and a second end of the first light-emitting connecting block 31-1 extends to the direction of the side where the second enable signal line 33 is located, and the first light-emitting connecting block 31-1 can be configured to be connected with the fifth gate 25 through the seventh connecting electrode formed subsequently. In some examples, the first enable signal line 31 and the plurality of first light-emitting connecting blocks 31-1 can be an integrated structure connected with each other.

[0711] In some examples, the first initial signal line 32 can be provided with a first protrusion 32-1 on one side close to the first enable signal line 31, one end of the first protrusion 32-1 is connected with the first initial signal line 32, and the other end of the first protrusion 32-1 extends toward the first enable signal line 31; the first initial signal line 32 includes a first initial connecting segment 32-2 and a second initial connecting segment 32-3, the first initial connecting segment 32-2 and the second initial connecting segment 32-3 are connected with each other in the first direction X; the first initial connecting segment 32-2 is connected with the first protrusion 32-1, and the first initial connecting segment 32-2 is located between the sixth gate 26 of the pixel circuit and the first enable signal line 31; the second initial connecting segment 32-3 is located between the fifth gate 25 of the pixel circuit and the second enable signal line 33. The main body part of the first initial signal line 32 formed by the connection of the first initial connecting segment 32-2 and the second initial connecting segment 32-3 can be a broken line or a curved line, that is, a non-straight line. In some examples, the first protrusion 32-1, the first initial connecting segment 32-2, and the second connecting segment 33-3 can be an integrated structure connected with each other.

[0712] In some examples, the second enabling signal line 33 can be provided with a second light emitting connecting block 33-1 away from one side of the first enabling signal line 31, the second light emitting connecting block 33-1 can be provided in each pixel circuit, a first end of the second light emitting connecting block 33-1 is connected with the second enabling signal line 33, a second end of the second light emitting connecting block 33-1 extends towards the direction of the side where the first enabling signal line 31 is located, and the second light emitting connecting block 33-1 can be configured to be connected with the sixth gate 26 through the eighth connecting electrode formed subsequently. In some examples, the second enabling signal line 33 and the plurality of second light emitting connecting blocks 33-1 can be an integrated structure connected with each other.

[0713] In some examples, the second reference signal line 35 of the nth row of pixel circuits can be provided with a second reference connecting block 35-1 away from one side of the third plate 73 of the nth row of pixel circuits, the second reference connecting block 35-1 can be provided in each pixel circuit, a first end of the second reference connecting block 35-1 is connected with the second reference signal line 35, and a second end of the second reference connecting block 35-1 can extend towards the direction of the side away from the third plate 73, i.e. towards the direction of the (n-1)th row of pixel circuits. In some examples, the second reference connecting block 35-1 of the second reference signal line 35 in the nth unit row is configured to be connected with the first area 181 of the ninth active layer 19 of the (n-1)th row of pixel circuits through the sixth connecting electrode formed subsequently, so as to provide the second reference signal to the first electrode of the ninth transistor T9 in the (n-1)th row of pixel circuits. In some examples, the second reference signal line 35 and the plurality of second reference connecting blocks 35-1 can be an integrated structure connected with each other.

[0714] In some examples, the third plate 73 of the first capacitor can have a rectangular shape, the corners of the rectangular shape can be provided with a chamfer, the third plate 73 can be located between the first enabling signal line 31 and the second reference signal line 35 of the pixel circuit, the first enabling signal line 31 can be located between the third plate 73 and the first initial signal line 32, the orthographic projection of the third plate 73 on the substrate layer and the orthographic projection of the first plate 71 on the substrate layer can at least partially overlap, the third plate 73 can serve as the upper plate of the first capacitor, i.e. the third plate 73 can serve as one end of the first capacitor C1 connected with the second node N2, the first plate 71 can serve as the other end of the first capacitor C1 connected with the first node N1, and the first plate 71 and the third plate 73 can constitute the first capacitor C1 of the pixel circuit.

[0715] In some examples, the fourth plate 74 of the second capacitor can have a rectangular shape, the corners of the rectangular shape can be chamfered, the fourth plate 74 can be located between the second reference signal line 35 of the pixel circuit and the third plate 73, the orthographic projection of the fourth plate 74 on the substrate layer can at least partially overlap the orthographic projection of the second plate 72 on the substrate layer, the fourth plate 74 can serve as the upper plate of the second capacitor, that is, the fourth plate 74 can serve as one end of the second capacitor C2 connected to the first power signal VDD, the second plate 72 can serve as the other end of the second capacitor C2 connected to the second node N2, and the second plate 72 and the fourth plate 74 can constitute the second capacitor C2 of the pixel circuit. In some examples, the second plate 72 and the third plate 73 can be electrically connected to the second node N2.

[0716] In some examples, the second capacitor C2 can further stabilize the voltage of the second node N2, and in turn can further stabilize the voltage of the first node N1.

[0717] In some examples, the orthographic projection of the third plate 73 on the substrate layer can have the same area as the orthographic projection of the fourth plate 74 on the substrate layer, or different areas. For example, the orthographic projection of the fourth plate 74 on the substrate layer can have an area smaller than the orthographic projection of the third plate 73 on the substrate layer.

[0718] In some examples, the fourth plate 74 can be provided with a first plate connecting line 74-1 on one side of the first direction X or on the opposite side of the first direction X, the first end of the first plate connecting line 74-1 is connected to the fourth plate 74 of the pixel circuit, and the other end of the first plate connecting line 74-1 extends along the first direction X or the opposite direction of the first direction X and is connected to the fourth plate 74 of the adjacent pixel circuit, so that the fourth plates 74 of the adjacent pixel circuits in each row of pixel circuits can be connected to each other. In some examples, the plurality of fourth plates 74 and the plurality of first plate connecting lines 74-1 can form an integrated structure. For example, the dimension of the first plate connecting line 74-1 along the second direction Y can be substantially the same as the dimension of the fourth plate 74 along the second direction Y. Since the fourth plate 74 is connected to the first power line formed later, the fourth plates 74 of the integrated structure of the plurality of pixel circuits can be reused as the transverse power line extending along the first direction X, which not only ensures that the plurality of fourth plates 74 in each row of pixel circuits have the same potential, but also reduces the voltage drop of the first power signal, which is conducive to improving the uniformity of the display panel, avoiding display defects of the display panel, and ensuring the display effect of the display panel.

[0719] In some examples, the third plate 73 of each pixel circuit can be provided with a first opening 730, which can be located in the middle of the third plate 73. The first opening 730 can be rectangular, so that the third plate 73 forms a ring-shaped structure. The first opening 730 can expose the second insulating layer covering the first plate 71 at the corresponding position, and the orthographic projection of the first plate 71 on the substrate layer can cover the orthographic projection of the first opening 730 on the substrate layer, i.e., the area where the first opening 730 is located falls within the area where the first plate 71 is located. The first opening 730 can penetrate the second conductive layer in the thickness direction, i.e., the first opening 730 can penetrate the third plate 73. In some examples, the first opening 730 can be configured to accommodate the tenth via hole formed subsequently, which can be located in the first opening 730 and expose part of the surface of the first plate 71, so that the first connecting electrode formed subsequently is connected with the first plate 71.

[0720] In some examples, the fourth plate 74 of each pixel circuit can be provided with a second opening 740, which can be located in the middle of the fourth plate 74. The second opening 740 can be rectangular, so that the fourth plate 74 forms a ring-shaped structure. The second opening 740 can expose the second insulating layer covering the second plate 72 at the corresponding area, and the orthographic projection of the second plate 72 on the substrate layer can contain the orthographic projection of the second opening 740 on the substrate layer. The second opening 740 can penetrate the fourth plate 74 in the thickness direction. In some examples, the second opening 740 can be configured to accommodate the eleventh via hole formed subsequently, which can be located in the second opening 740 and expose part of the surface of the second plate 72, so that the third connecting electrode formed subsequently is connected with the second plate 72. In some examples, the second opening 740 and the first opening 730 can not be aligned in the second direction Y.

[0721] In some examples, the fourth plate 74 can be provided with a second protruding portion 74-2 near one side of the second reference signal line 35, which can be provided in each pixel circuit. The second protruding portion 74-2 can be located on the side opposite to the second opening 740 in the second direction Y. The first end of the second protruding portion 74-2 is connected with the fourth plate 74, and the other end of the second protruding portion 74-2 extends towards the side near the first gate 21. The orthographic projection of the second protruding portion 74-2 on the substrate layer can be located between the first area 111 of the first active layer 11 and the second area 172 of the seventh active layer 17 of the current pixel circuit. The second protruding portion 74-2 of the current example can be configured to shield the influence of data voltage jump on the second node N2, so as to avoid the influence of data voltage jump on the normal work of the pixel circuit and improve the display effect. In some examples, the fourth plate 74 and the second protruding portion 74-2 can be an integrated structure connected with each other.

[0722] In some examples, a third protrusion 74-3 may be provided on the side of the fourth electrode 74 near the second reference signal line 35. The third protrusion 74-3 may be provided in each pixel circuit. The second protrusion 74-2 and the third protrusion 74-3 may be adjacent in the first direction X. For example, the third protrusion 74-3 may be located on the side of the second protrusion 74-2 in the first direction X. The first end of the third protrusion 74-3 is connected to the fourth electrode 74, and the other end of the third protrusion 74-3 extends toward the side near the seventh gate 27 and extends into the first groove K1. The orthographic projection of the third protrusion 74-3 onto the substrate layer and the orthographic projection of the first protrusion 72-1 of the second electrode 72 onto the substrate layer may at least partially overlap, for example, they may coincide with each other. For example, the dimension of the second protrusion 74-2 along the second direction Y can be larger than the dimension of the third protrusion 74-3 along the second direction Y, and the dimension of the second protrusion 74-2 along the first direction X can be smaller than the dimension of the third protrusion 74-3 along the first direction X. In this example, by setting the third protrusion 74-3 to at least partially overlap with the first electrode plate connection line 74-1, the area of ​​the second capacitor C2 can be increased, effectively increasing the total capacitance of the second capacitor C2, thereby improving the working performance of the pixel circuit and enhancing the display effect. In some examples, the fourth electrode plate 74 and the third protrusion 74-3 can be an integrally connected structure.

[0723] In some examples, the first shielding electrode 36 can have a substantially "T" shape, the first shielding electrode 36 can be located on a side of the fourth plate 74 close to the first enable signal line 31, and the first shielding electrode 36 can be disposed in each pixel circuit. The first shielding electrode 36 in the "T" shape can include a first extension segment 36-1 and a first shielding segment 36-2; one end of the first extension segment 36-1 is connected to the fourth plate 74, and the other end of the first extension segment 36-1 extends toward the side close to the first enable signal line 31 and is connected to the first shielding segment 36-2. The first shielding segment 36-2 can have a strip shape extending along the first direction X. The first shielding segment 36-2 can include a first shielding end 36-3 on one side of the first extension segment 36-1 in the first direction X and a second shielding end 36-4 on the other side of the first extension segment 36-1 in the opposite direction of the first direction X. The first shielding end 36-3 has a normal projection on the substrate layer that at least partially overlaps with a normal projection on the substrate layer of a fourth active layer between two gates of the fourth transistor T4 in the pixel circuit to which the first shielding end 36-3 belongs, and the second shielding end 36-4 has a normal projection on the substrate layer that at least partially overlaps with a normal projection on the substrate layer of a second active layer between two gates of the second transistor T2 in an adjacent pixel circuit. In some examples, the first shielding electrode 36 can be configured to shield the influence of data voltage jump on the fourth transistor T4 and the second transistor T2, avoid the influence of data voltage jump on the normal operation of the pixel circuit, and improve the display effect. In some examples, the fourth plate 74 and the first shielding electrode 36 can be an integrated structure connected to each other.

[0724] In some examples, the first shielding end 36-3 of the first shielding segment 36-2 has a normal projection on the substrate layer that partially overlaps with a normal projection on the substrate layer of a first region 131 of the third active layer 13 (also a second region 152 of the fifth active layer 15 and a second region 192 of the ninth active layer) in the pixel circuit. Since the first region 131 of the third active layer 13 (also the second region 152 of the fifth active layer 15 and the second region 192 of the ninth active layer) is a conductor layer after the conductor treatment, the first shielding segment 36-2 is also a conductor layer, and thus the first region 131 of the third active layer 13 (also the second region 152 of the fifth active layer 15 and the second region 192 of the ninth active layer) in one pixel circuit and the first shielding end 36-3 of the first shielding segment 36-2 of the first shielding electrode 36 of the pixel circuit can form a first voltage-stabilizing capacitor. Since the first shielding electrode 36 can be subsequently connected to the first power supply connection line to receive a first power supply signal with a constant voltage, the first voltage-stabilizing capacitor can be configured to stabilize the potential of the third node N3, prevent signal crosstalk, avoid the influence of data voltage jump on the third node N3, ensure the normal operation of the pixel circuit, and improve the display effect.

[0725] In some examples, the second shielding end 36-4 of the first shielding segment 36-2 is partially overlapped with the second region 132 of the third active layer 13 (also the first region 161 of the sixth active layer 16 and the second region 122 of the second active layer 12) in the adjacent pixel circuit in the orthographic projection on the substrate layer. Since the second region 132 of the third active layer 13 (also the first region 161 of the sixth active layer 16 and the second region 122 of the second active layer 12) is a conductor layer after the conductorization process, and the first shielding segment 36-2 is also a conductor layer, the second region 132 of the third active layer 13 (also the first region 161 of the sixth active layer 16 and the second region 122 of the second active layer 12) in one pixel circuit and the second shielding end 36-4 of the first shielding segment 36-2 of the first shielding electrode 36 of the adjacent pixel circuit can form a second voltage-stabilizing capacitor. Since the first shielding electrode 36 can be connected with the first power supply connection line later to receive the first power supply signal with constant voltage, the second voltage-stabilizing capacitor can be configured to stabilize the potential of the fourth node N4, prevent signal crosstalk, avoid the influence of data voltage jump on the fourth node N4, and thus ensure the normal work of the pixel circuit and improve the display effect.

[0726] In some examples, in combination with FIG. 11, the first shielding end 36-3 can form a coupling capacitor with the fourth transistor T4, that is, the first shielding end 36-3 accesses the first power supply signal VDD as one plate of the coupling capacitor, and part of the fourth active layer 14 of the fourth transistor T4 serves as the other plate of the coupling capacitor, so that the coupling capacitor can play a voltage-stabilizing role. The second shielding end 36-4 can form a coupling capacitor with the second transistor T2, that is, the second shielding end 36-4 accesses the first power supply signal VDD as one plate of the coupling capacitor, and part of the second active layer 12 of the second transistor T2 serves as the other plate of the coupling capacitor, so that the coupling capacitor can play a voltage-stabilizing role.

[0727] In some examples, the second transistor T2 and the fourth transistor T4 are electrically connected to the first node N1, and the first transistor T1 and the seventh transistor T7 are electrically connected to the second node N2. The second transistor T2 and the fourth transistor T4 are configured in a double-gate structure, and the first transistor T1 and the seventh transistor T7 are configured in a double-gate structure. The double-gate structure can control the leakage current of the transistors, and thus the voltage stability of the first node N1 and the second node N2 can be improved.

[0728] In some examples, the second shielding electrode 37 and the third shielding electrode 38 can be rectangular in shape, and can be located on the side of the second reference signal line 35 close to the fourth plate 74. The second shielding electrode 37 and the third shielding electrode 38 can be arranged in each pixel circuit. One end of the second shielding electrode 37 and the third shielding electrode 38 is connected to the second reference signal line 35, and the other end of the second shielding electrode 37 and the third shielding electrode 38 can extend towards the fourth plate 74. The orthogonal projection of the second shielding electrode 37 on the substrate layer can at least partially overlap with the orthogonal projection of the first active layer 11 between the two gates of the first transistor T1 in the pixel circuit, and the orthogonal projection of the third shielding electrode 38 on the substrate layer can at least partially overlap with the orthogonal projection of the seventh active layer 17 between the two gates of the seventh transistor T7 in the pixel circuit. In some examples, the second shielding electrode 37 can be configured to shield the influence of data voltage jump on the first transistor T1, and the third shielding electrode 38 can be configured to shield the influence of data voltage jump on the seventh transistor T7, so as to avoid the influence of data voltage jump on the normal operation of the pixel circuit and improve the display effect.

[0729] In some examples, in combination with FIG. 11, the second shielding electrode 37 can form a coupling capacitor with the first transistor T1, that is, the second shielding electrode 37 accesses the second reference signal Vref2 as one plate of the coupling capacitor, and part of the first active layer 11 of the first transistor T1 serves as the other plate of the coupling capacitor, so that the coupling capacitor can function as a voltage stabilizer. The third shielding electrode 38 can form a coupling capacitor with the seventh transistor T7, that is, the third shielding electrode 38 accesses the second reference signal Vref2 as one plate of the coupling capacitor, and part of the seventh active layer 17 of the seventh transistor T7 serves as the other plate of the coupling capacitor, so as to function as a voltage stabilizer.

[0730] In some examples, the second shielding electrode 37 and the third shielding electrode 38 can also function as light shielding, and can shield light for the active layer to avoid light leakage.

[0731] The fourth process is to form a third insulating layer. In some examples, a third insulating film is deposited on the side of the second conductive layer pattern away from the substrate layer, and the third insulating film is patterned by a patterning process to form a third insulating layer. The third insulating layer of each pixel circuit is provided with a plurality of vias, as shown in FIG. 14. FIG. 14 is a schematic diagram of the partial planar structure of the display panel after etching the vias in FIG. 12.

[0732] In some examples, the first insulating layer can include silicon nitride and / or silicon oxide; the second insulating layer can include silicon nitride and / or silicon oxide; and the third insulating layer can include silicon nitride and / or silicon oxide. In the case where the insulating layer includes silicon nitride and silicon oxide, the silicon nitride and the silicon oxide can be provided in a manner of being stacked in a thickness direction, for example, the third insulating layer can include a stacked structure of silicon oxide-silicon nitride-silicon oxide.

[0733] In some examples, the plurality of vias of each pixel circuit in the display panel can include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21, a twenty-second via V22, and a twenty-sixth via V26.

[0734] In some examples, the orthographic projection of the first via V1 on the substrate layer can be located within the orthographic projection of the first region 141 of the fourth active layer 14 on the substrate layer, the third insulating layer, the second insulating layer, and the first insulating layer within the first via V1 can be etched away, exposing part of the surface of the first region 141 of the fourth active layer 14, the first via V1 can be configured to enable the ninth connection electrode of the subsequent pass to connect with the first region of the fourth active layer 14 through the via, and in turn enable the first region of the fourth active layer 14 to connect with the first initial signal line formed subsequently through the twenty-sixth via V26 and the first region of the first active layer through the ninth connection electrode.

[0735] In some examples, the orthographic projection of the second via V2 on the substrate layer can be located within the orthographic projection of the second region 142 of the fourth active layer 14 (also the first region 121 of the second active layer 12) on the substrate layer, the third insulating layer, the second insulating layer, and the first insulating layer within the second via V2 can be etched away, exposing part of the surface of the second region 142 of the fourth active layer 14 (also the first region 121 of the second active layer 12), the second via V2 can be configured to enable the first connection electrode formed subsequently to connect with the second region 142 of the fourth active layer 14 (also the first region 121 of the second active layer 12) through the via.

[0736] In some examples, the third via V3 can be configured such that a third connection electrode formed subsequently can be connected to the first region 111 of the first active layer 11 through the via.

[0737] In some examples, the fourth via V4 can be configured such that a third connection electrode formed subsequently can be connected to the second region 112 of the first active layer 11 (also the second region 172 of the seventh active layer 17) through the via.

[0738] In some examples, the fifth via V5 can be configured such that a fourth connection electrode formed subsequently can be connected to the first region 151 of the fifth active layer 15 through the via.

[0739] In some examples, the sixth via V6 can be configured such that a fifth connection electrode formed subsequently can be connected to the second region 162 of the sixth active layer 16 (also the second region 182 of the eighth active layer 18) through the via.

[0740] In some examples, the seventh via V7 can be configured such that a second initial signal line formed subsequently can be connected to the first region 181 of the eighth active layer 18 through the via.

[0741] In some examples, the orthographic projection of the eighth via V8 on the substrate layer can be within the orthographic projection of the first region 191 of the ninth active layer 19 on the substrate layer, the third insulating layer, the second insulating layer and the first insulating layer within the eighth via V8 can be etched away, exposing part of the surface of the first region 191 of the ninth active layer 19, and the eighth via V8 can be configured to enable a sixth connection electrode formed subsequently to connect with the first region 191 of the ninth active layer 19 through the via.

[0742] In some examples, the orthographic projection of the ninth via V9 on the substrate layer can be within the orthographic projection of the first region 171 of the seventh active layer 17 on the substrate layer, the orthographic projection of the ninth via V9 on the substrate layer can be within the orthographic projection of the first reference connection block 34-1 on the substrate layer, the third insulating layer, the second insulating layer and the first insulating layer within the ninth via V9 can be etched away, exposing part of the surface of the first region 171 of the seventh active layer 17, and the ninth via V9 can be configured to enable a first reference signal line formed subsequently to connect with the first region 171 of the seventh active layer 17 through the via.

[0743] In some examples, the orthographic projection of the tenth via V10 on the substrate layer can be within the orthographic projection of the first opening 730 of the third plate 73 on the substrate layer, the third insulating layer and the second insulating layer within the tenth via V10 can be etched away, exposing part of the surface of the first plate 71, and the tenth via V10 can be configured to enable a first connection electrode formed subsequently to connect with the first plate 71 through the via.

[0744] In some examples, the orthographic projection of the eleventh via V11 on the substrate layer can be within the orthographic projection of the second opening 740 of the fourth plate 74 on the substrate layer, the third insulating layer and the second insulating layer within the eleventh via V11 can be etched away, exposing part of the surface of the second plate 72, and the eleventh via V11 can be configured to enable a third connection electrode formed subsequently to connect with the second plate 72 through the via.

[0745] In some examples, the orthographic projection of the twelfth via V12 on the substrate layer can be within the orthographic projection of the third plate 73 on the substrate layer, the third insulating layer within the twelfth via V12 can be etched away, exposing part of the surface of the third plate 73, and the twelfth via V12 can be configured to enable a third connection electrode formed subsequently to connect with the third plate 73 through the via.

[0746] In some examples, the orthogonal projection of the thirteenth via V13 on the substrate layer can be located within the range of the orthogonal projection of the fourth plate 74 on the substrate layer, the third insulating layer within the thirteenth via V13 can be etched away to expose part of the surface of the fourth plate 74, and the thirteenth via V13 can be configured to enable a first power connection line formed subsequently to connect with the fourth plate 74 through the via.

[0747] In some examples, the orthogonal projection of the fourteenth via V14 on the substrate layer can be located within the range of the orthogonal projection of the fourth gate 24 on the substrate layer, the third insulating layer and the second insulating layer within the fourteenth via V14 can be etched away to expose part of the surface of the fourth gate 24, and the fourteenth via V14 can be configured to enable a third gate signal line formed subsequently to connect with the fourth gate 24 through the via.

[0748] In some examples, the orthogonal projection of the fifteenth via V15 on the substrate layer can be located within the range of the orthogonal projection of the second gate 22 on the substrate layer, the third insulating layer and the second insulating layer within the fifteenth via V15 can be etched away to expose part of the surface of the second gate 22, and the fifteenth via V15 can be configured to enable a fifth scan signal line formed subsequently to connect with the second gate 22 through the via.

[0749] In some examples, the orthogonal projection of the sixteenth via V16 on the substrate layer can be located within the range of the orthogonal projection of the first gate 21 on the substrate layer, the third insulating layer and the second insulating layer within the sixteenth via V16 can be etched away to expose part of the surface of the first gate 21, and the sixteenth via V16 can be configured to enable a first gate signal line formed subsequently to connect with the first gate 21 through the via.

[0750] In some examples, the orthogonal projection of the seventeenth via V17 on the substrate layer can be located within the range of the orthogonal projection of the fifth gate 25 on the substrate layer, the third insulating layer and the second insulating layer within the seventeenth via V17 can be etched away to expose part of the surface of the fifth gate 25, and the seventeenth via V17 can be configured to enable a seventh connection electrode formed subsequently to connect with the fifth gate 25 through the via.

[0751] In some examples, the orthogonal projection of the eighteenth via V18 on the substrate layer can be located within the range of the orthogonal projection of the sixth gate 26 on the substrate layer, the third insulating layer and the second insulating layer within the eighteenth via V18 can be etched away to expose part of the surface of the sixth gate 26, and the eighteenth via V18 can be configured to enable an eighth connection electrode formed subsequently to connect with the sixth gate 26 through the via.

[0752] In some examples, the orthogonal projection of the nineteenth via V19 on the substrate layer can be located within the orthogonal projection of the seventh gate 27 on the substrate layer, the third insulating layer and the second insulating layer within the nineteenth via V19 can be etched away to expose part of the surface of the seventh gate 27, and the nineteenth via V19 can be configured to enable a second gate signal line formed subsequently to be connected to the seventh gate 27 through the via.

[0753] In some examples, the orthogonal projection of the twentieth via V20 on the substrate layer can be located within the orthogonal projection of the first light-emitting connection block 31-1 of the first enable signal line 31 on the substrate layer, the third insulating layer within the twentieth via V20 can be etched away to expose at least part of the surface of the first light-emitting connection block 31-1, and the twentieth via V20 can be configured to enable an eighth connection electrode formed subsequently to be connected to the first light-emitting connection block 31-1 through the via.

[0754] In some examples, the orthogonal projection of the twenty-first via V21 on the substrate layer can be located within the orthogonal projection of the second light-emitting connection block 33-1 of the second enable signal line 33 on the substrate layer, the third insulating layer within the twenty-first via V21 can be etched away to expose at least part of the surface of the second light-emitting connection block 33-1, and the twenty-first via V21 can be configured to enable a ninth connection electrode formed subsequently to be connected to the second light-emitting connection block 33-1 through the via.

[0755] In some examples, the orthogonal projection of the twenty-second via V22 on the substrate layer can be located within the orthogonal projection of the second reference connection block 35-1 of the second reference signal line 35 on the substrate layer, the third insulating layer within the twenty-second via V22 can be etched away to expose the surface of the second reference connection block 35-1, and the twenty-second via V22 can be configured to enable a sixth connection electrode formed subsequently to be connected to the second reference connection block 35-1 through the via.

[0756] In some examples, the orthogonal projection of the twenty-sixth via V26 on the substrate layer can be located within the orthogonal projection of the first bump 32-1 of the first initial signal line 32 on the substrate layer. The third insulating layer within the twenty-sixth via V26 is etched away to expose the surface of the first bump 32-1 of the first initial signal line 32, and the twenty-sixth via V26 can be configured to enable a ninth connection electrode formed subsequently to be connected to the first bump 32-1 through the via.

[0757] Fifth process: forming a third conductive layer. In some examples, a third conductive thin film is deposited on the side of the patterned third insulating layer away from the substrate layer, and the third conductive thin film is patterned using a patterning process to form a third conductive layer disposed on the third insulating layer, as shown in FIGS. 15 and 16.

[0758] FIG. 15 is a schematic diagram of a partial planar structure of the display panel after forming a third conductive layer in FIG. 14; and FIG. 16 is a schematic diagram of a partial planar structure of a third conductive layer provided by the present disclosure. In some examples, the third conductive layer can be referred to as a first source-drain electrode layer, and the third conductive layer can include a metal material.

[0759] In some examples, the third conductive layer of each of the plurality of pixel circuits in the display panel can include: a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a seventh connection electrode 47, an eighth connection electrode 48, a ninth connection electrode 49, a first gate signal line 61, a second gate signal line 62, a third gate signal line 63, a first power connection line 66, a fifth gate signal line 65, a second initial signal line 82, and a first reference signal line 34.

[0760] In some examples, the second gate signal line 62 and the fifth gate signal line 65 can each be configured to transmit a second gate signal GL2.

[0761] In some examples, the first gate signal line 61, the second gate signal line 62, the third gate signal line 63, the fifth gate signal line 65, the second initial signal line 82, and the first reference signal line 34 can each have a linear shape with a main body portion extending along the first direction X. The first power connection line 66 can have a polyline shape with a main body portion extending along the first direction X. The first gate signal line 61, the second gate signal line 62, and the first reference signal line 34 can be located on a side of the fourth plate 74 away from the third plate 73, the third gate signal line 63, the fifth gate signal line 65, and the second initial signal line 82 can be located on a side of the third plate 73 away from the fourth plate 74, and an area in which the first power connection line 66 is located can partially overlap an area in which the third plate 73 is located.

[0762] In some examples, the first reference signal line 34 can be located on a side of the fourth plate 74 in the opposite direction of the second direction Y, the second gate signal line 62 can be located on a side of the first reference signal line 34 in the opposite direction of the second direction Y, and the first gate signal line 61 can be located on a side of the second gate signal line 62 in the opposite direction of the second direction Y.

[0763] In some examples, the third gate signal line 63 can be located on a side of the third plate 73 in the second direction Y, the fifth gate signal line 65 can be located on a side of the third gate signal line 63 in the second direction Y, and the second initial signal line 82 can be located on a side of the fifth gate signal line 65 in the second direction Y. The fifth gate signal line 65 can be located between the third gate signal line 63 and the second initial signal line 82.

[0764] In some examples, the orthogonal projection of the third gate signal line 63 on the substrate layer can cover the active layer region between the two gates of the second transistor T2, the orthogonal projection of the third gate signal line 63 on the substrate layer can cover the active layer region between the two gates of the fourth transistor T4, the third gate signal line 63 can form a coupling capacitor with the active layer, can shield interference signals, and can also play a light shielding role.

[0765] The embodiments of the present disclosure set the first gate signal line 61, the second gate signal line 62, the third gate signal line 63, and the fifth gate signal line 65 on the third conductive layer, and the fourth gate signal line 64 on the first conductive layer. Except for the fourth gate signal line 64, the first conductive layer is provided with the gates of the transistors. Since the number of gate signal lines is large and the coverage area is large, the gate signal lines are arranged in two layers of conductive layers, which can convert the planar arrangement of the gate signal lines into a vertical arrangement, can reduce the occupied space of the planar arrangement, and the saved space can be used to arrange other wiring or film layer structures, which can provide space for improving the pixel arrangement density.

[0766] The present example sets the first initial signal line 32 on the second conductive layer and the second initial signal line 82 on the third conductive layer, which can increase the wiring space. The resistance of the first initial signal line 32 can be reduced, and the transmission effect of the first initial signal 32 can be ensured. By setting the first initial signal line 32 between the first enable signal line 31 and the second enable signal line 33, the distance between the first initial signal line 32 and the channel region of the fourth active layer of the fourth transistor T4 can be reduced. The first initial signal line 32 can provide the first initial signal for initializing the fourth transistor T4 through the shortest path, thereby facilitating the reduction of the length of the first region of the fourth active layer, reducing the load of the first initial signal line, and optimizing the initialization effect.

[0767] In some examples, the first power connection line 66 can be located on the side of the fourth plate 74 close to the third plate 73, and the orthogonal projection of the first power connection line 66 on the substrate layer can partially overlap the orthogonal projection of the third plate 73 on the substrate layer. The first power connection line 66 can be configured to be connected with the first power line formed subsequently, and a mesh communication structure of the high-voltage power grid structure is formed on the display panel.

[0768] In some examples, the first gate signal line 61 can be connected with the first gate 21 of the pixel circuit through the sixteenth via V16, which can realize that the first gate signal line 61 is connected with the first gate 21 of the first transistor T1, and the first gate signal GL1 transmitted by the first gate signal line 61 can control the conduction and disconnection of the first transistor T1.

[0769] In some examples, the second gate signal line 62 can be connected with the seventh gate 27 of the pixel circuit through the nineteenth via V19, so as to realize that the second gate signal line 62 is connected with the seventh gate 27 of the seventh transistor T7, and the second gate signal GL2 transmitted by the second gate signal line 62 can control the turn-on and turn-off of the seventh transistor T7.

[0770] In some examples, the first reference signal line 34 can be connected with the first region 171 of the seventh active layer 17 through the ninth via V9, so as to realize that the first reference signal line 34 is connected with the first electrode of the seventh transistor T7, and the first reference signal Vref1 transmitted by the first reference signal line 34 can be written into the first electrode of the seventh transistor T7.

[0771] In some examples, the third gate signal line 63 can be connected with the fourth gate 24 through the fourteenth via V14, so as to realize that the third gate signal line 63 is connected with the fourth gate 24 of the fourth transistor T4, and the third gate signal GL3 transmitted by the third gate signal line 63 can control the turn-on and turn-off of the fourth transistor T4.

[0772] In some examples, the fifth gate signal line 65 can be connected with the second gate 22 through the fifteenth via V15, so as to realize that the fifth gate signal line 65 is connected with the second gate 22 of the second transistor T2, and the second gate signal GL2 transmitted by the fifth gate signal line 65 can control the turn-on and turn-off of the second transistor T2.

[0773] In some examples, the second initial signal line 82 can be connected with the first region 181 of the eighth active layer 18 in the pixel circuit through the seventh via V7, so as to realize that the second initial signal line 82 is connected with the first electrode of the eighth transistor T8, and the second initial signal line 82 can write the second initial signal Vinit2 into the first electrode of the eighth transistor T8.

[0774] In some examples, the second initial signal line 82 can be provided with a second initial connection block 82-1 on one side close to the fifth gate signal line 65, and the second initial connection block 82-1 can be located between two adjacent pixel circuits in at least one row. The first end of the second initial connection block 82-1 is connected with the second initial signal line 82, and the other end of the second initial connection block 82-1 extends towards the direction of the side where the fifth gate signal line 65 is located, and the second initial connection block 82-1 can be configured to be connected with the second initial signal connection line formed subsequently.

[0775] In some examples, the first reference signal line 34 can be provided with a first reference connection block 34-1 near a side of the first power connection line 66, a first end of the first reference connection block 34-1 is connected with the first reference signal line 34, a second end of the first reference connection block 34-1 extends towards a direction of the first power connection line 66, and the first reference connection block 34-1 can be configured to be connected with a subsequently formed first reference signal connection line.

[0776] In some examples, the first power connection line 66 can be connected with the fourth plate 74 in the pixel circuit through a thirteenth via V13, and the first power connection line 66 can write the first power signal to the upper plate of the second capacitor (i.e., the first end of the second capacitor) due to the connection between the first power connection line 66 and a subsequently formed first power line.

[0777] In some examples, the first power connection line 66 can be provided with a first power connection block 66-1 near a side of the first scan signal line 61, a first end of the first power connection block 66-1 is connected with the first power connection line 66, and a second end of the first power connection block 66-1 extends away from the first scan signal line 61. In some examples, the first power connection block 66-1 can be configured to be connected with the fourth plate 74 through the thirteenth via V13 and to be connected with a subsequently formed first power line.

[0778] In some examples, the first connection electrode 41 can have a strip shape with a main body extending along the second direction Y, and the first connection electrode 41 can be located between the third gate signal line 63 and the first power connection line 66. A first end of the first connection electrode 41 can be connected with the second region 142 of the fourth active layer 14 (also the first region 121 of the second active layer 12) through the second via V2, and a second end of the first connection electrode 41 can be connected with the first plate 71 of the first capacitor through the tenth via V10. In some examples, the first connection electrode 41 can make the second electrode of the fourth transistor T4, the first electrode of the second transistor T2, the gate of the third transistor T3, and the first plate 71 of the first capacitor (i.e., the first end of the first capacitor) have the same potential, and the first connection electrode 41 can serve as a first node N1 of the pixel circuit.

[0779] In some examples, the second connection electrode 42 can have a substantially rectangular shape, and the second connection electrode 42 can be located between the first reference signal line 34 and the first power connection line 66. The second connection electrode 42 can be connected with the first region 111 of the first active layer 11 through the third via V3. In some examples, the second connection electrode 42 can serve as the first electrode of the first transistor T1, and the second connection electrode 42 can be configured to be connected with a subsequently formed data signal line.

[0780] In some examples, the third connection electrode 43 can have a shape of a broken line extending along the second direction Y, the third connection electrode 43 can be located between the first reference signal line 34 and the first power connection line 66, a first end of the third connection electrode 43 can be connected to the second region 112 of the first active layer 11 (also the second region 172 of the seventh active layer 17) through the fourth via V4, a second end of the third connection electrode 43 can be connected to the third plate 73 through the twelfth via V12, and a third end between the first end and the second end can be connected to the second plate 72 through the eleventh via V11. In some examples, the third connection electrode 43 can pass through the second opening 740 to make the second electrode of the first transistor T1, the second electrode of the seventh transistor T7, the third plate 73 of the first capacitor, and the second plate 72 of the second capacitor have the same potential, and the third connection electrode 43 can serve as the second node N2 of the pixel circuit.

[0781] In some examples, the fourth connection electrode 44 can have a shape of a rectangle, the fourth connection electrode 44 can be located between the fifth gate signal line 65 and the second initial signal line 82. The fourth connection electrode 44 can be connected to the first region 151 of the fifth active layer 15 through the fifth via V5. In some examples, the fourth connection electrode 44 can serve as the first electrode of the fifth transistor T5, and the fourth connection electrode 44 can be configured to be connected to the first power line formed later.

[0782] In some examples, the fifth connection electrode 45 can have a shape of an "L" letter or a "U" shape with a large opening, the fifth connection electrode 45 can be located between the fifth gate signal line 65 and the second initial signal line 82. The fifth connection electrode 45 can be connected to the second region 162 of the sixth active layer 16 (also the second region 182 of the eighth active layer 18) through the sixth via V6. In some examples, the fifth connection electrode 45 can serve as the second electrode of the sixth transistor T6 and the second electrode of the eighth transistor T8, and the fifth connection electrode 45 can be configured to be connected to the anode connection electrode formed later.

[0783] In some examples, the sixth connection electrode 46 can have a strip shape with a main body portion extending along the first direction X, and the sixth connection electrode 46 can be located between the fifth gate signal line 65 and the second initial signal line 82. The sixth connection electrode 46 can be located between the fifth connection electrode 45 and the second initial signal line 82, a first end of the sixth connection electrode 46 can be connected to the first area 191 of the ninth active layer 19 through the eighth via V8, and a second end of the sixth connection electrode 46 can be connected to the second reference connection block 35-1 through the twenty-second via V22. In some examples, the sixth connection electrode 46 can serve as a first electrode of the ninth transistor T9, and since the second reference connection block 35-1 is connected to the second reference signal line 35, the second reference signal line 35 is connected to the first electrode of the ninth transistor T9, and the second reference signal line 35 of the nth row of pixel circuits can write the second reference signal Vref2 to the first electrode of the ninth transistor T9 in the nth-1 row of pixel circuits.

[0784] In some examples, the seventh connection electrode 47 can have a strip shape with a main body portion extending along the first direction X, and the seventh connection electrode 47 can be located between the fifth gate signal line 65 and the second initial signal line 82. A first end of the seventh connection electrode 47 can be connected to the fifth gate 25 through the seventeenth via V17, and a second end of the seventh connection electrode 47 can be connected to the first light emitting connection block 31-1 through the twentieth via V20. Since the first light emitting connection block 31-1 is connected to the first enable signal line 31, the first enable signal line 31 is connected to the fifth gate 25 of the fifth transistor T5, and the first enable signal line 31 can control the turn-on and turn-off of the fifth transistor T5.

[0785] In some examples, the eighth connection electrode 48 can have a strip shape with a main body portion extending along a third direction intersecting the first direction X and the second direction Y. The eighth connection electrode 48 can be located between the fifth gate signal line 65 and the second initial signal line 82. A first end of the eighth connection electrode 48 can be connected to the sixth gate 26 through the eighteenth via V18, and a second end of the eighth connection electrode 48 can be connected to the second light emitting connection block 33-1 through the twenty-first via V21. Since the second light emitting connection block 33-1 is connected to the second enable signal line 33, the second enable signal line 33 is connected to the sixth gate 26 of the sixth transistor T6, and the second enable signal line 33 can control the turn-on and turn-off of the sixth transistor T6.

[0786] In some examples, the fifth transistor T5 is controlled to be turned on and turned off by a first enable signal EM, the sixth transistor T6 is controlled to be turned on and turned off by a second enable signal EM2, the fifth transistor T5 and the sixth transistor T6 are independently controlled switches, respectively, and the first power signal VDD can be written to the third node N3 through the turned-on fifth transistor T5, the first power signal VDD is written to the fourth node N4 through the turned-on third transistor T3, and the first power signal VDD is written to the fifth node N5 through the turned-on sixth transistor T6, so as to drive the light emitting device to emit light.

[0787] In some examples, the ninth connection electrode 49 can have a strip shape with a main body portion extending in the first direction X. The ninth connection electrode 49 can be located between the fifth gate signal line 65 and the second initial signal line 82. A first end of the ninth connection electrode 49 can be connected to the first region 141 of the fourth active layer 14 through the first via V1, and a second segment of the ninth connection electrode 49 can be connected to the first bump 32-1 of the first initial signal line 32 through the twenty-sixth via V26, so as to realize the connection between the ninth connection electrode 49 and the first initial signal line 32, and the ninth connection electrode 49 can realize the connection of the first electrode of the fourth transistor T4 to the first initial signal Vinit1.

[0788] The sixth process: forming a fourth insulating layer. In some examples, on the substrate layer on which the third conductive layer pattern is formed, a fourth insulating film is coated, and the fourth insulating film is patterned by using a patterning process to form a fourth insulating layer covering the third conductive layer. The fourth insulating layer in each pixel circuit can be provided with a plurality of vias, as shown in FIG. 17. FIG. 17 is a schematic diagram of the partial planar structure of the display panel after etching the via in FIG. 15. In some examples, the fourth insulating layer can also be referred to as a first planar layer, and the fourth insulating layer can include an organic insulating material.

[0789] In some examples, the plurality of vias of each pixel circuit in the display panel can at least include: a thirty-first via V31, a thirty-second via V32, a thirty-third via V33, a thirty-fourth via V34, and a thirty-fifth via V35.

[0790] In some examples, the orthographic projection of the thirty-first via V31 on the substrate layer can be located within the range of the orthographic projection of the second connection electrode 42 on the substrate layer, the fourth insulating layer in the thirty-first via V31 can be removed to expose part of the surface of the second connection electrode 42, and the thirty-first via V31 can be configured to enable the subsequent data signal line to be connected to the second connection electrode 42 through the via.

[0791] In some examples, the orthogonal projection of the thirty-second via V32 on the substrate layer can be located within the orthogonal projection of the fourth connection electrode 44 on the substrate layer, the fourth insulating layer in the thirty-second via V32 can be etched away to expose part of the surface of the fourth connection electrode 44, and the thirty-second via V32 can be configured to enable a first power line formed subsequently to be connected to the fourth connection electrode 44 through the via.

[0792] In some examples, the orthogonal projection of the thirty-third via V33 on the substrate layer can be located within the orthogonal projection of the fifth connection electrode 45 on the substrate layer, the fourth insulating layer in the thirty-third via V33 can be etched away to expose part of the surface of the fifth connection electrode 45, and the thirty-third via V33 can be configured to enable an anode connection electrode formed subsequently to be connected to the fifth connection electrode 45 through the via.

[0793] In some examples, the orthogonal projection of the thirty-fourth via V34 on the substrate layer can be located within the orthogonal projection of the first reference signal line 34 on the substrate layer, the fourth insulating layer in the thirty-fourth via V34 can be etched away to expose part of the surface of the first reference signal line 34, and the thirty-fourth via V34 can be configured to enable a first reference signal connection line formed subsequently to be connected to the first reference signal line 34 through the via. The ninth via V9 and the thirty-fourth via V34 can have a certain distance or partially overlap, and the thirty-fourth via V34 can be located close to the region where the first reference connection block 34-1 is located.

[0794] In some examples, the orthogonal projection of the thirty-fifth via V35 on the substrate layer can be located within the orthogonal projection of the first power connection block 66-1 of the first power connection line 66 on the substrate layer, the fourth insulating layer in the thirty-fifth via V35 can be etched away to expose part of the surface of the first power connection block 66-1, and the thirty-fifth via V35 can be configured to enable a first power line formed subsequently to be connected to the first power connection block 66-1 through the via.

[0795] In some examples, the at least one pixel circuit can further include a thirty-sixth via V36. A projection in the substrate layer of the thirty-sixth via V36 can be located within a projection in the substrate layer of the second initial signal line 82, a fourth insulating layer in the thirty-sixth via V36 can be removed to expose a portion of a surface of the second initial signal line 82, and the thirty-sixth via V36 can be configured to enable a subsequently formed second initial signal connection line to connect to the second initial signal line 82 through the via. In some examples, the thirty-sixth via V36 can be located between the first pixel circuit and the second pixel circuit. In some examples, an area in which the second initial signal line 82 corresponding to the thirty-sixth via V36 can be provided with a bump, and a dimension of the bump in the second direction Y can be greater than a dimension of the second initial signal line 82 in the second direction Y, which can increase a connection area of the thirty-sixth via V36.

[0796] A seventh process: forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate layer on which the fourth insulating layer pattern is formed, and the fourth conductive film is patterned using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, as shown in FIGS. 18 and 19.

[0797] FIG. 18 is a partial planar structural schematic diagram of a display panel after a fourth conductive layer is formed in FIG. 17, and FIG. 19 is a partial planar structural schematic diagram of a fourth conductive layer provided by the present disclosure. In some examples, the fourth conductive layer can be referred to as a second source-drain electrode layer, and the fourth conductive layer can include a metal material.

[0798] In some examples, the fourth conductive layer of each of the plurality of pixel circuits in the display panel can include a data signal line 51, a first power supply line 52, a first reference signal connection line 53, and an anode connection electrode 55.

[0799] In some examples, the data signal line 51, the first power supply line 52, and the first reference signal connection line 53 can have a shape of a bar with a main body portion extending along the second direction Y. The first power supply line 52 can be located on one side of the data signal line 51 in the first direction X, and the first reference signal connection line 53 can be located on one side of the first power supply line 52 in the first direction X, i.e., the first power supply line 52 can be located between the data signal line 51 and the first reference signal connection line 53.

[0800] In some examples, the data signal line 51 can have a shape of a straight line with a main body portion extending along the second direction Y, and the data signal line 51 can be connected to the second connection electrode 42 through the thirty-first via V31. Since the second connection electrode 42 can be connected to the first region 111 of the first active layer 11 through the third via V3, the data signal line 51 can write a data signal Data to the first electrode of the first transistor T1.

[0801] In some examples, the first power line 52 can have a shape of a polyline with a main body portion extending along the second direction Y. The first power line 52 can be connected with the fourth connection electrode 44 through the thirty-second via V32 and connected with the first power connection block 66-1 through the thirty-fifth via V35. Since the fourth connection electrode 44 is connected with the first area 151 of the fifth active layer 15 through the fifth via V5, the first power line 52 can be used to write the first power signal VDD to the first electrode of the fifth transistor T5. Since the first power connection block 66-1 is connected with the first power connection line 66, the first power connection line 66 with the main body portion extending along the first direction X and the first power line 52 with the main body portion extending along the second direction Y can be connected with each other, so that the first power line 52 and the first power connection line 66 form a mesh structure on the display panel for transmitting the first power signal VDD, which can effectively reduce the resistance of the first power line 52, reduce the voltage drop of the first power signal VDD, effectively improve the uniformity of the first power signal VDD in the display panel, effectively improve the display uniformity, and improve the display quality and display performance.

[0802] In some examples, the first power line 52 is provided with a first power connection block 52-1 on a side away from the first reference signal connection line 53. One end of the first power connection block 52-1 is connected with the first power line 52, and the other end of the first power connection block 52-1 extends towards a side close to an adjacent second pixel circuit. The first power connection block 52-1 can have a shape of a rectangle, and the orthographic projection of the first power connection block 52-1 on the substrate layer can cover the orthographic projection of the fourth connection electrode 44 on the substrate layer. In some examples, the first power line 52 and the first power connection block 52-1 can be an integrated structure.

[0803] In some examples, the orthographic projection of the first power line 52 on the substrate layer covers the orthographic projection of the first connection electrode 41 on the substrate layer. Since the first connection electrode 41 is used as the first node N1 in the pixel circuit, the first power line 52 for transmitting a constant voltage can effectively shield the influence of other signals in the pixel circuit on the first node N1, so that the potential of the first node N1 in the pixel circuit is not affected by other signals (such as data voltage jump), and the display effect is improved.

[0804] In some examples, the first power line 52 is provided with a second power connection block 52-2 on one side of the first reference signal connection line 53. The second power connection block 52-2 can be located on the side opposite to the first power connection block 52-1 in the second direction Y. One end of the second power connection block 52-2 is connected to the first power line 52, and the other end of the second power connection block 52-2 extends in the direction of the side where the first reference signal connection line 53 is located. The second power connection block 52-2 can be substantially rectangular in shape, and the orthographic projection of the second power connection block 52-2 on the substrate layer can at least partially overlap the orthographic projection of the fourth electrode plate 74 on the substrate layer. The second power connection block 52-2 can be connected to the first power connection block 66-1 through the thirty-fifth via hole V35, so as to connect the first power line 52 and the first power connection line 66. The size of the second power connection block 52-2 in the second direction Y can be smaller than the size of the first power connection block 52-1 in the second direction Y, and the size of the second power connection block 52-2 in the first direction Y can be substantially the same as the size of the first power connection block 52-1 in the first direction X. The present embodiment is not limited in this regard.

[0805] In some examples, the orthographic projection of the first power line 52 on the substrate layer can at least partially overlap the orthographic projection of the third connection electrode 43 on the substrate layer. For example, the orthographic projection of the first power line 52 on the substrate layer can cover the orthographic projection of the third connection electrode 43 on the substrate layer. Since the third connection electrode 43 serves as the second node N2 in the pixel circuit, the first power line 52 transmitting a constant voltage can effectively shield the influence of other signals in the pixel circuit on the second node N2, avoiding the influence of other signals on the potential of the second node N2 in the pixel circuit, and improving the display effect.

[0806] In some examples, the orthographic projection of the first power line 52 on the substrate layer can cover the orthographic projection of the first region 141 of the fourth active layer 14 of the fourth transistor T4 on the substrate layer. The orthographic projection of the first power line 52 on the substrate layer can cover the orthographic projection of the connection position between the first region 141 of the fourth active layer 14 of the fourth transistor T4 and the first initial signal line 32 on the substrate layer. By shielding the first region 141 of the fourth active layer 14 of the fourth transistor T4 connected to the first initial signal line 32 with the first power line 52, the influence of other signals on the first region 141 of the fourth active layer 14 of the fourth transistor T4 receiving the first initial signal Vinit1 can be avoided, thereby ensuring the transmission accuracy of the first initial signal Vinit1 and ensuring the initialization effect.

[0807] In some examples, the first power line 52 can be designed to have a non-equal width. The first power line 52 designed to have a non-equal width not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power line 52 and the data signal line 51.

[0808] In some examples, the first reference signal connecting line 53 can have a shape of a straight line with a main body portion extending along the second direction Y, and the first reference signal connecting line 53 can be connected with the first reference connecting block 34-1 through the thirty-fourth via hole V34. Since the first reference connecting block 34-1 is connected with the first reference signal line 34, the first reference signal line 34 with the main body portion extending along the first direction X and the first reference signal connecting line 53 with the main body portion extending along the second direction Y are connected with each other, so that the first reference signal line 34 and the first reference signal connecting line 53 form a mesh structure for transmitting the first reference signal Vref1 on the display panel, which can not only effectively reduce the resistance of the first reference signal line 34 and reduce the voltage drop of the first reference signal 34, but also effectively improve the uniformity of the first reference signal Vref1 in the display panel, effectively improve the display uniformity, and improve the display quality and display performance.

[0809] In some examples, the anode connecting electrode 55 can have a shape of a rectangle. The anode connecting electrode 55 can be located between the first power supply line 52 and the data signal line 51. The anode connecting electrode 55 can be connected with the fifth connecting electrode 45 through the thirty-third via hole V33. Since the fifth connecting electrode 45 is connected with the second region 162 of the sixth active layer 16 (also the second region 182 of the eighth active layer 18) through the sixth via hole V6, the anode connecting electrode 55 is connected with the second electrode of the sixth transistor T6 and the second electrode of the eighth transistor T8. In some examples, the anode connecting electrode 55 can be configured to be connected with the anode of the subsequently formed light emitting device, so that the pixel circuit can drive the light emitting device.

[0810] In some examples, the anode connecting electrode 55 can have a shape of a rectangle. The anode connecting electrode 55 can be located between the first power supply line 52 and the data signal line 51. The anode connecting electrode 55 can be connected with the fifth connecting electrode 45 through the thirty-third via hole V33. Since the fifth connecting electrode 45 is connected with the second region 162 of the sixth active layer 16 (also the second region 182 of the eighth active layer 18) through the sixth via hole V6, the anode connecting electrode 55 is connected with the second electrode of the sixth transistor T6 and the second electrode of the eighth transistor T8. In some examples, the anode connecting electrode 55 can be configured to be connected with the anode of the subsequently formed light emitting device, so that the pixel circuit can drive the light emitting device.

[0811] In some examples, the repair line 39 is disposed on the second conductive layer, and the anode connecting electrode 55 is disposed on the fourth conductive layer, which can facilitate the layout. The repair line 39 is disposed close to the anode connecting electrode 55, which can facilitate the repair of the anode of the light emitting device by the repair line 39.

[0812] In some examples, the at least one pixel circuit can further include a second initial signal connection line 54. The second initial signal connection line 54 can have a shape of a straight line with a main body extending along the second direction Y, and the second initial signal connection line 54 can be connected to the second initial connection block 82-1 through a thirty-sixth via hole V36. Since the second initial connection block 82-1 is connected to the second initial signal line 82, the second initial signal line 82 with the main body extending along the first direction X and the second initial signal connection line 54 with the main body extending along the second direction Y are connected to each other, so that the second initial signal connection line 54 and the second initial signal line 82 form a mesh structure on the display panel for transmitting the second initial signal Vinit2. This can effectively reduce the resistance of the second initial signal line 82, reduce the voltage drop of the second initial signal Vinit2, effectively improve the uniformity of the second initial signal Vinit2 in the display panel, effectively improve the display uniformity, and improve the display quality and display performance.

[0813] In some examples, the signal lines of the fourth conductive layer are vertical wires extending along the second direction Y, and the signal lines of the first conductive layer, the third conductive layer, and the second conductive layer are horizontal wires extending along the first direction X, for example, the second reference signal line 35, the first enable signal line 31, the first initial signal line 32, the second enable signal line 33, the fourth gate signal line 64, the first gate signal line 61, the second gate signal line 62, the first reference signal line 34, the third gate signal line 63, the fifth gate signal line 65, and the second initial signal line 82 are horizontal wires.

[0814] In some examples, the first power connection line 66 of the third conductive layer can be arranged in each row of pixel circuits, and the first power line 52 of the fourth conductive layer can be arranged in each column of pixel circuits. The plurality of first power lines 52 can be connected to the plurality of first power connection lines 66, respectively, to form a mesh structure for transmitting the first power signal VDD.

[0815] In some examples, the first reference signal line 34 of the third conductive layer can be arranged in each row of pixel circuits, and the first reference signal connection line 53 of the fourth conductive layer can be arranged in each column of pixel circuits. The plurality of first reference signal lines 34 can be connected to the plurality of first reference signal connection lines 53, respectively, to form a mesh structure for transmitting the first reference signal Vref1.

[0816] In some examples, the second initial signal line 82 of the third conductive layer can be arranged in each row of pixel circuits, and the second initial signal connection line 54 of the fourth conductive layer can be arranged in every two columns of pixel circuits. The plurality of second initial signal lines 82 are respectively connected to the plurality of second initial signal connection lines 54, and a mesh structure for transmitting the second initial signal Vinit2 is formed.

[0817] In some examples, the first power signal line 52 of the fourth conductive layer can be arranged in each column of pixel circuits, and the data signal line 51 of the fourth conductive layer can be arranged in each column of pixel circuits. The first initial signal line 32 of the second conductive layer can be arranged in every six rows of pixel circuits. The fourth conductive layer can further be provided with a second power line for transmitting a second power signal VSS. The second power line can be arranged in a non-display area, for example, the second power line can be electrically connected to the cathode through a hole punched in the frame of the display panel.

[0818] In some examples, the third thirty-sixth via V36 has no overlap with the orthographic projection of the second reference signal line 35 on the substrate layer, and the orthographic projection of the second initial signal line 82 on the substrate layer has no overlap with the orthographic projection of the second reference signal line 35 on the substrate layer. The second initial signal line 82 is located in the third conductive layer, and the second reference signal line 35 is located in the second conductive layer, which can avoid short circuit between the second reference signal line 35 and the second initial signal line 82.

[0819] In some examples, the first reference signal Vref1 can be connected through the vertical first reference signal connection line 53, the horizontal first reference signal line 34, and the active layer connected through the ninth via V9. The connection through three layers of wiring can reduce the resistance of the wiring. According to the foregoing current formula: It can be known that the light emitting current of the light emitting device EL is only related to the first reference signal Vref1 and the data signal Data. Therefore, reducing the resistance of the wiring for transmitting the first reference signal Vref1 can increase the current value, which is beneficial to reducing power consumption.

[0820] In some examples, the wiring for transmitting the first power signal VDD includes the vertical first power line 52, the horizontal first power connection line 66, and the fourth connection electrode 44, which are distributed in three different conductive layers. The resistance can be reduced, and the signal voltage drop can be reduced.

[0821] In some examples, the wiring for transmitting the second initial signal Vinit2 includes the horizontal second initial signal line 82, the vertical second initial signal connection line 54, and the eighth active layer 18, which are distributed in three film layers. In the fourth conductive layer, a vertical second initial signal connection line 54 can be arranged in every six columns of pixel circuits. The resistance can be reduced, and the signal voltage drop can be reduced.

[0822] In some examples, the fourth conductive layer can be provided with a vertical second reference signal connection line for each 6 columns of pixel circuits, and the second reference signal Vref2 can be transmitted by the horizontal second reference signal line 35 and the vertical second reference signal connection line, which are distributed in two different conductive layers. The resistance can be reduced, and the signal voltage drop can be reduced.

[0823] In some examples, since the secon...

Claims

A display panel comprises: a substrate layer; a driving backplane disposed on one side of the substrate layer, the driving backplane comprising a pixel circuit, the driving backplane comprising a plurality of conductive layers; a light emitting device layer disposed on a side of the driving backplane away from the substrate layer, the light emitting device layer comprising a plurality of light emitting devices, the light emitting device comprising an anode, the anode being electrically connected with the pixel circuit; the light emitting device comprises a first light emitting device, a second light emitting device and a third light emitting device, the first light emitting device, the second light emitting device and the third light emitting device are used to emit light of different colors; the anode of the first light emitting device comprises at least two first anode sub-blocks, the orthographic projection of the first anode sub-blocks on the substrate layer overlaps with the orthographic projection of at least four conductive layers on the substrate layer. The display panel according to claim 1, wherein the anode of the first light emitting device comprises a first connection part, at least two first anode sub-blocks are electrically connected through the first connection part. The display panel according to claim 2, wherein the anode of the first light emitting device comprises at least three first anode sub-blocks, there is no first connection part directly connected between two first anode sub-blocks in the first light emitting device. The display panel according to claim 2, wherein the first anode sub-blocks in the first light emitting device are sequentially connected end to end through the first connection part. The display panel according to claim 3, wherein the anode of the first light emitting device comprises N first anode sub-blocks, N first anode sub-blocks are connected with each other through M first connection parts, wherein N and M are natural numbers greater than or equal to 3, 0≤M-N≤2. The display panel according to claim 2, wherein the first connection part comprises a first sub-connection part and a second sub-connection part, the first sub-connection part connects two adjacent first anode sub-blocks in a first direction, the second sub-connection part connects two adjacent first anode sub-blocks in a second direction, the first direction intersects with the second direction; the number of the first sub-connection parts is less than or equal to the number of the second sub-connection parts. The display panel according to claim 2, wherein the shapes and areas of the orthographic projections of at least two first anode sub-blocks on the substrate layer are the same. The display panel according to claim 6, wherein in the first light emitting device, two adjacent first anode sub-blocks in the first direction are symmetrical about the first sub-connection part; and / or in the first light emitting device, two adjacent first anode sub-blocks in the second direction are symmetrical about the second sub-connection part. The display panel according to claim 1, wherein the first light emitting device and the second light emitting device are arranged alternately in a first direction, the first light emitting device and the third light emitting device are arranged alternately in the first direction; the second light emitting device and the third light emitting device are arranged alternately in a second direction, the first light emitting device is arranged in the second direction; The first direction intersects the second direction. The display panel of claim 9, wherein, The first anode sub-blocks of two first light emitting devices adjacent in the second direction are mirror set in shape about the first direction. The display panel of claim 2, wherein, The first anode sub-block is electrically connected with the pixel circuit through a first anode via; The first connecting part is arranged in a spacing region between the two connected first anode sub-blocks, and a projection of the first anode via on the substrate layer falls within a projection of the first connecting part on the substrate layer. The display panel of claim 2, wherein, The anode of the second light emitting device comprises a second anode block, and the anode of the third light emitting device comprises a third anode block; The first anode sub-block is electrically connected with the pixel circuit through a first anode via, the second anode block is electrically connected with the pixel circuit through a second anode via, and the third anode block is electrically connected with the pixel circuit through a third anode via; The first anode via, the second anode via, and the third anode via are arranged in sequence in a first direction, and the second anode via is arranged between the first anode via and the third anode via. The display panel of claim 12, wherein, The second anode via is located between two first anode sub-blocks adjacent in a second direction, and the first direction intersects the second direction. The display panel of claim 12, wherein, The first anode via and the second anode via are separated by the first anode sub-block adjacent in the first direction, and the first anode via and the third anode via are separated by the first anode sub-block. The display panel of claim 14, wherein, A projection of the first anode via on the substrate layer at least partially overlaps a projection of the first anode sub-block on the substrate. The display panel of claim 12, wherein, The anode of the first light emitting device comprises a first anode extension part connected with the first anode sub-block, and a projection of the first anode via on the substrate layer falls within a projection of the first anode extension part on the substrate layer; and / or, The anode of the second light emitting device comprises a second anode extension part connected with the second anode block, and a projection of the second anode via on the substrate layer falls within a projection of the second anode extension part on the substrate layer; and / or, The anode of the third light emitting device comprises a third anode extension part connected with the third anode block, and a projection of the third anode via on the substrate layer falls within a projection of the third anode extension part on the substrate layer. The display panel of claim 16, wherein, The second anode extension part is located in a spacing region between the first anode sub-block and the second anode block; and / or, The third anode overhang is located in a spacing region between the second anode block and the third anode block; and / or, A length extension direction of the second anode overhang intersects the first direction and the second direction. The display panel of claim 16, wherein, Part of the second anode overhang is located in a spacing region between the first anode sub-blocks adjacent in the second direction. The display panel of claim 18, wherein, The second anode overhang comprises an anode overhang segment and an anode via segment, the anode overhang segment is connected between the anode via segment and the second anode block, the anode via segment is electrically connected with the pixel circuit through the second anode via; A projection of the second anode via on the substrate layer falls within a projection of the anode via segment on the substrate layer, the anode overhang segment is located in a spacing region between the first anode sub-blocks adjacent in the first direction and the second anode block, the anode via segment is located in a spacing region between two first anode sub-blocks adjacent in the second direction. The display panel of claim 19, wherein, A distance between the second anode block and the first anode sub-block adjacent is less than a length of the anode overhang segment; And / or, A length extension direction of the anode overhang segment intersects the first direction and the second direction; And / or, A shape of the projection of the anode via segment on the substrate layer comprises a rectangle. The display panel of claim 16, wherein, A shape of the projection of the first anode overhang on the substrate layer comprises a rectangle; and / or, A shape of the projection of the second anode overhang on the substrate layer comprises a rectangle; and / or, A shape of the projection of the third anode overhang on the substrate layer comprises a rectangle; and / or, A shape of the projection of the first anode sub-block on the substrate layer comprises a rectangle; and / or, A shape of the projection of the first connection on the substrate layer comprises a rectangle; and / or, A shape of the projection of the second anode block on the substrate layer comprises a rectangle; and / or, A shape of the projection of the third anode block on the substrate layer comprises a rectangle. The display panel of any of claims 2-21, wherein, The anode of the second light emitting device comprises a second anode block, the anode of the third light emitting device comprises a third anode block; The drive backplane comprises a data signal line, the data signal line extends along the second direction, the data signal line is electrically connected with the pixel circuit; A projection of the data signal line on the substrate layer does not overlap with a projection of the first anode sub-block on the substrate layer; And / or, A projection of the data signal line on the substrate layer does not overlap with a projection of the second anode block on the substrate layer; And / or, A projection of the data signal line on the substrate layer does not overlap with a projection of the third anode block on the substrate layer. The display panel of claim 22, wherein in a case where the first light emitting device includes a first connection portion, a part of the data signal line has an overlap with a projection of one of the first connection portions on the substrate layer; and / or, a part of the data signal line has a projection on the substrate layer located in a spacing region between adjacent first anode sub-pixels in the first light emitting device; and / or, in a case where the anode of the second light emitting device includes a second anode protruding portion, a part of the data signal line has an overlap with a projection of the second anode protruding portion on the substrate layer. The display panel of claim 22, wherein the driving backplane includes a reference signal connection line and a first power supply line, the reference signal connection line and the first power supply line both extend along the second direction, the reference signal connection line is located between the data signal line and the first power supply line, the reference signal connection line and the first power supply line are both electrically connected with the pixel circuit, and the second direction intersects the first direction; the reference signal connection line includes a first reference connection segment and a second reference connection segment, the first reference connection segment and the second reference connection segment are connected in the second direction, at least a part of the first reference connection segment has a size in the first direction smaller than a size of the second reference connection segment in the first direction, a projection of the first reference connection segment on the substrate layer has no overlap with a projection of the first anode sub-pixel on the substrate layer, and a projection of the second reference connection segment on the substrate layer has an overlap with a projection of at least one of the first anode sub-pixels on the substrate layer; and / or, the first power supply line includes a first power supply connection segment and a second power supply connection segment, the first power supply connection segment and the second power supply connection segment are connected in the second direction, at least a part of the first power supply connection segment has a size in the first direction smaller than a size of the second power supply connection segment in the first direction, a projection of the first power supply connection segment on the substrate layer has no overlap with a projection of the first anode sub-pixel on the substrate layer, and a projection of the second power supply connection segment on the substrate layer has an overlap with a projection of at least one of the first anode sub-pixels on the substrate layer; and / or, a projection of the first power supply connection segment on the substrate layer has no overlap with a projection of the second anode sub-pixel on the substrate layer, and a projection of the second power supply connection segment on the substrate layer has an overlap with a projection of the second anode sub-pixel on the substrate layer; and / or, a projection of the first power supply connection segment on the substrate layer has no overlap with a projection of the third anode sub-pixel on the substrate layer, and a projection of the second power supply connection segment on the substrate layer has an overlap with a projection of the third anode sub-pixel on the substrate layer. The display panel of claim 24, wherein ​ A projection of the reference signal connection line on the substrate layer does not overlap with a projection of the second anode block on the substrate layer; and / or, A projection of the reference signal connection line on the substrate layer does not overlap with a projection of the third anode block on the substrate layer. The display panel according to claim 24, wherein Part of the reference signal connection lines are located in the interval region between the adjacent first anode sub-block and the second anode block; and / or, Part of the reference signal connection lines are located in the interval region between the adjacent first anode sub-block and the third anode block. The display panel according to claim 24, wherein The anode of the second light-emitting device comprises a second anode extension, the second anode block is connected with the second anode extension, the second anode extension is electrically connected with the pixel circuit through a second anode via, and a projection of the second anode via on the substrate layer falls within a projection of one end of the second anode extension away from the second anode block on the substrate layer; Part of the projection of the reference signal connection line on the substrate layer overlaps with the projection of the second anode extension on the substrate layer. The display panel according to claim 24, wherein A shape of the projection of the second reference connection segment on the substrate layer comprises a rectangle; and / or, A shape of the projection of the second power supply connection segment on the substrate layer comprises a rectangle. The display panel according to claim 24, wherein The light-emitting device layer comprises a pixel defining layer and a light-emitting layer, the pixel defining layer comprises a plurality of pixel openings, and the light-emitting layer is arranged in the pixel openings, and a projection of the pixel opening on the substrate layer falls within a projection of the anode on the substrate layer; In the case that the projection of the second reference connection segment on the substrate layer overlaps with the projection of the first anode sub-block on the substrate layer, and the projection of the second power supply connection segment on the substrate layer overlaps with the projection of the first anode sub-block on the substrate layer, an overlapping area of the projection of the second reference connection segment on the substrate layer and the projection of the first anode sub-block on the substrate layer is a first area, an overlapping area of the projection of the second power supply connection segment on the substrate layer and the projection of the first anode sub-block on the substrate layer is a second area, an area of the projection of the first anode sub-block on the substrate layer is a third area, an overlapping area of a projection of the pixel opening corresponding to the first anode sub-block on the substrate layer and the projection of the second reference connection segment on the substrate layer is a fourth area, an overlapping area of the projection of the pixel opening corresponding to the first anode sub-block on the substrate layer and the projection of the second power supply connection segment on the substrate layer is a fifth area, and an area of the projection of the pixel opening corresponding to the first anode sub-block on the substrate layer is a sixth area; A ratio of the first area to the third area is greater than or equal to 80%, and / or, a ratio of the second area to the third area is greater than or equal to 80%; and / or, a ratio of the fourth area to the sixth area is greater than or equal to 80%, and / or, a ratio of the fifth area to the sixth area is greater than or equal to 80%; and / or, a ratio of a sum of the first area and the second area to the third area is greater than or equal to 80%; and / or, a ratio of a sum of the fourth area and the fifth area to the sixth area is greater than or equal to 80%. The display panel of claim 22, wherein the driving backplane comprises a reference signal connection line and a first power line, the reference signal connection line and the first power line both extend along the second direction, the reference signal connection line is located between the data signal line and the first power line, and the reference signal connection line and the first power line are both electrically connected with the pixel circuit; a projection of the reference signal connection line on the substrate layer overlaps with a projection of the first anode sub-block on the substrate layer, and a projection of the first power line on the substrate layer overlaps with a projection of the first anode sub-block on the substrate layer; a boundary of the projection of the first anode sub-block on the substrate layer partially overlaps with a boundary of the projection of the first power line on the substrate layer, wherein the overlapping boundary extends along the second direction; and / or, a boundary of the projection of the first anode sub-block on the substrate layer partially overlaps with a boundary of the projection of the reference signal connection line on the substrate layer, wherein the overlapping boundary extends along the second direction. The display panel of claim 22, wherein the driving backplane comprises an initial signal connection line and an initial signal line, the initial signal connection line extends along the second direction, the initial signal line extends along a first direction, the initial signal connection line is electrically connected with the initial signal line, the initial signal line is electrically connected with the pixel circuit, and the first direction intersects with the second direction; at least part of the projection of the initial signal connection line on the substrate layer does not overlap with the projection of the first anode sub-block on the substrate layer. The display panel of claim 31, wherein part of the initial signal connection line is located in a spacing region between the first anode sub-block and the third anode block; and / or, part of the initial signal connection line is located in a spacing region between adjacent first anode sub-blocks. The display panel of any of claims 1 to 21, wherein the driving backplane comprises a gate signal line, the gate signal line extends along a first direction; the second light emitting device comprises a second anode block, and the third light emitting device comprises a third anode block; at least part of the projection of the gate signal line on the substrate layer does not overlap with the projection of the first anode sub-block on the substrate layer; and / or, the second anode block comprises a second anode opening, and part of the projection of the gate signal line on the substrate layer overlaps with the projection of the second anode opening on the substrate layer; and / or, The third anode block comprises a third anode opening, and a projection of the gate signal line on the substrate layer partially overlaps a projection of the third anode opening on the substrate layer. The display panel according to claim 33, wherein The first anode sub-block comprises a first anode opening, the anode of the second light emitting device comprises a second anode extension, the second anode extension is connected with the second anode block, and the second anode extension is electrically connected with the pixel circuit through a second anode via hole; A projection of the first anode opening on the substrate layer covers a projection of the second anode via hole on the substrate layer. The display panel according to claim 33, wherein A size of the second anode opening in the first direction is greater than or equal to 2 / 3 of a maximum size of the second anode block in the first direction; and / or A size of the third anode opening in the first direction is greater than or equal to 2 / 3 of a maximum size of the third anode block in the first direction. The display panel according to claim 33, wherein A plurality of the gate signal lines are arranged in the same layer. The display panel according to claim 33, wherein The gate signal lines comprise a first gate signal line, a second gate signal line, a third gate signal line, a fourth gate signal line and a fifth gate signal line, the first gate signal line, the second gate signal line, the third gate signal line, the fourth gate signal line and the fifth gate signal line are used to electrically connect gates of different transistors in the pixel circuit respectively, and the second gate signal line and the fifth gate signal line are used to transmit the same gate signal; At least two of the first gate signal line, the second gate signal line, the third gate signal line, the fourth gate signal line and the fifth gate signal line are arranged in different conductive layers, and the gate signal lines are arranged in two conductive layers respectively. The display panel according to claim 37, wherein The first gate signal line, the second gate signal line, the third gate signal line and the fifth gate signal line are arranged in the same conductive layer, and the fourth gate signal line and the first gate signal line are arranged in different conductive layers respectively. The display panel according to claim 37, wherein A projection of the fourth gate signal line on the substrate layer partially overlaps a projection of the first anode sub-block on the substrate layer; and / or A projection of the fourth gate signal line on the substrate layer partially overlaps a projection of the second anode block on the substrate layer; and / or A projection of the fourth gate signal line on the substrate layer partially overlaps a projection of the third anode block on the substrate layer. The display panel according to claim 37, wherein The anode of the first light emitting device comprises four first anode sub-blocks, which are a first sub-block, a second sub-block, a third sub-block and a fourth sub-block respectively; The first sub-block and the second sub-block are arranged along the first direction, the first sub-block and the third sub-block are arranged along a second direction, the third sub-block and the fourth sub-block are arranged along the first direction, and the second sub-block and the fourth sub-block are arranged along the second direction; The first gate signal line is located in the interval region between the first sub-block and the third sub-block, and / or the first gate signal line is located in the interval region between the second sub-block and the fourth sub-block. And / or, The second gate signal line is located in the interval region between the first sub-block and the third sub-block, and / or the second gate signal line is located in the interval region between the second sub-block and the fourth sub-block. According to claim 40, wherein In the case where the first light emitting device comprises a first connecting part, the first connecting part comprises a first sub-connecting part and a second sub-connecting part; The first sub-block and the second sub-block are connected through the first sub-connecting part, the first sub-block and the third sub-block are connected through the second sub-connecting part, the first connecting part is not arranged between the third sub-block and the fourth sub-block, and the second sub-block and the fourth sub-block are connected through the second sub-connecting part; The first gate signal line has an overlapping projection on the substrate layer with the second sub-connecting part; and / or, The second gate signal line has an overlapping projection on the substrate layer with the second sub-connecting part. According to claim 37, wherein The first gate signal line has an overlapping projection on the substrate layer with the third anode opening; and / or, The second gate signal line has an overlapping projection on the substrate layer with the third anode opening; And / or, The fifth gate signal line has an overlapping projection on the substrate layer with the second anode opening; And / or, The third gate signal line has an overlapping projection on the substrate layer with the second anode opening. According to claim 37, wherein The second anode block comprises a second connecting part and a plurality of second anode sub-blocks, at least two of the second anode sub-blocks are connected through the second connecting part, the size of the second anode sub-block in a first direction is greater than the size of the second connecting part in the first direction, and part of the signal lines of the driving backplane are arranged in the interval region between adjacent two second anode sub-blocks; and / or, The third anode block comprises a third connecting part and a plurality of third anode sub-blocks, at least two of the third anode sub-blocks are connected through the third connecting part, the size of the third anode sub-block in a first direction is greater than the size of the third connecting part in the first direction, and part of the signal lines of the driving backplane are arranged in the interval region between adjacent two third anode sub-blocks. According to claim 43, wherein A part of the projection of the gate signal line on the substrate layer overlaps with the projection of the second connecting part on the substrate layer. The second connecting part is connected to a main body part between two ends of the second anode sub-block in the first direction, and at least two second anode openings are formed between at least two second anode sub-blocks. And / or A part of the projection of the gate signal line on the substrate layer overlaps with the projection of the third connecting part on the substrate layer. According to claim 43, wherein The second anode sub-block is in a rectangular shape in the projection on the substrate layer; and / or The third anode sub-block is in a rectangular shape in the projection on the substrate layer; and / or The second connecting part is in a rectangular shape in the projection on the substrate layer; and / or The third connecting part is in a rectangular shape in the projection on the substrate layer; and / or The second anode opening is in a rectangular shape in the projection on the substrate layer; and / or The third anode opening is in a rectangular shape in the projection on the substrate layer. According to claim 37, wherein The driving backplane comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, which are sequentially stacked on one side of the substrate layer; The first conductive layer is provided with a plurality of block electrodes and the fourth gate signal line, and the block electrodes include the gate of a transistor and the plate of a capacitor in the pixel circuit; The second conductive layer is provided with a repair line, which extends along the first direction; The third conductive layer is provided with the first gate signal line, the second gate signal line, the third gate signal line and the fifth gate signal line; The fourth conductive layer is provided with an anode connecting electrode, which is electrically connected with the anode of the light emitting device. According to claim 47, wherein The projection of the anode connecting electrode on the substrate layer overlaps with the projection of the repair line on the substrate layer. According to claim 48, wherein The first conductive layer comprises a data signal line, which extends along a second direction perpendicular to the first direction. According to claim 47, wherein The driving backplane comprises an active layer, which is arranged between the substrate layer and the first conductive layer; At least four layers of insulating films are arranged between the active layer and the first conductive layer. According to claim 49, wherein The first conductive layer comprises a Ti-Al-Ti stack structure. According to claim 37, wherein ​ ​ ​ ​ The driving back plate comprises a data signal line, a first power supply line, a first enable signal line, a second enable signal line, a first initial signal line, a second initial signal line, a first reference signal line and a second reference signal line; The pixel circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor and a second capacitor; The first electrode of the first transistor is electrically connected with the data signal line, the second electrode of the first transistor is electrically connected with a second node, and the gate of the first transistor is electrically connected with the first gate signal line; One end of the second capacitor is electrically connected with the first power supply line, the other end of the second capacitor is electrically connected with the second node, one end of the first capacitor is electrically connected with the second node, and the other end of the first capacitor is electrically connected with a first node; The first electrode of the second transistor is electrically connected with the first node, the gate of the second transistor is electrically connected with the fifth gate signal line, and the second electrode of the second transistor is electrically connected with a fourth node; The first electrode of the third transistor is electrically connected with a third node, the second electrode of the third transistor is electrically connected with the fourth node, and the gate of the third transistor is electrically connected with the first node; The first electrode of the fifth transistor is electrically connected with the first power supply line, the second electrode of the fifth transistor is electrically connected with the third node, and the gate of the fifth transistor is electrically connected with the first enable signal line; The gate of the ninth transistor is electrically connected with the fourth gate signal line, the first electrode of the ninth transistor is electrically connected with the second reference signal line, and the second electrode of the ninth transistor is electrically connected with the third node; The first electrode of the sixth transistor is electrically connected with the fourth node, the second electrode of the sixth transistor is electrically connected with a fifth node, and the gate of the sixth transistor is electrically connected with the second enable signal line; The second electrode of the eighth transistor is electrically connected with the fifth node, the first electrode of the eighth transistor is electrically connected with the second initial signal line, and the gate of the eighth transistor is electrically connected with the fourth gate signal line; The first electrode of the fourth transistor is electrically connected with the first node, the second electrode of the fourth transistor is electrically connected with the first initial signal line, and the gate of the fourth transistor is electrically connected with the third gate signal line; The first electrode of the seventh transistor is electrically connected with the second node, the second electrode of the seventh transistor is electrically connected with the first reference signal line, and the gate of the seventh transistor is electrically connected with the second gate signal line; The fifth node is used for electrically connecting the light emitting device. The display panel according to claim 52, wherein At least one of the first transistor, the second transistor, the fourth transistor and the seventh transistor comprises a double-gate structure transistor. The display panel according to claim 52, wherein The pixel circuit includes a first pixel circuit, a second pixel circuit and a third pixel circuit, the first pixel circuit is electrically connected with the first light emitting device, the second pixel circuit is electrically connected with the second light emitting device, and the third pixel circuit is electrically connected with the third light emitting device. The channel width-length ratio of the third transistor of the first pixel circuit is greater than the channel width-length ratio of the third transistor of the second pixel circuit, and the channel width-length ratio of the third transistor of the first pixel circuit is greater than the channel width-length ratio of the third transistor of the third pixel circuit. The display panel according to claim 52, wherein The driving backplane includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer; The second reference signal line, the first enable signal line, the second enable signal line and the first initial signal line are all arranged on the second conductive layer; and / or The first reference signal line and the second initial signal line are both arranged on the third conductive layer; and / or The first power supply line, the data signal line, the reference signal connection line and the initial signal connection line are all arranged on the fourth conductive layer. A display panel comprises: a substrate layer; a driving backplane arranged on one side of the substrate layer, the driving backplane comprising a pixel circuit, a reference signal connection line and a first power supply line, the reference signal connection line and the first power supply line both being electrically connected with the pixel circuit, the reference signal connection line and the first power supply line both extending along a second direction intersecting a first direction; a light emitting device layer arranged on a side of the driving backplane away from the substrate layer, the light emitting device layer comprising a plurality of light emitting devices, the light emitting device comprising an anode, the anode being electrically connected with the pixel circuit; the reference signal connection line comprises a first reference connection segment and a second reference connection segment, the first reference connection segment being connected with the second reference connection segment in the second direction, at least part of the first reference connection segment in the first direction having a size smaller than that of the second reference connection segment in the first direction, a projection of the first reference connection segment on the substrate layer having no overlap with a projection of the anode on the substrate layer, and a projection of the second reference connection segment on the substrate layer having overlap with a projection of at least one of the anodes on the substrate layer; and / or the first power supply line comprises a first power supply connection segment and a second power supply connection segment, the first power supply connection segment being connected with the second power supply connection segment in the second direction, at least part of the first power supply connection segment in the first direction having a size smaller than that of the second power supply connection segment in the first direction, a projection of the first power supply connection segment on the substrate layer having no overlap with a projection of the anode on the substrate layer, and a projection of the second power supply connection segment on the substrate layer having overlap with a projection of at least one of the anodes on the substrate layer. The display panel according to claim 56, wherein ​ ​ The light emitting device layer comprises a pixel defining layer and a light emitting layer, the pixel defining layer comprises a plurality of pixel openings, the light emitting layer is arranged in the pixel openings, and a projection of the pixel openings on the substrate layer falls within a projection of the anode on the substrate layer; An overlapping area of the second reference connection segment on the substrate layer and a projection of the anode on the substrate layer is a seventh area, an overlapping area of the second power supply connection segment on the substrate layer and the projection of the anode on the substrate layer is an eighth area, a projection area of the anode on the substrate layer is a ninth area, an overlapping area of a projection of the pixel opening corresponding to the anode on the substrate layer and the second reference connection segment on the substrate layer is a tenth area, an overlapping area of a projection of the pixel opening corresponding to the anode on the substrate layer and the second power supply connection segment on the substrate layer is an eleventh area, and a projection area of the pixel opening corresponding to the anode on the substrate layer is a twelfth area; A ratio of the seventh area to the ninth area is greater than or equal to 80%, and / or a ratio of the tenth area to the twelfth area is greater than or equal to 80%; and / or A ratio of the eighth area to the ninth area is greater than or equal to 80%, and / or a ratio of the eleventh area to the twelfth area is greater than or equal to 80%; and / or A ratio of a sum of the seventh area and the eighth area to the ninth area is greater than or equal to 80%, and / or a ratio of a sum of the tenth area and the eleventh area to the twelfth area is greater than or equal to 80%. The display panel according to claim 56, wherein The light emitting device comprises a first light emitting device, a second light emitting device and a third light emitting device, and the first light emitting device, the second light emitting device and the third light emitting device are used to emit light of different colors; The anode of the first light emitting device comprises a first anode block, the anode of the second light emitting device comprises a second anode block, and the anode of the third light emitting device comprises a third anode block; The second reference connection segment has an overlapping area with a projection of the first anode block on the substrate layer; And / or The second power supply connection segment has an overlapping area with a projection of the first anode block on the substrate layer; and / or The reference signal connection line has no overlapping area with a projection of the second anode block on the substrate layer, and the second power supply connection segment has an overlapping area with the projection of the second anode block on the substrate layer; And / or The reference signal connection line has no overlapping area with a projection of the third anode block on the substrate layer, and the second power supply connection segment has an overlapping area with the projection of the third anode block on the substrate layer. The display panel according to claim 58, wherein The anode of the first light-emitting device comprises a first anode block and a first connecting part, the first anode block comprises a plurality of first anode sub-blocks, and the first anode sub-blocks are connected through the first connecting part; The second reference connecting segment has an intersection with the normal projection of at least one first anode sub-block on the substrate layer; And / or, The second power supply connecting segment has an intersection with the normal projection of at least one first anode sub-block on the substrate layer. The display panel according to claim 59, wherein The first anode block comprises at least three first anode sub-blocks, and there is no first connecting part directly connecting two first anode sub-blocks in the first anode block; or, The first anode sub-blocks in the first anode block are sequentially connected through the first connecting part; And / or, The first connecting part comprises a first sub-connecting part and a second sub-connecting part, the first sub-connecting part connects two adjacent first anode sub-blocks in a first direction, the second sub-connecting part connects two adjacent first anode sub-blocks in a second direction, and the first direction intersects with the second direction; The number of the first sub-connecting part is less than or equal to the number of the second sub-connecting part. The display panel according to claim 59, wherein The first anode sub-block and the pixel circuit are electrically connected through a first anode via, and the second anode block and the pixel circuit are electrically connected through a second anode via; The first connecting part is arranged in a spacing region between two connected first anode sub-blocks, and the normal projection of the first anode via on the substrate layer falls within the normal projection of the first connecting part on the substrate layer; And / or, The second anode via is located in a spacing region between two first anode sub-blocks adjacent in the second direction. The display panel according to any one of claims 59 to 61, wherein The driving back plate comprises a data signal line, the data signal line extends along the second direction, the data signal line is electrically connected with the pixel circuit, and the reference signal connecting line is located in a region between the first power supply line and the data signal line; The data signal line has no intersection with the normal projection of the first anode sub-block on the substrate layer; And / or, The data signal line has no intersection with the normal projection of the second anode block on the substrate layer; And / or, The data signal line has no intersection with the normal projection of the third anode block on the substrate layer. The display panel according to claim 62, wherein The driving back plate comprises an initial signal connecting line and an initial signal line, the initial signal connecting line extends along the second direction, the initial signal line extends along a first direction, the initial signal connecting line is electrically connected with the initial signal line, and the initial signal line is electrically connected with the pixel circuit; ​ At least part of the initial signal connection line has no overlap with the first anode sub-block in the substrate layer. The display panel according to claim 62, wherein, The driving backplane comprises a gate signal line, the gate signal line extends along a first direction; At least part of the gate signal line has no overlap with the first anode block in the substrate layer; And / or, The second anode block comprises a second anode opening, and part of the gate signal line has overlap with the second anode opening in the substrate layer; And / or, The third anode block comprises a third anode opening, and part of the gate signal line has overlap with the third anode opening in the substrate layer; and / or, The first anode block comprises a first anode opening, the anode of the second light emitting device comprises a second anode extension, the second anode extension is connected with the second anode block, and the second anode extension is electrically connected with the pixel circuit through a second anode via hole; The first anode opening covers the second anode via hole in the substrate layer. The display panel according to claim 64, wherein, The gate signal line comprises a first gate signal line, a second gate signal line, a third gate signal line, a fourth gate signal line and a fifth gate signal line, the first gate signal line, the second gate signal line, the third gate signal line, the fourth gate signal line and the fifth gate signal line are used to electrically connect the gate of different transistors in the pixel circuit respectively, and the second gate signal line and the fifth gate signal line are used to transmit the same gate signal; At least two of the first gate signal line, the second gate signal line, the third gate signal line, the fourth gate signal line and the fifth gate signal line are arranged on different conductive layers, and the gate signal line is arranged on two conductive layers respectively. The display panel according to claim 65, wherein, The driving backplane comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are arranged on one side of the substrate layer in sequence; The first conductive layer is provided with a plurality of block electrodes and the fourth gate signal line, the block electrodes comprise the gate of a transistor and the plate of a capacitor in the pixel circuit; The second conductive layer is provided with a repair line, and the repair line extends along the first direction; The third conductive layer is provided with the first gate signal line, the second gate signal line, the third gate signal line and the fifth gate signal line; The fourth conductive layer is provided with an anode connection electrode, and the anode connection electrode is electrically connected with the anode of the light emitting device. The display panel according to claim 65, wherein, ​ The driving back plate comprises a data signal line, a first power supply line, a first enable signal line, a second enable signal line, a first initial signal line, a second initial signal line, a first reference signal line and a second reference signal line; The pixel circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor and a second capacitor; The first electrode of the first transistor is electrically connected with the data signal line, the second electrode of the first transistor is electrically connected with a second node, and the gate of the first transistor is electrically connected with the first gate signal line; One end of the second capacitor is electrically connected with the first power supply line, the other end of the second capacitor is electrically connected with the second node, one end of the first capacitor is electrically connected with the second node, and the other end of the first capacitor is electrically connected with a first node; The first electrode of the second transistor is electrically connected with the first node, the gate of the second transistor is electrically connected with the fifth gate signal line, and the second electrode of the second transistor is electrically connected with a fourth node; The first electrode of the third transistor is electrically connected with a third node, the second electrode of the third transistor is electrically connected with the fourth node, and the gate of the third transistor is electrically connected with the first node; The first electrode of the fifth transistor is electrically connected with the first power supply line, the second electrode of the fifth transistor is electrically connected with the third node, and the gate of the fifth transistor is electrically connected with the first enable signal line; The gate of the ninth transistor is electrically connected with the fourth gate signal line, the first electrode of the ninth transistor is electrically connected with the second reference signal line, and the second electrode of the ninth transistor is electrically connected with the third node; The first electrode of the sixth transistor is electrically connected with the fourth node, the second electrode of the sixth transistor is electrically connected with a fifth node, and the gate of the sixth transistor is electrically connected with the second enable signal line; The second electrode of the eighth transistor is electrically connected with the fifth node, the first electrode of the eighth transistor is electrically connected with the second initial signal line, and the gate of the eighth transistor is electrically connected with the fourth gate signal line; The first electrode of the fourth transistor is electrically connected with the first node, the second electrode of the fourth transistor is electrically connected with the first initial signal line, and the gate of the fourth transistor is electrically connected with the third gate signal line; The first electrode of the seventh transistor is electrically connected with the second node, the second electrode of the seventh transistor is electrically connected with the first reference signal line, and the gate of the seventh transistor is electrically connected with the second gate signal line; The fifth node is used for electrically connecting the light emitting device. A display panel comprises: a substrate layer; a driving back plate arranged on one side of the substrate layer, the driving back plate comprising a pixel circuit; A light emitting device layer is disposed on a side of the driving backplate away from the substrate layer, the light emitting device layer comprising a plurality of light emitting devices, the light emitting device comprising an anode, the anode being electrically connected with the pixel circuit, the light emitting device comprising a first light emitting device, a second light emitting device and a third light emitting device, the first light emitting device, the second light emitting device and the third light emitting device being respectively configured to emit light of different colors; The anode of the first light emitting device comprises a first anode block, the anode of the second light emitting device comprises a second anode block and a second anode extension, the second anode extension being connected with the second anode block, the second anode extension being electrically connected with the pixel circuit through a second anode via, and the third light emitting device comprises a third anode block; The first anode block and the second anode block are arranged in a first direction, the first anode block and the third anode block are alternately arranged in the first direction, the second anode block and the third anode block are arranged in a second direction, the first direction intersects the second direction; The second anode via is located in a spacing region between two adjacent first anode blocks in the second direction. The display panel according to claim 68, wherein The second anode extension comprises an anode extension segment and an anode via segment, the anode extension segment being connected between the anode via segment and the second anode block, and the anode via segment being electrically connected with the pixel circuit through the second anode via; A projection of the second anode via on the substrate layer falls within a projection of the anode via segment on the substrate layer, the anode extension segment is located in a spacing region between the first anode block and the second anode block adjacent in the first direction, and the anode via segment is located in a spacing region between two first anode blocks adjacent in the second direction. The display panel according to claim 68, wherein The first anode block comprises a plurality of first anode sub-blocks, the anode of the first light emitting device comprises a first connection portion, and the first anode sub-blocks are connected through the first connection portion; The second anode via is located in a spacing region between two first anode sub-blocks adjacent in the second direction. The display panel according to any one of claims 68 to 70, wherein The driving backplate comprises a reference signal connection line and a first power supply line, the reference signal connection line and the first power supply line are both electrically connected with the pixel circuit, and the reference signal connection line and the first power supply line both extend along the second direction; ​ The reference signal connecting line comprises a first reference connecting segment and a second reference connecting segment, the first reference connecting segment is connected with the second reference connecting segment in the second direction, at least part of the first reference connecting segment in the first direction is smaller than the size of the second reference connecting segment in the first direction, the orthogonal projection of the first reference connecting segment on the substrate layer does not overlap with the orthogonal projection of the first anode block on the substrate layer, and the orthogonal projection of the second reference connecting segment on the substrate layer overlaps with the orthogonal projection of the first anode block on the substrate layer; and / or, The first power supply line comprises a first power supply connecting segment and a second power supply connecting segment, the first power supply connecting segment is connected with the second power supply connecting segment in the second direction, at least part of the first power supply connecting segment in the first direction is smaller than the size of the second power supply connecting segment in the first direction, the orthogonal projection of the first power supply connecting segment on the substrate layer does not overlap with the orthogonal projection of the first anode block on the substrate layer, and the orthogonal projection of the second power supply connecting segment on the substrate layer overlaps with the orthogonal projection of the first anode block on the substrate layer; and / or, The orthogonal projection of the first power supply connecting segment on the substrate layer does not overlap with the orthogonal projection of the second anode block on the substrate layer, and the orthogonal projection of the second power supply connecting segment on the substrate layer overlaps with the orthogonal projection of the second anode block on the substrate layer; and / or, The orthogonal projection of the first power supply connecting segment on the substrate layer does not overlap with the orthogonal projection of the third anode block on the substrate layer, and the orthogonal projection of the second power supply connecting segment on the substrate layer overlaps with the orthogonal projection of the third anode block on the substrate layer. The display panel according to claim 71, wherein The light-emitting device layer comprises a pixel defining layer and a light-emitting layer, the pixel defining layer comprises a plurality of pixel openings, and the light-emitting layer is arranged in the pixel openings, and the orthogonal projection of the pixel openings on the substrate layer falls within the orthogonal projection of the anode on the substrate layer; In the case where the first anode block comprises a plurality of first anode sub-blocks, the first anode sub-blocks are connected through first connecting parts; The orthogonal projection of the second reference connecting segment on the substrate layer overlaps with the orthogonal projection of at least one first anode sub-block on the substrate layer; And / or, The orthogonal projection of the second power supply connecting segment on the substrate layer overlaps with the orthogonal projection of at least one first anode sub-block on the substrate layer; The overlapping area of the orthogonal projection of the second reference connecting segment on the substrate layer and the orthogonal projection of the first anode sub-block on the substrate layer is a first area, the overlapping area of the orthogonal projection of the second power supply connecting segment on the substrate layer and the orthogonal projection of the first anode sub-block on the substrate layer is a second area, the orthogonal projection area of the first anode sub-block on the substrate layer is a third area, and the first area is smaller than the second area, and the second area is smaller than the third area. A fourth area of an intersection of a normal projection of the pixel opening corresponding to the first anode sub-block on the substrate layer and a normal projection of the second reference connection segment on the substrate layer, a fifth area of an intersection of a normal projection of the pixel opening corresponding to the first anode sub-block on the substrate layer and a normal projection of the second power connection segment on the substrate layer, and a sixth area of a normal projection of the pixel opening corresponding to the first anode sub-block on the substrate layer; a ratio of the first area to the third area is greater than or equal to 80%, and / or a ratio of the second area to the third area is greater than or equal to 80%; and / or a ratio of the fourth area to the sixth area is greater than or equal to 80%, and / or a ratio of the fifth area to the sixth area is greater than or equal to 80%; and / or a ratio of a sum of the first area and the second area to the third area is greater than or equal to 80%; and / or a ratio of a sum of the fourth area and the fifth area to the sixth area is greater than or equal to 80%. The display panel of claim 71, wherein the driving backplate comprises a data signal line, the data signal line extends along the second direction, the data signal line is electrically connected with the pixel circuit, the reference signal connection line is located in a region between the first power line and the data signal line; a normal projection of the data signal line on the substrate layer does not overlap with a normal projection of the first anode block on the substrate layer; and / or a normal projection of the data signal line on the substrate layer does not overlap with a normal projection of the second anode block on the substrate layer; and / or a normal projection of the data signal line on the substrate layer does not overlap with a normal projection of the third anode block on the substrate layer. The display panel of any one of claims 68 to 70, wherein the driving backplate comprises an initial signal connection line and an initial signal line, the initial signal connection line extends along the second direction, the initial signal line extends along the first direction, the initial signal connection line is electrically connected with the initial signal line, and the initial signal line is electrically connected with the pixel circuit; the first anode block comprises a plurality of first anode sub-blocks; part of the initial signal connection line is located in a spacing region between the first anode sub-block and the third anode block; and / or part of the initial signal connection line is located in a spacing region between two adjacent first anode sub-blocks. The display panel of any one of claims 68 to 70, wherein the driving backplate comprises a gate signal line, the gate signal line extends along the first direction; the first anode block comprises a plurality of first anode sub-blocks, and a normal projection of at least part of the gate signal line on the substrate layer does not overlap with a normal projection of the first anode sub-block on the substrate layer; and / or the second anode block comprises a second anode opening, and a normal projection of part of the gate signal line on the substrate layer overlaps with a normal projection of the second anode opening on the substrate layer; and / or The third anode block comprises a third anode opening, and a part of the orthogonal projection of the gate signal line on the substrate layer overlaps with the orthogonal projection of the third anode opening on the substrate layer. The display panel according to claim 75, wherein The gate signal lines comprise a first gate signal line, a second gate signal line, a third gate signal line, a fourth gate signal line and a fifth gate signal line, the first gate signal line, the second gate signal line, the third gate signal line, the fourth gate signal line and the fifth gate signal line are used for electrically connecting the gates of different transistors in the pixel circuit respectively, and the second gate signal line and the fifth gate signal line are used for transmitting the same gate signal; At least two of the first gate signal line, the second gate signal line, the third gate signal line, the fourth gate signal line and the fifth gate signal line are arranged on different conductive layers, and the gate signal lines are arranged on two conductive layers respectively. The display panel according to claim 76, wherein The driving back plate comprises data signal lines, the data signal lines extend along the second direction, and the data signal lines are arranged on the same layer as the fourth gate signal lines; The driving back plate comprises an active layer, the active layer is arranged between the substrate layer and the conductive layer where the data signal lines are located; At least four insulating thin films are arranged between the active layer and the conductive layer where the data signal lines are located. The display panel according to claim 76, wherein The pixel circuit comprises a first pixel circuit, a second pixel circuit and a third pixel circuit, the first pixel circuit is electrically connected with the first light emitting device, the second pixel circuit is electrically connected with the second light emitting device, and the third pixel circuit is electrically connected with the third light emitting device; The channel width-length ratio of the driving transistor of the first pixel circuit is greater than the channel width-length ratio of the driving transistor of the second pixel circuit, and the channel width-length ratio of the driving transistor of the first pixel circuit is greater than the channel width-length ratio of the driving transistor of the third pixel circuit. A display panel comprises: a substrate layer; a driving back plate arranged on one side of the substrate layer, the driving back plate comprising a pixel circuit; a light emitting device layer arranged on a side of the driving back plate away from the substrate layer, the light emitting device layer comprising a plurality of light emitting devices, the light emitting devices comprising anodes, the anodes being electrically connected with the pixel circuit, the light emitting devices comprising a first light emitting device, a second light emitting device and a third light emitting device, the first light emitting device, the second light emitting device and the third light emitting device being used for emitting light of different colors respectively; a second anode block of the second light emitting device comprises a second anode opening, and the orthogonal projection of the second anode opening on the substrate layer overlaps with the orthogonal projection of part of the signal lines of the driving back plate on the substrate layer; and / or a third anode block of the third light emitting device comprises a third anode opening, and the orthogonal projection of the third anode opening on the substrate layer overlaps with the orthogonal projection of part of the signal lines of the driving back plate on the substrate layer. ​ The display panel of claim 79, wherein, the first light emitting device comprises a first anode block, the first anode block comprises a first anode opening, the anode of the second light emitting device comprises a second anode protrusion, the second anode protrusion is connected with the second anode block, the second anode protrusion is electrically connected with the pixel circuit through a second anode via hole; a projection of the first anode opening on the substrate layer covers a projection of the second anode via hole on the substrate layer. The display panel of claim 80, wherein, the first anode block comprises a plurality of first anode sub-blocks, the first anode sub-blocks comprise the first anode opening; a projection of part of the second anode protrusion on the substrate layer falls within a projection of the first anode opening on the substrate layer. The display panel of claim 80, wherein, the second anode block comprises a plurality of second anode sub-blocks, the anode of the second light emitting device comprises a second connection part, at least two of the second anode sub-blocks are connected through the second connection part, a size of the second anode sub-block in a first direction is greater than a size of the second connection part in the first direction, part of the signal lines of the drive backplate are arranged in a spacing region between two adjacent second anode sub-blocks; and / or, the third anode block comprises a plurality of third anode sub-blocks, the anode of the third light emitting device comprises a third connection part, at least two of the third anode sub-blocks are connected through the third connection part, a size of the third anode sub-block in a first direction is greater than a size of the third connection part in the first direction, part of the signal lines of the drive backplate are arranged in a spacing region between two adjacent third anode sub-blocks. The display panel of claim 82, wherein, the second connection part connects two of the second anode sub-blocks in a second direction; and / or, the third connection part connects two of the third anode sub-blocks in a second direction; and / or, a connection of the second anode sub-block and the second connection part is used to form the second anode opening, a connection of the third anode sub-block and the third connection part is used to form the third anode opening; the second anode opening comprises a gap hollow with an open mouth and / or a closed hollow with a closed shape, the third anode opening comprises a gap hollow with an open mouth and / or a closed hollow with a closed shape. The display panel of any one of claims 79-83, wherein, the signal lines of the drive backplate comprise gate signal lines, the gate signal lines extend along a first direction; in a case where the first light emitting device comprises a first anode block, a projection of at least part of the gate signal lines on the substrate layer does not overlap with a projection of the first anode block on the substrate layer; and / or, a projection of part of the gate signal lines on the substrate layer overlaps with projections of the second anode opening and the third anode opening. The display panel of claim 84, wherein, The first anode block comprises a plurality of first anode sub-blocks, the anode of the first light emitting device comprises a first connecting part, at least two of the first anode sub-blocks are connected by the first connecting part, and part of the gate signal lines are arranged in the interval region between adjacent first anode sub-blocks. The display panel according to claim 84, wherein, The gate signal lines comprise a first gate signal line, a second gate signal line, a third gate signal line, a fourth gate signal line and a fifth gate signal line, the first gate signal line, the second gate signal line, the third gate signal line, the fourth gate signal line and the fifth gate signal line are used for electrically connecting the gates of different transistors in the pixel circuit respectively, and the second gate signal line and the fifth gate signal line are used for transmitting the same gate signal; At least two of the first gate signal line, the second gate signal line, the third gate signal line, the fourth gate signal line and the fifth gate signal line are arranged on different conductive layers, and the gate signal lines are arranged on two conductive layers respectively. The display panel according to claim 86, wherein, The driving back plate comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, and the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are sequentially stacked on one side of the substrate layer; The first conductive layer is provided with a plurality of block electrodes and the fourth gate signal line, and the block electrodes comprise the gates of transistors and the plates of capacitors in the pixel circuit; The second conductive layer is provided with a repair line, and the repair line extends along the first direction; The third conductive layer is provided with the first gate signal line, the second gate signal line, the third gate signal line and the fifth gate signal line; The fourth conductive layer is provided with an anode connecting electrode, and the anode connecting electrode is electrically connected with the anode of the light emitting device. The display panel according to any one of claims 79 to 83, wherein, The driving back plate comprises a data signal line, the data signal line extends along a second direction, and the data signal line is electrically connected with the pixel circuit; The anode of the first light emitting device comprises a first anode block, and the orthogonal projection of the data signal line on the substrate layer does not overlap with the orthogonal projection of the first anode block on the substrate layer; and / or, The orthogonal projection of the data signal line on the substrate layer does not overlap with the orthogonal projection of the second anode block on the substrate layer; and / or, The orthogonal projection of the data signal line on the substrate layer does not overlap with the orthogonal projection of the third anode block on the substrate layer. The display panel according to claim 88, wherein, The driving back plate comprises a reference signal connecting line and a first power supply line, the reference signal connecting line and the first power supply line both extend along the second direction, the reference signal connecting line is located between the data signal line and the first power supply line, the reference signal connecting line and the first power supply line are both electrically connected with the pixel circuit, and the second direction intersects with the first direction. The reference signal connection line includes a first reference connection segment and a second reference connection segment, the first reference connection segment is connected with the second reference connection segment in the second direction, at least part of the first reference connection segment in the first direction is smaller than the size of the second reference connection segment in the first direction, the orthogonal projection of the first reference connection segment on the substrate layer does not overlap with the orthogonal projection of the first anode block on the substrate layer, and the orthogonal projection of the second reference connection segment on the substrate layer overlaps with the orthogonal projection of the first anode block on the substrate layer; and / or, The first power supply line includes a first power supply connection segment and a second power supply connection segment, the first power supply connection segment is connected with the second power supply connection segment in the second direction, at least part of the first power supply connection segment in the first direction is smaller than the size of the second power supply connection segment in the first direction, the orthogonal projection of the first power supply connection segment on the substrate layer does not overlap with the orthogonal projection of the first anode block on the substrate layer, and the orthogonal projection of the second power supply connection segment on the substrate layer overlaps with the orthogonal projection of the first anode block on the substrate layer; and / or, The orthogonal projection of the first power supply connection segment on the substrate layer does not overlap with the orthogonal projection of the second anode block on the substrate layer, and the orthogonal projection of the second power supply connection segment on the substrate layer overlaps with the orthogonal projection of the second anode block on the substrate layer; and / or, The orthogonal projection of the first power supply connection segment on the substrate layer does not overlap with the orthogonal projection of the third anode block on the substrate layer, and the orthogonal projection of the second power supply connection segment on the substrate layer overlaps with the orthogonal projection of the third anode block on the substrate layer. The display panel according to claim 89, wherein The driving back plate includes an initial signal connection line and an initial signal line, the initial signal connection line extends along the second direction, the initial signal line extends along a first direction, the initial signal connection line is electrically connected with the initial signal line, the initial signal line is electrically connected with the pixel circuit, and the first direction intersects with the second direction; The orthogonal projection of the initial signal connection line on the substrate layer does not overlap with the orthogonal projection of the first anode block on the substrate layer. A display device includes: The display panel of any one of claim 1, claim 56, claim 68, and claim 79. ​

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