Display panel and preparation method therefor, and display device

Abstract

A display panel and a preparation method therefor, and a display device. The display panel is provided with a through hole, and comprises a display area and a transition area, wherein the transition area surrounds the through hole, and the display area surrounds the transition area. The display panel comprises a substrate, a first isolation structure, a plurality of sub-pixels and a first stacked structure. The first isolation structure is disposed on the substrate in the display area, and comprises a plurality of openings. Each sub-pixel is located in the corresponding opening, and comprises a light-emitting layer, a second electrode and a first encapsulation layer, which are stacked in a direction away from the substrate. The plurality of sub-pixels comprises first color sub-pixels. The first stacked structure is disposed in the transition area, and comprises a first thin film, a second thin film and a third thin film, which are stacked in the direction away from the substrate, wherein the materials of the first thin film, the second thin film and the third thin film are the same as those of light-emitting layers, second electrodes and first encapsulation layers of the first color sub-pixels, respectively; and there is a distance between the boundary of the first stacked structure away from the display area and the boundary of the through hole.

Description

Display panel, preparation method thereof and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display panel, a preparation method thereof and a display device. BACKGROUND

[0002] An organic light emitting diode (OLED) display panel has the advantages of self-illumination, low driving voltage, high luminous efficiency, thin thickness, wide viewing angle, fast response speed, and flexible display, and has gradually become one of the mainstream products in the display field.

[0003] In some technologies, a through hole needs to be arranged in a display area of a display panel, and the through hole is used to place a photosensitive device to realize functions such as camera shooting and infrared sensing.

[0004] SUMMARY

[0005] In one aspect, a display panel is provided, the display panel is provided with a through hole, and the display panel includes a display area and a transition area, the transition area surrounds the through hole, and the display area surrounds the transition area. The display panel includes a substrate, a first isolation structure, a plurality of sub-pixels, and a first stacked structure. The first isolation structure is arranged on the substrate and in the display area, and includes a plurality of openings. One of the sub-pixels is located in one of the openings, and the sub-pixel includes a light-emitting layer, a second electrode, and a first encapsulation layer which are arranged in a stacked manner away from the substrate. The plurality of sub-pixels includes a first color sub-pixel. The first stacked structure is arranged in the transition area, and includes a first film, a second film, and a third film which are arranged in a stacked manner away from the substrate, the materials of the first film, the second film, and the third film are the same as those of the light-emitting layer, the second electrode, and the first encapsulation layer of the first color sub-pixel, respectively, and the first stacked structure has a spacing between a boundary thereof away from the display area and a boundary of the through hole.

[0006] In some embodiments, the display panel further includes at least one second isolation structure, the second isolation structure is located in the transition area and surrounds the through hole. The second isolation structure is made of the same material as the first isolation structure. The boundary of the first stacked structure away from the display area is located on a side of any of the second isolation structures close to the display area, and the first stacked structure is in contact with the second isolation structure.

[0007] In some embodiments, the first isolation structure and the second isolation structure each comprise a first isolation layer, a second isolation layer and a third isolation layer stacked in a direction away from the substrate, an edge of the third isolation layer protruding away from the second isolation layer compared to the second isolation layer. The first isolation layer, the second isolation layer and the third isolation layer of the first isolation structure are of the same material as the first isolation layer, the second isolation layer and the third isolation layer of the second isolation structure, respectively.

[0008] In some embodiments, the display panel further comprises a barrier dam disposed in the transition region, the barrier dam surrounding the through hole. At least one of the second isolation structures is disposed on a side of the barrier dam close to the display region and / or at least one of the second isolation structures is disposed on a side of the barrier dam away from the display region.

[0009] In some embodiments, the first stack structure is located on a side of the barrier dam close to the display region or on a side of the barrier dam away from the display region.

[0010] In some embodiments, the display panel further comprises a pixel circuit layer between the substrate and the plurality of sub-pixels, the pixel circuit layer comprising a plurality of metal layers stacked in a direction perpendicular to the substrate. At least one of the metal layers comprises at least one pad layer, the pad layer being located in the transition region and surrounding the through hole. In an orthographic projection onto the substrate, at least one of the pad layers overlaps at least one of the second isolation structures.

[0011] In some embodiments, at least one of the pad layers is disposed on a side of the barrier dam close to the display region and / or at least one of the pad layers is disposed on a side of the barrier dam away from the display region.

[0012] In some embodiments, the plurality of metal layers comprises a first gate layer and a second gate layer stacked in a direction away from the substrate. At least one of the pad layers is disposed in the first gate layer and / or at least one of the pad layers is disposed in the second gate layer.

[0013] In some embodiments, the plurality of metal layers further comprises a third gate layer and / or a light shielding metal layer. The third gate layer is disposed on a side of the second gate layer away from the substrate, and at least one of the pad layers is disposed in the third gate layer. The light shielding metal layer is disposed between the substrate and the first gate layer, and at least one of the pad layers is disposed in the light shielding metal layer.

[0014] In some embodiments, the display panel includes multiple groups of the pads, each group of the pads includes multiple pads stacked in a direction perpendicular to the substrate, and each group of the pads is disposed corresponding to one of the second isolation structures. In a projection onto the substrate, at least one pad in each group of the pads overlaps the corresponding second isolation structure.

[0015] In some embodiments, in the projection onto the substrate, all the pads belonging to the same group overlap the corresponding second isolation structure.

[0016] In some embodiments, at least two pads located at different metal layers are staggered in the direction perpendicular to the substrate.

[0017] In some embodiments, at least two pads are provided in one of the metal layers, and the at least two pads are sequentially and spacedly sleeved in a radial direction of the via. The display panel further includes at least one connecting portion connected between two adjacent pads located at the same metal layer, and the connecting portion is made of the same material as the two pads.

[0018] In some embodiments, the display panel further includes a pixel circuit layer located between the substrate and the multiple sub-pixels, and the pixel circuit layer includes multiple metal layers stacked in a direction perpendicular to the substrate. At least one of the metal layers is provided with multiple pads, the pads are located in the transition region, and the pads are disposed around the via. The multiple pads are sequentially and spacedly sleeved in a radial direction of the via.

[0019] In some embodiments, in the first stack structure, the first film, the second film, and the third film are flush away from the boundary of the display area.

[0020] In some embodiments, the display panel further includes an anti-crack structure disposed around the via. The anti-crack structure is disposed between the via and the pad farthest away from the display area.

[0021] In some embodiments, the display panel further includes multiple inorganic layers located between the substrate and the multiple sub-pixels, and the anti-crack structure is formed in a portion of the multiple inorganic layers close to the via. A boundary of the multiple inorganic layers and a boundary of the via have a spacing, and a spacing between a boundary of the first stack structure and a boundary of the via away from the display area is greater than the spacing between the boundary of the multiple inorganic layers and the boundary of the via.

[0022] In some embodiments, the plurality of sub-pixels includes a second color sub-pixel. The display panel further includes a second stack structure disposed on a side of the first stack structure away from the substrate, the second stack structure including a first thin film, a second thin film, and a third thin film stacked in a direction away from the substrate, the first thin film, the second thin film, and the third thin film of the second stack structure being made of the same material as the light-emitting layer, the second electrode, and the material of the first encapsulation layer of the second color sub-pixel, respectively. Further, the second stack structure has a spacing between a boundary of the second stack structure away from a boundary of the display area and a boundary of the via hole.

[0023] In another aspect, a display device is provided, including the display panel of any one of the above and a circuit board connected with the display panel.

[0024] In yet another aspect, a method for manufacturing a display panel is provided, the display panel including a display area, a transition area, and a via hole area, the transition area surrounding the via hole area, and the display area surrounding the transition area. The method includes forming a first isolation structure on a substrate, the first isolation structure being located in the display area, the first isolation structure including a plurality of openings, the plurality of openings including a plurality of first openings for defining first color sub-pixels. A first sub-pixel stack is formed, the first sub-pixel stack being located in the display area, the transition area, and the via hole area, the first sub-pixel stack including a light-emitting material layer, an initial second electrode layer, and an initial first encapsulation layer stacked in a direction away from the substrate. A mask layer is formed on a side of the first sub-pixel stack away from the substrate, the mask layer covering the plurality of first openings and a portion of the transition area close to the display area. Based on the mask layer, the first sub-pixel stack is etched, the first sub-pixel stack retained in the plurality of first openings forming the first color sub-pixels, and the first sub-pixel stack retained in the portion of the transition area close to the display area forming a first stack structure, the first stack structure having a spacing between a boundary of the first stack structure away from a boundary of the display area and a boundary of the via hole area. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, the actual proportion between structures, the actual flow of the method, etc. of the product involved in the embodiments of the present disclosure.

[0026] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0027] Fig. 2 is a sectional view of a partial structure of the display device in Fig. 1 along the AA direction;

[0028] Fig. 3 is a sectional view of a partial structure of the display device in Fig. 1 along the BB direction;

[0029] Fig. 4 is a top view of a display panel according to some embodiments;

[0030] Fig. 5 is a sectional view of a partial structure of the display panel in Fig. 4 along the CC direction;

[0031] Fig. 6 is a sectional view of an isolation column according to some embodiments;

[0032] Fig. 7 is a sectional view of another partial structure of the display panel in Fig. 4 along the CC direction;

[0033] Fig. 8 is a sectional view of still another partial structure of the display panel in Fig. 4 along the CC direction

[0034] Fig. 9A is a top view of a display panel according to some embodiments of the present disclosure;

[0035] Fig. 9B is a structural view of a display panel according to some embodiments of the present disclosure;

[0036] Fig. 10 is a structural view of a display panel at a via according to some embodiments of the present disclosure;

[0037] Fig. 11 is a structural view of a display panel according to some embodiments of the present disclosure;

[0038] Fig. 12 is a structural view of a display panel according to some embodiments of the present disclosure;

[0039] Fig. 13 is a structural view of a display panel according to some embodiments of the present disclosure;

[0040] Fig. 14 is a structural view of a display panel according to some embodiments of the present disclosure;

[0041] Fig. 15 is a structural view of a display panel according to some embodiments of the present disclosure;

[0042] Fig. 16A is a structural view of a display panel according to some embodiments of the present disclosure;

[0043] Fig. 16B is another structural view of the display panel in Fig. 16A at a via;

[0044] Fig. 17 is still another structural view of some embodiments of the present disclosure at a via;

[0045] Figs. 18A to 18C are partial structural views of a pad layer according to some embodiments of the present disclosure;

[0046] FIGS. 19A-19C are partial structural diagrams of another cushion layer, according to some embodiments of the present disclosure;

[0047] FIG. 20 is a flowchart of a pixel evaporation method, according to some embodiments of the related art;

[0048] FIGS. 21-31 are structural diagrams of a display panel in each step of the pixel evaporation method of FIG. 20;

[0049] FIG. 32 is a flowchart of a display panel manufacturing method, according to some embodiments of the present disclosure;

[0050] FIGS. 33-43 are structural diagrams of a display panel in each step of the manufacturing method of FIG. 32. DETAILED DESCRIPTION

[0051] The technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0052] Unless otherwise required by context, the term “comprise” and other forms of the term, such as “comprises” and “comprising,” are used throughout the specification and claims in an open-ended way, i.e., to mean including, but not limited to. In the description of the specification, the terms “one embodiment,” “some embodiments,” “exemplary embodiments,” “example,” “specific example” or “some examples” are used to indicate that the particular feature, structure, material, or characteristic being described is included in at least one embodiment or example of the present disclosure. The illustrative appearance of these terms in various places in the specification are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0053] Hereinafter, the terms “first” and “second” are used only for the purpose of description, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of “a plurality of” is two or more, unless otherwise specified.

[0054] In describing some embodiments, the use of "connection" and / or "coupling" and / or terms of similar import can be used. The term "connection" is to be construed broadly, for example, "connection" can be a fixed connection, or a detachable connection, or integral; can be directly connected, or indirectly connected through an intermediate medium. The embodiments disclosed herein are not necessarily limited to the content herein.

[0055] "A, B, and C at least one of" is synonymous with "at least one of A, B, or C," and includes the following combinations of A, B, and C: only A, only B, only C, A and B, A and C, B and C, and A and B and C.

[0056] "A and / or B" includes the following three combinations: A alone, B alone, and A and B together.

[0057] The use of "configured to" herein means an open and inclusive language that does not exclude devices configured to perform additional tasks or steps.

[0058] In addition, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more recited conditions or values can be based on additional conditions or values beyond those recited.

[0059] As used herein, "approximately" includes the recited value and the average value within an acceptable range of deviation from the recited value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0060] As used herein, "parallel," "perpendicular," and "equal" include the recited condition and conditions that are approximately the recited condition, where the approximately recited condition is within an acceptable range of deviation, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, where the acceptable range of deviation for approximately parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and approximately perpendicular, where the acceptable range of deviation for approximately perpendicular can also be, for example, within 5°. "Equal" includes absolute equal and approximately equal, where the acceptable range of deviation for approximately equal can be, for example, a difference between the two that is less than or equal to 5% of either.

[0061] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0062] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the individual features of actual implementations are necessarily shown in a particular figure. Additionally, details of well-known devices and techniques are not shown in detail in order to avoid unnecessarily obscuring the exemplary embodiments. Thus, the exemplary embodiments are not limited to the specific examples presented herein. For example, the etched regions shown as rectangular will typically have curved features. Therefore, the regions shown in the drawings are intended to be illustrative and not definitive of the actual shape of the regions of the devices, and are not intended to limit the scope of the exemplary embodiments.

[0063] As shown in FIG. 1, an embodiment of the present disclosure provides a display device 1000, which is a product having an image display function. Exemplarily, the display device 1000 can be any device that displays images whether moving (e.g., video) or fixed (e.g., still image) and whether text or image.

[0064] Exemplarily, the display device 1000 can be a television, a notebook computer, a tablet computer, a Personal Digital Assistant (PDA), a mobile phone, a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a display of a camera view (e.g., a display of a rear view camera in a vehicle), a wearable device, an Augmented Reality (AR) device, a Virtual Reality (VR) device, an in-vehicle display, a flight display, or the like, any product or component having a display function. For example, as shown in FIG. 1, the display device 1000 can be a mobile phone.

[0065] From the light-emitting type of the display device 1000, the display device 1000 can be an OLED display device or a quantum dot light emitting diode (QLED) display device. From the form of the display device 1000, the display device 1000 can be a flat display device, a curved display device, or a foldable display device, etc. From the shape of the display device 1000, the display device 1000 can be rectangular, circular, etc. From the light-emitting direction of the display device 1000, the display device 1000 can be a top emission display device or a bottom emission display device. Embodiments of the present disclosure do not make specific limitations on this.

[0066] In the following, some embodiments of the present disclosure are schematically described by taking an organic light-emitting diode display device as an example, which is a top emission type, rectangular, and flat. However, the embodiments of the present disclosure are not limited thereto, and any other display device can also be considered as long as the same technical idea is applied.

[0067] With reference to FIGS. 2 and 3, FIG. 2 is a cross-sectional view of a partial structure of the display device 1000 along the AA direction in FIG. 1, and FIG. 3 is a cross-sectional view of a partial structure of the display device 1000 along the BB direction in FIG. 1. The display device 1000 includes a display panel 1001 and a cover plate 1002. The cover plate 1002 is arranged on the light-emitting side of the display panel 1001 and is used to protect the display panel 1001. An optical clear adhesive (OCA) is arranged between the display panel 1001 and the cover plate 1002, and is used to bond the display panel 1001 and the cover plate 1002. In some embodiments, the display device 1000 includes a polarizer (POL) between the OCA and the display panel 1001.

[0068] Under the premise that the display device 1000 is an OLED display device, the display panel 1001 is an OLED display panel. The structure of the display panel 1001 is described in detail below by taking the display panel 1001 as an OLED display panel as an example.

[0069] Continuing to refer to FIG. 2, some embodiments of the present disclosure provide a display panel 1001, which includes an array substrate 100, a light-emitting device layer 200, and an encapsulation structure 300 arranged in a stack.

[0070] The array substrate 100 includes a substrate 110 and a pixel circuit layer 120 arranged in a stack.

[0071] The material of the substrate 110 is a transparent material. For example, the substrate 110 can adopt a transparent flexible substrate, or can also adopt a transparent rigid substrate such as glass or ultra-thin glass.

[0072] The pixel circuit layer 120 includes a plurality of pixel circuits configured to drive the light emitting device layer 200 to emit light. The pixel circuit layer 120 can include a plurality of conductive layers, which can include, for example, a semiconductor layer ACT, a first gate layer GT1, a second gate layer GT2, a first source-drain layer SD1, and a second source-drain layer SD2 arranged in sequence in a direction perpendicular to and away from the substrate 110. Of course, the array substrate can also include other conductive layers, such as an oxide semiconductor layer, a third gate layer, a light shielding metal layer, etc., which are not specifically limited here.

[0073] The plurality of conductive layers form a plurality of thin film transistors TFT, which can include a semiconductor pattern 101 located in the semiconductor layer ACT, a gate 102 located in the gate conductive layer GT, and a source 103 and a drain 104 located in the source-drain conductive layer SD.

[0074] The pixel circuit layer 120 can also include an insulating layer between adjacent conductive layers, for example, the array substrate 100 can include a first gate insulating layer GI1 between the semiconductor layer ACT and the first gate layer GT1, a second gate insulating layer GI2 between the first gate layer GT1 and the second gate layer GT2, an interlayer dielectric layer ILD between the second gate layer GT2 and the first source-drain layer SD1, a passivation layer PVX and a first planarization layer PLN1 between the first source-drain layer SD1 and the second source-drain layer SD2, and a second planarization layer PLN2 between the second source-drain layer SD2 and the light emitting device layer 200. Of course, the pixel circuit layer 120 can also include other insulating film layers, which are not described one by one here.

[0075] The light emitting device layer 200 includes a first electrode 201, a light emitting material layer 202, and a second electrode 203 arranged in a direction away from the array substrate 100. The light emitting device layer 200 includes a plurality of first isolation structures 410 and a plurality of light emitting devices, for example, selected from sub-pixels, the first isolation structures 410 form a plurality of openings for defining the light emitting devices. The first isolation structures 410 include, for example, a first isolation layer 401, a second isolation layer 402, and a third isolation layer 403, in some embodiments, the second isolation layer 402 is selected from a metal layer, and the third isolation layer is selected from an inorganic layer.

[0076] The display panel 1001 includes a plurality of light emitting devices. Each light emitting device is connected with a pixel circuit, and the pixel circuit is configured to drive the light emitting device to emit light. The plurality of light emitting devices can be light emitting devices of different colors, for example, red light emitting devices, green light emitting devices, or blue light emitting devices, so that the display panel 1001 can display a color picture. The plurality of light emitting devices can also be single white light emitting devices or single blue light emitting devices, in which case, a color conversion structure is arranged above the light emitting device layer 200 to convert light of a single color into a target color. In some possible embodiments, the second electrodes 203 of the plurality of light emitting devices are connected with each other to form a continuous whole-layer structure.

[0077] In some embodiments, the first electrode 201 is configured as a cathode of the light emitting device layer 200, and the second electrode 203 is configured as an anode of the light emitting device layer 200. In other embodiments, the first electrode 201 is configured as an anode of the light emitting device layer 200, and the second electrode 203 is configured as a cathode of the light emitting device layer 200.

[0078] In some embodiments, the first electrode 201 is a reflective electrode, and the second electrode 203 is a semi-transparent and semi-reflective electrode, in which case, the display panel 1001 is a top emission display panel. In other embodiments, the first electrode 201 is a semi-transparent and semi-reflective electrode, and the second electrode 203 is a reflective electrode, in which case, the display panel 1001 is a bottom emission display panel. The embodiments of the present disclosure do not make a specific limitation in this regard.

[0079] The light emitting material layer 202 includes an organic light emitting layer. In the case where the plurality of light emitting devices are light emitting devices of different colors, the organic light emitting layers of the light emitting devices of different colors are arranged independently of each other. In the case where the plurality of light emitting devices are single white light emitting devices or single blue light emitting devices, the organic light emitting layers of the plurality of light emitting devices can be connected to form a whole surface structure, or can be arranged independently of each other.

[0080] The light emitting material layer 202 can further include at least one common layer, and the common layer includes a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. The hole injection layer and / or the hole transport layer can be arranged between the anode and the organic light emitting layer, and the electron injection layer and / or the electron transport layer can be arranged between the cathode and the organic light emitting layer. The structure is not shown in the drawings of the present embodiment, and can be understood with reference to the structure of an organic light emitting diode display panel in the related art. In the case where the light emitting material layer 202 includes one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer, these film layers can be in a whole surface structure, or can be arranged independently of each other.

[0081] In some embodiments, the display panel 1001 can further include a pixel definition layer (PDL) located between the first isolation layer 401 and the array substrate 100, and the PDL includes a plurality of openings, and at least part of each light emitting material layer 202 is located in one of the openings.

[0082] The encapsulation structure 300 is located on the side of the light emitting device layer 200 away from the array substrate 100. The encapsulation structure 300 is configured to reduce the risk of water vapor and oxygen in the external environment entering the light emitting device layer 200, thereby improving the service life of the display panel 1001. As shown in FIG. 2, the encapsulation structure 300 can be an encapsulation film, and in this case, the encapsulation structure 300 can include a first encapsulation layer 301 and a second encapsulation layer 302 stacked.

[0083] Exemplarily, the material of the first encapsulation layer 301 includes a combination of one or more of silicon nitride (SiNx), silicon dioxide (SiOx), and silicon oxynitride (SiON). The first encapsulation layer 301 is formed by a chemical vapor deposition (CVD) process.

[0084] Exemplarily, the material of the second encapsulation layer 302 includes a combination of one or more of silicon nitride (SiNx), silicon dioxide (SiOx), and silicon oxynitride (SiON). The second encapsulation layer 302 is formed by a chemical vapor deposition (CVD) process.

[0085] The display panel 1001 further includes an organic encapsulation layer 30 located between the first encapsulation layer 301 and the second encapsulation layer 302.

[0086] Exemplarily, the material of the organic encapsulation layer 30 includes a polymer combination of one or more of an acrylic-based polymer, a silicon-based polymer, and an epoxy-based polymer. The above material is fabricated on the first encapsulation layer 301 by an ink jet printing (IJP) method, and is subjected to ultraviolet (UV) curing to form the organic encapsulation layer 30.

[0087] The cutting position of the through hole T is shown by the dashed line in FIG. 3. Due to the presence of the through hole T, the encapsulation structure 300 at the edge of the cutting position cannot completely cover the light-emitting device layer 200, that is, the sidewall of the light-emitting device layer 200 is exposed, and thus water vapor and oxygen in the environment can easily penetrate from the cutting position, for example, through the second electrode 203 and the light-emitting material layer 202, to corrode the light-emitting device layer 200 in the transition area Q22 and the display area Q1 adjacent to the transition area Q22 and the encapsulation structure 300, which can easily cause the light-emitting device layer 200 in the display area Q1 of the display panel 1001 to fail to emit light, resulting in a GDSH (Growing Dark Spot Hole) and affecting the display quality of the display panel 1001. In order to prevent water and oxygen in the air from penetrating into the inside of the display area of the display panel 1001 along the light-emitting material layer 202 and / or the second electrode 203 at the boundary of the through hole T, some related technologies propose some technical solutions of setting a partition structure in the transition area.

[0088] Referring to FIG. 4, in some embodiments, the display panel 1001 includes a display area Q1 and a non-display area Q2 adjacent to the display area Q1, where the non-display area Q2 includes a frame area Q21 at the frame of the display panel 1001. In some application scenarios of the display panel 1001, the display panel 1001 is designed with an AA Hole (Active Area Hole) design, that is, a through hole T is provided in the display panel 1001 to accommodate a camera, a sensor or the like. In the case where the through hole T is provided in the display panel 1001, the non-display area Q2 further includes a transition area Q22, which is an area around the through hole T. In this case, the transition area Q22 surrounds the through hole T, and the display area Q1 surrounds the transition area Q22.

[0089] With reference to FIGS. 4 and 5, FIG. 5 is a cross-sectional view of a partial structure of the display panel 1001 along the CC direction in FIG. 4. In order to disconnect the second electrode 203 and the light-emitting material layer 202 in the display area Q1 from the second electrode 203 and the light-emitting material layer 202 in the transition area Q22 to prevent water and oxygen in the external environment from corroding the sub-pixels in the display area Q1 via the light-emitting material layer 202 and the second electrode 203, an isolation groove can be etched on the substrate 110 and arranged around the through hole T.

[0090] Exemplarily, the display panel 1001 comprises a substrate 110 and a light-emitting device layer 200 disposed on the substrate 110. The substrate 110 comprises a first sub-substrate 111, a first barrier layer 112, a second sub-substrate 113 and a second barrier layer 114 which are stacked. Exemplarily, the first sub-substrate 111 and the second sub-substrate 113 are selected from a flexible substrate material such as polyimide, and the first barrier layer 112 and the second barrier layer 114 are selected from an inorganic material. In some embodiments, an amorphous silicon layer is further included between the first barrier layer 112 and the second sub-substrate 113, and a buffer layer is further included on a side of the second barrier layer 114 away from the second sub-substrate 113. The buffer layer is selected from, for example, one or a combination of multiple layers of amorphous silicon (a-Si), silicon nitride (SiNx) and silicon oxide (SiOx).

[0091] As can be seen from FIG. 5, the related art adds a mask process to etch the substrate 110 before forming the light-emitting device layer 200, for example, to etch the second sub-substrate 113 and the second barrier layer 114 to form an isolation groove on the substrate 110. Thus, the light-emitting device layer 200 is disconnected at the isolation groove due to a height difference during evaporation, achieving electrical isolation of the light-emitting device layer 200 and effectively preventing black spots in the hole area caused by electrochemical corrosion. However, forming the isolation groove on the substrate 110 destroys the original structure of the substrate 110, resulting in a decrease in the overall structural strength of the substrate 110 and making it more prone to structural defects such as cracks. The position of the isolation groove is thinned, and the ability of the substrate 110 to resist the invasion of impurities from the outside is reduced, to some extent, increasing the risk of black spots in the hole area caused by impurity invasion. At the same time, adding a mask process before forming the light-emitting device layer 200 increases the cost.

[0092] In some embodiments, a mask process can also be added to etch the first planar layer PLN1 and / or the second planar layer PLN2 to form an isolation groove in the planar layer. Thus, the light-emitting device layer 200 is disconnected at the isolation groove due to a height difference during evaporation, achieving electrical isolation of the light-emitting device layer 200 and effectively preventing black spots in the hole area caused by electrochemical corrosion. However, etching the isolation groove on the planar layer requires an additional mask process, increasing the cost.

[0093] With reference to FIG. 4, FIG. 6 and FIG. 7, FIG. 6 is a cross-sectional view of a spacer according to some embodiments, and FIG. 7 is a cross-sectional view of another partial structure of the display panel along the CC direction in FIG. 4. For ease of description, other film layers of the light-emitting material layer 202 are not shown in the example of the second electrode 203 overlapping the sidewall of the spacer L. The display panel 1001 includes a substrate 110, a spacer L disposed on one side of the substrate 110, a second electrode 203 covering the substrate 110 and the spacer L, and a first encapsulation layer 301 covering the second electrode 203. The spacer L includes a first titanium metal layer L1, an aluminum metal layer L2, and a second titanium metal layer L3 stacked together, the first titanium metal layer L1 and the second titanium metal layer L3 are, for example, selected from metal titanium, and the aluminum metal layer L2 is, for example, selected from metal aluminum. The spacer L and the substrate 110 further include, for example, a gate insulating layer GI.

[0094] It can be seen that the second electrode 203 overlaps at the aluminum metal layer L2, and the display panel 1001 has a conductive path Conp composed of the second electrode 203 on one side of the spacer L, the aluminum metal layer L2 in the spacer L, and the second electrode 203 on the other side of the spacer L. In the display area Q1 of the display panel 1001, the second electrode 203 forms a continuous whole-layer structure through the overlap of the spacer L, which is beneficial to improve the display reliability of the display panel 1001. However, in the Q22, such overlap can cause external water and oxygen to invade and damage the encapsulation structure 300 and the light-emitting material layer 202 in the display area Q1 near the via T area.

[0095] Referring to FIG. 7, the display panel 1001 includes a substrate 110, the display area Q1 of the display panel 1001 includes a gate layer GT, a source layer SD, a planarization layer PLN, and a pixel definition layer PDL stacked together, and the transition area Q22 includes one or more spacers L and a barrier dam DAM. The first encapsulation layer 301, the organic encapsulation layer 30, and the second encapsulation layer 302 are stacked on one side of the 1001. One or more spacers L are disposed in the transition area Q22 to separate the second electrode 203 and the light-emitting material layer 202 in the transition area Q22 from the second electrode 203 and the light-emitting material layer 202 in the display area Q1. When this embodiment is used, the spacer L can be formed without increasing the process and maintaining the cost. However, due to the conductive path Conp as shown in FIG. 6, the reliability quality of the display panel 1001 under the power-on condition cannot be ensured.

[0096] The encapsulation structure 300 near the via hole T of the display panel 1001 cannot completely cover the light-emitting device layer 200, that is, the sidewall of the light-emitting device layer 200 is in a state of being exposed to the outside, and thus water vapor, oxygen in the environment and potassium ions released from the polarizer POL are likely to invade from the edge position of the via hole T to corrode the light-emitting device layer 200 and the encapsulation structure 300 in the transition area Q22. Under the running condition of the display panel 1001, that is, the power-on condition, the second electrode 203 in the transition area Q22 is still charged due to the existence of the conductive path Conp of the isolation column L, the water vapor is electrolyzed to generate hydroxyl ions, and the hydroxyl ions and the potassium ions form a strong alkaline environment at the dotted line frame to corrode the inorganic material in the first encapsulation layer 301 and further cause encapsulation failure. The above-mentioned electrochemical corrosion forms an invasion channel from the boundary of the via hole T to the display area Q1. Since the organic light-emitting material in the light-emitting material layer 202 is very sensitive to water vapor and oxygen, once the water vapor and oxygen invade into the display area Q1 through the channel, the light-emitting device layer 200 in the display area Q1 of the display panel 1001 is likely to fail to emit light, a hole area black spot appears, and the display quality of the display panel 1001 is affected.

[0097] FIG. 8 is a cross-sectional view of another partial structure of the display panel in FIG. 4 along the CC direction. The display panel 1001 includes a substrate 110 and a light-emitting device layer 200 which are arranged in a stack.

[0098] The substrate 110 includes a first sub-substrate 111, a first barrier layer 112, a second sub-substrate 113 and a second barrier layer 114 arranged in a stack. For example, the first sub-substrate 111 and the second sub-substrate 113 are selected from a flexible substrate material such as polyimide, and the first barrier layer 112 and the second barrier layer 114 are selected from an inorganic material. In some embodiments, an amorphous silicon layer is further included between the first barrier layer 112 and the second sub-substrate 113, and a buffer layer is further included on the side of the second barrier layer 114 away from the second sub-substrate 113. The buffer layer is, for example, selected from one or a combination of multiple layers of amorphous silicon (a-Si), silicon nitride (SiNx) and silicon oxide (SiOx) arranged in a stack.

[0099] After the light-emitting device layer 200 is formed by evaporation, the light-emitting device layer 200 in the transition area Q22 is removed by laser to achieve electrical isolation. The electrical isolation effect is good, the overall structural strength is high without damaging the substrate 110, but the technical solution of laser removal needs to increase additional equipment and process, and the cost is increased.

[0100] To solve the above problems, embodiments of the present disclosure provide a display panel 1001. In combination with FIG. 9A and FIG. 9B, FIG. 9A is a top view of a display panel provided by some embodiments of the present disclosure, and FIG. 9B is a cross-sectional view of a partial structure of the display panel 1001 along the DD direction in FIG. 9A. The display panel 1001 includes a first isolation structure 410 located in the display area Q1, a sub-pixel 600 located in the display area Q1, and a first laminated structure 510 located in the transition area Q22. The first isolation structure 410 includes a plurality of openings, and the plurality of openings include a plurality of first openings, a plurality of second openings, and a plurality of third openings; one sub-pixel 600 is located in one opening, and the sub-pixel 600 includes, for example, a first color sub-pixel 601, a second color sub-pixel 602, and a third color sub-pixel 603. The exemplary first color sub-pixel 601 is located at the first opening, the second color sub-pixel 602 is located at the second opening, and the third color sub-pixel 603 is located at the third opening. The sub-pixel 600 includes a light-emitting material layer 202, a second electrode 203, and a first encapsulation layer 301 stacked in a direction away from the substrate 110, the first laminated structure 510 includes a first thin film 501, a second thin film 502, and a third thin film 503 stacked in a direction away from the substrate 110, the first thin film 501, the second thin film 502, and the third thin film 503 of the first laminated structure 510 are respectively the same as the light-emitting material layer 202, the second electrode 203, and the first encapsulation layer 301 of the first color sub-pixel 601; and the first laminated structure 510 has a spacing between the boundary away from the display area Q1 and the boundary of the through hole T.

[0101] In some embodiments, during the preparation of the display panel 1001, after sequentially forming the light-emitting material layer 202, the second electrode 203, and the first encapsulation layer 301 covering the display area Q1, the transition area Q22, and the through hole area, the light-emitting material layer 202, the second electrode 203, and the first encapsulation layer 301 in the first opening are reserved by a mask etching process, and the light-emitting material layer 202, the second electrode 203, and the first encapsulation layer 301 close to the display area Q1 in the transition area Q22 are reserved, so that the remaining light-emitting material layer 202, the second electrode 203, and the first encapsulation layer 301 of the transition area Q22 have a spacing between the boundary away from the display area Q1 and the through hole area.

[0102] The display panel 1001 provided in some embodiments of the present disclosure has a spacing between the first stack structure of the transition area Q22 and the via T, that is, the second electrode 203 surrounding the via T is removed, there is no conductive path from the via T to the display area Q1, effectively avoiding the hole area black spot caused by electrochemical corrosion. At the same time, the first stack structure 510 is made of the same material as the first color sub-pixel 601 and is arranged in the same layer, and the two are compatible in the preparation step, without the need to increase additional processes, without increasing the cost on the premise of obtaining better display reliability. Moreover, the first stack structure 510 of the transition area Q22 extends the coverage range of the second electrode 203 to the transition area Q22, reduces the resistance of the area, and is beneficial to improve the display uniformity of the display panel 1001.

[0103] In some embodiments, the display panel 1001 further comprises at least one second isolation structure 420, the second isolation structure 420 is located in the transition area Q22 and is arranged around the via T. The number of the second isolation structure 420 can be one or more, and in FIG. 9B, the display panel 1001 is taken as an example comprising four second isolation structures 420, it should be understood that the number of the second isolation structure 420 can also be 1, 2 or 3, and the present disclosure does not make a limitation in this regard.

[0104] The second isolation structure 420 is made of the same material as the first isolation structure 410, and the second isolation structure 420 also comprises the first isolation layer 401, the second isolation layer 402 and the third isolation layer 403. For example, in the first isolation structure 410 or the second isolation structure 420, the edge of the third isolation layer 403 protrudes away from the second isolation layer 402. The first film 501 away from the boundary of the display area Q1 is located on one side of any second isolation structure 420 close to the display area Q1, and the first film 501 is in contact with the second isolation structure 420.

[0105] In some embodiments, the display panel 1001 further comprises a pixel definition layer, the pixel definition layer is located on one side of the first isolation structure 410 close to the substrate 110, and the pixel definition layer comprises a plurality of openings, one sub-pixel is located in one opening.

[0106] In the preparation process of the display panel 1001, the preparation steps of the first isolation structure 410 and the second isolation structure 420 can comprise: sequentially forming the first isolation layer 401, the second isolation layer 402 and the third isolation layer 403 covering the display panel 1001, using a mask etching process to form the first isolation structure 410 for defining the opening in the display area Q1, and forming one or more second isolation structures 420 surrounding the via T in the non-display area Q2.

[0107] By setting at least one second isolation structure 420 around the through hole T, the structural strength of the display panel 1001 can be effectively increased, and the risk of defects such as cracks caused by stress can be reduced.

[0108] In some embodiments, the first isolation layer 401, the second isolation layer 402, and the third isolation layer 403 of the first isolation structure 410 are respectively the same in material as the first isolation layer 401, the second isolation layer 402, and the third isolation layer 403 of the second isolation structure 420 and are set in the same layer, and are compatible in the preparation step without the need to increase additional processes.

[0109] In some embodiments, the display panel 1001 further includes a barrier dam DAM located in the transition area Q22 and arranged around the through hole T, and includes two second isolation structures 420 on the side of the barrier dam DAM close to the display area Q1 and two second isolation structures 420 on the side of the barrier dam DAM away from the display area Q1. The boundary of the first thin film 501 is, for example, located on the side of the barrier dam DAM close to the display area Q1, that is, the boundary of the first stack structure 510 away from the display area Q1 is located on the side of the two second isolation structures 420 included on the side of the barrier dam DAM close to the display area Q1, and any one of the second isolation structures 420 on the side close to the display area Q1 is in contact with the first thin film 501.

[0110] In some embodiments, the display panel 1001 further includes a pad layer 701 and a pad layer 702 located in the transition area Q22 and arranged around the through hole T. The display panel 1001 can include one or more pad layers, and when the display panel 1001 includes multiple pad layers, the multiple pad layers can be stacked in the direction perpendicular to the substrate 110 or can be sleeved in the direction parallel to the substrate 110. Similarly, the display panel 1001 can have both stacked pad layers and sleeved pad layers. In combination with FIG. 2 and FIG. 9B, taking the display panel 1001 including eight pad layers as an example, four pad layers 701 which are in the same layer as the first gate layer GT1 and are sleeved in the radial direction of the through hole T, and four pad layers 702 which are in the same layer as the second gate layer GT2 and are sleeved in the radial direction of the through hole T. The pad layer 701 and the pad layer 702 are respectively arranged on the side of each second isolation structure 420 close to the substrate 110. For example, for ease of description, the pad layer 702 and the pad layer 701 arranged on the side of the second isolation structure 420 close to the substrate can be regarded as a group of pad layers.

[0111] The pad layer 701 and the pad layer 702 are regarded as a group of pad layers, the group of pad layers is arranged corresponding to one second isolation structure 420, and the group of pad layers is located at a side of the second isolation structure 420 close to the substrate 110, that is, the second isolation structure 420 and the pad layer 701 and / or the pad layer 702 overlap in the orthographic projection toward the substrate 110, and the overlap in the orthographic projection toward the substrate 110 can further strengthen the structural strength of the display panel 1001.

[0112] Referring to FIG. 2, the pixel circuit layer 120 includes a plurality of metal layers arranged in a direction perpendicular to the substrate 110, the pad layer 701 is the same as the GT1 material and is arranged in the same layer, and the pad layer 702 is the same as the second gate layer GT2 material and is arranged in the same layer. In the preparation process of the display panel 1001, the GT1 covering the substrate 110 is formed at one side of the substrate 110, the GT1 is etched to obtain a corresponding first gate pattern in the display area Q1 and one or more pad layers 701 in the non-display area Q2; after the second gate insulating layer GI2 and the second gate layer GT2 covering the display panel 1001 are sequentially formed, the second gate layer GT2 is etched to obtain a corresponding second gate pattern in the display area Q1 and one or more pad layers 702 in the non-display area Q2.

[0113] In the embodiment, the display panel 1001 includes four groups of pad layers, each group of pad layers includes the pad layer 701 and the pad layer 702 arranged in a direction perpendicular to the substrate 110, and the pad layer 702 is located at a side of the pad layer 701 away from the substrate 110; two groups of pad layers are included at a side of the barrier dam DAM close to the display area Q1, and two groups of pad layers are included at a side of the barrier dam DAM away from the display area Q1.

[0114] The pad layer 701 and the pad layer 702 are both made of a metal material and are annular around the through hole T, and the toughness and ductility of the metal can effectively improve the structural strength of the display panel 1001. The pad layer is the same as one layer of the plurality of metal layers in material and is arranged in the same layer, so that the preparation steps of the pad layer are compatible with the preparation steps of one layer of the plurality of metal layers, without the need to increase additional steps.

[0115] In some embodiments, the display panel 1001 further includes an anti-crack structure 801, the anti-crack structure 801 is located in the transition area Q22 and is arranged around the through hole T, and the anti-crack structure 801 is located, for example, between the through hole T and the pad layer farthest from the display area Q1. Referring to FIG. 2, the anti-crack structure 801 is the same as one or more interlayer dielectric layers included in the pixel circuit layer 120 in material, and the one or more interlayer dielectric layers are regarded as inorganic layers in the non-display area Q2.

[0116] In the preparation process of the display panel 1001, part of the inorganic layer of the transition region Q22 is removed by etching, for example, by using an interlayer dielectric layer ILD or EBB process, to form the crack prevention structure 801. In this embodiment, the crack prevention structure 801 has a comb-shaped cross-sectional view.

[0117] The crack prevention structure 801 can avoid cracks in the display panel 1001 during cutting, module assembly, or transportation under stress, and block the path of cracks from the transition region Q22 to the display region Q1. Moreover, the crack prevention structure 801 can ensure a certain spacing between the pad and the boundary of the through hole T, so as to avoid the extension of cracks to the pad during the cutting of the through hole T, thereby preventing the pad from being broken.

[0118] In some embodiments, the display panel 1001 further comprises a second stack structure, the first film, the second film, and the third film of the second stack structure being made of the same material as the light-emitting material layer 202, the second electrode 203, and the first encapsulation layer 301 of the second color sub-pixel 602, respectively; the second stack structure is located on the side of the first stack structure 510 away from the substrate 110, and the second stack structure has a spacing between the boundary away from the display region Q1 and the boundary of the through hole T.

[0119] In some embodiments, the display panel 1001 further comprises a third stack structure, the first film, the second film, and the third film of the third stack structure being made of the same material as the light-emitting material layer 202, the second electrode 203, and the first encapsulation layer 301 of the third color sub-pixel 603, respectively; the third stack structure is located on the side of the second stack structure away from the substrate 110, and the third stack structure has a spacing between the boundary away from the display region Q1 and the boundary of the through hole T.

[0120] FIG. 10 is a structure diagram of a display panel at a through hole according to some embodiments of the present disclosure, which is a partial enlarged view of the through hole in FIG. 9A. In combination with FIG. 9A, FIG. 9B, and FIG. 10, it can be seen that, in some embodiments, the transition region Q22 of the display panel 1001 comprises the crack prevention structure 801 surrounding the through hole T, two circles of the second isolation structure 420, and the pad 701 and the pad 702 blocked by the second isolation structure 420 in the top view, the blocking dam DAM, two circles of the second isolation structure 420, and the pad 701 and the pad 702 blocked by the second isolation structure 420 in the top view.

[0121] FIG. 11 is a structural diagram of a display panel according to some embodiments of the present disclosure. The display panel 1001 includes the first isolation structure 410 in the display area Q1, the sub-pixel 600, the second isolation structure 420 in the transition area Q22, the dam D AM, the first stack structure 510, the pad layer 701, the pad layer 702, and the crack prevention structure 801. The first isolation structure 410 includes a plurality of openings, and the plurality of openings include a first opening. One sub-pixel 600 is located in one opening. The sub-pixel 600 includes, for example, a first color sub-pixel 601 located in the first opening. The sub-pixel 600 includes the light-emitting material layer 202, the second electrode 203, and the first encapsulation layer 301 stacked in a direction away from the substrate 110. The first stack structure 510 includes the first thin film 501, the second thin film 502, and the third thin film 503 stacked in a direction away from the substrate 110. The first thin film 501, the second thin film 502, and the third thin film 503 of the first stack structure 510 are made of the same material as the light-emitting material layer 202, the second electrode 203, and the first encapsulation layer 301 of the first color sub-pixel 601, respectively. The first stack structure 510 has a spacing between a boundary of the first stack structure 510 and a boundary of the via T away from the boundary of the display area Q1.

[0122] The second isolation structure 420 is disposed around the via T. The second isolation structure 420 is made of the same material as the first isolation structure 410. The second isolation structure 420 also includes the first isolation layer 401, the second isolation layer 402, and the third isolation layer 403. In some embodiments, the edge of the third isolation layer 403 protrudes away from the second isolation layer 402 in the first isolation structure 410 or the second isolation structure 420. In some embodiments, the display panel 1001 includes a plurality of second isolation structures 420, for example, four second isolation structures 420.

[0123] The dam D AM is disposed around the via T. In some embodiments, the dam D AM includes two second isolation structures 420 on a side of the dam D AM close to the display area Q1, and includes two second isolation structures 420 on a side of the dam D AM away from the display area Q1. The boundary of the first stack structure 510 is located on the side of the dam D AM away from the display area Q1, that is, the boundary of the first stack structure 510 away from the boundary of the display area Q1 is located on the side of the two second isolation structures 420 included in the dam D AM away from the display area Q1. Any one of the second isolation structures 420 on the side close to the display area Q1 is in contact with the first thin film 501.

[0124] The pad layer 701 and the pad layer 702 are arranged around the through hole T. The pad layer 701 and the pad layer 702 are regarded as a group of pad layers, the group of pad layers is arranged corresponding to one second isolation structure 420, and the group of pad layers is located at a side of the second isolation structure 420 close to the substrate 110, that is, the second isolation structure 420 and the pad layer 701 and / or the pad layer 702 overlap in the orthographic projection toward the substrate 110.

[0125] Referring to FIG. 2, the pixel circuit layer 120 includes a plurality of metal layers arranged in a direction perpendicular to the substrate 110. The pad layer 701 is made of the same material as the GT1 and arranged in the same layer. The pad layer 702 is made of the same material as the second gate layer GT2 and arranged in the same layer. In this embodiment, the display panel 1001 includes four groups of pad layers, each group of pad layers including the pad layer 701 and the pad layer 702 arranged in a direction perpendicular to the substrate 110, and the pad layer 702 is located at a side of the pad layer 701 away from the substrate 110. For example, two groups of pad layers are arranged at a side of the barrier dam DAM close to the display area Q1, and two groups of pad layers are arranged at a side of the barrier dam DAM away from the display area Q1.

[0126] The anti-cracking structure 801 is arranged around the through hole T, for example, between the through hole T and the pad layer farthest from the display area Q1. Referring to FIG. 2, the anti-cracking structure 801 is made of the same material as one or more interlayer dielectric layers included in the pixel circuit layer 120.

[0127] The first stack structure 510 is located at a side of the barrier dam DAM away from the display area Q1, and the second electrode 203 covers a larger area, the resistance is reduced, and the display uniformity of the display panel 1001 is further improved.

[0128] FIG. 12 is a structural diagram of a display panel according to some embodiments of the present disclosure. The display panel 1001 includes a first isolation structure 410 in a display area Q1, a sub-pixel 600, a second isolation structure 420 in a transition area Q22, a barrier dam DAM, a first stack structure 510, a pad layer 701, a pad layer 702, and a crack prevention structure 801. The first isolation structure 410 includes a plurality of openings, and the plurality of openings includes a first opening; one sub-pixel 600 is located in one opening, and the sub-pixel 600 includes, for example, a first color sub-pixel 601 located in the first opening. The sub-pixel 600 includes a light-emitting material layer 202, a second electrode 203, and a first encapsulation layer 301 stacked in a direction away from the substrate 110, the first stack structure 510 includes a first thin film 501, a second thin film 502, and a third thin film 503 stacked in a direction away from the substrate 110, the first thin film 501, the second thin film 502, and the third thin film 503 of the first stack structure 510 are respectively made of the same material as the light-emitting material layer 202, the second electrode 203, and the first encapsulation layer 301 of the first color sub-pixel 601; and the first stack structure 510 has a spacing between a boundary of the first stack structure 510 away from a boundary of the display area Q1 and a boundary of the through hole T.

[0129] The second isolation structure 420 is arranged around the through hole T. The second isolation structure 420 is made of the same material as the first isolation structure 410, and the second isolation structure 420 also includes a first isolation layer 401, a second isolation layer 402, and a third isolation layer 403. For example, in the first isolation structure 410 or the second isolation structure 420, the edge of the third isolation layer 403 protrudes away from the second isolation layer 402. In this embodiment, the display panel 1001 includes one second isolation structure 420. The first stack structure 510 is away from a side of the second isolation structure 420 close to the display area Q1, and the first stack structure 510 is in contact with the second isolation structure 420.

[0130] The barrier dam DAM is arranged around the through hole T. In this embodiment, the second isolation structure 420 is located on a side of the barrier dam DAM close to the display area Q1, or the second isolation structure 420 is located on a side of the barrier dam DAM away from the display area Q1.

[0131] The pad layer 701 and the pad layer 702 are arranged around the through hole T. The pad layer 701 and the pad layer 702 are regarded as a group of pad layers, and in this embodiment, the number of the second isolation structure 420 is less than the number of the group of pad layers. A group of pad layers corresponding to the second isolation structure 420 is located on a side of the second isolation structure 420 close to the substrate 110, that is, the second isolation structure 420 and the pad layer 701 and / or the pad layer 702 overlap in the orthographic projection toward the substrate 110.

[0132] Referring to FIG. 2, the pixel circuit layer 120 includes a plurality of metal layers stacked in a direction perpendicular to the substrate 110, the pad layer 701 is the same as the GT1 material and is disposed in the same layer, and the pad layer 702 is the same as the second gate layer GT2 material and is disposed in the same layer. In this embodiment, the display panel 1001 includes four groups of pad layers, each group of pad layers includes the pad layer 701 and the pad layer 702 stacked in a direction perpendicular to the substrate 110, and the pad layer 702 is located on a side of the pad layer 701 away from the substrate 110. For example, the side of the barrier dam DAM close to the display area Q1 includes two groups of pad layers, and the side of the barrier dam DAM away from the display area Q1 includes two groups of pad layers.

[0133] The anti-cracking structure 801 is disposed around the through hole T, for example, between the through hole T and the pad layer farthest away from the display area Q1. Referring to FIG. 2, the anti-cracking structure 801 is the same as one or more interlayer dielectric layer materials included in the pixel circuit layer 120.

[0134] In this embodiment, the number of the second isolation structure 420 is reduced, and only the second isolation structure 420 at the boundary position of the first stack structure 510 away from the display area Q1 is reserved, which is beneficial to improve the flatness of the first encapsulation layer 301, avoid the first encapsulation layer 301 being broken on both sides of the second isolation structure 420 due to the height difference at the second isolation structure 420, and thus avoid the encapsulation failure, and is beneficial to prolong the service life of the display panel 1001.

[0135] FIG. 13 is a structural diagram of a display panel provided by some embodiments of the present disclosure, the display panel 1001 includes the first isolation structure 410, the sub-pixel 600 in the display area Q1, the barrier dam DAM, the first stack structure 510, the pad layer 701, the pad layer 702, and the anti-cracking structure 801 in the transition area Q22. The first isolation structure 410 includes a plurality of openings, the plurality of openings include a first opening; one sub-pixel 600 is located in one opening, and the sub-pixel 600 includes, for example, a first color sub-pixel 601, which is located in the first opening. The sub-pixel 600 includes the light-emitting material layer 202, the second electrode 203, and the first encapsulation layer 301 stacked in a direction away from the substrate 110, the first stack structure 510 includes the first thin film 501, the second thin film 502, and the third thin film 503 stacked in a direction away from the substrate 110, the first thin film 501, the second thin film 502, and the third thin film 503 of the first stack structure 510 are respectively the same as the light-emitting material layer 202, the second electrode 203, and the first encapsulation layer 301 of the first color sub-pixel 601 in material; and the first stack structure 510 has a spacing between the boundary away from the display area Q1 and the boundary of the through hole T.

[0136] The barrier dam DAM is arranged around the through hole T. In some embodiments, the first stack structure 510 is located on the side of the barrier dam DAM close to the display area Q1 away from the boundary of the display area Q1, or the first stack structure 510 is located on the side of the barrier dam DAM away from the display area Q1 away from the boundary of the display area Q1. In the first stack structure 510, the first thin film 501, the second thin film 502, and the third thin film 503 are flush with the boundary of the display area Q1.

[0137] In some embodiments, the light-emitting material layer 202 further comprises at least one common layer, wherein the common layer comprises one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. The position of the common layer can refer to the previous description, which will not be repeated here. Therefore, the above-mentioned "in the first stack structure 510, the first thin film 501, the second thin film 502, and the third thin film 503 are flush with the boundary of the display area Q1" can further comprise that at least one common layer in the light-emitting material layer 202 is flush with the boundary of the first thin film 501 and the third thin film 503 away from the boundary of the display area Q1.

[0138] The cushion layer 701 and the cushion layer 702 are arranged around the through hole T. The cushion layer 701 and the cushion layer 702 are regarded as a group of cushion layers, and in the embodiment, the number of the second isolation structures 420 is less than the number of the group of cushion layers. The group of cushion layers corresponding to the second isolation structure 420 is located on the side of the second isolation structure 420 close to the substrate 110, that is, the second isolation structure 420 and the cushion layer 701 and / or the cushion layer 702 overlap in the orthographic projection toward the substrate 110.

[0139] Referring to FIG. 2, the pixel circuit layer 120 comprises a plurality of metal layers arranged in a vertical direction to the substrate 110, the cushion layer 701 is the same as and arranged in the same layer as the GT1 material, and the cushion layer 702 is the same as and arranged in the same layer as the second gate layer GT2 material. In the embodiment, the display panel 1001 comprises four groups of cushion layers, each group of cushion layers comprising the cushion layer 701 and the cushion layer 702 arranged in a vertical direction to the substrate 110, and the cushion layer 702 is located on the side of the cushion layer 701 away from the substrate 110. For example, two groups of cushion layers are arranged on the side of the barrier dam DAM close to the display area Q1, and two groups of cushion layers are arranged on the side of the barrier dam DAM away from the display area Q1.

[0140] The anti-cracking structure 801 is arranged around the through hole T, for example, between the through hole T and the cushion layer farthest from the display area Q1. Referring to FIG. 2, the anti-cracking structure 801 is the same as one or more interlayer dielectric layer materials included in the pixel circuit layer 120.

[0141] In the embodiment, the second isolation structure 420 is not included, which is beneficial to improve the flatness of the first encapsulation layer 301, avoid the first encapsulation layer 301 being broken on both sides of the second isolation structure 420 due to the height difference at the second isolation structure 420, and thus causing the encapsulation failure, and is beneficial to prolong the service life of the display panel 1001. Meanwhile, the pad layers 701 and 702 are both made of metal material and are annular around the through hole T, and the toughness and ductility of the metal can effectively improve the structural strength of the display panel 1001.

[0142] FIG. 14 is a structural diagram of a display panel provided by some embodiments of the present disclosure, the display panel 1001 including a first isolation structure 410, a sub-pixel 600 in a display area Q1, a second isolation structure 420, a blocking dam DAM, a first laminated structure 510, a pad layer 701, a pad layer 702 and an anti-crack structure 801 in a transition area Q22. The first isolation structure 410 includes a plurality of openings, and the plurality of openings include a first opening; one sub-pixel 600 is located in one opening, and the sub-pixel 600 includes, for example, a first color sub-pixel 601 located in the first opening. The sub-pixel 600 includes a light-emitting material layer 202, a second electrode 203 and a first encapsulation layer 301 stacked in a direction away from the substrate 110, the first laminated structure 510 includes a first thin film 501, a second thin film 502 and a third thin film 503 stacked in a direction away from the substrate 110, the first thin film 501, the second thin film 502 and the third thin film 503 of the first laminated structure 510 are respectively made of the same material as the light-emitting material layer 202, the second electrode 203 and the first encapsulation layer 301 of the first color sub-pixel 601; and the first laminated structure 510 has a spacing between the boundary away from the display area Q1 and the boundary of the through hole T.

[0143] The second isolation structure 420 is arranged around the through hole T. The second isolation structure 420 is made of the same material as the first isolation structure 410, and the second isolation structure 420 also includes a first isolation layer 401, a second isolation layer 402 and a third isolation layer 403. For example, in the first isolation structure 410 or the second isolation structure 420, the edge of the third isolation layer 403 protrudes in a direction away from the second isolation layer 402 compared with the second isolation layer 402. In the embodiment, the display panel 1001 includes a plurality of second isolation structures 420, for example, 4 second isolation structures 420.

[0144] The barrier dam DAM is disposed around the through hole T. Exemplarily, two second isolation structures 420 are included on the side of the barrier dam DAM close to the display area Q1, and two second isolation structures 420 are included on the side of the barrier dam DAM away from the display area Q1. The boundary of the first stack structure 510 is located on the side of the barrier dam DAM close to the display area Q1, that is, the boundary of the first stack structure 510 away from the display area Q1 is located on the side of the two second isolation structures 420 included on the side of the barrier dam DAM close to the display area Q1, and the first thin film 501 is in contact with any one of the second isolation structures 420 on the side close to the display area Q1.

[0145] The cushion layer 701 and the cushion layer 702 are disposed around the through hole T. The cushion layer 701 and the cushion layer 702 are regarded as a group of cushion layers, and the group of cushion layers is disposed corresponding to one second isolation structure 420 and is located on the side of the second isolation structure 420 close to the substrate 110, that is, the second isolation structure 420 and the cushion layer 701 and / or the cushion layer 702 overlap in the orthographic projection toward the substrate 110.

[0146] Referring to FIG. 2, the pixel circuit layer 120 includes a plurality of metal layers disposed in a vertical direction to the substrate 110. The cushion layer 701 is made of the same material as the GT1 and is disposed in the same layer. The cushion layer 702 is made of the same material as the second gate layer GT2 and is disposed in the same layer. In this embodiment, the display panel 1001 includes four groups of cushion layers, each group of cushion layers including the cushion layer 701 and the cushion layer 702 disposed in a vertical direction to the substrate 110, and the cushion layer 702 is located on the side of the cushion layer 701 away from the substrate 110. Exemplarily, two groups of cushion layers are included on the side of the barrier dam DAM close to the display area Q1, and two groups of cushion layers are included on the side of the barrier dam DAM away from the display area Q1.

[0147] The anti-crack structure 801 is disposed around the through hole T. The anti-crack structure 801 is located, for example, between the through hole T and the cushion layer farthest away from the display area Q1. Referring to FIG. 2, the anti-crack structure 801 is made of the same material as one or more interlayer dielectric layers included in the pixel circuit layer 120. In some embodiments, the interlayer dielectric layer is selected from an inorganic layer, and the inorganic layer has a second spacing between the boundary away from the display area Q1 and the through hole T. Assuming that the spacing between the boundary of the first stack structure 510 away from the display area Q1 and the through hole T is a first spacing, the first spacing is greater than the second spacing. Removing the inorganic layer between the anti-crack structure 801 and the through hole T can prevent the transmission of defects such as cracks along the inorganic layer to the display area Q1.

[0148] FIG. 15 is a structural diagram of a display panel according to some embodiments of the present disclosure. The display panel 1001 includes a first isolation structure 410 in a display area Q1, a sub-pixel 600, a second isolation structure 420 in a transition area Q22, a barrier dam DAM, a first stack structure 510, a pad layer 701, a pad layer 702, a pad layer 703, and an anti-crack structure 801. The first isolation structure 410 includes a plurality of openings, and the plurality of openings includes a first opening. One sub-pixel 600 is located in one opening. The sub-pixel 600 includes, for example, a first color sub-pixel 601 located in the first opening. The sub-pixel 600 includes a light-emitting material layer 202, a second electrode 203, and a first encapsulation layer 301 stacked in a direction away from the substrate 110. The first stack structure 510 includes a first thin film 501, a second thin film 502, and a third thin film 503 stacked in a direction away from the substrate 110. The first thin film 501, the second thin film 502, and the third thin film 503 of the first stack structure 510 are made of the same material as the light-emitting material layer 202, the second electrode 203, and the first encapsulation layer 301 of the first color sub-pixel 601, respectively. The first stack structure 510 has a spacing between a boundary of the first stack structure 510 away from a boundary of the display area Q1 and a boundary of the through hole T.

[0149] The second isolation structure 420 is disposed around the through hole T. The second isolation structure 420 is made of the same material as the first isolation structure 410. The second isolation structure 420 also includes a first isolation layer 401, a second isolation layer 402, and a third isolation layer 403. In some embodiments, an edge of the third isolation layer 403 of the first isolation structure 410 or the second isolation structure 420 extends away from the second isolation layer 402. In some embodiments, the display panel 1001 includes a plurality of second isolation structures 420, for example, four second isolation structures 420.

[0150] The barrier dam DAM is disposed around the through hole T. In some embodiments, the barrier dam DAM includes two second isolation structures 420 on a side of the barrier dam DAM close to the display area Q1 and two second isolation structures 420 on a side of the barrier dam DAM away from the display area Q1. A boundary of the first stack structure 510 is located on the side of the barrier dam DAM close to the display area Q1, for example. That is, a boundary of the first stack structure 510 away from a boundary of the display area Q1 is located on the side of the two second isolation structures 420 included in the barrier dam DAM close to the display area Q1. The first thin film 501 is in contact with any one of the second isolation structures 420 on the side of the barrier dam DAM close to the display area Q1.

[0151] The cushion layer 701, the cushion layer 702, and the cushion layer 703 are arranged around the through hole T. The cushion layer 701, the cushion layer 702, and the cushion layer 703 are regarded as a group of cushion layers, the group of cushion layers is arranged corresponding to one second isolation structure 420, and the group of cushion layers is located at a side of the second isolation structure 420 close to the substrate 110, that is, the second isolation structure 420 and the cushion layer 701 and / or the cushion layer 702 and / or the cushion layer 703 overlap in the orthographic projection toward the substrate 110.

[0152] Referring to FIG. 2, the pixel circuit layer 120 includes a plurality of metal layers arranged in a direction perpendicular to the substrate 110, for example, the pixel circuit layer 120 includes GT1, a second gate layer GT2, and in some embodiments, the pixel circuit layer 120 further includes a third gate layer GT3. The second gate layer GT2 is located at a side of the GT1 away from the substrate 110, and the third gate layer GT3 is located at a side of the second gate layer GT2 away from the substrate 110. The cushion layer 701 is the same as the GT1 in material and is arranged in the same layer, the cushion layer 702 is the same as the second gate layer GT2 in material and is arranged in the same layer, and the cushion layer 703 is the same as the third gate layer GT3 in material and is arranged in the same layer.

[0153] In some embodiments, the pixel circuit layer 120 further includes a light shielding metal layer located at a side of the GT1 close to the substrate 110, and the group of cushion layers further includes a cushion layer 704, which is the same as the light shielding metal layer in material and is arranged in the same layer.

[0154] Increasing the number of cushion layers in a direction perpendicular to the substrate 110 can further improve the structural strength of the display panel 1001.

[0155] In the embodiment, the display panel 1001 includes four groups of cushion layers, each group of cushion layers includes the cushion layer 701 and the cushion layer 702 arranged in a direction perpendicular to the substrate 110, and the cushion layer 702 is located at a side of the cushion layer 701 away from the substrate 110. For example, two groups of cushion layers are included at a side of the blocking dam DAM close to the display area Q1, and two groups of cushion layers are included at a side of the blocking dam DAM away from the display area Q1.

[0156] The anti-cracking structure 801 is arranged around the through hole T, for example, between the through hole T and the cushion layer farthest from the display area Q1. Referring to FIG. 2, the anti-cracking structure 801 is the same as one or more interlayer dielectric layers included in the pixel circuit layer 120 in material. In some embodiments, the interlayer dielectric layer is selected from an inorganic layer.

[0157] FIG. 16A is a structural diagram of a display panel 1001 including a first isolation structure 410 located in a display area Q1, a sub-pixel 600, a second isolation structure 420 located in a transition area Q22, a barrier dam DAM, a first stack structure 510, a pad layer 701, a pad layer 702, and a crack prevention structure 801, according to some embodiments of the present disclosure. The first isolation structure 410 includes a plurality of openings, and the plurality of openings includes a first opening; one sub-pixel 600 is located in one opening, and the sub-pixel 600 includes, for example, a first color sub-pixel 601 located in the first opening. The sub-pixel 600 includes a light-emitting material layer 202, a second electrode 203, and a first encapsulation layer 301 stacked in a direction away from the substrate 110, the first stack structure 510 includes a first thin film 501, a second thin film 502, and a third thin film 503 stacked in a direction away from the substrate 110, the first thin film 501, the second thin film 502, and the third thin film 503 of the first stack structure 510 are made of the same material as the light-emitting material layer 202, the second electrode 203, and the first encapsulation layer 301 of the first color sub-pixel 601, respectively; and the first stack structure 510 has a spacing between a boundary of the first stack structure 510 away from the display area Q1 and a boundary of the through hole T.

[0158] The second isolation structure 420 is disposed around the through hole T. The second isolation structure 420 is made of the same material as the first isolation structure 410, and the second isolation structure 420 also includes a first isolation layer 401, a second isolation layer 402, and a third isolation layer 403. For example, in the first isolation structure 410 or the second isolation structure 420, the edge of the third isolation layer 403 protrudes away from the second isolation layer 402. In this embodiment, the display panel 1001 includes a plurality of second isolation structures 420, for example, 4 second isolation structures 420.

[0159] The barrier dam DAM is disposed around the through hole T. For example, the barrier dam DAM includes two second isolation structures 420 on a side of the barrier dam DAM close to the display area Q1, and includes two second isolation structures 420 on a side of the barrier dam DAM away from the display area Q1. The boundary of the first stack structure 510 is located, for example, on the side of the barrier dam DAM close to the display area Q1, that is, the boundary of the first stack structure 510 away from the display area Q1 is located on the side of the two second isolation structures 420 included in the barrier dam DAM close to the display area Q1, and the first thin film 501 is in contact with any one of the second isolation structures 420 on the side close to the display area Q1.

[0160] The cushion layer 701 and the cushion layer 702 are arranged around the through hole T. Referring to FIG. 2, the pixel circuit layer 120 includes a plurality of metal layers arranged in a direction perpendicular to the substrate 110, the cushion layer 701 is the same as the GT1 material and is arranged in the same layer, and the cushion layer 702 is the same as the GT2 material and is arranged in the same layer. The cushion layer 701 and the cushion layer 702 are regarded as a group of cushion layers, a group of cushion layers is arranged corresponding to one second isolation structure 420, and a group of cushion layers is located on a side of the second isolation structure 420 close to the substrate 110, that is, the second isolation structure 420 and the cushion layer 701 and / or the cushion layer 702 overlap in the orthographic projection toward the substrate 110.

[0161] In some embodiments, the cushion layer 701 and the cushion layer 702 are alternately arranged in a direction perpendicular to the substrate 110, as shown in FIG. 16B. For the convenience of description, the second isolation structure is not shown in FIG. 16B. It can be seen that, in some embodiments, the transition area Q22 of the display panel 1001 includes the anti-crack structure 801, two groups of cushion layers, the blocking dam DAM, and two groups of cushion layers around the through hole T and gradually close to the display area Q1. Since each group of cushion layers is alternately arranged in a direction perpendicular to the substrate 110, the cushion layer 701 and the cushion layer 702 can be seen to be sequentially sleeved in a direction parallel to the substrate in FIG. 16B.

[0162] In the present embodiment, the display panel 1001 includes four groups of cushion layers, each group of cushion layers includes the cushion layer 701 and the cushion layer 702 arranged in a direction perpendicular to the substrate 110, and the cushion layer 702 is located on a side of the cushion layer 701 away from the substrate 110. For example, two groups of cushion layers are included on a side of the blocking dam DAM close to the display area Q1, and two groups of cushion layers are included on a side of the blocking dam DAM away from the display area Q1.

[0163] The anti-crack structure 801 is arranged around the through hole T, for example, between the through hole T and the cushion layer farthest from the display area Q1. Referring to FIG. 2, the anti-crack structure 801 is the same as one or more interlayer dielectric layer materials included in the pixel circuit layer 120. In some embodiments, the interlayer dielectric layer is selected from an inorganic layer.

[0164] The plurality of cushion layers staggered in a direction perpendicular to the substrate 110 are approximately continuous in a direction parallel to the substrate, which can further improve the structural strength of the display panel 1001.

[0165] FIG. 17 is another structure diagram of the display panel 1001 at the through hole in some embodiments of the present disclosure. The transition area Q22 of the display panel 1001 includes the anti-crack structure 801, two groups of cushion layers, the blocking dam DAM, and two groups of cushion layers around the through hole T and gradually close to the display area Q1. Here, the cushion layer 702 is taken as an example for description. For the convenience of description, the cushion layer 701 is not shown in the figure, which is blocked or partially blocked by the cushion layer 702.

[0166] In some embodiments, the two pads 702 of the blocking dam DAM close to one side of the display area Q1 are sleeved and arranged in the radial direction of the through hole T, and the display panel 1001 further comprises a connecting portion 705 connecting the two sleeved and arranged pads 702, and the connecting portion 705 and the two pads 702 connected thereto are of the same material and arranged in the same layer. The two pads 702 of the blocking dam DAM away from the other side of the display area Q1 are arranged in the same way. For example, referring to FIG. 15, the connecting portion 705 can also be used to connect the two pads 703 and / or the two pads 704 which are sleeved and arranged in the same way. The present embodiment is not limited in this regard.

[0167] The adjacent pads sleeved in the radial direction of the through hole T in the same layer are connected by the connecting portion 705 to form a mesh structure, which further increases the structural strength of the display panel 1001 while retaining the toughness and ductility of the metal material by changing the structure. Moreover, the connecting portion 705 is of the same material as the pads in the same layer, and the preparation steps of the connecting portion 705 are compatible with the preparation steps of the pads, without the need to add additional processes.

[0168] FIGS. 18A-18C are partial enlarged views of the pads of some embodiments of the present disclosure. Referring to FIG. 16B, the pads 701 and 702 are selected from a circular shape. In some embodiments, the pads 701 and / or 702 can also be selected from a ring shape formed by other shapes, such as any one of the jagged ring shape shown in FIG. 18A, the gear ring shape shown in FIG. 18B, or the wavy line ring shape shown in FIG. 18C.

[0169] In some embodiments, the pads 701 and 702 are arranged in a staggered manner in a direction perpendicular to the substrate 110, and the center lines of the pads 701 and 702 coincide. The partial structure diagram is shown in FIGS. 19A-19C. It should be understood that the center lines of the pads 701 and 702 arranged in a staggered manner can also not coincide.

[0170] Referring to FIG. 15, the pads 703 and / or 704 can also adopt the shapes of FIGS. 18A-18C and the arrangement of FIGS. 19A-19C, which are not limited by the present disclosure.

[0171] The present disclosure also provides a preparation method of the display panel 1001. Before describing the preparation method, a pixel evaporation method provided by some embodiments of the related art will be briefly described. The flowchart is shown in FIG. 20. The pixel evaporation method comprises:

[0172] Step S101, forming an isolation structure layer on the substrate 110. The step of forming an isolation structure layer on the substrate 110 can include: forming a first isolation layer 401, a second isolation layer 402 and a third isolation layer 403 stacked in a direction perpendicular to the substrate 110 and away from the substrate 110. For example, the first isolation layer 401 is selected from PDL, the second isolation layer 402 is selected from an isolation metal layer, and the third isolation layer 403 is selected from an isolation inorganic layer. The first electrode 201 is also included on one side of the substrate 110, and the first isolation layer 401 formed covers the substrate 110 and the first electrode 201, as shown in FIG. 21.

[0173] Step S102, etching to form a first isolation structure 410. The step of etching to form a first isolation structure 410 can include: covering the selected area with a mask Mk, and removing the third isolation layer 403, the second isolation layer 402 and the first isolation layer 401 not covered by the mask Mk using an etching process, such as wet etching and / or dry etching. Specifically, dry etching is used to remove the third isolation layer 403 not covered by the mask Mk, wet etching is used to remove the second isolation layer 402 not covered by the mask Mk, and dry etching is used to remove the first isolation layer 401 not covered by the mask Mk, to form the first isolation structure 410 and a plurality of openings defined by the first isolation structure 410, as shown in FIG. 22.

[0174] Step S201, forming a first sub-pixel stack. The step of forming a first sub-pixel stack can include: forming a light-emitting material layer, an initial second electrode layer and an initial first encapsulation layer stacked in a direction perpendicular to the substrate 110 and away from the substrate 110, as shown in FIG. 23. It can be seen that the light-emitting material layer 202 and the second electrode 203 on both sides of the first isolation structure 410 in FIG. 23 are disconnected from the light-emitting material layer 202 and the second electrode 203 on the top of the first isolation structure 410 due to the height difference.

[0175] Step S202, forming a mask at the first opening. The step of forming a mask at the first opening can include: covering the photoresist Pr on the side of the first encapsulation layer 301 of the first sub-pixel stack away from the substrate 110 to cover the first opening with the mask Mk, and exposing and developing to remove the photoresist Pr not covered by the mask Mk, as shown in FIG. 24.

[0176] Step S203, etching to remove the first sub-pixel stack at the second opening and the third opening. This step can include: etching and peeling off the first sub-pixel stack not covered by the photoresist Pr, thereby forming a first color sub-pixel 601 in the first opening, as shown in FIG. 25.

[0177] Step S301, forming a second sub-pixel stack. The step of forming the second sub-pixel stack can include forming the light-emitting material layer 202, the second electrode 203 and the first encapsulation layer 301 stacked along a direction perpendicular to the substrate 110 and away from the substrate 110, as shown in FIG. 26. It can be seen that the light-emitting material layer 202 and the second electrode 203 on both sides of the first isolation structure 410 in FIG. 26 are disconnected from the light-emitting material layer 202 and the second electrode 203 on the top of the first isolation structure 410 due to the height difference, and the second sub-pixel stack covers the first color sub-pixel 601 at the first opening.

[0178] Step S302, forming a mask at the second opening. The step of forming the mask at the second opening can include covering the photoresist Pr on the side of the first encapsulation layer 301 of the second sub-pixel stack away from the substrate 110 to cover the second opening with the mask Mk, and exposing and developing to remove the photoresist Pr not covered by the mask Mk, as shown in FIG. 27.

[0179] Step S303, etching to remove the second sub-pixel stack at the first opening and the third opening. The step can include etching and peeling off the second sub-pixel stack not covered by the photoresist Pr, thereby forming the second color sub-pixel 602 in the second opening, as shown in FIG. 28. For example, the light-emitting material layer 202 of the second color sub-pixel 602 uses a different light-emitting material from the light-emitting material layer 202 of the first color sub-pixel 601.

[0180] Step S401, forming a third sub-pixel stack. The step of forming the third sub-pixel stack can include forming the light-emitting material layer 202, the second electrode 203 and the first encapsulation layer 301 stacked along a direction perpendicular to the substrate 110 and away from the substrate 110, as shown in FIG. 29. It can be seen that the light-emitting material layer 202 and the second electrode 203 on both sides of the first isolation structure 410 in FIG. 29 are disconnected from the light-emitting material layer 202 and the second electrode 203 on the top of the first isolation structure 410 due to the height difference, and the third sub-pixel stack covers the first color sub-pixel 601 at the first opening and the second color sub-pixel 602 at the second opening.

[0181] Step S402, forming a mask at the third opening. The step of forming the mask at the third opening can include covering the photoresist Pr on the side of the first encapsulation layer 301 of the third sub-pixel stack away from the substrate 110 to cover the third opening with the mask Mk, and exposing and developing to remove the photoresist Pr not covered by the mask Mk, as shown in FIG. 30.

[0182] At step S403, the third sub-pixel stack at the first opening and the second opening is etched and removed. This step can include etching and stripping the third sub-pixel stack not covered by the photoresist Pr, so as to form a third color sub-pixel 603 in the third opening, as shown in FIG. 31. Exemplarily, the light-emitting material layer 202 of the third color sub-pixel 603, the light-emitting material layer 202 of the first color sub-pixel 601, and the light-emitting material layer 202 of the second color sub-pixel 602 adopt different light-emitting materials.

[0183] FIG. 32 is a flowchart of a display panel preparation method according to some embodiments of the present disclosure, including:

[0184] At step S10, a first isolation structure is formed on the substrate 110.

[0185] At step S20, a first sub-pixel stack is formed.

[0186] At step S30, a mask layer is formed on a side of the first sub-pixel stack away from the substrate 110.

[0187] At step S40, based on the mask layer, the first sub-pixel stack is etched to obtain a first color sub-pixel and a first stack structure.

[0188] The preparation method of the display panel 1001 provided in this embodiment will be described in detail below in combination with FIG. 2 and FIGS. 33-43.

[0189] Before step S10, there is also step S01: forming an array substrate 100. That is, forming a pixel circuit layer 120 on the substrate 110.

[0190] Exemplarily, referring to FIG. 2, the step of forming the pixel circuit layer 120 includes sequentially forming a plurality of conductive layers, and the step of forming the plurality of conductive layers can include, for example, forming a semiconductor layer ACT, a GT1, a second gate layer GT2, a first source-drain layer SD1, and a second source-drain layer SD2 arranged in sequence in a direction perpendicular to and away from the substrate 110. The step of forming the pixel circuit layer 120 also includes forming an insulating layer between adjacent conductive layers during the formation of the plurality of conductive layers, such as forming a first gate insulating layer GI1 between the semiconductor layer ACT and the GT1, forming a second gate insulating layer GI2 between the GT1 and the second gate layer GT2, forming an interlayer dielectric layer ILD between the second gate layer GT2 and the first source-drain layer SD1, forming a passivation layer PVX and a first planarization layer PLN1 between the first source-drain layer SD1 and the second source-drain layer SD2, and forming a second planarization layer PLN2 between the second source-drain layer SD2 and the light-emitting device layer 200.

[0191] In the process of step S01, a crack prevention structure 801 is also formed in the transition area Q22 of the display panel 1001 surrounding the through hole area; it can be understood that the through hole area of the display panel 1001 is a through hole T which is penetrated in the subsequent process to install a camera or a sensor.

[0192] In the following, the embodiments of the present disclosure are introduced based on the transition area Q22. Based on the inventive idea of the present application scheme, the following introduction to the frame area Q21 is also applicable.

[0193] Step S01 includes, for example, step S01A and step S01B. In step S01A, referring to FIG. 2, FIG. 32 and FIG. 33, at least one pad layer 701 is formed in the transition area Q22 at the same time when GT1 in the pixel circuit layer 120 is formed, the at least one pad layer 701 is the same as GT1 in material and is arranged in the same layer, so that the preparation step of the at least one pad layer 701 is compatible with the preparation step of GT1, not only can simplify the process, improve the generation efficiency of the display panel 1001, but also the pad layer 701 can increase the structural strength of the display panel 1001, avoid defects such as cracks under stress in the process of cutting, assembling and transporting, and block the path of crack transmission from the transition area Q22 to the display area Q1. At least one pad layer 702 is formed in the transition area Q22 at the same time when the second gate layer GT2 in the pixel circuit layer 120 is formed, the at least one pad layer 702 is the same as GT1 in material and is arranged in the same layer, so that the preparation step of the at least one pad layer 702 is compatible with the preparation step of the second gate layer GT2, not only can simplify the process, improve the generation efficiency of the display panel 1001, but also the pad layer 702 can increase the structural strength of the display panel 1001, avoid defects such as cracks under stress in the process of cutting, assembling and transporting, and block the path of crack transmission from the transition area Q22 to the display area Q1. Finally, the pad layer 701 and the pad layer 702 as shown in FIG. 9B are formed in the transition area Q22 of the display panel 1001.

[0194] In some embodiments, the pad layer 701 and the pad layer 702 are arranged in a staggered manner in a direction perpendicular to the substrate 110, and finally the pad layer 701 and the pad layer 702 as shown in FIG. 16A and FIG. 18B are formed.

[0195] In some embodiments, when the pad layer 701 and / or the pad layer 702 are formed, the pad layer 701 and / or the pad layer 702 can also be patterned, the shape thereof is changed, or a connecting portion is added between two pad layers 701 which are sleeved along the through hole area and adjacent to each other, and finally the pad layer 701 and the pad layer 702 as shown in FIG. 17 to FIG. 19C are formed.

[0196] In some embodiments, the display panel 1001 employs LTPO (Low Temperature Polycrystalline Oxide) technology, i.e., the display panel 1001 includes both Low Temperature Poly-Silicon (LTPS) thin film transistors and oxide thin film transistors. In this case, the material forming the semiconductor layer ACT is selected from, for example, low temperature poly-silicon, and the display panel 1001 further includes an oxide semiconductor layer and a third gate layer GT3, the oxide semiconductor layer being located on the side of the second gate layer GT2 away from the substrate 110, and the third gate layer GT3 being located on the side of the oxide semiconductor layer away from the substrate. Then, the step S01A further includes: forming at least one pad layer 703 in the transition region Q22, the at least one pad layer 703 being made of the same material as and being disposed in the same layer as the third gate layer GT3, so that the preparation step of the at least one pad layer 703 is compatible with the preparation step of the third gate layer GT3.

[0197] In some embodiments, when the pixel circuit layer 120 further includes a light shielding metal layer BSM (Bottom Shielding Metal) located on the side of the first gate layer GT1 close to the substrate 110, a light shielding pattern is formed in the pixel circuit layer 120 on the side of the thin film transistor TFT close to the substrate 110 to shield the light incident from the side of the substrate 110, so as to avoid the incident light from irradiating the semiconductor layer ACT and causing adverse effects on the thin film transistor TFT. In this case, the step S01A further includes: forming at least one pad layer 704 in the transition region Q22, the at least one pad layer 704 being made of the same material as and being disposed in the same layer as the light shielding metal layer BSM, so that the preparation step of the at least one pad layer 704 is compatible with the preparation step of the light shielding metal layer BSM. Finally, the pad layers 701, 702, 703 and 704 shown in FIG. 15 are formed in the transition region Q22 of the display panel 1001.

[0198] In the step S01B, the planar layer PLN in the transition region Q22 is etched to form the blocking dam DAM, and the anti-crack structure 801 surrounding the through-hole region is formed in one or more inorganic layers in the transition region Q22, so as to avoid defects such as cracks caused by stress during cutting, module assembly or transportation from being transmitted to the display region Q1.

[0199] In some embodiments, the inorganic layer adjacent to the through-hole T in the transition region Q22 is removed, and the display panel 1001 shown in FIG. 14 is formed.

[0200] In the step S10, forming the first isolation structure 410 on the substrate 110 includes the step S10A and the step S10B.

[0201] In step S10A, an isolation structure layer is formed on the substrate 110. Specifically, the first isolation layer 401, the second isolation layer 402, and the third isolation layer 403 are formed in a stacked manner along a direction perpendicular to and away from the substrate 110. For example, the first isolation layer 401 is selected from a PDL, the second isolation layer 402 is selected from an isolation metal layer, and the third isolation layer 403 is selected from an isolation inorganic layer. The first electrode 201 is further included on one side of the substrate 110. The first isolation layer 401 covers the substrate 110 and the first electrode 201. For example, the pixel circuit layer 120 is further included on the substrate 110. The first isolation layer 401, the second isolation layer 402, and the third isolation layer 403 are formed on the array substrate 100. The display panel 1001 shown in FIG. 33 is formed.

[0202] In step S10B, the selected region of the display area Q1 is covered with the mask Mk. The third isolation layer 403, the second isolation layer 402, and the first isolation layer 401 that are not covered with the mask Mk are removed by an etching process. For example, the etching process is selected from wet etching and / or dry etching. Specifically, the third isolation layer 403 that is not covered with the mask Mk is removed by dry etching, the second isolation layer 402 that is not covered with the mask Mk is removed by wet etching, and the first isolation layer 401 that is not covered with the mask Mk is removed by dry etching. The first isolation structure 410 and a plurality of openings defined by the first isolation structure 410 are formed. For example, the plurality of openings include a first opening for defining a first color sub-pixel, a second opening for defining a second color sub-pixel, and a third opening for defining a third color sub-pixel. In this embodiment, the display panel 1001 shown in FIG. 13 is finally formed.

[0203] In some embodiments, when the selected region of the display area Q1 is covered with the mask Mk, step S10B further includes covering the selected region of the transition area Q22 with the mask Mk. After the subsequent etching process is completed, the transition area Q22 forms at least one second isolation structure 420. The display panel 1001 shown in FIGS. 9B, 11, or 12 is finally formed.

[0204] After step S10 is completed, the display panel 1001 shown in FIG. 34 is formed, for example.

[0205] It should be understood that the number of the second isolation structures 420 in the transition area Q22 is not limited in the present disclosure. The number can be zero, one, or more, as shown in FIGS. 11-13.

[0206] In step S20, a first sub-pixel stack is formed. The light-emitting material layer, the initial second electrode layer and the initial first encapsulation layer are sequentially formed on the display panel 1001 shown in FIG. 34, forming the first sub-pixel stack covering the display area Q1, the transition area Q22 and the through-hole area, obtaining the display panel 1001 shown in FIG. 35.

[0207] In step S30, a mask layer is formed on the side of the first sub-pixel stack away from the substrate 110. For example, step S30 includes step S30A and step S30B. In step S30A, the photoresist Pr is coated on the side of the initial first encapsulation layer of the first sub-pixel stack away from the substrate 110 to cover the mask Mk covering the first opening and the part of the first sub-pixel stack in the transition area Q22 close to the display area Q1, and the photoresist Pr not covered by the mask Mk is removed by exposure and development, forming the display panel 1001 shown in FIG. 36.

[0208] In step S30B, the first sub-pixel stack not covered by the photoresist Pr is etched and peeled off to form the first thin film 501 located in the first opening and the first stack structure 510 located in the transition area Q22, and the first stack structure 510 has a spacing between the boundary away from the display area Q1 and the boundary of the through-hole area, obtaining the display panel 1001 shown in FIG. 37.

[0209] In some embodiments, the boundary of the first stack structure 510 away from the display area Q1 is located on the side of any second isolation structure 420 close to the display area Q1 and in contact with the second isolation structure 420.

[0210] In some embodiments, the boundaries of the first thin film 501, the second thin film 502 and the third thin film 503 are flush at the boundary of the first stack structure 510 away from the display area Q1.

[0211] In some embodiments, the first color sub-pixel 601 is selected from three primary colors, for example, selected from any one of red, green or blue. Correspondingly, the material of the second thin film 502 of the first stack structure 510 is the same as that of the light-emitting material layer 202 of the first color sub-pixel 601, which is any one of red, green or blue.

[0212] In combination with FIG. 20 and FIG. 32, it can be seen that steps S10 to S40 are basically consistent with steps S101 to S203. In step S30 of the preparation method of the display panel 1001 provided in the present application, when the mask layer is formed on the side of the first sub-pixel stack away from the substrate, step S30 not only includes forming the mask layer at the first opening, but also includes forming the mask layer in the part of the transition area Q22 close to the display area Q1. In the subsequent etching process, when the first sub-pixel stack not covered by the mask layer is removed, the first color sub-pixel 601 and the first stack structure 510 can be formed at the same time. In this way, the first thin film 501, the second thin film 502, and the third thin film 503 of the first stack structure 510 are respectively the same as and arranged in the same layer as the light-emitting material layer 202, the second electrode 203, and the first encapsulation layer 301 material of the first color sub-pixel 601. The first stack structure 510 is compatible with the first color sub-pixel 601 in the preparation step. No additional process is needed, and it can be ensured that there is no conductive path between the through hole T and the display area Q1 of the display panel 1001, preventing the risk of black spots in the hole area caused by electrochemical corrosion.

[0213] After step S30, steps S301 to S303 and steps S401 to S403 are further included, so as to form a complete light-emitting device layer 200.

[0214] In step S301, a second sub-pixel stack is formed. The step of forming the second sub-pixel stack can include: forming a light-emitting material layer, an initial second electrode layer, and an initial first encapsulation layer stacked in a direction perpendicular to the substrate 110 and away from the substrate 110, that is, forming a second sub-pixel stack covering the display area Q1, the transition area Q22, and the through hole area, to obtain a display panel 1001 as shown in FIG. 38. In FIG. 38, the second sub-pixel stack covers the first color sub-pixel 601 at the first opening and the first stack structure 510 in the transition area Q22.

[0215] In step S302, a mask layer is formed on the side of a plurality of second openings away from the substrate 110. The step of forming the mask at the second opening can include: covering the photoresist Pr on the side of the first encapsulation layer 301 of the second sub-pixel stack away from the substrate 110 to cover the second opening with the mask Mk. Expose and develop to remove the photoresist Pr not covered by the mask Mk, as shown in FIG. 39.

[0216] In step S303, the second sub-pixel stack not covered by the mask layer is etched and removed. This step can include: etching and peeling off the second sub-pixel stack not covered by the photoresist Pr, so as to form a second color sub-pixel 602 in the second opening, as shown in FIG. 40. For example, the light-emitting material layer 202 of the second color sub-pixel 602 uses a different light-emitting material from the light-emitting material layer 202 of the first color sub-pixel 601.

[0217] Step S401, forming a third sub-pixel stack. The step of forming the third sub-pixel stack can include forming a light-emitting material layer, an initial second electrode layer and an initial first encapsulation layer stacked in a direction perpendicular to the substrate 110 and away from the substrate 110, as shown in FIG. 41. The third sub-pixel stack covers the first color sub-pixel 601 at the first opening, the second color sub-pixel 602 at the second opening and the first stack structure 510 of the transition region Q22.

[0218] Step S402, forming a mask layer on the side of the third opening away from the substrate 110. The step of forming the mask on the third opening can include covering the photoresist Pr on the side of the first encapsulation layer 301 of the third sub-pixel stack away from the substrate 110 to cover the third opening with the mask Mk, and exposing and developing to remove the photoresist Pr not covered by the mask Mk, as shown in FIG. 42.

[0219] Step S403, etching to remove the third sub-pixel stack at the first opening and the second opening. This step can include etching and peeling off the third sub-pixel stack not covered by the photoresist Pr, thereby forming the third color sub-pixel 603 in the third opening, as shown in FIG. 43. Illustratively, the light-emitting material of the light-emitting material layer 202 of the third color sub-pixel 603, the light-emitting material layer 202 of the first color sub-pixel 601 and the light-emitting material layer 202 of the second color sub-pixel 602 are all different.

[0220] It should be understood that the first color sub-pixel 601, the second color sub-pixel 602 and the third color sub-pixel 603 are only used to distinguish different color sub-pixels, and do not represent the order of their formation. Illustratively, the preparation method of the display panel 1001 provided by the present disclosure can also be in the order of forming the second color sub-pixel 602, forming the first color sub-pixel 601 and the first stack structure 510, and forming the third color sub-pixel 603, or in the order of forming the third color sub-pixel 603, forming the first color sub-pixel 601 and the first stack structure 510, and forming the second color sub-pixel 602, or in the order of forming the second color sub-pixel 602, forming the third color sub-pixel 603, forming the first color sub-pixel 601 and the first stack structure 510, or in any other possible order, which is not limited by the present disclosure.

[0221] In some embodiments, for step S302, the step included therein is modified from "covering the second opening with a mask layer" to "covering the second opening and the part of the second sub-pixel stack in the transition region Q22 close to the display region Q1 with a mask layer" to form a second stack structure on the side of the first stack structure 510 away from the substrate 110.

[0222] In some embodiments, for step S402, the step included therein is modified from "covering the third opening with the mask layer" to "covering the third opening and the part of the third sub-pixel stack in the transition region Q22 close to the display region Q1 with the mask layer" to form the third stack structure on the side of the second stack structure away from the substrate 110.

[0223] Similarly, when the display panel 1001 includes the second stack structure and / or the third stack structure, the preparation method of the display panel 1001 can also follow the order of forming the second color sub-pixel 602 and the second stack structure, forming the first color sub-pixel 601 and the first stack structure 510, forming the third color sub-pixel 603, or follow the order of forming the third color sub-pixel 603, forming the first color sub-pixel 601 and the first stack structure 510, forming the second color sub-pixel 602 and the second stack structure, or follow the order of forming the second color sub-pixel 602, forming the first color sub-pixel 601 and the first stack structure 510, forming the third color sub-pixel 603 and the third stack structure, or any other possible order, and the present disclosure does not limit this.

[0224] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel provided with a through hole, the display panel comprising a display area and a transition area, the transition area surrounding the through hole, and the display area surrounding the transition area; the display panel comprising: a substrate; a first isolation structure provided on the substrate and in the display area, the first isolation structure comprising a plurality of openings; a plurality of sub-pixels, one of the sub-pixels being located in one of the openings, the sub-pixels comprising, in a direction away from the substrate, a light-emitting layer, a second electrode and a first encapsulation layer stacked in sequence, the plurality of sub-pixels comprising first color sub-pixels; and a first stack structure provided in the transition area, the first stack structure comprising, in a direction away from the substrate, a first film, a second film and a third film stacked in sequence, the first film, the second film and the third film being made of the same material as the light-emitting layer, the second electrode and the first encapsulation layer of the first color sub-pixels respectively, and the first stack structure having a spacing between a boundary of the first stack structure away from the display area and a boundary of the through hole. 2.The display panel of claim 1, further comprising: at least one second isolation structure located in the transition area, the second isolation structure surrounding the through hole; the second isolation structure being made of the same material as the first isolation structure; and the boundary of the first stack structure away from the display area being located on a side of any of the second isolation structures close to the display area, and the first stack structure being in contact with the second isolation structure. 3.The display panel of claim 2, the first isolation structure and the second isolation structure each comprising, in a direction away from the substrate, a first isolation layer, a second isolation layer and a third isolation layer stacked in sequence, an edge of the third isolation layer extending away from the second isolation layer compared with the second isolation layer; the first isolation layer, the second isolation layer and the third isolation layer of the first isolation structure being made of the same material as the first isolation layer, the second isolation layer and the third isolation layer of the second isolation structure respectively. 4.The display panel of claim 2 or 3, further comprising: a blocking dam provided in the transition area, the blocking dam surrounding the through hole; at least one of the second isolation structures being provided on a side of the blocking dam close to the display area; and / or at least one of the second isolation structures being provided on a side of the blocking dam away from the display area; and the boundary of the first stack structure away from the display area being located on the side of the blocking dam close to the display area or on the side of the blocking dam away from the display area. 6.The display panel of any one of claims 2 to 5, further comprising: a pixel circuit layer located between the substrate and the plurality of sub-pixels, the pixel circuit layer comprising a plurality of metal layers stacked in sequence in a direction perpendicular to the substrate; at least one of the metal layers being provided with at least one pad layer, the pad layer being located in the transition area and surrounding the through hole; and in an orthogonal projection onto the substrate, at least one of the pad layers being located in at least one of the second isolation structures in an overlapping manner; the blocking dam of the display panel being provided with at least one of the pad layers on a side of the blocking dam close to the display area; and / or the blocking dam of the display panel being provided with at least one of the pad layers on a side of the blocking dam away from the display area. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 5. The display panel of claim 4, wherein, ​ ​ ​ ​ ​ 7. The display panel of claim 6, wherein, ​ The barrier dam is provided with at least one pad layer away from one side of the display area.

8. The display panel of claim 6 or 7, wherein, The multi-layer metal layer comprises a first gate layer and a second gate layer stacked in a direction away from the substrate. The first gate layer is provided with at least one pad layer; and / or, The second gate layer is provided with at least one pad layer.

9. The display panel of claim 8, wherein, The multi-layer metal layer further comprises a third gate layer provided on a side of the second gate layer away from the substrate, and the third gate layer is provided with at least one pad layer; and / or, The multi-layer metal layer further comprises a light shielding metal layer provided between the substrate and the first gate layer, and the light shielding metal layer is provided with at least one pad layer.

10. The display panel according to any one of claims 6 to 9, wherein, The display panel comprises a plurality of groups of pad layers, each group of pad layers comprising a plurality of pad layers stacked in a direction perpendicular to the substrate, and each group of pad layers is provided corresponding to one second isolation structure; In the orthographic projection of the substrate, at least one pad layer in a group of pad layers overlaps the corresponding second isolation structure.

11. The display panel of claim 10, wherein, In the orthographic projection of the substrate, a plurality of pad layers belonging to the same group all overlap the corresponding second isolation structure.

12. The display panel according to any one of claims 6 to 11, wherein, At least two pad layers located in different metal layers are staggered in a direction perpendicular to the substrate.

13. The display panel according to any one of claims 6 to 12, wherein, At least two pad layers in one metal layer are sequentially sleeved and spaced in a radial direction of the via hole. The display panel further comprises: At least one connecting portion connected between two adjacent pad layers located in the same metal layer, and the connecting portion is made of the same material as the two pad layers.

14. The display panel of claim 1, further comprising: a pixel circuit layer located between the substrate and the plurality of sub-pixels, comprising a plurality of metal layers stacked in a direction perpendicular to the substrate; A plurality of pad layers are provided in at least one of the metal layers, the pad layers are located in the transition area, and the pad layers are arranged around the via hole; and the plurality of pad layers are sequentially sleeved and spaced in a radial direction of the via hole.

15. The display panel of claim 14, wherein, In the first laminated structure, the first film, the second film and the third film are flush away from the boundary of the display area.

16. The display panel of any one of claims 6-15, further comprising: a crack prevention structure arranged around the via hole; The crack prevention structure is arranged between the via hole and the pad layer farthest away from the display area.

17. The display panel of claim 16, further comprising: a multi-layer inorganic layer located between the substrate and the plurality of sub-pixels; the crack prevention structure is formed in a portion of the multi-layer inorganic layer close to the via hole; The boundary of the multi-layer inorganic layer and the boundary of the via hole have a spacing, and the spacing between the boundary of the first laminated structure and the boundary of the via hole away from the display area is greater than the spacing between the boundary of the multi-layer inorganic layer and the boundary of the via hole.

18. The display panel according to any one of claims 1 to 17, wherein, The plurality of sub-pixels comprise second color sub-pixels; The display panel further comprises: A second stack structure is disposed on a side of the first stack structure away from the substrate, the second stack structure comprising a first thin film, a second thin film and a third thin film stacked in a direction away from the substrate, the first thin film, the second thin film and the third thin film of the second stack structure being respectively the same as the light-emitting layer, the second electrode and the material of the first encapsulation layer of the second color sub-pixel; and the second stack structure having a spacing between a side thereof away from the boundary of the display area and the boundary of the via hole.

19. A display device comprising: the display panel according to any one of claims 1-18; and a circuit board connected to the display panel.

20. A method for manufacturing a display panel, the display panel comprising a display area, a transition area and a via hole area, the transition area surrounding the via hole area, and the display area surrounding the transition area; the method comprising: forming a first isolation structure on a substrate, the first isolation structure being located in the display area, the first isolation structure comprising a plurality of openings, the plurality of openings comprising a plurality of first openings for defining first color sub-pixels; forming a first sub-pixel stack, the first sub-pixel stack being located in the display area, the transition area and the via hole area, the first sub-pixel stack comprising a light-emitting material layer, an initial second electrode layer and an initial first encapsulation layer stacked in a direction away from the substrate; forming a mask layer on a side of the first sub-pixel stack away from the substrate, the mask layer covering the plurality of first openings and a portion of the transition area close to the display area; based on the mask layer, etching the first sub-pixel stack, the first sub-pixel stack remaining in the plurality of first openings forming first color sub-pixels, and the first sub-pixel stack remaining in the portion of the transition area close to the display area forming a first stack structure; the first stack structure having a spacing between a side thereof away from the boundary of the display area and the boundary of the via hole area.

Images