Gallium nitride-based enhancement mode power device and preparation method therefor

Abstract

The present application provides a gallium nitride-based enhancement mode power device, and a preparation method therefor. The gallium nitride-based enhancement mode power device may comprise: a substrate; a heterostructure, the heterostructure comprising a gallium nitride buffer layer, an Al(In, Ga)N barrier layer, and an (In)GaN ohmic contact layer, formed on the substrate in sequence along a direction away from the substrate, the Al(In, Ga)N barrier layer being made of a group III alloy nitride, and the (In)GaN ohmic contact layer comprising a gallium nitride base material and an n-type dopant; an electrode layer, the electrode layer being formed at a side of the heterostructure distant from the substrate, and comprising a source electrode, a drain electrode, a gate electrode, and a gate dielectric layer between the gate electrode and the heterostructure. The gallium nitride-based enhancement mode power device has a relatively high current conduction capability, and is suitable for preparing a nitride-based low-voltage power device and a radio frequency device, and for integration between the nitride-based low-voltage power device and the radio frequency device.

Description

Gallium nitride-based enhancement-mode power device and preparation method thereof TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductors, and particularly relates to a gallium nitride-based enhancement-mode power device and a preparation method thereof. BACKGROUND

[0002] High-electron-mobility transistors (HEMTs) based on gallium nitride (GaN) heterojunctions have become an excellent choice for the next generation of radio frequency and power devices due to their high-density two-dimensional electron gas (2-D Electron Gas, 2DEG), high breakdown voltage, and high power density.

[0003] However, due to the high-density 2DEG induced by the polarization of the gallium nitride-based heterojunction, the gallium nitride-based HEMT is a natural depletion-mode semiconductor device. The enhancement-mode power device can avoid negative voltage shutdown, has the characteristics of safe failure, improves system reliability, and realizes board-level integration, and the UTB-Al(In,Ga)N / GaN heterojunction can realize intrinsic enhancement-mode power devices. At present, the application of gallium nitride power devices in the low-voltage radio frequency and power field has also become a trend. Low operating voltage requires low on-resistance to meet certain current capacity, so the ohmic contact resistance and drift region resistance of the device must be reduced. However, the reduction of 2DEG concentration in thin barrier devices increases the difficulty of ohmic contact fabrication and leads to an increase in drift region resistance. The heavily doped n-type (In) GaN layer can effectively reduce the ohmic contact resistance, and the scaling of the device can reduce the drift region length and thus reduce the drift region resistance.

[0004] It should be noted that the above statements are only used to provide background technical information related to the present application, and do not necessarily constitute prior art.

[0005] SUMMARY

[0006] The present application proposes a gallium nitride-based enhancement-mode power device and a preparation method thereof. The gallium nitride-based enhancement-mode power device has a lower on-resistance and is suitable for low operating voltage fields.

[0007] The first aspect of the present application proposes a gallium nitride-based enhancement-mode power device, comprising:

[0008] a substrate;

[0009] The heterostructure comprises, in sequence from the substrate, a gallium nitride buffer layer, an Al(In,Ga)N barrier layer, and an (In)GaN ohmic contact layer formed on the substrate in a direction away from the substrate; the Al(In,Ga)N barrier layer is made of a Group III alloy nitride, and the (In)GaN ohmic contact layer comprises a gallium nitride base and an n-type dopant;

[0010] The electrode layer is formed on a side of the heterostructure away from the substrate, and comprises a source electrode, a drain electrode, a gate electrode, and a gate dielectric layer between the gate electrode and the heterostructure.

[0011] In some embodiments of the present application, the thickness of the Al(In,Ga)N barrier layer is greater than 1 nm and less than 10 nm.

[0012] In some embodiments of the present application, the material of the Al(In,Ga)N barrier layer comprises a ternary alloy of aluminum, gallium, and nitrogen, wherein the proportion of aluminum is greater than 0% and less than 100% of the total metal elements; or,

[0013] The material of the Al(In,Ga)N barrier layer comprises a ternary alloy of aluminum, indium, and nitrogen, wherein the proportion of aluminum is greater than or equal to 75% and less than or equal to 90% of the total metal elements; or,

[0014] The material of the Al(In,Ga)N barrier layer comprises a quaternary alloy of aluminum, indium, gallium, and nitrogen, wherein the proportion of aluminum and the proportion of indium are both greater than 0% and less than 100% of the total metal elements.

[0015] In some embodiments of the present application, the gallium nitride base of the (In)GaN ohmic contact layer comprises a binary alloy of gallium and nitrogen or a ternary alloy of indium, gallium, and nitrogen, and the thickness of the (In)GaN ohmic contact layer is greater than or equal to 5 nm and less than or equal to 200 nm.

[0016] In some embodiments of the present application, the doping concentration of the (In)GaN ohmic contact layer is greater than or equal to 1×1018cm-3 and less than or equal to 1×1020cm-3. 17 cm -3 20 cm -3 .

[0017] In some embodiments of the present application, the gate metal covers the entire gate trench, and the depth of the gate trench includes etching to the interface between the gallium nitride buffer layer and the Al(In,Ga)N barrier layer, or the interface between the Al(In,Ga)N barrier layer and the (In)GaN ohmic contact layer.​

[0018] In some embodiments of the present application, the gate dielectric layer comprises a single-layer gate dielectric layer or a composite gate dielectric layer.

[0019] In some embodiments of the present application, the single-layer gate dielectric layer is a high-insulating gate dielectric layer, comprising any one of Al2O3, SiN x , SiO2, NiO, Ga x O 1-x N, Al x Si 1-x O or Al x Si 1-x N.

[0020] In some embodiments of the present application, the thickness of the single-layer gate dielectric layer is greater than or equal to 5 nm and less than or equal to 40 nm.

[0021] In some embodiments of the present application, the composite gate dielectric layer comprises a dielectric insertion layer and a high-insulating gate dielectric layer, the dielectric insertion layer being in contact with the heterostructure, and the high-insulating layer being in contact with the gate metal.

[0022] In some embodiments of the present application, the thickness of the dielectric insertion layer is less than or equal to 5 nm, for reducing the interface state density between the high-insulating gate dielectric layer and the III-nitride layer structure.

[0023] In some embodiments of the present application, the dielectric insertion layer is any one of a single-crystal, a polycrystal or an amorphous dielectric, comprising any one of AlN, SiN x , Ga2O3 or Ga x O 1-x N.

[0024] Embodiments of the second aspect of the present application provide a method for manufacturing a gallium nitride-based enhancement-mode power device, the method comprising:

[0025] manufacturing a substrate;

[0026] forming a heterostructure on the substrate, comprising: sequentially forming a gallium nitride buffer layer and an Al(In, Ga)N barrier layer on the substrate in a direction away from the substrate, and epitaxially growing an (In)GaN ohmic contact layer on the Al(In, Ga)N barrier layer; the Al(In, Ga)N barrier layer is made of a III-alloy nitride, and the (In)GaN ohmic contact layer comprises a gallium nitride-based material and an n-type dopant;

[0027] forming an electrode layer on the side of the heterostructure away from the substrate, the electrode layer comprising a source electrode, a drain electrode, a gate electrode, and a gate dielectric layer between the gate electrode and the heterostructure.

[0028] The technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0029] The gallium nitride-based enhancement-mode power device provided by the embodiments of the present application comprises a substrate, a heterostructure and an electrode layer, the heterostructure is based on a heavily doped n-type gallium nitride-based heterojunction, and a low-voltage gallium nitride-based enhancement-mode power device with an Al(In, Ga)N barrier layer without a drift region is formed, so that the on-resistance of the gallium nitride-based enhancement-mode power device is effectively reduced, the gallium nitride-based enhancement-mode power device has sufficient current on ability under low-voltage driving, and has good threshold voltage (Vth) uniformity and high power performance. BRIEF DESCRIPTION OF DRAWINGS

[0030] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not intended to limit the scope of the present application. Moreover, the same reference numerals in different figures represent the same or similar components.

[0031] In the drawings:

[0032] FIG. 1 shows a structure schematic diagram of a gallium nitride-based enhancement-mode power device provided by an embodiment of the present application;

[0033] FIG. 2 shows another structure schematic diagram of a gallium nitride-based enhancement-mode power device provided by an embodiment of the present application;

[0034] FIG. 3 shows a flow schematic diagram of a preparation method of a gallium nitride-based enhancement-mode power device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0035] Exemplary embodiments of the present application will be described in detail with reference to the drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thoroughly and completely understood, and so that the scope of the present application will be fully conveyed to those skilled in the art.

[0036] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in the present application should be understood as the common meanings understood by those skilled in the art to which the present application belongs.

[0037] According to different field effect principles, the semiconductor power device can be divided into depletion type and enhancement type. The depletion type semiconductor power device has a large drain current because there is a conduction channel between the source and the drain when the gate voltage is zero. The enhancement type semiconductor power device has no conduction channel when the gate voltage is zero, so the drain current is zero. A certain gate voltage is needed to form a conduction channel between the source and the drain, and the device has a drain current.

[0038] In the related art, although the gallium nitride-based power device has excellent electrical properties such as high breakdown voltage and high power density, the high-density and high-mobility 2DEG makes the gallium nitride-based HEMT a natural depletion type semiconductor device. The depletion type semiconductor device may need a negative gate voltage to be turned off, which may be inconvenient or less efficient in some circuit designs. The enhancement type power device can avoid negative voltage turn-off and has the characteristics of safe failure, which can improve system reliability and realize board-level integration, and is more suitable for low-voltage driving scenarios.

[0039] To solve the above problems, the embodiment of the present application provides a gallium nitride-based enhancement type power device and a preparation method thereof. The gallium nitride-based enhancement type power device is based on a heavily doped n-type gallium nitride-based heterojunction, and forms a low-voltage gallium nitride-based enhancement type power device with a drift-free Al(In, Ga)N barrier layer. The on-resistance of the gallium nitride-based enhancement type power device is effectively reduced, so that the gallium nitride-based enhancement type power device also has sufficient current conduction capability under low-voltage driving, as well as good threshold voltage (Vth) uniformity and high power performance.

[0040] The threshold voltage refers to the minimum gate voltage required to form a conduction channel in the power device.

[0041] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0042] Embodiment one

[0043] Please refer to FIG. 1, which is a structure schematic diagram of the gallium nitride-based enhancement type power device provided by the embodiment of the present application. As shown in FIG. 1, the gallium nitride-based enhancement type power device includes a substrate 10, a heterostructure 20 and an electrode layer. The heterostructure 20 includes a gallium nitride buffer layer 21, an Al(In, Ga)N barrier layer 22 and an (In)GaN ohmic contact layer 23 formed in the direction away from the substrate 10 in sequence on the substrate 10; the material of the Al(In, Ga)N barrier layer 22 is a group III alloy nitride, and the (In)GaN ohmic contact layer 23 includes a gallium nitride base material and an n-type dopant. The electrode layer is formed on the side of the heterostructure 20 away from the substrate 10, and includes a source electrode 31, a drain electrode 32, a gate electrode 33 and a gate dielectric layer 34 between the gate electrode 33 and the heterostructure 20.

[0044] The substrate 10 can be a gallium nitride homogenous substrate or a heterogenous substrate, such as a sapphire, silicon carbide, or silicon single crystal material, and the present embodiment is not limited in this regard.

[0045] The chemical formula of the group III alloy nitride is Al(In, Ga)N, and can include a nitrogen element and two or more group III metal elements (aluminum, indium, gallium, etc.). For example, the material of the Al(In, Ga)N barrier layer 22 can include a ternary alloy of aluminum, gallium, and nitrogen, a ternary alloy of aluminum, indium, and nitrogen, or a quaternary alloy of aluminum, indium, gallium, and nitrogen, and the present embodiment is not limited in this regard as long as two or more group III metal elements are included.

[0046] The (In) GaN ohmic contact layer 23 is used to contact the electrodes (including the source 31, the drain 32, and the gate 33), and the gallium nitride-based material contained therein can be a gallium nitride single substance or an alloy of gallium nitride and other group III nitrides. For example, the (In) GaN ohmic contact layer 23 can include a ternary alloy of indium, gallium, and nitrogen, and the present embodiment is not limited in this regard. The n-type dopant contained in the (In) GaN ohmic contact layer 23 can include, but is not limited to, silicon, alkali metals, and organic compounds thereof, and the like, as long as it can n-type dope the gallium nitride-based material and reduce the ohmic contact resistance. In addition, the heavily doped n-type (In) GaN ohmic contact layer 23 can be formed by direct epitaxial growth to further reduce the ohmic contact resistance. In combination with a self-alignment process, the length of the drift region of the gallium nitride-based enhancement mode power device can be more accurately defined, so as to reduce the resistance of the drift region by reducing the length of the drift region.

[0047] The gallium nitride-based enhancement-mode power device provided by the embodiment comprises a heterostructure 20 formed by a gallium nitride buffer layer 21, an Al(In,Ga)N barrier layer 22 and an (In)GaN ohmic contact layer 23. The Al(In,Ga)N / GaN heterojunction is formed in the heterostructure 20. Due to the different polarization strengths between different materials, the polarization effect can be generated to induce a high-density two-dimensional electron gas (2DEG). Due to the difference in the energy band structure between different materials, a quantum well is formed at the interface, and the 2DEG exists in the quantum well. The strength and direction of the built-in electric field generated at the heterojunction interface can be changed by forming an ultra-thin Al(In,Ga)N barrier layer 22 and adjusting the composition ratio of the alloy material in the Al(In,Ga)N barrier layer 22, which is helpful to form the enhancement-mode power device. The ohmic contact resistance can be reduced by forming a heavily doped (In)GaN ohmic contact layer 23, which effectively reduces the on-resistance of the gallium nitride-based enhancement-mode power device, so that the gallium nitride-based enhancement-mode power device has sufficient current conduction capability and good threshold voltage (Vth) uniformity and high power performance under low-voltage driving. In addition, the heterostructure 20 of the embodiment comprises a buffer layer, so that the gallium nitride-based enhancement-mode power device can use a gallium nitride hetero-substrate, thereby reducing the manufacturing cost of the gallium nitride-based enhancement-mode power device.

[0048] Specifically, the thickness of the Al(In,Ga)N barrier layer 22 can be greater than 1 nanometer and less than 10 nanometers to ensure that the enhancement-mode power device can be realized.

[0049] In the case that the material of the Al(In,Ga)N barrier layer 22 comprises a ternary alloy of aluminum element, gallium element and nitrogen element, that is, the Al(In,Ga)N barrier layer 22 can be an Al x Ga (1-x) N ternary alloy barrier layer, wherein the percentage of the aluminum element in the whole metal element can be greater than 0% and less than 100%.

[0050] In the case that the material of the Al(In,Ga)N barrier layer 22 comprises a ternary alloy of aluminum element, indium element and nitrogen element, that is, the Al(In,Ga)N barrier layer 22 can be an Al x In (1-x) N ternary alloy barrier layer, wherein the percentage of the aluminum element in the whole metal element is greater than or equal to 75% and less than or equal to 90%.

[0051] In the case that the material of the Al(In,Ga)N barrier layer 22 comprises a quaternary alloy of aluminum element, indium element, gallium element and nitrogen element, that is, the Al(In,Ga)N barrier layer 22 can be an Al x In y Ga(1-x-y) N quaternary alloy barrier layer, wherein the aluminum element component and the indium element component account for more than 0% and less than 100% of the percentage of the overall metal elements.

[0052] The Al(In, Ga)N barrier layer 22 of the above various materials can change the strength and direction of the built-in electric field formed in the heterojunction by adjusting the composition ratio of the alloy, so as to more contribute to the formation of the enhancement type device.

[0053] In some optional embodiments, the thickness of the (In)GaN ohmic contact layer 23 is greater than or equal to 5 nanometers and less than or equal to 200 nanometers, which can be specifically set according to the threshold voltage and on-resistance of the actual design, and the present embodiment does not make specific limitations.

[0054] Further, the doping concentration of the (In)GaN ohmic contact layer 23 can be greater than or equal to 1×10 17 cm -3 and less than or equal to 1×10 20 cm -3 to form a heavily doped n-type (In)GaN ohmic contact layer 23, thereby effectively reducing the on-resistance of the gallium nitride-based enhancement mode power device.

[0055] In another optional embodiment, the cross section of the gate 33 can be a "T" shaped structure, that is, the gate slot depth can include etching to the interface between the gallium nitride buffer layer 21 and the Al(In, Ga)N barrier layer 22, or to the interface between the Al(In, Ga)N barrier layer 22 and the (In)GaN ohmic contact layer 23.

[0056] In the present embodiment, before forming the gate 33, the (In)GaN ohmic contact layer 23 can be etched to form a gate 33 slot, wherein the etching method can include but is not limited to dry etching, for example, Cl-based plasma etching.

[0057] Specifically, as shown in FIG. 2, during etching of the (In)GaN ohmic contact layer 23, the etching can be automatically stopped when reaching the interface between the Al(In, Ga)N barrier layer 22 and the (In)GaN ohmic contact layer 23, and the gate 33 can be deposited at the interface between the Al(In, Ga)N barrier layer 22 and the (In)GaN ohmic contact layer 23, so that the complete Al(In, Ga)N barrier layer 22 can be ensured to ensure the uniformity of the threshold voltage of the GaN-based enhancement-mode power device. Alternatively, the etching can be continued until the Al(In, Ga)N barrier layer 22 is completely etched, so that the gate 33 can be deposited at the interface between the Al(In, Ga)N barrier layer 22 and the GaN buffer layer 21, and the Al(In, Ga)N barrier layer 22 under the gate 33 is etched, thereby further improving the threshold voltage of the GaN-based enhancement-mode power device.

[0058] In some alternative embodiments, the thickness of the gate dielectric layer 34 can be greater than or equal to 5 nm and less than or equal to 40 nm to avoid leakage of the gate 33 while preventing the required gate 33 voltage from being too high. The main function of the gate dielectric layer 34 is to provide insulation to prevent direct electrical connection between the gate 33 and the (In)GaN ohmic contact layer 23, thereby reducing or avoiding current leakage of the gate 33. Therefore, the gate dielectric layer 34 needs to have a certain thickness, but cannot be too thick to affect the conductivity of the power device.

[0059] Specifically, the gate dielectric layer 34 can be a single-layer structure or a composite structure, i.e., a multi-layer structure. When the gate dielectric layer 34 is a single-layer structure, a high-insulation dielectric material can be used, such as but not limited to aluminum oxide Al2O3, silicon nitride SiNx, silicon dioxide SiO2, nickel oxide NiO, a compound Ga x O 1-x N composed of gallium and oxygen and nitrogen elements, a compound Al x Si 1-x O composed of aluminum and silicon and oxygen elements, and a compound Al x Si 1-x N composed of aluminum and silicon and nitrogen elements, etc.

[0060] When the gate dielectric layer 34 is a composite structure, it can include a dielectric insertion layer and a high-insulation layer, wherein the dielectric insertion layer is in contact with the heterostructure 20, and the high-insulation layer is in contact with the gate 33. In this way, the dielectric insertion layer is arranged between the high-insulation layer and the heterostructure 20, which can be used to reduce the interface state density between the high-insulation layer and the III-nitride layer heterostructure 20, improve the interface characteristics, and reduce the channel resistance.

[0061] Specifically, the medium insertion layer can be a single crystal structure (including an approximate single crystal structure), and the single crystal structure has good binding between the cutoff insertion layer and the heterostructure 20 and the high insulating layer. Therefore, the single crystal structure of the medium insertion layer can form a buffer layer between the heterostructure 20 and the high insulating layer, so as to reduce the interface state density between the high insulating gate medium and the heterostructure 20 of the III-nitride layer. It can be understood that the medium insertion layer can also be a polycrystalline structure or an amorphous medium, and the embodiment does not make specific limitations thereto.

[0062] The specific material of the medium insertion layer can be, but is not limited to, aluminum nitride AlN, silicon nitride SiN x , gallium oxide Ga2O3, or a compound composed of gallium elements, oxygen elements and nitrogen elements Ga x O 1-x N, etc. The thickness of the medium insertion layer can be less than or equal to 5 nanometers, so as to reduce the interface state density between the high insulating layer and the heterostructure 20 of the III-nitride layer without affecting the insulation.

[0063] Further, in the embodiment, the deposition method can be used to generate the above-mentioned gate medium layer 34, so as to generate an effective high insulating gate medium layer 34 between the gate 33 and the heterostructure 20, thereby reducing the risk of leakage of the gate 33.

[0064] It can be understood that the process of forming the gallium nitride-based enhancement mode power device in the embodiment is only for illustration, and the specific process of forming the above-mentioned gallium nitride-based enhancement mode power device is not specifically limited in the embodiment, as long as the above-mentioned gallium nitride-based enhancement mode power device can be realized.

[0065] Embodiment two

[0066] Based on the same concept of the above-mentioned gallium nitride-based enhancement mode power device, the embodiment further provides a preparation method of a gallium nitride-based enhancement mode power device. The method can be used to prepare the gallium nitride-based enhancement mode power device provided in the above-mentioned embodiments. As shown in FIG. 3, the preparation method of the gallium nitride-based enhancement mode power device comprises the following steps:

[0067] Step S1, manufacturing a substrate;

[0068] Step S2, forming a heterostructure on the substrate, comprising: sequentially forming a gallium nitride buffer layer and an Al(In, Ga)N barrier layer on the substrate in a direction away from the substrate, and epitaxially growing an (In)GaN ohmic contact layer on the Al(In, Ga)N barrier layer; the material of the Al(In, Ga)N barrier layer is a III-alloy nitride, and the (In)GaN ohmic contact layer comprises a gallium nitride-based material and an n-type dopant;

[0069] Step S3, forming an electrode layer on the side of the heterostructure away from the substrate, the electrode layer including a source electrode, a drain electrode, a gate electrode, and a gate dielectric layer between the gate electrode and the heterostructure.

[0070] The substrate can be a gallium nitride homogenous substrate or a hetero-substrate, such as a sapphire, silicon carbide, or silicon single crystal material, and the present embodiment is not limited in this regard.

[0071] It can be understood that the above step S1, i.e. the process of manufacturing the substrate, can include but is not limited to crystal growth, wafer cutting, wafer polishing, and wafer cleaning, and the present embodiment is not limited in this regard as long as the substrate of the gallium nitride-based enhancement-mode power device can be manufactured.

[0072] In step S2, i.e. the process of forming the heterostructure on the substrate, the gallium nitride buffer layer and the Al(In, Ga)N barrier layer of the heterostructure can be formed by deposition or epitaxial growth, and the present embodiment is not limited in this regard. The (In) GaN ohmic contact layer of the heterostructure can be formed by direct epitaxial growth on the Al(In, Ga)N barrier layer to reduce the ohmic contact resistance.

[0073] Specifically, the Al(In, Ga)N barrier layer formed can be a group III alloy nitride with a chemical formula of Al(In, Ga)N, i.e. can include nitrogen and two or more group III metal elements (aluminum, indium, and gallium), such as a ternary alloy of aluminum, gallium, and nitrogen, a ternary alloy of aluminum, indium, and nitrogen, a quaternary alloy of aluminum, indium, gallium, and nitrogen, and the like, and the present embodiment is not limited in this regard as long as two or more group III metal elements are included.

[0074] The thickness of the Al(In, Ga)N barrier layer formed can be greater than 1 nanometer and less than 10 nanometers to ensure that the enhancement-mode power device can be implemented.

[0075] In the case where the material of the Al(In, Ga)N barrier layer includes a ternary alloy of aluminum, gallium, and nitrogen, i.e. the Al(In, Ga)N barrier layer can be Al x Ga (1-x) N ternary alloy Al(In, Ga)N barrier layer, wherein the percentage of aluminum in the total metal elements can be greater than 0% and less than 100%.

[0076] In the case where the material of the Al(In, Ga)N barrier layer includes a ternary alloy of aluminum, gallium, and nitrogen, i.e. the Al(In, Ga)N barrier layer can be Alx In (1-x) N quaternary alloy Al(In,Ga)N barrier layer, wherein the aluminum element component and the indium element component account for more than or equal to 0% and less than or equal to 100% of the percentage of the total metal elements.

[0077] In the material of the Al(In,Ga)N barrier layer includes aluminum element, indium element, gallium element and nitrogen element, that is, the Al(In,Ga)N barrier layer can be Al x In y Ga (1-x-y) N quaternary alloy Al(In,Ga)N barrier layer, wherein the aluminum element component and the indium element component account for more than or equal to 0% and less than or equal to 100% of the percentage of the total metal elements.

[0078] The Al(In,Ga)N barrier layer of the above various materials can change the strength and direction of the built-in electric field formed in the heterojunction by adjusting the composition ratio of the alloy during the formation process, which can more effectively form the enhancement device.

[0079] The (In)GaN ohmic contact layer formed for contact with the electrode can include a gallium nitride base material that can be a single substance of gallium nitride or an alloy of gallium nitride and other group III nitrides, such as a ternary alloy including indium element, gallium element and nitrogen element, which is not specifically limited in the embodiment. The n-type dopant contained in the (In)GaN ohmic contact layer can include, but is not limited to, silicon, alkali metals and their organic compounds, etc., as long as it can n-type dope the gallium nitride base material and reduce the ohmic contact resistance. In addition, a heavily doped n-type (In)GaN ohmic contact layer can be formed by direct epitaxial growth to further reduce the ohmic contact resistance. In combination with a self-alignment process, the length of the drift region of the gallium nitride base enhancement power device can be more accurately defined, so as to reduce the resistance of the drift region by reducing the length of the drift region.

[0080] The thickness of the (In)GaN ohmic contact layer can be greater than or equal to 5 nanometers and less than or equal to 200 nanometers, which can be specifically set according to the actual design of the threshold voltage and on-resistance, etc., which is not specifically limited in the embodiment.

[0081] During the formation of the (In)GaN ohmic contact layer, a n-type dopant can be used for heavy doping, and the specific doping concentration can be greater than or equal to 1×10 17 cm -3 and less than or equal to 1×10 20 cm -3 to effectively reduce the on-resistance of the gallium nitride base enhancement power device.

[0082] In practical applications, in order to improve production efficiency, the above-mentioned gallium nitride-based enhancement-mode power device can be prepared in batches, the shapes of the electrodes (including the source electrode, the drain electrode and the gate electrode) of each power device can be the same or different, but the deposition and the heterostructure of each power device are the same, so a large substrate can be prepared first, and a corresponding size of the heterostructure can be formed on the large substrate. Then, the electrodes of each gallium nitride-based enhancement-mode power device can be formed on the heterostructure, at this time, a plurality of power devices are arranged closely together. In order to prevent electrical interference between two adjacent power devices, device isolation can be performed on the two adjacent power devices to ensure that each power device can work independently.

[0083] In step S3, that is, in the process of forming the above-mentioned electrode layer on the substrate, for the preparation of the source electrode and the drain electrode, a corresponding electrode metal layer can be deposited on the (In)GaN ohmic contact layer respectively, and then a specific shape of the source electrode and the drain electrode can be obtained through photolithography and etching.

[0084] For the preparation of the gate electrode, the (In)GaN ohmic contact layer can be etched to form a gate trench before the gate electrode is formed, and then the above-mentioned gate electrode can be deposited in the gate trench. The etching method can include but is not limited to dry etching, for example, Cl-based plasma etching.

[0085] Specifically, in the process of etching the (In)GaN ohmic contact layer, the etching can be automatically stopped when the Al(In,Ga)N barrier layer and the (In)GaN ohmic contact layer are etched to the interface, the gate electrode can be deposited to the interface of the Al(In,Ga)N barrier layer and the (In)GaN ohmic contact layer, and the complete Al(In,Ga)N barrier layer can be ensured to ensure the uniformity of the threshold voltage of the gallium nitride-based enhancement-mode power device. The etching can also continue to etch the Al(In,Ga)N barrier layer until the Al(In,Ga)N barrier layer is completely etched, so that the gate electrode can be deposited in the Al(In,Ga)N barrier layer, and the Al(In,Ga)N barrier layer under the gate electrode is removed, thereby further improving the threshold voltage of the gallium nitride-based enhancement-mode power device.

[0086] Specifically, in the above-mentioned process of forming the electrode, before etching, the wafer (including the substrate and the heterostructure) can be marked first, for example, the positions of the source electrode, the drain electrode and the gate electrode, and the mask space can be marked. Then, through a self-alignment process, the mask and the wafer can be aligned according to the previous mark in the photolithography process, so as to realize smaller device size and higher integration.

[0087] It should be noted that the above-mentioned specific preparation process of the electrode layer is only for the distance of the embodiment, and the embodiment is not necessarily the first, as long as the above-mentioned electrode layer can be prepared.

[0088] In some alternative embodiments, a high-insulation gate dielectric layer can be deposited in the gate trench and on the (In)GaN ohmic contact layer before depositing the gate electrode, so as to reduce the gate leakage current.

[0089] Specifically, the gate dielectric layer can have a thickness greater than or equal to 5 nm and less than or equal to 40 nm, so as to avoid the gate leakage current while preventing the gate voltage from being too high. The gate dielectric layer mainly serves to provide insulation and prevent direct electrical connection between the gate electrode and the (In)GaN ohmic contact layer, so as to reduce or avoid the gate current leakage. Therefore, the gate dielectric layer needs to have a certain thickness, but cannot be too thick, so as not to affect the conductivity of the power device.

[0090] Specifically, the gate dielectric layer can be a single-layer structure or a composite structure, i.e., a multi-layer structure. When the gate dielectric layer is a single-layer structure, a high-insulation dielectric material can be used, such as but not limited to aluminum oxide Al2O3, silicon nitride SiNx, silicon dioxide SiO2, nickel oxide NiO, a compound GaO x N composed of gallium and oxygen and nitrogen elements, a compound Al 1-x Si x O composed of aluminum and silicon and oxygen elements, and a compound Al 1-x Si x N composed of aluminum and silicon and nitrogen elements, etc. 1-x

[0091] When the gate dielectric layer is a composite structure, the gate dielectric layer can include a dielectric insertion layer and a high-insulation layer, where the dielectric insertion layer is in contact with the heterostructure, and the high-insulation layer is in contact with the gate electrode. In this way, the dielectric insertion layer arranged between the high-insulation layer and the heterostructure can be used to reduce the interface state density between the high-insulation layer and the heterostructure of the III-nitride layer, and improve the interface characteristics, so as to reduce the channel resistance.

[0092] Specifically, the dielectric insertion layer can have a single-crystal structure (including an approximate single-crystal structure), which has good bonding with the heterostructure and the high-insulation layer. Therefore, the dielectric insertion layer having the single-crystal structure can form a buffer layer between the heterostructure and the high-insulation layer, so as to reduce the interface state density between the high-insulation gate dielectric layer and the heterostructure of the III-nitride layer.

[0093] Specifically, the dielectric insertion layer can be, but is not limited to, aluminum nitride AlN, silicon nitride SiN x , gallium oxide Ga2O3, or a compound Ga x O 1-x N composed of gallium and oxygen and nitrogen elements. The thickness of the dielectric insertion layer can be less than or equal to 5 nm, so as to reduce the interface state density between the high-insulation layer and the heterostructure of the III-nitride layer without affecting the insulation.​

[0094] Further, the deposition method can be used to form the gate dielectric layer in the embodiment, so as to form an effective high insulating gate dielectric layer between the gate and the heterostructure, thereby reducing the risk of gate leakage.

[0095] It can be understood that the process of forming the gallium nitride-based enhancement-mode power device in the embodiment is only for illustration, and the specific process of forming the gallium nitride-based enhancement-mode power device in the embodiment is not limited, as long as the gallium nitride-based enhancement-mode power device can be realized.

[0096] The preparation method of the gallium nitride-based enhancement-mode power device provided in the embodiment includes the heterostructure formed by the gallium nitride buffer layer, the Al(In, Ga)N barrier layer and the (In) GaN ohmic contact layer. The Al(In, Ga)N / GaN heterojunction is formed in the heterostructure. Due to the difference in polarization intensity between different materials, the polarization effect can be generated, thereby inducing a high-density two-dimensional electron gas (2DEG). Due to the difference in energy band structure between different materials, a quantum well is formed at the heterojunction interface, and the 2DEG exists in the quantum well. The strength and direction of the built-in electric field generated at the heterojunction interface can be changed by forming an ultra-thin Al(In, Ga)N barrier layer and adjusting the composition ratio of the alloy material in the Al(In, Ga)N barrier layer, which is helpful to form the enhancement-mode power device. The ohmic contact resistance can be reduced by forming the heavily doped (In) GaN ohmic contact layer, thereby effectively reducing the on-resistance of the gallium nitride-based enhancement-mode power device. The gallium nitride-based enhancement-mode power device has sufficient current conduction capability under low-voltage driving, good threshold voltage (Vth) uniformity and high power performance. In addition, the heterostructure in the embodiment includes the buffer layer, so that the gallium nitride-based enhancement-mode power device can use a gallium nitride hetero-substrate, thereby reducing the manufacturing cost of the gallium nitride-based enhancement-mode power device.

[0097] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should be covered in the scope of the claims and the description of the present application. Especially, as long as there is no structural conflict, each technical feature mentioned in each embodiment can be combined in any way. The present application is not limited to the specific embodiments disclosed in the text, but includes all technical solutions falling within the scope of the claims.

Claims

1. A gallium nitride based enhancement mode power device, characterized by, The application relates to a gallium nitride-based enhancement-mode power device. The device comprises a substrate, a heterostructure formed on the substrate in a direction away from the substrate, an electrode layer formed on a side of the heterostructure away from the substrate, and a gate dielectric layer between the gate and the heterostructure. The Al(In, Ga)N barrier layer has a thickness greater than 1 nm and less than 10 nm. The Al(In, Ga)N barrier layer is made of a ternary alloy of aluminum, gallium and nitrogen, wherein the proportion of aluminum in the total metal elements is greater than 0% and less than 100%.

2. The power device of claim 1, wherein, The Al(In, Ga)N barrier layer is made of a ternary alloy of aluminum, indium and nitrogen, wherein the proportion of aluminum in the total metal elements is greater than or equal to 75% and less than or equal to 90%.

3. The power device of claim 1, wherein, The Al(In, Ga)N barrier layer is made of a quaternary alloy of aluminum, indium, gallium and nitrogen, wherein the proportion of aluminum and indium in the total metal elements is greater than 0% and less than 100%. The (In) GaN ohmic contact layer is made of a binary alloy of gallium and nitrogen or a ternary alloy of indium, gallium and nitrogen, and has a thickness greater than or equal to 5 nm and less than or equal to 200 nm. The gate metal covers the entire gate slot, and the depth of the gate slot includes etching to the interface between the gallium nitride buffer layer and the Al(In, Ga)N barrier layer or the interface between the Al(In, Ga)N barrier layer and the (In) GaN ohmic contact layer.

4. The power device of claim 1, wherein, The gate dielectric layer comprises a single-layer gate dielectric layer or a composite gate dielectric layer.

5. The power device of claim 1, wherein, The (In)GaN ohmic contact layer has a doping concentration greater than or equal to 1 x 1018cm-3and less than or equal to 1 x 1020cm-3. 17 cm -3 and less than or equal to 1 x 1020cm-3. 20 cm -3 .

6. The power device of claim 1, wherein, The single-layer gate dielectric layer has a thickness greater than or equal to 5 nm and less than or equal to 40 nm.

7. The power device of claim 1, wherein, The composite gate dielectric layer comprises a dielectric insertion layer and a high-insulation gate dielectric layer, the dielectric insertion layer is in contact with the heterostructure, and the high-insulation gate dielectric layer is in contact with the gate metal.

8. The power device of claim 1, wherein, The single-layer gate dielectric layer is a high-insulation gate dielectric, including any one of Al2O3, SiN x , SiO2, NiO, Ga x O 1-x N, Al x Si 1-x O or Al x Si 1-x N.

9. The power device of claim 1, wherein, The dielectric insertion layer has a thickness less than or equal to 5 nm.

10. The power device of claim 1, wherein, The application also provides a preparation method of the gallium nitride-based enhancement-mode power device.

11. The power device of claim 1, wherein, The method comprises the following steps: preparing a substrate, forming a heterostructure on the substrate, and epitaxially growing an (In) GaN ohmic contact layer on the Al(In, Ga)N barrier layer.

12. The power device of claim 1, wherein, The medium insertion layer is any one of single crystal, polycrystal or amorphous medium, and the material includes any one of AlN, SiN x , Ga2O3 or Ga x O 1-x N. ​ ​ ​ An electrode layer is formed on the side of the heterostructure distal from the substrate, the electrode layer comprising a source, a drain, a gate, and a gate dielectric layer between the gate and the heterostructure.

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