Thin film capacitor element and manufacturing method therefor

Abstract

Provided in the present application are a thin film capacitor element and a manufacturing method therefor in the technical field of capacitors. The manufacturing method comprises: forming a dielectric thin film on a lower electrode; measuring a relative dielectric constant and film thickness of the dielectric thin film; and on the basis of the relative dielectric constant and the film thickness, determining the area where an upper electrode should be formed, and on the basis of the area where the upper electrode should be formed, using a direct delineation apparatus to form a plurality of upper electrodes on the dielectric thin film. The present application enables the manufacturing of a thin film capacitor element having a target electrostatic capacitance value while increasing productivity.

Description

A thin film capacitor element and a manufacturing method thereof

[0001] This application claims priority to the Chinese patent application No. 202410899418.4, filed on July 05, 2024, which is incorporated by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of capacitor elements, for example to a thin film capacitor element and a manufacturing method thereof. BACKGROUND

[0003] Thin film capacitor elements have a wide range of applications in electronic devices, for example in power converters, filters, energy storage devices and many other types of electronic devices.

[0004] The manufacturing process of a thin film capacitor element includes forming a dielectric thin film on a lower electrode, patterning an upper electrode on the dielectric thin film, and laminating the lower electrode and the upper electrode via the dielectric thin film.

[0005] The electrostatic capacitance value of a thin film capacitor assembly is determined by the relative dielectric constant of the dielectric film used, the dielectric film thickness and the area of the upper electrode patterned on the dielectric film. In order to pattern the upper electrode, the related art uses ordinary photolithography which requires a photomask, so that the actual upper electrode becomes a certain surface area determined by the photomask, which means that the electrostatic capacitance value of the thin film capacitor assembly can be a certain value determined by the actual relative dielectric constant of the dielectric film used, the actual thickness of the dielectric film and the actual area of the patterned upper electrode.

[0006] Due to fluctuations in production processes and process control capabilities, there are deviations in the relative dielectric constant and film thickness of the dielectric thin film, which makes it difficult to accurately manufacture thin film capacitor elements with a target electrostatic capacitance value. Due to the changes in the dielectric constant and film thickness of the dielectric thin film, it is not easy to accurately manufacture thin film capacitors with a target capacitance value. For example, US4894316A discloses a technology for adjusting the capacitance by removing a portion of the upper electrode after patterning the upper electrode using photolithography.

[0007] The related art uses photolithography to remove a portion of the upper electrode after patterning the upper electrode to adjust the electrostatic capacitance, so that the actual electrostatic capacitance value of the thin film capacitor element deviates from the target electrostatic capacitance value by an amount less than or equal to a preset threshold.

[0008] However, after patterning the upper electrode, an electrostatic capacitance adjustment process is required for the upper electrode, which will result in a reduction in productivity. In addition, in actual production, when the electrostatic capacitance value at the time of patterning the upper electrode is smaller than the target electrostatic capacitance value, the actual electrostatic capacitance value of the thin film capacitor element cannot be adjusted by the electrostatic capacitance adjustment process, and only the pattern can be removed to make the actual electrostatic capacitance value smaller.

[0009] Based on this, the present application provides a thin film capacitor element and a manufacturing method thereof to improve the related art. SUMMARY

[0010] The present application aims to provide a thin film capacitor element and a manufacturing method thereof, which can manufacture a thin film capacitor element with a target electrostatic capacitance value while improving productivity.

[0011] The purpose of the present application is achieved by adopting the following technical solutions:

[0012] In a first aspect, the present application provides a manufacturing method of a thin film capacitor element, comprising the following steps:

[0013] forming a dielectric thin film on the lower electrode;

[0014] measuring the relative dielectric constant and the film thickness of the dielectric thin film;

[0015] determining the area of the upper electrode to be formed according to the relative dielectric constant and the film thickness, and forming a plurality of upper electrodes on the dielectric thin film using a direct drawing device according to the area of the upper electrode to be formed.

[0016] In a possible implementation manner, the plurality of upper electrodes are independent of each other.

[0017] In a possible implementation manner, the areas of the upper electrodes are the same or different.

[0018] In a possible implementation manner, the patterns of the upper electrodes are the same or different.

[0019] In a possible implementation manner, before the step of forming a dielectric thin film on the lower electrode, the manufacturing method of the thin film capacitor element further comprises the following steps:

[0020] forming a lower electrode on a support body.

[0021] In a possible implementation manner, after the step of determining the area of the upper electrode to be formed according to the relative dielectric constant and the film thickness, and forming a plurality of upper electrodes on the dielectric thin film using a direct drawing device according to the area of the upper electrode to be formed, a thin film capacitor with a plurality of upper electrodes is obtained.

[0022] The manufacturing method of the thin film capacitor element further comprises the following steps:

[0023] The thin film capacitor with the plurality of upper electrodes is cut into a plurality of thin film capacitor elements.

[0024] In one possible implementation, the step of determining the area of the upper electrode to be formed according to the relative dielectric constant and the film thickness, and forming the plurality of upper electrodes on the dielectric thin film using the direct writing device according to the area of the upper electrode to be formed comprises the following steps:

[0025] forming a resist film on the metal film for the upper electrode;

[0026] determining the area of the upper electrode to be formed according to the target electrostatic capacitance, the vacuum dielectric constant, the relative dielectric constant and the film thickness;

[0027] performing maskless exposure on the resist film using a laser direct writing device according to the pattern of the upper electrode and the area of the upper electrode to be formed;

[0028] developing the exposed resist film to form an upper electrode resist pattern;

[0029] etching the metal film for the upper electrode according to the upper electrode resist pattern to form a plurality of independent upper electrodes, and obtaining the thin film capacitor with the plurality of upper electrodes.

[0030] In one possible implementation, the step of determining the area of the upper electrode to be formed according to the target electrostatic capacitance, the vacuum dielectric constant, the relative dielectric constant and the film thickness comprises the following formula (1):

[0031] In the formula, S is the area of the upper electrode to be formed, C is the target electrostatic capacitance, ε is the relative dielectric constant of the dielectric thin film, ε0 is the vacuum dielectric constant, and d is the film thickness of the dielectric thin film.

[0032] In a second aspect, the present application provides a thin film capacitor element manufactured by the above manufacturing method of the thin film capacitor element.

[0033] The thin film capacitor element and the manufacturing method thereof have at least the following advantages:

[0034] The present application can form the upper electrode for obtaining the target electrostatic capacitance by determining the relative dielectric constant and the film thickness of the dielectric thin film after forming the dielectric thin film and before forming the upper electrode, and combining with the direct writing device, without the need to adjust the electrostatic capacitance of the formed upper electrode. Further, the present application can manufacture the thin film capacitor element with the target electrostatic capacitance value while improving the productivity. BRIEF DESCRIPTION OF DRAWINGS

[0035] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0036] Fig. 1 shows a flowchart of a manufacturing method of a thin film capacitor element according to an embodiment of the present application.

[0037] Fig. 2 shows a schematic view of the structure after step S1 in Fig. 1.

[0038] Fig. 3 shows a schematic view of the structure after step S2 in Fig. 1.

[0039] Fig. 4 shows a schematic view of the structure after step S4 in Fig. 1.

[0040] Fig. 5A shows a schematic view of the structure after step S5-1 in Fig. 1.

[0041] Fig. 5B shows a schematic view of the structure after step S5-3 in Fig. 1: (a) is a sectional view showing a state where a plurality of upper electrode patterns are exposed on a resist using LDI, and (b) is a plan view showing a state where a plurality of upper electrode patterns are exposed on a resist using LDI.

[0042] Fig. 5C shows a schematic view of the structure after step S5-4 in Fig. 1.

[0043] Fig. 5D shows a schematic view of the structure after step S5-5 in Fig. 1.

[0044] Fig. 5E shows a schematic view of the structure after step S5-6 in Fig. 1.

[0045] Fig. 6 shows a schematic view of the structure after step S7 in Fig. 1: (a) is a sectional view (a) showing a state where a plurality of thin film capacitors manufactured are singulated, and (b) is a plan view showing a state where a plurality of thin film capacitors manufactured are singulated.

[0046] Fig. 7 shows a schematic view of a laser direct drawing device according to an embodiment of the present application.

[0047] In the drawings: 10, support body; 20, lower electrode; 30, dielectric thin film; 40, metal film for upper electrode; 40P1 to 40P3, upper electrode; 50, resist film; 50P1 to 50P3, upper electrode resist pattern; C, thin film capacitor; C1 to C3, thin film capacitor element; 100, light source; 101, DMD; 102, optical fiber; 103, projection lens; 104, stage; 105, controller. DETAILED DESCRIPTION

[0048] The technical solutions in the present application will be described below with reference to the drawings and specific embodiments of the present application. It should be noted that the embodiments described below and the technical features thereof can be combined with each other or among each other to form new embodiments without conflict.

[0049] In the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects. "At least one of the following" or similar expressions means any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b or c can mean a, b, c, a and b, a and c, b and c, and a and b and c, where a, b and c can be single or multiple. It should be noted that "at least one" can also be interpreted as "one or more".

[0050] It should be noted that in the embodiments of the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any implementation or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or advantageous than other implementation or design solutions. Rather, the use of the words "exemplary" or "for example" is intended to present relevant concepts in a concrete manner.

[0051] Next, the manufacturing method of the thin film capacitor elements C1-C3 of the present application will be described with reference to FIGS. 1-6. When applied, the manufacturing method of the thin film capacitor elements C1-C3 of the present application includes steps S1-S7.

[0052] Step S1, as shown in FIG. 2, a lower electrode 20 is formed on a support 10.

[0053] As the support 10, a wafer or substrate of silicon, ceramic, glass, an insulator sheet of glass, polymer, ceramic, an insulator film of glass, polymer, etc. can be used. In one embodiment, a wafer is used as the support 10.

[0054] The material of the lower electrode 20 is platinum, nickel, copper, etc., which is formed by a vapor deposition method, a sputtering method, a bonding method, etc.

[0055] In some embodiments, the lower electrode 20 is formed on the support 10, but the support 10 can also not be used, and a metal sheet or metal film made of an alloy of gold, platinum, nickel, copper, etc. can be used as the lower electrode 20.

[0056] Step S2, as shown in Fig. 3, a dielectric thin film 30 is formed on the lower electrode 20.

[0057] The dielectric thin film 30 is formed on the lower electrode 20 by an evaporation method, a sputtering method, a CVD method, a sol-gel method, a coating method, or the like. The dielectric material is a material having a high relative dielectric constant, and, for example, lead zirconate titanate (PZT) or barium titanate (BaTiO3) can be used.

[0058] Step S3, the relative dielectric constant and the film thickness of the dielectric thin film 30 are measured.

[0059] In the measurement of the film thickness, an X-ray diffractometer (XRD) can be used, and in the measurement of the relative dielectric constant, a mercury probe can be used. At the time of use, the measured data of the relative dielectric constant and the film thickness are used for the determination of the upper electrode area to be formed, which will be described later.

[0060] The measurement area and the number of measurement points of the relative dielectric constant and the film thickness are not particularly limited, and can be determined depending on various conditions. For example, the distribution of the relative dielectric constant and the film thickness of the dielectric thin film 30 formed (in wafer surface, between wafers) can be determined. Specifically, in the case where the distribution of the relative dielectric constant and the film thickness of the dielectric thin film 30 is good, one point in the wafer surface can be used as a representative point, which can be the center of the wafer (in the upper electrode formation area) or the edge of the wafer or the like outside the upper electrode formation area; in the case where the distribution of the relative dielectric constant and the film thickness of the dielectric thin film 30 is relatively poor, a plurality of points in the wafer surface can be measured, and the average value of the plurality of points can be used as a representative value, and the upper electrode area can be determined in units of wafers (in the case where the distribution in the wafer surface is small). Furthermore, the upper electrode area around each measurement point can be determined depending on the measured value (in the case where the distribution in the wafer surface is large).

[0061] Step S4, as shown in Fig. 4, a metal film 40 for the upper electrode is formed on the dielectric thin film 30.

[0062] The material of the metal film 40 for the upper electrode is a metal such as platinum, nickel, or copper, and can be formed by an evaporation method, a sputtering method, a bonding method, or the like. At the time of use, a tight layer of titanium, chromium, or the like can be formed between the dielectric film 30 and the metal film 40 for the upper electrode.

[0063] Step S5, the plurality of upper electrodes 40P1 to 40P3 having different areas are patterned.

[0064] Specifically, Step S5 includes Step S5-1 to Step S5-6.

[0065] Step S5-1, as shown in Fig. 5A, a resist film 50 is applied to the metal film 40 for the upper electrode.

[0066] The resist film 50 can be formed using spin coating, spray coating, slit coating, laminator (dry film), etc.

[0067] Step S5-2, determine the upper electrode area to be formed.

[0068] The upper electrode area to be formed is determined according to the target electrostatic capacitance, vacuum permittivity, relative permittivity, and film thickness, and specifically includes (1) the following formula:

[0069] In the formula, S is the upper electrode area to be formed, C is the target electrostatic capacitance, ε is the relative permittivity of the dielectric film, ε0 is the vacuum permittivity, and d is the film thickness of the dielectric film.

[0070] In one embodiment, in order to form multiple thin film capacitor elements C1-C3, for example, thin film capacitor chips, with different electrostatic capacitances on the same wafer, it is necessary to separately pre-calculate the upper electrode area of each thin film capacitor chip. It should be noted that the pre-calculated upper electrode area varies according to the measured data of the relative permittivity and film thickness of the dielectric film 30, and accordingly, the exposure conditions such as the size of the upper electrode pattern to be exposed need to be adjusted or corrected accordingly.

[0071] In addition, the upper electrode area to be formed and the exposure conditions can also be determined before step S4.

[0072] Step S5-3, as shown in FIG. 5B, according to the patterns of the upper electrodes 40P1-40P3 and the upper electrode area to be formed, multiple different upper electrode patterns are exposed on the resist film 50 using a direct drawing device (LDI) without a mask.

[0073] In one embodiment, the direct drawing device can be a laser direct drawing device, but a direct drawing device with an LED light source 100 or a direct drawing device with a UV lamp light source 100 can also be used.

[0074] In step S5-2, the exposure conditions are modified from the initial exposure conditions, but since exposure is performed using a laser direct drawing device, as long as the exposure conditions of the laser direct drawing device are modified, the operation is simple and easy to perform. For the same reason, even if the exposure conditions of multiple different area upper electrode patterns need to be adjusted, it can be quickly achieved.

[0075] Next, the structure and exposure principle of the laser direct drawing device will be introduced in combination with the remaining steps.

[0076] As shown in FIG. 7, the laser direct writing device includes a light source 100, a digital micro device (DMD 101) as a spatial light modulator, an optical fiber 102 for transmitting light from the light source 100 to the DMD 101, a projection lens 103, a stage 104 for fixing an exposure object, and a controller 105 for controlling the output of the light source 100, the position / moving speed of the DMD 101 and the stage 104.

[0077] The DMD 101 includes a plurality of micro-mirrors arranged in order, and the direction of reflected light is controlled by controlling the inclination of the micro-mirrors by a digital signal. Specifically, the angle of each micro-mirror is adjusted by an actuator, so that each micro-mirror controls the incident light of the projection lens 103. When the micro-mirror of the DMD 101 is activated (or "on"), it reflects light in a direction, and the light is projected onto the stage 104 through the projection lens 103, thereby performing exposure. Specifically, when the DMD 101 is activated, the light emitted from the light source 100 is reflected by the DMD 101 and forms an image on the stage 104 through the projection lens 103, thereby performing exposure. When the micro-mirror of the DMD 101 is not activated (or "off"), it does not reflect light to the projection lens 103, or reflects it to other places (such as a light trap). Specifically, when the DMD 101 is off, light is not reflected to the projection lens 103, and thus the stage 104 is not exposed. Since no exposure is performed at this time, any image pattern can be projected.

[0078] The stage 104 is movable in the y direction, and the projection lens 103 is movable in the x direction. The exposure process is performed in cooperation with the y direction scanning of the stage 104 and the stepwise movement of the projection lens 103 in the x direction. After the stage 104 completes a scan in the y direction each time, the projection lens 103 is stepwise moved in the x direction, and then the stage 104 starts the next scan in the y direction until the entire exposure area is covered. Specifically, when the movement of the stage 104 in the y direction of the exposure range ends, the projection lens 103 stepwise moves the irradiation area AR in the x direction, and the scan in the y direction of the stage 104 is started again. By repeatedly moving the stage 104 and the projection lens 103, the entire surface in the exposure range can be irradiated, and thus any image can be projected to any position in the stage 104.

[0079] According to the parameters such as film thickness and relative dielectric constant, the controller 105 calculates and adjusts the micro-mirror pattern of the DMD 101 to control the area and intensity of the exposed part, so as to ensure that the required upper electrode area and performance are obtained. In application, in order to further improve the image quality and exposure accuracy, advanced image processing algorithms and high-precision mechanical systems can be used to optimize the micro-mirror pattern of the DMD 101 and the movement of the stage 104 / projection lens 103.

[0080] Step S5-4, as shown in FIG. 5C, the exposed resist film 50 is developed to obtain the upper electrode resist patterns 50P1-50P3. In one implementation, the development can use spray development.

[0081] Step S5-5, as shown in FIG. 5D, the upper electrode metal film 40 is selectively etched.

[0082] In one implementation, the etching can use dry etching or wet etching.

[0083] Step S5-6, as shown in FIG. 5E, the remaining resist film 50 on the upper electrode metal film 40, i.e. the upper electrode resist patterns 50P1-50P3, is removed to obtain a plurality of independent upper electrodes 40P1-40P3, and further obtain a thin film capacitor C with a plurality of upper electrodes 40P1-40P3.

[0084] In one implementation, the removal of the resist film 50 can use solution removal and dry removal such as plasma ashing. In application, the patterning of the thin film capacitor C is completed before step S5-3.

[0085] Step S6, the actual electrostatic capacitance of each upper electrode 40P1-40P3 is measured.

[0086] In one implementation, the measured electrostatic capacitance of the upper electrode using the LCR meter, for example, according to the measurement data, it is judged whether the deviation of the electrostatic capacity between wafers is within the specified range.

[0087] Step S7, as shown in FIG. 6, the thin film capacitor C with a plurality of upper electrodes formed on the same wafer is cut into a plurality of thin film capacitor elements C1-C3. For example: a plurality of thin film capacitor chips, the area and pattern of the upper electrode of each thin film capacitor chip can be the same or different.

[0088] In one implementation, the cutting technology uses laser cutting, blade cutting, etching, etc.

[0089] This application calculates the area of the upper electrode to be formed according to the relative dielectric constant and film thickness of the dielectric film 3050 before forming the dielectric film 3050 and patterning the upper electrode, and uses a laser direct writing device to expose the upper electrode pattern in the exposure of the upper electrode pattern, so that the upper electrode 40P1-40P3 with an area for obtaining the target electrostatic capacitance can be formed.

[0090] In one possible implementation, the application not only prevents the deviation of the electrostatic capacitance of the thin film capacitor C with multiple upper electrodes 40P1-40P3 formed in the same wafer surface, but also avoids the deviation of the electrostatic capacitance among wafers in terms of the relative dielectric constant and film thickness of the dielectric thin film 3050 of each wafer.

[0091] In one possible implementation, the application does not need to perform the electrostatic capacitance adjustment process after the upper electrode is formed, and the production rate is improved.

[0092] In order to make the purpose, technical solutions and advantages of the application more clear and understandable, the application will be further described in detail below in combination with specific examples. It should be understood that the specific examples described herein are only used to explain the application and not to limit the application.

[0093] Example 1

[0094] In one implementation, PZT (lead zirconate titanate) thin film is formed on a silicon wafer with a diameter of 100 mm as a dielectric, and thin film capacitor elements C1-C3 with 10 pF, 50 pF and 100 pF are formed on the same wafer.

[0095] Preparation of the dielectric thin film 30:

[0096] On the silicon wafer with a diameter of 100 mm, a layer of 10 nm Ti and 100 nm Pt is first deposited as the lower electrode 20 by the RF magnetron sputtering method in the physical vapor deposition (PVD) technology.

[0097] On the Ti / Pt lower electrode 20, PZT is formed as the dielectric thin film 30 by the RF magnetron sputtering method. The target film thickness of the dielectric thin film 30 is 500 nm, and the target relative dielectric constant is 1100. As known, when PZT is sputtered onto the Ti / Pt bottom electrode, a polycrystalline film mainly with PZT orientation is obtained, and its relative dielectric constant is about 1100. In order to ensure the uniform distribution of the film thickness and the relative dielectric constant in the substrate surface, the target diameter used in the sputtering film formation is 300 mm, which is large enough relative to the substrate diameter of 100 mm, and thus the distribution of the film thickness and the relative dielectric constant in the wafer surface does not need to be considered.

[0098] Film thickness and dielectric constant measurement of the dielectric thin film 30:

[0099] Immediately after the PZT film formation, the PZT film thickness at the center of the substrate is measured by XRF (X-ray fluorescence analysis), and its relative dielectric constant is measured by the mercury probe method. The measured actual PZT film thickness is 0.55 μm, and the actual relative dielectric constant is 1020.

[0100] Preparation of the upper electrodes 40P1-40P3:

[0101] On the dielectric thin film 30, an upper electrode was formed again by RF magnetron sputtering method, with a structure of Ti 10 nm / Pt 100 nm.

[0102] A dry film (such as DuPont LDI7330) was used as the resist film 50, and exposure was performed by a laser direct drawing device. Using the actual film thickness and actual relative dielectric constant measured previously, the upper electrode area to be formed (vacuum dielectric constant 8.85e-12 F / m) was calculated by the formula for 10 pF, 50 pF, and 100 pF.

[0103] The exposure conditions were set to a wavelength of 405 nm and an exposure energy of 10 mJ / sqcm. After exposure, development was performed (such as spray development using a Na2CO3 developer), and then the Ti 10 nm / Pt 100 nm layer of the upper electrode was etched by ion milling.

[0104] After etching, the dry film was removed by NaOH spray treatment and oxygen plasma ashing.

[0105] Capacitance measurement and evaluation:

[0106] The actual electrostatic capacitance of the thin film capacitor elements C1-C3 produced was measured using a probe, and compared with the target electrostatic capacitance. Table 1 shows the details. In the related art, an upper electrode area correction method was used.

[0107] According to the evaluation results in Table 2, the deviation of the actual electrostatic capacitance from the target electrostatic capacitance was within 3%.

[0108] Table 1 Actual parameters and target parameters of thin film capacitor elements C1-C3

[0109] Table 2 Deviation of electrostatic capacitance of thin film capacitor elements C1-C3

[0110] Expansion to larger substrates:

[0111] For substrates with a diameter greater than 100 mm (such as 150 mm, 200 mm, 300 mm), since the film thickness and relative dielectric constant distribution in the substrate plane can increase, it is recommended to increase the measurement points in the substrate plane, and calculate the upper electrode 40P1-40P3 area of that part according to the film thickness and relative dielectric constant near each measurement point.

[0112] By adjusting the drawing conditions of the laser direct drawing device, thin film capacitor elements C1-C3 with actual electrostatic capacitance close to the target electrostatic capacitance were obtained on the entire surface of the substrate.

[0113] In one implementation, PZT thin film capacitor elements C1-C3 with different capacitance values were successfully prepared on a 100 mm diameter silicon wafer, and by optimizing the preparation and measurement processes, the deviation of the actual electrostatic capacitance from the target electrostatic capacitance was ensured to be within an acceptable range, for example, 3%. For larger size substrates, by increasing the measurement points and adjusting the preparation conditions, the actual electrostatic capacitance can also be made close to the target electrostatic capacitance.

[0114] The above describes the embodiments of the present application in detail, but the present application is not limited to this specific example, and various modifications and changes can be made within the scope of the spirit of the present application as recited in the claims.

Claims

1. A method for manufacturing a thin film capacitor element, comprising the steps of: forming a dielectric thin film (30) on a lower electrode (20); measuring a relative dielectric constant and a film thickness of the dielectric thin film (30); determining an area on which an upper electrode should be formed, based on the relative dielectric constant and the film thickness; and forming a plurality of upper electrodes (40P1-40P3) on the dielectric thin film (30) using a direct drawing device, based on the area on which the upper electrode should be formed. The plurality of upper electrodes (40P1-40P3) are independent of each other. The area of each of the upper electrodes (40P1-40P3) is the same or different. The pattern of each of the upper electrodes (40P1-40P3) is the same or different.

2. A method of manufacturing a thin film capacitor element according to claim 1, wherein Before the step of forming the dielectric thin film (30) on the lower electrode (20), the method for manufacturing a thin film capacitor element further comprises the step of: forming the lower electrode (20) on a support (10).

3. A method of manufacturing a thin film capacitor element according to claim 1, wherein, After the step of determining the area on which the upper electrode should be formed, based on the relative dielectric constant and the film thickness, and forming a plurality of upper electrodes (40P1-40P3) on the dielectric thin film (30) using a direct drawing device, based on the area on which the upper electrode should be formed, a thin film capacitor (C) having a plurality of upper electrodes (40P1-40P3) is obtained.

4. A method of manufacturing a thin film capacitor element according to claim 1, wherein The method for manufacturing a thin film capacitor element further comprises the step of: cutting the thin film capacitor (C) having a plurality of upper electrodes into a plurality of thin film capacitor elements (C1-C3).

5. A method of manufacturing a thin film capacitor element according to claim 1, wherein, The step of determining the area on which the upper electrode should be formed, based on the relative dielectric constant and the film thickness, and forming a plurality of upper electrodes (40P1-40P3) on the dielectric thin film (30) using a direct drawing device, based on the area on which the upper electrode should be formed, comprises the steps of: forming a resist film (50) on the upper electrode metal film (40); determining the area on which the upper electrode should be formed, based on a target electrostatic capacitance, a vacuum dielectric constant, the relative dielectric constant, and a film thickness; performing a maskless exposure on the resist film (50) using a direct drawing device, based on the pattern of the upper electrode and the area on which the upper electrode should be formed; developing the exposed resist film (50) to form an upper electrode resist pattern (50P1-50P3); and etching the upper electrode metal film (40) based on the upper electrode resist pattern (50P1-50P3) to form a plurality of upper electrodes (40P1-40P3) independent of each other, thereby obtaining the thin film capacitor (C) having a plurality of upper electrodes (40P1-40P3). In the formula, S is the area on which the upper electrode should be formed, C is the target electrostatic capacitance, ε is the relative dielectric constant of the dielectric thin film, ε0 is the vacuum dielectric constant, and d is the film thickness of the dielectric thin film.

6. A method of manufacturing a thin film capacitor element according to claim 1, wherein The thin film capacitor element is manufactured using the method for manufacturing a thin film capacitor element according to any one of claims 1-8. ​ ​ 7. A method of manufacturing a thin film capacitor element according to claim 1, wherein ​ ​ ​ ​ ​ ​ 8. A method of manufacturing a thin film capacitor element according to claim 7, wherein The determining of the area in which the upper electrode should be formed based on the target electrostatic capacitance, the vacuum permittivity, the relative permittivity, and the film thickness includes Equation (1): ​ 9. A thin film capacitor element, wherein, ​

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