Embedded packaging structure and packaging method

Abstract

Disclosed are an embedded packaging structure and packaging method for an integrated circuit and a power device, which are configured to encapsulate an integrated circuit die and a power device onto a resin substrate. The surfaces of the integrated circuit die (104a) and the power device (104b) are respectively provided with bonding pads (141a, 141b), and the back surface of the power device (104b) is provided with a back electrode (142b). The surface of the resin substrate (101) is provided with a plurality of recessed grooves (112a, 112b), the depths of the recessed grooves (112a, 112b) being different to adapt to the integrated circuit die (104a) and the power device (104b) of different thicknesses; an electrically conductive layer (121) extending to the surface of the resin substrate (101) is arranged at the bottom of the recessed groove (112b) in which the power device (104b) is embedded, and the back electrode (142b) of the power device (104b) comes into contact with the electrically conductive layer (121), leading the back electrode (142b) out to the surface of the resin substrate (101) by means of the electrically conductive layer (121) at the bottom of the recessed groove; all the bonding pads (141a, 141b) and the back electrode (142b) are led to the same surface (111), the integrated circuit die (104a) and the power device (104b) are connected to each other, and conductors for conductive connection with external devices are provided; and an encapsulation layer (106) encapsulates the integrated circuit die (104a) and the power device (104b) onto the resin substrate (101) from one side of the surface (111).

Description

Embedded package structure and package method TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor packaging process, and particularly relates to an embedded package structure and a package method. BACKGROUND

[0002] Different from the traditional chip packaging mode after wafer cutting, wafer level chip scale packaging (WLCSP) is an advanced CSP electronic packaging technology based on BGA technology and improved, and its main feature is that packaging and testing are directly completed before wafer cutting. According to different lead modes, wafer level packaging is mainly divided into fan-in wafer level packaging (Fan-In WLCSP) and fan-out wafer level packaging (Fan-Out WLCSP).

[0003] In the current fan-in packaging and fan-out packaging, all pins of the die need to be on the same side of the wafer, so as to facilitate subsequent wiring, ball planting and other processes. However, in the fan-out packaging process, when some dies are discrete devices (such as power devices), the electrodes of the discrete devices are often blocked on the back surface of the device, but the electrodes need to be conductively connected, which leads to that the current fan-out packaging process cannot meet such a demand. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present disclosure is to provide an embedded package structure and a package method to solve the problems in the related art.

[0005] The first aspect of the present disclosure provides an embedded package structure, comprising: a resin carrier plate, a surface of the resin carrier plate is formed with a plurality of sunken grooves; a first wiring structure, comprising: a conductive layer leading out from the bottom of part of the plurality of sunken grooves to the surface of the resin carrier plate; an integrated circuit die and a power device, respectively embedded in the plurality of sunken grooves, the surface of the integrated circuit die has a press welding point, and the power device has a back surface electrode in contact with the conductive layer in the part of the sunken grooves provided on the back surface in addition to the press welding point on the surface; a second wiring structure interconnecting the integrated circuit die and the power device, comprising: a conductive body interconnecting the press welding point on the surface of the integrated circuit die, the press welding point on the surface of the power device, and the conductive layer on the surface of the resin carrier plate connected with the back surface electrode of the power device with an external device; and a packaging layer packaging the integrated circuit die and the power device on the resin carrier plate from the surface of the resin carrier plate.

[0006] In an embodiment of the first aspect, the plurality of sunk grooves have a depth matching a thickness of the embedded integrated circuit die or the power device.

[0007] In an embodiment of the first aspect, the electrically conductive body includes a first electrically conductive body connecting the soldering points of the integrated circuit die and the power device, and a second electrically conductive body formed on the electrically conductive layer of the first electrically conductive body and the surface of the resin carrier board for interconnection with external devices.

[0008] In an embodiment of the first aspect, the encapsulation layer exposes the second electrically conductive body.

[0009] In an embodiment of the first aspect, the second electrically conductive body is a package soldering point.

[0010] The second aspect of the present disclosure provides an embedded packaging method, comprising: forming a plurality of sunk grooves on a surface of a resin carrier board; forming a first wiring structure on the surface of the resin carrier board, the first wiring structure including an electrically conductive layer leading from a bottom of part of the plurality of sunk grooves to the surface of the resin carrier board; embedding an integrated circuit die and a power device into the plurality of sunk grooves, respectively, to expose soldering points on a surface of the integrated circuit die and soldering points on a surface of the power device, and to make a back electrode of the power device contact the electrically conductive layer provided in the part of the sunk grooves; forming a second wiring structure on the integrated circuit die and the power device for interconnection with the integrated circuit die and the power device, the second wiring structure including an electrically conductive body interconnecting the soldering points on the surface of the integrated circuit die, the soldering points on the surface of the power device, and the electrically conductive layer on the surface of the resin carrier board connected with the back electrode of the power device with external devices; and encapsulating the integrated circuit die and the power device in the resin carrier board from a side of the surface of the resin carrier board.

[0011] In an embodiment of the second aspect, the plurality of sunk grooves have a depth matching a thickness of the embedded integrated circuit die or the power device.

[0012] In an embodiment of the second aspect, the electrically conductive body includes a first electrically conductive body connecting the soldering points of the integrated circuit die and the power device, and a second electrically conductive body provided on the electrically conductive layer of the first electrically conductive body and the surface of the resin carrier board.

[0013] In an embodiment of the second aspect, the encapsulating the integrated circuit die and the power device in the resin carrier board from the side of the surface of the resin carrier board includes forming an encapsulation layer on the resin carrier board covering the second wiring structure and exposing the second electrically conductive body.

[0014] In an embodiment of the second aspect, the second conductive body is a package bump.

[0015] As described above, the present disclosure provides an embedded package structure and a package method for integrated circuit and power device, for packaging integrated circuit die and power device on a resin carrier board. The integrated circuit die has a solder bump on the surface of the die; the power device has a solder bump on the surface and other electrodes on the back surface. The resin carrier board has a plurality of sunken grooves on the surface, the sunken grooves have different depths to accommodate integrated circuit dies and power devices with different thicknesses; a conductive layer is laid on the bottom of the sunken groove in which the power device is embedded, the conductive layer extends to the surface of the resin carrier board, the back surface electrodes of the power device are in contact with the conductive layer, and the back surface electrodes are led out through the conductive layer at the bottom of the sunken groove to be connected to the surface of the resin carrier board; the surface solder bump of the integrated circuit, the surface electrode of the power device, and the back surface electrode of the power device are all on the surface of the resin carrier board, the integrated circuit die and the power device are interconnected, and there is a conductive body for communication with external devices, and the part of the conductive body on the surface of the resin carrier board except the second conductive body is encapsulated by a package layer. The package structure in the embodiment of the present disclosure can encapsulate the solder bump of the integrated chip die and the back surface electrode of the power device, and overcome the shortcomings of the embedded package process in the related art. BRIEF DESCRIPTION OF DRAWINGS

[0016] FIG. 1 shows a schematic diagram of an embedded package structure in an embodiment of the present disclosure.

[0017] FIG. 2 shows a schematic diagram of an embedded package method in an embodiment of the present disclosure.

[0018] FIG. 3 shows a schematic diagram of a mold structure for forming a resin carrier board in an embodiment of the present disclosure.

[0019] FIG. 4 shows a schematic diagram of a structure in which a mold surface in FIG. 3 is subjected to plastic packaging such as resin material to form a resin carrier board.

[0020] FIG. 5 shows a schematic diagram of a structure in which the resin carrier board in FIG. 4 is separated from the mold.

[0021] FIG. 6 shows a schematic diagram of a structure in which a surface side of the resin carrier board obtained in FIG. 5 is subjected to metal sputtering to form a metal film.

[0022] FIG. 7 shows a schematic diagram of a structure in which the metal film in FIG. 6 is processed to obtain a conductive layer.

[0023] FIG. 8 shows a schematic diagram of a structure in which an integrated circuit die and a power device are embedded into a sunken groove of the resin carrier board in FIG. 7. DETAILED DESCRIPTION

[0024] The advantages and features of the present disclosure will become apparent from specific examples which are given as thorough and complete descriptions of the present disclosure. It will be obvious to those of ordinary skill in the art that various alternatives to the examples can be practiced without departing from the spirit and scope of the present disclosure. The present disclosure is not intended to be limited to the examples described herein but is to be accorded the full scope that the art appreciates from the multiple different embodiments and examples taught herein.

[0025] The embodiments of the present disclosure will be described in detail by referring to the attached drawings, in order for those skilled in the art to easily implement the present disclosure. The present disclosure can be embodied in various ways, and is not limited to the embodiments described herein.

[0026] In the present disclosure, the expressions of "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like mean that the specific features, structures, materials or characteristics expressed in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. Also, the specific features, structures, materials or characteristics expressed can be combined in any one or a set of embodiments or examples in a suitable manner. In addition, the different embodiments or examples expressed in the present disclosure and the features of the different embodiments or examples can be combined and integrated by those skilled in the art without contradiction.

[0027] In addition, the terms "first", "second", etc. are used only to indicate the purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In the present disclosure, the meaning of "a set" is two or more, unless otherwise specifically limited.

[0028] In order to clearly explain the present disclosure, devices irrelevant to the description are omitted, and the same reference numerals are assigned to the same or similar constituent elements throughout the specification.

[0029] Throughout the specification, when it is said that a device is "connected" to another device, it includes not only the case of "direct connection", but also the case of "indirect connection" in which other elements are interposed therebetween. In addition, when it is said that a device "includes" a certain constituent element, unless otherwise specifically stated, other constituent elements are not excluded, but it means that other constituent elements can be further included.

[0030] Although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first interface and a second interface, etc. are distinguished from each other. Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including" used herein specify the presence of stated features, steps, operations, elements, modules, items, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, modules, items, components, and / or groups thereof. As used herein, the terms "or" and "and / or" are to be interpreted as inclusive, i.e., as meaning one or any combination of items. Thus, "A, B or C" or "A, B and / or C" means any of the following: A; B; C; A and B; A and C; B and C; A, B and C. Only when a combination of elements, functions, steps or actions is inherently mutually exclusive is an exception to this definition presented.

[0031] The professional terms used herein are only used to refer to specific embodiments, and are not intended to limit the disclosure. The singular form used herein, unless the context clearly indicates otherwise, also includes the plural form. The meaning of "comprising" used in the specification is to specify a particular feature, region, integer, step, operation, element and / or component, and does not exclude the presence or addition of other features, regions, integers, steps, operations, elements and / or components.

[0032] Although not defined differently, all terms including technical terms and scientific terms used herein have the same meaning as that generally understood by those skilled in the art to which the disclosure belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with the meanings in related technical documents and the currently prompted messages, unless defined, and should not be over-interpreted as ideal or very formal meanings.

[0033] In the current fan-in or fan-out package, all pins of the die need to be on the same side of the wafer. However, in the fan-out packaging process, some discrete devices have electrodes on the back surface facing the resin carrier plate, and the electrodes need to be conductively connected but are blocked, resulting in that the current fan-out packaging process cannot complete the conductive connection requirement.

[0034] In view of this, the wafer-level fan-out packaging structure and packaging method are provided in the embodiments of the disclosure to solve the above problems.

[0035] Referring to FIG. 1, a schematic diagram of a wafer-level fan-out packaging structure in an embodiment of the disclosure is shown.

[0036] In FIG. 1, the embedded package structure includes, in sequence, a resin carrier 101, a first wiring structure 102, an integrated circuit die 104a, a power device 104b, a second wiring structure 105, and a package layer 106.

[0037] The resin carrier 101 has a surface 111, which is exemplified as an upper surface. The surface 111 is formed with a plurality of sunken recesses 112a, 112b. In the example of FIG. 1, the surface 111 is presented as a horizontal plane. The plurality of sunken recesses 112a, 112b are configured to fitly bury the integrated circuit die 104a and the power device 104b. Different integrated circuit dies 104a, power devices 104b can have different thicknesses. For this reason, the depths of the sunken recesses 112a, 112b can be configured to respectively match the thicknesses of the integrated circuit dies 104a, power devices 104b to be buried. Thus, when the integrated circuit die 104a and the power device 104b are inserted into the sunken recesses 112a, 112b having depths matching their thicknesses, their upper surfaces (exemplified as upper surfaces consistent with the orientation of the surface 111) exposed from the sunken recesses 112a, 112b can be substantially flush with the surface 111 of the resin carrier 101. That is, the sunken recesses 112a, 112b can also have corresponding different depths to one-by-one match each integrated circuit die 104a and power device 104b to be packaged, corresponding to packaging requirements of a plurality of buried devices having different thicknesses. The sunken recesses 112a, 112b of different depths accommodate the integrated circuit dies 104a and power devices 104b of different thicknesses. After the integrated circuit dies 104a and power devices 104b of different thicknesses are buried, the surfaces thereof can be substantially flush with the surface 111. In addition, in some embodiments, the shape of each sunken recess 112a, 112b can also match the shape of the corresponding integrated circuit die 104a or power device 104b to be combined. In some embodiments, the width and / or length of each sunken recess 112a, 112b can also match the width and / or length of the corresponding integrated circuit die 104a or power device 104b to be combined, so that the integrated circuit die 104a and the power device 104b are dimensionally matched to be buried in the corresponding sunken recess 112a, 112b.

[0038] The first wiring structure 102 includes a conductive layer 121 leading out from the surface of the sink recess 112b for setting the power device to the surface 111. That is, the conductive layer 121 includes a first portion 1211 located in the sink recess 112b and a second portion 1212 extending to the surface 111. Exemplarily, the first portion 1211 can include a first sub-portion 12111 located at the bottom surface of the sink recess 112b and a second sub-portion 12112 extending upwardly from the sidewall of the sink recess 112b. In some embodiments, the first wiring structure 102 can be formed by a metal patterning technique, for example, metal sputtering of a target material on the side of the surface 111 of the resin carrier 101, and then photoetching, etching, etc. to obtain the first wiring structure 102.

[0039] The surface of the integrated circuit die 104a and the surface of the power device 104b can have press points 141a, 141b respectively. In addition, the sink recess 112b provided with the conductive layer 121 can be used to set the power device 104b with a back electrode 142b. Referring to FIG. 1, the back electrode 142b of the power device 104b can be in conductive contact with the first sub-portion 12111 of the conductive layer 121 at the bottom surface of the sink recess 112b to form an electrical connection, and the back electrode 142b can be led out to the surface 111 through the conductive layer 121. In this way, each of the press points 141a, 141b and the back electrode 142b is led to the same surface 111, which facilitates subsequent packaging.

[0040] The second wiring structure 105 is interconnected with the integrated circuit die 104a and the power device 104b. Specifically, the second wiring structure 105 includes conductive bodies interconnecting the press points 141a on the surface of the integrated circuit die 104a, the press points 141b on the surface of the power device 104b, and the portion of the conductive layer 121 on the surface 111 of the resin carrier 101 connected with the back electrode 142b of the power device 104b with external devices.

[0041] Exemplarily, the second wiring structure 105 can include first conductive bodies 151 and second conductive bodies 152. The first conductive bodies 151 are formed by a redistribution layer (RDL) and are led out to desired positions, including positions outside the integrated circuit die 104a and the power device 104b, by setting the second conductive bodies 152. The second wiring structure 105 is formed on the surface 111. A plurality of first conductive bodies 151 are respectively electrically connected with the press points 141a, 141b of the integrated circuit die 104a and the power device 104, and the second conductive bodies 152 are led out at predetermined positions on the surface 111 for external devices to be electrically connected to the press points 141a, 141b. Also, the second conductive bodies 152 can be set at predetermined positions on the portion of the conductive layer 121 (i.e., the second portion 1212 of the conductive layer 121) on the surface 111 for external devices to be electrically connected to the back electrode 142b.

[0042] The encapsulation layer 106 encapsulates the integrated circuit die 104a and power devices 104b, 104b on the resin substrate 101 from the surface 111 side, and leads out a second conductor 152 that is electrically connected to the bonding pads 141a, 141b and the back electrode 142b.

[0043] Exemplarily, the encapsulation layer 106 covers the second wiring structure 105 onto the resin carrier 101 and exposes the second conductor 152. The encapsulation layer 106 may have holes to expose the second conductor 152. Further exemplaryly, the encapsulation layer 106 may be an organic polymer material, such as polyimide (PI). Exemplarily, each second conductor 152 may be a solder ball obtained through ball array (BGA) encapsulation.

[0044] Referring to Figure 2, a flowchart illustrating an embedded packaging method according to an embodiment of this disclosure is shown. The embedded packaging method can be used to fabricate the embedded packaging structure shown in Figure 1.

[0045] In Figure 2, the process specifically includes:

[0046] Step S201: A plurality of recessed grooves 112a and 112b are formed on the surface of the resin carrier plate 101.

[0047] As an example, refer to Figures 3 through 5. Figure 3 shows a mold 201 used to form the resin carrier plate 101. Figure 4 shows the encapsulation of, for example, resin material on the surface of the mold 201, such that the protrusions on the surface of the mold 201 are completely covered by resin, forming the resin carrier plate 101. Figure 5 shows the resin carrier plate 101 being detached from the mold 201, resulting in an individual resin carrier plate 101.

[0048] Step S202: A first wiring structure is formed on the surface of the resin carrier 101. The first wiring structure includes a conductive layer extending from the bottom of a partially recessed groove to the surface 111 of the resin carrier 101.

[0049] As an example, refer to Figures 6 and 7. Figure 6 shows the formation of a metal thin film 301 by metal sputtering on one side of the surface of the resin substrate 101. Figure 7 shows the retention of a conductive layer 121 extending from the bottom of the recessed groove 112b to the surface 111 of the resin substrate 101 by photolithography, etching, and other processes on the metal thin film 301.

[0050] Step S203: Embed the integrated circuit die and the power device into the recessed groove respectively, so that the solder joints on the surface of the integrated circuit die and the solder joints on the surface of the power device are exposed, and the back electrode of the power device is in contact with the conductive layer in the recessed groove.

[0051] Referring to FIG. 8. As an example, the depth of the sink recesses 112a, 112b is configured to match the thickness of the embedded integrated circuit die 104a, power device 104b, so that the surface of the embedded integrated circuit die 104a, power device 104b after embedding remains substantially flush with the surface 111 of the resin carrier board 101. The surface of the integrated circuit die 104a, power device 104b is provided with a press-fit point 141a, 141b, respectively. The conductive layer 121 includes a first sub-portion 12111 provided on the bottom surface of the sink recess 112b. The back surface of the power device 104b facing the bottom surface of the sink recess 112b can be provided with a back surface electrode 142b for forming conductive contact with the first sub-portion 12111.

[0052] Step S204: forming a second wiring structure on the integrated circuit die and the power device for interconnecting the integrated circuit die and the power device, the second wiring structure including a conductive body for interconnecting the press-fit point on the surface of the integrated circuit die, the press-fit point on the surface of the power device, the conductive layer on the surface of the resin carrier board connected with the back surface electrode of the power device, and an external device.

[0053] Specifically, the second wiring structure 105 is formed on the surface 111 of the resin carrier board 101. The conductive body in the second wiring structure 105 includes a plurality of first conductive bodies 151, each of which is electrically connected with the press-fit point 141a of the integrated circuit die 104a, the press-fit point 141b of the power device 104b, and a second conductive body 152 led out at a predetermined position of the partial conductive layer 121 (i.e., the second portion 1212 of the conductive layer 121) on the surface 111. As an example, the second conductive body 152 can be implemented as a package solder point, such as a solder ball formed by BGA packaging.

[0054] Step S205: encapsulating the integrated circuit die and the power device in the resin carrier board from the side of the surface of the resin carrier board.

[0055] Specifically, the encapsulation layer can be an insulating layer made of PI or the like.

[0056] Thus, the embedded packaging structure in FIG. 1 is obtained.

[0057] It can be seen that, by leading out the back surface electrode on the back surface of the power device to the surface through the first wiring structure, and embedding the integrated circuit die and the power device in the sink recesses with depths matching the thicknesses of the integrated circuit die and the power device, so that the press-fit points on the surfaces of the integrated circuit die and the power device are substantially flush with the surface of the resin carrier board, and then performing RDL packaging on the surface to lead out the conductive body from the press-fit points and the back surface electrode, an improved embedded packaging structure and packaging method are implemented, and the problems in the related art are solved.

[0058] In summary, the present disclosure provides an embedded packaging structure and a packaging method for integrated circuit and power device, which are used for packaging integrated circuit die and power device on a resin carrier board. The integrated circuit die has a soldering point on the surface of the chip; the power device has a soldering point on the surface and other electrodes on the back surface. The resin carrier board has a plurality of sunken grooves on the surface, and the depths of the sunken grooves are different to adapt to integrated circuit dies and power devices with different thicknesses; a conductive layer extending to the surface of the resin carrier board is laid on the bottom of the sunken groove in which the power device is embedded; the back surface electrodes of the power device contact the conductive layer, and the back surface electrodes are led out to be connected to the surface of the resin carrier board through the conductive layer on the bottom of the sunken groove; the surface soldering points of the integrated circuit, the surface electrodes of the power device, and the back surface electrodes of the power device are all on the surface of the resin carrier board, the integrated circuit die and the power device are interconnected, and there are conductive bodies for communication with external devices, and the part of the surface conductive bodies of the resin carrier board except the second conductive bodies is encapsulated by an encapsulation layer.

[0059] The above embodiments are only illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed by the present disclosure should still be covered by the protection scope of the present disclosure.

Claims

1. An embedded package structure, comprising: Comprising: a resin board having a plurality of sunken grooves formed on a surface thereof; a first wiring structure including a conductive layer drawn out from a bottom of part of the plurality of sunken grooves to the surface of the resin board; an integrated circuit die and a power device respectively embedded in the plurality of sunken grooves, the integrated circuit die having a surface with a press bonding point, the power device having a back surface electrode in addition to a surface with a press bonding point, the back surface electrode being in contact with the conductive layer provided in the part of the sunken grooves; a second wiring structure interconnecting the integrated circuit die and the power device, including a conductive body interconnecting the press bonding point of the surface of the integrated circuit die, the press bonding point of the surface of the power device, and the conductive layer of the surface of the resin board connected to the back surface electrode of the power device with an external device; and a packaging layer packaging the integrated circuit die and the power device from the surface of the resin board to the resin board.

2. The embedded package structure of claim 1, wherein, The plurality of sunken grooves have a depth matching a thickness of the integrated circuit die or the power device embedded therein.

3. The embedded package structure of claim 1, wherein, The conductive body includes a first conductive body connecting the press bonding point of the integrated circuit die and the press bonding point of the power device, and a second conductive body formed on the first conductive body and the conductive layer of the surface of the resin board for interconnection with the external device.

4. The embedded package structure of claim 3, wherein, The packaging layer exposes the second conductive body.

5. The embedded package structure of claim 3, wherein, The second conductive body is a packaging bonding point.

6. An embedded packaging method, characterized by, Comprising: forming a plurality of sunken grooves on a surface of a resin board; forming a first wiring structure on the surface of the resin board, the first wiring structure including a conductive layer drawn out from a bottom of part of the plurality of sunken grooves to the surface of the resin board; embedding an integrated circuit die and a power device respectively into the plurality of sunken grooves so that a press bonding point of a surface of the integrated circuit die and a press bonding point of a surface of the power device are exposed, and a back surface electrode of the power device is in contact with a conductive layer provided in the part of the sunken grooves; forming a second wiring structure on the integrated circuit die and the power device, the second wiring structure interconnecting the integrated circuit die and the power device, the second wiring structure including a conductive body interconnecting the press bonding point of the surface of the integrated circuit die, the press bonding point of the surface of the power device, and the conductive layer of the surface of the resin board connected to the back surface electrode of the power device with an external device; and packaging the integrated circuit die and the power device from a surface side of the resin board to the resin board. The plurality of sunken grooves have a depth matching a thickness of the integrated circuit die or the power device embedded therein.

7. The method of claim 6, wherein, The conductive body includes a first conductive body connecting the press bonding point of the integrated circuit die and the press bonding point of the power device, and a second conductive body formed on the first conductive body and the conductive layer of the surface of the resin board for interconnection with the external device.

8. The method of claim 6, wherein, The packaging of the integrated circuit die and the power device from the surface side of the resin board to the resin board includes forming a packaging layer on the resin board, the packaging layer covering the second wiring structure and exposing the second conductive body.

9. The method of claim 8, wherein, ​ 10. The method of claim 8, wherein, The second conductive body is a package bump.

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