Display substrate and display device

Abstract

The present application provides a display substrate and a display device. The display substrate comprises a base, a driving circuit layer, a light-emitting structure layer, a first inorganic layer, and multiple first bonding pads. The driving circuit layer comprises multiple pixel circuits, multiple data lines, multiple data traces, and at least one organic layer. The multiple data lines are located in a display region and are electrically connected to the pixel circuits. The multiple data traces are located in a peripheral region and are electrically connected to the multiple data lines. The at least one organic layer is located in the display region and the peripheral region; between a bending region and a first bonding region, the at least one organic layer is located on the side of the multiple data traces away from the base; the at least one organic layer comprises a groove passing through the at least one organic layer in a direction perpendicular to the base; and the groove is at least partially located between the bending region and the first bonding region. The first inorganic layer is at least partially located in the groove. The multiple first bonding pads are located in the first bonding region, the multiple data traces are electrically connected to the multiple first bonding pads, and the multiple first bonding pads are configured to be bonded to a driver chip.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0002] OLED (Organic Light-Emitting Diode) has the advantages of self-luminous, high efficiency, bright color, light and thin, power saving, wide temperature range of use, and has been gradually applied to large area display, lighting and vehicle display fields.

[0003] In the related art, the OLED display substrate includes a display area, a bending area located on one side of the display area, and a binding area located on a side of the bending area away from the display area. A circuit and a signal line are provided between the bending area and the binding area. Water and oxygen in the environment are easy to invade the circuit or the signal line through the bending area, thereby causing the display substrate to have a display problem. SUMMARY

[0004] The present application provides a display substrate and a display device.

[0005] According to a first aspect of an embodiment of the present application, a display substrate is provided. The display substrate includes a display area and a peripheral area located on at least one side of the display area. The peripheral area includes a bending area and a first binding area located on a side of the bending area away from the display area. The display substrate includes:

[0006] a substrate;

[0007] a driving circuit layer located on one side of the substrate. The driving circuit layer includes a plurality of pixel circuits, a plurality of data lines, a plurality of data traces, and at least one organic layer. The plurality of data lines are located in the display area. The pixel circuits are located in the display area and electrically connected to the plurality of data lines. The plurality of data traces are located in the peripheral area, and the plurality of data traces are connected to the plurality of data lines. The at least one organic layer is located between the display area and the peripheral area, between the bending area and the first binding area. The at least one organic layer is located on a side of the plurality of data traces away from the substrate. The at least one organic layer includes a groove penetrating the at least one organic layer in a direction perpendicular to the substrate. The groove is at least partially located between the bending area and the first binding area;

[0008] a light emitting structure layer located on a side of the driving circuit layer away from the substrate. The light emitting structure layer includes a pixel definition layer and a plurality of light emitting elements. The pixel definition layer has a plurality of pixel openings. Light emitting layers of the plurality of light emitting elements are located in the plurality of pixel openings. The pixel circuits are configured to drive the light emitting elements.

[0009] a first inorganic layer at least partially located in the recess;

[0010] a plurality of first bonding pads located in the first bonding area, the plurality of data traces being electrically connected with the plurality of first bonding pads, the plurality of first bonding pads being configured to be bonded with a driving chip.

[0011] In one embodiment, the display substrate further comprises a second inorganic layer located in the display area and the peripheral area, in the display area, the second inorganic layer is located between the plurality of pixel circuits and the at least one organic layer, and the portion of the first inorganic layer located in the recess directly contacts the second inorganic layer.

[0012] In one embodiment, the display substrate further comprises a touch structure layer located on a side of the light-emitting structure layer away from the substrate, the touch structure layer comprises, in sequence from a side away from the light-emitting structure layer, a touch buffer layer, a first touch conductive layer, a touch interlayer insulating layer, and a second touch conductive layer; and the first inorganic layer comprises at least one of the pixel definition layer, the touch buffer layer, and the touch interlayer insulating layer.

[0013] In one embodiment, the pixel definition layer, the touch buffer layer, and the touch interlayer insulating layer are all inorganic insulating layers, and the first inorganic layer comprises the pixel definition layer, the touch buffer layer, and the touch interlayer insulating layer.

[0014] In one embodiment, the recess comprises a side surface and a bottom surface, and the first inorganic layer covers the side surface and the bottom surface.

[0015] In one embodiment, the display substrate further comprises a touch structure layer located on a side of the light-emitting structure layer away from the substrate, the touch structure layer comprises, in sequence from a side away from the light-emitting structure layer, a touch buffer layer, a first touch conductive layer, a touch interlayer insulating layer, and a second touch conductive layer; and the first inorganic layer comprises the pixel definition layer, the touch buffer layer, and the touch interlayer insulating layer, and the pixel definition layer, the touch buffer layer, and the touch interlayer insulating layer respectively cover the side surface and the bottom surface.

[0016] In one embodiment, the driving circuit layer further comprises a power signal line located between the bending area and the first bonding area, the power signal line extends along a first direction, the at least one organic layer covers the power signal line, and the recess is at least partially located between the power signal line and the bending area.

[0017] In an embodiment, the display substrate comprises an electrostatic discharge circuit between the bending area and the first binding area, the at least one organic layer covers the electrostatic discharge circuit; the electrostatic discharge circuit is electrically connected with the plurality of data traces and the power signal line, and is configured to discharge static electricity on the plurality of data traces to the power signal line; the groove comprises a first sub-groove between the electrostatic discharge circuit and the bending area.

[0018] In an embodiment, the groove further comprises a second sub-groove between the electrostatic discharge circuit and the plurality of first binding pads.

[0019] In an embodiment, the display substrate further comprises a first test circuit between the bending area and the first binding area, the at least one organic layer covers the first test circuit; the first test circuit is electrically connected with the plurality of data traces, and is configured to detect whether the plurality of sub-pixels can be lit in the display substrate preparation stage.

[0020] The first test circuit is between the electrostatic discharge circuit and the second sub-groove.

[0021] In an embodiment, the display substrate further comprises a first test circuit and a second test circuit between the bending area and the first binding area, the at least one organic layer covers the first test circuit and the second test circuit; the first test circuit is electrically connected with the plurality of data traces, and is configured to detect whether the plurality of sub-pixels can be lit in the display substrate preparation stage; the second test circuit is electrically connected with the plurality of data traces, and is configured to detect whether the display substrate has cracks by detecting whether the plurality of sub-pixels have bright lines in the display substrate preparation stage.

[0022] The second test circuit is on a side of the first test circuit away from the first sub-groove, and is between the first test circuit and the second sub-groove.

[0023] In one embodiment, the display substrate further comprises a first test circuit and a second test circuit between the bending area and the first binding area, the second test circuit is located on a side of the first test circuit away from the first sub-groove, and the at least one organic layer covers the first test circuit and the second test circuit; the first test circuit is electrically connected with the plurality of data wires and is configured to detect whether the plurality of sub-pixels can be lit in the display substrate preparation stage; the second test circuit is electrically connected with the plurality of data wires and is configured to detect whether the plurality of sub-pixels appear bright lines in the display substrate preparation stage, and then determine whether the display substrate appears cracks.

[0024] The groove comprises a third sub-groove and a fourth sub-groove, the second sub-groove is located between the second sub-test circuit and the first binding area; the third sub-groove and the fourth sub-groove are respectively located on both sides of the electrostatic discharge circuit and are respectively connected with the first sub-groove and the second sub-groove, and the electrostatic discharge circuit, the first test circuit and the second test circuit are located in the area surrounded by the first sub-groove, the third sub-groove, the second sub-groove and the first sub-groove.

[0025] In one embodiment, the display substrate further comprises a first test circuit between the bending area and the first binding area, and the at least one organic layer covers the first test circuit; the first test circuit is electrically connected with the plurality of data wires and is configured to detect whether the plurality of sub-pixels can be lit in the display substrate preparation stage; the groove further comprises a third sub-groove and a fourth sub-groove; the first test circuit is located between the electrostatic discharge circuit and the second sub-groove; the third sub-groove and the fourth sub-groove are respectively located on both sides of the electrostatic discharge circuit and are respectively connected with the first sub-groove and the second sub-groove, and the electrostatic discharge circuit and the first test circuit are located in the area surrounded by the first sub-groove, the third sub-groove, the second sub-groove and the first sub-groove.

[0026] In one embodiment, the groove between the bending area and the first binding area is a strip-shaped groove, the extension direction of the strip-shaped groove is parallel to the edge of the display area close to the bending area, and the strip-shaped groove penetrates the at least one organic layer along its extension direction.

[0027] In one embodiment, the drive circuit layer comprises at least one thin film transistor and a first planar layer, the first planar layer is located on a side of the at least one thin film transistor away from the substrate, the at least one thin film transistor comprises an active layer, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate, the light emitting element is electrically connected to one of the source or the drain through a via in the first planar layer; the number of the at least one organic layer is one layer, and the one layer of organic layer is located in the same layer as the first planar layer.

[0028] In one embodiment, the drive circuit layer comprises at least one thin film transistor and a first planar layer, the first planar layer is located on a side of the at least one thin film transistor away from the substrate, the at least one thin film transistor comprises an active layer, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate; the drive circuit layer further comprises a first transfer electrode and a second planar layer arranged in sequence away from the first planar layer, the first transfer electrode is electrically connected to the source or the drain through a via in the first planar layer; the light emitting element is electrically connected to the first transfer electrode through a via in the second planar layer.

[0029] The number of the at least one organic layer is two layers, and the two layers of organic layer are respectively located in the same layer as the first planar layer and the second planar layer.

[0030] In one embodiment, the drive circuit layer comprises at least one thin film transistor and a first planar layer, the first planar layer is located on a side of the at least one thin film transistor away from the substrate, the at least one thin film transistor comprises an active layer, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate; the drive circuit layer further comprises a first transfer electrode, a second planar layer, a second transfer electrode and a third planar layer arranged in sequence away from the first planar layer, the second transfer electrode is electrically connected to the first transfer electrode through a via in the second planar layer, and the light emitting element is electrically connected to the second transfer electrode through a via in the third planar layer.

[0031] The number of the at least one organic layer is three layers, and the three layers of organic layer are respectively located in the same layer as the first planar layer, the second planar layer and the third planar layer.

[0032] According to a second aspect of the embodiments of the present application, a display device is provided, which comprises the display substrate described above.

[0033] The display substrate and the display device provided by the embodiments of the present application can improve the encapsulation performance of the display substrate by arranging a groove in at least one organic layer on the side of the data wire away from the substrate, the groove penetrating the at least one organic layer in a direction perpendicular to the substrate, and the groove being at least partially located between the bending area and the first binding area, and the first inorganic layer being at least partially located in the groove, so that the path of the water and oxygen entering the at least one organic layer through the bending area and then transmitted along the at least one organic layer to the circuit or signal line between the groove and the first binding area is blocked, and the electrochemical corrosion of the circuit or signal line between the groove and the first binding area caused by the water and oxygen can be avoided, thereby improving the performance of the display substrate. BRIEF DESCRIPTION OF DRAWINGS

[0034] FIG. 1 is a schematic diagram of a display substrate provided by an example embodiment of the present application;

[0035] FIG. 2 is a sectional view of the display substrate shown in FIG. 1 along AA;

[0036] FIG. 3 is another sectional view of the display substrate shown in FIG. 1 along AA;

[0037] FIG. 4 is still another sectional view of the display substrate shown in FIG. 1 along AA;

[0038] FIG. 5 is a schematic diagram of a display substrate provided by an example embodiment of the present application;

[0039] FIG. 6 is a partial enlarged view of a first binding area provided by an example embodiment of the present application;

[0040] FIG. 7 is a detailed enlarged view of region S in FIG. 6;

[0041] FIG. 8 is a structural schematic diagram of an electrostatic discharge circuit of a display substrate provided by an example embodiment of the present application;

[0042] FIG. 9 is another sectional view of the display substrate shown in FIG. 5 along BB;

[0043] FIG. 10 is a schematic diagram of a display substrate provided by another example embodiment of the present application;

[0044] FIG. 11 is a schematic diagram of a display substrate provided by still another example embodiment of the present application;

[0045] FIG. 12 is a schematic diagram of a display substrate provided by yet another example embodiment of the present application;

[0046] FIG. 13 is a schematic diagram of a display substrate provided by yet another example embodiment of the present application;

[0047] FIG. 14 is a schematic diagram of a display substrate provided by yet another example embodiment of the present application;

[0048] FIG. 15 is a schematic view of a display substrate according to another example embodiment of the present application;

[0049] FIG. 16 is a schematic view of a display substrate according to another example embodiment of the present application;

[0050] FIG. 17 is a schematic view of a display substrate according to another example embodiment of the present application;

[0051] FIG. 18 is a schematic view of a display substrate according to another example embodiment of the present application. DETAILED DESCRIPTION

[0052] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings. When the following description refers to the drawings, identical or similar elements in different drawings are denoted by identical reference numerals, unless otherwise indicated. The following examples and features in the examples can be combined with each other, without conflict.

[0053] The display substrate according to an embodiment of the present application is provided. As shown in FIG. 1, the display substrate 100 includes a display area 110 and a peripheral area 120 located at least one side of the display area 110. The display substrate 100 includes a substrate 10 and a plurality of sub-pixels Pxl. The plurality of sub-pixels Pxl are located in the display area 110. A plurality of data lines DATA are also provided in the display area 110. The plurality of data lines DATA are arranged along a first direction x and extend along a second direction y, and are connected to the plurality of sub-pixels Pxl. A plurality of gate lines GATE are also provided in the display area 110, which extend along the x direction and are arranged along the second direction y. In FIG. 1, each gate line GATE is connected to at least one row of sub-pixels Pxl, and each data line DATA is connected to at least one column of sub-pixels Pxl. In operation, a gate driving signal at the gate line GATE will turn on the row of sub-pixels connected thereto, and the data signals at the data lines DATA connected to the row of sub-pixels will be input to the row of sub-pixels Pxl respectively, so that the row of sub-pixels emits light. The sub-pixel includes a pixel circuit and a light emitting device, and the pixel circuit is configured to drive the light emitting device. The pixel circuit is electrically connected to the display area 110 and the data line DATA.

[0054] Although the above describes an example in which each data line is connected to one column of sub-pixels and each gate line is connected to one row of sub-pixels, the embodiments of the present application are not limited thereto. The data lines and the gate lines can connect the sub-pixels in any other manner as needed, such as each gate line connecting two or more rows of sub-pixels, or each data line connecting two or more columns of sub-pixels, and the like.

[0055] FIG. 2 is a schematic diagram of a partial cross-sectional view of a display area of a display substrate according to at least one embodiment of the present application. In FIG. 2, the structure of one sub-pixel of the display area is taken as an example for illustration. In the present example, the same type of transistors in the pixel circuit is taken as an example for illustration, for example, the transistors in the pixel circuit can all be low-temperature polysilicon thin film transistors or all be oxide thin film transistors. In other examples, the transistors in the pixel circuit can be low-temperature polysilicon thin film transistors and oxide thin film transistors. In addition, the present example takes the display substrate integrating a mutual-capacitance touch structure to form an FMLOC structure as an example for illustration.

[0056] In some examples, as shown in FIG. 2, in a direction perpendicular to the display surface of the display substrate, the display substrate includes a substrate 10, and a driving circuit layer 20, a light-emitting structure layer 30, an encapsulation structure layer 40, a touch structure layer 50, a color filter layer 60, and an insulating protective layer 93 arranged in sequence on the substrate 10. The display structure layer can include at least the driving circuit layer 20 and the light-emitting structure layer 30. The driving circuit layer 20 can include at least the pixel circuit of a plurality of sub-pixels, and each pixel circuit of a sub-pixel can include a plurality of transistors and at least one capacitor. The light-emitting structure layer 30 can include at least the light-emitting element of a plurality of sub-pixels.

[0057] In some examples, FIG. 2 is a schematic diagram of one thin film transistor 21 and one capacitor 22 included in each sub-pixel. In some examples, the driving circuit layer 20 can include a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 10. The plurality of display area metal layers of the display structure layer of the present example can include the first gate metal layer, the second gate metal layer, the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer. A first gate insulating layer 101 can be disposed between the semiconductor layer and the first gate metal layer, a second gate insulating layer 102 can be disposed between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 103 can be disposed between the second gate metal layer and the first source-drain metal layer, a passivation layer 104 and a first planarization layer 105 can be disposed between the first source-drain metal layer and the second source-drain metal layer, a second planarization layer 106 can be disposed between the second source-drain metal layer and the third source-drain metal layer, and a third planarization layer 107 can be disposed on the side of the third source-drain metal layer away from the substrate 10. The first gate insulating layer 101, the second insulating layer 102, the interlayer insulating layer 103, and the passivation layer 104 can be inorganic insulating layers, and the first planarization layer 105, the second planarization layer 106, and the third planarization layer 107 can be organic insulating layers. However, the present embodiment is not limited thereto. In other examples, a buffer layer can be further disposed on the side of the semiconductor layer close to the substrate. The buffer layer can prevent harmful substances in the substrate from invading the inside of the display substrate, and can also increase the adhesion of the film layers in the display substrate to the substrate. In other examples, a bottom shielding metal layer (BSM) can be disposed on the side of the buffer layer close to the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the thin film transistor of the pixel circuit, so as to avoid the influence of external light on the performance of the thin film transistor. In other examples, the passivation layer can be omitted between the first source-drain metal layer and the second source-drain metal layer, and only the first planarization layer can be disposed between the first source-drain metal layer and the second source-drain metal layer.

[0058] In some examples, as shown in FIG. 2, the semiconductor layer of the display area can at least include: an active layer 210 of a thin film transistor 21. The active layer 210 of the thin film transistor 21 can include: a first region 2101, a second region 2102, and a channel region 2100 between the first region 2101 and the second region 2102. The first gate metal layer can at least include: a gate 213 of the thin film transistor 21, and a first plate 221 of a capacitor 22. The gate 213 of the thin film transistor 21 can cover the channel region 2100 of the active layer 210 in the orthographic projection of the substrate 10. The second gate metal layer can at least include: a second plate 222 of the capacitor 22. The second plate 222 and the first plate 221 of the capacitor 22 can at least partially overlap in the orthographic projection of the substrate 10, for example, the two can coincide. The first source-drain metal layer can at least include: a source 211 and a drain 212 of the thin film transistor 21. The interlayer insulating layer 103 can be provided with a plurality of vias (for example, including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the first pixel via can be removed to expose at least part of the surface of the first region 2101 of the active layer 210; the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the second pixel via can be removed to expose at least part of the surface of the second region 2102 of the active layer 210. The source 211 of the thin film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer can at least include: a first transfer electrode 251. The first transfer electrode 251 can be electrically connected to the drain 212 of the thin film transistor 21 of the pixel circuit through a third pixel via provided by the passivation layer 104 and the first planarization layer 105. The third source-drain metal layer can at least include a second transfer electrode 252. The second transfer electrode 252 can be electrically connected to the first transfer electrode 251 of the second source-drain metal layer through a fourth pixel via provided by the second planarization layer 106. The second transfer electrode 252 can be electrically connected to the first electrode 301 (for example, an anode) of the light emitting element through a fifth pixel via provided by the third planarization layer 107. The first transfer electrode 251 and the second transfer electrode 252 can be used to electrically connect the pixel circuit and the light emitting element in the present example.

[0059] In some examples, the gate lines of the display area can be located in the first gate metal layer, for example, the data lines of the display area can be located in the second source-drain metal layer or the third source-drain metal layer, and the high potential power lines of the display area can be located in at least one of the second source-drain metal layer and the third source-drain metal layer. The present embodiment is not limited in this regard. The driving circuit layer of the present example can include three source-drain metal layers, which can avoid arranging more traces in a single source-drain metal layer, thereby facilitating the realization of a narrow frame structure.

[0060] In some examples, as shown in FIG. 2, the light-emitting structure layer 30 can include a pixel definition layer 304 and a plurality of light-emitting elements. For example, each light-emitting element can include a first electrode 301, an organic light-emitting layer 302, and a second electrode 303 stacked. The first electrode 301 of the light-emitting element can be an anode, and the first electrode 301 can be disposed on the third planar layer 107 and electrically connected to the second transfer electrode 252 through a fifth pixel via hole opened in the third planar layer 107. The pixel definition layer 304 is disposed on the first electrode 301 and the third planar layer 107, and the pixel definition layer 304 can be provided with a plurality of pixel openings, and each pixel opening can expose at least part of the surface of the corresponding first electrode 301. At least part of the organic light-emitting layer 302 can be disposed in one pixel opening and connected to the corresponding first electrode 301. The second electrode 303 can be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303. The side of the pixel definition layer 304 away from the substrate 10 can also be provided with a spacer layer, and the spacer layer can include a plurality of spacer columns (PS).

[0061] In some examples, the organic light-emitting layer 302 of the light-emitting element can include an emitting layer (EML) and one or more film layers including a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting characteristics of the organic material can be utilized to emit light according to the required gray scale.

[0062] In some examples, the organic light emitting layers of the light emitting elements of different colors can be different. For example, the red light emitting element includes a red light emitting layer, the green light emitting element includes a green light emitting layer, and the blue light emitting element includes a blue light emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer located on one side of the organic light emitting layer can adopt a common layer, and the electron injection layer and the electron transport layer located on the other side of the organic light emitting layer can adopt a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by one process (one evaporation process or one inkjet printing process), and isolation can be achieved by the surface step of the formed film layer or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light emitting layer can be prepared by evaporation using a fine metal mask (FMM) or an open mask, or by an inkjet process.

[0063] In some examples, as shown in FIG. 2, the encapsulation structure layer 40 can include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked. The first encapsulation layer 401 and the third encapsulation layer 403 can be made of inorganic materials, and the second encapsulation layer 402 can be made of an organic material. The second encapsulation layer 402 can be arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to prevent external water vapor from entering the light emitting element. However, the present embodiment is not limited thereto. For example, the encapsulation structure layer can adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0064] In one embodiment, as shown in FIG. 2, the touch structure layer 50 includes a touch buffer layer 511, a first touch conductive layer 501, a touch interlayer insulating layer 512, and a second touch conductive layer 502 arranged in sequence away from the light emitting structure layer 30.

[0065] In one embodiment, as shown in FIG. 2, the color filter layer 60 includes a black matrix layer 61 and a plurality of color filter portions 62. The black matrix layer 61 is provided with a plurality of spaced-apart openings, and each color filter portion 62 is located in one opening. The plurality of color filter portions 62 correspond one-to-one to the plurality of light emitting elements, and the orthographic projection of each color filter portion 62 on the substrate covers the orthographic projection of the pixel opening corresponding to the light emitting element on the substrate. The color of each color filter portion 62 is the same as the light emitting color of the corresponding light emitting element. The color filter layer 60 can be located only in the display area 110.

[0066] In one embodiment, as shown in FIG. 2, the insulating protective layer 93 covers the color filter layer 60. The material of the insulating protective layer 93 can be an organic material. The insulating protective layer 93 is located in the display area 110 and the peripheral area 120.

[0067] FIG. 3 is a schematic view of a partial cross section of a display area of a display substrate according to another embodiment of the present application. In FIG. 3, the structure of one sub-pixel of the display area is taken as an example. Hereinafter, only the differences between FIG. 3 and FIG. 2 will be described, and the same parts will not be described again. The embodiment shown in FIG. 3 differs from the embodiment shown in FIG. 2 in that the drive circuit layer 20 does not include the third source-drain metal layer and the third planarization layer 107, and the first transfer electrode 251 of the second source-drain metal layer is electrically connected to the first electrode 301 of the light emitting element through a via hole formed in the second planarization layer 106.

[0068] FIG. 4 is a schematic view of a partial cross section of a display area of a display substrate according to another embodiment of the present application. In FIG. 4, the structure of one sub-pixel of the display area is taken as an example. Hereinafter, only the differences between FIG. 4 and FIG. 2 will be described, and the same parts will not be described again. The embodiment shown in FIG. 4 differs from the embodiment shown in FIG. 2 in that the drive circuit layer 20 does not include the second source-drain metal layer, the third source-drain metal layer, the second planarization layer 106 and the third planarization layer 107, and the drain 212 of the thin film transistor 21 is electrically connected to the first electrode 301 of the light emitting element through a via hole formed in the first planarization layer 105 and the passivation layer 104.

[0069] In one embodiment, in the embodiments shown in FIG. 2 to FIG. 4, the display substrate can not include the passivation layer 104. In the embodiments shown in FIG. 2 and FIG. 3, when the display substrate does not include the passivation layer 104, the first transfer electrode 251 is electrically connected to the drain 212 of the thin film transistor 21 of the pixel circuit through a via hole formed in the first planarization layer 105. In the embodiment shown in FIG. 4, when the display substrate does not include the passivation layer 104, the first electrode 301 is electrically connected to the drain 212 of the thin film transistor 21 of the pixel circuit through a via hole formed in the first planarization layer 105.

[0070] In one embodiment, as shown in FIG. 1 and FIG. 5, the peripheral area 120 of the display substrate 100 surrounds the display area 110. The peripheral area 120 includes a bending area 121 located at one side of the display area 110 and a first binding area 122 located at a side of the bending area 121 away from the display area 110. The peripheral area 120 of the display substrate 100 further includes a second binding area 123 located at a side of the first binding area 122 away from the display area 110. The first binding area 122 is provided with a plurality of first binding pads 91 (see FIG. 9) configured to be bound with a driving chip. The second binding area 123 is provided with a plurality of second binding pads configured to be bound with a circuit board. The first binding pads and the second binding pads are electrically connected by wires AL.

[0071] In one embodiment, as shown in FIG. 1 and FIG. 5, the peripheral area 120 further includes a first sub-peripheral area 124 and a second sub-peripheral area 125 located at opposite sides of the display area 110.

[0072] In one embodiment, as shown in FIG. 5, the display substrate 100 further includes a gate driving circuit and a plurality of signal lines connected to the gate driving circuit located in the first sub-peripheral area 124 and the second sub-peripheral area 125. The gate driving circuit includes a plurality of first shift registers GOA0, GOA1, …, GOAn cascaded in multiple stages. The signal lines connected to the gate driving circuit include a first start voltage signal line GSTV, a first clock signal line GCK, a second clock signal line GCB, a high-level power supply signal line VGH, and a low-level power supply signal line VGL.

[0073] In some embodiments, as shown in FIG. 5, the display substrate further includes a plurality of data traces DL located in the peripheral area 120 and extending from the edge 111 of the display area 110 close to the bending area 121 to the first binding area 122 along a second direction y. The plurality of data traces DL are connected to the plurality of data lines DATA, and the plurality of data traces DL are connected to the plurality of first binding pads 91. Specifically, the plurality of data traces DL are connected to the plurality of data lines DATA one-to-one, and the plurality of data traces DL are connected to the plurality of first binding pads 91 one-to-one.

[0074] FIG. 6 is a partial enlarged view of the first bonding area 122 according to an embodiment of the present application. As shown in FIG. 6, the plurality of first bonding pads 91 of the first bonding area 122 can be arranged in multiple rows (for example, four rows). Each row of the plurality of first bonding pads 91 can be arranged in sequence along a first direction x, and the multiple rows of the first bonding pads 91 can be arranged in sequence along a second direction y. The first bonding pads 91 of adjacent two rows can be arranged in staggered manner along the first direction x. However, the present embodiment is not limited thereto. In other examples, the plurality of first bonding pads 91 of the first bonding area 122 can be arranged in one row.

[0075] In some embodiments, the plurality of first bonding pads 91 of the first bonding area 122 can be divided into at least multiple groups (for example, two groups). FIG. 6 takes two groups of pads (a first group of pads 1221 and a second group of pads 1222) as an example for illustration and description. The second group of pads 1222 can be located on a side of the first group of pads 1221 away from the display area. The first group of pads 1221 can include three rows of the plurality of first bonding pads 91 arranged along the first direction x. The second group of pads 1222 can include one row of the plurality of first bonding pads 91 arranged along the first direction x. The first group of pads 1221 and the second group of pads 1222 can be arranged in staggered manner along the first direction x. For example, the first bonding pads 91 in the first group of pads 1221 and the second group of pads 1222 can not be aligned along the second direction y. There is a gap between adjacent first bonding pads 91 in the same group, and there is a gap between the first bonding pads 91 of adjacent groups. In some embodiments, a group of pads can be one row of first bonding pads 91, two rows of first bonding pads 91, or three rows of first bonding pads 91. The present application is not limited to the number of rows of pads and the number of pads in each row. The first bonding pads 91 of the first group of pads 1221 are connected to the plurality of data lines DL. The plurality of first bonding pads 91 of the second group of pads 1222 are connected to the plurality of second bonding pads of the second bonding area 123 in one-to-one correspondence through the conductive wires AL. The plurality of first bonding pads 91 of the second group of pads 1222 are used to input signals, which are converted by the bonded driving chip and then output to the first bonding pads 91 of the first group of pads 1221.

[0076] FIG. 7 is a detailed enlarged view of the area S in FIG. 6. In some examples, as shown in FIG. 7, the plurality of data line wires DL can extend in the gap between the plurality of first bonding pads 91 along the second direction y. For example, two data line wires DL can be arranged between adjacent two first bonding pads 91 of a group of pads. One data line wire DL can be electrically connected to at least one first bonding pad 91, for example, one data line wire DL can be connected to one first bonding pad 91. The cross-sectional view of the first bonding pad 91 referred to hereinafter in the present application can be taken along the CC line in FIG. 7.

[0077] In an embodiment, as shown in FIG. 5, the display substrate 100 further comprises an electrostatic discharge circuit 71 and power signal lines 711, 712 between the bending area 121 and the first binding area 122, the power signal lines 711, 712 extending along the first direction x; the electrostatic discharge circuit 71 is electrically connected to the plurality of data lines DL and the power signal lines 711, 712, and is configured to discharge static electricity on the plurality of data lines DL to the power signal lines 711, 712. The electrostatic discharge circuit 71 is connected to the high-level power signal line VGH through the power signal line 711, and is connected to the low-level power signal line VGL through the power signal line 712.

[0078] In an embodiment, as shown in FIG. 5, the display substrate 100 further comprises a first test circuit 72 between the bending area 121 and the first binding area 122, the first test circuit 72 being electrically connected to the plurality of data lines DL, and being configured to detect whether the plurality of sub-pixels Pxl can be lit in the display substrate manufacturing stage. The first test circuit 72 is between the electrostatic discharge circuit 71 and the first binding area 122.

[0079] In an embodiment, as shown in FIG. 5, the display substrate 100 further comprises a second test circuit 73 between the bending area 121 and the first binding area 122, the second test circuit 73 being electrically connected to the plurality of data lines DL, and being configured to detect whether the plurality of sub-pixels Pxl appear bright lines by controlling the second test circuit 73 in the display substrate manufacturing stage, so as to determine whether the display substrate appears cracks. The second test circuit 73 is between the first test circuit 72 and the first binding area 122.

[0080] In an embodiment, as shown in FIG. 5, each data line DL is electrically connected to the electrostatic discharge circuit 71, the first test circuit 72 and the second test circuit 73.

[0081] In an embodiment, as shown in FIG. 8, the electrostatic discharge circuit 71 can comprise a plurality of electrostatic discharge units 713, the plurality of electrostatic discharge units 713 being connected to the plurality of data lines DL. The power signal line 711 and the power signal line 712 are respectively electrically connected to the plurality of electrostatic discharge units 713. Two adjacent electrostatic discharge units 713 in the second direction y are respectively connected to different data lines DL. The two adjacent data lines DL can be located in different metal layers, for example, one is located in the first gate metal layer, and the other is located in the second gate metal layer. In the embodiment shown in FIG. 8, each electrostatic discharge unit 713 comprises four thin film transistors. In other embodiments, each electrostatic discharge unit 713 can comprise two thin film transistors, or three or more thin film transistors.

[0082] Similarly, in some embodiments, the first test circuit 72 can include a plurality of first test sub-circuits connected to the plurality of data lines DL one-to-one.

[0083] In one embodiment, as shown in FIG. 5, each of the first start voltage signal lines GSTV, each of the first clock signal lines GCK, and each of the second clock signal lines GCB extends to the first bonding area 122.

[0084] In one embodiment, as shown in FIG. 5 and FIG. 9, the display substrate further includes a first inorganic layer 80, and the driving circuit layer 20 includes at least one organic layer 23; between the bending area 121 and the first bonding area 122, the at least one organic layer 23 is located on a side of the plurality of data lines DL away from the substrate 10, and the at least one organic layer 23 includes a groove 231 penetrating the at least one organic layer 23 in a direction perpendicular to the substrate 10, and the groove 231 is at least partially located between the bending area 121 and the first bonding area 122.

[0085] The display substrate provided by the embodiments of the present application can improve the encapsulation performance of the display substrate. The groove 231 penetrating the at least one organic layer 23 in a direction perpendicular to the substrate 10 is at least partially located between the bending area 121 and the first bonding area 122, and the first inorganic layer 80 is at least partially located in the groove 231. Thus, the transmission path of water and oxygen along the at least one organic layer 23 to the circuit or signal line located between the groove 231 and the first bonding area 122 is blocked, and the performance of the circuit or signal line located between the groove 231 and the first bonding area 122 affected by the electrochemical corrosion caused by the invasion of water and oxygen can be improved, which helps to improve the encapsulation performance of the display substrate.

[0086] In one embodiment, as shown in FIG. 9, the driving circuit layer 20 further includes a second inorganic layer 24 located in the display area 110 and the peripheral area 120. In the display area 110, the second inorganic layer 24 is located between the plurality of pixel circuits and the at least one organic layer 23, and the part of the first inorganic layer 80 located in the groove 231 directly contacts the second inorganic layer 24. In this way, even if water and oxygen are transmitted along the side surface of the groove 231 to the direction close to the substrate 10, the second inorganic layer 24 can block the transmission path of water and oxygen, which can further improve the effect of preventing the invasion of water and oxygen; and the adhesion between the first inorganic layer 80 and the second inorganic layer 24 is good, which helps to prevent the separation of the first inorganic layer 80 and the second inorganic layer 24.

[0087] In one embodiment, the display substrate includes the passivation layer 104, and the second inorganic layer 24 is a portion of the passivation layer 104 located in the peripheral area 120. In other embodiments, the display substrate does not include the passivation layer 104, and the second inorganic layer 24 is a portion of the interlayer insulating layer 103 located in the peripheral area 120.

[0088] In one embodiment, as shown in FIG. 9, the first inorganic layer 80 includes at least one of the pixel definition layer 304, the touch buffer layer 511, and the touch interlayer insulating layer 512. In this way, the formation of the first inorganic layer 80 does not increase the process steps of the display substrate. In other embodiments, the first inorganic layer 80 is only located in the peripheral area 120 and is not formed simultaneously with the inorganic film layer of the display area.

[0089] In one embodiment, the first inorganic layer 80 includes the pixel definition layer 304. The pixel definition layer 304 is in direct contact with the at least one organic layer 23. In the process of preparing the display substrate, a water washing process is not required before the formation of the pixel definition layer 304, which can prevent water and oxygen from invading the at least one organic layer 23 during the water washing process and further invading the circuit and signal lines located between the bending area 121 and the first binding area 122 through the at least one organic layer 23.

[0090] In one embodiment, as shown in FIG. 9, the pixel definition layer 304, the touch buffer layer 511, and the touch interlayer insulating layer 512 are all inorganic insulating layers, and the first inorganic layer 80 includes the pixel definition layer 304, the touch buffer layer 511, and the touch interlayer insulating layer 512. In this way, the first inorganic layer 80 has a better water and oxygen blocking effect, which can further reduce the risk of water and oxygen invading the circuit or signal lines located in the groove 231 and the first binding area 122.

[0091] In one embodiment, the groove 231 includes a side surface and a bottom surface, and the first inorganic layer 80 covers the side surface and the bottom surface. In this way, water and oxygen can be effectively prevented from invading the circuit or signal lines located in the groove 231 and the first binding area 122 along the bottom surface or side surface of the groove.

[0092] Further, the first inorganic layer 80 includes the pixel definition layer 304, the touch buffer layer 511, and the touch interlayer insulating layer 512, and the pixel definition layer 304, the touch buffer layer 511, and the touch interlayer insulating layer 512 cover the side surface and the bottom surface, respectively.

[0093] In one embodiment, as shown in FIG. 9, when the structure of the display substrate is as shown in FIG. 2, the number of the at least one organic layer 23 is three, and the three organic layers are located in the same layer as the first planarization layer 105, the second planarization layer 106 and the third planarization layer 107 respectively.

[0094] In one embodiment, as shown in FIG. 9, when the structure of the display substrate is as shown in FIG. 2, the number of the at least one organic layer 23 is three, and the three organic layers are located in the same layer as the first planarization layer 105, the second planarization layer 106 and the third planarization layer 107 respectively.

[0095] In one embodiment, as shown in FIG. 9, when the structure of the display substrate is as shown in FIG. 2, the number of the at least one organic layer 23 is three, and the three organic layers are located in the same layer as the first planarization layer 105, the second planarization layer 106 and the third planarization layer 107 respectively.

[0096] In one embodiment, as shown in FIG. 9, the data wire DL includes a first wire segment 27 and a second wire segment 25, the first wire segment 27 is located in the bending area 121, the second wire segment 25 extends from the bending area 121 to the first binding area 122, and the first wire segment 27 is electrically connected to the second wire segment 25; the first wire segment 27 is located on the side of the second wire segment 25 away from the substrate 10, and the electrostatic discharge circuit 71, the first test circuit 72, the second test circuit 73 and the first binding pad 91 are all connected to the second wire segment 25.

[0097] In one embodiment, as shown in FIG. 9, the first wire segment 27 is located in the second source-drain metal layer, the second wire segment 25 is located in the first gate metal layer, and the first wire segment 27 is electrically connected to the second wire segment 25 through a via hole penetrating through the second gate insulating layer 102, the interlayer insulating layer 103, the passivation layer 104 and the first planarization layer 105.

[0098] In one embodiment, as shown in FIG. 9, the display substrate further includes a first binding pad 91 located in the first binding area 122, and the first binding pad 91 is electrically connected to the second wire segment 25. In some embodiments, the first binding pad 91 includes multiple metal layers, for example, a second sub-pad 912 located in the second source-drain metal layer and a first sub-pad 911 located in the first source-drain metal layer, the second sub-pad 912 is electrically connected to the first sub-pad 911 through a via hole penetrating through the passivation layer 104 and the first planarization layer 105, and the first sub-pad 911 is electrically connected to the second wire segment 25 through a via hole penetrating through the second gate insulating layer 102 and the interlayer insulating layer 103.

[0099] In one embodiment, the at least one organic layer 23 covers the power signal lines 711, 712, and the groove 231 is at least partially located between the power signal lines 711, 712 and the bending area 121, as shown in FIG. 5 and FIG. 9. Specifically, the groove 231 includes a first sub-groove 2311 located between the power signal lines 711, 712 and the bending area 121. In this way, the path of the water and oxygen entering the at least one organic layer 23 through the bending area 121 along the at least one organic layer 23 to the power signal lines 711, 712 is blocked, so as to prevent the water and oxygen entering the at least one organic layer 23 through the bending area 121 from invading the power signal lines 711, 712, thereby improving the problem that the power signal lines 711, 712 (especially the high-level power signal lines) are affected in signal transmission due to electrochemical corrosion caused by the invasion of water and oxygen, and thus the problem of persistent bright lines, abnormal display or no display in the display area of the display substrate during display is solved, and the display effect of the display substrate is improved.

[0100] In one embodiment, the first sub-groove 2311 is located between the electrostatic discharge circuit 71 and the bending area 121, as shown in FIG. 5 and FIG. 9. In this way, the path of the water and oxygen entering the at least one organic layer 23 through the bending area 121 along the at least one organic layer 23 to the electrostatic discharge circuit 71 is blocked, so as to prevent the water and oxygen entering the at least one organic layer 23 through the bending area 121 from invading the electrostatic discharge circuit 71.

[0101] In one embodiment, the groove 231 further includes a second sub-groove 2312 located between the electrostatic discharge circuit 71 and the plurality of first bonding pads 91 of the first bonding area 122, as shown in FIG. 5 and FIG. 9. In this way, the path of the water and oxygen entering the at least one organic layer 23 through the first bonding area 122 along the at least one organic layer 23 to the electrostatic discharge circuit 71 is blocked, so as to prevent the water and oxygen entering the at least one organic layer 23 through the first bonding area 122 from invading the electrostatic discharge circuit 71.

[0102] Further, the second sub-groove 2312 is located between the second test circuit 72 and the first bonding area 122, that is, the first test circuit 72 and the second test circuit 73 are located between the second sub-groove 2312 and the first sub-groove 2311, as shown in FIG. 5. In this way, the water and oxygen entering the at least one organic layer 23 through the first bonding area 122 are prevented from invading the first test circuit 72 and the second test circuit 73.

[0103] Further, as shown in FIG. 5, the groove 231 further comprises a third sub-groove 2313 and a fourth sub-groove 2314, the third sub-groove 2313 and the fourth sub-groove 2314 are respectively located on two sides of the electrostatic discharge circuit, and are respectively connected with the first sub-groove 2311 and the second sub-groove 2312, the electrostatic discharge circuit 71, the first test circuit 72 and the second test circuit 73 are all located in the area surrounded by the first sub-groove 2311, the second sub-groove 2312, the third sub-groove 2313 and the fourth sub-groove 2314. In this way, the water and oxygen intruding from the first binding area 122 and the bending area 121 cannot be transmitted to the electrostatic discharge circuit 71, the first test circuit 72 and the second test circuit 73 through any area of the at least one organic layer 23.

[0104] Further, as shown in FIG. 5, the power signal lines 711, 712 are located in the area surrounded by the first sub-groove 2311, the second sub-groove 2312, the third sub-groove 2313 and the fourth sub-groove 2314.

[0105] In an embodiment, as shown in FIG. 9, the display substrate further comprises a sealing glue 92, which protects the part of the at least one organic layer 23 located in the bending area 121. The sealing glue 92 has good sealing property, which can improve the packaging effect of the bending area 121.

[0106] In an embodiment, as shown in FIG. 10, the groove 231 comprises the first sub-groove 2311, the second sub-groove 2312, the third sub-groove 2313 and the fourth sub-groove 2314, the electrostatic discharge circuit 71 and the power signal lines 711, 712 are located in the area surrounded by the first sub-groove 2311, the second sub-groove 2312, the third sub-groove 2313 and the fourth sub-groove 2314, and the first test circuit 72 is located between the second sub-groove 2312 and the second test circuit 73.

[0107] In an embodiment, as shown in FIG. 11, the groove 231 comprises the first sub-groove 2311, the second sub-groove 2312, the third sub-groove 2313 and the fourth sub-groove 2314, the electrostatic discharge circuit 71, the power signal lines 711, 712 and the second test circuit 73 are located in the area surrounded by the first sub-groove 2311, the second sub-groove 2312, the third sub-groove 2313 and the fourth sub-groove 2314; and the display substrate does not comprise the first test circuit 72.

[0108] In one embodiment, as shown in FIG. 12, the recess 231 includes the first sub-recess 2311, the second sub-recess 2312, the third sub-recess 2313, and the fourth sub-recess 2314, and the electrostatic discharge circuit 71, the power signal lines 711, 712, the first test circuit 72, the second test circuit 73, and the first bonding area 122 are all located in the area surrounded by the first sub-recess 2311, the second sub-recess 2312, the third sub-recess 2313, and the fourth sub-recess 2314.

[0109] In one embodiment, as shown in FIG. 13, the recess 231 includes the first sub-recess 2311 and the second sub-recess 2312, and the electrostatic discharge circuit 71, the power signal lines 711, 712, the first test circuit 72, and the second test circuit 73 are all located between the first sub-recess 2311 and the second sub-recess 2312. In this embodiment, the recess 231 does not include a third sub-recess and a fourth sub-recess.

[0110] In one embodiment, as shown in FIG. 14, the recess 231 includes the first sub-recess 2311 and the second sub-recess 2312, the electrostatic discharge circuit 71 and the power signal lines 711, 712 are located between the first sub-recess 2311 and the second sub-recess 2312, and the first test circuit 72 and the second test circuit 73 are located between the second sub-recess 2312 and the first bonding area 122. In this embodiment, the recess 231 does not include a third sub-recess and a fourth sub-recess.

[0111] In one embodiment, as shown in FIG. 15, the recess 231 includes the first sub-recess 2311 and the second sub-recess 2312, the electrostatic discharge circuit 71, the power signal lines 711, 712, and the first test circuit 72 are all located between the first sub-recess 2311 and the second sub-recess 2312, and the second test circuit 73 is located between the second sub-recess 2312 and the first bonding area 122. In this embodiment, the recess 231 does not include a third sub-recess and a fourth sub-recess.

[0112] In one embodiment, as shown in FIG. 16, the recess 231 includes the first sub-recess 2311 and the second sub-recess 2312, the display substrate does not include the first test circuit 72, and the electrostatic discharge circuit 71, the power signal lines 711, 712, and the second test circuit 73 are all located between the first sub-recess 2311 and the second sub-recess 2312. In this embodiment, the recess 231 does not include a third sub-recess and a fourth sub-recess.

[0113] In one embodiment, as shown in FIG. 17, the groove 231 only includes a first sub-groove 2311, which is located between the electrostatic discharge circuit 71 and the bending area 121.

[0114] In one embodiment, as shown in FIGS. 13-17, the groove 231 in the portion between the bending area 121 and the first binding area 122 is a strip-shaped groove. The strip-shaped groove is parallel to the edge 111 of the display area 110 close to the bending area 121, and the strip-shaped groove penetrates the at least one organic layer 23 along its extending direction. In this embodiment, the groove 231 does not include the third sub-groove 2313 and the fourth sub-groove 2314. When the groove 231 includes the first sub-groove 2311, the first sub-groove 2311 is a strip-shaped groove extending along the first direction x, and the first sub-groove 2311 penetrates the at least one organic layer 23 along its first direction x. When the groove 231 includes the second sub-groove 2312, the second sub-groove 2312 is a strip-shaped groove extending along the first direction x, and the second sub-groove 2312 penetrates the at least one organic layer 23 along its first direction x. In this way, when the groove 231 includes the first sub-groove 2311, the water and oxygen intruded by the bending area 121 cannot be transmitted to the circuit or signal line located between the first sub-groove 2311 and the first binding area 122 through any area of the at least one organic layer 23, which can effectively isolate the water and oxygen; when the groove 231 includes the second sub-groove 2312, the water and oxygen intruded by the first binding area 122 cannot be transmitted to the circuit or signal line located between the second sub-groove 2312 and the first binding area 122 through any area of the at least one organic layer 23, which can effectively isolate the water and oxygen. Here, the strip-shaped groove being parallel to the edge 111 of the display area 110 close to the bending area 121 means that the two are substantially parallel, for example, the included angle between the two is less than or equal to 10°, which can be considered as parallel.

[0115] In one embodiment, as shown in FIG. 18, the at least one inorganic layer 23 is provided with a groove 232 located in the first sub-peripheral area 124 and a groove 233 located in the second sub-peripheral area 125; in the first sub-peripheral area 1024, the groove 232 is located on the side of the gate drive circuit and the signal line connected with the gate drive circuit away from the display area 110; in the second sub-peripheral area 1025, the groove 233 is located on the side of the gate drive circuit and the signal line connected with the gate drive circuit away from the display area 110. In this way, the path of the water and oxygen entering the at least one organic layer 23 from the external environment to the gate drive circuit and the signal line connected with the gate drive circuit is blocked, which can prevent the water and oxygen from intruding into the gate drive circuit and the signal line connected with the gate drive circuit.

[0116] In one embodiment, the side surface of the groove 231, 232, 233 extends outwardly in a direction pointing from the substrate 10 to the light-emitting structure layer 30. In this way, the first inorganic layer 80 can be prevented from being broken at the side surface of the groove, and thus water and oxygen can be prevented from entering the at least one organic layer 23 along the broken part of the first inorganic layer 80.

[0117] In one embodiment, the first inorganic layer 80 includes a plurality of inorganic film layers, and the thickness of the inorganic film layer in direct contact with the at least one organic layer is greater than or equal to 1 μm. In this way, the inorganic film layer in direct contact with the at least one organic layer can be prevented from being too thin to be broken at the side surface of the groove.

[0118] The embodiments of the present application also provide a display device, which includes the display substrate described in any of the above embodiments.

[0119] In one embodiment, the display device further includes a driving chip and a power supply circuit, the driving chip is configured to provide a driving signal for driving the sub-pixel to emit light, and the power supply circuit is configured to supply power to the display substrate.

[0120] In one embodiment, the display device further includes a housing, and the display substrate is arranged in the housing.

[0121] The display device provided by the embodiments of the present application can be, for example, a mobile phone, a tablet computer, a television, a notebook computer, a vehicle-mounted device, or any device having a display function.

[0122] It should be noted that in the drawings, the sizes of the layers and regions can be exaggerated for clarity. When an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer, or intervening layers can also be present. When an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or layer, or one or more intervening layers can also be present.

[0123] It should be noted that the technical solutions or technical features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of the present application is not limited to the precise structures described in the above embodiments and shown in the drawings; any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A display substrate, characterized by, The display substrate comprises a display area, a peripheral area located at least one side of the display area, the peripheral area comprising a bending area and a first binding area located at a side of the bending area away from the display area; the display substrate comprises: a substrate; a drive circuit layer located at one side of the substrate, the drive circuit layer comprising a plurality of pixel circuits, a plurality of data lines, a plurality of data traces and at least one organic layer; the plurality of data lines are located in the display area, the pixel circuits are located in the display area and electrically connected with the plurality of data lines; the plurality of data traces are located in the peripheral area, and the plurality of data traces are connected with the plurality of data lines; the at least one organic layer is located in the display area and the peripheral area, between the bending area and the first binding area, the at least one organic layer is located at a side of the plurality of data traces away from the substrate, the at least one organic layer comprises a groove penetrating the at least one organic layer in a direction perpendicular to the substrate, the groove is at least partially located between the bending area and the first binding area; a light emitting structure layer located at a side of the drive circuit layer away from the substrate, the light emitting structure layer comprising a pixel definition layer and a plurality of light emitting elements, the pixel definition layer having a plurality of pixel openings, light emitting layers of the plurality of light emitting elements being located in the plurality of pixel openings; the pixel circuits are configured to drive the light emitting elements; a first inorganic layer at least partially located in the groove; a plurality of first binding pads located in the first binding area, the plurality of data traces being electrically connected with the plurality of first binding pads, the plurality of first binding pads being configured to be bound with a drive chip.

2. The display substrate of claim 1, wherein, The drive circuit layer further comprises a second inorganic layer located in the display area and the peripheral area, in the display area, the second inorganic layer is located between the plurality of pixel circuits and the at least one organic layer, the part of the first inorganic layer located in the groove directly contacts the second inorganic layer.

3. The display substrate of claim 1, wherein, The display substrate further comprises a touch structure layer located at a side of the light emitting structure layer away from the substrate, the touch structure layer comprising, in sequence from a side away from the light emitting structure layer, a touch buffer layer, a first touch conductive layer, a touch interlayer insulating layer and a second touch conductive layer; the first inorganic layer comprises at least one of the pixel definition layer, the touch buffer layer and the touch interlayer insulating layer.

4. The display substrate of claim 3, wherein, The pixel definition layer, the touch buffer layer and the touch interlayer insulating layer are all inorganic insulating layers, and the first inorganic layer comprises the pixel definition layer, the touch buffer layer and the touch interlayer insulating layer.

5. The display substrate of claim 1, wherein, The groove comprises a side surface and a bottom surface, and the first inorganic layer covers the side surface and the bottom surface. 6.The display substrate of claim 5, wherein, The display substrate further comprises a touch structure layer on a side of the light-emitting structure layer away from the substrate, the touch structure layer comprises, in sequence on a side away from the light-emitting structure layer, a touch buffer layer, a first touch conductive layer, a touch interlayer insulating layer, and a second touch conductive layer; the first inorganic layer comprises the pixel definition layer, the touch buffer layer, and the touch interlayer insulating layer, and the pixel definition layer, the touch buffer layer, and the touch interlayer insulating layer cover the side surface and the bottom surface, respectively. 7.The display substrate of claim 1, wherein, The driving circuit layer further comprises a power signal line between the bending area and the first binding area, the power signal line extends along a first direction, the at least one organic layer covers the power signal line, and the groove is at least partially between the power signal line and the bending area. 8.The display substrate of claim 7, wherein, The display substrate comprises an electrostatic discharge circuit between the bending area and the first binding area, the at least one organic layer covers the electrostatic discharge circuit; the electrostatic discharge circuit is electrically connected with the plurality of data traces and the power signal line, the electrostatic discharge circuit is configured to discharge static electricity on the plurality of data traces to the power signal line; the groove comprises a first sub-groove, the first sub-groove is between the electrostatic discharge circuit and the bending area. 9.The display substrate of claim 8, wherein, The groove further comprises a second sub-groove, the second sub-groove is between the electrostatic discharge circuit and the plurality of first binding pads. 10.The display substrate of claim 9, wherein, The display substrate further comprises a first test circuit between the bending area and the first binding area, the at least one organic layer covers the first test circuit; the first test circuit is electrically connected with the plurality of data traces and is configured to detect whether the plurality of sub-pixels can be lit in a preparation stage of the display substrate. The first test circuit is between the electrostatic discharge circuit and the second sub-groove. 11.The display substrate of claim 9, wherein, The display substrate further comprises a first test circuit and a second test circuit between the bending area and the first binding area, the at least one organic layer covers the first test circuit and the second test circuit; the first test circuit is electrically connected with the plurality of data traces and is configured to detect whether the plurality of sub-pixels can be lit in a preparation stage of the display substrate; the second test circuit is electrically connected with the plurality of data traces and is configured to detect whether the plurality of sub-pixels appear bright lines in the preparation stage of the display substrate, and further determine whether the display substrate appears cracks; The second test circuit is on a side of the first test circuit away from the first sub-groove and is between the first test circuit and the second sub-groove. 12.The display substrate of claim 9, wherein, The display substrate further comprises a first test circuit and a second test circuit between the bending area and the first binding area, the second test circuit is located on a side of the first test circuit away from the first sub-groove, and the at least one organic layer covers the first test circuit and the second test circuit; the first test circuit is electrically connected with the plurality of data wires, and is configured to detect whether the plurality of sub-pixels can be lighted in the display substrate preparation stage; the second test circuit is electrically connected with the plurality of data wires, and is configured to detect whether the plurality of sub-pixels appear bright lines in the display substrate preparation stage, and then judge whether the display substrate appears cracks. The groove comprises a third sub-groove and a fourth sub-groove, the second sub-groove is located between the second sub-test circuit and the first binding area; the third sub-groove and the fourth sub-groove are respectively located on two sides of the electrostatic discharge circuit, and are respectively connected with the first sub-groove and the second sub-groove, and the electrostatic discharge circuit, the first test circuit and the second test circuit are located in an area surrounded by the first sub-groove, the third sub-groove, the second sub-groove and the first sub-groove. 13.The display substrate of claim 9, wherein, The display substrate further comprises a first test circuit between the bending area and the first binding area, and the at least one organic layer covers the first test circuit; the first test circuit is electrically connected with the plurality of data wires, and is configured to detect whether the plurality of sub-pixels can be lighted in the display substrate preparation stage; the groove further comprises a third sub-groove and a fourth sub-groove; the first test circuit is located between the electrostatic discharge circuit and the second sub-groove; the third sub-groove and the fourth sub-groove are respectively located on two sides of the electrostatic discharge circuit, and are respectively connected with the first sub-groove and the second sub-groove, and the electrostatic discharge circuit and the first test circuit are located in an area surrounded by the first sub-groove, the third sub-groove, the second sub-groove and the first sub-groove. 14.The display substrate of claim 1, wherein, The groove is a strip-shaped groove between the bending area and the first binding area, the extension direction of the strip-shaped groove is parallel to the edge of the display area close to the bending area, and the strip-shaped groove penetrates the at least one organic layer along the extension direction thereof. 15.The display substrate of claim 1, wherein, The driving circuit layer comprises at least one thin film transistor and a first planar layer, the first planar layer is located on a side of the at least one thin film transistor away from the substrate, the at least one thin film transistor comprises an active layer, a gate electrode located on a side of the active layer away from the substrate, and a source electrode and a drain electrode located on a side of the gate electrode away from the substrate, and the light emitting element is electrically connected with one of the source electrode or the drain electrode through a via in the first planar layer; the number of the at least one organic layer is one layer, and the one layer of organic layer is located in the same layer as the first planar layer. 16.The display substrate of claim 1, wherein, The driving circuit layer comprises at least one thin film transistor and a first planar layer, the first planar layer is located on a side of the at least one thin film transistor away from the substrate, the at least one thin film transistor comprises an active layer, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate; the driving circuit layer further comprises a first transfer electrode and a second planar layer arranged in sequence away from the first planar layer, the first transfer electrode is electrically connected with the source or the drain through a via hole in the first planar layer; the light emitting element is electrically connected with the first transfer electrode through a via hole in the second planar layer. The number of the at least one organic layer is two, and the two organic layers are located in the same layer as the first planar layer and the second planar layer respectively. 17.The display substrate of claim 1, wherein, The driving circuit layer comprises at least one thin film transistor and a first planar layer, the first planar layer is located on a side of the at least one thin film transistor away from the substrate, the at least one thin film transistor comprises an active layer, a gate located on a side of the active layer away from the substrate, and a source and a drain located on a side of the gate away from the substrate; the driving circuit layer further comprises a first transfer electrode, a second planar layer, a second transfer electrode and a third planar layer arranged in sequence away from the first planar layer, the second transfer electrode is electrically connected with the first transfer electrode through a via hole in the second planar layer, and the light emitting element is electrically connected with the second transfer electrode through a via hole in the third planar layer. The number of the at least one organic layer is three, and the three organic layers are located in the same layer as the first planar layer, the second planar layer and the third planar layer respectively.

18. A display device comprising: The display device comprises the display substrate according to any one of claims 1 to 17.

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