Pixel circuit, display panel, and display device comprising same

Abstract

A pixel circuit. One frame period comprises a plurality of sub-periods which are sequentially performed, and each sub-period comprises a light-emitting stage. The pixel circuit comprises a driving sub-circuit and a gating sub-circuit. The driving sub-circuit is connected to a first node, a second node, and a third node. The first node is coupled to a data signal end, and the second node is coupled to a first power supply signal end. The driving sub-circuit is configured to, in the light-emitting stage, generate a driving current signal on the basis of the voltages of the first node and the third node, and transmit the driving current signal to the third node. The gating sub-circuit is connected to the third node. The gating sub-circuit is configured to be connected to a plurality of light-emitting devices, and transmit, in different light-emitting stages to different light-emitting devices, the driving current signal from the third node. The driving sub-circuit comprises a first transistor, the gating sub-circuit comprises second transistors, and a channel of at least one second transistor and a channel of the first transistor are located in different layers and at least partially opposite to each other.

Description

Pixel circuit, display panel and display device thereof

[0001] This application claims priority to the Chinese patent application No. 202410876919.0, filed on July 01, 2024, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit, a display panel and a display device thereof. BACKGROUND

[0003] With the rapid development of display technology, display devices have gradually spread in people's lives. Among them, organic light emitting diodes (OLED) have been widely used in smart products such as mobile phones, televisions, notebook computers, etc. due to their self-luminous, low power consumption, wide viewing angle, fast response speed, high contrast and flexible display advantages. SUMMARY

[0004] In one aspect, a pixel circuit is provided. One frame period includes a plurality of sub-periods performed in sequence, each of the sub-periods including a light emitting phase. The pixel circuit includes a driving sub-circuit and a gating sub-circuit. The driving sub-circuit is connected to a first node, a second node and a third node. The first node is coupled to a data signal terminal, and the second node is coupled to a first power signal terminal. The driving sub-circuit is configured to generate a driving current signal according to voltages of the first node and the third node in the light emitting phase, and transmit the driving current signal to the third node. The gating sub-circuit is connected to the third node. The gating sub-circuit is configured to connect a plurality of light emitting devices, and transmit the driving current signal from the third node to different light emitting devices in different light emitting phases. Wherein, the driving sub-circuit includes a first transistor, the gating sub-circuit includes a second transistor, and the channel of at least one second transistor and the channel of the first transistor are located in different layers and at least partially opposite.

[0005] In some embodiments, the gating sub-circuit includes a plurality of gating branches, the gating branches are coupled to the third node, a fourth node and a first light emitting control signal terminal, and the fourth nodes and the first light emitting control signal terminals coupled to different gating branches are different. The fourth node is configured to be coupled to the light emitting device, and the light emitting devices coupled to different fourth nodes are different. The gating branch is configured to transmit the driving current signal of the third node to the fourth node in response to the light emitting control signal received at the first light emitting control signal terminal in one light emitting phase of one frame period.

[0006] In some embodiments, the gating branch includes the second transistor, a control electrode of the second transistor is coupled with the first light emitting control signal terminal, a first electrode is coupled with the third node, and a second electrode is coupled with the fourth node.

[0007] In some embodiments, the sub-stage includes a reset stage, the reset stage is located before the light emitting stage, and the pixel circuit further includes a reset sub-circuit, the reset sub-circuit is coupled with a reset signal terminal and an initialization signal terminal, and further coupled with the third node and / or the fourth node. The reset sub-circuit is configured to, in the reset stage, transmit an initialization signal received at the initialization signal terminal to the third node and / or the fourth node in response to a reset signal received at the reset signal terminal.

[0008] In some embodiments, the reset sub-circuit includes a third transistor, a control electrode of the third transistor is coupled with the reset signal terminal, a first electrode is coupled with the initialization signal terminal, and a second electrode is coupled with the third node. The channel of the third transistor is located in the same layer as the channel of the first transistor, and the channel of at least one of the second transistors is at least partially opposite to the channel of the third transistor.

[0009] In some embodiments, the gating sub-circuit includes two gating branches, each of the gating branches includes a second transistor. Among the two second transistors included in the two gating branches, the channel of one of the second transistors is at least partially opposite to the channel of the first transistor, and the channel of the other of the second transistors is at least partially opposite to the channel of the third transistor.

[0010] In some embodiments, the sub-stage further includes a data writing stage, the data writing stage is located before the light emitting stage, and the pixel circuit further includes a data writing sub-circuit, the data writing sub-circuit is coupled with a first scan signal terminal, a data signal terminal, and the first node. The data writing sub-circuit is configured to, in the data writing stage, transmit a data signal received at the data signal terminal to the first node in response to a first scan signal received at the first scan signal terminal.

[0011] In some embodiments, the sub-stage further includes a compensation stage, the compensation stage is located before the data writing stage. The driving sub-circuit is further configured to, in the compensation stage, transmit the voltage of the second node to the third node under the control of the voltages of the first node and the third node, until the voltage difference between the first node and the third node is equal to the threshold voltage of the first transistor included in the driving sub-circuit.

[0012] The pixel circuit further includes a first energy storage sub-circuit coupled to the first node and the third node. The first energy storage sub-circuit is configured to, in the light emitting stage, pull up or pull down the voltage of the first node according to the change of the voltage of the third node, so as to maintain the voltage difference between the first node and the third node unchanged.

[0013] In some embodiments, the data writing sub-circuit is further configured to, in the compensation stage, transmit the data signal received at the data signal terminal to the first node in response to the first scan signal received at the first scan signal terminal.

[0014] In some embodiments, the pixel circuit further includes a first voltage sub-circuit coupled to a second scan signal terminal, a first voltage signal terminal and the first node. The first voltage sub-circuit is configured to, in the compensation stage, transmit the first voltage signal received at the first voltage signal terminal to the first node in response to the second scan signal received at the second scan signal terminal.

[0015] In some embodiments, the data writing sub-circuit includes a fourth transistor, a control electrode of which is coupled to the first scan signal terminal, a first electrode of which is coupled to the data signal terminal, and a second electrode of which is coupled to the first node. The channel of the fourth transistor and the channel of the first transistor are located in the same layer.

[0016] In some embodiments, the pixel circuit includes a reset sub-circuit including a third transistor. In a first direction, the channel of the third transistor and the channel of the fourth transistor are located on opposite sides of the channel of the first transistor.

[0017] In some embodiments, the pixel circuit includes a first voltage sub-circuit including a fifth transistor, a control electrode of which is coupled to the second scan signal terminal, a first electrode of which is coupled to the first voltage signal terminal, and a second electrode of which is coupled to the first node. The channel of the fifth transistor and the channel of the fourth transistor are located in different layers and at least partially opposite.

[0018] In another aspect, a display panel is provided. One frame period includes a plurality of sub-periods performed in sequence, each of the sub-periods including a light emitting stage. The display panel includes a driving circuit layer and a light emitting device layer.

[0019] The driving circuit layer comprises a plurality of pixel circuits, each of which comprises a driving sub-circuit and a selection sub-circuit, and the driving sub-circuit is coupled with a first node, a second node and a third node. The first node is coupled to a data signal terminal, and the second node is coupled to a first power signal terminal. The selection sub-circuit is coupled with the third node. The driving sub-circuit comprises a first transistor, and the selection sub-circuit comprises a second transistor. The channel of at least one of the second transistors is located in a different layer from the channel of the first transistor, and at least partially opposite to the channel of the first transistor.

[0020] The light emitting device layer is arranged on one side of the driving circuit layer. The light emitting device layer comprises a plurality of light emitting devices, each of which is coupled with a selection sub-circuit, and at least two of the light emitting devices are coupled with the same selection sub-circuit. The selection sub-circuit is configured to transmit the driving current signal from the third node to different light emitting devices in different light emitting stages.

[0021] In some embodiments, the pixel circuit comprises a reset sub-circuit connected with a reset signal terminal and an initialization signal terminal, and coupled with the third node.

[0022] The display panel further comprises an initialization signal line coupled with the initialization signal terminal. The initialization signal line comprises a plurality of first sub-lines and a plurality of second sub-lines. The first sub-lines extend along a first direction, and the second sub-lines extend along a second direction. One of the first sub-lines is connected with the plurality of second sub-lines, and one of the second sub-lines is connected with the plurality of first sub-lines. The first direction and the second direction intersect.

[0023] The display panel further comprises a first power line coupled with the first power signal terminal. The first power line comprises a plurality of third sub-lines and a plurality of fourth sub-lines. The third sub-lines extend along the first direction, and the fourth sub-lines extend along the second direction. One of the third sub-lines is connected with the plurality of fourth sub-lines, and one of the fourth sub-lines is connected with the plurality of third sub-lines. Moreover, the third sub-lines are arranged staggered with the first sub-lines, and the fourth sub-lines are arranged staggered with the second sub-lines.

[0024] In some embodiments, the pixel circuit comprises a reset sub-circuit connected with a reset signal terminal and an initialization signal terminal, and coupled with the fourth node.

[0025] The display panel further comprises an initialization signal line coupled with the initialization signal terminal. The initialization signal line comprises a plurality of first sub-lines and a plurality of second sub-lines. The first sub-lines extend along a first direction, and the second sub-lines extend along a second direction. One of the first sub-lines is connected with the plurality of second sub-lines, and one of the second sub-lines is connected with the plurality of first sub-lines. The first direction and the second direction intersect.

[0026] The display panel further comprises a first power supply line coupled with a first power supply signal terminal. The first power supply line comprises a plurality of third sub-lines and a plurality of fourth sub-lines. The third sub-lines extend along the first direction, and the fourth sub-lines extend along the second direction. One of the third sub-lines is connected with the plurality of fourth sub-lines, and one of the fourth sub-lines is connected with the plurality of third sub-lines. The third sub-lines are arranged staggered with the first sub-lines, and the fourth sub-lines are arranged staggered with the second sub-lines.

[0027] In some embodiments, the display panel comprises 10 conductive layers, and the driving circuit layer comprises 8 conductive layers. Or, the display panel comprises 9 conductive layers, and the driving circuit layer comprises 7 conductive layers. Or, the display panel comprises 8 conductive layers, and the driving circuit layer comprises 6 conductive layers.

[0028] In some embodiments, the pixel circuit comprises a data writing sub-circuit coupled with a first scan signal terminal, a data signal terminal and a first node. The display panel comprises a first source-drain conductive layer comprising a data line coupled with the data signal terminal.

[0029] The driving circuit layer comprises a first semiconductor layer, a first gate conductive layer, a second gate conductive layer and a third gate conductive layer. The first semiconductor layer comprises a first channel portion and a first conductive portion. The first gate conductive layer is arranged on a side of the first semiconductor layer close to the light emitting device layer. The first gate conductive layer comprises a reset signal line and a first scan signal line extending along the second direction, and the reset signal line and the first scan signal line respectively overlap the first channel portion of the first semiconductor layer. The second gate conductive layer is arranged on a side of the first gate conductive layer close to the light emitting device layer. The second gate conductive layer comprises a second conductive block. The third gate conductive layer is arranged on a side of the second gate conductive layer close to the light emitting device layer.

[0030] In some embodiments, the first gate conductive layer further comprises a first conductive block overlapping the first channel portion of the first semiconductor layer, and the second conductive block at least partially opposes the first conductive block.

[0031] In some embodiments, the third gate conductive layer further comprises a third conductive block, and the third conductive block is at least partially opposite to the second conductive block.

[0032] In some embodiments, the display panel further comprises an initialization signal line and a first power supply line, and the initialization signal line comprises a first sub-line and a second sub-line, and the first power supply line comprises a third sub-line and a fourth sub-line. The first sub-line is located in the first source-drain conductive layer. The second sub-line is located in the second gate conductive layer, and the third sub-line and the fourth sub-line are located in the third gate conductive layer.

[0033] In some embodiments, the display panel further comprises an initialization signal line and a first power supply line, and the initialization signal line comprises a first sub-line and a second sub-line, and the first power supply line comprises a third sub-line and a fourth sub-line. The first sub-line and the third sub-line are located in the first source-drain conductive layer, and the second sub-line and the fourth sub-line are located in the second gate conductive layer.

[0034] In some embodiments, the reset signal lines and the first scan signal lines extend along the second direction, and two of the reset signal lines are located between two of the first scan signal lines.

[0035] In some embodiments, the second sub-line is located between two adjacent reset signal lines.

[0036] In some embodiments, the fourth sub-line is located between the reset signal line and the first scan signal line.

[0037] In some embodiments, the drive circuit layer comprises a first sub-drive layer, and the first sub-drive layer comprises a first transistor. The second sub-drive layer is disposed between the first sub-drive layer and the light emitting device layer. The second sub-drive layer comprises a second transistor, and a channel of at least one second transistor is at least partially opposite to a channel of the first transistor.

[0038] In some embodiments, the pixel circuit comprises a data writing sub-circuit, and the data writing sub-circuit is coupled to a first scan signal terminal, a data signal terminal, and a first node. The display panel further comprises a first source-drain conductive layer, and the first source-drain conductive layer is disposed between the first sub-drive layer and the second sub-drive layer. The first source-drain conductive layer comprises a data line, and the data line is coupled to the data signal terminal.

[0039] In some embodiments, the first sub-driving layer includes a second gate conductive layer including a second conductive block. The second sub-driving layer includes a fourth gate conductive layer and a second semiconductor layer. The fourth gate conductive layer includes a first transfer block connected with the second conductive block. The second semiconductor layer is disposed on a side of the fourth gate conductive layer away from the first sub-driving layer. The second semiconductor layer includes a second channel portion, a second conductive portion, and a first connecting column. The first connecting column is located between the second conductive portion and the first transfer block, and in electrical contact with the second conductive portion and the first transfer block.

[0040] In some embodiments, the first sub-driving layer includes a second gate conductive layer including a second conductive block. The second sub-driving layer includes a fourth gate conductive layer, a second semiconductor layer, and a second source-drain conductive layer. The fourth gate conductive layer includes a first transfer block connected with the second conductive block. The second semiconductor layer is disposed on a side of the fourth gate conductive layer away from the first sub-driving layer. The second semiconductor layer includes a second channel portion and a second conductive portion.

[0041] The second source-drain conductive layer is disposed on a side of the second semiconductor layer away from the first sub-driving layer. The second source-drain conductive layer includes a third transfer block and a second connecting column. A portion of the second connecting column is staggered with the second channel portion and the second conductive portion, and is located between the third transfer block and the first transfer block, in electrical contact with the third transfer block and the first transfer block. Another portion is located between the third transfer block and the second conductive portion, and in electrical contact with the third transfer block and the second conductive portion.

[0042] In some embodiments, the first sub-driving layer includes a second gate conductive layer including a second conductive block. The second sub-driving layer includes a fourth gate conductive layer, a second semiconductor layer, and a second source-drain conductive layer. The fourth gate conductive layer includes a first transfer block connected with the second conductive block. The second semiconductor layer is disposed on a side of the fourth gate conductive layer away from the first sub-driving layer. The second semiconductor layer includes a second channel portion and a second conductive portion.

[0043] The second source-drain conductive layer is disposed on a side of the second semiconductor layer away from the first sub-driving layer. The second source-drain conductive layer includes a fourth transfer block, a third connecting column, and a fourth connecting column, and the third connecting column and the fourth connecting column are disposed in a spaced manner. The third connecting column is staggered with the second channel part and the second conductive part, and is located between the fourth transfer block and the first transfer block and in electrical contact with the fourth transfer block and the first transfer block. The fourth connecting column is located between the fourth transfer block and the second conductive part and in electrical contact with the fourth transfer block and the second conductive part.

[0044] In some embodiments, the second sub-driving layer further includes a fifth gate conductive layer disposed on a side of the fourth gate conductive layer away from the first sub-driving layer, and the second semiconductor layer is disposed on a side of the fifth gate conductive layer away from the first sub-driving layer. The fifth gate conductive layer includes a second scan signal line and a first light-emitting control signal line, and the second scan signal line and the first light-emitting control signal line extend along the second direction and overlap the second channel part of the second semiconductor layer, respectively.

[0045] In some embodiments, the second sub-driving layer further includes a sixth gate conductive layer disposed on a side of the second semiconductor layer away from the first sub-driving layer. The sixth gate conductive layer includes a second scan signal line and a first light-emitting control signal line, and the second scan signal line and the first light-emitting control signal line extend along the second direction and overlap the second channel part of the second semiconductor layer, respectively.

[0046] In some embodiments, at least 4 first light-emitting control signal lines are located between two second scan signal lines.

[0047] In some embodiments, the display panel includes a reset signal line and a first scan signal line, and the reset signal line and the first scan signal line extend along the second direction. The second scan signal line at least partially overlaps the first scan signal line. The reset signal line is located between two first light-emitting control signal lines connected to and adjacent to first light-emitting control signal ends belonging to different pixel circuits.

[0048] In some embodiments, the display panel further includes a first power supply line, and the first power supply line includes a third sub-line and a fourth sub-line, and the fourth sub-line is located between adjacent first light-emitting control signal lines and second scan signal lines.

[0049] In some embodiments, the first sub-driving layer includes a first semiconductor layer, and a material of the first semiconductor layer includes an oxide or low-temperature polysilicon. The second sub-driving layer includes a second semiconductor layer, and a material of the second semiconductor layer includes an oxide or low-temperature polysilicon.

[0050] In some embodiments, the materials of the first semiconductor layer and the second semiconductor layer include an oxide.

[0051] In some embodiments, a difference between a number of transistors included in the first sub-driving layer and a number of transistors included in the second sub-driving layer is 0 or 1.

[0052] In some embodiments, the driving circuit layer includes a plurality of pixel circuits, and the plurality of pixel circuits are arranged in a plurality of rows and a plurality of columns. Each column includes at least two pixel circuits arranged in a first direction, and each row includes at least two pixel circuits arranged in a second direction. The first direction and the second direction intersect. In the first direction and / or the second direction, any two adjacent pixel circuits are symmetrically arranged.

[0053] In some embodiments, the plurality of light emitting devices are arranged in a plurality of rows and a plurality of columns. Each column includes at least two light emitting devices arranged in a first direction, and each row includes at least two light emitting devices arranged in a second direction. The first direction and the second direction intersect. The plurality of light emitting devices connected to the same gate sub-circuit are located in the same column.

[0054] In some embodiments, the gate sub-circuit includes a plurality of gate branches. The gate branches are connected to the third node, the fourth node, and the first light emitting control signal terminal. The fourth node is connected to the light emitting device. The fourth nodes connected to different gate branches are connected to different light emitting devices.

[0055] The display panel further includes a first gate driving circuit and a first light emitting control signal line. The first light emitting control signal line is connected to the first gate driving circuit. In the first direction, the plurality of first light emitting control signal lines are divided into a plurality of first light emitting control signal line groups. Each first light emitting control signal line group includes at least two first light emitting control signal lines arranged adjacent to each other. The first light emitting control signal terminals of the plurality of gate branches in a row of pixel circuits are respectively connected to the plurality of first light emitting control signal lines in one first light emitting control signal line group.

[0056] The first light-emitting control signal lines in the first light-emitting control signal line group are connected with the first gate drive circuit respectively. The number of the first light-emitting control signal lines between any two adjacent first light-emitting control signal lines in the same first light-emitting control signal line group connected with the same first gate drive circuit is the same along the first direction.

[0057] In some embodiments, the plurality of columns of light-emitting devices comprises a first column of light-emitting devices and a second column of light-emitting devices. The light-emitting devices in the first column of light-emitting devices have different light-emitting colors. The light-emitting devices in the second column of light-emitting devices have the same light-emitting color.

[0058] In some embodiments, the first column of light-emitting devices comprises a plurality of red light-emitting devices and a plurality of blue light-emitting devices, and the plurality of red light-emitting devices and the plurality of blue light-emitting devices are arranged alternately. The second column of light-emitting devices comprises a plurality of green light-emitting devices.

[0059] Alternatively, the first column of light-emitting devices comprises a plurality of red light-emitting devices and a plurality of green light-emitting devices, and the plurality of red light-emitting devices and the plurality of green light-emitting devices are arranged alternately. The second column of light-emitting devices comprises a plurality of blue light-emitting devices.

[0060] In some embodiments, the display panel further comprises a pixel definition layer provided with a plurality of pixel openings, and one light-emitting device is located in one pixel opening. The shape of the pixel opening is substantially quadrilateral or elliptical.

[0061] In some embodiments, the light-emitting device comprises a first electrode, a light-emitting part and a second electrode, the first electrode and the second electrode are located on opposite sides of the light-emitting part, and the first electrode is located on the side of the light-emitting part close to the drive circuit layer. The first electrode comprises a main body part and a lap joint part, the pixel opening exposes at least part of the main body part, and the lap joint part is connected with the second electrode of the second transistor through a connection hole.

[0062] In some embodiments, the two adjacent columns of light-emitting devices are a first column of light-emitting devices and a second column of light-emitting devices. In the first column of light-emitting devices, along the first direction, the lap joint part is located on the first side of the main body part. In the second column of light-emitting devices, along the first direction, the lap joint part is located on the second side of the main body part. The first side and the second side are opposite sides of the main body part.

[0063] In some embodiments, the ratio of the area of the main body part to the area of the pixel opening is 0.7-0.9.

[0064] In some embodiments, the ratio of the size of the connection hole to the size of the pixel opening is 0.5-0.9 in any direction parallel to the pixel defining layer.

[0065] In some embodiments, the display panel includes a plurality of gate lines, the plurality of gate lines including at least one of a first light emitting control signal line, a first scan signal line, a second scan signal line, and a reset signal line, and a ratio of the size of the gate line to the size of the pixel opening is 0.5-1.2 in a direction perpendicular to the extension direction of the gate line.

[0066] In another aspect, a display panel is provided. The display panel includes a driving circuit layer, a light emitting device layer, and a pixel defining layer.

[0067] The driving circuit layer includes a plurality of pixel circuits, the pixel circuit including a common sub-circuit coupled to a data signal terminal, a first power signal terminal, and a third node. The common sub-circuit is configured to generate a driving current signal and transmit the driving current signal to the third node during the light emitting phase.

[0068] The light emitting device layer is disposed on a side of the driving circuit layer. The light emitting device layer includes a plurality of light emitting devices coupled to the common sub-circuit, and at least two of the light emitting devices are coupled to the same common sub-circuit. The light emitting device includes a first electrode including a main body portion and an overlapping portion, and the overlapping portion is connected to the pixel circuit through a connection hole.

[0069] The pixel defining layer is disposed on a side of the driving circuit layer. The pixel defining layer is provided with a plurality of pixel openings, one of the light emitting devices is located in one of the pixel openings, and the pixel opening exposes at least part of the main body portion. In a first direction, the connection hole and the pixel opening are at least partially opposite.

[0070] In some embodiments, the common sub-circuit includes a driving sub-circuit coupled to a first node, a second node, and the third node, the first node is coupled to the data signal terminal, and the second node is coupled to the first power signal terminal. The driving sub-circuit is configured to generate a driving current signal according to the voltage of the first node and the third node and transmit the driving current signal to the third node during the light emitting phase.

[0071] In some embodiments, the common sub-circuit further includes a reset sub-circuit coupled to the third node, a reset signal terminal, and an initialization signal terminal. The reset sub-circuit is configured to transmit an initialization signal received at the initialization signal terminal to the third node in response to a reset signal received at the reset signal terminal during the reset phase.

[0072] In some embodiments, the common sub-circuit further comprises a data write sub-circuit coupled with the first scan signal terminal, the data signal terminal and the first node. The data write sub-circuit is configured to, in the data write phase, transmit a data signal received at the data signal terminal to the first node in response to a first scan signal received at the first scan signal terminal.

[0073] In some embodiments, the common sub-circuit further comprises a first energy storage sub-circuit coupled with the first node and the third node. The first energy storage sub-circuit is configured to, in the light emitting phase, pull up or pull down the voltage of the first node according to the change of the voltage of the third node, so as to maintain the voltage difference between the first node and the third node unchanged.

[0074] In some embodiments, the common sub-circuit further comprises a first voltage sub-circuit coupled with a second scan signal terminal, a first voltage signal terminal and the first node. The first voltage sub-circuit is configured to, in the compensation phase, transmit a first voltage signal received at the first voltage signal terminal to the first node in response to a second scan signal received at the second scan signal terminal.

[0075] In another aspect, a display device is provided. The display device is any one of a wearable device, a virtual reality device and an augmented reality device, and the display device comprises the display panel and the circuit board as described in any one of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0076] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual flow, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0077] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0078] FIG. 2 is a structural diagram of another display device according to some embodiments;

[0079] FIG. 3 is a sectional view along the section line A-A in FIG. 1;

[0080] FIG. 4 is a structural diagram of a display panel according to some embodiments;

[0081] FIG. 5 is a cross-sectional view of a display panel, according to some embodiments;

[0082] FIG. 6 is a structural block diagram of a pixel circuit, according to some embodiments;

[0083] FIG. 7 is a circuit diagram of a pixel circuit, according to some embodiments;

[0084] FIG. 8 is a timing diagram of the pixel circuit shown in FIG. 7;

[0085] FIG. 9 is a circuit diagram of another pixel circuit, according to some embodiments;

[0086] FIG. 10 is a timing diagram of the pixel circuit shown in FIG. 9;

[0087] FIG. 11 is a circuit diagram of still another pixel circuit, according to some embodiments;

[0088] FIG. 12 is a circuit diagram of yet another pixel circuit, according to some embodiments;

[0089] FIG. 13A is a timing diagram of the pixel circuit shown in FIG. 11;

[0090] FIG. 13B is a timing diagram of another pixel circuit shown in FIG. 11;

[0091] FIG. 14 is a timing diagram of the pixel circuit shown in FIG. 12;

[0092] FIG. 15A is a circuit diagram of yet another pixel circuit, according to some embodiments;

[0093] FIG. 15B is a current flow diagram of the pixel circuit shown in FIG. 15A;

[0094] FIG. 16 is a timing diagram of the pixel circuit shown in FIG. 15B;

[0095] FIG. 17 is a circuit diagram of yet another pixel circuit, according to some embodiments;

[0096] FIG. 18 is a circuit diagram of yet another pixel circuit, according to some embodiments;

[0097] FIG. 19 is a timing diagram of the pixel circuit shown in FIG. 18;

[0098] FIG. 20 is a top view of a drive circuit layer of a display panel, according to some embodiments;

[0099] FIG. 21 is a structural diagram of a first semiconductor layer of a display panel, according to some embodiments;

[0100] FIG. 22 is a structural diagram of a first gate conductive layer of a display panel, according to some embodiments;

[0101] FIG. 23 is a structure diagram of a second gate conductive layer of a display panel according to some embodiments;

[0102] FIG. 24 is a structure diagram of a first semiconductor layer, a first gate conductive layer, and a second gate conductive layer stack of a display panel according to some embodiments;

[0103] FIG. 25 is a structure diagram of a third gate conductive layer of a display panel according to some embodiments;

[0104] FIG. 26 is a structure diagram of a first source-drain conductive layer of a display panel according to some embodiments;

[0105] FIG. 27 is a structure diagram of a second gate conductive layer, a third gate conductive layer, and a first source-drain conductive layer stack of a display panel according to some embodiments;

[0106] FIG. 28 is a structure diagram of a first gate conductive layer of another display panel according to some embodiments;

[0107] FIG. 29 is a structure diagram of a second gate conductive layer of another display panel according to some embodiments;

[0108] FIG. 30 is a structure diagram of a third gate conductive layer of another display panel according to some embodiments;

[0109] FIG. 31 is a structure diagram of a first source-drain conductive layer of another display panel according to some embodiments;

[0110] FIG. 32 is a structure diagram of a first semiconductor layer, a first gate conductive layer, and a second gate conductive layer stack of another display panel according to some embodiments;

[0111] FIG. 33 is a structure diagram of a second gate conductive layer, a third gate conductive layer, and a first source-drain conductive layer stack of another display panel according to some embodiments;

[0112] FIG. 34 is a structure diagram of a fourth gate conductive layer of a display panel according to some embodiments;

[0113] FIG. 35 is a structure diagram of a first semiconductor layer, a first gate conductive layer, a second gate conductive layer, and a fourth gate conductive layer stack of a display panel according to some embodiments;

[0114] FIG. 36 is a cross-sectional view of a first sub-drive layer, a first source-drain conductive layer, and a fourth gate conductive layer stack of a display panel according to some embodiments;

[0115] FIG. 37 is a cross-sectional view of a first sub-drive layer, a first source-drain conductive layer, and a fourth gate conductive layer stack of another display panel according to some embodiments;

[0116] FIG. 38A is a structural diagram of a fifth gate conductive layer of a display panel according to some embodiments;

[0117] FIG. 38B is a structural diagram of a plurality of gate lines of a display panel according to some embodiments;

[0118] FIG. 39 is a structural diagram of a second semiconductor layer of a display panel according to some embodiments;

[0119] FIG. 40 is a structural diagram of a sixth gate conductive layer of a display panel according to some embodiments;

[0120] FIG. 41 is a structural diagram of a second source-drain conductive layer of a display panel according to some embodiments;

[0121] FIG. 42A is a structural diagram of a first electrode layer and a light-emitting functional layer stack of a display panel according to some embodiments;

[0122] FIG. 42B is a structural diagram of a first electrode of a display panel according to some embodiments;

[0123] FIG. 42C is a structural diagram of another first electrode of a display panel according to some embodiments;

[0124] FIG. 43 is a structural diagram of a second sub-driving layer of a display panel according to some embodiments;

[0125] FIG. 44 is a cross-sectional view of a second sub-driving layer of a display panel according to some embodiments;

[0126] FIG. 45 is a cross-sectional view of another second sub-driving layer of a display panel according to some embodiments;

[0127] FIG. 46 is a cross-sectional view of yet another second sub-driving layer of a display panel according to some embodiments;

[0128] FIG. 47 is a structural diagram of another display panel according to some embodiments;

[0129] FIG. 48 is a structural diagram of yet another display panel according to some embodiments. DETAILED DESCRIPTION

[0130] The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0131] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise," and variations thereof (e.g., "comprises" and "comprising"), will be construed to be inclusive in a manner consistent with the term's plain meaning, namely, "including but not limited to." In describing the description, the terms "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," are not necessarily referring to the same embodiment or example. Furthermore, the above terms are not necessarily mutually exclusive. Throughout the description and claims, the meaning of "a," "an," and "the" includes singular and plural referents unless the context clearly dictates otherwise.

[0132] Hereinafter, the terms "first" and "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0133] In describing some embodiments, "coupled" and "connected," and variations thereof, can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "coupling" can also refer to two or more components that do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0134] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C," and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0135] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0136] As used herein, the term "if' is, optionally, interpreted as meaning "when" or "while" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [stated condition or event] is detected," is, optionally, interpreted as meaning "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0137] Use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0138] Additionally, use of "based on" means open and inclusive, as a process, step, calculation, or other action "based on" one or more stated conditions or values can in practice be based on additional conditions or values beyond those stated.

[0139] "About," "approximately," or "substantially" as used herein includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art to be within the scope of what is claimed while considering the measurement in question and the error associated with that measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0140] "Parallel," "perpendicular," "equal" as used herein include the stated condition as well as conditions that approximate the stated condition within an acceptable range of deviation, where the acceptable range of deviation is as determined by one of ordinary skill in the art considering the measurement in question and the error associated with that measurement (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where the acceptable range of deviation for near parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where the acceptable range of deviation for near perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and near equality, where the acceptable range of deviation for near equality can be, for example, a difference between the two that is less than or equal to 5% of either.

[0141] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0142] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

[0143] In this specification, unless defined otherwise, all terms used herein including technical terms and scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure pertains. It will be further understood that terms, e.g., terms defined in a generally used dictionary, should not be interpreted as having ideal or excessively formal meanings.

[0144] In the present disclosure, terms such as "lower", "below", "upper" and "above" are used to explain the relative positional relationship of components shown in the drawings. The terms can be relative concepts and described based on the direction indicated in the drawings, or based on the order of process steps formed, but are not limited thereto.

[0145] The term "opposite" means that a first element can be directly or indirectly opposite to a second element. In the case where a third element is interposed between the first element and the second element, although still opposite to each other, the first element and the second element can be understood as indirectly opposite to each other.

[0146] In the embodiments of the present disclosure, the transistor employed can be a thin film transistor (TFT), a metal oxide semiconductor (MOS), or other switching devices with the same characteristics, and the embodiments of the present disclosure are described taking the thin film transistor as an example.

[0147] In embodiments of the present disclosure, the control electrode of each thin film transistor is the gate electrode of the transistor, the first electrode is one of the source electrode and the drain electrode of the thin film transistor, and the second electrode is the other of the source electrode and the drain electrode of the thin film transistor. Since the source electrode and the drain electrode of the thin film transistor can be symmetrical in structure, the source electrode and the drain electrode of the thin film transistor can be indistinguishable in structure, that is, the first electrode and the second electrode of the thin film transistor in embodiments of the present disclosure can be indistinguishable in structure. For example, when the transistor is a P-type transistor, the first electrode of the transistor is the source electrode, and the second electrode of the transistor is the drain electrode; for example, when the transistor is an N-type transistor, the first electrode of the transistor is the drain electrode, and the second electrode of the transistor is the source electrode.

[0148] In embodiments of the present disclosure, the capacitor can be a capacitor device separately manufactured by a process, for example, a capacitor device realized by manufacturing a special capacitor electrode, and each capacitor electrode of the capacitor can be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), or the like. The capacitor can also be a parasitic capacitor between transistors, or realized by a transistor itself and other devices, lines, or the like, or realized by using a parasitic capacitor between lines of a circuit itself.

[0149] In embodiments of the present disclosure, the nodes such as the first node, the second node, and the third node do not represent actual components, but represent the convergence points of relevant electrical connections in a circuit diagram, that is, these nodes are nodes equivalent to the convergence points of relevant electrical connections in a circuit diagram.

[0150] In addition, in the circuit provided by embodiments of the present disclosure, the transistors are all taken as N-type transistors for illustration. It should be noted that embodiments of the present disclosure include but are not limited to this. For example, one or more transistors in the circuit provided by embodiments of the present disclosure can also adopt P-type transistors, as long as each electrode of the selected type of transistor is connected according to the corresponding electrode of the corresponding transistor in embodiments of the present disclosure, and the corresponding voltage terminal provides the corresponding high voltage or low voltage.

[0151] In the pixel circuit provided in embodiments of the present disclosure, the "working voltage" refers to a voltage capable of turning on the operated transistor included in the pixel circuit, and correspondingly, the "non-working voltage" (or "non-activation voltage") refers to a voltage incapable of turning on the operated transistor included in the pixel circuit (that is, the transistor is cut off). According to factors such as the type (N-type or P-type) of the transistor in the circuit structure of the pixel circuit, the working voltage can be higher or lower than the non-working voltage.

[0152] As shown in FIGS. 1 and 2, some embodiments of the present disclosure provide a display device 1000, which can be any device displaying images whether in motion (e.g., video) or stationary (e.g., still images), and whether textual or pictorial.

[0153] Exemplarily, the display device 1000 can be any product or component having a display function, such as a television, a notebook computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a mixed reality (MR) device, an extended reality (XR) device, a sight device, a range finder, etc.

[0154] For example, as shown in FIG. 1, the display device 1000 can be a portable display product; for example, the display device 1000 can be a mobile phone as shown in FIG. 1. For another example, referring to FIG. 2, the display device 1000 can be a VR device as shown in FIG. 2.

[0155] It should be noted that according to different application scenarios, the display device 1000 can be a flat display device, a curved display device, a folding display device, etc., and the shape of the display surface of the display device 1000 can be any one of a circle, an ellipse, a polygon, or an irregular figure, which is not specifically limited in the embodiments of the present disclosure.

[0156] In the following, some embodiments of the present disclosure will be schematically described by taking the display device 1000 as the mobile phone shown in FIG. 1 as an example, but the embodiments of the present disclosure are not limited thereto, and any other display device can also be considered as long as the same technical idea is applied.

[0157] In some embodiments, referring to FIG. 3, the display device 1000 includes a display panel 100, which can include a display side and a non-display side arranged oppositely, for example. The display side is a side of the display panel 100 used for display, i.e., the upper side in FIG. 3.

[0158] The type of the display panel 100 described above includes a variety of types, which can be selected and arranged according to actual needs. Exemplarily, the display panel 100 described above can be an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diode (Micro LED) display panel, etc., which is not specifically limited in the embodiments of the present disclosure.

[0159] The following describes some embodiments of the present disclosure by taking the OLED display panel 100 as an example, but the embodiments of the present disclosure are not limited thereto, and any other display panel can also be considered as long as the same technical idea is applied.

[0160] In some embodiments, referring to FIG. 3, the display device 1000 can further include a housing 200, a cover plate 300, and a circuit board 400 and other electronic accessories. The display panel 100 and the circuit board 400 can be disposed in the housing 200.

[0161] For example, as shown in FIG. 3, the housing 200 can be a box-shaped structure with an opening, the cover plate 300 is disposed on one side of the display panel 100 and at the opening of the housing 200. The display panel 100 and the circuit board 400 can be disposed in the housing 200, and the circuit board 400 can be bound to the display panel 100 at the end of the display panel 100 and bent to the back side of the display panel 100 to reduce the frame of the display panel 100 and improve the screen-to-body ratio.

[0162] In some embodiments, referring to FIG. 4, the display panel 100 includes a display area A and a peripheral area B located on at least one side of the display area A. For example, the peripheral area B surrounds the display area A, and FIG. 4 illustrates the peripheral area B surrounding the display area A as an example.

[0163] As shown in FIG. 5, the display panel 100 includes a substrate 10, a driving circuit layer 110 disposed on the substrate 10, and a light emitting device layer 120 disposed on the driving circuit layer 110 away from the substrate 10.

[0164] As shown in FIG. 4 and FIG. 5, the substrate 10 can be a rigid substrate or a flexible substrate. The material of the rigid substrate can include glass and / or Polymethyl Methacrylate (PMMA). The material of the flexible substrate can include at least one of Polyethylene Terephthalate (PET), Polyethylene Naphthalate Two Formic Acid Glycol Ester (PEN), and Polyimide (PI).

[0165] As shown in FIG. 4 and FIG. 5, the driving circuit layer 110 includes the pixel circuit 20 disposed in the display area A, the pixel circuit 20 including a plurality of transistors T, the transistor T including a channel 201, a first electrode 211, a second electrode 212, and a control electrode 213, the first electrode 211 and the second electrode 212 both being in contact with the channel 201. One of the first electrode 211 and the second electrode 212 is a source electrode, and the other is a drain electrode, which are not specifically limited in the embodiments of the present disclosure.

[0166] As shown in FIG. 4 and FIG. 5, the light emitting device layer 120 includes the light emitting device 30 disposed in the display area A, the light emitting device 30 including a first electrode 31, a light emitting part 32, and a second electrode 33, the first electrode 31 being coupled with the first electrode 211 or the second electrode 212 of one of the transistors T, and the second electrode 33 being coupled with a second power signal terminal VSS (see FIG. 6). In FIG. 5, the first electrode 31 and the second electrode 212 of the transistor T are coupled as an example. It should be noted that the second power signal received by the second power signal terminal VSS (see FIG. 6) can be a signal of the negative electrode of a direct current power supply.

[0167] In the related art, one pixel circuit is connected with one light emitting device to form one sub-pixel. In this case, since the area occupied by the pixel circuit on the display panel is much larger than the area occupied by the light emitting device on the display panel, the number of sub-pixels arranged in the unit area of the display panel cannot be further increased due to the size limitation of the pixel circuit, resulting in that the display panel cannot realize higher pixel density (Pixels Per Inch, referred to as PPI), and cannot meet the growing resolution demand of users.

[0168] Based on this, referring to FIG. 6 and FIG. 7, some embodiments of the present disclosure provide a pixel circuit 20 including a shared sub-circuit 270, the shared sub-circuit 270 being coupled with a data signal terminal DATA, a first power signal terminal VDD, and a third node N3. The shared sub-circuit 270 is configured to generate a driving current signal in a light emitting phase P10, and transmit the driving current signal to the third node N3.

[0169] Among them, at least two light emitting devices 30 are coupled with the same shared sub-circuit 270, and the plurality of light emitting devices 30 emit light in different time in one frame period F (see FIG. 8).

[0170] As shown in FIG. 7 and FIG. 8, one frame period F refers to the time period during which the display panel 100 displays an image, and one frame period F can include a plurality of sub-periods P, and the sub-period P includes a light emitting phase P10, and the plurality of light emitting devices 30 coupled with the pixel circuit 20 emit light in the light emitting phase P10 of the plurality of sub-periods P, respectively.

[0171] In some examples, the common sub-circuit 270 includes the driving sub-circuit 210 configured to provide the driving current signal, and the pixel circuit 20 further includes the gating sub-circuit 220 coupled with the plurality of light emitting devices 30 to drive the plurality of light emitting devices 30 to emit light in the light emitting phase P10 of the plurality of sub-phases P of the frame period F (see FIG. 8) in time.

[0172] As shown in FIGS. 6 and 7, the driving sub-circuit 210 can be coupled with the first node N1, the second node N2, and the third node N3. The first node N1 is coupled to the data signal terminal DATA, and the second node N2 is coupled to the first power signal terminal VDD. As shown in FIGS. 7 and 8, the driving sub-circuit 210 is configured to generate the driving current signal according to the voltages of the first node N1 and the third node N3 and transmit the driving current signal to the third node N3 in the light emitting phase P10. It should be noted that the first power signal received by the first power signal terminal VDD can be a signal of the positive electrode of a direct current power supply.

[0173] As shown in FIG. 7, the driving sub-circuit 210 includes the first transistor T1, the control electrode of which is coupled with the first node N1, the first electrode of which is coupled with the second node N2, and the second electrode of which is coupled with the third node N3. As shown in FIGS. 7 and 8, in the light emitting phase P10, the first transistor T1 is turned on, and the driving current signal is generated according to the voltages of the first node N1 and the third node N3 and transmitted to the third node N3.

[0174] As shown in FIGS. 6 and 7, the gating sub-circuit 220 can be coupled with the third node N3. The gating sub-circuit 220 is configured to be coupled with the plurality of light emitting devices 30. As shown in FIGS. 7 and 8, the gating sub-circuit 220 is configured to transmit the driving current signal from the third node N3 to different light emitting devices 30 in different light emitting phases P10, so that the plurality of light emitting devices 30 emit light in the light emitting phase P10 of the plurality of sub-phases P of the frame period F respectively.

[0175] In this case, the plurality of light emitting devices 30 are coupled with the same pixel circuit 20 to form a plurality of sub-pixels. The plurality of sub-pixels can share at least one driving sub-circuit 210 to generate the driving current signal. That is, the plurality of sub-pixels share one driving sub-circuit 210, which can save the number of driving sub-circuits 210 and compress the area occupied by the pixel circuit 20 of the plurality of sub-pixels, so that more sub-pixels can be arranged in the unit area of the display panel 100 to improve the pixel density and resolution of the display panel 100 and meet the user's demand for increasing resolution.

[0176] On this basis, referring to FIGS. 5, 7 and 20, the gating sub-circuit 220 includes a second transistor T2, and the channel 201 (see FIG. 39) of at least one second transistor T2 in the gating sub-circuit 220 is located at a different layer from and at least partially opposite to the channel 201 (see FIG. 21) of the first transistor T1. That is, the orthogonal projection of the channel 201 of at least one second transistor T2 on the substrate 10 at least partially overlaps the orthogonal projection of the channel 201 of the first transistor T1 on the substrate 10.

[0177] In this document, the term "opposite" means that a first element can be directly or indirectly opposite to a second element. In the case that a third element is interposed between the first element and the second element, although still opposite to each other, the first element and the second element can be understood as indirectly opposite to each other.

[0178] In this case, at least one second transistor T2 in the gating sub-circuit 220 is arranged on the side of the first transistor T1 close to or away from the substrate 10, and the second transistor T2 and the first transistor T1 can overlap, so that the total area occupied by the first transistor T1 and the second transistor T2 can be reduced, thereby facilitating further reduction of the area occupied by the pixel circuit 20, so that more sub-pixels can be arranged in a unit area of the display panel 100, to further improve the pixel density and resolution of the display panel 100, to meet the user's demand for increasing resolution.

[0179] Exemplarily, as shown in FIG. 7, the gating sub-circuit 220 includes a plurality of gating branches 221, and the gating branches 221 are coupled with the third node N3, the fourth node N4 and the first light-emitting control signal end EM1. Different gating branches 221 are coupled with different fourth nodes N4 and different first light-emitting control signal ends EM1. The fourth node N4 is configured to be coupled with the light-emitting device 30, and different fourth nodes N4 are coupled with different light-emitting devices 30. That is, the plurality of gating branches 221 are coupled with different light-emitting devices 30.

[0180] As shown in FIGS. 7 and 8, the gating branch 221 is configured to, in a light-emitting stage P10 of a frame period F, transmit the driving current signal of the third node N3 to the fourth node N4 in response to the light-emitting control signal received at the first light-emitting control signal end EM1. That is, each gating branch 221 is controlled by a first light-emitting control signal end EM1 to be turned on in the light-emitting stage P10 of each sub-period P of a frame period F, so that the plurality of light-emitting devices 30 coupled with the gating sub-circuit 220 emit light in the light-emitting stage P10 of each sub-period P of a frame period F, respectively.

[0181] For example, as shown in FIG. 7, the gating branch 221 can include a second transistor T2, a control electrode of the second transistor T2 being coupled with the first light-emitting control signal terminal EM1, a first electrode being coupled with the third node N3, and a second electrode being coupled with the fourth node N4, which is simple in circuit structure and convenient for preparation.

[0182] In some examples, as shown in FIGS. 7 and 8, the gating sub-circuit 220 includes two gating branches 221, the two gating branches 221 being respectively coupled with two first light-emitting control signal terminals EM1, the two first light-emitting control signal terminals EM1 being respectively a first sub-light-emitting control signal terminal EM1-1 and a second sub-light-emitting control signal terminal EM1-2.

[0183] At this time, the two gating branches 221 are controlled by the first sub-light-emitting control signal terminal EM1-1 and the second sub-light-emitting control signal terminal EM1-2 respectively to be turned on in the light-emitting stage P10 of the plurality of sub-frames P of the frame period F respectively, so that the two light-emitting devices 30 emit light in the light-emitting stage P10 of the plurality of sub-frames P of the frame period F respectively.

[0184] In other examples, as shown in FIGS. 9 and 10, the gating sub-circuit 220 includes three gating branches 221, the three gating branches 221 being respectively coupled with three first light-emitting control signal terminals EM1, the three first light-emitting control signal terminals EM1 being respectively a first sub-light-emitting control signal terminal EM1-1, a second sub-light-emitting control signal terminal EM1-2 and a third sub-light-emitting control signal terminal EM1-3.

[0185] At this time, the three gating branches 221 are controlled by the first sub-light-emitting control signal terminal EM1-1, the second sub-light-emitting control signal terminal EM1-2 and the third sub-light-emitting control signal terminal EM1-3 respectively to be turned on in the light-emitting stage P10 of the plurality of sub-frames P of the frame period F respectively, so that the three light-emitting devices 30 emit light in the light-emitting stage P10 of the plurality of sub-frames P of the frame period F respectively.

[0186] In the following, some embodiments of the present disclosure will be described illustratively taking an example that the gating sub-circuit 220 includes two gating branches 221, but the embodiments of the present disclosure are not limited thereto, and more gating branches 221 can also be considered as long as the same technical idea is applied.

[0187] In some embodiments, referring to FIG. 8, the sub-frame P further includes a reset stage P20, the reset stage P20 being located before the light-emitting stage P10.

[0188] At this time, as shown in FIGS. 6 and 11, the common sub-circuit 270 can further include a reset sub-circuit 230, the reset sub-circuit 230 being coupled with the reset signal terminal RESET and the initialization signal terminal VINIT, and further being coupled with the third node N3.

[0189] Referring to FIGS. 11 and 13A, the reset sub-circuit 230 is configured to, in the reset phase P20, transmit the initialization signal received at the initialization signal terminal VINIT to the third node N3 in response to the reset signal received at the reset signal terminal RESET, so as to reset the voltage of the third node N3 and eliminate the influence of the voltage of the previous frame period F, thereby improving the display effect.

[0190] For example, as shown in FIGS. 11 and 13A, the reset sub-circuit 230 is coupled with the reset signal terminal RESET, the initialization signal terminal VINIT and the third node N3. For example, the reset sub-circuit 230 includes a third transistor T3, the control electrode of which is coupled with the reset signal terminal RESET, the first electrode of which is coupled with the initialization signal terminal VINIT, and the second electrode of which is coupled with the third node N3. The circuit structure is simple and facilitates manufacturing.

[0191] In this case, the light emitting devices 30 of the plurality of sub-pixels can at least share one reset sub-circuit 230 to reset the third node N3. That is, the plurality of sub-pixels share one reset sub-circuit 230, which can save the number of reset sub-circuits 230 and compress the area occupied by the pixel circuit 20 of the plurality of sub-pixels, so that more sub-pixels can be arranged in the unit area of the display panel 100, thereby improving the pixel density and resolution of the display panel 100 and meeting the demand of users for increasing resolution.

[0192] On this basis, referring to FIGS. 5, 11 and 13A, the gate sub-circuit 220 can also be configured to, in the reset phase P20, transmit the initialization signal from the third node N3 to the fourth node N4 to reset the first electrode 31 of the light emitting device 30.

[0193] For example, as shown in FIGS. 5, 11 and 13A, the gate sub-circuit 220 includes two gate branches 221, which can be turned on in the reset phase P20 of the plurality of sub-periods P of one frame period F, respectively, so that the first electrodes 31 of the two light emitting devices 30 are reset in the plurality of reset phases P20 of one frame period F, respectively. In this way, the interval between the reset phase P20 and the light emitting phase P10 of each light emitting device 30 is short, which is conducive to improving the uniformity of the brightness of the light emitting device 30.

[0194] Exemplarily, as shown in FIG. 5, FIG. 11 and FIG. 13B, the gate sub-circuit 220 includes two gate branches 221, which can be turned on at the same reset stage P20 of the frame period F, so as to reset the first electrodes 31 of the two light emitting devices 30 at the same reset stage P20 of the frame period F. In this way, the light emitting devices 30 are reset at the same reset stage P20, which is conducive to simplifying the circuit design.

[0195] In yet some embodiments, as shown in FIG. 12, the pixel circuit 20 can further include a reset sub-circuit 230, which is coupled with the reset signal terminal RESET and the initialization signal terminal VINIT, and further coupled with the fourth node N4.

[0196] Referring to FIG. 12 and FIG. 14, the reset sub-circuit 230 is configured to, at the reset stage P20, transmit the initialization signal received at the initialization signal terminal VINIT to the fourth node N4 in response to the reset signal received at the reset signal terminal RESET, so as to reset the voltage of the fourth node N4 and clear the influence of the voltage of the previous frame period F, thereby improving the display effect.

[0197] Exemplarily, as shown in FIG. 12 and FIG. 14, the reset sub-circuit 230 is coupled with the reset signal terminal RESET, the initialization signal terminal VINIT and the fourth node N4. For example, two reset sub-circuits 230 are coupled with the fourth nodes N4 of the two gate branches 221 respectively, and each reset sub-circuit 230 includes a third transistor T3, the control electrode of which is coupled with the reset signal terminal RESET, the first electrode of which is coupled with the initialization signal terminal VINIT, and the second electrode of which is coupled with the fourth node N4, so as to simplify the circuit structure and facilitate the preparation.

[0198] As shown in FIG. 12 and FIG. 14, the two reset sub-circuits 230 are coupled with the two reset signal terminals RESET and the two initialization signal terminals VINIT respectively, and the two reset signal terminals RESET are a first sub-reset signal terminal RESET1-1 and a second sub-reset signal terminal RESET1-2 respectively, and the two initialization signal terminals VINIT are a first sub-initialization signal terminal VINIT1-1 and a second sub-initialization signal terminal VINIT1-2 respectively.

[0199] At this time, the two reset sub-circuits 230 are controlled by the first sub-reset signal terminal RESET1-1 and the second sub-reset signal terminal RESET1-2 respectively, so as to be turned on at the reset stage P20 of the multiple sub-periods P of the frame period F respectively, thereby resetting the first electrodes 31 of the two light emitting devices 30 at the reset stage P20 of the multiple sub-periods P of the frame period F respectively.

[0200] The signals transmitted by the first sub-reset signal terminal RESET1-1 and the second sub-reset signal terminal RESET1-2 can be the same or different. For example, the first sub-reset signal terminal RESET1-1 and the second sub-reset signal terminal RESET1-2 are coupled to the same signal line.

[0201] The signals transmitted by the first sub-initialization signal terminal VINIT1-1 and the second sub-initialization signal terminal VINIT1-2 can be the same or different. For example, the first sub-initialization signal terminal VINIT1-1 and the second sub-initialization signal terminal VINIT1-2 are coupled to the same signal line.

[0202] The reset sub-circuit 230 is coupled to the reset signal terminal RESET, the initialization signal terminal VINIT, and the third node N3, and some embodiments of the present disclosure are schematically described below, but the implementation of the present disclosure is not limited thereto.

[0203] On this basis, referring to FIG. 21, the channel 201 of the third transistor T3 and the channel 201 of the first transistor T1 can be located in the same layer, that is, the channel 201 of the first transistor T1 and the channel 201 of the third transistor T3 can be prepared in the same process step, so as to simplify the process flow and reduce the preparation cost.

[0204] In some embodiments, referring to FIGS. 11, 20, 21, and 39, the channel 201 of at least one second transistor T2 in the gate sub-circuit 220 can be opposite or at least partially opposite to the channel 201 of the third transistor T3.

[0205] For example, the orthogonal projection of the channel 201 of at least one second transistor T2 on the substrate 10 at least partially overlaps the orthogonal projection of the channel 201 of the third transistor T3 on the substrate 10.

[0206] In this case, the at least one second transistor T2 in the gate sub-circuit 220 is arranged on the side of the third transistor T3 close to or away from the substrate 10, and the second transistor T2 and the third transistor T3 can overlap, so as to reduce the total area occupied by the second transistor T2 and the third transistor T3, thereby facilitating further reduction of the area occupied by the pixel circuit 20, so that more sub-pixels can be arranged in a unit area of the display panel 100, so as to further improve the pixel density and resolution of the display panel 100, and meet the user's demand for increasing resolution.

[0207] For example, as shown in FIG. 11, FIG. 21 and FIG. 39, the gate sub-circuit 220 includes two gate branches 221, each of which includes a second transistor T2. Among the two second transistors T2 included in the two gate branches 221, the channel 201 of one second transistor T2 is at least partially opposite to the channel 201 of the first transistor T1, and the channel 201 of the other second transistor T2 is at least partially opposite to the channel 201 of the third transistor T3.

[0208] In this case, one second transistor T2 and the first transistor T1 can overlap, and the other second transistor T2 and the third transistor T3 can overlap, which can further reduce the total area occupied by the first transistor T1, the second transistor T2 and the third transistor T3, thereby facilitating further reduction of the area occupied by the pixel circuit 20, so that more sub-pixels can be arranged in a unit area of the display panel 100, to further improve the pixel density and resolution of the display panel 100.

[0209] It should be understood that, referring to FIG. 8, the sub-stage P further includes a data writing stage P30, which is located between the reset stage P20 and the light emitting stage P10, to write the data signal.

[0210] At this time, as shown in FIG. 6, FIG. 7 and FIG. 11, the common sub-circuit 270 can further include a data writing sub-circuit 240, which is coupled with the first scan signal end G1, the data signal end DATA and the first node N1.

[0211] Among them, referring to FIG. 7, FIG. 8 and FIG. 11, the data writing sub-circuit 240 is configured to, in the data writing stage P30, transmit the data signal received at the data signal end DATA to the first node N1 in response to the first scan signal received at the first scan signal end G1.

[0212] For example, as shown in FIG. 7 and FIG. 11, the data writing sub-circuit 240 includes a fourth transistor T4, the control electrode of which is coupled with the first scan signal end G1, the first electrode of which is coupled with the data signal end DATA, and the second electrode of which is coupled with the first node N1, which has a simple circuit structure and is easy to manufacture.

[0213] In this case, the light emitting devices 30 of the plurality of sub-pixels can at least share one data writing sub-circuit 240 to write the data signal to the first node N1. That is, the plurality of sub-pixels share one data writing sub-circuit 240, which can save the number of data writing sub-circuits 240 and compress the area occupied by the pixel circuits 20 of the plurality of sub-pixels, so that more sub-pixels can be arranged in a unit area of the display panel 100, to improve the pixel density and resolution of the display panel 100.

[0214] On this basis, referring to FIG. 21, the channel 201 of the fourth transistor T4 and the channel 201 of the first transistor T1 may, for example, be located in the same layer, that is, the channel 201 of the fourth transistor T4 and the channel 201 of the first transistor T1 may be prepared in the same process step, so as to simplify the process flow and reduce the preparation cost.

[0215] In addition, as shown in FIG. 21, along the first direction X, the channel 201 of the third transistor T3 and the channel 201 of the fourth transistor T4 may, for example, be located on opposite sides of the channel 201 of the first transistor T1, so that the circuit wiring is more regular, and the size of the pixel circuit 20 in the second direction Y is reduced. It should be noted that the first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y.

[0216] Meanwhile, the channel 201 of the third transistor T3 may extend along the first direction X, and the plurality of light emitting devices 30 coupled to the same pixel circuit 20 may be arranged along the first direction X. In this way, the maximum distance between the plurality of light emitting devices 30 and the maximum size of the pixel circuit 20 are both in the first direction X, which is beneficial to reduce the area occupied by the plurality of sub-pixels including the pixel circuit 20 and the plurality of light emitting devices 30 coupled thereto, so that more sub-pixels can be arranged in a unit area of the display panel 100, to further improve the pixel density and resolution of the display panel 100.

[0217] In some embodiments, referring to FIG. 13A, the sub-stage P further includes a compensation stage P40, which is located between the data writing stage P30 and the reset stage P20.

[0218] At this time, as shown in FIGS. 7, 11 and 13A, the driving sub-circuit 210 is further configured to, in the compensation stage P40, transmit the voltage of the second node N2 to the third node N3 under the control of the voltages of the first node N1 and the third node N3, until the voltage difference between the first node N1 and the third node N3 is equal to the threshold voltage of the first transistor T1 included in the driving sub-circuit 210, so as to extract the threshold voltage of the first transistor T1 included in the driving sub-circuit 210. In this case, in the data writing stage P30, the voltage difference between the first node N1 and the third node N3 will compensate for the threshold voltage, so as to eliminate the interference caused by the threshold voltage in the light emitting stage P10.

[0219] On this basis, as shown in FIG. 7, FIG. 11 and FIG. 13A, the common sub-circuit 270 can further include a first energy storage sub-circuit 250 coupled with the first node N1 and the third node N3. The first energy storage sub-circuit 250 is configured to, in the light emitting phase P10, pull up or pull down the voltage of the first node N1 according to the change of the voltage of the third node N3, so as to maintain the voltage difference between the first node N1 and the third node N3 unchanged, thereby playing a role of voltage stabilization.

[0220] Exemplarily, as shown in FIG. 7 and FIG. 11, the first energy storage sub-circuit 250 includes a first capacitor C1, a first plate of the first capacitor C1 is coupled with the first node N1, and a second plate of the first capacitor C1 is coupled with the third node N3, which is simple in structure and convenient for preparation.

[0221] In some embodiments, referring to FIG. 7, FIG. 11 and FIG. 13A, the data writing sub-circuit 240 is further configured to, in the compensation phase P40, transmit the data signal received at the data signal terminal DATA to the first node N1 in response to the first scan signal received at the first scan signal terminal G1. At this time, the size of the driving current is calculated according to the voltage of the data signal in the compensation phase P40 and the data writing phase P30.

[0222] It should be noted that the voltage of the data signal in the compensation phase P40 is different from the voltage of the data signal in the data writing phase P30; for example, the voltage of the data signal in the data writing phase P30 is greater than the voltage of the data signal in the compensation phase P40.

[0223] In addition, the data writing sub-circuit 240 can be further configured to, in the reset phase P20, transmit the data signal received at the data signal terminal DATA to the first node N1 in response to the first scan signal received at the first scan signal terminal G1, so as to reset the voltage of the first node N1.

[0224] In other embodiments, referring to FIG. 15A, FIG. 15B and FIG. 16, the common sub-circuit 270 can further include a first voltage sub-circuit 260 coupled with the second scan signal terminal G2, the first voltage signal terminal Vref and the first node N1.

[0225] As shown in FIGS. 15A, 15B and 16, the first voltage sub-circuit 260 is configured to, in the compensation phase P40, transmit the first voltage signal received at the first voltage signal terminal Vref to the first node N1 in response to the second scan signal received at the second scan signal terminal G2. At this time, the size of the driving current is calculated according to the first voltage signal in the compensation phase P40 and the voltage of the data signal in the data writing phase P30. It should be noted that the first voltage signal received at the first voltage signal terminal Vref can be a constant reference voltage, which is less than the voltage of the data signal in the data writing phase P30.

[0226] In addition, the first voltage sub-circuit 260 can also be configured to, in the reset phase P20, transmit the first voltage signal received at the first voltage signal terminal Vref to the first node N1 in response to the second scan signal received at the second scan signal terminal G2, so as to reset the voltage of the first node N1.

[0227] As shown in FIGS. 15A and 15B, the first voltage sub-circuit 260 may, for example, include a fifth transistor T5, the control electrode of which is coupled with the second scan signal terminal G2, the first electrode of which is coupled with the first voltage signal terminal Vref, and the second electrode of which is coupled with the first node N1. The circuit structure is simple and facilitates preparation.

[0228] On this basis, referring to FIGS. 20, 21 and 39, the channel 201 of the fifth transistor T5 and the channel 201 of the fourth transistor T4 may, for example, be located in different layers and at least partially opposite. That is, the orthogonal projection of the channel 201 of the fifth transistor T5 on the substrate 10 at least partially overlaps with the orthogonal projection of the channel 201 of the fourth transistor T4 on the substrate 10.

[0229] In this case, the fifth transistor T5 is arranged on the side of the fourth transistor T4 close to or away from the substrate 10, and the fourth transistor T4 and the fifth transistor T5 can overlap. In this way, the total area occupied by the fourth transistor T4 and the fifth transistor T5 can be reduced, thereby facilitating further reduction of the area occupied by the pixel circuit 20, so that more sub-pixels can be arranged in a unit area of the display panel 100, to further improve the pixel density and resolution of the display panel 100, and meet the user's demand for increasing resolution.

[0230] In addition, as shown in FIG. 39, the channel 201 of the fifth transistor T5 and the channel 201 of the second transistor T2 may, for example, be located in the same layer, that is, the channel 201 of the fifth transistor T5 and the channel 201 of the second transistor T2 can be prepared in the same process step, so as to simplify the process flow and reduce the preparation cost.

[0231] In some embodiments, referring to FIGS. 17 and 18, the common sub-circuit 270 further comprises a light emission control sub-circuit 280 coupled with the first power signal terminal VDD, the second light emission control signal terminal EM2 and the second node N2.

[0232] In some embodiments, referring to FIGS. 18 and 19, the light emission control sub-circuit 280 is configured to, in the compensation phase P40 and the light emission phase P10, transmit the first power signal received at the first power signal terminal VDD to the second node N2 in response to the second light emission control signal received at the second light emission control signal terminal EM2.

[0233] In some embodiments, the light emission control sub-circuit 280 can be further configured to, in the reset phase P20, turn off in response to the second light emission control signal received at the second light emission control signal terminal EM2, so as to avoid the first transistor T1 and the third transistor T3 being turned on in the reset phase P20, resulting in the first power signal terminal VDD being in communication with the initialization signal terminal VINIT, causing power loss.

[0234] In some embodiments, referring to FIGS. 17 and 18, the light emission control sub-circuit 280 comprises a sixth transistor T6, the control electrode of the sixth transistor T6 is coupled with the second light emission control signal terminal EM2, the first electrode is coupled with the first power signal terminal VDD, and the second electrode is coupled with the second node N2, which is simple in circuit structure and easy to manufacture.

[0235] In the following, the pixel circuit 20 shown in FIG. 15B is taken as an example, and each phase in a sub-section P is described in combination with the driving timing of FIG. 16, and the embodiments of the present disclosure are not limited thereto.

[0236] In the reset phase P20, the first scan signal received at the first scan signal terminal G1 is a non-working voltage (low voltage), and the fourth transistor T4 is turned off. The second scan signal received at the second scan signal terminal G2 is a working voltage (high voltage), and the fifth transistor T5 is turned on to transmit the first voltage signal received at the first voltage signal terminal Vref to the first node N1, so as to reset the voltage of the first node N1.

[0237] In addition, the reset signal received at the reset signal terminal RESET is a working voltage (high voltage), the third transistor T3 is turned on to transmit the initialization signal received at the initialization signal terminal VINIT to the third node N3, so as to reset the voltage of the third node N3. In addition, the first light emission control signal received at the first light emission control signal terminal EM1 is a working voltage (high voltage), and the second transistor T2 is turned on to reset the fourth node N4, i.e., the first electrode 31 (see FIG. 5) of the light emitting device 30. At this time, the first transistor T1 is turned on under the action of the voltage of the first node N1 and the voltage of the third node N3.

[0238] In the compensation phase P40, the first scan signal received at the first scan signal terminal G1 is a non-working voltage (low voltage), and the fourth transistor T4 is cut off. The second scan signal received at the second scan signal terminal G2 is a working voltage (high voltage), and the fifth transistor T5 is turned on to transmit the first voltage signal received at the first voltage signal terminal Vref to the first node N1, so as to maintain the voltage of the first node N1.

[0239] In addition, the reset signal received at the reset signal terminal RESET is a non-working voltage (low voltage), and the third transistor T3 is cut off. Moreover, the first light-emitting control signal received at the first light-emitting control signal terminal EM1 is a non-working voltage (low voltage), and the second transistor T2 is cut off. At this time, the voltage of the second node N2 is transmitted to the third node N3 under the control of the voltages of the first node N1 and the third node N3, until the voltage difference between the first node N1 and the third node N3 is equal to the threshold voltage of the first transistor T1, so as to extract the threshold voltage of the first transistor T1.

[0240] In the data writing phase P30, the first scan signal received at the first scan signal terminal G1 is a working voltage (high voltage), and the fourth transistor T4 is turned on to transmit the data signal received at the data signal terminal DATA to the first node N1. The second scan signal received at the second scan signal terminal G2 is a non-working voltage (low voltage), and the fifth transistor T5 is cut off. At this time, the data signal is written into the first node N1, and the first transistor T1 is turned on.

[0241] In addition, the reset signal received at the reset signal terminal RESET is a non-working voltage (low voltage), and the third transistor T3 is cut off. Moreover, the first light-emitting control signal received at the first light-emitting control signal terminal EM1 is a non-working voltage (low voltage), and the second transistor T2 is cut off.

[0242] In the light-emitting phase P10, the first scan signal received at the first scan signal terminal G1 is a non-working voltage (low voltage), and the fourth transistor T4 is cut off. The second scan signal received at the second scan signal terminal G2 is a non-working voltage (low voltage), and the fifth transistor T5 is cut off.

[0243] In addition, the reset signal received at the reset signal terminal RESET is a non-working voltage (low voltage), and the third transistor T3 is cut off. Moreover, the first light-emitting control signal received at the first light-emitting control signal terminal EM1 is a working voltage (high voltage), and the second transistor T2 is turned on. At this time, the first transistor T1 is turned on, and a driving current signal is generated according to the voltages of the first node N1 and the third node N3, and the driving current signal is transmitted to the third node N3; and the second transistor T2 is turned on to transmit the driving current signal to the light-emitting device 30, so as to drive the corresponding light-emitting device 30 to emit light.

[0244] In some embodiments of the display panel 100 provided by the present disclosure, referring to FIG. 4 and FIG. 5, the driving circuit layer 110 includes a plurality of pixel circuits 20 of any of the above embodiments. The plurality of pixel circuits 20 can be arranged in a plurality of rows and a plurality of columns, for example. Each column includes at least two pixel circuits 20 arranged along a first direction X, and each row includes at least two pixel circuits 20 arranged along a second direction Y. In this case, any two adjacent pixel circuits 20 can be symmetrically arranged along the first direction X and / or the second direction Y, so that the circuit design is more regular, the structure is more compact, and the space utilization is high.

[0245] It should be noted that the first direction X is the column direction of the arrangement of the plurality of pixel circuits 20, and the second direction Y is the row direction of the arrangement of the plurality of pixel circuits 20.

[0246] In addition, referring to FIG. 4, the plurality of light emitting devices 30 are arranged in a plurality of rows and a plurality of columns. Each column includes at least two light emitting devices 30 arranged along the first direction X, and each row includes at least two light emitting devices 30 arranged along the second direction Y. In addition, the plurality of light emitting devices 30 coupled to the same selection sub-circuit 220 are located in the same column.

[0247] In the following, some embodiments of the present disclosure will be exemplarily described by taking the arrangement of the plurality of pixel circuits 20 and the plurality of light emitting devices 30 in a plurality of rows and a plurality of columns as an example, but the embodiments of the present disclosure are not limited thereto.

[0248] In this case, referring to FIG. 42A, the plurality of columns of light emitting devices 30 include a first type of light emitting device column 311 and a second type of light emitting device column 312. The light emitting colors of the at least two light emitting devices 30 in the first type of light emitting device column 311 are different. The light emitting colors of the light emitting devices 30 in the second type of light emitting device column 312 are the same.

[0249] Exemplarily, referring to FIG. 42A, the first type of light emitting device column 311 includes a plurality of red light emitting devices R and a plurality of blue light emitting devices B, and the plurality of red light emitting devices R and the plurality of blue light emitting devices B are arranged alternately. The second type of light emitting device column 312 includes a plurality of green light emitting devices G.

[0250] Exemplarily, referring to FIG. 42A, the first type of light emitting device column 311 includes a plurality of red light emitting devices R and a plurality of green light emitting devices G, and the plurality of red light emitting devices R and the plurality of green light emitting devices G are arranged alternately. The second type of light emitting device column 312 includes a plurality of blue light emitting devices B.

[0251] In some embodiments, referring to FIG. 5, the driving circuit layer 110 includes a first sub-driving layer 111 and a second sub-driving layer 112, and the second sub-driving layer 112 is arranged between the first sub-driving layer 111 and the light emitting device layer 120.

[0252] The first sub-driving layer 111 includes the first transistor T1, and the second sub-driving layer 112 includes the second transistor T2. In this case, the second transistor T2 is closer to the light emitting device 30, and the distance between the second transistor T2 and the light emitting device 30 is smaller. In the process of connecting the second transistor T2 and the light emitting device 30, the depth of the via hole to be etched is shallower, and the process difficulty is low, which is beneficial to improve the production yield.

[0253] At this time, referring to FIGS. 5 and 15A, in a case where the pixel circuit 20 further includes a third transistor T3, a fourth transistor T4, and a fifth transistor T5, the first sub-driving layer 111 further includes the third transistor T3 and the fourth transistor T4, and the second sub-driving layer 112 further includes the fifth transistor T5.

[0254] It should be noted that the number of transistors T included in the first sub-driving layer 111 can be 0 or 1 different from the number of transistors T included in the second sub-driving layer 112, so that most of the channels 201 of the transistors T can share part of the area of at least one channel 201 of the transistors T, thereby improving the space utilization and reducing the occupied area of the pixel circuit 20.

[0255] On this basis, referring to FIGS. 5 and 26, the display panel 100 can further include a first source-drain conductive layer SD1 disposed between the first sub-driving layer 111 and the second sub-driving layer 112. The first source-drain conductive layer SD1 includes a data line DL extending along the first direction X and configured to transmit a data signal. One data line DL can be coupled to the data signal end DATA (see FIG. 15B) of one column of pixel circuits 20, for example.

[0256] In this case, the distance between the data line DL and the first electrode 31 of the light emitting device 30 is far, and the second sub-driving layer 112 is further disposed between the data line DL and the first electrode 31 of the light emitting device 30, which is beneficial to reduce the influence of the voltage jump of the data line DL on the first electrode 31, thereby reducing the crosstalk between signals and improving the display effect.

[0257] In some embodiments, referring to FIGS. 4, 27, and 33, the display panel 100 includes an initialization signal line VIL coupled to an initialization signal end VINIT and a first power supply line VDL coupled to a first power supply signal end VDD (see FIG. 15A).

[0258] In some examples, as shown in FIGS. 4, 27 and 33, the initialization signal line VIL includes a plurality of first sub-lines VIL1 and a plurality of second sub-lines VIL2, the second sub-lines VIL2 extend along the second direction Y and are coupled to the initialization signal terminals VINIT (see FIG. 15A) of a row of pixel circuits 20 to transmit the initialization signal.

[0259] In addition, the first sub-lines VIL1 extend along the first direction X, and one first sub-line VIL1 is connected to a plurality of second sub-lines VIL2, and one second sub-line VIL2 is connected to a plurality of first sub-lines VIL1 to form a mesh structure. In this case, the initialization signal line VIL forms a mesh structure, which can reduce the voltage drop of the initialization signal and reduce the difference in the initialization signal received by different pixel circuits 20, thereby improving the brightness uniformity of the display panel 100.

[0260] In some examples, as shown in FIGS. 4, 27 and 33, the first power supply line VDL includes a plurality of third sub-lines VDL1 and a plurality of fourth sub-lines VDL2, the fourth sub-lines VDL2 extend along the second direction Y and are coupled to the first power supply signal terminals VDD (see FIG. 15A) of a row of pixel circuits 20 to transmit the first power supply signal.

[0261] In addition, the third sub-lines VDL1 extend along the first direction X, and one third sub-line VDL1 is connected to a plurality of fourth sub-lines VDL2, and one fourth sub-line VDL2 is connected to a plurality of third sub-lines VDL1 to form a mesh structure. In this case, the first power supply line VDL forms a mesh structure, which can reduce the voltage drop of the first power supply signal and reduce the difference in the first power supply signal received by different pixel circuits 20, thereby improving the brightness uniformity of the display panel 100.

[0262] As shown in FIGS. 27 and 33, when the initialization signal line VIL includes the first sub-line VIL1 and the second sub-line VIL2, and the first power supply line VDL includes the third sub-line VDL1 and the fourth sub-line VDL2, the third sub-line VDL1 and the first sub-line VIL1 can be staggered, and the fourth sub-line VDL2 and the second sub-line VIL2 can be staggered. In this way, the initialization signal line VIL and the first power supply line VDL are staggered, which can reduce the risk of electrostatic breakdown causing the initialization signal line VIL and the first power supply line VDL to be short-circuited, thereby improving product yield.

[0263] It should be noted that the third sub-line VDL1 and the first sub-line VIL1 are staggered, which means that the third sub-line VDL1 and the first sub-line VIL1 do not overlap. The fourth sub-line VDL2 and the second sub-line VIL2 are staggered, which means that the fourth sub-line VDL2 and the second sub-line VIL2 do not overlap.

[0264] In some embodiments, referring to FIG. 5, the display panel 100 includes 10 conductive layers, and the driving circuit layer 110 includes 8 conductive layers. For example, the driving circuit layer 110 includes a first gate conductive layer GT1, a second gate conductive layer GT2, a third gate conductive layer GT3, a first source-drain conductive layer SD1, a fourth gate conductive layer GT4, a fifth gate conductive layer GT5, a sixth gate conductive layer GT6, and a second source-drain conductive layer SD2. The light emitting device layer 120 includes the first electrode layer 310 and the second electrode layer 330.

[0265] In other embodiments, the display panel 100 includes 9 conductive layers, and the driving circuit layer 110 includes 7 conductive layers. For example, the driving circuit layer 110 includes the first gate conductive layer GT1, the second gate conductive layer GT2, the third gate conductive layer GT3, the first source-drain conductive layer SD1, the fourth gate conductive layer GT4, and the second source-drain conductive layer SD2, and further includes either one of the fifth gate conductive layer GT5 and the sixth gate conductive layer GT6. The light emitting device layer 120 includes the first electrode layer 310 and the second electrode layer 330.

[0266] In yet other embodiments, the display panel 100 includes 8 conductive layers, and the driving circuit layer 110 includes 6 conductive layers. For example, the driving circuit layer 110 includes the first gate conductive layer GT1, the second gate conductive layer GT2, the first source-drain conductive layer SD1, the fourth gate conductive layer GT4, and the second source-drain conductive layer SD2, and further includes either one of the fifth gate conductive layer GT5 and the sixth gate conductive layer GT6. The light emitting device layer 120 includes the first electrode layer 310 and the second electrode layer 330.

[0267] In some embodiments, referring to FIG. 5, FIG. 36, and FIG. 37, the first sub-driving layer 111 includes a first semiconductor layer ACT1, the first gate conductive layer GT1, the second gate conductive layer GT2, and the third gate conductive layer GT3.

[0268] The first gate conductive layer GT1 is disposed on a side of the first semiconductor layer ACT1 close to the light emitting device layer 120, the second gate conductive layer GT2 is disposed on a side of the first gate conductive layer GT1 close to the light emitting device layer 120, and the third gate conductive layer GT3 is disposed on a side of the second gate conductive layer GT2 close to the light emitting device layer 120.

[0269] The first sub-driving layer 111 can further include a plurality of insulating layers, for example, a first gate insulating layer GI1, a second gate insulating layer GI2, a third gate insulating layer GI3, and a first interlayer insulating layer ILD1. The first gate insulating layer GI1 is disposed between the first semiconductor layer ACT1 and the first gate conductive layer GT1. The second gate insulating layer GI2 is disposed between the first gate conductive layer GT1 and the second gate conductive layer GT2. The third gate insulating layer GI3 is disposed between the second gate conductive layer GT2 and the third gate conductive layer GT3. The first interlayer insulating layer ILD1 is disposed between the third gate conductive layer GT3 and the first source-drain conductive layer SD1.

[0270] It should be noted that the thickness of the first interlayer insulating layer ILD1 is 150 nm to 300 nm. For example, the thickness of the first interlayer insulating layer ILD1 is any one of 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, and 300 nm.

[0271] In some examples, as shown in FIG. 21, the first semiconductor layer ACT1 includes a first channel portion 2011 and a first conductive portion 2012. The first channel portion 2011 can include a channel 201 of a transistor T of the first sub-driving layer 111. For example, the first channel portion 2011 includes a channel 201 of a first transistor T1, a channel 201 of a third transistor T3, and a channel 201 of a fourth transistor T4. In addition, two first conductive portions 2012 can be respectively disposed on opposite sides of one first channel portion 2011 as a first pole 211 and a second pole 212 of the transistor T to be coupled with other electronic elements (capacitors, transistors, and light emitting devices, etc.).

[0272] It should be noted that the material of the first semiconductor layer ACT1 includes an oxide and / or low-temperature polysilicon. For example, the material of the first semiconductor layer ACT1 includes low-temperature polysilicon.

[0273] In some examples, as shown in FIGS. 22, 24, 28, and 32, the first gate conductive layer GT1 includes a reset signal line RL, a first scan signal line GL1, and a first conductive block 40. The reset signal line RL and the first scan signal line GL1 extend along the second direction Y, and the first conductive block 40 can be located between the reset signal line RL and the first scan signal line GL1.

[0274] In combination with FIGS. 36 and 37, the first conductive block 40 can serve as a first plate of the first capacitor C1, and the reset signal line RL, the first scan signal line GL1, and the first conductive block 40 respectively overlap the first channel portion 2011 of the first semiconductor layer ACT1 to form a control electrode of the third transistor T3, a control electrode of the fourth transistor T4, and a control electrode of the first transistor T1, respectively.

[0275] In addition, as shown in FIG. 38B, two reset signal lines RL can be located between two first scan signal lines GL1. On this basis, the second sub-line VIL2 can be located between the two adjacent reset signal lines RL. In this way, the second sub-line VIL2 is also staggered with the reset signal line RL and the first scan signal line GL1, which can reduce the risk of short circuit between the second sub-line VIL2 and the reset signal line RL and the first scan signal line GL1, reduce the interference between signals, and the circuit structure is compact, which is conducive to improving the pixel density.

[0276] In addition, as shown in FIG. 38B, two reset signal lines RL can be located between two first scan signal lines GL1. On this basis, the second sub-line VIL2 can be located between the two adjacent reset signal lines RL. In this way, the second sub-line VIL2 is also staggered with the reset signal line RL and the first scan signal line GL1, which can reduce the risk of short circuit between the second sub-line VIL2 and the reset signal line RL and the first scan signal line GL1, reduce the interference between signals, and the circuit structure is compact, which is conducive to improving the pixel density.

[0277] In some examples, as shown in FIGS. 23, 24, 29, and 32, the second gate conductive layer GT2 includes a second conductive block 50, and the second conductive block 50 is at least partially opposite to the first conductive block 40 to form the first capacitor C1. In combination with FIGS. 36 and 37, the second conductive block 50 can serve as a second plate of the first capacitor C1, and the geometric center of the second conductive block 50 does not coincide with that of the first conductive block 40, so that part of the first conductive block 40 is exposed to facilitate the coupling of the first conductive block 40 with the corresponding circuit structure (such as the fourth transistor T4). For example, the second conductive block 50 shown in FIG. 24 exposes an edge region of a corner of the first conductive block 40; or, the second conductive block 50 shown in FIG. 32 exposes an edge region of a side of the first conductive block 40. In addition, the second sub-line VIL2 can be located in the second gate conductive layer GT2.

[0278] In this case, the spacing between the second sub-line VIL2 and the first sub-line VIL1, and between the second sub-line VIL2 and the first electrode 211 of the third transistor T3 is small, and the depth of the via required to be etched in the process of connecting the second sub-line VIL2 with the first sub-line VIL1 and the first electrode 211 of the third transistor T3 is shallow, which is low in process difficulty and conducive to improving the production yield.

[0279] On this basis, referring to FIG. 25 and FIG. 30, the third gate conductive layer GT3 can be provided with the first power line VDL, or can be provided with the third conductive block 60 to increase the capacitance of the first energy storage sub-circuit 250.

[0280] Exemplarily, as shown in FIG. 23, FIG. 25, FIG. 26 and FIG. 27, the first sub-line VIL1 can be located in the first source-drain conductive layer SD1, and the second sub-line VIL2 can be located in the second gate conductive layer GT2. The first power line VDL can be located in the third gate conductive layer GT3, i.e., the third sub-line VDL1 and the fourth sub-line VDL2 are located in the third gate conductive layer GT3. In this case, the initialization signal line VIL and the first power line VDL are distributed in three layers of conductive layers, i.e., the first source-drain conductive layer SD1, the second gate conductive layer GT and the third gate conductive layer GT3, which can reduce the number of lines of each conductive layer, reduce the line density, reduce the process difficulty, and improve the production yield.

[0281] Exemplarily, as shown in FIG. 29, FIG. 30, FIG. 31 and FIG. 33, the first sub-line VIL1 and the third sub-line VDL1 are located in the first source-drain conductive layer SD1, and the second sub-line VIL2 and the fourth sub-line VDL2 are located in the second gate conductive layer GT2. On this basis, the third gate conductive layer GT3 can include the third conductive block 60, which is at least partially opposite to the second conductive block 50 to form the first capacitor C1 to increase one first capacitor C1. Wherein, the third conductive block 60 can be connected with the first conductive block 40, so that the two first capacitors C1 are connected in parallel, thereby increasing the capacitance of the first energy storage sub-circuit 250.

[0282] In some embodiments, referring to FIG. 5, FIG. 44, FIG. 45 and FIG. 46, the second sub-driving layer 112 includes the fourth gate conductive layer GT4, the fifth gate conductive layer GT5, the second semiconductor layer ACT2, the sixth gate conductive layer GT6 and the second source-drain conductive layer SD2 (not shown in FIG. 44).

[0283] Further, the fifth gate conductive layer GT5 is arranged on the side of the fourth gate conductive layer GT4 away from the first sub-driving layer 111, the second semiconductor layer ACT2 is arranged on the side of the fifth gate conductive layer GT5 away from the first sub-driving layer 111, the sixth gate conductive layer GT6 is arranged on the side of the second semiconductor layer ACT2 away from the first sub-driving layer 111, and the second source-drain conductive layer SD2 is arranged on the side of the sixth gate conductive layer GT6 away from the first sub-driving layer 111.

[0284] The second sub-driving layer 112 can further include a plurality of insulating layers, for example, the plurality of insulating layers can include a third interlayer insulating layer ILD3, a fourth gate insulating layer GI4, a fifth gate insulating layer GI5, a fourth interlayer insulating layer ILD4, and a first planar layer PLN. The third interlayer insulating layer ILD3 is arranged between the fourth gate conductive layer GT4 and the fifth gate conductive layer GT5. The fourth gate insulating layer GI4 is arranged between the fifth gate conductive layer GT5 and the second semiconductor layer ACT2. The fifth gate insulating layer GI5 is arranged between the second semiconductor layer ACT2 and the sixth gate conductive layer GT6. The fourth interlayer insulating layer ILD4 is arranged between the sixth gate conductive layer GT6 and the second source-drain conductive layer SD2. The first planar layer PLN is arranged between the second source-drain conductive layer SD2 and the light-emitting device layer 120.

[0285] In addition, the third interlayer insulating layer ILD3 can include a second planar layer ILD31 and a buffer layer ILD32. The second planar layer ILD31 has a planar effect. The buffer layer ILD32 is arranged on the side of the second planar layer ILD31 away from the fourth gate conductive layer GT4, and has a buffer effect to reduce the risk of damage to the transistor T on the upper side.

[0286] On this basis, the material of the second planar layer ILD31 includes a low dielectric constant material, for example, the material of the second planar layer ILD31 includes a material with a dielectric constant less than or equal to 4; for example, the material of the second planar layer ILD31 includes an organic resin, which is conducive to reducing the interference between the first sub-driving layer 111 and the second sub-driving layer 112, and the interference between the data line DL and the first electrode 31. In addition, the thickness of the second planar layer ILD31 can be relatively large, for example, the thickness of the second planar layer ILD31 is 1.5 μm to 2 μm; for example, the thickness of the second planar layer ILD31 is any one of 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, and 2 μm, to further reduce the interference between the first sub-driving layer 111 and the second sub-driving layer 112, and the interference between the data line DL and the first electrode 31.

[0287] In some examples, as shown in FIG. 39, the second semiconductor layer ACT2 includes a second channel portion 2021 and a second conductive portion 2022. The second channel portion 2021 can include the channel 201 of the transistor T of the second sub-driving layer 112. For example, the second channel portion 2021 includes the channel 201 of the second transistor T2 and the channel 201 of the fifth transistor T5. In addition, two second conductive portions 2022 can be arranged on opposite sides of one second channel portion 2021 as the first pole 211 and the second pole 212 of the transistor T, to be coupled with other electronic elements (capacitors, transistors, and light-emitting devices, etc.).

[0288] It should be noted that the material of the second semiconductor layer ACT2 can include an oxide. For example, the material of the second semiconductor layer ACT2 includes any one of indium gallium zinc oxide, indium tin zinc oxide, and indium zinc oxide, to avoid causing adverse effects on the transistor T of the first sub-driving layer 111 below by using a high-temperature process (e.g., greater than or equal to 400°C) to form low-temperature polysilicon.

[0289] In addition, the materials of the first semiconductor layer ACT1 and the second semiconductor layer ACT2 can be the same. For example, the materials of the first semiconductor layer ACT1 and the second semiconductor layer ACT2 are both oxides. Of course, the materials of the first semiconductor layer ACT1 and the second semiconductor layer ACT2 can also be different. For example, the material of the first semiconductor layer ACT1 is low-temperature polysilicon, and the material of the second semiconductor layer ACT2 is an oxide.

[0290] In some examples, as shown in FIG. 34, the fourth gate conductive layer GT4 includes a first transfer block 81 and a second transfer block 82.

[0291] In combination with FIGS. 34, 35, 36, 39, and 44, the first transfer block 81 is connected with the second conductive block 50 and the second conductive part 2022, respectively, to couple the first pole 211 of the second transistor T2 with the second pole plate of the first capacitor C1. In combination with FIGS. 34, 35, and 36, the second transfer block 82 is connected with the first conductive block 40 and the first conductive part 2012, to couple the second pole 212 of the fourth transistor T4 with the first pole plate of the first capacitor C1.

[0292] In combination with FIGS. 43, 44, 45, and 46, the connection manner of the first transfer block 81 with the second conductive part 2022 is not unique, which can be directly connected or connected through the second source-drain conductive layer SD2.

[0293] Exemplarily, as shown in FIG. 44, the second semiconductor layer ACT2 further includes a first connecting column 91, which is located between the second conductive part 2022 and the first transfer block 81 and in electrical contact with the second conductive part 2022 and the first transfer block 81. In this way, the distance between the second conductive part 2022 and the first transfer block 81 is closer, the depth of the via required to be etched in the process of forming the first connecting column 91 is shallower, the process difficulty is low, and the production yield is improved.

[0294] Exemplarily, as shown in FIG. 45, the second source-drain conductive layer SD2 includes the third transfer block 83 and the second connecting column 92, a part of the second connecting column 92 is staggered with the second channel portion 2021 and the second conductive portion 2022, and is located between the third transfer block 83 and the first transfer block 81, and is in electrical contact with the third transfer block 83 and the first transfer block 81; another part is located between the third transfer block 83 and the second conductive portion 2022, and is in electrical contact with the third transfer block 83 and the second conductive portion 2022.

[0295] In this way, the first transfer block 81 is transferred to the second conductive portion 2022 through the second source-drain conductive layer SD2, and the process of the transfer can be performed synchronously with the connection process of other structures included in the second source-drain conductive layer SD2, for example, the connection between the fifth transfer block 85 and the second conductive portion 2022 mentioned below, so that the process flow can be simplified and the manufacturing cost can be reduced. Moreover, the second connecting column 92 can be directly formed by one etching process, so that the process flow can be simplified and the manufacturing cost can be reduced.

[0296] Exemplarily, as shown in FIG. 46, the second source-drain conductive layer SD2 further includes the fourth transfer block 84, the third connecting column 93 and the fourth connecting column 94, and the third connecting column 93 and the fourth connecting column 94 are arranged in a spaced manner. Among them, the third connecting column 93 is staggered with the second channel portion 2021 and the second conductive portion 2022, and is located between the fourth transfer block 84 and the first transfer block 81, and is in electrical contact with the fourth transfer block 84 and the first transfer block 81. The fourth connecting column 94 is located between the fourth transfer block 84 and the second conductive portion 2022, and is in electrical contact with the fourth transfer block 84 and the second conductive portion 2022.

[0297] In this way, the first transfer block 81 is transferred to the second conductive portion 2022 through the second source-drain conductive layer SD2, and the process of the transfer can be performed synchronously with the connection process of other structures included in the second source-drain conductive layer SD2, for example, the connection between the fifth transfer block 85 and the second conductive portion 2022 mentioned below, so that the process flow can be simplified and the manufacturing cost can be reduced. Moreover, the third connecting column 93 and the fourth connecting column 94 are formed respectively, and the depth of the corresponding via can be controlled respectively, so as to avoid the adverse effects caused by over-etching.

[0298] In some examples, as shown in FIG. 38A, the fifth gate conductive layer GT5 includes the second scan signal line GL2 and the first emission control signal line EL1, and the second scan signal line GL2 and the first emission control signal line EL1 extend along the second direction Y and overlap with the second channel portion 2021 of the second semiconductor layer ACT2 respectively, so as to form the first control electrode of the fifth transistor T5 and the first control electrode of the second transistor T2 respectively.

[0299] In some examples, as shown in FIG. 40, the sixth gate conductive layer GT6 includes the second scan signal lines GL2 and the first emission control signal lines EL1, the second scan signal lines GL2 and the first emission control signal lines EL1 extend along the second direction Y and respectively overlap with the second channel portions 2021 of the second semiconductor layers ACT2 to respectively form the second control electrodes of the fifth transistors T5 and the second control electrodes of the second transistors T2.

[0300] That is, some of the second scan signal lines GL2 are located in the fifth gate conductive layer GT5 to form the first control electrodes of the fifth transistors T5, and some of the second scan signal lines GL2 are located in the sixth gate conductive layer GT6 to form the second control electrodes of the fifth transistors T5, so that the fifth transistors T5 are controlled by the first control electrodes and the second control electrodes, and the leakage current can be reduced.

[0301] In addition, some of the first emission control signal lines EL1 are located in the fifth gate conductive layer GT5 to form the first control electrodes of the second transistors T2, and some of the first emission control signal lines EL1 are located in the sixth gate conductive layer GT6 to form the second control electrodes of the second transistors T2, so that the second transistors T2 are controlled by the first control electrodes and the second control electrodes, and the leakage current can be reduced.

[0302] It should be noted that the display panel 100 can also only include the fifth gate conductive layer GT5 and not include the sixth gate conductive layer GT6. Alternatively, the display panel 100 can also only include the sixth gate conductive layer GT6 and not include the fifth gate conductive layer GT5.

[0303] As shown in FIG. 38B, at least 4 first emission control signal lines EL1 can be located between two second scan signal lines GL2. On this basis, the second scan signal lines GL2 and the first scan signal lines GL1 can at least partially overlap. The reset signal line RL is located between two first emission control signal lines EL1 connected to and adjacent to the first emission control signal terminals EM of different pixel circuits 20. In this way, the reset signal line RL is also staggered with the first emission control signal lines EL1 and the second scan signal lines GL2, which can reduce the risk of short circuit between the reset signal line RL and the first emission control signal lines EL1 and the second scan signal lines GL2, reduce the interference between signals, and the circuit structure is compact, which is beneficial to improve the pixel density.

[0304] In addition, the fourth sub-line VDL2 can be located between the adjacent first light-emitting control signal line EL1 and the second scan signal line GL2. In this way, the fourth sub-line VDL2 is arranged away from both the first light-emitting control signal line EL1 and the second scan signal line GL2, which can reduce the risk of short circuit between the fourth sub-line VDL2 and the first light-emitting control signal line EL1 and the second scan signal line GL2, reduce interference between signals, and compact the circuit structure, thereby improving the pixel density.

[0305] In some examples, as shown in FIG. 41, the second source-drain conductive layer SD2 includes a reference voltage signal line VRL and a fifth adapter block 85 connected with the second conductive part 2022 and the first electrode 31 of the light-emitting device 30 to couple the second electrode 212 of the second transistor T2 with the first electrode 31 of the light-emitting device 30.

[0306] It should be noted that, according to the arrangement of the light-emitting device 30, the size and shape of the fifth adapter block 85 connected with different light-emitting devices 30 can be adaptively adjusted, which is not limited in the embodiments of the present disclosure.

[0307] In addition, the reference voltage signal line VRL includes a fifth sub-line VRL1 and a sixth sub-line VRL2, the fifth sub-line VRL1 extends along the first direction X, and the sixth sub-line VRL2 extends along the second direction Y, and one fifth sub-line VRL1 is connected with a plurality of sixth sub-lines VRL2, and one sixth sub-line VRL2 is connected with a plurality of fifth sub-lines VRL1 to form a mesh structure. In this case, the reference voltage signal line VRL forms a mesh structure, which can reduce the voltage drop of the reference voltage signal and reduce the difference in the reference voltage signals received by different pixel circuits 20, thereby improving the brightness uniformity of the display panel 100.

[0308] In some embodiments, referring to FIG. 5, the light-emitting device layer 120 includes a first electrode layer 310, a light-emitting functional layer 320, and a second electrode layer 330 arranged in sequence, and the second electrode layer 330 is located on the side of the first electrode layer 310 away from the driving circuit layer 110.

[0309] As shown in FIGS. 41 and 42A, the first electrode layer 310 includes a plurality of first electrodes 31 connected with the fifth adapter block 85 to be coupled with the second electrode 212 of the second transistor T2 through the fifth adapter block 85. Of course, the first electrode 31 can also be directly connected with the second electrode 212 of the second transistor T2, that is, the second source-drain conductive layer SD2 does not include the fifth adapter block 85, which is not limited in the embodiments of the present disclosure.

[0310] In addition, the light-emitting functional layer 320 includes a plurality of light-emitting portions 32. The second electrode layer 330 can be a continuous whole layer structure. The second electrode layer 330 includes a plurality of second electrodes 33, which can be, for example, portions of the second electrode layer 330 that overlap the light-emitting portions 32.

[0311] It should be noted that the light-emitting functional layer 320 can include only a light-emitting layer, or the light-emitting functional layer 320 can include at least one of an electron transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL) in addition to the light-emitting layer.

[0312] In some embodiments, as shown in FIG. 5, the display panel 100 further includes a pixel definition layer PDL, which is provided with a plurality of pixel openings 101, and one light-emitting device 30 is located in one pixel opening 101. The shape of the pixel opening 101 is at least one of substantially a quadrangle, an ellipse, and a circle.

[0313] In this document, “substantially a circle or an ellipse” means that the shape is generally a circle or an ellipse, but is not limited to a standard circle or an ellipse. That is, “a circle or an ellipse” herein includes not only a substantially circular or elliptical shape, but also a shape similar to a circle or an ellipse.

[0314] In this document, “substantially a quadrangle” means that the shape is generally a quadrangle, but is not limited to a standard quadrangle. That is, “a quadrangle” herein includes not only a substantially quadrangular shape, but also a shape similar to a quadrangle. For example, the quadrangle is curved at each intersection (i.e., at the corners), i.e., the corners are smooth, and the shape is a rounded quadrangle.

[0315] In some embodiments, in combination with FIGS. 42A, 42B, and 42C, the first electrode 31 includes a main body portion 301 and a lapping portion 302, and the pixel opening 101 exposes at least part of the main body portion 301, and the lapping portion 302 is connected to the second electrode 212 (see FIG. 39) of the second transistor T2 through a connection hole 303. In the first direction X, the connection hole 303 is at least partially opposite to the pixel opening 101, for example, the geometric center line of the connection hole 303 and the geometric center line of the pixel opening 101 are substantially parallel to the first direction X.

[0316] In some embodiments, as shown in FIGS. 42A, 42B and 42C, the two adjacent columns of light emitting devices 30 are a first column of light emitting devices 313 and a second column of light emitting devices 314. In the first column of light emitting devices 313, the overlap portion 302 is located at a first side of the body portion 301 along the first direction X. In the second column of light emitting devices 314, the overlap portion 302 is located at a second side of the body portion 301 along the first direction X. The first side and the second side are opposite sides of the body portion 301.

[0317] In some embodiments, as shown in FIGS. 42B and 42C, the ratio of the area of the body portion 301 to the area of the pixel opening 101 is 0.7-0.9. For example, the ratio of the area of the body portion 301 to the area of the pixel opening 101 is any one of 0.7, 0.72, 0.75, 0.77, 0.78, 0.8, 0.82, 0.85, 0.86, 0.88 and 0.9.

[0318] In some embodiments, as shown in FIGS. 42B and 42C, the ratio of the size of the connection hole 303 to the size of the pixel opening 101 in any direction parallel to the pixel defining layer PDL (see FIG. 5) is 0.5-0.9. For example, the ratio of the size of the connection hole 303 to the size of the pixel opening 101 is any one of 0.5, 0.54, 0.55, 0.56, 0.58, 0.6, 0.65, 0.68, 0.7, 0.72, 0.75, 0.8, 0.82, 0.85, 0.88 and 0.9.

[0319] In some embodiments, as shown in FIGS. 5 and 38B, the display panel 100 includes a plurality of gate lines MGL, which can include at least one of the first light emitting control signal line EL1, the first scan signal line GL1, the second scan signal line GL2 and the reset signal line RL, for example. The ratio of the size of the gate line MGL to the size of the pixel opening 101 is 0.5-1.2 in a direction perpendicular to the extension direction of the gate line MGL. For example, the ratio of the size of the gate line MGL to the size of the pixel opening 101 is any one of 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, 1.05, 1.1, 1.15 and 1.2.

[0320] In some embodiments, as shown in FIG. 5, the display panel 100 further includes an encapsulation layer 130 disposed on the side of the light emitting device layer 120 away from the substrate 10 to reduce the risk of water and oxygen corrosion. The encapsulation layer 130 can be an encapsulation film or an encapsulation substrate, which is not limited in the embodiments of the present disclosure.

[0321] In some embodiments, referring to FIG. 4, the display panel 100 includes a gate driving circuit 140 and a source driving circuit 150, the source driving circuit 150 is disposed at least one side of the display area A along the first direction X, and the gate driving circuit 140 is disposed at least one side of the display area A along the second direction Y.

[0322] The source driving circuit 150 is coupled with a data line DL, and one data line DL is coupled with at least one column of pixel circuits 20 to provide a data signal to the at least one column of pixel circuits 20. In combination with FIG. 4 and FIG. 47, the gate driving circuit 140 includes a plurality of cascaded shift registers RS, one shift register RS is coupled with at least one control signal line KL, and one control signal line KL is coupled with at least one row of pixel circuits 20 to provide a control signal to the at least one row of pixel circuits 20, the control signal includes any one of a first light emitting control signal, a second light emitting control signal, a first scanning signal, a second scanning signal, and a reset signal.

[0323] For example, referring to FIG. 47, the signal input end of the first stage of shift registers RS is coupled with a start signal line STV, and in each adjacent two stages of shift registers RS, the signal input end of the lower stage of shift registers RS is coupled with the output end of the upper stage of shift registers RS.

[0324] In some examples, referring to FIG. 47, the gate driving circuit 140 is disposed at one side of the display area A, and each row of pixel circuits 20 is sequentially driven row by row from a single side of the display area A to form a single-side driving. In other examples, referring to FIG. 4, the gate driving circuit 140 is disposed at opposite sides of the display area A, and two gate driving circuits 140 simultaneously drive each row of pixel circuits 20 row by row from opposite sides of the display area A to form a double-side driving.

[0325] In the following, some embodiments of the present disclosure are illustratively described taking the single-side driving as an example, but the embodiments of the present disclosure are not limited thereto, and any other driving mode can also be considered as long as the same technical idea is applied.

[0326] In some embodiments, referring to FIG. 47, the plurality of gate driving circuits 140 includes a first gate driving circuit 141, and the first gate driving circuit 141 is coupled with a first light emitting control signal line EL1 to provide a first light emitting control signal.

[0327] As shown in FIG. 15A and FIG. 47, along the first direction X, the plurality of first light-emitting control signal lines EL1 are divided into a plurality of first light-emitting control signal line groups EL10, each of which includes at least two first light-emitting control signal lines EL1 arranged adjacently. The first light-emitting control signal ends EM1 of the plurality of selection branches 221 in a row of pixel circuits 20 are respectively coupled to the plurality of first light-emitting control signal lines EL1 in one first light-emitting control signal line group EL10.

[0328] On this basis, as shown in FIG. 47, the plurality of first light-emitting control signal lines EL1 in the first light-emitting control signal line group EL10 are respectively coupled to the plurality of first gate drive circuits 141, and the plurality of first gate drive circuits 141 are configured to be driven sequentially within one frame period F to drive the plurality of rows of light-emitting devices 30 respectively coupled to one row of pixel circuits 20 within one frame period F.

[0329] In addition, along the first direction Y, the number of first light-emitting control signal lines EL1 between the two first light-emitting control signal lines EL1 coupled to the same first gate drive circuit 141 in any two adjacent first light-emitting control signal line groups EL10 is the same. In this case, the wiring arrangement is regular, and the interval between the rows of light-emitting devices 30 that are sequentially lit is fixed. Within one frame period F, the brightness of the light-emitting devices 30 in the two adjacent rows is fused, which can balance the overall brightness of the picture and improve the brightness uniformity.

[0330] Exemplarily, as shown in FIG. 47, the first light-emitting control signal line group EL10 includes two first light-emitting control signal lines EL1, and the two first light-emitting control signal lines EL1 are respectively coupled to one first gate drive circuit 141.

[0331] At this time, one first gate drive circuit 141 is used to sequentially drive the light-emitting devices 30 in the odd rows, and the other first gate drive circuit 141 is used to sequentially drive the light-emitting devices 30 in the even rows. For example, one first gate drive circuit 141 sequentially drives the light-emitting devices 30 in the 1st, 3rd, 5th, …, 2N+1th rows, and the other first gate drive circuit 141 sequentially drives the light-emitting devices 30 in the 2nd, 4th, 6th, …, 2(N+1)th rows, where N is greater than or equal to 0 and is an integer.

[0332] Exemplarily, as shown in FIG. 48, the first light-emitting control signal line group EL10 includes three first light-emitting control signal lines EL1, and the three first light-emitting control signal lines EL1 are respectively coupled to one first gate drive circuit 141.

[0333] At this time, one first gate drive circuit 141 can drive the light emitting devices 30 of the 1st, 4th, 7th,..., 3M+1st rows in order, one first gate drive circuit 141 can drive the light emitting devices 30 of the 2nd, 5th, 8th,..., 3M+2nd rows in order, and the remaining one first gate drive circuit 141 can drive the light emitting devices 30 of the 3rd, 6th, 9th,..., 3(M+1)th rows in order, M is greater than or equal to 0 and is an integer.

[0334] In the description of the present specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in an appropriate manner.

[0335] The above description is merely specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A pixel circuit, a frame period comprising a plurality of sub-periods performed in sequence, each of the sub-periods comprising a light emitting phase, the pixel circuit comprising: a driving sub-circuit coupled to a first node, a second node and a third node; the first node coupled to a data signal terminal, the second node coupled to a first power signal terminal; the driving sub-circuit configured to, in the light emitting phase, generate a driving current signal according to voltages of the first node and the third node, and transmit the driving current signal to the third node; a gate sub-circuit coupled to the third node; the gate sub-circuit configured to be coupled to a plurality of light emitting devices, and transmit the driving current signal from the third node to different light emitting devices in different light emitting phases; wherein the driving sub-circuit comprises a first transistor, the gate sub-circuit comprises a second transistor, and channels of at least one of the second transistors and a channel of the first transistor are located in different layers and at least partially opposite.

2. The pixel circuit of claim 1, wherein, the gate sub-circuit comprising: a plurality of gate branches, the gate branches coupled to the third node, a fourth node and a first light emitting control signal terminal, different gate branches coupled to different fourth nodes and different first light emitting control signal terminals; the fourth nodes configured to be coupled to the light emitting devices, and different fourth nodes coupled to different light emitting devices; the gate branches configured to, in a light emitting phase of a frame period, transmit the driving current signal of the third node to the fourth node in response to a light emitting control signal received at the first light emitting control signal terminal.

3. The pixel circuit of claim 2, wherein, the gate branches comprising the second transistors, control electrodes of the second transistors coupled to the first light emitting control signal terminals, first electrodes coupled to the third node, and second electrodes coupled to the fourth nodes.

4. The pixel circuit according to claim 2 or 3, wherein the sub-periods comprising a reset phase, the reset phase located before the light emitting phase, the pixel circuit further comprising: a reset sub-circuit coupled to a reset signal terminal and an initialization signal terminal, and further coupled to the third node and / or the fourth node; the reset sub-circuit configured to, in the reset phase, transmit an initialization signal received at the initialization signal terminal to the third node and / or the fourth node in response to a reset signal received at the reset signal terminal.

5. The pixel circuit of claim 4, wherein, the reset sub-circuit comprising: a third transistor, a control electrode of the third transistor coupled to the reset signal terminal, a first electrode coupled to the initialization signal terminal, and a second electrode coupled to the third node; a channel of the third transistor located in the same layer as a channel of the first transistor, and a channel of at least one of the second transistors at least partially opposite to a channel of the third transistor.

6. The pixel circuit of claim 5, wherein, the gate sub-circuit comprising two gate branches, each of the gate branches comprising a second transistor; among two second transistors comprised by the two gate branches, a channel of one of the second transistors at least partially opposite to the channel of the first transistor, and a channel of the other of the second transistors at least partially opposite to a channel of the third transistor.

7. The pixel circuit according to any one of claims 1 to 6, wherein The sub-stage further comprises a data writing stage, which is located before the light emitting stage, and the pixel circuit further comprises: a data writing sub-circuit, coupled with the first scan signal terminal, the data signal terminal and the first node; the data writing sub-circuit is configured to, in the data writing stage, transmit the data signal received at the data signal terminal to the first node in response to the first scan signal received at the first scan signal terminal.

8. The pixel circuit of claim 7, wherein, The sub-stage further comprises a compensation stage, which is located before the data writing stage; The driving sub-circuit is further configured to, in the compensation stage, transmit the voltage of the second node to the third node under the control of the voltages of the first node and the third node, until the voltage difference between the first node and the third node is equal to the threshold voltage of the first transistor included in the driving sub-circuit; The pixel circuit further comprises: a first energy storage sub-circuit, coupled with the first node and the third node; the first energy storage sub-circuit is configured to, in the light emitting stage, pull up or pull down the voltage of the first node according to the change of the voltage of the third node, so as to maintain the voltage difference between the first node and the third node unchanged.

9. The pixel circuit of claim 8, wherein, The data writing sub-circuit is further configured to, in the compensation stage, transmit the data signal received at the data signal terminal to the first node in response to the first scan signal received at the first scan signal terminal.

10. The pixel circuit of claim 8, wherein, The pixel circuit further comprises: a first voltage sub-circuit, coupled with the second scan signal terminal, the first voltage signal terminal and the first node; the first voltage sub-circuit is configured to, in the compensation stage, transmit the first voltage signal received at the first voltage signal terminal to the first node in response to the second scan signal received at the second scan signal terminal.

11. The pixel circuit according to any one of claims 7 to 10, wherein The data writing sub-circuit comprises: a fourth transistor, the control electrode of which is coupled with the first scan signal terminal, the first electrode of which is coupled with the data signal terminal, and the second electrode of which is coupled with the first node; the channel of the fourth transistor is located in the same layer as the channel of the first transistor.

12. The pixel circuit according to claim 11, comprising a reset sub-circuit, the reset sub-circuit comprising a third transistor; along a first direction, the channel of the third transistor and the channel of the fourth transistor are located on opposite sides of the channel of the first transistor.

13. The pixel circuit according to claim 11 or 12, comprising a first voltage sub-circuit, the first voltage sub-circuit comprising: a fifth transistor, the control electrode of which is coupled with the second scan signal terminal, the first electrode of which is coupled with the first voltage signal terminal, and the second electrode of which is coupled with the first node; the channel of the fifth transistor is located in different layers from the channel of the fourth transistor, and at least partially opposite to the channel of the fourth transistor.

14. A display panel, one frame period comprising a plurality of sub-stages performed in sequence, each of the sub-stages comprising a light emitting stage, the display panel comprising: A driving circuit layer includes a plurality of pixel circuits, the pixel circuit includes a driving sub-circuit and a gate-on sub-circuit, the driving sub-circuit is coupled with a first node, a second node and a third node; the first node is coupled to a data signal end, the second node is coupled to a first power signal end; the gate-on sub-circuit is coupled with the third node; the driving sub-circuit includes a first transistor, the gate-on sub-circuit includes a second transistor, the channel of at least one second transistor and the channel of the first transistor are located in different layers and at least partially opposite; A light emitting device layer is arranged on one side of the driving circuit layer; the light emitting device layer includes a plurality of light emitting devices, the light emitting device is coupled with the gate-on sub-circuit, and at least two light emitting devices are coupled with the same gate-on sub-circuit; the gate-on sub-circuit is configured to transmit the driving current signal from the third node to different light emitting devices in different light emitting stages.

15. The display panel of claim 14, wherein, The pixel circuit includes a reset sub-circuit, the reset sub-circuit is coupled with a reset signal end and an initialization signal end, and is also coupled with a third node; The display panel further includes: An initialization signal line is coupled with the initialization signal end; the initialization signal line includes: A plurality of first sub-lines extend in a first direction; A plurality of second sub-lines extend in a second direction; one first sub-line is connected with the plurality of second sub-lines, and one second sub-line is connected with the plurality of first sub-lines; the first direction and the second direction intersect; A first power line is coupled with a first power signal end; the first power line includes: A plurality of third sub-lines extend in the first direction; A plurality of fourth sub-lines extend in the second direction; one third sub-line is connected with the plurality of fourth sub-lines, and one fourth sub-line is connected with the plurality of third sub-lines; and, the third sub-line is arranged staggered with the first sub-line, and the fourth sub-line is arranged staggered with the second sub-line.

16. The display panel of claim 14 or 15, wherein, The pixel circuit includes a reset sub-circuit, the reset sub-circuit is coupled with a reset signal end and an initialization signal end, and is also coupled with a third node; The display panel further includes: An initialization signal line is coupled with the initialization signal end; the initialization signal line includes: A plurality of first sub-lines extend in a first direction; A plurality of second sub-lines extend in a second direction; one first sub-line is connected with the plurality of second sub-lines, and one second sub-line is connected with the plurality of first sub-lines; the first direction and the second direction intersect; A first power line is coupled with a first power signal end; the first power line includes: A plurality of third sub-lines extend in the first direction; A plurality of fourth sub-lines extend in the second direction; one third sub-line is connected with the plurality of fourth sub-lines, and one fourth sub-line is connected with the plurality of third sub-lines; and, the third sub-line is arranged staggered with the first sub-line, and the fourth sub-line is arranged staggered with the second sub-line.

17. The display panel according to any one of claims 14-16, comprising 10 conductive layers, and the driving circuit layer comprises 8 conductive layers; or, the display panel comprises 9 conductive layers, and the driving circuit layer comprises 7 conductive layers; or, the display panel comprises 8 conductive layers, and the driving circuit layer comprises 6 conductive layers.

18. The display panel of claim 17, wherein, The pixel circuit comprises a data writing sub-circuit, which is coupled with a first scan signal terminal, a data signal terminal and a first node; the display panel comprises a first source-drain conductive layer, which comprises a data line coupled with the data signal terminal; The driving circuit layer comprises: a first semiconductor layer comprising a first channel portion and a first conductive portion; a first gate conductive layer disposed on a side of the first semiconductor layer close to the light emitting device layer; the first gate conductive layer comprises a reset signal line and a first scan signal line, the reset signal line and the first scan signal line extend along the second direction, and the reset signal line and the first scan signal line respectively overlap the first channel portion of the first semiconductor layer; a second gate conductive layer disposed on a side of the first gate conductive layer close to the light emitting device layer; the second gate conductive layer comprises a second conductive block; a third gate conductive layer disposed on a side of the second gate conductive layer close to the light emitting device layer.

19. The display panel of claim 18, wherein, The first gate conductive layer further comprises a first conductive block, the first conductive block overlaps the first channel portion of the first semiconductor layer, and the second conductive block at least partially opposes the first conductive block.

20. The display panel of claim 18 or 19, wherein, The third gate conductive layer further comprises a third conductive block, the third conductive block at least partially opposes the second conductive block.

21. The display panel of any of claims 18-20, wherein, The display panel further comprises an initialization signal line and a first power supply line, the initialization signal line comprises a first sub-line and a second sub-line, and the first power supply line comprises a third sub-line and a fourth sub-line: The first sub-line is located in the first source-drain conductive layer; the second sub-line is located in the second gate conductive layer, and the third sub-line and the fourth sub-line are located in the third gate conductive layer.

22. The display panel of any one of claims 18-20, wherein, The display panel further comprises an initialization signal line and a first power supply line, the initialization signal line comprises a first sub-line and a second sub-line, and the first power supply line comprises a third sub-line and a fourth sub-line: The first sub-line and the third sub-line are located in the first source-drain conductive layer, and the second sub-line and the fourth sub-line are located in the second gate conductive layer.

23. The display panel of claim 21 or 22, wherein, The reset signal line and the first scan signal line extend along the second direction, and two reset signal lines are located between two first scan signal lines.

24. The display panel of claim 23, wherein, The second sub-line is located between two adjacent reset signal lines.

25. The display panel of claim 23 or 24, wherein, The fourth sub-line is located between the reset signal line and the first scan signal line.

26. The display panel of any one of claims 14-25, wherein, The driving circuit layer comprises: a first sub-driving layer comprising a first transistor; a second sub-driving layer disposed between the first sub-driving layer and the light emitting device layer; the second sub-driving layer comprises a second transistor, and a channel of at least one second transistor at least partially opposes a channel of the first transistor.

27. The display panel of claim 26, wherein, The pixel circuit comprises a data writing sub-circuit coupled with a first scanning signal end, a data signal end and a first node; and the display panel further comprises: A first source-drain conductive layer is arranged between the first sub-driving layer and the second sub-driving layer; the first source-drain conductive layer comprises a data line coupled with the data signal end.

28. The display panel of claim 27, wherein, The first sub-driving layer comprises a second gate conductive layer comprising a second conductive block; and the second sub-driving layer comprises: A fourth gate conductive layer comprising a first adapter block connected with the second conductive block; A second semiconductor layer is arranged on a side of the fourth gate conductive layer away from the first sub-driving layer; the second semiconductor layer comprises a second channel portion, a second conductive portion and a first connecting column; the first connecting column is located between the second conductive portion and the first adapter block and electrically contacts the second conductive portion and the first adapter block.

29. The display panel of claim 27, wherein, The first sub-driving layer comprises a second gate conductive layer comprising a second conductive block; and the second sub-driving layer comprises: A fourth gate conductive layer comprising a first adapter block connected with the second conductive block; A second semiconductor layer is arranged on a side of the fourth gate conductive layer away from the first sub-driving layer; the second semiconductor layer comprises a second channel portion and a second conductive portion; A second source-drain conductive layer is arranged on a side of the second semiconductor layer away from the first sub-driving layer; the second source-drain conductive layer comprises a third adapter block and a second connecting column; a part of the second connecting column is staggered with the second channel portion and the second conductive portion and is located between the third adapter block and the first adapter block and electrically contacts the third adapter block and the first adapter block; another part is located between the third adapter block and the second conductive portion and electrically contacts the third adapter block and the second conductive portion.

30. The display panel of claim 27, wherein, The first sub-driving layer comprises a second gate conductive layer comprising a second conductive block; and the second sub-driving layer comprises: A fourth gate conductive layer comprising a first adapter block connected with the second conductive block; A second semiconductor layer is arranged on a side of the fourth gate conductive layer away from the first sub-driving layer; the second semiconductor layer comprises a second channel portion and a second conductive portion; A second source-drain conductive layer is arranged on a side of the second semiconductor layer away from the first sub-driving layer; the second source-drain conductive layer comprises a fourth adapter block, a third connecting column and a fourth connecting column; the third connecting column and the fourth connecting column are arranged at intervals; wherein the third connecting column is staggered with the second channel portion and the second conductive portion and is located between the fourth adapter block and the first adapter block and electrically contacts the fourth adapter block and the first adapter block; the fourth connecting column is located between the fourth adapter block and the second conductive portion and electrically contacts the fourth adapter block and the second conductive portion.

31. The display panel of any of claims 28-30, wherein, The second sub-driving layer further comprises a fifth gate conductive layer, the fifth gate conductive layer is arranged on a side of the fourth gate conductive layer away from the first sub-driving layer, and the second semiconductor layer is arranged on a side of the fifth gate conductive layer away from the first sub-driving layer. The fifth gate conductive layer comprises a second scan signal line and a first light-emitting control signal line, the second scan signal line and the first light-emitting control signal line extend along the second direction and respectively overlap with the second channel part of the second semiconductor layer.

32. The display panel of any one of claims 28-31, wherein, The second sub-driving layer further comprises a sixth gate conductive layer, the sixth gate conductive layer is arranged on a side of the second semiconductor layer away from the first sub-driving layer. The sixth gate conductive layer comprises a second scan signal line and a first light-emitting control signal line, the second scan signal line and the first light-emitting control signal line extend along the second direction and respectively overlap with the second channel part of the second semiconductor layer.

33. The display panel of claim 31 or 32, wherein, At least four first light-emitting control signal lines are located between two second scan signal lines.

34. The display panel of claim 33, comprising a reset signal line and a first scan signal line, the reset signal line and the first scan signal line extend along the second direction; The second scan signal line at least partially overlaps with the first scan signal line; and the reset signal line is located between two first light-emitting control signal lines connected to first light-emitting control signal terminals of pixel circuits belonging to different groups.

35. The display panel of claim 34, further comprising a first power supply line, the first power supply line comprises a third sub-line and a fourth sub-line, the fourth sub-line is located between the first light-emitting control signal line and the second scan signal line.

36. The display panel of any one of claims 26-35, wherein, The first sub-driving layer comprises a first semiconductor layer, a material of the first semiconductor layer comprises an oxide or low-temperature polysilicon; and the second sub-driving layer comprises a second semiconductor layer, a material of the second semiconductor layer comprises an oxide or low-temperature polysilicon.

37. The display panel of claim 36, wherein, The materials of the first semiconductor layer and the second semiconductor layer comprise an oxide.

38. The display panel of any one of claims 26-37, wherein, The number of transistors included in the first sub-driving layer and the number of transistors included in the second sub-driving layer differ by 0 or 1.

39. The display panel of any one of claims 14-38, wherein, The driving circuit layer comprises a plurality of pixel circuits, the plurality of pixel circuits are arranged in multiple rows and multiple columns, each column comprises at least two pixel circuits arranged along a first direction, each row comprises at least two pixel circuits arranged along a second direction, the first direction and the second direction intersect; and, in the first direction and / or the second direction, any two adjacent pixel circuits are symmetrically arranged.

40. The display panel of any one of claims 14-39, wherein, The plurality of light-emitting devices are arranged in multiple rows and multiple columns, each column comprises at least two light-emitting devices arranged along a first direction, each row comprises at least two light-emitting devices arranged along a second direction, the first direction and the second direction intersect; and, the plurality of light-emitting devices coupled to the same gate sub-circuit are located in the same column.

41. The display panel of claim 40, wherein, The gate sub-circuit comprises a plurality of gate branches, the gate branches are coupled with the third node, the fourth node and the first light-emitting control signal terminal, the fourth node is coupled with the light-emitting device, and the fourth nodes coupled with different gate branches are coupled with different light-emitting devices; The display panel further comprises: The first gate driving circuit; The first light-emitting control signal line is coupled with the first gate driving circuit; along the first direction, the plurality of first light-emitting control signal lines are divided into a plurality of first light-emitting control signal line groups, each first light-emitting control signal line group comprises at least two first light-emitting control signal lines arranged adjacently; and the first light-emitting control signal terminals of the plurality of gate branches in a row of pixel circuits are respectively coupled with the plurality of first light-emitting control signal lines in a first light-emitting control signal line group. The plurality of first light-emitting control signal lines in the first light-emitting control signal line group are respectively coupled with the plurality of first gate driving circuits; and along the first direction, the number of first light-emitting control signal lines between the two first light-emitting control signal lines coupled with the same first gate driving circuit in any two adjacent first light-emitting control signal line groups is the same.

42. The display panel of claim 40 or 41, wherein, The plurality of columns of light-emitting devices comprises a first column of light-emitting devices and a second column of light-emitting devices; The light-emitting colors of at least two light-emitting devices in the first column of light-emitting devices are different; and the light-emitting colors of the light-emitting devices in the second column of light-emitting devices are the same.

43. The display panel of claim 42, wherein, The first column of light-emitting devices comprises a plurality of red light-emitting devices and a plurality of blue light-emitting devices, and the plurality of red light-emitting devices and the plurality of blue light-emitting devices are arranged alternately; and the second column of light-emitting devices comprises a plurality of green light-emitting devices. Alternatively, the first column of light-emitting devices comprises a plurality of red light-emitting devices and a plurality of green light-emitting devices, and the plurality of red light-emitting devices and the plurality of green light-emitting devices are arranged alternately; and the second column of light-emitting devices comprises a plurality of blue light-emitting devices.

44. The display panel of any one of claims 40-43, further comprising a pixel defining layer, the pixel defining layer being provided with a plurality of pixel openings, one light-emitting device being located in one pixel opening; and the pixel opening is at least one of a quadrilateral, an ellipse and a circle in shape.

45. The display panel of claim 44, wherein, The light-emitting device comprises a first electrode, a light-emitting part and a second electrode, the first electrode and the second electrode are located on opposite sides of the light-emitting part, and the first electrode is located on a side of the light-emitting part close to the driving circuit layer; The first electrode comprises a main body part and an overlapping part, the pixel opening exposes at least part of the main body part, and the overlapping part is connected with the second electrode of the second transistor through a connection hole.

46. The display panel of claim 45, wherein, The two columns of light-emitting devices adjacent to each other are a first column of light-emitting devices and a second column of light-emitting devices, in the first column of light-emitting devices, along the first direction, the overlapping part is located on a first side of the main body part; in the second column of light-emitting devices, along the first direction, the overlapping part is located on a second side of the main body part; and the first side and the second side are opposite sides of the main body part.

47. The display panel of claim 45 or 46, wherein, The ratio of the area of the main body part to the area of the pixel opening is 0.7-0.

9.

48. The display panel of any one of claims 45-47, wherein, In any direction parallel to the pixel defining layer, the ratio of the size of the connecting hole to the size of the pixel opening is 0.5-0.

9.

49. The display panel of any one of claims 45-48, comprising a plurality of gate lines, the plurality of gate lines comprising at least one of a first light emitting control signal line, a first scan signal line, a second scan signal line, and a reset signal line, and a ratio of a size of the gate line to a size of the pixel opening is 0.5-1.2 along a direction perpendicular to an extension direction of the gate line.

50. A display panel, comprising: a driving circuit layer comprising a plurality of pixel circuits, the pixel circuit comprising a common sub-circuit coupled to a data signal terminal, a first power signal terminal, and a third node; the common sub-circuit configured to generate a driving current signal and transmit the driving current signal to the third node in the light emitting phase; a light emitting device layer disposed on a side of the driving circuit layer; the light emitting device layer comprising a plurality of light emitting devices, the light emitting device coupled to the common sub-circuit, and at least two light emitting devices coupled to the same common sub-circuit; the light emitting device comprising a first electrode, the first electrode comprising a main body part and an overlap part, the overlap part connected to the pixel circuit through a connecting hole; a pixel defining layer disposed on a side of the driving circuit layer; the pixel defining layer provided with a plurality of pixel openings, one light emitting device located in one pixel opening, and the pixel opening exposing at least part of the main body part; in a first direction, the connecting hole and the pixel opening at least partially oppose each other.

51. The display panel of claim 50, wherein, the common sub-circuit comprising: a driving sub-circuit coupled to a first node, a second node, and the third node; the first node coupled to the data signal terminal, and the second node coupled to the first power signal terminal; the driving sub-circuit configured to generate a driving current signal according to voltages of the first node and the third node and transmit the driving current signal to the third node in the light emitting phase.

52. The display panel of claim 50 or 51, wherein, the common sub-circuit further comprising: a reset sub-circuit coupled to the third node, a reset signal terminal, and an initialization signal terminal; the reset sub-circuit configured to transmit an initialization signal received at the initialization signal terminal to the third node in response to a reset signal received at the reset signal terminal in the reset phase.

53. The display panel of any one of claims 50-52, wherein, the common sub-circuit further comprising: a data writing sub-circuit coupled to a first scan signal terminal, the data signal terminal, and the first node; the data writing sub-circuit configured to transmit a data signal received at the data signal terminal to the first node in response to a first scan signal received at the first scan signal terminal in the data writing phase.

54. The display panel of any one of claims 50-53, wherein, the common sub-circuit further comprising: A first energy storage sub-circuit is coupled to the first node and the third node; the first energy storage sub-circuit is configured to, in the light emitting stage, pull up or pull down the voltage of the first node according to the change of the voltage of the third node, so as to maintain the voltage difference between the first node and the third node unchanged.

55. The display panel of any one of claims 50-54, wherein, The common sub-circuit further includes: A first voltage sub-circuit is coupled to the second scan signal terminal, the first voltage signal terminal and the first node; the first voltage sub-circuit is configured to, in the compensation stage, in response to the second scan signal received at the second scan signal terminal, transmit the first voltage signal received at the first voltage signal terminal to the first node.

56. A display device, wherein, The display device is any one of a wearable device, a virtual reality device and an augmented reality device, and the display device includes: The display panel according to any one of claims 14-55; A circuit board connected to the display panel.

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