Array substrate and display device

Abstract

The present disclosure belongs to the technical field of display. Provided are an array substrate and a transparent display device. The array substrate comprises: a transparent substrate, which comprises a display area, the display area comprising a plurality of sub-pixel areas arranged in an array, and a light-transmitting area other than the sub-pixel areas; and a plurality of gate lines, which are located on the transparent substrate, wherein one of the gate lines corresponds to at least one row of the sub-pixel areas, there is at least one group of adjacent first and second gate lines, and in all or part of the display area, the dimension of the light-transmitting area between the first gate line and the second gate line in a column direction is greater than the total dimension occupied by all sub-pixel area rows corresponding to one of the gate lines in the column direction.

Description

Array substrate and display device

[0001] The present application claims priority to the Chinese patent application No. 202410875200.5, filed on July 1, 2024, and entitled "Array substrate and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, in particular to an array substrate and a display device. BACKGROUND

[0003] Recently, transparent displays are widely used in many fields such as advertising, construction, home use, vehicle-mounted (public, personal), etc. There are two methods to realize transparent displays, passive matrix and active matrix. In order to realize high-resolution and high-performance transparent displays, active matrix has become the mainstream.

[0004] In the active matrix type transparent display, generally, low-resistance metal wires are used to form gate lines and data lines, the gate lines and the data lines are perpendicular to each other, and TFT (Thin Film Transistor) and Cst (Storage Capacitance) are formed at each intersection. However, in this design, due to the grid pattern formed by the metal wires on the transparent panel, light will diffract, so that the objects in the space observed through the transparent display are not clear enough.

[0005] SUMMARY

[0006] Based on the background technology, the present disclosure provides an array substrate and a display device.

[0007] In a first aspect, the present disclosure provides an array substrate, comprising:

[0008] a transparent substrate, comprising a display area, the display area comprising a plurality of sub-pixel areas arranged in an array, and a light-transmitting area other than the sub-pixel areas;

[0009] a plurality of gate lines on the transparent substrate, one of the gate lines corresponding to at least one row of the sub-pixel areas;

[0010] wherein there is at least one group of adjacent first gate lines and second gate lines, and in all or part of the display area, the light-transmitting area between the first gate lines and the second gate lines is larger in size in the column direction than the total size of all the sub-pixel area rows corresponding to one of the gate lines in the column direction.

[0011] Exemplarily, in the whole area of the display region, the light-transmitting regions located between the first gate line and the second gate line have a uniform size in the column direction.

[0012] Exemplarily, two adjacent rows of the sub-pixel regions have an inter-row gap; wherein, the first gate line and / or the second gate line further comprises a third gate line in the inter-row gap.

[0013] Exemplarily, the display region comprises a first area and a second area different from the first area;

[0014] In the first area, the size of the light-transmitting regions between the first gate line and the second gate line in the column direction is different from that in the second area.

[0015] Exemplarily, two adjacent rows of the sub-pixel regions have an inter-row gap, and at least one of the first gate line and the second gate line is a target gate line, which is located in different inter-row gaps in the first area and the second area, respectively.

[0016] Exemplarily, the first gate line and the second gate line are located in the same inter-row gap in the first area, and are located in different inter-row gaps in the second area.

[0017] Exemplarily, the target gate line comprises a first section located in the first area, a second section located in the second area, and a third section connecting the first section and the second section;

[0018] The first section and the second section are located in different inter-row gaps, and the third section runs along the arrangement direction of the plurality of sub-pixel regions sharing the target gate line.

[0019] Exemplarily, the first gate line and the second gate line are symmetric about a row direction as a symmetry axis.

[0020] Exemplarily, the display region comprises a plurality of first areas and a plurality of second areas;

[0021] The plurality of first areas and the plurality of second areas are staggered.

[0022] Exemplarily, in the whole or part of the area, the size of the light-transmitting regions between the first gate line and the second gate line in the column direction is consistent with the size of the whole row of sub-pixel regions corresponding to the first gate line and the second gate line in the column direction.

[0023] Exemplarily, sub-pixel regions in the same row emit the same color, and sub-pixel regions in every two adjacent rows emit different colors.

[0024] The plurality of rows of sub-pixel regions emitting different colors share one of the gate lines.

[0025] Exemplarily, the array substrate further comprises:

[0026] The plurality of data lines are arranged orthogonally to the plurality of gate lines.

[0027] The n data lines correspond to sub-pixel regions emitting different colors in the column of sub-pixel regions.

[0028] Exemplarily, sub-pixel regions in the same column emit the same color, and sub-pixel regions in every two adjacent columns emit different colors.

[0029] The one gate line corresponds to one row of sub-pixel regions.

[0030] Exemplarily, the plurality of sub-pixel regions are arranged in a symmetrical polygonal structure on the transparent substrate.

[0031] The polygonal structure comprises at least one of a quadrilateral, a hexagon, and an octagon.

[0032] Exemplarily, the transparent substrate further comprises a non-display region.

[0033] The interval between the first gate line and the second gate line in the non-display region is different from the interval between the first gate line and the second gate line in the display region.

[0034] Exemplarily, in the non-display region, the interval between every two adjacent gate lines of the plurality of gate lines is equal.

[0035] Exemplarily, the plurality of sub-pixel regions have an inter-row gap between two adjacent rows of sub-pixel regions. For two gate lines in the display region, which are located in the same inter-row gap, the two gate lines are located in different film layers.

[0036] Exemplarily, the plurality of gate lines have the same length.

[0037] The second aspect of the present disclosure further provides a transparent display device comprising the array substrate of any one of the first aspect.

[0038] The array substrate provided by the present disclosure comprises a transparent substrate and a plurality of gate lines, wherein the transparent substrate comprises a display area, the display area comprises a plurality of sub-pixel areas arranged in an array and a light-transmitting area between the sub-pixel areas, and one of the gate lines corresponds to at least one row of the sub-pixel areas; wherein there is at least one set of adjacent first gate lines and second gate lines, in all or part of the display area, the first gate lines and the second gate lines are spaced apart by the light-transmitting area, and the size of the spaced-apart light-transmitting area in the column direction is greater than the total size of all the sub-pixel area rows corresponding to one gate line in the column direction. Since in part or all of the area, the size of the light-transmitting area spaced apart between the adjacent first gate lines and the second gate lines is greater than the total size of all the sub-pixel area rows corresponding to one gate line in the column direction, the area of the light-transmitting area between the first gate lines and the second gate lines can be expanded, and since the area of the light-transmitting area is increased, the diffraction effect can be weakened, thereby improving the clarity of observing objects in space through the transparent display.

[0039] The above description is only a summary of the technical solutions of the present disclosure, in order to more clearly understand the technical means of the present disclosure, the content of the specification can be implemented, and in order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure are described below.

[0040] Brief Description of Drawings

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the drawings needed to be used in the embodiments or related technology description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.

[0042] Figure 1 shows a schematic diagram of observing a penguin image through a transparent substrate in the related art;

[0043] Figures 2-7 show schematic diagrams of the top plane of six array substrates in embodiments of the present disclosure;

[0044] Figure 8 shows a schematic diagram of the wiring of the data lines in embodiments of the present disclosure;

[0045] Figure 9 shows a schematic diagram of the top plane of another array substrate in embodiments of the present disclosure;

[0046] Figure 10 shows a schematic diagram of the penguin image observed by the transparent device formed by the array substrate of Example #2 in embodiments of the present disclosure.

[0047] 101, display area; 102, non-display area; 11, sub-pixel area; 12, light transmission area; G, gate line; S, data line; G1, first section; G2, second section; G3, third section; G4, fourth section; G5, fifth section; 1021, first non-display area; 1022, second non-display area.

[0048] DETAILED DESCRIPTION

[0049] To make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0050] In the present specification, "parallel" refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0051] In the present specification, a polygon is not strictly a triangle, a parallelogram, a trapezoid, a pentagon, or a hexagon, and the like, and can be an approximate polygon, and can include some small deformations due to tolerances.

[0052] Referring to FIG. 1, a schematic diagram of observing an object in a space through a transparent display in the related art is shown. As shown in FIG. 1, due to the influence of the meshed metal lines of the transparent display, the image of the object displayed through the transparent display is very blurred and has low clarity.

[0053] In view of this, the present disclosure provides a method for increasing the area of the light transmission area between the metal lines to reduce the diffraction effect caused by the meshed metal lines. Specifically, an array substrate is provided, in which, among a plurality of gate lines distributed on the array substrate, adjacent gate lines are arranged as close as possible to each other, so that the area of the light transmission area between the gate lines is large enough, thereby reducing the degree of meshing, weakening the diffraction effect, and improving the observation clarity.

[0054] It should be noted that the array substrate provided in the present embodiment can be applied to a transparent display of a liquid crystal type, and can also be applied to a transparent display of an OLED (Organic Electroluminescence Display) type.

[0055] Referring to FIG. 2 and FIG. 3, the top view schematic diagrams of the array substrate proposed in the embodiments of the present disclosure are shown, as shown in FIG. 2 and FIG. 3, the array substrate in the embodiments can include:

[0056] a transparent substrate, including a display area 101, the display area 101 including a plurality of sub-pixel areas 11 arranged in an array, and a light-transmitting area 12 between the sub-pixel areas;

[0057] a plurality of gate lines G, located on the transparent substrate, one gate line G corresponding to at least one row of sub-pixel areas 11;

[0058] wherein, there is at least a group of adjacent first gate lines and second gate lines, in all or part of the display area, the first gate line and the second gate line are spaced apart by a light-transmitting area, and the size of the light-transmitting area in the column direction is greater than the total size of all sub-pixel area rows corresponding to one gate line in the column direction.

[0059] In the embodiments, the transparent substrate can be a glass substrate or a substrate of other transparent material. The transparent substrate can include a display area 101 and a non-display area 102, and the display area and the non-display area are adjacent. Wherein, the non-display area can enclose the display area or semi-enclose the display area.

[0060] wherein, in the display area, a plurality of sub-pixel areas arranged in an array, the plurality of sub-pixel areas can be arranged in rows and columns, such as arranged in multiple rows and multiple columns. In some examples, when the plurality of sub-pixel areas are arranged in rows and columns, they can be arranged in different shapes, such as arranged in a rectangular shape, or arranged in other polygonal shapes.

[0061] wherein, the area in the display area other than the sub-pixel area is a light-transmitting area, as shown in FIG. 2, the area in the display area other than the sub-pixel area can be referred to as a light-transmitting area. The light-transmitting area is used to allow light to exit from one side of the transparent substrate to the other side, such as from the back of the transparent substrate to the front of the transparent substrate, so that the object located on the back of the transparent substrate can be observed.

[0062] The one side of the transparent substrate comprises a plurality of gate lines, one gate line corresponds to at least one row of sub-pixel regions. Specifically, a pixel circuit layer can be formed on the transparent substrate, the pixel circuit layer is formed by a transparent electrode and comprises a plurality of pixel circuits, each pixel circuit comprises a thin film transistor TFT, each sub-pixel region corresponds to one thin film transistor, and one gate line can be connected to the gate electrode of the thin film transistor in at least one row of sub-pixel regions. Specifically, as shown in FIG. 2 and FIG. 3, the one side of the transparent substrate further comprises a plurality of data lines S, the data lines are connected to the source electrodes of the thin film transistors, in the case that the array substrate is the substrate of an LCD display, the drain electrode of the thin film transistor can be connected to the pixel electrode, and in the case that the array substrate is the substrate of an OLED display, the drain electrode of the thin film transistor can be connected to the anode in the display substrate. The thin film transistor can be located at the intersection of the gate line and the data line.

[0063] In practice, the voltage signal provided by the gate line can cause the thin film transistor to be cut off or turned on, for example, when the gate line provides a high-level signal, the thin film transistor is turned on, and in the case that the thin film transistor is turned on, the signal input by the data line can be transmitted to the anode or the pixel electrode via the thin film transistor. When the gate line provides a low-level signal, the thin film transistor is cut off, and in the case that the thin film transistor is cut off, the signal input by the data line can not be transmitted to the anode or the pixel electrode.

[0064] It should be noted that the gate line, the data line and the thin film transistor in the embodiments of the present disclosure can be made of transparent materials, for example, the gate line can be made of transparent metal materials or transparent metal oxide materials.

[0065] In some examples, one gate line can correspond to one row of sub-pixel regions, so that the thin film transistors of one row of sub-pixel regions are connected in parallel on the one gate line, as shown in FIG. 2, which shows the case that one gate line corresponds to one row of sub-pixel regions, in this case, the number of gate lines is consistent with the number of rows of sub-pixels. In yet other examples, one gate line can correspond to a plurality of rows of sub-pixel regions, so that the thin film transistors of the plurality of rows of sub-pixel regions share the one gate line, that is, the gate electrodes of the thin film transistors of the plurality of rows of sub-pixel regions are connected in parallel on the one gate line, in this case, the number of gate lines is less than the total number of rows of sub-pixel regions. As shown in FIG. 3, which shows the case that one gate line corresponds to three rows of sub-pixel regions.

[0066] In the present example, the one gate line corresponding to one row of sub-pixel regions means that the one gate line is connected to the gate electrodes of the thin film transistors of the sub-pixel regions located in the same row, and the one gate line corresponding to a plurality of rows of sub-pixel regions means that the one gate line is connected to the gate electrodes of the thin film transistors of the sub-pixel regions located in the plurality of rows.

[0067] In the display panel, each of the sub-pixel regions can correspond to one color of light. In other words, a plurality of sub-pixel regions corresponding to different colors of light and adjacent to each other can form one pixel unit. For example, as shown in FIG. 2, each of two adjacent sub-pixel regions in a row emits light of a different color, such as a red sub-pixel region R, a green sub-pixel region G, and a blue sub-pixel region B. The two adjacent sub-pixel regions R, G, and B form one pixel unit. In this case, when the plurality of sub-pixel regions in one pixel unit are located in the same row, one gate line can correspond to one row of sub-pixel regions. When the plurality of sub-pixel regions in one pixel unit are located in the same column, one gate line can correspond to three rows of sub-pixel regions.

[0068] In some examples, however, one gate line can correspond to one row of sub-pixel regions regardless of whether the plurality of sub-pixel regions in one pixel unit are located in the same row or the same column.

[0069] In order to reduce the density of the grid formed by the gate lines and the data lines, two adjacent gate lines can be arranged closely to each other, so that the two adjacent gate lines that are not arranged closely to each other have a larger light-transmitting region therebetween. For example, as shown in FIGS. 2 and 3, assuming that each of the gate lines has a respective number, two adjacent gate lines having odd numbers and even numbers can be arranged closely to each other, such as being located between the same two rows of sub-pixel regions, so that the size of the light-transmitting region between another group of two adjacent gate lines having odd numbers and even numbers is increased. As shown in FIG. 2, the i+1th gate line and the i+2th gate line are arranged closely to each other, so that the distance between the i+2th gate line and the i+3th gate line is increased, and thus the size of the light-transmitting region between the i+2th gate line and the i+3th gate line is increased.

[0070] In the display panel, the size of the light-transmitting region between the first gate line and the second gate line in the column direction is greater than the total size of all the rows of sub-pixel regions corresponding to one gate line in the column direction. Alternatively, in some display areas, the size of the light-transmitting region between the first gate line and the second gate line in the column direction is greater than the total size of all the rows of sub-pixel regions corresponding to one gate line in the column direction.

[0071] In the display panel, the size of the light-transmitting region between the first gate line and the second gate line in the column direction is greater than the total size of all the rows of sub-pixel regions corresponding to one gate line in the column direction. Alternatively, in some display areas, the size of the light-transmitting region between the first gate line and the second gate line in the column direction is greater than the total size of all the rows of sub-pixel regions corresponding to one gate line in the column direction.

[0072] The size of the light-transmitting area between the first gate line and the second gate line in the column direction can be understood as the size of the light-transmitting area in the direction parallel to the column direction, such as the size d1 in FIG. 2. The total size of all the sub-pixel area rows corresponding to one gate line in the column direction can be understood as the total size of all the sub-pixel area rows corresponding to one gate line in the direction parallel to the column direction, such as the size d2 in FIG. 2.

[0073] In some examples, the distance between the first gate line and the second gate line can not be uniform. For example, the distance between the first gate line and the second gate line is different in different regions of the display area, so that the size of the light-transmitting area between the first gate line and the second gate line in the column direction can be different in different regions of the display area. In this case, the size of the light-transmitting area between the first gate line and the second gate line in the column direction can be greater than the total size of all the sub-pixel area rows corresponding to one gate line in the column direction in different regions of the display area, or the size of the light-transmitting area between the first gate line and the second gate line in the column direction is greater than the total size of all the sub-pixel area rows corresponding to one gate line in the column direction in some regions of the display area, and the size of the light-transmitting area between the first gate line and the second gate line in the column direction is less than the total size of all the sub-pixel area rows corresponding to one gate line in the column direction in the remaining regions of the display area.

[0074] The total size of all the sub-pixel area rows corresponding to one gate line in the column direction can refer to the length of all the sub-pixel area rows corresponding to one gate line in the column direction perpendicular to the row direction. Specifically, the size of the light-transmitting area between the first gate line and the second gate line in the column direction can be greater than the size of all the sub-pixel area rows corresponding to one gate line in the column direction, and less than the size of all the sub-pixel area rows corresponding to two gate lines in the column direction. For example, one gate line corresponds to two rows of sub-pixel areas, so that the size of the light-transmitting area between the first gate line and the second gate line in the column direction can be greater than the size of the two rows of sub-pixel areas in the column direction, and less than the size of four rows of sub-pixel areas in the column direction, such as the total size of three rows of sub-pixel areas in the column direction. For another example, one gate line corresponds to three rows of sub-pixel areas, so that the size of the light-transmitting area between the first gate line and the second gate line in the column direction can be the total size of four rows of sub-pixel areas in the column direction, or the total size of five rows of sub-pixel areas in the column direction.

[0075] Alternatively, the size of the light-transmitting region between the first gate line and the second gate line in the column direction can be equal to the total size of all the sub-pixel region rows corresponding to the two gate lines in the column direction. As shown in FIG. 2, one gate line corresponds to one row of sub-pixel regions, and the size of the light-transmitting region between the first gate line (the (i+2)th gate line) and the second gate line (the (i+3)th gate line) in the column direction can be the total size of two rows of sub-pixel regions in the column direction. For another example, as shown in FIG. 3, one gate line corresponds to three rows of sub-pixel regions, and the size of the light-transmitting region between the first gate line (the (i+2)th gate line) and the second gate line (the (i+3)th gate line) in the column direction can be the total size of six rows of sub-pixel regions in the column direction.

[0076] In some examples, there can be multiple sets of adjacent first gate lines and second gate lines, for example, as shown in FIG. 2, the (i+1)th gate line and the (i+2)th gate line form a set of adjacent first gate line and second gate line, and the (i+3)th gate line and the (i+4)th gate line form a set of adjacent first gate line and second gate line. Among them, the (i+2)th gate line and the (i+3)th gate line are immediately adjacent. In this example, not every two adjacent gate lines are spaced apart by a large size light-transmitting region, and in this example, in the entire display area, the size of the light-transmitting region between the first gate line and the second gate line in the column direction is greater than the total size of all the sub-pixel region rows corresponding to one gate line in the column direction.

[0077] In this example, the adjacent n gate lines can be arranged immediately adjacent, for example, the (i)th gate line, the (i+1)th gate line and the (i+2)th gate line are arranged immediately adjacent, for example, between the same two rows of sub-pixel regions, and the size of the light-transmitting region between the (i+2)th gate line and the (i+3)th gate line is increased. Among them, the (i+2)th gate line and the (i+3)th gate line are the first gate line and the second gate line. Alternatively, the (i)th gate line and the (i+1)th gate line can be arranged immediately adjacent, and the size of the light-transmitting region between the (i+1)th gate line and the (i+2)th gate line is increased, and the (i+2)th gate line and the (i+1)th gate line are the first gate line and the second gate line.

[0078] In yet other examples, every two adjacent gate lines can be the first gate line and the second gate line, that is, the size of the light-transmitting region between every two adjacent gate lines in the column direction, in this example, in some areas of the display area, the size of the light-transmitting region between the first gate line and the second gate line in the column direction is greater than the total size of all the sub-pixel region rows corresponding to one gate line in the column direction, and in other areas, the size of the light-transmitting region between the first gate line and the second gate line in the column direction is less than or equal to the total size of all the sub-pixel region rows corresponding to one gate line in the column direction.

[0079] According to the technical scheme in the embodiment, the size of the light-transmitting area between the first gate line and the second gate line in some or all areas is greater than the total size of the sub-pixel area rows in the column direction corresponding to one gate line, so that the area of the light-transmitting area between the gate lines can be enlarged as a whole, the density of the metal line grid can be reduced, the diffraction effect can be weakened, and the clarity of observing objects in space through the transparent display can be improved.

[0080] In some embodiments, the distance between the first gate line and the second gate line can be uniform, so that the size of the light-transmitting area between the first gate line and the second gate line in the column direction is uniform in the entire display area.

[0081] Please continue to refer to FIGS. 2 and 3, in the entire display area, the first gate line and the second gate line can be wired along a straight line, so that the distance between the first gate line and the second gate line is uniform, in this case, the size d1 of the light-transmitting area between the first gate line and the second gate line in the column direction can be the sum of the size d2 of the sub-pixel area rows in the column direction corresponding to the first gate line and the second gate line.

[0082] For example, as shown in FIG. 2, the gate lines are wired along a straight line on the transparent substrate, the size d1 of the light-transmitting area between the i+2th gate line and the i+3th gate line in the column direction can be the sum of the size d2 of two sub-pixel area rows in the column direction. For another example, as shown in FIG. 3, the size d1 of the light-transmitting area between the i+2th gate line and the i+3th gate line in the column direction can be consistent with the sum of the size d2 of six sub-pixel area rows in the column direction, the consistency can mean approximate consistency.

[0083] When this embodiment is adopted, the wiring difficulty of the gate lines can be simplified, and the density of the metal line grid can be reduced, so that the diffraction effect can be weakened.

[0084] In combination with the above embodiments, in some examples, in addition to the two adjacent gate lines with a relatively large distance in a plurality of gate lines, there can be two gate lines with a very small distance, for example, there is a third gate line adjacent to the first gate line or the second gate line, the distance between the third gate line and the adjacent first gate line or second gate line is less than the size of the sub-pixel area rows in the column direction corresponding to one gate line. Specifically, each two adjacent rows of sub-pixel areas have a row gap, the third gate line and the adjacent first gate line can be located in the same row gap or different row gaps, in the case of being located in different row gaps, the size of the light-transmitting area between the first gate line and the third gate line in the column direction is less than the size of the sub-pixel area rows in the column direction corresponding to one gate line.

[0085] In the embodiment, the row-to-row gap refers to a gap in the column direction between two adjacent row sub-pixel regions. The two adjacent column sub-pixel regions have a column-to-column gap TD in the row direction. As shown in FIG. 3, in an example, the area of the row-to-row gap MD is smaller than the area of the column-to-column gap TD.

[0086] In an example of the embodiment, the first gate line can be included in the row-to-row gap in which the first gate line is located, or the second gate line can be included in the row-to-row gap in which the second gate line is located, or the first gate line can be included in the row-to-row gap in which the first gate line is located and the second gate line can be included in the row-to-row gap in which the second gate line is located. For example, as shown in FIG. 2, in the i th gate line and the i+1 th gate line, the i+2 th gate line is not included in the row-to-row gap in which the i th gate line is located, and the i+2 th gate line is included in the row-to-row gap in which the i+1 th gate line is located. For another example, in the i+2 th gate line and the i+3 th gate line, the i+2 th gate line and the i+3 th gate line are both included in the row-to-row gap in which the i+2 th gate line and the i+3 th gate line are located.

[0087] In the example, the adjacent odd and even gate lines can be routed in the same row-to-row gap, so as to increase the area of the light-transmitting region between the gate lines and reduce the density of the grid.

[0088] In combination with the above embodiment, the first gate line and the second gate line can have different intervals in different regions of the display region. As shown in FIGS. 4-6, three top view schematic diagrams of array substrates are shown, and as shown in FIGS. 4-6, the display region can include a first region 101a and a second region 101b. In the second region, the size of the light-transmitting region between the first gate line and the second gate line in the column direction is different from the size of the light-transmitting region between the first gate line and the second gate line in the column direction in the second region.

[0089] In the embodiment, the size of the light-transmitting region between the first gate line and the second gate line in the column direction can be non-uniform. Specifically, the display region can include a first region and a second region different from the first region, and the interval between the first gate line and the second gate line is different in the first region and the second region. The first region and the second region can be adjacent or not adjacent.

[0090] In some examples of the present embodiment, for each two adjacent gate lines among the plurality of gate lines, the size of the light-transmitting area between the two adjacent gate lines in the partial area of the display area in the column direction can be greater than the total size of the sub-pixel area rows connected by one gate line in the column direction. As shown in FIG. 4 and FIG. 6, the intervals between the i+1th gate line and the i+2th gate line, between the i+2th gate line and the i+3th gate line, and between the i+3th gate line and the i+4th gate line are different between the first area and the second area. The interval between the i+1th gate line and the i+2th gate line in the first area 101a is smaller than the interval in the second area 101b. The interval between the i+2th gate line and the i+3th gate line in the first area 101a is greater than the interval in the second area 101b. In each first area and second area, the size of the light-transmitting area between the two adjacent gate lines in the column direction is 6 sub-pixel area rows in the column direction.

[0091] In some examples of the present embodiment, the plurality of gate lines can be sequentially divided into a plurality of gate line groups, each gate line group including two adjacent gate lines, and different gate line groups do not have repeated gate lines. Thus, in the partial area of the display area, the size of the light-transmitting area between the two adjacent gate lines in the gate line group in the column direction can be greater than the total size of the sub-pixel area rows connected by one gate line in the column direction. As shown in FIG. 5, the intervals between the i+3th gate line and the i+2th gate line are different between the first area and the second area. The interval between the i+2th gate line and the i+3th gate line in the first area 101a is greater than the interval in the second area 101b. In the first area 101a, the size of the light-transmitting area between the i+2th gate line and the i+3th gate line in the column direction is 6 sub-pixel area rows in the column direction.

[0092] In combination with FIG. 4-FIG. 6, in the case where the intervals between the first gate line and the second gate line in the first area and the second area are different, the wiring between the first gate line and the second gate line can be slightly different. For example, assuming that there is an inter-row gap between two adjacent rows of sub-pixel areas, at least one target gate line exists in the first gate line and the second gate line, and the target gate line is located in different inter-row gaps in the first area and the second area, respectively.

[0093] In this example, the first gate line or the second gate line can be located in different inter-row gaps in the first area and the second area, or the first gate line is located in different inter-row gaps in the first area and the second area, and the second gate line is also located in different inter-row gaps in the first area and the second area. For example, the i+1th gate line is located in different inter-row gaps in the first area and the second area, and the i+2th gate line is located in different inter-row gaps in the first area and the second area, as shown in FIGS. 4 and 6; for another example, the i+1th gate line is located in different inter-row gaps in the first area and the second area, and the i+2th gate line is located in the same inter-row gap in the first area and the second area, as shown in FIG. 5.

[0094] In combination with FIGS. 4-6, through different wiring designs, the light transmission area on the array substrate can be divided into multiple light transmission grids by the multiple gate lines and the data lines, wherein the size of the light transmission area between each adjacent two gate lines in the first area or the second area in the column direction can be greater than the size of the sub-pixel area connected by one gate line in the column direction, thereby the multiple light transmission grids can be staggered on the transparent substrate, and the size of the light transmission area in the light transmission grid can be consistent, as shown in FIG. 4.

[0095] In combination with FIGS. 4-6, through different wiring designs, the light transmission area on the array substrate can be divided into multiple light transmission grids by the multiple gate lines and the data lines, wherein the size of the light transmission area between each adjacent two gate lines in the first area or the second area in the column direction can be greater than the size of the sub-pixel area connected by one gate line in the column direction, thereby the multiple light transmission grids can be staggered on the transparent substrate, and the size of the light transmission area in the light transmission grid can be consistent, as shown in FIG. 4.

[0096] In this embodiment, since the target gate line is located in different inter-row gaps in the first area and the second area, the target gate line can be folded and wired on the transparent substrate, and according to the arrangement mode of the first area and the second area, the target gate line can be continuously folded and wired in a U shape, as shown in FIGS. 4 and 5, or the target gate line can be zigzag wired, as shown in FIG. 6.

[0097] Further, in a further embodiment of this example, when the target gate line is located in different inter-row gaps in the first area and the second area, the first gate line and the second gate line are arranged close to each other in the first area or the second area. For example, the first gate line and the second gate line are located in the same inter-row gap in the first area, and the first gate line and the second gate line are located in different inter-row gaps in the second area, so that the first gate line and the second gate line have different distances between them in the first area and the second area.

[0098] Please continue to refer to FIG. 4-6, in order to further reduce the density of the grid, the first and second grid lines can be arranged adjacent to each other in the first region, such as the first and second grid lines being located in the same row gap, while the first and second grid lines are located in different row gaps in the second region, and in the second region, the size of the light transmission area between the first and second grid lines in the column direction is greater than the total size of the row of sub-pixel areas connected by a grid line in the column direction.

[0099] More specifically, in a further example of this example, the target grid line can include a first segment G1 located in the first region, a second segment G2 located in the second region, and a third segment G3 connected between the first segment and the second segment; wherein the first segment and the second segment are located in different row gaps, and the third segment runs along the arrangement direction of the plurality of sub-pixel areas sharing the target grid line.

[0100] In this example, a grid line can connect multiple rows of adjacent sub-pixel areas, that is, be shared by multiple rows of adjacent sub-pixel areas, so that no matter how the plurality of sub-pixels in the multiple rows of sub-pixel areas are arranged, the third segment can run along the arrangement direction of the plurality of sub-pixel areas sharing the target grid line, thereby allowing the target grid line to bend and run on the transparent substrate. The distance between the first segment and the second segment in the column direction can be less than or equal to the total size of the plurality of sub-pixel areas corresponding to the target grid line in the column direction. For example, as shown in FIG. 4-6, the distance between the first segment and the second segment in the column direction can be equal to the total size of the three sub-pixel areas corresponding to the target grid line in the column direction.

[0101] Wherein, for the third segment, the third segment is related to the arrangement direction of the plurality of rows of sub-pixel areas corresponding to the target grid line, specifically, the third segment can be orthogonal to the first segment or the second segment, for example, as shown in FIG. 4-6, the third segment can be orthogonal to the first segment and can be orthogonal to the second segment. More specifically, the third segment can form an angle with the first segment that is not 90 degrees, such as forming an obtuse angle with the first segment and the second segment. For example, referring to FIG. 7, another top view schematic diagram of an array substrate is shown, the angle between the third segment and the first segment is an obtuse angle, such as an obtuse angle of 120 degrees, and the angle between the third segment and the second segment is also an obtuse angle.

[0102] In some examples, the angle between the first segment and the third segment can be the same as the angle between the second segment and the third segment.

[0103] In a further example, the first gate line and the second gate line can both be target gate lines, as shown in FIG. 4, the light-transmissive region on the array substrate can be divided into a plurality of light-transmissive grids by the plurality of gate lines and the plurality of data lines, the plurality of light-transmissive grids can be staggered on the transparent substrate, and the size of the light-transmissive region in the light-transmissive grid can be consistent. In this example, the first gate line and the second gate line can be symmetrical with the row direction as the axis of symmetry. Specifically, every two adjacent gate lines in the plurality of gate lines in the transparent substrate can be symmetrical with the row direction as the axis of symmetry.

[0104] In a further example, for the first region and the second region in the display region, the display region can be divided into a first region and a second region, the first region and the second region are adjacent, and the area of the first region can be different from the area of the second region, for example, as shown in FIG. 6, the area of the first region can be smaller than the area of the second region. Alternatively, the area of the first region can be equal to the area of the second region.

[0105] In a further example, the display region can be divided into a plurality of first regions and a plurality of second regions, wherein the plurality of first regions and the plurality of second regions can be staggered, and because the spacing of the first gate line and the second gate line in the first region and the spacing of the first gate line and the second gate line in the second region are different, the size of the light-transmissive region between the first gate line and the second gate line in the column direction can change in the first region and the second region. For example, as shown in FIG. 4, the size of the light-transmissive region between every two adjacent gate lines in the column direction can change in the first region and the second region, and every two adjacent gate lines are symmetrical in the row direction, thereby forming a plurality of light-transmissive grids, the light-transmissive regions in the plurality of light-transmissive grids have the same area and are staggered on the transparent substrate.

[0106] For another example, as shown in FIG. 5, the size of the light-transmissive region between every two adjacent gate lines in the column direction can change in the first region and the second region, and every two adjacent gate lines are asymmetrical, thereby including a light-transmissive region of a first area and a light-transmissive region of a second area; wherein the light-transmissive region of the first area is distributed in the first region, the light-transmissive region of the second area is distributed in the second region, and the size of the light-transmissive region of the first area in the column direction is greater than the size of the light-transmissive region of the second area in the column direction. The size of the light-transmissive region of the first area in the column direction is the total size of the six sub-pixel regions connected by the two gate lines in the column direction; and the size of the light-transmissive region of the second area in the column direction is the total size of the six sub-pixel regions connected by the one gate line in the column direction. This example can also weaken the diffraction effect and improve the clarity of observing objects in space through the transparent display.

[0107] In combination with the above examples, in all or part of the regions, the size of the light-transmissive region between the first gate line and the second gate line in the column direction is consistent with the size of the total sub-pixel region corresponding to the first gate line and the second gate line in the column direction.

[0108] In this embodiment, as shown in FIG. 2 and FIG. 3, in all regions, the size of the light-transmitting region between the first gate line and the second gate line in the column direction is consistent, and the size of the light-transmitting region between the first gate line and the second gate line in the column direction is consistent with the size of the entire row of sub-pixel regions corresponding to the first gate line and the second gate line in the column direction. In this example, the first gate line and the second gate line are both straight lines.

[0109] In this embodiment, as shown in FIG. 4, FIG. 6 and FIG. 7, in some regions, in the first region, the size of the light-transmitting region between the first gate line and the second gate line in the column direction is consistent, and in the second region, the size of the light-transmitting region between the first gate line and the second gate line in the column direction is consistent; but the size of the light-transmitting region between the first gate line and the second gate line in the first region and the second region in the column direction is different. Among them, in the first region and the second region, for the light-transmitting region with a larger size between the first gate line and the second gate line, the size of the light-transmitting region in the column direction is consistent with the size of the entire row of sub-pixel regions corresponding to the two gate lines in the column direction. For example, as shown in FIG. 4, in the first region, the i+1th gate line and the i+2th gate line are in the same inter-row gap, and in the second region, the size of the light-transmitting region between the i+1th gate line and the i+2th gate line in the column direction is consistent with the size of the entire row of sub-pixel regions corresponding to the two gate lines in the column direction, that is, six sub-pixel regions are spaced apart. For another example, in the first region, the i+2th gate line and the i+3th gate line are spaced apart by six rows of sub-pixel regions, and in the second region, the i+3th gate line and the i+2th gate line are in the same inter-row gap.

[0110] Next, the arrangement of the sub-pixel regions in this embodiment will be described.

[0111] In some embodiments, the plurality of sub-pixel regions are arranged in a grid structure on the transparent substrate.

[0112] Among them, the orthogonal projection of the grid in the grid structure on the transparent substrate is at least one of a quadrilateral, a hexagon, and an octagon.

[0113] As shown in FIG. 4, the plurality of sub-pixel regions are arranged along the row direction and the column direction, which can form a rectangular grid. As shown in FIG. 7, the plurality of sub-pixel regions are arranged with a position offset along the row direction and the column direction, which can form a hexagonal grid.

[0114] Through different arrangements of sub-pixel regions, the area of the light-transmitting region between two adjacent columns of sub-pixel regions can be increased, so that the area of the light-transmitting region in the column direction can be increased while the area of the light-transmitting region in the row direction can also be increased.

[0115] In an arrangement mode A, sub-pixel regions in the same row emit the same color, and sub-pixel regions in every two adjacent rows emit different colors; wherein, sub-pixel regions in multiple adjacent rows emitting different colors share one gate line.

[0116] In this embodiment, the array substrate can be used as an array substrate of an LCD display or an array substrate of an OLED display. In this case, one gate line can correspond to three rows of sub-pixel regions emitting different colors, as shown in FIG. 3. The three rows of sub-pixel regions emitting different colors share one gate line. For example, one gate line is shared by sub-pixel regions R emitting red light, sub-pixel regions G emitting green light, and sub-pixel regions B emitting blue light.

[0117] The arrangement mode of this embodiment can reduce the number of gate lines, so that the number of gate lines is one third of the total number of rows of sub-pixel regions, thereby greatly reducing the wiring area of the gate lines and reducing the degree of meshing.

[0118] Correspondingly, in a further example of this embodiment, each column of sub-pixel regions can share one data line, or each column of sub-pixel regions can share multiple data lines. In a more specific example, one column of sub-pixel regions can correspond to n data lines. Referring to FIG. 8, a schematic diagram of the wiring of data lines of an array substrate is shown. As shown in FIG. 8, the array substrate can also include multiple data lines, which are arranged orthogonally to the gate lines. Sub-pixel regions in the same column correspond to n data lines, and different data lines in the n data lines correspond to sub-pixel regions emitting different colors in the column of sub-pixel regions. As shown in FIG. 8, each column of sub-pixel regions corresponds to three data lines, and the three data lines correspond to sub-pixel regions R emitting red light, sub-pixel regions G emitting green light, and sub-pixel regions B emitting blue light, respectively.

[0119] The orthogonal projection of the n data lines on the transparent substrate can be located within the orthogonal projection of the sub-pixel regions on the transparent substrate, or the orthogonal projection of the n data lines on the transparent substrate can not overlap with the orthogonal projection of the sub-pixel regions on the transparent substrate. Of course, in the case that the orthogonal projection of the n data lines on the transparent substrate can be located within the orthogonal projection of the sub-pixel regions on the transparent substrate, the area of the light transmission region between two adjacent columns of sub-pixel regions can be increased.

[0120] In this example, the number of n data lines is consistent with the number of types of light emitting colors corresponding to one column of sub-pixel regions. For example, if one column of sub-pixel regions includes three types of light emitting colors, n is 3, that is, one column of sub-pixel regions corresponds to 3 data lines. One data line is shared by sub-pixel regions emitting the same color in one column of sub-pixel regions, and different data lines correspond to sub-pixel regions emitting different colors in one column of sub-pixel regions.

[0121] The technical scheme of the embodiment can control the light-emitting color of each sub-pixel area independently by setting the gate lines and the data lines, thereby improving the control accuracy.

[0122] In another arrangement B, the sub-pixel areas in the same column emit the same color, and the sub-pixel areas in each two adjacent columns emit different colors; one gate line corresponds to one row of sub-pixel areas.

[0123] In the embodiment, the array substrate can be used as an array substrate of an LCD display or an array substrate of an OLED display. In this case, one gate line can correspond to one row of sub-pixel areas. As shown in FIG. 2, the sub-pixel areas in the same column emit the same color light, each two adjacent sub-pixel areas in the same row emit different color light, and one row of sub-pixel areas is connected to one gate line. For example, one gate line is shared by the sub-pixel areas R emitting red light, the sub-pixel areas G emitting green light, and the sub-pixel areas B emitting blue light.

[0124] In the embodiment, in addition to the case that two gate lines are located in the same inter-row gap, three or four gate lines can also be located in the same inter-row gap. As shown in FIG. 9, which is a top view of the array substrate in another example, three adjacent gate lines are located in the same inter-row gap. In this case, the two adjacent gate lines can be the i+4th gate line and the i+3th gate line. Compared with the case shown in FIG. 2, in which two gate lines are located in the same inter-row gap, the area of the light-transmitting area between the first gate line and the second gate line can be increased, thereby more effectively reducing the diffraction effect of light and further improving the clarity when observing an object.

[0125] In a further example of the example, each data line of the plurality of data lines can be shared by one column of sub-pixel areas. For example, one data line can be shared by the sub-pixel areas emitting the same color light.

[0126] In some embodiments, the distance between the first gate line and the second gate line in the non-display area is different from the distance between the first gate line and the second gate line in the display area.

[0127] In the embodiment, the distance between the first gate line and the second gate line in the non-display area can be greater than the minimum distance between the first gate line and the second gate line in the display area and less than the maximum distance between the first gate line and the second gate line in the display area. As shown in FIGS. 2 and 3, the distance between the first gate line and the second gate line in the non-display area can be less than the distance between the first gate line and the second gate line in the display area. For example, the distance between the i+2th gate line and the i+3th gate line in the display area is greater than the distance between the i+2th gate line and the i+3th gate line in the non-display area.

[0128] For example, as shown in FIG. 4, the spacing between the first gate line and the second gate line in the non-display area can be between the minimum spacing and the maximum spacing of the first gate line and the second gate line in the display area. For example, the spacing between the i+2th gate line and the i+1th gate line in the non-display area is between the maximum spacing and the minimum spacing in the display area.

[0129] With this wiring mode, when there are two adjacent gate lines in the same row-to-row gap in the plurality of gate lines, the spacing between the non-display areas can be increased, thereby avoiding the problem of short circuit caused by the close distance between the gate lines in the non-display area.

[0130] In a further example of this embodiment, in the non-display area, the spacing between each adjacent two gate lines in the plurality of gate lines is equal. In this example, the entire gate line can be bent and routed on the transparent substrate, so that the spacing between the adjacent two gate lines in the display area and the non-display area is different.

[0131] For example, as shown in FIG. 2, in the non-display area, the spacing between each adjacent two gate lines in the plurality of gate lines is equal, and in the display area, the spacing between the adjacent two gate lines in the plurality of gate lines can include a first spacing and a second spacing; accordingly, the spacing between each adjacent two gate lines in the non-display area is between the first spacing and the second spacing. The first spacing is the spacing between the adjacent first gate line and the third gate line, both of which are in the same row-to-row gap, such as the i+1th gate line and the i+2th gate line, the i+3th gate line and the i+4th gate line, and the i+5th gate line and the i+6th gate line. The second spacing is the spacing between the adjacent first gate line and the second gate line, both of which are in different row-to-row gaps, such as the i+1th gate line and the i+1th gate line, the i+2th gate line and the i+3th gate line, and the i+4th gate line and the i+5th gate line, and the size of the light-transmitting area between them in the column direction is the total size of the two rows of sub-pixel areas in the column direction.

[0132] As shown in FIG. 4, in the non-display area, the distance between each two adjacent gate lines is equal, and in the display area, the distance between the adjacent first gate line and the second gate line can include a first distance and a second distance; accordingly, the distance between each two adjacent gate lines in the non-display area is between the first distance and the second distance. The first distance is the distance when the first gate line and the second gate line are in the same row gap, for example, the i+1th gate line and the i+2th gate line in the first area are in the same row gap; the second distance is the distance when the adjacent first gate line and the second gate line are in different row gaps, for example, the i+1th gate line and the i+2th gate line in the second area are in different row gaps, and the size of the light transmission area between the two gate lines in the column direction is six times the total size of the sub-pixel areas in the column direction.

[0133] In this embodiment, when the distance between each two adjacent gate lines in the non-display area is equal, if the distance between each two adjacent first gate line and second gate line in different regions of the display area is different, in the first non-display area 1021 and the second non-display area 1022 located on the opposite sides of the display area, the fourth segment G4 of a gate line located in the first non-display area is not in the same straight line with the fifth segment G5 located in the second non-display area. For example, when the axis in the column direction is the axis of symmetry, the gate lines in this embodiment are asymmetrically arranged about the axis of symmetry, which can be specifically referred to FIG. 4-7.

[0134] Of course, when the distance between each two adjacent gate lines in the non-display area is equal, if the distance between each two adjacent first gate line and second gate line in different regions of the display area is equal, when the axis in the column direction is the axis of symmetry, the gate lines in this embodiment are symmetrically arranged about the axis of symmetry, which can be specifically referred to FIG. 2 and FIG. 3. This embodiment can reduce the difficulty of the gate line wiring.

[0135] In some embodiments, the wiring lengths of different gate lines in the plurality of gate lines can be equal, so that each two adjacent gate lines in the plurality of gate lines are symmetrically arranged about the row direction as the axis of symmetry, as shown in FIG. 2-4. Each two adjacent gate lines are symmetrically arranged about the row direction as the axis of symmetry, so that the wiring lengths of the gate lines are equal and the wiring manner is symmetrical.

[0136] In some embodiments, for two adjacent gate lines located in the same row gap, the two gate lines can be located in different film layers. Specifically, there is a row gap between two adjacent rows of sub-pixel areas, and for two gate lines located in the same row gap in all or part of the display area, the two gate lines can be located in different film layers.

[0137] In some examples of this embodiment, two adjacent gate lines can be located in the same inter-row gap in the entire display area, as shown in FIGS. 2 and 3. In this case, the adjacent odd and even gate lines are arranged closely, so that the distance between the first and second adjacent gate lines is large. In this case, the two gate lines arranged closely in the same inter-row gap can be located in different film layers. For example, as shown in FIG. 2, the i+1th and i+2th gate lines are located in the same inter-row gap in the entire display area, so that the i+1th and i+2th gate lines can be located in different film layers to avoid short circuit caused by too close distance between the two gate lines. Further, in this example, for two adjacent gate lines not located in the same inter-row gap in the entire display area, the two gate lines can be located in the same film layer. For example, as shown in FIG. 2, the i+1th and i+2th gate lines can be located in different film layers, but the i+2th and i+3th gate lines can be located in the same film layer.

[0138] In some examples of this embodiment, two adjacent gate lines can be located in the same inter-row gap in part of the display area and in different inter-row gaps in other areas. In this case, for each two adjacent gate lines, the two gate lines can be located in different film layers. As shown in FIGS. 4 and 6, the i+1th and i+2th gate lines are located in the same inter-row gap in the first area and in different inter-row gaps in the second area, so that the i+1th and i+2th gate lines can be located in different film layers to avoid short circuit caused by too close distance between the two gate lines; the i+2th and i+3th gate lines are located in different inter-row gaps in the first area and in the same inter-row gap in the second area, so that the i+2th and i+3th gate lines can be located in different film layers.

[0139] In some embodiments, the plurality of sub-pixel regions can form a symmetrical polygon structure on the transparent substrate. For example, as shown in FIG. 4, a rectangular structure can be formed, and for another example, as shown in FIG. 7, a hexagonal structure can be formed. In this case, the plurality of sub-pixel regions are arranged in a wave shape in the column direction, and adjacent two columns of sub-pixel regions are arranged symmetrically in the column direction. When this design is adopted, the distance between adjacent two columns of sub-pixel regions is not uniform, so that the size of the light transmission area between the gate lines in the row direction can be enlarged, thereby further increasing the light transmission area and improving the observation clarity.

[0140] In the following, the array substrate proposed by the present disclosure is exemplarily described in combination with several examples:

[0141] Example #1. Please refer to FIG. 3. The array substrate in this example includes:

[0142] A transparent substrate comprises a display area, the display area comprises a plurality of sub-pixel areas arranged in an array, and a light-transmitting area other than the sub-pixel areas; wherein the sub-pixel areas in the same row emit the same color, and the sub-pixel areas in adjacent two rows emit different colors.

[0143] A plurality of gate lines are located on the transparent substrate, one gate line corresponds to three adjacent rows of sub-pixel areas, and the three rows of sub-pixel areas respectively emit color light, red light and green light.

[0144] A plurality of data lines are orthogonal to the gate lines, and one column of sub-pixel areas corresponds to three data lines, and the arrangement of the data lines is shown in FIG. 8; at the position where the data line and the gate line intersect, a thin film transistor of the sub-pixel area is located, the data line is connected with the source electrode of the thin film transistor, and the gate line is connected with the gate electrode of the thin film transistor.

[0145] The odd gate lines and the even gate lines are arranged in close proximity, so that the odd gate lines and the even gate lines are located in the same row-to-row gap, the plurality of gate lines are divided into a plurality of gate line groups, and the gate line groups do not have repeated gate lines; for example, the i+1th gate line and the i+2th gate line are divided into a gate line group, and the two gate lines in the gate line group are linearly arranged in the same row-to-row gap; the first gate line and the second gate line respectively belonging to different gate line groups and being adjacent in position are separated by six rows of sub-pixel areas, so that the light-transmitting area located between the first gate line and the second gate line has a size in the column direction which is the size of six rows of sub-pixel areas in the column direction.

[0146] The interval distance between the plurality of gate lines located in the non-display area can be the same or different, for example, as shown in FIG. 3, the interval distance between the two gate lines in the gate line group can be smaller than the interval distance between the first gate line and the second gate line in the non-display area.

[0147] In this embodiment, the plurality of sub-pixel areas are arranged in a vertical and horizontal manner.

[0148] Example #2, please refer to FIG. 4, the array substrate in this example comprises:

[0149] A transparent substrate comprises a display area, the display area comprises a plurality of sub-pixel areas arranged in an array, and a light-transmitting area other than the sub-pixel areas; wherein the sub-pixel areas in the same row emit the same color, and the sub-pixel areas in adjacent two rows emit different colors.

[0150] A plurality of gate lines are located on the transparent substrate, one gate line corresponds to three adjacent rows of sub-pixel areas, and the three rows of sub-pixel areas respectively emit color light, red light and green light.

[0151] A plurality of data lines are orthogonal to the gate lines, and one column of sub-pixel areas corresponds to three data lines, and the arrangement of the data lines is shown in FIG. 8; at the position where the data line and the gate line intersect, a thin film transistor of the sub-pixel area is located, the data line is connected with the source electrode of the thin film transistor, and the gate line is connected with the gate electrode of the thin film transistor.

[0152] The display region includes a plurality of first regions and a plurality of second regions, the plurality of first regions and the plurality of second regions are staggered, and the spacing between each two adjacent gate lines is different in the first region and the second region; wherein the adjacent first gate line and the second gate line are in the same interline gap in the first region or the second region, and are in different interline gaps in the other region, and the spacing therebetween is the spacing of six rows of sub-pixel regions. In this example, each two adjacent gate lines are symmetric about the symmetry axis in the row direction, so that the entire display region can be divided into a plurality of light transmission grids by a plurality of gate lines, and the size of each light transmission grid in the column direction is the total size of six rows of sub-pixel regions in the column direction.

[0153] In the non-display region, the spacing between each two adjacent gate lines is the same.

[0154] Example #3, please refer to FIG. 7, which is different from example #2, the spacing between the adjacent two columns of sub-pixel regions changes regularly, and a plurality of sub-pixel regions form a hexagon; and each gate line includes a first section in the first region, a second section in the second region, and a third section connecting the first section and the second section, the third section runs along the arrangement direction of the three rows of sub-pixel regions corresponding to the gate line.

[0155] The array substrate of the above-mentioned embodiment, because in part or all regions, the size of the light transmission region between the adjacent two gate lines is greater than the total size of the column direction occupied by all the rows of sub-pixel regions corresponding to a gate line, thereby the area of the light transmission region between the first gate line and the second gate line can be expanded, and because the area of the light transmission region is increased, the diffraction effect can be weakened, thereby improving the clarity of observing objects in space through the transparent display.

[0156] Based on the same inventive concept, the present disclosure also provides a transparent display device, which includes the array substrate in any of the above-mentioned embodiments. Wherein the transparent display device can be an LCD device, in this case, it can also include a cell substrate corresponding to the array substrate, and a liquid crystal between the array substrate and the cell substrate, wherein the cell substrate, the liquid crystal and the array substrate are all made of transparent materials. Wherein the transparent display device can also be an OLED display device, in this case, an organic light-emitting layer can be formed on one side of the array substrate, and the organic light-emitting layer can be in a transparent state in an unpowered state.

[0157] For example, a transparent display device is formed by using the array substrate of example #2 described above, and the penguin image shown in FIG. 1 is observed through the transparent display device, and the observed penguin image is shown in FIG. 10, which has significantly improved clarity compared with FIG. 1.

[0158] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0159] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0160] The above provides a detailed description of an array substrate and a transparent display device provided by this disclosure. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

[0161] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0162] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

[0163] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0164] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosure can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0165] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word 'comprising' does not exclude the presence of elements or steps other than those listed in a claim. The word 'a' or 'an' preceding an element does not exclude the presence of a plurality of such elements. The disclosure can be implemented by means of both hardware and software, and any combination thereof. In a unitary claim, several devices, apparatuses or means can be listed, comprising means for carrying out a certain task. The use of the term'means' in a claim is intended to refer to a combination of means for performing a task, even if such means are not explicitly recited in the claim. The word 'first','second', 'third', etc. do not imply any order. The terms 'first','second', 'third', etc. are to be interpreted according to the context in which they are used.

[0166] It has to be noted that the above-mentioned embodiments illustrate rather than limit the application, since various modifications are possible within the scope of the appended claims. As such, the particular embodiments provided are meant to be illustrative only and not meant to be limiting as to the scope of the disclosure.

Claims

1. An array substrate, characterized by, The array substrate comprises: a transparent substrate comprising a display area, the display area comprising a plurality of sub-pixel areas arranged in an array and light-transmitting areas between the sub-pixel areas; a plurality of gate lines on the transparent substrate, one of the gate lines corresponding to at least one row of the sub-pixel areas; wherein at least one set of adjacent first gate lines and second gate lines exist, and in all or part of the display area, the light-transmitting areas between the first gate lines and the second gate lines have a size in the column direction that is greater than the total size of all the sub-pixel area rows corresponding to one of the gate lines in the column direction.

2. The array substrate of claim 1, wherein, In all of the display area, the light-transmitting areas between the first gate lines and the second gate lines have a uniform size in the column direction.

3. The array substrate of claim 2, wherein, Adjacent two rows of the sub-pixel areas have an inter-row gap; wherein the first gate line and / or the second gate line further comprises a third gate line in the inter-row gap.

4. The array substrate of claim 1, wherein, The display area comprises a first region and a second region different from the first region; wherein in the first region, the size of the light-transmitting areas between the first gate lines and the second gate lines in the column direction is different from the size of the light-transmitting areas between the first gate lines and the second gate lines in the column direction in the second region.

5. The array substrate of claim 4, wherein, Adjacent two rows of the sub-pixel areas have an inter-row gap, and at least one target gate line exists among the first gate lines and the second gate lines, the target gate line being located in different inter-row gaps in the first region and the second region, respectively.

6. The array substrate of claim 5, wherein, In the first region, the first gate line and the second gate line are located in the same inter-row gap, and in the second region, the first gate line and the second gate line are located in different inter-row gaps.

7. The array substrate of claim 5, wherein, The target gate line comprises a first section located in the first region, a second section located in the second region, and a third section connected between the first section and the second section; wherein the first section and the second section are located in different inter-row gaps, and the third section runs along the arrangement direction of the plurality of sub-pixel areas sharing the target gate line.

8. The array substrate of claim 4, wherein, The first gate line and the second gate line are symmetric about a row direction as a symmetry axis.

9. The array substrate according to any one of claims 4-8, wherein, The array substrate comprises a plurality of the first regions and a plurality of the second regions; wherein the plurality of the first regions and the plurality of the second regions are arranged alternately.

10. The array substrate according to any one of claims 1-8, wherein, In all or part of the regions, the size of the light-transmitting areas between the first gate lines and the second gate lines in the column direction is consistent with the size of all the sub-pixel area rows corresponding to the first gate lines and the second gate lines in the column direction.

11. The array substrate of claim 1, wherein, Sub-pixel areas in the same row emit the same color, and sub-pixel areas in each adjacent two rows emit different colors; wherein adjacent and different-color-emitting rows of the sub-pixel areas share one of the gate lines.

12. The array substrate of claim 11, wherein, The array substrate further comprises: a plurality of data lines arranged orthogonally to the plurality of gate lines; wherein sub-pixel areas in the same column correspond to n data lines, and different data lines in the n data lines correspond to sub-pixel areas of different light-emitting colors in the column of sub-pixel areas.

13. The array substrate of claim 1, wherein, Sub-pixel areas in the same column emit the same color, and sub-pixel areas in each adjacent two columns emit different colors; One of the gate lines corresponds to one row of the sub-pixel regions.

14. The array substrate of claim 1, wherein, The plurality of sub-pixel regions are arranged in a grid structure on the transparent substrate. A grid in the grid structure has a projection on the transparent substrate which is at least one of a quadrilateral, a hexagon, and an octagon.

15. The array substrate of claim 1, wherein, The transparent substrate further comprises a non-display region. In the non-display region, a distance between the first gate line and the second gate line is different from a distance between the first gate line and the second gate line in the display region.

16. The array substrate of claim 16, wherein, In the non-display region, a distance between each adjacent two of the plurality of gate lines is equal.

17. The array substrate according to any one of claims 1 to 8 and any one of claims 11 to 16, wherein, Adjacent two rows of the sub-pixel regions have a row gap, and two gate lines in the display region located in the same row gap are located in different film layers, respectively.

18. The array substrate according to any one of claims 1 to 8 and any one of claims 11 to 16, wherein, The plurality of gate lines have the same length.

19. A transparent display device, characterized by An array substrate as claimed in any one of claims 1-18. An array substrate as claimed in any one of claims 1-18.

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