Annealing method and annealing apparatus for cadmium telluride series semiconductor crystals

Abstract

The present application provides an annealing method and an annealing apparatus for cadmium telluride series semiconductor crystals, as well as a cadmium telluride series semiconductor crystal after annealing. The annealing method comprises: on the basis of a cadmium-containing chloride and / or an indium-containing chloride, preparing a molten-state annealing agent; and using the molten-state annealing agent to anneal a cadmium telluride series semiconductor crystal. In the present application, the molten-state annealing agent prepared from the cadmium-containing chloride and / or an indium-containing chloride is used for annealing, which can, during annealing, achieve Cd vacancy compensation and In element doping for the cadmium telluride series semiconductor crystal, thereby significantly improving the crystal quality uniformity, resistivity and carrier transport characteristics, and also reducing annealing time consumption, avoiding surface damage to the crystal, improving efficiency, and reducing energy consumption.

Description

Annealing method and annealing device for cadmium telluride series semiconductor crystal TECHNICAL FIELD

[0001] The present application relates to cadmium telluride series semiconductor crystals, in particular, to an annealing method and an annealing device for cadmium telluride series semiconductor crystals, and an annealed cadmium telluride series semiconductor crystal. BACKGROUND

[0002] The cadmium telluride series semiconductor crystal has high average atomic number, large band gap, high resistivity, excellent carrier transport performance, and the like, and thus becomes the most ideal material for constructing a room temperature nuclear radiation detector. Among them, cadmium zinc telluride (Cd 1-x Zn x Te, CZT) crystal is considered to be one of the most promising room temperature nuclear radiation semiconductor detector materials to date. However, the crystal of this type of material has a high melting point, low thermal conductivity, strong ionic bond characteristics, low stacking fault energy, and is prone to form secondary phases such as inclusion phases, precipitated phases, and structural defects such as dislocations and twins. In addition, the segregation of the doping components such as Zn and the high vapor pressure of Cd element also cause vacancies, which result in non-uniformity of the crystal composition. These defects can capture or scatter carriers, affecting the carrier lifetime, mobility, and other electrical properties, thereby seriously affecting the X-ray and γ-ray detection performance of the device.

[0003] Therefore, it is necessary to take necessary processing technology to improve the performance of the grown crystal, which is usually performed at a high temperature (300-1240°C), and to introduce a high-concentration, low-saturation-vapor-pressure, non-corrosive annealing medium into a sealed container to reduce or even eliminate various defects caused by growth.

[0004] At present, the mainstream method for annealing and modifying the cadmium telluride series semiconductor crystal is a gas phase method, and the annealing atmosphere used is an inert gas (Ar, He, H2, D2, etc.), and the annealing agent includes a Cd metal source, a Cd / Zn metal alloy, a Te source, and the like, among which the Cd metal source is mostly used as the annealing agent.

[0005] CN102168313A provides a two-step gas phase annealing method for Cd 1-x Zn x Te crystal, which uses non-metallic Te and metallic alloy Cd / Zn as annealing sources in sequence, and achieves the effects of improving the resistivity of the crystal and the energy resolution of the detector, eliminating inclusion phases, and improving the carrier transport performance. However, the annealing time is as long as 2400h, which greatly reduces the production efficiency and increases the production energy consumption.

[0006] CN106192014A discloses a moving cycle annealing modification method of CdZnTe crystal, using metal Cd as annealing agent, to solve the technical problem of poor effect of eliminating small inclusions below 10 pm in existing annealing method of CdZnTe crystal. It does not mention the changes in carrier mobility-lifetime product, resistivity, etc.

[0007] CN114737256A discloses a Cd 1-x Zn x Te crystal annealing method under Cd saturated vapor atmosphere, which improves the uniformity of the crystal by eliminating Cd vacancies. The annealing process is to make CZT more suitable as a substrate for growing tellurium cadmium mercury material, and there is no mention of CZT for radiation detection.

[0008] US8268663B2 discloses a method of annealing Cd 1-x Zn x Te wafer in a hydrogen or deuterium gas atmosphere and a Te vapor atmosphere, which increases the carrier mobility-lifetime product (μτ) by 2-5 times. However, the resistivity of the wafer decreases by 2-5 times after annealing, which is not conducive to the application of CZT material in radiation detection.

[0009] JP6004601B2 discloses a method of annealing II-VI semiconductor materials in an open annealing container under inert gas conditions to remove precipitated phase and inclusion phase impurities, which can effectively remove secondary phase defects, but does not mention the performance improvement of semiconductor materials.

[0010] Another type of liquid phase annealing is less used. CN115161773A discloses a method of liquid phase annealing using an annealing agent containing Cd element, aqueous solution of cadmium chloride (or cadmium nitrate, cadmium acetate, cadmium sulfate, cadmium sulfide) as annealing agent, annealing container is a stainless steel shell with polytetrafluoroethylene lining container, wafer is completely immersed in the solution, the container is sealed and put into a muffle furnace for annealing, the annealing temperature is 80℃, and the time is 20-30h, the resistivity of Cd 1-x Zn x Te wafer is increased from 2.35x10 7 Ω·cm to 1.11x10 9 Ω·cm. The annealing agent contains water and the annealing temperature is low, resulting in poor annealing effect and room for improvement in resistivity.

[0011] CN1186484C discloses a gas-liquid combined annealing method. A metal liquid with atomic percentage of Cd:Zn=100:1 is used as liquid phase annealing medium and gas phase annealing source, and Cd 1-x Zn xThe Te wafer is annealed. The composition distribution of the wafer is made more uniform, and the resistivity is raised from 5.74*10 8 Ω*cm to 1.29*10 11 Ω*cm. However, under high temperature, Cd metal is unstable and easy to sublimate, which leads to a large increase in vapor pressure in the crucible, greater operation risk, long annealing time, easy damage to the wafer surface, high energy consumption, and low efficiency.

[0012] In the existing annealing modification method of cadmium telluride series semiconductor crystals, there are problems such as long annealing time, easy damage to the crystal surface, insufficient improvement of the performance of the crystal, inability to balance the resistivity and carrier mobility-lifetime product, high energy consumption, and low efficiency, which limits the application of the crystal in the detector level. SUMMARY

[0013] To solve the above technical problems, the first aspect of the present application provides an annealing method for cadmium telluride series semiconductor crystals. The annealing method comprises the following steps:

[0014] The first step (S11) is to prepare an annealing agent in a molten state based on a cadmium-containing chloride and / or an indium-containing chloride; and

[0015] The second step (S12) is to anneal a cadmium telluride series semiconductor crystal using the annealing agent in a molten state.

[0016] In some embodiments of the present application, the first step (S11) comprises:

[0017] The annealing agent in a molten state is prepared based on a powder mixture of CdCl2 and InCl2, wherein the content ratio of CdCl2 and InCl2 in the powder mixture of CdCl2 and InCl2 is 100:(1-5) in terms of the atomic ratio of Cd and In.

[0018] In some embodiments of the present application, the first step (S11) comprises:

[0019] After the powder mixture of CdCl2 and InCl2 is heated to a first temperature, the powder mixture of CdCl2 and InCl2 is melted into a mixed melt of CdCl2 and InCl2 by heat preservation at the first temperature and for a first time length, wherein the first temperature is not more than 500°C, and the first time length is greater than 1h.

[0020] In some embodiments of the present application, the first temperature is 400-500°C.

[0021] In some embodiments of the present application, the first time length is 5-10h.

[0022] In some embodiments of the present application, the second step (S12) comprises:

[0023] warming up the CdTe-based semiconductor crystal to a second temperature, wherein the second temperature is greater than or equal to the first temperature; and

[0024] immersing the warmed-up CdTe-based semiconductor crystal in the mixed melt of CdCl2and InCl2, warming up the melt temperature to the second temperature, and then keeping the temperature at the second temperature for a second time duration, wherein the second time duration is greater than 5 h.

[0025] In some embodiments of the present application, the second temperature is 500-600 °C.

[0026] In some embodiments of the present application, the second time duration is 20-40 h.

[0027] In some embodiments of the present application, in the first step (S11), the warming-up rate of the powder mixture of CdCl2and InCl2to the first temperature is 50-70 °C / h.

[0028] In some embodiments of the present application, in the second step (S12), the warming-up rate of the CdTe-based semiconductor crystal to the second temperature is 50-70 °C / h.

[0029] In some embodiments of the present application, after the second step (S12), the annealing method further comprises:

[0030] separating the CdTe-based semiconductor crystal from the mixed melt of CdCl2and InCl2, and cooling the CdTe-based semiconductor crystal to room temperature.

[0031] In some embodiments of the present application, the step of cooling the CdTe-based semiconductor crystal to room temperature comprises: first cooling the CdTe-based semiconductor crystal to a third temperature at a rate of 25-35 °C / h, and then cooling the CdTe-based semiconductor crystal to room temperature at a rate of 45-55 °C / h.

[0032] In some embodiments of the present application, the third temperature is 150-300 °C.

[0033] In some embodiments of the present application, before the first step (S11), the annealing method further comprises:

[0034] a first pre-treatment step (S21): placing the Cd-containing chloride and / or In-containing chloride and the CdTe-based semiconductor crystal into a crucible, and removing oxygen attached to the surface of the crucible and the CdTe-based semiconductor crystal;

[0035] a second pre-treatment step (S22) of evacuating the pressure of the crucible to 10 -2 Pa~10 -6 Paand sealing the crucible.

[0036] In some embodiments of the present application, the first pre-treatment step (S21) comprises removing the oxygen by means of vacuum evacuation and inert atmosphere backfilling.

[0037] In some embodiments of the present application, the first step (S11) comprises a melt annealant step (S23) of:

[0038] In a state where the crucible is kept at a first position, an annealant in a molten state is prepared based on a cadmium-containing chloride and / or an indium-containing chloride, wherein in the first position, the cadmium telluride series semiconductor crystal is separated from the cadmium-containing chloride and / or the indium-containing chloride or the annealant in a molten state;

[0039] The second step (S12) comprises a crystal soaking step (S24) of:

[0040] The crucible is rotated from the first position to a second position, and in a state where the crucible is kept at the second position, the cadmium telluride series semiconductor crystal is annealed by the annealant in a molten state, wherein in the second position, the cadmium telluride series semiconductor crystal is soaked in the annealant in a molten state.

[0041] In some embodiments of the present application, the cadmium telluride series semiconductor crystal comprises a wafer and / or a bar.

[0042] A second aspect of the present application provides an annealing device for a cadmium telluride series semiconductor crystal, comprising:

[0043] a crucible having a first region for containing a cadmium-containing chloride and / or an indium-containing chloride and a second region for containing a cadmium telluride series semiconductor crystal;

[0044] a heating furnace comprising a furnace body for containing the crucible and a heating device, wherein the heating device is used for heating the crucible; and

[0045] a position adjusting device connected to the heating furnace, used for adjusting the position of the crucible contained in the furnace body after the cadmium-containing chloride and / or the indium-containing chloride is heated to be an annealant in a molten state, so as to soak the cadmium telluride series semiconductor crystal in the annealant in a molten state, thereby annealing the cadmium telluride series semiconductor crystal by the annealant in a molten state.

[0046] In some embodiments of the present application, the position adjusting device comprises:

[0047] a rotating shaft connected to the furnace body; and

[0048] a motor connected to the rotating shaft,

[0049] Under the action of the motor, the rotating shaft can rotate the furnace body, thereby driving the crucible to rotate, so as to immerse the cadmium telluride series semiconductor crystal in the annealing agent in the molten state, thereby annealing the cadmium telluride series semiconductor crystal by using the annealing agent in the molten state.

[0050] In some embodiments of the present application, the position of the crucible comprises a first position and a second position, wherein in the first position, the second zone is located above the first zone, and the cadmium telluride series semiconductor crystal is separated from the cadmium-containing chloride and / or indium-containing chloride or the annealing agent in the molten state; in the second position, the second zone is located below the first zone, and the cadmium telluride series semiconductor crystal is immersed in the annealing agent in the molten state.

[0051] Optionally, the rotating angle of the crucible when rotating from the first position to the second position or from the second position to the first position is 120°-180°.

[0052] In some embodiments of the present application, the annealing device further comprises a clamp, wherein the clamp has a groove for fixing the cadmium telluride series semiconductor crystal; and

[0053] a clamping groove arranged in the second zone of the crucible for fixing the clamp.

[0054] Optionally, the clamp has one or more groove groups, and each groove group is provided with a plurality of grooves.

[0055] The design aims to facilitate batch annealing of cadmium telluride series semiconductor crystals. The corresponding crystal clamp and crucible can be designed according to the size and processing amount of the crystal, so that the annealing is not limited by the size and quantity of the crystal, greatly improving the production efficiency and controlling the production cost.

[0056] In some embodiments of the present application, the crucible comprises a crucible cap and a crucible body, the crucible cap comprises a crucible mouth and a connecting part for connecting with the crucible body; the crucible body comprises an open end and a containing body, the containing body comprises the first zone and the second zone, and a second protrusion is formed on the inner wall of the second zone. The connecting part of the crucible cap can extend into the crucible body, and the inner wall of the open end of the crucible body is connected together by high-temperature sintering to form a sintering area, and a first protrusion is formed on one end of the sintering area close to the containing body, the first protrusion and the second protrusion constitute the clamping groove for fixing the clamp.

[0057] The length of the sintering area is 10-20 mm, and the sintering area has a spacing of ≥30 mm with the groove provided in the clamp. By providing the spacing, the high temperature during sintering can be avoided to damage the crystal.

[0058] In some embodiments of the present application, the furnace body comprises a first temperature zone and a second temperature zone, and the heating device comprises a first heating element provided corresponding to the first temperature zone and a second heating element provided corresponding to the second temperature zone, wherein the first heating element in the first temperature zone is used for heating the first zone, and the second heating element in the second temperature zone is used for heating the second zone.

[0059] Optionally, the first heating element and the second heating element can be controlled individually.

[0060] The third aspect of the present application provides an annealed cadmium telluride series semiconductor crystal, which is prepared by any of the above-mentioned annealing methods or by any of the above-mentioned annealing devices, wherein the annealed cadmium telluride series semiconductor crystal is doped with In element.

[0061] In some embodiments of the present application, the annealed cadmium telluride series semiconductor crystal comprises a Te-In chemical bond.

[0062] In some embodiments of the present application, the resistivity of the annealed cadmium telluride series semiconductor crystal is ≥5×10 10 Ω·cm, and the product of carrier mobility and lifetime is ≥1×10 -3 cm 2 / V.

[0063] In some embodiments of the present application, the cadmium telluride series semiconductor crystal comprises CdTe, Cd 1-x Zn x Te or a material doped and modified by lanthanide, first group element, second group element, third group element, seventh group element, wherein 0

[0064] The application uses the cadmium-containing chloride and / or indium-containing chloride to prepare the annealing agent in a molten state for annealing, which can realize Cd vacancy compensation and In element doping of the cadmium telluride series semiconductor crystal during annealing, so as to significantly improve the crystal quality uniformity, resistivity and carrier transport characteristics, reduce the annealing time, avoid damage to the crystal surface, improve the efficiency and reduce the energy consumption.

[0065] The annealing device provided by the application is simple, and when used in cooperation with the annealing method provided by the application, a crystal with very good performance can be prepared.

[0066] Additional aspects and advantages of the application will be described in part below, will become apparent from the following description, or will be learned by practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0067] The embodiments of the application will be described in detail below with reference to the accompanying drawings. Here, the accompanying drawings that form a part of the application are used to provide further understanding of the application. The schematic embodiments of the application and the descriptions thereof are used to explain the application and do not constitute an improper limitation on the application.

[0068] Fig. 1 is an annealing process flow chart of a cadmium telluride series semiconductor crystal provided by an embodiment of the application;

[0069] Fig. 2 is an annealing process flow chart of a cadmium telluride series semiconductor crystal provided by another embodiment of the application;

[0070] Fig. 3 is a cross-sectional view of an annealing device provided by an embodiment of the application;

[0071] Fig. 4 is a cross-sectional view of a crucible provided by an embodiment of the application;

[0072] Fig. 5 is a cross-sectional view of a crucible provided by another embodiment of the application;

[0073] Fig. 6 is a cross-sectional view showing the position structure of a sintering area of a crucible and a clamp provided by still another embodiment of the application. DETAILED DESCRIPTION

[0074] In the following, only certain exemplary embodiments are simply described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the application. Therefore, the drawings and the description are considered to be exemplary in nature rather than limiting.

[0075] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0076] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or connections that allow for communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0077] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0078] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0079] The preferred embodiments of the present application are described below in conjunction with the accompanying drawings, in which it is understood that the preferred embodiments described below are merely for the purpose of illustrating and explaining the present application and are not intended to limit the present application.

[0080] FIG. 1 shows an annealing method of a cadmium telluride series semiconductor crystal according to an embodiment of the present application, which comprises the following steps S11 and S12.

[0081] The first step S11 is to prepare an annealing agent in a molten state based on a cadmium-containing chloride and / or an indium-containing chloride.

[0082] The first step S11 is to prepare an annealing agent in a molten state based on a cadmium-containing chloride and / or an indium-containing chloride. Compared with the metal Cd element in the prior art, the cadmium-containing chloride and / or the indium-containing chloride used as the annealing source in the present application is not easy to be oxidized, and the risk of oxidation of the metal element can be avoided, thereby preventing the adverse effects of oxygen on the performance of the cadmium telluride semiconductor crystal. Moreover, the chlorine element generally does not dope into the crystal, and even if it dopes into the crystal due to uncontrollable reasons, the trace doping is beneficial to the improvement of the resistivity of the cadmium telluride semiconductor crystal, thereby ensuring the improvement of the performance of the crystal. Moreover, the cadmium-containing or indium-containing chloride is more stable and is not easy to sublimate, thereby avoiding the risk of cracking of the crucible caused by the excessive saturated vapor pressure of the sublimation of the metal Cd element at high temperature, and improving the safety of the annealing process.

[0083] In addition, the Cd element can compensate for the Cd vacancy defects caused by the crystal growth process, thereby achieving the effect of improving the resistivity of the crystal. The addition of the In element can effectively compensate for the problem of uneven composition of the cadmium telluride series semiconductor crystal caused by the segregation of the Zn element, and the In element can replace a small amount of Cd elements and Cd vacancies to form In doping, and the In element can form a Te-In chemical bond with the Te element in the cadmium telluride series semiconductor crystal, not only consuming the Te inclusions, but also improving the resistivity, carrier concentration, and carrier mobility lifetime product of the crystal, thereby improving the responsivity and response speed of the detector.

[0084] Moreover, the Cd element and the In element themselves have high energy in the molten state, and are more likely to interact with the cadmium telluride series semiconductor crystal, thereby deeply diffusing in the crystal and improving the efficiency of the annealing heat treatment, thereby overcoming the problems of long time consumption, high energy consumption, and low efficiency caused by the insufficient contact between the annealing agent and the crystal in the gas phase annealing. Moreover, the liquid metal element in the prior art is easy to cause damage (etching) to the surface of the crystal, and the chloride in the molten state does not damage the surface of the crystal, and is safer to use.

[0085] Optionally, the cadmium-containing chloride can be CdCl2, and the indium-containing chloride can be InCl2, so as to avoid introducing more impurities. Further optionally, the cadmium-containing chloride and / or the indium-containing chloride is a powder mixture of CdCl2 and InCl2. In this case, the first step S11 can be: preparing the annealing agent in a molten state based on the powder mixture of CdCl2 and InCl2.

[0086] In the crystal growth process, it is very difficult to dope In elements because the Cd vapor pressure inside the crucible is too large. In the present application, during the annealing process of the mixed melt of CdCl2 and InCl2, CdCl2 does not form a large saturated vapor pressure, so that the doping of In elements is relatively easy.

[0087] Moreover, the elemental metal Cd has a very high vapor pressure at high temperatures, which can easily cause the crucible to burst, and the danger is relatively high. The use of CdCl2 as the annealing agent can well avoid this problem. In addition, InCl2 has a low melting point of about 262°C, and after mixing with CdCl2 (melting point of about 568°C), the melting point of the mixture can be reduced to within 500°C, which also has the effect of reducing the annealing temperature.

[0088] Optionally, the content ratio of CdCl2 and InCl2 in the powder mixture of CdCl2 and InCl2 is 100:(1-5) in terms of the atomic ratio of Cd and In. Under this ratio, Cd vacancy compensation and In element doping can be achieved at the same time, which can significantly improve the crystal quality uniformity, resistivity and carrier transport properties. In some specific embodiments, the content ratio of CdCl2 and InCl2 in terms of the atomic ratio of Cd and In can be 100:1, 100:1.5, 100:2, 100:2.5, 100:3, 100:3.5, 100:4, 100:4.5 or 100:5.

[0089] Optionally, the first step S11 specifically comprises: heating the powder mixture of CdCl2 and InCl2 to a first temperature, and then performing heat preservation at the first temperature and for a first time length, so that the powder mixture of CdCl2 and InCl2 is melted into a mixed melt of CdCl2 and InCl2.

[0090] Optionally, the first temperature can be no more than 500°C, and further optionally, the first temperature is 400-500°C. The melting point of the powder mixture of CdCl2 and InCl2 is about 500°C, so as to avoid overheating and sublimation of the melt. The above first temperature can ensure the melting of CdCl2 and InCl2, and will not cause sublimation of CdCl2 and InCl2. In some specific embodiments, the first temperature can be 400°C, 410°C, 420°C, 430°C, 440°C, 450°C, 460°C, 470°C, 480°C, 490°C or 500°C.

[0091] The first time period can be greater than 1 hour, and further optionally, the first time period is 5-10 hours. In this time period, CdCl2and InCl2can be completely melted, and time is not wasted. In some specific embodiments, the first time period can be 5 hours, 5.5 hours, 6 hours, 6.5 hours, 7 hours, 7.5 hours, 8 hours, 8.5 hours, 9 hours, 9.5 hours, or 10 hours.

[0092] Optionally, the heating rate of the powder mixture of CdCl2and InCl2to the first temperature is 50-70 °C / h. A faster heating rate can enable the powder mixture of CdCl2and InCl2to be quickly melted. In some specific embodiments, the heating rate can be 50 °C / h, 52 °C / h, 54 °C / h, 56 °C / h, 58 °C / h, 60 °C / h, 62 °C / h, 64 °C / h, 66 °C / h, 68 °C / h, or 70 °C / h.

[0093] After the above operation, the powder mixture of CdCl2and InCl2can be completely melted into a uniform melt.

[0094] The second step S12 is annealing the cadmium telluride series semiconductor crystal with the annealing agent in a molten state.

[0095] Optionally, the second step S12 first heats the cadmium telluride series semiconductor crystal, and then immerses it in the annealing agent in a molten state prepared in the first step S11, thereby completing the annealing. Preferably, the cadmium telluride series semiconductor crystal is completely immersed in the annealing agent in a molten state.

[0096] Heating the cadmium telluride series semiconductor crystal first avoids the crystal suddenly contacting the high-temperature annealing agent in a molten state, which can cause the crystal to crack due to sudden temperature changes, and also enables the atoms inside the cadmium telluride series semiconductor crystal to be in a relatively active state, thereby enabling better reaction with Cd and / or In elements.

[0097] Specifically, the second step S12 can be: heating the cadmium telluride series semiconductor crystal to a second temperature, wherein the second temperature is greater than or equal to the first temperature; and

[0098] After heating, the cadmium telluride series semiconductor crystal is immersed in the mixed melt of CdCl2and InCl2, and then the mixed melt is adjusted to the second temperature, and the second temperature and the second time period are maintained.

[0099] The second temperature is the temperature at which the crystal reacts with Cd and / or In elements. If the second temperature is lower than the first temperature, the mixed melt of CdCl2 and InCl2 will solidify and cannot be annealed. Optionally, the second temperature is 500–600°C. In some specific embodiments, the second temperature may be 500°C, 510°C, 520°C, 530°C, 540°C, 550°C, 560°C, 570°C, 580°C, 590°C, or 600°C.

[0100] Optionally, the second duration is greater than 5 hours, allowing the crystal to react fully with Cd and / or In. Further optionally, the second duration is 20–40 hours. In some specific embodiments, the second duration can be 20 hours, 22 hours, 22 hours, 26 hours, 28 hours, 30 hours, 32 hours, 34 hours, 36 hours, 38 hours, or 40 hours.

[0101] Optionally, the heating rate for raising the cadmium telluride semiconductor crystal to the second temperature is 50–70 °C / h. A faster heating rate allows the cadmium telluride semiconductor crystal to be heated quickly. In some specific embodiments, the heating rate can be 50 °C / h, 52 °C / h, 54 °C / h, 56 °C / h, 58 °C / h, 60 °C / h, 62 °C / h, 64 °C / h, 66 °C / h, 68 °C / h, or 70 °C / h.

[0102] Optionally, the cadmium telluride series semiconductor crystals are cadmium telluride series semiconductor crystals grown using the Bridgman process, such as CdTe and Cd2. 1-x Zn x Materials modified with Te (0 < x < 1) or by doping with lanthanide rare earth elements, Group I elements, Group II elements, Group III elements, or Group VII elements. Optionally, the cadmium telluride series semiconductor crystals reacting with the mixed melt of CdCl2 and InCl2 are wafers and / or strips. The cadmium telluride series semiconductor crystals can be cut into blank wafers or strips, and then the blank wafers or strips can be ground, polished, cleaned, and dried with nitrogen to obtain wafers or strips.

[0103] In the second step S12, the powder mixture of CdCl2 and InCl2 is mixed with cadmium telluride series semiconductor crystals (such as CdCl2). 1-x Zn xThe Te wafer or ingot is heated to the corresponding temperature respectively, and then the CdTe series semiconductor crystal is immersed in the mixed melt of CdCl2 and InCl2, so that the CdTe series semiconductor crystal can be in full contact with the annealing agent. The Cd and In elements in the melt have high energy at high temperature, and are more likely to diffuse deeply in the crystal, so that the Cd vacancies in the crystal are fully compensated. The In element diffuses from the surface of the crystal to the inside until the solubility in the crystal reaches saturation, replacing a small amount of Cd elements and Cd vacancies to form In-doped, and at the same time, forming part of In-Te chemical bonds with Te elements. Not only the Te inclusions are consumed, but also the carrier concentration and electron mobility of the crystal are improved, so as to prepare a detector-grade single crystal wafer / ingot for high-energy radiation detection.

[0104] Optionally, the method further comprises separating the CdTe series semiconductor crystal from the mixed melt of CdCl2 and InCl2, and cooling the CdTe series semiconductor crystal to room temperature.

[0105] Optionally, the CdTe series semiconductor crystal is first cooled from the second temperature to the third temperature at a rate of 25-35 ℃ / h, and then cooled to room temperature at a rate of 45-55 ℃ / h. The slow cooling first and then the fast cooling can help to prevent the crystal from being unstable due to the rapid temperature drop.

[0106] In some specific embodiments, the initial cooling rate (i.e. the rate from the second temperature to the third temperature) can be 25 ℃ / h, 27 ℃ / h, 29 ℃ / h, 31 ℃ / h, 33 ℃ / h or 35 ℃ / h. In some specific embodiments, the subsequent cooling rate (i.e. the rate from the third temperature to room temperature) can be 45 ℃ / h, 47 ℃ / h, 49 ℃ / h, 51 ℃ / h, 53 ℃ / h or 55 ℃ / h.

[0107] Optionally, the third temperature is 150-300 ℃. The crystal state is stable in the above temperature range, and the crystal can be rapidly cooled to room temperature. In some specific embodiments, the third temperature can be 150 ℃, 170 ℃, 190 ℃, 200 ℃, 220 ℃, 240 ℃, 260 ℃, 280 ℃ or 300 ℃.

[0108] After cooling, the entire annealing process is completed.

[0109] FIG. 2 shows an annealing method of a CdTe series semiconductor crystal according to another embodiment of the present application. The annealing method shown in FIG. 2 is completed in a crucible, and includes the following S21-S25.

[0110] The first pretreatment step S21: placing the cadmium-containing chloride and / or indium-containing chloride and the CdTe series semiconductor crystal into the crucible, and removing the oxygen attached to the surface of the crucible and the CdTe series semiconductor crystal.

[0111] Oxygen on the surface of the CdTe-based semiconductor crystal and the crucible reacts during the annealing process, which affects the quality of the final crystal. Alternatively, the oxygen attached to the surface of the CdTe-based semiconductor crystal and the crucible is removed by vacuumizing and backfilling with an inert atmosphere. In some embodiments, the interior of the crucible can be vacuumized to 10 -2 Pa, the crucible is filled with an inert gas (e.g., high-purity Ar gas), and the inert gas is removed, which is repeated several times (e.g., 3 times) to complete the cleaning of the atmosphere in the crucible, thereby removing the oxygen.

[0112] Alternatively, in use, the crucible is first soaked in an aqueous solution of hydrofluoric acid for about 10 min to remove metal ions and other impurities, then sequentially cleaned with an organic solvent (e.g., acetone, anhydrous ethanol) by ultrasonic cleaning (about 15 min for each cleaning) to remove organic impurities, and finally rinsed several times (e.g., 3-5 times) with deionized water and dried (e.g., in a clean oven at about 200°C).

[0113] The second pre-treatment step S22: the pressure of the crucible is vacuumized to 10 -2 Pa~10 -6 Pa, and the crucible is sealed.

[0114] That is, the crucible is vacuumized to perform the subsequent annealing step.

[0115] The melt annealing agent step S23: based on the cadmium-containing chloride and / or indium-containing chloride, a melt state annealing agent is prepared while the crucible is kept in the first position.

[0116] That is, the first step S11 is performed while the crucible is kept in the first position.

[0117] In the first position, the CdTe-based semiconductor crystal is separated from the cadmium-containing chloride and / or indium-containing chloride (or the melt state annealing agent). That is, at this time, although in the same crucible, the CdTe-based semiconductor crystal is separated from the cadmium-containing chloride and / or indium-containing chloride (or the melt state annealing agent) and does not contact.

[0118] Specifically, based on the cadmium-containing chloride and / or indium-containing chloride, a melt state annealing agent is prepared as in the first step S11, which is not repeated here.

[0119] The soaking crystal step S24: the crucible is rotated from the first position to the second position, and the CdTe-based semiconductor crystal is annealed by the melt state annealing agent while the crucible is kept in the second position.

[0120] That is, the second step S12 is performed while the crucible is kept in the second position.

[0121] In the second position, the cadmium telluride series semiconductor crystal is immersed in the annealing agent in a molten state, so as to realize annealing of the cadmium telluride series semiconductor crystal.

[0122] Specifically, the cadmium telluride series semiconductor crystal is annealed by using the annealing agent in a molten state as in the second step S12, which will not be described herein again.

[0123] The separation and cooling step S25: the crucible is rotated from the second position to the first position, so as to separate the cadmium telluride series semiconductor crystal from the mixed melt of CdCl2 and InCl2, and cool the cadmium telluride series semiconductor crystal to room temperature.

[0124] In the separation and cooling step S25, the cadmium telluride series semiconductor crystal is separated from the mixed melt of CdCl2 and InCl2 by rotating the crucible, and then the cadmium telluride series semiconductor crystal is cooled to room temperature, and the whole annealing process is completed. The specific cooling method has been described before, which will not be described herein again.

[0125] The annealing method provided in the present application compensates for the Cd vacancies caused by growth in the cadmium telluride series semiconductor crystal, realizes In element doping, and forms Te-In chemical bonds between In elements and Te elements, which not only consumes Te inclusions, but also improves the carrier concentration and electron mobility of the crystal, thereby improving the responsivity and response speed of the detector comprising the same, making the crystal more sensitive to γ rays, and more suitable for photon counting detectors with high time response requirements. Moreover, the annealing temperature is controlled to be less than or equal to 600°C, and the whole heat treatment process takes less than 70 hours, effectively solving the problems of energy consumption and time consumption in annealing of the cadmium telluride series semiconductor crystal.

[0126] The present application further provides an annealing device for a cadmium telluride series semiconductor crystal, comprising a crucible, a heating furnace and a position adjusting device.

[0127] FIG. 3 shows an annealing device 1000 provided in an embodiment of the present application, which comprises a crucible 100, a heating furnace 200, a position adjusting device 300 and a base 400. The crucible 100 can be a quartz crucible.

[0128] Fig. 4 shows the detailed structure of the crucible 100 in Fig. 3. In Fig. 4, the crucible 100 is in the shape of a bottle, which includes a crucible cap 110, a crucible body 120, and a clamp 130. The crucible body 120 includes an open end and a containing main body part, which includes a first zone 121 and a second zone 122. A second protrusion 1232 is formed on the inner wall of the second zone 122. The first zone 121 is used to contain the aforementioned cadmium-containing chloride and / or indium-containing chloride, and the second zone 122 is used to contain the aforementioned cadmium telluride series semiconductor crystal. The crucible cap 110 includes a crucible mouth 1101 and a connecting part 1102 used to connect with the crucible body 120. When not in use, the crucible cap 110 and the crucible body 120 are separated. When in use (i.e., after the cadmium-containing chloride and / or indium-containing chloride and the cadmium telluride series semiconductor crystal are respectively placed in the first zone 121 and the second zone 122), the connecting part 1102 of the crucible cap 110 can extend into the crucible body 120 (the upper part of the crucible body 120) from the open end of the crucible body 120, and can be connected with the inner wall of the open end of the crucible body 120 by high-temperature sintering. Fig. 4 shows the effect after sintering.

[0129] In the embodiment shown in Fig. 4, the cadmium-containing chloride and / or indium-containing chloride B is placed in the first zone 121. After the connecting part 1102 of the crucible cap 110 and the open end of the crucible body 120 are sintered, a sintered area is formed, and a first protrusion 1231 is formed at one end of the sintered area close to the second zone 122. The first protrusion 1231 and the aforementioned second protrusion 1232 together form a clamping groove used to fix the clamp 130, and the clamp 130 can be limited in the clamping groove. The second protrusion 1232 can be arranged in a ring around the inner wall of the second zone 122, or can be spaced apart in multiple forms on the inner wall of the second zone 122. Under the action of the clamp 130, the cadmium telluride series semiconductor crystal A can be fixed in the second zone 122. In this way, when the crucible 100 is in the position shown in Fig. 3 (in this application, the position shown in Fig. 3 can also be referred to as the first position, and at this time the first zone 121 is below and the second zone 122 is above), the cadmium telluride series semiconductor crystal A and the cadmium-containing chloride and / or indium-containing chloride B are separated.

[0130] In use, the jig 130 with the cadmium telluride series semiconductor crystal A is first placed in the crucible body 120, and then the connecting portion 1102 of the crucible cap 110 is inserted into the open end of the crucible body 120, and then the connecting portion 1102 and the open end of the crucible body 120 are high-temperature sintered to form a sintered region, so as to be combined together. The first protrusion 1231 and the second protrusion 1232 formed at the end of the sintered region close to the second region 122 constitute a clamping groove, and the jig 130 is limited in the clamping groove, so as to limit the cadmium telluride series semiconductor crystal A in the second region 122. In order to prevent the cadmium telluride series semiconductor crystal A from being adversely affected during high-temperature sintering, the jig 130 can be designed to have a groove starting from a distance from the end close to the crucible cap 110, so that after the jig is installed in the clamping groove and the cadmium telluride series semiconductor crystal A is placed in the groove, the crystal is spaced apart from the sintered region. As an example, the length of the sintered region formed is 10-20 mm, and the sintered region has a spacing of ≥30 mm from the groove provided in the jig. In addition, in order to avoid damage to the crystal caused by high temperature during sintering, the jig can also have a groove without the above-mentioned spacing, and the groove of the jig 130 close to the crucible cap 110 (i.e. the top of the jig 130, for example, one or two rows of grooves) does not place the cadmium telluride series semiconductor crystal A.

[0131] In the embodiment shown in FIG. 4, the jig 130 has only a single row of groove groups. FIG. 5 shows another embodiment of the crucible 100' provided by the present application, which is different from the embodiment shown in FIG. 4 in that the jig 130' of the second region 122' has two rows of groove groups. Each row of groove groups can have a plurality of grooves arranged uniformly along the longitudinal direction of the row, and each groove can limit one cadmium telluride series semiconductor crystal A (such as a cadmium telluride series semiconductor wafer). In other embodiments of the present application, the number of rows of grooves and the number of grooves in each row can be set as required. Although the crucible 100 is used in FIG. 3, the crucible 100' or other crucibles meeting the requirements can also be used.

[0132] As shown in FIG. 3, the heating furnace 200 includes a furnace body 210 for accommodating the aforementioned crucible 100 or crucible 100', and a heating device 220. The heating device 220 can be used to heat the crucible 100 or crucible 100', so that the cadmium-containing chloride and / or indium-containing chloride B is melted into an annealing agent in a molten state.

[0133] As shown in FIG. 3, the furnace body 210 comprises a first temperature zone 211 and a second temperature zone 212, and the heating device 220 comprises a first heating element 211A arranged corresponding to the first temperature zone 211 and a second heating element 212A arranged corresponding to the second temperature zone 212. When the crucible 100 or the crucible 100' is contained in the furnace body, the first heating element 211A in the first temperature zone 211 is used to heat the first zone 121 or the first zone 121', and the second heating element 212A in the second temperature zone 212 is used to heat the second zone 122 or the second zone 122'. The first heating element 211A and the second heating element 212A can be controlled independently, so that the first temperature zone 211 and the second temperature zone 212 can be controlled independently.

[0134] The position adjusting device 300 is connected with the heating furnace 200, and is used to adjust the position of the crucible 100 or the crucible 100' contained in the furnace body 210, so as to immerse the cadmium telluride series semiconductor crystal A in the annealing agent in a molten state, and thus anneal the cadmium telluride series semiconductor crystal A by using the annealing agent in a molten state.

[0135] In the embodiment shown in FIG. 3, the position adjusting device 300 comprises a rotating shaft 310 and a motor 320. The rotating shaft 310 is connected with the furnace body 210, and the motor 320 is connected with the rotating shaft 310. Under the action of the motor 320, the rotating shaft 310 can rotate the furnace body 210, so as to drive the crucible 100 or the crucible 100' to rotate, so as to immerse the cadmium telluride series semiconductor crystal A in the annealing agent in a molten state, and thus anneal the cadmium telluride series semiconductor crystal by using the annealing agent in a molten state. In this embodiment, two groups of rotating shafts 310 can be arranged to clamp the opposite sides of the furnace body 210, and the rotating shafts 310 are used to drive the furnace body 210 to rotate. The rotating shafts 310 are preferably arranged at the middle part of the furnace body 210 in the axial direction, so as to drive the furnace body 210 to rotate uniformly and improve the stability.

[0136] In the embodiment shown in FIG. 3, the motor 320 has a pair of motors arranged at the two sides of the heating furnace 200. In other embodiments of the present application, the number of the motors 320 can be increased or decreased according to the needs. In the embodiment shown in FIG. 3, the rotating shaft 310 and the motor 320 are connected with the base 400. In other embodiments of the present application, the base 400 can be omitted or replaced by other components.

[0137] In the embodiment shown in FIG. 3, the position of the crucible 100 comprises a first position and a second position. In the first position, the second zone 122 is located above the first zone 121, and the cadmium telluride series semiconductor crystal A is separated from the cadmium-containing chloride and / or the indium-containing chloride B or the annealing agent in a molten state. In the second position, the second zone 122 is located below the first zone 121, and the cadmium telluride series semiconductor crystal A is immersed in the annealing agent in a molten state.

[0138] With reference to the crucible 100 shown in FIG. 4, in combination with the aforementioned FIG. 2, when the cadmium telluride series semiconductor crystal A is fixed in the second zone 122 and the cadmium-containing chloride and / or indium-containing chloride B is placed in the first zone 121, the crucible 100 is in the first position as shown in FIG. 3, and at this time, the first pre-treatment step S21 shown in FIG. 2 is performed.

[0139] After the first pre-treatment step S21 is completed, the second pre-treatment step S22 is performed, and then the melting annealing agent step S23 is performed while the crucible 100 is kept in the first position shown in FIG. 3, to obtain the annealing agent in a molten state.

[0140] Then, the crystal immersion step S24 is performed, and the crucible 100 is rotated from the first position shown in FIG. 3 to the second position. In the present embodiment, the second position can be a position in which the second zone 122 is below and the first zone 121 is above, that is, the crucible 100 is rotated by 180°. In the second position, the annealing agent in a molten state can flow from the first zone 121 into the second zone 122, so that the cadmium telluride series semiconductor crystal A is immersed in the annealing agent in a molten state, thereby achieving annealing of the cadmium telluride series semiconductor crystal A.

[0141] After the crystal immersion step S24 is completed, the separation cooling step S25 is performed, and the crucible 100 is rotated again from the second position to the first position, so that the annealing agent in a molten state flows from the second zone 122 into the first zone 121, thereby separating the cadmium telluride series semiconductor crystal A from the annealing agent in a molten state.

[0142] In the present application, the rotation angle of the crucible 100 from the first position to the second position or from the second position to the first position can be 120° to 180°, for example, 120°, 130°, 140°, 150°, 160°, 170°, or 180°.

[0143] Alternatively, the rotation speed of the crucible 100 from the first position to the second position or from the second position to the first position is 1 to 5° / min, so that the molten annealing agent is slowly separated from the crystal (wafer or ingot), the annealing agent is slowly separated from the crystal by using the surface tension of the liquid, and there is no annealing agent residue on the surface of the crystal. In some specific embodiments, the rotation speed can be 1° / min, 1.5° / min, 2° / min, 2.5° / min, 3° / min, 3.5° / min, 4° / min, 4.5° / min, or 5° / min.

[0144] After the separation and cooling step S25 is completed, the crucible 100 can be cut open with a glass knife, and the crystal can be carefully knocked out along the score. In an embodiment of the present application, the crystal obtained by the above method is observed to have no surface damage after the entire annealing process. However, the use of metallic Cd for annealing in the prior art can easily cause etching of the crystal surface, resulting in surface damage. The present application avoids the problem of surface damage by using a melt as the annealing agent.

[0145] After being removed from the crucible, the crystal can be sequentially cleaned with deionized water-ethanol-deionized water (e.g., each for about 10 min), dried (e.g., by blowing with nitrogen), and stored to complete the process.

[0146] The annealing device provided by the present application is simple, and can be used in combination with the annealing method provided by the present application to produce a crystal with very good performance.

[0147] The present application further provides a cadmium telluride series semiconductor crystal produced by the above annealing method or annealing device. The crystal is doped with an In element. Alternatively, the annealed crystal further comprises a Te-In chemical bond.

[0148] Alternatively, the resistivity of the annealed crystal is ≥5×10 10 Ω·cm, and the carrier mobility lifetime product is ≥1×10 -3 cm 2 / V. Compared with the prior art, the resistivity of the crystal is improved by 3 orders of magnitude, and the carrier mobility lifetime product is improved from ~10 -4 cm 2 / V to ~10 -3 cm 2 / V order of magnitude.

[0149] Alternatively, the crystal capable of being annealed comprises CdTe, Cd 1-x Zn xTe (0 < x < 1) or a material doped with lanthanide, first group element, second group element, third group element, seventh group element. The lanthanide elements can include lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu). The first group elements can include lithium (Li), sodium (Na), potassium (K), rubidium (Rb), cesium (Cs), francium (Fr), copper (Cu), silver (Ag), gold (Au). The second group elements can include beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), radium (Ra), zinc (Zn), cadmium (Cd), mercury (Hg), Uub. The third group elements can include boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Ta). The seventh group elements can include fluorine (F), chlorine (Cl), bromine (Br), iodine (I), astatine (At).

[0150] The crystal prepared by the annealing method or the annealing device provided in the application has uniform quality, and the resistivity and carrier transport characteristics can meet the requirements of a photon counting detector.

[0151] The following illustrates the specific experimental examples of the application.

[0152] Experimental Example 1

[0153] The Cd 1-x Zn x Te (0 < x < 1) crystal is directionally cut to obtain a wafer, the wafer is ground, polished, and cleaned, and after nitrogen blowing, a small part of the wafer is taken out for resistivity determination and carrier mobility-lifetime product (μτ) determination, and the remaining part of the wafer is waiting for heat treatment. The resistivity of the wafer before heat treatment is 6.53-8.71 x 10 7 Ω·cm, and the carrier mobility-lifetime product (μτ) is about 10 -4 cm 2 / V.

[0154] The quartz crucible for heat treatment is first soaked in a hydrofluoric acid aqueous solution for 10 min to remove metal ions and other impurities, then sequentially ultrasonically cleaned with acetone and anhydrous ethanol for 15 min each to remove organic impurities, and finally washed with deionized water for 3-5 times and dried at 200°C in a clean oven.

[0155] A part of the wafers from the part of wafers waiting for heat treatment is taken out and fixed in the groove of the quartz clamp. First, a mixture of CdCl2 and InCl2 powders is filled in the first zone (the bottom of the crucible) of the crucible body, wherein the content ratio of CdCl2 and InCl2 is 100:1 in terms of the atomic ratio of Cd and In, and the mixture is uniformly mixed in the bottom of the crucible; then the quartz clamp with the wafers placed therein is smoothly put into the crucible body and clamped at the second protrusion provided on the inner wall of the crucible body; the connecting part of the crucible cap is inserted into the opening end of the crucible body, and the connecting part of the crucible cap and the crucible body are connected together by high-temperature sintering to form a sintering area, and the clamp is fixed between the first protrusion formed by sintering at one end of the sintering area close to the second zone and the second protrusion. The inside of the crucible is vacuumed to 10 -2 Pa, and the atmosphere in the crucible is washed by repeatedly filling and extracting high-purity Ar gas for 3 times to remove the oxygen attached to the surface of the crucible and the wafer. Finally, the pressure in the crucible is extracted to ≤10 -4 Pa, and the crucible is sealed by high-temperature sintering.

[0156] The sealed crucible is vertically placed in a heating furnace for heat treatment. The annealing agent is at the first temperature zone and the wafer is at the second temperature zone. The second temperature zone is slowly raised to 500-600℃ at a speed of 50-70℃ / h, while the first temperature zone is raised to 400-500℃, and the temperature is kept for 5-10h to make the mixture of CdCl2 and InCl2 fully melt into a uniform melt. The rotating motor is turned on to make the heating furnace rotate 120-180° along the shaft until the wafer is immersed in the melt. Then the temperature zone where the wafer is located is continuously kept at 500-600℃ for 20-40h for annealing.

[0157] After the annealing is completed, the annealing furnace is counterclockwise rotated back to the initial position at a speed of 1-5° / min to slowly separate the molten medium from the wafer until the separation is completed. After the annealing is completed, the first temperature zone where the wafer is located is first cooled to 200℃ at a speed of 30℃ / h, and then cooled to room temperature at a speed of 50℃ / h, and the second temperature zone is naturally cooled to room temperature.

[0158] The quartz crucible is cut open with a glass knife, and the wafer is taken out. Observation shows that the heat treatment process does not cause damage to the surface of the wafer. The wafer is sequentially ultrasonically cleaned with deionized water-ethanol-deionized water for 10min each, and dried by nitrogen blowing for storage.

[0159] The resistivity of the crystal obtained by testing is increased from 6.53-8.71×10 7 Ω·cm to 5.27-7.11×10 10 Ω·cm, which is improved by 3 orders of magnitude; then the electrical properties of the wafer are tested, and the carrier mobility-lifetime product (μτ) of the crystal is about 10 -4 cm2 / V to ~ 10 -3 cm 2 / V order of magnitude. It is proved that the defect density and electrical properties of the CdTe series semiconductor crystals are obviously improved after the melt annealing treatment.

[0160] Experimental Example 2

[0161] In Experimental Example 2, except that the mixture of CdCl2 and InCl2 powder is set as a mixture with the content ratio of CdCl2 and InCl2 being 100:5 in terms of the atomic ratio of Cd and In, other conditions are the same as those in Experimental Example 1, and the same tests as those in Experimental Example 1 are conducted. It is known from the test results that, after the annealing treatment, the resistivity of the crystal is increased from 6.53-8.71 x 10 7 Ω·cm to 5.6-8.21 x 10 10 Ω·cm, and the carrier mobility-lifetime product (μτ) is increased from ~ 10 -4 cm 2 / V to ~ 10 -3 cm 2 / V order of magnitude. It is proved that the defect density and electrical properties of the CdTe series semiconductor crystals are obviously improved after the melt annealing treatment.

[0162] Experimental Example 3

[0163] In Experimental Example 3, except that the mixture of CdCl2 and InCl2 powder is set as a mixture with the content ratio of CdCl2 and InCl2 being 100:0.3 in terms of the atomic ratio of Cd and In, other conditions are the same as those in Experimental Example 1, and the same tests as those in Experimental Example 1 are conducted. It is known from the test results that, after the annealing treatment, the resistivity of the crystal is 1.32-5.14 x 10 9 Ωcm, and the carrier mobility-lifetime product (μτ) is 7.35 x 10 -4 cm 2 / V. This is because the carrier concentration and electron mobility of the wafer are not effectively improved due to the small amount of In element doping, and the resistivity is increased to ~ 10 9 Ω·cm order of magnitude.

[0164] Experimental Example 4

[0165] In Experimental Example 4, except that the mixture of CdCl2 and InCl2 powder is set as a mixture with the content ratio of CdCl2 and InCl2 being 100:10 in terms of the atomic ratio of Cd and In, other conditions are the same as those in Experimental Example 1, and the same tests as those in Experimental Example 1 are conducted. It is known from the test results that, after the annealing treatment, the resistivity of the crystal is 2.74-8.96 x 108 Ω-cm, and the carrier mobility-lifetime product (μτ) is 1.2 x 10 -4 cm 2 / V. It can be seen that the resistivity of the wafer is improved, but only to the order of 10 8 Ω-cm, and the μτ value level is not effectively improved. This is because the wafer surface after annealing is etched by excess In, and a small amount of In inclusion phase is added to the wafer interior, resulting in a substantial decrease in electrical performance compared to the atomic ratio of Cd and In of 100:(1-5).

[0166] The above merely describes exemplary embodiments of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, modifications or equivalent replacements of the technical solutions described in the foregoing embodiments or equivalent replacements of some technical features can be made by those skilled in the art. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An annealing method of a cadmium telluride series semiconductor crystal, characterized by, The method comprises the following steps: a first step (S11) of preparing an annealing agent in a molten state based on a cadmium-containing chloride and / or an indium-containing chloride; and a second step (S12) of annealing a cadmium telluride series semiconductor crystal using the annealing agent in the molten state.

2. The annealing method according to claim 1, characterized by, The first step (S11) comprises: preparing the annealing agent in the molten state based on a powder mixture of CdCl2 and InCl2, wherein the content ratio of CdCl2 and InCl2 in the powder mixture of CdCl2 and InCl2 is 100:(1-5) in terms of the atomic ratio of Cd and In.

3. The annealing method of claim 1, wherein The first step (S11) comprises: after heating the powder mixture of CdCl2 and InCl2 to a first temperature, heat preserving is performed at the first temperature for a first time length, so that the powder mixture of CdCl2 and InCl2 is melted into a mixed melt of CdCl2 and InCl2, wherein the first temperature is not higher than 500°C, and the first time length is greater than 1h; optionally, the first temperature is 400-500°C; optionally, the first time length is 5-10h.

4. The annealing method according to claim 3, wherein The second step (S12) comprises: heating the cadmium telluride series semiconductor crystal to a second temperature, wherein the second temperature is greater than or equal to the first temperature; and immersing the heated cadmium telluride series semiconductor crystal in the mixed melt of CdCl2 and InCl2, heating the melt to the second temperature, and then heat preserving is performed at the second temperature for a second time length, wherein the second time length is greater than 5h, optionally, the second temperature is 500-600°C, optionally, the second time length is 20-40h.

5. The annealing method according to claim 4, wherein in the first step (S11), the heating rate of the powder mixture of CdCl2 and InCl2 to the first temperature is 50-70°C / h; in the second step (S12), the heating rate of the cadmium telluride series semiconductor crystal to the second temperature is 50-70°C / h.

6. The annealing method of claim 4, wherein After the second step (S12), the annealing method further comprises: separating the cadmium telluride series semiconductor crystal from the mixed melt of CdCl2 and InCl2, and cooling the cadmium telluride series semiconductor crystal to room temperature, optionally, the step of cooling the cadmium telluride series semiconductor crystal to room temperature comprises: first cooling the cadmium telluride series semiconductor crystal to a third temperature at a rate of 25-35°C / h, and then cooling the cadmium telluride series semiconductor crystal to room temperature at a rate of 45-55°C / h, the third temperature is 150-300°C.

7. The annealing method of claim 1, wherein Before the first step (S11), the annealing method further comprises: a first pretreatment step (S21) of placing the cadmium-containing chloride and / or the indium-containing chloride and the cadmium telluride series semiconductor crystal into a crucible, and removing oxygen attached to the surface of the cadmium telluride series semiconductor crystal and the crucible; A second pre-treatment step (S22): the pressure of the crucible is drawn to 10 -2 Pa ~ 10 -6 Pa The crucible is then sealed, optionally, the first pretreatment step (S21) comprises: removing the oxygen by vacuumizing and back-filling with an inert atmosphere.

8. The annealing method of claim 7, wherein the first step (S11) comprises a molten annealing agent step (S23) of preparing a molten annealing agent based on a cadmium-containing chloride and / or an indium-containing chloride while the crucible is kept at a first position in which the cadmium telluride series semiconductor crystal is separated from the cadmium-containing chloride and / or the indium-containing chloride or the molten annealing agent; the second step (S12) comprises a crystal soaking step (S24) of rotating the crucible from the first position to a second position, and annealing the cadmium telluride series semiconductor crystal with the molten annealing agent while the crucible is kept at the second position in which the cadmium telluride series semiconductor crystal is soaked in the molten annealing agent. The cadmium telluride series semiconductor crystal comprises a wafer and / or a bar.

9. The annealing method of claim 1, wherein, The annealing device comprises:

10. An annealing apparatus for cadmium telluride series semiconductor crystals, characterized in that, a crucible having a first zone for containing a cadmium-containing chloride and / or an indium-containing chloride and a second zone for containing a cadmium telluride series semiconductor crystal; a heating furnace comprising a furnace body for containing the crucible and a heating device for heating the crucible; and a position adjusting device connected to the heating furnace for adjusting the position of the crucible contained in the furnace body after the cadmium-containing chloride and / or the indium-containing chloride is heated to be molten into a molten annealing agent, so as to soak the cadmium telluride series semiconductor crystal in the molten annealing agent. The position adjusting device comprises:

11. The annealing apparatus of claim 10, wherein a rotating shaft connected to the furnace body; and a motor connected to the rotating shaft, and under the action of the motor, the rotating shaft can rotate the furnace body to drive the crucible to rotate, so as to soak the cadmium telluride series semiconductor crystal in the molten annealing agent. The position of the crucible comprises a first position and a second position, wherein in the first position, the second zone is located above the first zone, and the cadmium telluride series semiconductor crystal is separated from the cadmium-containing chloride and / or the indium-containing chloride or the molten annealing agent, and in the second position, the second zone is located below the first zone, and the cadmium telluride series semiconductor crystal is soaked in the molten annealing agent; 12. The annealing apparatus of claim 10, wherein Optionally, the rotating angle of the crucible when rotating from the first position to the second position or from the second position to the first position is 120°-180°. The annealing device further comprises a clamp having a groove for fixing the cadmium telluride series semiconductor crystal; and 13. The annealing apparatus of claim 10, wherein a clamping groove provided in the second zone of the crucible for fixing the clamp, Optionally, the clamp has one or more groove groups, and each groove group is provided with a plurality of grooves. The crucible comprises a crucible cap and a crucible body, 14. The annealing apparatus of claim 13, wherein ​ The crucible cap comprises a crucible mouth and a connecting part for connecting with the crucible body; the crucible body comprises an open end and a containing main body part, the containing main body part comprises the first area and the second area, and a second protrusion is formed on the inner wall of the second area, The connecting part of the crucible cap can be extended into the crucible body, and the inner wall of the open end of the crucible body is connected together by high-temperature sintering to form a sintering area, and a first protrusion is formed on one end of the sintering area close to the containing main body part, the first protrusion and the second protrusion constitute the clamping groove for fixing the clamp.

15. The annealing device according to claim 14, characterized in that, The length of the sintering area is 10-20 mm, and the sintering area has a spacing of ≥30 mm with the groove arranged in the clamp.

16. The annealing apparatus of claim 10, wherein The furnace body comprises a first temperature zone and a second temperature zone, and the heating device comprises a first heating element arranged corresponding to the first temperature zone and a second heating element arranged corresponding to the second temperature zone, wherein the first heating element in the first temperature zone is used for heating the first area, and the second heating element in the second temperature zone is used for heating the second area, Optionally, the first heating element and the second heating element can be controlled individually.

17. An annealed cadmium telluride series semiconductor crystal, characterized by, The annealed cadmium telluride series semiconductor crystal is prepared by the annealing method according to any one of claims 1-9 or by the annealing device according to any one of claims 10-16, wherein the annealed cadmium telluride series semiconductor crystal is doped with In element.

18. The annealed cadmium telluride series semiconductor crystal of claim 17, wherein, The annealed cadmium telluride series semiconductor crystal comprises a Te-In chemical bond.

19. The annealed cadmium telluride series semiconductor crystal of claim 17, wherein, The resistivity of the annealed cadmium telluride series semiconductor crystal is ≥ 5 x 10 10 Ω-cm, and the carrier mobility lifetime product is ≥ 1 x 10 -3 cm 2 / V.

20. The annealed cadmium telluride series semiconductor crystal of claim 19, wherein, The cadmium telluride series semiconductor crystals include CdTe, Cd 1-x Zn x Te or a material modified by doping with lanthanides, elements of the first group, elements of the second group, elements of the third group, elements of the seventh group, wherein 0 < x < 1.

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