Multilayer ceramic capacitor

Abstract

A multilayer ceramic capacitor according to the present disclosure includes a laminate, external electrodes, and a pair of side margin parts. The laminate is formed by alternately laminating dielectric layers and internal electrode layers, and has a pair of end surfaces, a pair of side surfaces, and a pair of main surfaces. The pair of side margin parts are made of a dielectric material and cover the pair of side surfaces, respectively. The multilayer ceramic capacitor has a plurality of pores between the internal electrode layers and the side margin parts. The plurality of pores include first pores present near a first surface of a pair of surfaces, second pores present near a second surface of the pair of surfaces, and third pores present in a center part between the pair of surfaces. The pore diameter of the first pores and the pore diameter of the second pores are smaller than the pore diameter of the third pores.

Description

Multilayer ceramic capacitors

[0001] The present disclosure relates to multilayer ceramic capacitors.

[0002] 2. Description of the Related Art Conventionally, a multilayer ceramic capacitor is known, for example, as described in Patent Document 1.

[0003] Japanese Patent Application Laid-Open No. 2016-225603

[0004] The multilayer ceramic capacitor according to the present disclosure is a laminate in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked, the laminate having a pair of end faces facing each other, a pair of side faces continuing to the pair of end faces and facing each other, and a pair of faces continuing to the pair of end faces and the pair of side faces and facing each other; a first external electrode covering a first end face of the pair of end faces and connected to a first internal electrode layer of the plurality of internal electrode layers exposed at the first end face; a second external electrode covering a second end face of the pair of end faces and connected to a second internal electrode layer of the plurality of internal electrode layers exposed at the second end face; and a second external electrode covering each of the pair of side faces and connected to a dielectric. and a pair of side margin portions each consisting of an internal electrode layer ...

[0005] The objects, features, and advantages of the present disclosure will become more apparent from the following detailed description and drawings.

[0023] FIG. 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present disclosure.

[0024] FIG. 2 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 1.

[0025] FIG. 3 is a cross-sectional view taken along the cross-sectional line III-III of FIG. 1.

[0026] FIG. 4 is a cross-sectional view taken along the cross-sectional line IV-IV of FIG. 3.

[0027] FIG. 5 is an enlarged view showing the left side of the upper four corners, the right side of the upper four corners, the left side of the lower four corners, the right side of the lower four corners, the left side of the center between the upper and lower four corners, and the right side of the center between the upper and lower four corners in the cross-sectional view of FIG. 4.

[0028] FIG. 6 is a graph showing the relationship between the number of stacked internal electrode layers and the average pore diameter of pores.

[0029] FIG. 7 is a cross-sectional view showing the deformation amount when a plurality of laminates are placed at a first interval on a cushioning material on which side margin sheets are arranged, and are pressed in by a first indentation amount.

[0029] FIG. 8 is a perspective view showing a state in which a plurality of laminates are placed at a first interval on a cushioning material on which side margin sheets are arranged, and are pressed in by a first indentation amount. 1 is a cross-sectional view showing the amount of deformation when a plurality of laminates are placed on a cushioning material on which side margin sheets are arranged at a second interval and pressed in by a second amount. FIG. 2 is a perspective view showing a state where a plurality of laminates are placed on a cushioning material on which side margin sheets are arranged at a second interval and pressed in by a second amount. FIG. 3 is a cross-sectional view showing the amount of deformation when a plurality of laminates are placed on a cushioning material on which side margin sheets are arranged at a third interval and pressed in by a third amount. FIG. 4 is a perspective view showing a state where a plurality of laminates are placed on a cushioning material on which side margin sheets are arranged at a third interval and pressed in by a third amount. FIG. 5 is an enlarged cross-sectional view of the upper part of four corners of a multilayer ceramic capacitor of a comparative example. FIG. 6 is an enlarged cross-sectional view of the upper part of four corners of a multilayer ceramic capacitor.

[0006] Conventional multilayer ceramic capacitors are composed of a laminate in which internal electrodes and dielectric layers are alternately stacked, and a side margin portion made of a dielectric and provided to cover the side surface of the laminate. The capacitor has an offset portion located between the internal electrode and the side margin portion, which offsets the end of the internal electrode on the side surface from the side surface toward the inside of the laminate.

[0007] In conventional multilayer ceramic capacitors, when side margins are formed on the side surfaces, pores can occur between the side margins and the internal electrodes. If the pore diameter of the pores generated at the four corners (see below) of the element body having the laminate and side margins is large, cracks can occur starting from the pores, potentially reducing the strength of the laminate. Therefore, there is a need for a multilayer ceramic capacitor that can reduce the reduction in strength of the laminate 2.

[0008] Hereinafter, embodiments of the multilayer ceramic capacitor of the present disclosure will be described with reference to the drawings. The drawings referred to below are schematic, and the dimensional ratios and the like shown in the drawings are not necessarily accurate. The present disclosure is not limited to multilayer ceramic capacitors, and can be applied to multilayer piezoelectric elements, multilayer thermistor elements, multilayer chip coils, ceramic multilayer substrates, and the like. In this specification, a Cartesian coordinate system XYZ is defined for convenience in some of the drawings. The X-axis direction is also referred to as the first direction or length direction. The Y-axis direction is also referred to as the second direction or width direction. The Z-axis direction is also referred to as the third direction, height direction, or stacking direction.

[0009] Fig. 1 is a perspective view showing a multilayer ceramic capacitor 1 according to an embodiment of the present disclosure. Fig. 2 is a perspective view showing an element body 6 of the multilayer ceramic capacitor 1 of Fig. 1. Fig. 3 is a cross-sectional view taken along the cutting line III-III in Fig. 1. Fig. 4 is a cross-sectional view taken along the cutting line IV-IV in Fig. 3. In Fig. 2, for ease of illustration, the ends of the internal electrode layers 5 exposed at the end faces of the laminate 2 are shown hatched.

[0010] 1, the multilayer ceramic capacitor 1 of this embodiment includes a laminate 2, a pair of external electrodes 3a, 3b, and a pair of side margin portions 13. The pair of external electrodes 3a, 3b are a first external electrode 3a and a second external electrode 3b.

[0011] As shown in FIG. 2 , the laminate 2 has a substantially rectangular parallelepiped shape. The laminate 2 has a pair of opposing surfaces 7a, 7b, a pair of opposing end surfaces 8a, 8b, and a pair of opposing side surfaces 9a, 9b. The pair of surfaces 7a, 7b are a first surface 7a and a second surface 7b that face each other in the third direction (Z-axis direction). The pair of end surfaces 8a, 8b are a first end surface 8a and a second end surface 8b that face each other in the first direction (X-axis direction). The pair of side surfaces 9a, 9b are a first side surface 9a and a second side surface 9b that face each other in the second direction (Y-axis direction). The first surface 7a and the second surface 7b may be perpendicular to the third direction Z. The first end surface 8a and the second end surface 8b may be perpendicular to the first direction (X-axis direction). The first side surface 9a and the second side surface 9b may be perpendicular to the second direction (Y-axis direction).

[0012] 3, the laminate 2 is configured by alternately stacking a plurality of dielectric layers 4 and a plurality of internal electrode layers 5. The plurality of dielectric layers 4 and the plurality of internal electrode layers 5 are stacked in a third direction (Z-axis direction).

[0013] The dielectric layer 4 is made of an insulating dielectric material, such as barium titanate (BaTiO ３ ), barium calcium titanate (Ba １－ｘ Ca ｘ TiO ３ ), calcium titanate (CaTiO ３ ), strontium titanate (SrTiO ３ ), barium zirconate (BaZrO ３ The ceramic material may be composed of a ceramic material containing, as a main component, a material such as a fluorine-containing compound (Fc) or a fluorine-containing compound (Hf). In this specification, the term "main component" refers to the component that has the highest content in the material or member of interest. The content may be expressed, for example, in mol% or mass%.

[0014] The dielectric layer 4 may contain metal elements such as magnesium (Mg), manganese (Mn), and vanadium (V), and rare earth elements such as yttrium (Y), dysprosium (Dy), holmium (Ho), terbium (Tb), and ytterbium (Yb). It may also contain a sintering aid and a glass material whose main component is Si. In this case, it is possible to control the sintering state of the multilayer ceramic capacitor 1 and improve the high-temperature load life and temperature characteristics of the capacitance.

[0015] The thinner the dielectric layer 4, the greater the capacitance of the multilayer ceramic capacitor 1. The thickness of the dielectric layer 4 may be, for example, not less than about 0.5 μm and not more than about 10 μm.

[0016] The internal electrode layers 5 are configured to contain a metal material, and may be configured to contain, for example, a metal such as nickel (Ni), copper (Cu), silver (Ag), tin (Sn), platinum (Pt), palladium (Pd), or gold (Au), or an alloy containing these metals.

[0017] Both ends (side surfaces 9 a, 9 b) of the laminate 2 in the second direction Y are covered by side margin portions 13. The side margin portions 13 include a first side margin portion 13 a and a second side margin portion 13 b. The first side margin portion 13 a covers the first side surface 9 a, and the second side margin portion 13 b covers the second side surface 9 b.

[0018] The side margin portion 13 is made of an insulating dielectric material, such as BaTiO ３ , barium calcium titanate (Ba １－ｘ Ca ｘ TiO ３ ), CaTiO ３ , SrTiO ３ , BaZrO ３ The side margin portion 13 may be made of the same ceramic material as the ceramic material that constitutes the dielectric layer 4.

[0019] The internal electrode layers 5 are exposed on the first side surface 9a and the second side surface 9b. The side margin portions 13 electrically insulate the internal electrode layers 5 of different polarities exposed on the side surfaces 9a, 9b from each other. The side margin portions 13 also mechanically protect the outer portions of the internal electrode layers 5 exposed on the side surfaces 9a, 9b. The side margin portions 13 are also referred to as protective layers. The laminate 2 having the side margin portions 13 disposed on the side surfaces 9a, 9b is also referred to as an element body 6.

[0020] The thinner the first side margin portion 13 a and the second side margin portion 13 b are, the smaller and larger the capacitance of the multilayer ceramic capacitor 1. The thickness of the first side margin portion 13 a and the second side margin portion 13 b may be, for example, not less than about 5 μm and not more than about 30 μm.

[0021] The internal electrode layer 5 is exposed at a first end surface 8a or a second end surface 8b depending on the polarity. The end of the internal electrode layer 5 exposed at the first end surface 8a is covered by and connected to the first external electrode 3a of the pair of external electrodes 3a, 3b. The end of the internal electrode layer 5 exposed at the second end surface 8b is covered by and connected to the second external electrode 3b of the pair of external electrodes 3a, 3b.

[0022] As long as the characteristics of the multilayer ceramic capacitor can be ensured, the thinner the thickness of the internal electrode layers 5, the more likely it is that internal defects caused by internal stress during firing of the laminate 2 or during voltage application can be reduced, thereby improving the reliability of the multilayer ceramic capacitor 1. The thickness of the internal electrode layers 5 may be, for example, about 1.5 μm or less.

[0023] The first external electrode 3a is located at least on the first end surface 8a. The first external electrode 3a may be located from the first end surface 8a to at least one of the first surface 7a and the second surface 7b. As shown in FIG. 1 , the first external electrode 3a may be located from the first end surface 8a to the first surface 7a, the second surface 7b, the first side surface 9a, and the second side surface 9b.

[0024] The second external electrode 3b is located at least on the second end surface 8b. The second external electrode 3b may be located from the second end surface 8b to at least one of the first surface 7a and the second surface 7b. As shown in FIG. 1 , the second external electrode 3b may be located from the second end surface 8b to the first surface 7a, the second surface 7b, the first side surface 9a, and the second side surface 9b.

[0025] The first external electrode 3a and the second external electrode 3b are composed of a single layer or multiple layers of conductive layers. As shown in FIG. 3 , each of the first external electrode 3a and the second external electrode 3b may be composed of a first layer 31 and a second layer 32. The first layer 31 is also referred to as an underlayer. The underlayer 31 contacts the surface of the laminate 2 and is connected to the ends of the internal electrode layer 5 exposed at the end faces 8a and 8b. The second layer 32 is also referred to as an outer layer. The outer layer 32 covers the surface of the underlayer 31 opposite the laminate 2 side. By configuring the first external electrode 3a and the second external electrode 3b with multiple conductive layers, it is possible to improve the adhesion between the first external electrode 3a and the second external electrode 3b and the laminate 2 while also improving the wettability of a conductive bonding material such as solder to the first external electrode 3a and the second external electrode 3b. As a result, the reliability of the multilayer ceramic capacitor 1 and the mounting structure including the multilayer ceramic capacitor 1 can be improved.

[0026] The underlayer 31 may be made of a metal material, such as Ni, Cu, Ag, Pd, or Au, or an alloy containing any of these metals. The underlayer 31 may be formed using a thin-film formation technique, such as plating, sputtering, or vapor deposition, or may be formed using a thick-film formation technique, such as dipping, screen printing, or gravure printing.

[0027] The outer layer 32 may be configured to include a metal material. The outer layer 32 may be configured to include, for example, a metal such as Ni, Cu, Au, or Sn, or an alloy containing these metals. The outer layer 32 may be formed using a thin film formation technique such as an electroless plating method or an electrolytic plating method. The outer layer 32 may be a single-layer plated layer or multiple-layer plated layers.

[0028] 5 is an enlarged view showing the left side of the upper four corners, the right side of the upper four corners, the left side of the lower four corners, the right side of the lower four corners, the left side of the center between the upper and lower four corners, and the right side of the center between the upper and lower four corners of the element body 6 in the cross-sectional view of FIG.

[0029] 5, the upper portions of the four corners are regions including 1 to 100 internal electrode layers 5 from the first surface 7a to the second surface 7b. The central portion is a region including 101 to 200 internal electrode layers 5 from the first surface 7a to the second surface 7b. The lower portions of the four corners are regions including 201 to 300 internal electrode layers 5 from the first surface 7a to the second surface 7b. In this specification, unless otherwise specified, the number of stacked internal electrode layers 5 in the laminate 2 is assumed to be 300, but is not limited to this.

[0030] The element body 6 has, in a cross-sectional view parallel to the end faces 8 a, 8 b, a plurality of pores 14 (voids) present between the plurality of internal electrode layers 5 and each of the side margins 13 a, 13 b. In a cross-sectional view parallel to the end faces 8 a, 8 b, the plurality of pores 14 include a first pore 141 present between the internal electrode layer 5 located closer to the first surface 7 a of the pair of surfaces 7 a, 7 b and the side margins 13 a, 13 b (upper portions of the four corners), a second pore 142 present between the internal electrode layer 5 located closer to the second surface 7 b of the pair of surfaces 7 a, 7 b and the side margins 13 a, 13 b (lower portions of the four corners), and a third pore 143 present between the internal electrode layer 5 located in the center between the pair of surfaces 7 a, 7 b and the side margins 13 a, 13 b (central portion).

[0031] The number of internal electrode layers 5 located closer to the first surface 7a or closer to the second surface 7b may be 15% to 35% of the number of stacked internal electrode layers 5. For example, when the number of stacked layers is 300, the internal electrode layers 5 located closer to the first surface 7a may be 1 to 100 internal electrode layers 5 from the first surface 7a to the second surface 7b. Furthermore, the internal electrode layers 5 located closer to the second surface 7b may be 201 to 300 internal electrode layers 5 from the first surface 7a. Furthermore, the internal electrode layers 5 located in the center between the pair of surfaces 7a, 7b may be 101 to 200 internal electrode layers 5 from the first surface 7a.

[0032] Furthermore, for example, when the number of stacked internal electrode layers 5 is 600, the internal electrode layers 5 located closer to the first surface 7a may be 1 to 200 internal electrode layers 5 from the first surface 7a to the second surface 7b. The internal electrode layers 5 located closer to the second surface 7b may be 401 to 600 internal electrode layers 5 from the first surface 7a to the second surface 7b. Furthermore, the internal electrode layers 5 located in the center between the pair of surfaces 7a, 7b may be 201 to 400 internal electrode layers 5 from the first surface 7a to the second surface 7b.

[0033] The multilayer ceramic capacitor 1 is configured such that the pore diameters of the first pores 141 and the second pores 142 are smaller than the pore diameter of the third pores 143. The maximum pore diameters of the first pores 141 and the second pores 142 may be 1.3 μm or less. In a cross-sectional view parallel to the end faces 8 a, 8 b, the ratio of the number of the first pores 141 and the number of the second pores 142 to the number of the internal electrode layers 5 or the dielectric layers 4 may be 29% or more and 55% or less. Furthermore, the ratio of the number of the third pores 143 to the number of the internal electrode layers 5 or the dielectric layers 4 may be 56% or more and 64% or less.

[0034] FIG. 6 is a graph showing the relationship between the number of stacked internal electrode layers 5 and the average pore diameter (average value of pore diameter) of the pores 14. FIG. 5 shows that the average pore diameter is 0.19 μm when the number of stacked layers is 50, which means that the average pore diameter of the pores 14 between the 1st to 50th internal electrode layers 5 and the side margin portion 13 from the first surface 7a to the second surface 7b is 0.19 μm. FIG. 5 also shows that the average pore diameter is 0.243 μm when the number of stacked layers is 100, which means that the average pore diameter of the pores 14 between the 51st to 100th internal electrode layers 5 and the side margin portion 13 from the first surface 7a to the second surface 7b is 0.243 μm. The same applies to the average pore diameters when the number of stacked layers is 150, 200, 250, and 300. Note that when calculating the average pore diameter, areas without pores 14 are counted as 0, and the average value is calculated. 5, the pores 14 are formed in areas surrounded by frame lines m1, m2, m3, m4, m5, and m6, which are near the boundaries between the ends of the internal electrode layers 5 and the side margins 13a and 13b. Since the element body 6 is less brittle at the four corners than at the center, cracks tend to enter from the four corners rather than the center. Therefore, by making the average pore diameter of the pores 14 at the four corners smaller than the average pore diameter of the pores 14 at the center, it is possible to reduce the occurrence of cracks.

[0035] Furthermore, since the average pore diameter of the pores 14 in the center is larger than that of the four corners, even if the dielectric layer 4 is subjected to tensile force due to sintering shrinkage of the internal electrode layer 5, the pores 14 can alleviate the force, thereby reducing residual stress in the center.

[0036] In a cross-sectional view parallel to the end faces 8 a and 8 b of the multilayer ceramic capacitor 1, the shrinkage rate of the internal electrode layers 5 increases toward the center. Therefore, the pores 14 in the center can alleviate the tensile stress toward the side margin portions 13.

[0037] Table 1 shows the average, minimum, and maximum values ​​of the pore diameter of the pores 14 relative to the number of stacked internal electrode layers 5. The calculation of the average pore diameter is as described above. Table 1 shows that the minimum value of the pore diameter is 0 μm and the maximum value is 0.820 μm when the number of stacked layers is 50. This means that the minimum value of the pore diameter of the pores 14 between the 1st to 50th internal electrode layers 5 and the side margin portion 13 from the first surface 7a to the second surface 7b is 0 μm and the maximum value is 0.820 μm. The same applies to the minimum and maximum values ​​of the pore diameter when the number of stacked layers is 100, 150, 200, 250, and 300.

[0038]

[0039] Next, a description will be given of a process of attaching ceramic green sheets (also referred to as side margin sheets) that will become the side margin portions 13 to the unsintered laminate 2. In the following description, the terms laminate 2, side margin portions 13, etc. may be used in the same manner before and after firing.

[0040] The laminate 2 can be produced, for example, by cutting a base laminate, which is an assembly of a plurality of laminates 2. Since the ends of a plurality of internal electrode layers 5 are exposed on the side surfaces 9a, 9b of the laminate 2 obtained by cutting the base laminate, the ends exposed on the side surfaces 9a, 9b of at least some of the internal electrode layers 5 are removed. This makes it possible to form pores 14 between the internal electrode layers 5 and the side margin portions 13. The method for removing the ends of the internal electrode layers 5 is not particularly limited, and known methods can be used. Note that if no pores 14 exist or the pore diameter is small, the distance between the internal electrode layers 5 will be short, or electrical contact between the internal electrode layers 5 will likely occur stochastically, which may result in a short circuit between the internal electrode layers 5.

[0041] Next, a cushioning material (also referred to as an adhesive film) is prepared, a side margin sheet is placed on the upper surface of the cushioning material, and the laminate 2 is placed on the side margin sheet so that the first side surface 9a contacts the ceramic green sheet. The laminate 2 is then pressed against the cushioning material and the side margin sheet is punched out, thereby forming a first side margin portion 13a on the first side surface 9a of the laminate 2. Similarly, a second side margin portion 13b can be formed on the second side surface 9b of the laminate 2. When forming the side margin portion 13, a pressure device positioned below the cushioning material may be used to press the cushioning material upward. The adhesive film may be made of PET (polyethylene terephthalate).

[0042] FIG. 7A is a cross-sectional view showing the amount of deformation when a plurality of laminates 2 are placed at a first interval on a cushioning material on which side margin sheets are arranged and pressed down a first amount ΔL1. FIG. 7B is a perspective view showing the state in which a plurality of laminates 2 are placed at a first interval on a cushioning material on which side margin sheets are arranged and pressed down a first amount ΔL1. FIG. 7A shows a cross-section taken along the section line VIIA-VIIA in FIG. 7B. FIG. 8A is a cross-sectional view showing the amount of deformation when a plurality of laminates 2 are placed at a second interval on a cushioning material on which side margin sheets are arranged and pressed down a second amount ΔL2. FIG. 8B is a perspective view showing the state in which a plurality of laminates 2 are placed at a second interval on a cushioning material on which side margin sheets are arranged and pressed down a second amount ΔL2. FIG. 8A shows a cross-section taken along the section line VIIIA-VIIIA in FIG. 8B. Fig. 9A is a cross-sectional view showing the deformation amount when a plurality of laminates 2 are placed on a cushioning material on which side margin sheets are arranged at a third interval and pressed in by a third depression amount ΔL3. Fig. 9B is a perspective view showing a state in which a plurality of laminates 2 are placed on a cushioning material on which side margin sheets are arranged at a third interval and pressed in by a third depression amount ΔL3. Note that Fig. 9A shows a cross section seen from the cutting line IXA-IXA of Fig. 9B.

[0043] Each laminate 2 is placed on the adhesive film so that the first side surface 9a contacts the side margin sheet. When the longitudinal dimension of the first side surface 9a is 0.77 mm and the transverse dimension is 0.59 mm, the first spacing δ11 in the transverse direction is δ11 = 1.50 mm, the second spacing δ12 in the transverse direction is δ12 = 1.25 mm, and the third spacing δ13 in the transverse direction is δ13 = 1.00 mm. The first spacing δ21 in the longitudinal direction is δ21 = 2.00 mm, the second spacing δ22 in the longitudinal direction is δ22 = 1.70 mm, and the third spacing δ23 in the longitudinal direction is δ23 = 1.40 mm. The longitudinal direction and the transverse direction may be the first direction (X-axis direction) and the third direction (Z-axis direction), respectively.

[0044] The arrangement pitch ratios in the width direction when the dimension of the first side surface 9a is taken as the reference value (=1) are δ1 = 2.56, δ2 = 2.13, and δ3 = 1.71, respectively. The arrangement pitch ratios in the length direction to the dimension of the first side surface 9a are δ1 = 2.59, δ2 = 2.20, and δ3 = 1.81.

[0045] The first indentation amount ΔL1 is ΔL1 = 74 μm, the second indentation amount ΔL2 is ΔL2 = 54 μm, and the third indentation amount ΔL3 is ΔL3 = 34 μm. The first indentation amount ΔL1, the second indentation amount ΔL2, and the third indentation amount ΔL3 were calculated by simulation taking into account the hardness or dimensions of the related objects and the applied pressure.

[0046] When punching out the side margin sheet, the laminate 2 is pressed against the side margin sheet while a load is applied to the four corners of the second side surface 9b of the laminate 2 placed on the adhesive film. The load applied to the four corners is, for example, 200 g / mm ２ It may be to some extent.

[0047] The center of the laminate 2 is slightly recessed, and the four corners of the first side surface 9a come into contact with the adhesive film first via the side margin sheet, so a large force acts on the four corners of the first side surface 9a.

[0048] When the side margin sheet is punched out, the adhesive film between the pressurizer and the side margin sheet applies greater pressure to the four sides of the first side surface 9a, i.e., the first surface 7a side and the second surface 7b side, than to the center side, so that the dielectric material constituting the side margin portions 13a, 13b enters the first pores 141 and the second pores 142. By firing the laminate 2 in which the dielectric material constituting the side margin portions 13a, 13b has entered the first pores 141 and the second pores 142, it is possible to produce an element body 6 in which the pore diameters of the first pores 141 and the second pores 142 are smaller than the pore diameter of the third pore 143. By forming a pair of external electrodes 3a, 3b on the produced element body 6, it is possible to manufacture the multilayer ceramic capacitor 1.

[0049] 10A is an enlarged cross-sectional view of the upper part of four corners of an element body of a multilayer ceramic capacitor of a comparative example. Fig. 10B is an enlarged cross-sectional view of the upper part of four corners of an element body 6 of a multilayer ceramic capacitor 1 of the present disclosure. The multilayer ceramic capacitor of the comparative example is a multilayer ceramic capacitor in which the maximum pore diameter of the pores present in the upper part of the four corners is greater than 1.3 μm. In the following description, terms and reference symbols such as internal electrode layers 5 and pores 14 may also be used for the multilayer ceramic capacitor of the comparative example.

[0050] The side margin portion 13 shown in Figures 10A and 10B is formed by attaching a side margin sheet to the side surfaces 9a and 9b of the laminate 2 using the method described above. If the maximum pore diameter of the first pores 141 is greater than 1.3 μm, when the dielectric material of the side margin portions 13a and 13b enters the first pores 141, there is a risk of the internal electrode layers 5 collapsing, as shown by reference symbol m7 in Figure 10A. By setting the maximum pore diameter of the first pores 141 to 1.3 μm or less, as shown in Figure 10B, even if the dielectric material enters the first pores 141, the internal electrode layers 5 can be prevented from collapsing. As a result, the occurrence of short circuits between the internal electrode layers 5 can be reduced. The same applies to the second pores 142 at the bottom of the four corners.

[0051] The mechanism of electrode collapse of the internal electrode layer 5 is thought to be as follows. When the side margin sheet is attached, stress is first generated in the protruding dielectric layer 4. As a result, the side margin sheet begins to fill the first pores 141 and the second pores 142. When the maximum pore diameter of the first pores 141 and the second pores 142 exceeds 1.3 μm, the dielectric material of the side margin sheet cannot fill all of the first pores 141 and the second pores 142, and the protruding dielectric layer 4 begins to collapse due to stress. As a result, the internal electrode layer 5 is pulled by the collapse of the dielectric layer 4 and also begins to collapse, for example, to bend.

[0052] If the maximum pore diameter of the first pores 141 and the second pores 142 is 1.3 μm or less, when the side margin sheet is pressed, the side margin sheet enters the first pores 141 and the second pores 142 and fills the first pores 141 and the second pores 142. As a result, even if further pressure is applied to the laminate 2, the dielectric layers 4 are less likely to collapse, and collapse of the internal electrode layers 5 can also be reduced.

[0053] Furthermore, if the maximum pore diameter of the first pores 141 and the second pores 142 is greater than 1.3 μm, electrode collapse may occur, causing the internal electrode layers 5 to ball. For example, if the internal electrode layers 5 made of Ni ball, the internal electrode layers 5 become locally thick and the dielectric layers 4 become locally thin, increasing the electric field strength. As a result, the life, i.e., the reliability, of the multilayer ceramic capacitor is reduced. The multilayer ceramic capacitor 1 according to the present disclosure can reduce electrode collapse of the internal electrode layers 5 and reduce the thinning of the dielectric layers 4 due to the balling of the internal electrode layers 5, thereby achieving a high dielectric constant and an improved high-temperature load life.

[0054] In the multilayer ceramic capacitor 1, in a cross-sectional view parallel to the end faces 8 a, 8 b, the ratio of the number of the first pores 141 and the number of the second pores 142 to the number of the internal electrode layers 5 at the four corners may be 29% or more and 55% or less. In the multilayer ceramic capacitor 1, in a cross-sectional view parallel to the end faces 8 a, 8 b, the ratio of the number of the third pores 143 to the number of the internal electrode layers 5 at the center may be 56% or more and 64% or less. The number of the internal electrode layers 5 at the four corners is also the number of the dielectric layers 4 adjacent to the internal electrode layers 5 at the four corners, and the number of the internal electrode layers 5 at the center is also the number of the dielectric layers 4 adjacent to the internal electrode layers 5 at the center.

[0055] Table 2 shows the results (porcelain analysis results) obtained by observing a cross section parallel to the end faces 8a and 8b of the multilayer ceramic capacitor 1. In obtaining the magnetic analysis results in Table 2, based on the analysis and measurement results using image analysis and measurement software (WinRoof), 64 layers of the internal electrode layers 5 included in the upper four corners were measured, 36 layers of the internal electrode layers 5 included in the central portion were analyzed, and 51 layers of the internal electrode layers 5 included in the lower four corners were analyzed.

[0056]

[0057] The multilayer ceramic capacitor 1 whose magnetic analysis results are shown in Table 2 has side margin portions 13 formed by the method described with reference to FIGS. 7A, 7B, 8A, 8B, 9A, and 9B.

[0058] According to the multilayer ceramic capacitor 1 of the present disclosure, the ratio of the number of first pores 141 and second pores 142 is reduced by 1% or more and 35% or less compared to the ratio of the number of third pores 143, thereby reducing the occurrence of cracks in the laminate 2.

[0059] The present disclosure can be implemented in the following configurations (1) to (3).

[0060] (1) A laminate in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked, the laminate having a pair of end faces facing each other, a pair of side faces continuing to the pair of end faces and facing each other, and a pair of surfaces continuing to the pair of end faces and the pair of side faces and facing each other, a first external electrode covering a first end face of the pair of end faces and connected to a first internal electrode layer exposed to the first end face of the plurality of internal electrode layers, a second external electrode covering a second end face of the pair of end faces and connected to a second internal electrode layer exposed to the second end face of the plurality of internal electrode layers, and a pair of side margin portions made of a dielectric covering each of the pair of side faces, wherein in a cross section parallel to the end faces, a plurality of pores are present between the internal electrode layer and the side margin portion, the plurality of pores comprising: a first pore present between an internal electrode layer located closer to a first surface of the pair of surfaces and the side margin portion in a cross section parallel to the end faces; a second pore present between an internal electrode layer located closer to a second surface of the pair of surfaces and the side margin portion; and a third pore present between an internal electrode layer located in a central portion between the pair of surfaces and the side margin portion, wherein a pore diameter of the first pore and a pore diameter of the second pore are smaller than a pore diameter of the third pore.

[0061] (2) The multilayer ceramic capacitor according to the above configuration (1), wherein the maximum pore diameter of the first pores and the second pores is 1.3 μm or less.

[0062] (3) The multilayer ceramic capacitor according to the above configuration (1) or (2), wherein, in a cross-sectional view parallel to the end face, the ratio of the number of the first pores and the number of the second pores to the number of the internal electrode layers or the dielectric layers is 29% or more and 55% or less, and the ratio of the number of the third pores to the number of the internal electrode layers or the dielectric layers is 56% or more and 64% or less.

[0063] According to the multilayer ceramic capacitor according to the present disclosure, it is possible to reduce the decrease in strength of the laminate and reduce the occurrence of cracks.

[0064] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above-described embodiments, and various modifications and improvements are possible within the scope of the gist of the present disclosure. It goes without saying that all or part of the components constituting each of the above-described embodiments can be combined as appropriate within the scope of not contradicting each other.

[0065] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3a First external electrode 3b Second external electrode 4 Dielectric layer 5 Internal electrode layer 6 Element body 7a First surface 7b Second surface 8a First end surface 8b Second end surface 9a First side surface 9b Second side surface 13, 13a, 13b Side margin portion 14, 141, 142, 143 Pore 31 Underlayer 32 Outer layer

Claims

1. A laminate in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked, the laminate having a pair of end faces facing each other, a pair of side faces continuing to the pair of end faces and facing each other, and a pair of surfaces continuing to the pair of end faces and the pair of side faces and facing each other; a first external electrode covering a first end face of the pair of end faces and connected to a first internal electrode layer exposed at the first end face of the plurality of internal electrode layers; a second external electrode covering a second end face of the pair of end faces and connected to a second internal electrode layer exposed at the second end face of the plurality of internal electrode layers; and a pair of side margins made of a dielectric covering each of the pair of side faces, wherein in a cross section parallel to the end faces, there are a plurality of pores between the internal electrode layer and the side margins, the plurality of pores comprising: a first pore present between an internal electrode layer located closer to a first surface of the pair of surfaces and the side margins in a cross section parallel to the end faces; a second pore present between an internal electrode layer located closer to a second surface of the pair of surfaces and the side margin portion; and a third pore present between an internal electrode layer located in a central portion between the pair of surfaces and the side margin portion, wherein a pore diameter of the first pore and a pore diameter of the second pore are smaller than a pore diameter of the third pore.

2. The multilayer ceramic capacitor according to claim 1, wherein the maximum pore diameter of the first pores and the second pores is 1.3 μm or less.

3. A multilayer ceramic capacitor according to claim 1 or 2, wherein, in a cross-sectional view parallel to the end face, the ratio of the number of the first pores and the number of the second pores to the number of the internal electrode layers or the dielectric layers is 29% or more and 55% or less, and the ratio of the number of the third pores to the number of the internal electrode layers or the dielectric layers is 56% or more and 64% or less.

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