Multilayer ceramic electronic component

Abstract

Provided is a multilayer ceramic electronic component capable of preventing separation of a spacer and a multilayer ceramic capacitor, or preventing separation of a substrate and a multilayer ceramic electronic component after mounting the component on the substrate.　This multilayer ceramic electronic component 100 comprises: a multilayer ceramic capacitor that includes a multilayer body having a first surface and a second surface facing each other in the height direction, a third surface and a fourth surface facing each other in a first direction orthogonal to the height direction, and a fifth surface and a sixth surface facing each other in a second direction orthogonal to the height direction and the first direction, a first external electrode disposed on the second surface and the third surface of the multilayer body, and a second external electrode disposed on the second surface and the fourth surface of the multilayer body; a first spacer connected to the first external electrode; a second spacer connected to the second external electrode; and a third spacer disposed between the first spacer and the second spacer. The first spacer has a central region and a peripheral region located around the central region. The metal component ratio of the first spacer is 86.4-94.3%, and the metal component ratio of the central area is 91.6-94.2%.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] A multilayer ceramic capacitor has an inner layer portion in which dielectric layers and internal electrodes are alternately stacked. Dielectric layers are arranged on the top and bottom of the inner layer portion to form a rectangular parallelepiped laminate, which serves as an outer layer portion. External electrodes are provided on both longitudinal end faces of the laminate, forming a multilayer ceramic capacitor. In a multilayer ceramic capacitor, capacitance is generated when the internal electrodes face each other via the dielectric layers. It is known that vibrations occur in the multilayer ceramic capacitor due to the piezoelectric phenomenon, and when these vibrations are transmitted to the substrate, they cause what is known as "noise."

[0003] To suppress the occurrence of "squeak noise," for example, it is effective to separate the multilayer ceramic capacitor from the substrate. For this reason, for example, a multilayer ceramic electronic component is known that includes bumps (spacers) formed on the side of the multilayer ceramic capacitor that is mounted on the substrate so as to cover part of the external electrodes.

[0004] For example, Patent Document 1 describes a multilayer ceramic capacitor in which an interposer (spacer) is formed by applying an interposer-forming paste onto a capacitor body and then performing a heat treatment.

[0005] Japanese Patent Application Laid-Open No. 2022-177518

[0006] However, there is a risk that the interposer and the capacitor body may become detached due to an impact, or that the multilayer ceramic capacitor with the interposer attached may become detached from the substrate after mounting on the substrate.

[0007] Therefore, an object of the present invention is to provide a multilayer ceramic electronic component that can prevent the spacer and the multilayer ceramic capacitor from coming off, or the multilayer ceramic electronic component from coming off the substrate after mounting on the substrate.

[0008] A multilayer ceramic electronic component according to the present invention comprises: a laminate including first and second surfaces opposing each other in a height direction, third and fourth surfaces opposing each other in a first direction perpendicular to the height direction, and fifth and sixth surfaces opposing each other in a second direction perpendicular to the height direction and the first direction; a multilayer ceramic capacitor including first external electrodes disposed on the second and third surfaces of the laminate and second external electrodes disposed on the second and fourth surfaces of the laminate; a first spacer connected to the first external electrodes, a second spacer connected to the second external electrodes, and a third spacer disposed between the first spacer and the second spacer; the first spacer having a first central region and a first peripheral region located around the first central region; a metal component ratio of the first spacer being 86.4% or more and 94.3% or less, and a metal component ratio of the first central region being 91.6% or more and 94.2% or less.

[0009] A multilayer ceramic electronic component according to the present invention comprises a multilayer ceramic capacitor, a first spacer connected to a first external electrode, a second spacer connected to a second external electrode, and a third spacer disposed between the first spacer and the second spacer, wherein the first spacer has a first central region and a first peripheral region located around the first central region, and the first spacer has a metal component ratio of 86.4% or more and 94.3% or less, and the first central region has a metal component ratio of 91.6% or more and 94.2% or less. This improves the adhesive strength between the first spacer and the second spacer and the multilayer ceramic capacitor, and makes it possible to prevent the spacers from becoming detached from the multilayer ceramic capacitor or from becoming detached from a substrate on which the multilayer ceramic electronic component is mounted.

[0010] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can prevent the spacer and the multilayer ceramic capacitor from coming off, or the multilayer ceramic electronic component from coming off the substrate after mounting on the substrate.

[0011] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0012] Fig. 1 is an external perspective view showing a multilayer ceramic electronic component according to an embodiment of the present invention; Fig. 2 is a front view showing a multilayer ceramic electronic component according to an embodiment of the present invention; Fig. 3 is a bottom view of the multilayer ceramic electronic component according to an embodiment of the present invention; Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 2; Fig. 5 is a cross-sectional view taken along line VV in Fig. 3; Fig. 6 is an enlarged cross-sectional view showing a first spacer (second spacer) and a third spacer of the multilayer ceramic electronic component according to an embodiment of the present invention; Fig. 7 is a diagram showing a mounted state of the multilayer ceramic electronic component according to an embodiment of the present invention;

[0013] 1. Multilayer Ceramic Electronic Component A multilayer ceramic electronic component 100 according to the present invention will be described with reference to FIGS. 1 to 6. FIG. 1 is an external perspective view showing a multilayer ceramic electronic component according to an embodiment of the present invention. FIG. 2 is a front view showing a multilayer ceramic electronic component according to an embodiment of the present invention. FIG. 3 is a bottom view of the multilayer ceramic electronic component according to an embodiment of the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. FIG. 5 is a cross-sectional view taken along line VV in FIG. 3. FIG. 6 is an enlarged cross-sectional view showing a first spacer (second spacer) and a third spacer of the multilayer ceramic electronic component according to an embodiment of the present invention.

[0014] A multilayer ceramic electronic component 100 according to the present invention comprises a multilayer ceramic capacitor 10 having a laminate 12 and two external electrodes 30 a, 30 b, a first spacer 52 connected to one of the external electrodes 30 a, a second spacer 54 connected to the other external electrode 30 b, and a third spacer 56 disposed between the first spacer 52 and the second spacer 54.

[0015] (Laminate) The laminate 12 has a plurality of stacked dielectric layers 14 and a plurality of internal electrodes 16 stacked on the dielectric layers 14. The laminate 12 has a first surface 12a and a second surface 12b facing in a height direction x, a third surface 12c and a fourth surface 12d perpendicular to the height direction x and facing in a first direction y, and a fifth surface 12e and a sixth surface 12f perpendicular to the height direction x and the first direction y and facing in a second direction z. In this embodiment, the first surface 12a side of the laminate 12 is the non-mounting surface side, and the second surface 12b side of the laminate 12 is the mounting surface side. The height direction x is a direction perpendicular to the mounting surface S. Furthermore, a second direction z connecting the fifth surface 12e and the sixth surface 12f of the laminate 12 may be the stacking direction.

[0016] The laminate 12 has a hexahedral shape. Furthermore, it is preferable that the corners and ridges of the laminate 12 are rounded. The corners refer to the portions where three adjacent faces of the laminate 12 intersect, and the ridges refer to the portions where two adjacent faces of the laminate 12 intersect. Furthermore, unevenness may be formed on some or all of the first face 12a and the second face 12b, the third face 12c and the fourth face 12d, and the fifth face 12e and the sixth face 12f.

[0017] The laminate 12 has an inner layer portion 18 in which a plurality of inner electrodes 16 face each other. In other words, in the inner layer portion 18, the first inner electrode 16a and the second inner electrode 16b face each other.

[0018] The laminate 12 is located on the first surface 12a side and has a first outer layer portion 20a formed from a plurality of dielectric layers 14 located between the first surface 12a and the outermost surface of the inner layer portion 18 on the first surface 12a side and an extension of that outermost surface.

[0019] Similarly, the laminate 12 has a second outer layer portion 20b located on the second surface 12b side and formed from a plurality of dielectric layers 14 located between the second surface 12b and the outermost surface of the inner layer portion 18 on the second surface 12b side and an extension of that outermost surface.

[0020] (Dielectric Layer) The ceramic material constituting the dielectric layer 14 may be, for example, a dielectric ceramic composed of a main component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Alternatively, a material containing these main components and added with a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound may be used.

[0021] The thickness of the dielectric layer 14 is preferably 0.5 μm or more and 10 μm or less. The number of the dielectric layers 14, including the first outer layer portion 20 a and the second outer layer portion 20 b, is preferably 10 or more and 700 or less.

[0022] (Internal Electrode) The internal electrode 16 includes a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b.

[0023] The first internal electrodes 16a are disposed on the plurality of dielectric layers 14 and are exposed on the third surface 12c.

[0024] The second internal electrode 16b is disposed on the plurality of dielectric layers 14 and is exposed on the fourth surface 12d.

[0025] The first internal electrode 16a includes a first opposing electrode portion 26a that faces the second internal electrode 16b, and a first extraction electrode portion 28a that is extracted from the first opposing electrode portion 26a to the third surface 12c of the laminate 12. An end of the first extraction electrode portion 28a of the first internal electrode 16a is extracted to the surface of the third surface 12c of the laminate 12, forming an exposed portion.

[0026] The second internal electrode 16b includes a second opposing electrode portion 26b that faces the first internal electrode 16a, and a second extraction electrode portion 28b that is extracted from the second opposing electrode portion 26b to the fourth surface 12d of the laminate 12. The second extraction electrode portion 28b of the second internal electrode 16b has an end that is extracted to the surface of the fourth surface 12d of the laminate 12, forming an exposed portion.

[0027] The shapes of the first opposing electrode portion 26a of the first internal electrode 16a and the second opposing electrode portion 26b of the second internal electrode 16b are not particularly limited, but are preferably rectangular, although the corners may be rounded or angled (tapered).

[0028] The shapes of the first lead electrode portion 28a of the first internal electrode 16a and the second lead electrode portion 28b of the second internal electrode 16b are not particularly limited, but are preferably rectangular, although the corners may be rounded or angled (tapered).

[0029] The width of the first opposing electrode portion 26a of the first internal electrode 16a and the second opposing electrode portion 26b of the second internal electrode 16b may be the same as the width of the first extraction electrode portion 28a of the first internal electrode 16a and the second extraction electrode portion 28b of the second internal electrode 16b, or one of them may be formed to have a narrower width.

[0030] In this embodiment, the opposing electrode portions 26 of the internal electrodes 16 face each other via the dielectric layer 14, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0031] The first internal electrode 16a and the second internal electrode 16b can be made of an appropriate conductive material, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0032] Furthermore, by including a Sn solid solution layer between the first internal electrode 16a and the second internal electrode 16b and the dielectric layer 14, it is possible to alleviate electric field concentration at the interface between the internal electrode 16 and the dielectric layer 14, leading to improved high-temperature load reliability. In this case, even if Sn is included in only one of the internal electrodes 16, either the first internal electrode 16a or the second internal electrode 16b, it can exhibit a sufficient effect.

[0033] The thickness of each of the first internal electrode 16a and the second internal electrode 16b is preferably, for example, 0.2 μm or more and 2.0 μm or less. The number of internal electrodes 16 is preferably 10 or more and 700 or less.

[0034] (External Electrode) The external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0035] The first external electrode 30a is connected to the first internal electrode 16a and is disposed on the third surface 12c and the second surface 12b. Alternatively, the first external electrode 30a may be disposed on a portion of the first surface 12a, a portion of the fifth surface 12e, and a portion of the sixth surface 12f. In this embodiment, the first external electrode 30a extends from the third surface 12c to a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f.

[0036] The second external electrode 30b is connected to the second internal electrode 16b and is disposed on the fourth surface 12d and the second surface 12b. Alternatively, the second external electrode 30b may be disposed on a portion of the first surface 12a, a portion of the fifth surface 12e, and a portion of the sixth surface 12f. In this embodiment, the second external electrode 30b extends from the fourth surface 12d to a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f.

[0037] The first external electrode 30 a and the second external electrode 30 b have an underlying electrode layer 32 disposed on the surface of the laminate 12 and a plating layer 34 disposed so as to cover the underlying electrode layer 32 .

[0038] (Base Electrode Layer) The base electrode layer 32 is disposed on the third surface 12c and the fourth surface 12d. Furthermore, on the first external electrode 30a side and the second external electrode 30b side, the base electrode layer 32 may also be disposed on parts of the first surface 12a and the second surface 12b, parts of the fifth surface 12e, and parts of the sixth surface 12f. In this embodiment, on the first external electrode 30a side and the second external electrode 30b side, the base electrode layer 32 is formed so as to extend from the third surface 12c and the fourth surface 12d to parts of the first surface 12a and the second surface 12b, parts of the fifth surface 12e, and parts of the sixth surface 12f.

[0039] The base electrode layer 32 includes a first base electrode layer 32a and a second base electrode layer 32b.

[0040] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0041] (In the case of a baking layer) The baking layer contains a glass component and a metal. The glass component of the baking layer contains, for example, at least one selected from B, Si, Ba, Mg, Al, and Li. The metal of the baking layer contains, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, etc.

[0042] The baked layer may be a multi-layer. The baked layer is formed by applying and baking a conductive paste containing glass and metal to the laminate 12. The baked layer may be formed by simultaneously firing a laminated chip having the internal electrodes 16 and the dielectric layer 14 with the conductive paste applied to the laminated chip, or by firing a laminated chip having the internal electrodes 16 and the dielectric layer 14 to obtain the laminate 12, and then applying and baking the conductive paste to the laminate 12. When simultaneously firing a laminated chip having the internal electrodes 16 and the dielectric layer 14 with the conductive paste applied to the laminated chip, it is preferable to form the baked layer by adding a dielectric material instead of the glass component and baking it.

[0043] The thickness in the first direction y connecting the third surface 12c and the fourth surface 12d at the center of the height direction x connecting the first surface 12a and the second surface 12b of the first baking layer located on the third surface 12c (i.e., the thickness of the base electrode layer at the center of the third surface 12c) is preferably, for example, 3 μm or more and 160 μm or less.

[0044] The thickness in the first direction y connecting the third surface 12c and the fourth surface 12d at the center of the height direction x connecting the first surface 12a and the second surface 12b of the second baking layer located on the fourth surface 12d (i.e., the thickness of the base electrode layer at the center of the fourth surface 12d) is preferably, for example, 3 μm or more and 160 μm or less.

[0045] Furthermore, the thickness in the height direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the first baking layer located on a part of the first surface 12a and a part of the second surface 12b is preferably, for example, 3 μm or more and 40 μm or less.

[0046] Furthermore, the thickness in the height direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the second baking layer located on a part of the first surface 12a and a part of the second surface 12b is preferably, for example, 3 μm or more and 40 μm or less.

[0047] (In the case of conductive resin layer) When a conductive resin layer is provided as the base electrode layer 32, the conductive resin layer may be disposed so as to cover the baked layer. Alternatively, the conductive resin layer may be disposed directly on the laminate 12 without providing a baked layer. The conductive resin layer may completely cover the base electrode layer 32, or may cover only a portion of the base electrode layer 32. Alternatively, the conductive resin layer may be formed of multiple layers.

[0048] The conductive resin layer contains, for example, a thermosetting resin and a metal component.

[0049] Specific examples of the thermosetting resin include various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0050] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used as the curing agent.

[0051] The metal contained in the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these. Alternatively, a metal powder with an Ag coating on its surface can be used. When using a metal powder with an Ag coating on its surface, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder. The reason for using Ag conductive metal powder as the metal contained in the conductive resin layer is that Ag has the lowest resistivity among metals, making it suitable as an electrode material, and Ag is a noble metal that does not oxidize and has high weather resistance. Furthermore, it is possible to use an inexpensive base metal while maintaining the above-mentioned properties of Ag. Furthermore, Cu or Ni that has been subjected to an oxidation prevention treatment can also be used as the metal contained in the conductive resin layer. Alternatively, a metal powder with an Sn, Ni, or Cu coating on its surface can also be used as the metal contained in the conductive resin layer. When using a metal powder with an Sn, Ni, or Cu coating on its surface, it is preferable to use Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder.

[0052] The metal contained in the conductive resin layer can be spherical, flat, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder. The metal contained in the conductive resin layer is primarily responsible for the electrical conductivity of the conductive resin layer. Specifically, contact between conductive fillers (metal contained in the conductive resin layer) forms an electrical path inside the conductive resin layer.

[0053] Since the conductive resin layer contains a thermosetting resin, it is more flexible than a base electrode layer made of, for example, a plating film or a fired conductive paste, and therefore functions as a buffer layer to prevent cracks in the multilayer ceramic capacitor even when the multilayer ceramic capacitor is subjected to a physical impact or an impact due to a thermal cycle.

[0054] The thickness of the thickest part of the conductive resin layer is preferably, for example, 10 μm or more and 150 μm or less.

[0055] (In the case of a thin film layer) The thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0056] (Plating Layer) The plating layer 34 includes a first plating layer 34a and a second plating layer 34b. The first plating layer 34a is disposed so as to cover the first base electrode layer 32a. The second plating layer 34b is disposed so as to cover the second base electrode layer 32b.

[0057] The plating layer 34 contains at least one selected from the group consisting of Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, and Au.

[0058] The plating layer 34 may be formed of multiple layers. Preferably, it has a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic electronic component 100. The Sn plating layer also improves the wettability of the solder when mounting the multilayer ceramic electronic component 100, facilitating mounting.

[0059] The thickness of each plating layer 34 is preferably 2 μm or more and 15 μm or less.

[0060] The external electrode 30 may be formed using only the plating layer 34 without providing the base electrode layer 32. A structure in which the plating layer 34 is provided without providing the base electrode layer 32 will be described below.

[0061] For each of the first external electrode 30a and the second external electrode 30b, the plating layer 34 may be formed directly on the surface of the laminate 12 without providing the base electrode layer 32. That is, the multilayer ceramic capacitor 10 may have a structure including the plating layer 34 that is directly connected to the first internal electrode 16a and the second internal electrode 16b. In such a case, the plating layer 34 may be formed after a catalyst is disposed on the surface of the laminate 12 as a pretreatment.

[0062] When a plating layer is formed directly on the laminate 12 without providing the base electrode layer 32, the reduction in the thickness of the base electrode layer 32 can be converted into a lower profile, i.e., a thinner body, or into the thickness of the laminate 12, i.e., the thickness of the inner layer portion 18 (effective layer portion), thereby improving the design freedom of thin chips.

[0063] Furthermore, the plating layer 34 preferably includes a lower-layer plating electrode formed on the surface of the laminate 12 and an upper-layer plating electrode formed on the surface of the lower-layer plating electrode.

[0064] The lower layer plating electrode and the upper layer plating electrode each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal.

[0065] The lower layer plated electrode is preferably formed using Ni, which has solder barrier properties, and the upper layer plated electrode is preferably formed using Sn, which has good solder wettability.

[0066] Furthermore, for example, when the first internal electrode 16 a and the second internal electrode 16 b are formed using Ni, it is preferable that the lower-layer plated electrode be formed using Cu, which has good bonding properties with Ni. Note that the upper-layer plated electrode may be formed as needed, and the first external electrode 30 a and the second external electrode 30 b may each be composed of only the lower-layer plated electrode.

[0067] The plating layer 34 may have an upper layer plating electrode as the outermost layer, or another plating electrode may be formed on the surface of the upper layer plating electrode.

[0068] The thickness of each plating layer 34, which is disposed without providing a base electrode layer 32, is preferably 1 μm or more and 15 μm or less. The plating layer 34 preferably does not contain glass. The metal content per unit volume of the plating layer 34 is preferably 99% by volume or more.

[0069] The dimension of the multilayer ceramic capacitor 10 in the first direction y is defined as the L dimension. The L dimension is preferably 1.0 mm or more and 10 mm or less. The dimension of the multilayer ceramic capacitor 10 in the second direction z is defined as the W dimension. The W dimension is preferably 0.5 mm or more and 5 mm or less. The dimension of the multilayer ceramic capacitor 10 in the height direction x is defined as the T dimension. The T dimension is preferably 0.5 mm or more and 5 mm or less. More preferably, the L dimension is preferably 1.0 mm or more and 2.1 mm or less. The W dimension is preferably 0.5 mm or more and 1.3 mm or less. The T dimension is preferably 0.5 mm or more and 1.3 mm or less.

[0070] (Spacer) The multilayer ceramic electronic component 100 includes a multilayer ceramic capacitor 10 and a spacer 50. The spacer 50 includes a first spacer 52 that covers at least a portion of the first external electrode 30a, a second spacer 54 that covers at least a portion of the second external electrode 30b, and a third spacer 56 that covers a portion of the laminate 12, a portion of the first spacer 52, and a portion of the second spacer 54. In this embodiment, the first spacer 52, the second spacer 54, and the third spacer 56 are described separately from one another, but there are cases in which the first spacer 52, the second spacer 54, and the third spacer 56 are integrated and cannot be distinguished from one another.

[0071] 7 , when the multilayer ceramic electronic component 100 is mounted on a mounting substrate 60, the first spacer 52 and the second spacer 54 are electrically and mechanically connected to the land electrodes 64 a, 64 b via the solder 62. At this time, the solder 62 forms fillets along the first spacer 52 and the first external electrode 30 a, and along the second spacer 54 and the second external electrode 30 b. Note that fillets formed by the solder 62 may be formed only on the first spacer 52 or the second spacer 54. When fillets are formed only on the first spacer 52 and the second spacer 54, the amount of wetting of the solder 62 onto the multilayer ceramic capacitor 10 can be reduced, thereby suppressing acoustic noise.

[0072] (First Spacer and Second Spacer) The first spacer 52 is disposed between the first external electrode 30a and the mounting surface S and is connected to the first external electrode 30a. The second spacer 54 is disposed between the second external electrode 30b and the mounting surface S and is connected to the second external electrode 30b.

[0073] The shapes of the first spacer 52 and the second spacer 54 are not particularly limited. In other words, the shapes of the first spacer 52 and the second spacer 54 may be, for example, substantially hexahedral. In the following description, the shapes of the first spacer 52 and the second spacer 54 will be described as being hexahedral.

[0074] The first spacer 52 has a first surface 52a and a second surface 52b facing in the height direction x, a third surface 52c and a fourth surface 52d perpendicular to the height direction x and facing in the first direction y, and a fifth surface 52e and a sixth surface 52f perpendicular to the height direction x and the first direction y and facing in the second direction z. In this case, the first spacer 52 may have a truncated quadrangular pyramid shape in which the area of ​​the second surface 52b is smaller than the area of ​​the first surface 52a.

[0075] The second surface 52b of the first spacer 52 is positioned on the mounting surface S side. The first surface 52a of the first spacer 52 is connected to the first external electrode 30a. Furthermore, the edge portion of the first spacer 52 that is closest to the center of the multilayer ceramic capacitor 10 in the first direction y is positioned closer to the center than the end portion of the first external electrode 30a that is closest to the center of the multilayer ceramic capacitor 10 in the first direction y. Furthermore, the ridge portion of the first spacer 52 where the first surface 52a and the fourth surface 52d of the first spacer 52 intersect is positioned closer to the center in the first direction y than the end portion of the first external electrode 30a that is closest to the center of the multilayer ceramic capacitor 10 in the first direction y. Therefore, the first spacer 52 has, on the first surface 52a, a portion that contacts the first external electrode 30a and a portion that extends from the portion that contacts the first external electrode 30a toward the center in the first direction y.

[0076] The second spacer 54 has a first surface 54a and a second surface 54b facing in the height direction x, a third surface 54c and a fourth surface 54d perpendicular to the height direction x and facing in the first direction y, and a fifth surface 54e and a sixth surface 54f perpendicular to the height direction x and the first direction y and facing in the second direction z. In this case, the second spacer 54 may have a truncated quadrangular pyramid shape such that the area of ​​the second surface 54b is smaller than the area of ​​the first surface 54a.

[0077] The second surface 54b of the second spacer 54 is located on the mounting surface S side. The first surface 54a of the second spacer 54 is connected to the second external electrode 30b. Furthermore, the edge portion of the second spacer 54 that is closest to the center of the multilayer ceramic capacitor 10 in the first direction y is located closer to the center than the end portion of the second external electrode 30b that is closest to the center of the multilayer ceramic capacitor 10 in the first direction y. Furthermore, the ridge portion of the second spacer 54 where the first surface 54a and the fourth surface 54d intersect is located closer to the center in the first direction y than the end portion of the second external electrode 30b that is closest to the center of the multilayer ceramic capacitor 10 in the first direction y. Therefore, the second spacer 54 has, on the first surface 54a, a portion that contacts the second external electrode 30b and a portion that extends from the portion that contacts the second external electrode 30b toward the center in the first direction y.

[0078] By arranging the first spacer 52 and the second spacer 54 between the multilayer ceramic capacitor 10 and the mounting surface S, the distance between the inner layer portion 18, which is the capacitance forming portion of the multilayer ceramic capacitor 10, and the mounting surface S can be increased, thereby suppressing "squeak".

[0079] In this case, although it depends on the dimension T in the height direction x of the multilayer ceramic capacitor 10, the dimension of the first spacer 52 and the second spacer 54 in the height direction x is preferably, for example, 120 μm or more and 250 μm or less. For example, when the dimension L in the first direction y of the multilayer ceramic capacitor 10 is 1.6 mm, the dimension W in the second direction z of the multilayer ceramic capacitor 10 is 0.8 mm, and the dimension T in the height direction x of the multilayer ceramic capacitor 10 is 0.8 mm, the dimension of the first spacer 52 and the second spacer 54 in the height direction x is preferably approximately 160 μm. For example, when the dimension L in the first direction y of the multilayer ceramic capacitor 10 is 2.0 mm and the dimension W in the second direction z of the multilayer ceramic capacitor 10 is 1.25 mm, the dimension in the direction perpendicular to the mounting surface of the multilayer ceramic electronic component 100 is preferably approximately 1.60 mm. Furthermore, the first spacer 52 and the second spacer 54 may have portions with irregularities. If the shapes of the first spacer 52 and the second spacer 54 cause some unevenness, it is preferable that the minimum thickness of the first spacer 52 and the second spacer 54 in the height direction x is approximately 120 μm. Various dimensions are defined by the longest dimension in the first direction y, the second direction z, and the direction x perpendicular to the mounting surface. It is preferable that the distance between the first spacer 52 and the second spacer 54 in the first direction y be 0.4 mm or more.

[0080] As shown in Figure 6, the first spacer 52 and the second spacer 54 include a metal region M formed from metal powder. The metal powder preferably contains at least one of Cu, Ni, and Sn. In addition, Ag may also be contained. The intermetallic compound formed by Cu, Ni, and Sn is less likely to deform due to heat and can easily maintain its shape when soldering is performed to mount the multilayer ceramic electronic component on a substrate.

[0081] In addition, as shown in FIG. 6 , the first spacer 52 and the second spacer 54 have a resin region R formed by a resin component. The resin component can relieve stress. More preferably, the resin component is 5 wt % or more and 15 wt % or less. The resin component is a phenolic resin. The phenolic resin coats the particles of the intermetallic compound and is interspersed so as to fill the gaps between the particles. When the first spacer 52 and the second spacer 54 contain a phenolic resin, the phenolic resin coats the particles of the metal powder and is interspersed so as to fill the gaps between the particles. The phenolic resin may not completely coat the particles of the intermetallic compound. The phenolic resin has good heat resistance, making it less likely to volatilize at the heat treatment temperature used in the heat treatment process for forming the first spacer 52 and the second spacer 54. This reduces the amount of voids formed within the spacers.

[0082] The phenolic resin may be exposed on the surfaces of the first spacer 52 and the second spacer 54, and may cover at least a portion of the surfaces of the first spacer 52 and the second spacer 54. By covering the surfaces of the first spacer 52 and the second spacer 54 with the phenolic resin, the smoothness of the surfaces of the first spacer 52 and the second spacer 54 is improved, and the mechanical strength of the first spacer 52 and the second spacer 54 can be increased.

[0083] Examples of the phenol resin include novolac-type phenol resins such as phenol novolac resin, phenol aralkyl resin, cresol novolac resin, Tcrt-butylphenol novolac resin, and nonylphenol novolac resin; resol-type phenol resin; and polyoxystyrene such as polyparaoxystyrene.

[0084] Furthermore, the first spacer 52 and the second spacer 54 may be configured to contain metal powder in resin. If the resin component is contained in a larger amount than the metal powder, the resin component can buffer the vibration of the multilayer ceramic capacitor 10, thereby reducing the vibration transmitted to the substrate. In this case, the surfaces of the first spacer 52 and the second spacer 54 may be plated.

[0085] Furthermore, a plurality of voids P are arranged inside the first spacer 52 and the second spacer 54 .

[0086] In this embodiment, the metal component ratio of the entire first spacer 52 and the entire second spacer 54 is 86.4% or more and 94.3% or less. Here, the metal component ratio of the entire first spacer 52 and the entire second spacer 54 refers to the proportion of the metal region M in the exposed cross section of the first spacer 52 and the second spacer 54 in the first direction y × height direction x.

[0087] 6 , in an exposed cross section of the first spacer 52 in the first direction y × height direction x, when the first spacer 52 is divided into a central region A and a peripheral region B disposed around the central region A, the metal component ratio, which is the ratio of the metal region M in the central region A, is 91.6% or more and 94.2% or less. Similarly, in an exposed cross section of the second spacer 54 in the first direction y × height direction x, when the second spacer 54 is divided into the central region A and the peripheral region B disposed around the central region A, the metal component ratio, which is the ratio of the metal region M in the central region A, is 91.6% or more and 94.2% or less. This improves the adhesive strength between the third spacer 56 and the first spacer 52, which will be described later, and the connectivity with the solder, thereby reducing the possibility that the multilayer ceramic electronic component will become detached from the substrate after mounting, and the first spacer 52, the second spacer 54, and the multilayer ceramic capacitor will become detached from the substrate after mounting, and can also prevent the multilayer ceramic electronic component 100 from becoming detached from the substrate after mounting on the substrate.

[0088] The metal component ratio, which is the ratio of the metal region M to the peripheral region B, is preferably 64.2% or more and 97.4% or less.

[0089] The method for measuring the metal component ratio in each region is described below. The cross section of the multilayer ceramic electronic component is polished in the second direction z to a position 1 / 2W to expose a cross section in the first direction y × height direction x. Then, using ImageJ (image processing software), the image is cropped to surround the outlines of the first spacer 52 and the second spacer 54. The image type of ImageJ is set to 8 bits. The central region A is a rectangular region measuring 300 μm × 100 μm. Any region not overlapping the outlines of the first spacer 52 and the second spacer 54 is defined as the central region A, and the region between the central region A and the outlines of the first spacer 52 and the second spacer 54 is defined as the peripheral region B. The central region A, specified as a rectangular region measuring 300 μm × 100 μm, is defined as any region 10 μm inward from the outlines of the first spacer 52 and the second spacer 54. Then, for the obtained image, a threshold value is set in the range of 0 to 140 so that the positions of the voids P and the resin R become white. Then, by performing binarization using the set threshold value, particle analysis is performed from the area of ​​each of the metal regions M and other regions, and the area ratio of the metal component (metal component ratio) is measured.

[0090] The components of the first spacer 52 and the second spacer 54 can be detected, for example, as follows. The multilayer ceramic electronic component 100 is cross-polished perpendicular to the mounting surface S and up to ½W of the second direction z to expose a cross-section (LT plane) in the height direction x and the first direction y. The components of the first spacer 52 and the second spacer 54 can be detected by qualitative analysis using EDX with an FE-SEM (SU8230, manufactured by Hitachi High-Technologies Corporation) obtained by cross-polishing. The cross-section obtained by cross-polishing can be magnified 50 times with a microscope (BX-51, manufactured by Olympus Corporation) and photographed with a microscope digital camera (DP22, manufactured by Olympus Corporation). This allows the metal types in the first spacer 52 and the second spacer 54 to be observed, and, if plating is present on the first spacer 52 and the second spacer 54, the differences in the metal types of the plating. Furthermore, without being limited to this, by taking photographs using a microscope (Axio (registered trademark)-Imager-MAT manufactured by ZEISS) at a total magnification of 100 times or more and 500 times or less, it is also possible to observe the difference in the metal type within the first spacer 52 and the second spacer 54, or the difference in the metal type of plating if plating is present on the first spacer 52 and the second spacer 54. In addition to this, cross-section polishing may be performed up to ½W in the second direction z.

[0091] (Third Spacer) The third spacer 56 covers a portion of the laminate 12, a portion of the first spacer 52, and a portion of the second spacer 54. More specifically, when viewed in a direction perpendicular to the mounting surface S, the third spacer 56 covers the first spacer 52. Similarly, when viewed in a direction perpendicular to the mounting surface S, the third spacer 56 covers the second spacer 54. For example, the third spacer 56 covers the fourth surface 52d of the first spacer 52 and the fourth surface 54d of the second spacer 54. In this case, a portion of the third spacer 56 may be disposed so as to extend into the first spacer 52. This can further improve the adhesive strength between the first spacer 52 and the third spacer 56. Furthermore, a portion of the third spacer 56 may be disposed so as to extend into the second spacer 54. This can further improve the adhesive strength between the second spacer 54 and the third spacer 56.

[0092] In this case, the third spacer 56 is preferably disposed so as to be inserted between the first spacer 52 and the laminate 12, and between the second spacer 54 and the laminate 12. The third spacer 56 preferably continuously covers the surface of the laminate 12. This allows the distance between the center of the laminate 100 in the first direction y, where vibration occurs most, and the laminated ceramic electronic component 100 to be increased, thereby reducing the possibility of contact between the mounting substrate and the laminated ceramic electronic component 100.

[0093] It is preferable that the color of the multilayer ceramic electronic component 100 be different when viewed from the bottom surface (mounting surface) than when viewed from the top surface (non-mounting surface). The different colors make it easier to select the direction when mounting the component on a substrate, and can reduce the number of times the multilayer ceramic electronic component 100 is mounted on a surface other than the surface on which it should be mounted.

[0094] The third spacer 56 includes, for example, carbon, Co, Al, Cu, N, or Cr. In addition, the third spacer 56 may include an epoxy resin, a hardener, or another organic solvent.

[0095] For example, when the third spacer 56 contains a large amount of carbon, the hue of the third spacer 56 can be made closer to black. Also, when the third spacer 56 contains a large amount of Co, Al, or Cr, the hue of the third spacer 56 can be made closer to blue. In addition, the hue can be changed by using various other materials.

[0096] The content of the various materials for changing the hue is preferably 0.1 wt % to 5.0 wt % based on the solid content of the third spacer 56, i.e., the amount of solid content excluding solvent (epoxy resin, phenolic resin), additives (coupling agent, catalyst), and inorganic materials (silica, alumina)). If the weight ratio is too small, the hue change may be insufficient, and the image may not be correctly recognized during image processing. Furthermore, if the weight ratio is too large, the third spacer 56 may cause electrical conduction between the first external electrode 30a and the second external electrode 30b, or between the first spacer 52 and the second spacer 54. Depending on the distribution of the various materials, there may be areas with partially different hues. However, even in such cases, directional selection is possible as long as the hues are sufficiently different. It is preferable that the hue be different over at least half of the area of ​​the region between the first spacer 52 and the second spacer 54 on the mounting surface.

[0097] To distinguish between the portion where the third spacer 56 is present and the other portions, a method for measuring the hue of the mounting surface side and the non-mounting surface side of the multilayer ceramic electronic component 100 will be described. The first surface 12a, which is the non-mounting surface side, and the second surface 12b, which is the mounting surface side, of the multilayer ceramic electronic component 100 are measured using a digital microscope (Keyence Corporation, VHX-6000) (RGB measurement). The measurement conditions are brightness set to auto "100," gain set to auto "100," and ring removal set to "medium" for reflection removal. The mounting surface side is measured on 1 / 2W of the multilayer ceramic electronic component 100, 1 / 2L of the multilayer ceramic electronic component 100, the contact point between the first spacer 52 and the laminate 12, and the contact point between the second spacer 54 and the laminate 12. Furthermore, on the non-mounting surface, measurements are made on ½ W of the multilayer ceramic electronic component 100, ½ L of the multilayer ceramic electronic component 100, near the contact points between the first external electrode 30 a and the laminate 12, and near the contact points between the second external electrode 30 b and the laminate 12. When the mounting surface and non-mounting surface of the multilayer ceramic electronic component 100 are measured, a difference in hue is defined as being 10 or more in any of the R, G, and B values. In this case, a difference in hue at even one of the measurement points is considered to be a difference in hue.

[0098] 1 , the metal component ratio of the entire first spacer 52 is 86.4% or more and 94.3% or less. Furthermore, when the first spacer 52 is divided into a central region A and a peripheral region B surrounding the central region A at least in a cross section of the first spacer 52 exposed in the first direction y × height direction x, the metal component ratio, which is the ratio of the metal region M in the central region A, is 91.6% or more and 94.2% or less. This improves the adhesive strength between the first spacer 52 and the multilayer ceramic capacitor 10, thereby preventing the first spacer 52 from coming off the multilayer ceramic capacitor 10. Similarly, the metal component ratio of the entire second spacer 54 is 86.4% or more and 94.3% or less. Furthermore, when the second spacer 54 is divided into a central region A and a peripheral region B arranged around the central region A, at least in the exposed cross section of the second spacer 54 in the first direction y × height direction x, if the metal component ratio, which is the proportion of the metal region M in the central region A, is 91.6% or more and 94.2% or less, the adhesive strength between the second spacer 54 and the multilayer ceramic capacitor 10 can be improved, and therefore, the second spacer 54 can be prevented from coming off the multilayer ceramic capacitor 10.

[0099] 2. Method for Manufacturing Multilayer Ceramic Electronic Components Next, a method for manufacturing multilayer ceramic electronic components will be described.

[0100] First, a conductive paste for the dielectric sheet and the internal electrodes is prepared. The conductive paste for the dielectric sheet and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0101] Next, a dielectric sheet on which no internal electrode pattern is printed and a dielectric sheet on which a conductive paste for the internal electrodes is printed in a predetermined pattern by, for example, screen printing or gravure printing are prepared, thereby preparing a dielectric sheet on which a first internal electrode pattern is printed and a dielectric sheet on which a second internal electrode pattern is printed.

[0102] Next, a predetermined number of dielectric sheets on which no internal electrode pattern is printed are laminated, and dielectric sheets on which the first internal electrode pattern and the second internal electrode pattern are printed are laminated in order thereon to form a portion that will become the inner layer portion 18. Furthermore, a predetermined number of dielectric sheets on which no internal electrode pattern is printed are laminated on the portion that will become the inner layer portion 18 to produce a laminated sheet.

[0103] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0104] Next, the laminated block is cut to a predetermined size to cut out laminated chips, and at this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0105] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the materials of the dielectric layers 14 and the internal electrodes 16, but is preferably 900°C or higher and 1400°C or lower.

[0106] Next, a conductive paste that will become the base electrode layer 32 is applied to the third surface 12c and the fourth surface 12d of the laminate 12 to form the base electrode layer 32. In this embodiment, a baked layer is formed as the base electrode layer 32. When forming the baked layer, a conductive paste containing a glass component and a metal is applied by a method such as dipping, and then a baking process is performed to form the base electrode layer 32. The temperature of the baking process at this time is preferably 700°C or higher and 900°C or lower.

[0107] When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of a baked layer, or the conductive resin layer may be formed directly on the laminate without forming a baked layer.

[0108] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate, followed by heat treatment at a temperature of 250°C to 550°C to thermally cure the thermosetting resin and form the conductive resin layer. The heat treatment is preferably performed in an N2 atmosphere. Furthermore, to prevent scattering of the thermosetting resin and oxidation of the various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0109] When the base electrode layer 32 is formed as a thin film layer, the base electrode layer 32 can be formed by a thin film formation method such as sputtering or vapor deposition. The base electrode layer 32 formed as a thin film layer is a layer of metal particles deposited to a thickness of 1 μm or less.

[0110] Furthermore, the plating layer 34 may be provided on the exposed portion of the internal electrode 16 of the laminate 12 without providing the base electrode layer 32. In this case, the plating layer 34 can be formed by the following method.

[0111] The third surface 12c and the fourth surface 12d of the laminate 12 are plated to form a base plated electrode on the exposed portion of the internal electrode 16. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating requires pretreatment using a catalyst or the like to improve the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferred. Barrel plating is preferably used as the plating method. If necessary, an upper plated electrode may be formed on the surface of the lower plated electrode in the same manner.

[0112] Thereafter, a plating layer 34 is formed on the surface of the base electrode layer 32, the surface of the conductive resin layer or the surface of the lower-layer plating electrode, and the surface of the upper-layer plating electrode. In this embodiment, a Ni plating layer and a Sn plating layer are formed on the baked layer. The Ni plating layer and the Sn plating layer are formed sequentially by, for example, barrel plating.

[0113] In this manner, the multilayer ceramic capacitor 10 is manufactured.

[0114] Next, a method for arranging the first spacers 52 and the second spacers 54 in the multilayer ceramic capacitor 10 will be described.

[0115] A first spacer manufacturing paste used to manufacture the first spacer 52 and a second spacer manufacturing paste used to manufacture the second spacer 54 are prepared. The first spacer manufacturing paste and the second spacer manufacturing paste contain, for example, a metal including at least one of Cu, Ni, Sn, Ag, etc., and a resin component. However, this is not limited thereto, and the first spacer manufacturing paste and the second spacer manufacturing paste may be composed of a conductive paste. Next, the first spacer manufacturing paste and the second spacer manufacturing paste are placed on a holding substrate (e.g., an alumina plate) by screen printing, dispensing, or the like. Next, the multilayer ceramic capacitor 10 is placed on top of the spacer manufacturing paste in an orientation facing the holding substrate. At this time, the first external electrode 30a and the first spacer manufacturing paste, and the second external electrode 30b and the second spacer manufacturing paste are aligned, and the first spacer manufacturing paste and the second spacer manufacturing paste are applied to the multilayer ceramic capacitor 10.

[0116] Thereafter, a heat treatment is performed to form the first spacers 52 and the second spacers 54. By appropriately adjusting the heating temperature, TOP temperature, or heat treatment time in this heat treatment, the overall metal component ratio of each of the first spacers 52 and the second spacers 54 can be set to 86.4% or more and 94.3% or less, and the metal component ratio of the peripheral region B of each of the first spacers 52 and the second spacers 54 can be set to 64.2% or more and 97.4% or less. The heat treatment temperature for the first spacers 52 and the second spacers 54 is 200°C or more and 300°C or less in an N2 atmosphere, and the first spacers 52 and the second spacers 54 are formed by controlling the heating rate. If the heating rate and the heat treatment conditions are not controlled, heat is easily transferred from the outside of the first spacers 52 and the second spacers 54, which may result in an excessively high porosity as a whole.

[0117] Alternatively, the first spacer 52 and the second spacer 54 can be disposed on the multilayer ceramic capacitor 10 by the following method: The multilayer ceramic capacitor 10 is disposed on a holding substrate (e.g., an alumina plate) using an adhesive. Each spacer manufacturing paste is disposed on the external electrodes 30 of the multilayer ceramic capacitor 10 disposed on the holding substrate by screen printing, dispensing, or the like. The first external electrode 30a and the first spacer manufacturing paste, and the second external electrode 30b and the second spacer manufacturing paste are aligned, and the first spacer manufacturing paste and the second spacer manufacturing paste are attached to the multilayer ceramic capacitor 10.

[0118] In the spacer placement step, the first spacers 52 and second spacers 54 can be formed in a desired shape and in a desired placement by changing the amount of paste or the design of the mask.

[0119] Thereafter, heat treatment is performed to form the first spacers 52 and the second spacers 54. By appropriately adjusting the temperature rise and TOP temperature in this heat treatment, or the time for performing the heat treatment, the overall metal component ratio of each of the first spacers 52 and the second spacers 54 can be set to 86.4% or more and 94.3% or less, and the metal component ratio of the peripheral region B of each of the first spacers 52 and the second spacers 54 can be set to 64.2% or more and 97.4% or less.

[0120] Next, a method for arranging the third spacer 56 in the multilayer ceramic capacitor 10 will be described.

[0121] The surface of the multilayer ceramic capacitor 10 on which the first spacers 52 and the second spacers 54 are disposed is cleaned with a solvent. After the cleaning is completed, the multilayer ceramic capacitor 10 on which the first spacers 52 and the second spacers 54 are disposed is aligned so that the first spacers 52 and the second spacers 54 face upward.

[0122] Next, a paste for manufacturing the third spacers 56 is prepared. The paste for manufacturing the third spacers 56 is composed of an insulating paste. The color of the third spacers 56 can be changed by adding various materials as additives.

[0123] Next, with respect to the multilayer ceramic capacitor 10 on which the first spacers 52 and second spacers 54 have been arranged, a dispenser or squeegee printing is used to form a third spacer 56 between the first spacer 52 and the second spacer 54. The amount of wetting of the first spacer 52 and the second spacer 54 can be changed by adjusting the amount of the paste for manufacturing the third spacer.

[0124] When the third spacer 56 is inserted between the laminate 12 and the first spacer 52, or between the laminate 12 and the second spacer 54, the third spacer 56 can be inserted by evacuating after placing the paste for manufacturing the third spacer. The amount of insertion can be controlled by changing the time and pressure of the evacuation.

[0125] Then, the chip on which the third spacer 56 is formed on the multilayer ceramic capacitor 10 on which the first spacer 52 and the second spacer 54 are arranged is heated at a temperature of 100°C or higher and 200°C or lower for 20 minutes or higher and 80 minutes or lower.

[0126] Through the above steps, the multilayer ceramic electronic component 100 of this embodiment is manufactured.

[0127] 3. Experimental Example Next, in order to confirm the effects of the multilayer ceramic electronic component according to the present invention described above, multilayer ceramic electronic components in which the metal component ratio in the peripheral region B of the first spacer was varied were produced as experimental samples according to the manufacturing method described above, and a drop test was performed.

[0128] (1) Specifications of the multilayer ceramic capacitors fabricated as samples of experimental examples Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors provided in the multilayer ceramic electronic components, which are samples No. 1 to No. 6, were fabricated. - Dimensions of the multilayer ceramic capacitor (design values) L dimension: 1.6 mm ± 0.1 mm W dimension: 0.8 mm ± 0.1 mm T dimension: 0.8 mm ± 0.1 mm - Ceramic material: BaTiO3 - Material of internal electrodes: Ni - Base electrode layer of external electrodes: Conductive metal (Cu) and glass component - Plating layer Two layers formed of Ni plating layer and Sn plating layer Ni plating layer thickness: Approximately 3 μm Sn plating layer thickness: Approximately 5 μm

[0129] (2) Specifications of Spacers of Multilayer Ceramic Electronic Components as Samples of Experimental Examples Using the manufacturing method according to the above embodiment, spacers of multilayer ceramic electronic components, which are samples Nos. 1 to 6, were formed. - Dimension of the first and second spacers in the first direction: 0.45 mm ± 0.05 mm - Dimension of the first and second spacers in the second direction: 0.85 mm ± 0.05 mm - Dimension of the first and second spacers in the height direction: 0.15 mm ± 0.05 mm - Amount of resin to form the third spacer after hardening: 10 μg - Ingredients of the first and second spacers: 31.5 wt% Cu-10 wt% Ni powder with a D50 of 5 μm, 58.5 wt% solder powder with a composition of Sn-3 wt% Ag-0.5 wt% Cu, and 10 wt% in total of phenolic resin, solvent, and additive ingredients - Ingredients of the third spacer: epoxy resin, phenolic resin, additives (coupling agent, catalyst), inorganic substances (silica, alumina), pigment

[0130] The metal component ratios of the central region A in the first spacer for sample numbers 1 to 6 are shown in Table 1. The metal component ratios of the central region A in the first spacer for each of sample numbers 4 to 6 were within the range of 91.6% to 94.2%, and the area ratio of the metal region M of the entire first spacer was within the range of 86.4% to 94.35%. On the other hand, the metal component ratios of the entire first spacer for each of sample numbers 1 to 3 were outside the range of 86.4% to 94.3%.

[0131] (3) Method for Measuring the Metal Component Ratio in the Entire Cross Section of the First Spacer and the Metal Component Ratio in the Central Region A The metal component ratio for each sample was calculated as follows. First, the cross section of the multilayer ceramic electronic component corresponding to each sample number was polished in the second direction z to expose the cross section in the first direction y × height direction x. Then, using ImageJ (image processing software), an image was cropped to surround the outline of the first spacer. The image type of ImageJ was set to 8-bit. The central region A was a rectangular region measuring 300 μm × 100 μm, and any region not overlapping the outlines of the first spacer and the second spacer was defined as the central region A. The region between the central region A and the outlines of the first spacer and the second spacer was defined as the peripheral region B. The central region A, identified as a rectangular region measuring 300 μm × 100 μm, was defined as any region 10 μm inward from the outline of the first spacer. Then, for the obtained image, a threshold value was set in the range of 0 to 140 so that the positions of the voids P and the resin R would appear white. Then, by binarizing the image using the set threshold value, particle analysis was performed on the areas of the metal regions M and other regions, and the ratio of the metal component was measured.

[0132] (4) Drop test method Each of the above samples of multilayer ceramic electronic components was dropped to a drop height of 0.0150 mm. 3 The multilayer ceramic electronic components were mounted on an evaluation board as they were. Then, the components were dropped 60 times from a height of 1.5 m with the evaluation board facing downwards, and the number of multilayer ceramic electronic components that came off the evaluation board was counted. The number of samples used in the drop test was 100 for each sample number. (5) Results Table 1 shows the results of the drop test for the multilayer ceramic electronic components of sample numbers 1 to 6, with respect to the change in the metal component ratio in the peripheral region B.

[0133]

[0134] According to Table 1, for each of samples No. 4 to No. 6, when the metal component ratio in the central region A was 91.6% or more and 94.2% or less, the drop test showed that the number of multilayer ceramic capacitors of each sample that came off the evaluation board was 0.

[0135] On the other hand, the metal component ratios in the central region A of each of Sample Nos. 1 to 3 were 79.3%, 81.7%, and 84.9%, respectively, which were less than 91.6%, and therefore, as a result of the drop test, 8 or more of 100 multilayer ceramic electronic components for each sample came off the evaluation substrate.

[0136] The above results suggest that in this invention, when the metal component ratio of the entire first spacer is in the range of 86.4% or more and 94.3% or less, the metal component ratio of the central region A of the first spacer is in the range of 91.6% or more and 94.2% or less, and the adhesive strength of the multilayer ceramic electronic component to the substrate can be improved.

[0137] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited to this.

[0138] In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc. without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0139] REFERENCE SIGNS LIST 100 Multilayer ceramic electronic component 10 Multilayer ceramic capacitor 12 Laminate 12a First surface 12b Second surface 12c Third surface 12d Fourth surface 12e Fifth surface 12f Sixth surface 14 Dielectric layer 16 Internal electrode 16a First internal electrode 16b Second internal electrode 18 Internal layer portion 20a First outer layer portion 20b Second outer layer portion 26 Counter electrode portion 26a First counter electrode portion 26b Second counter electrode portion 28 Lead electrode portion 28a First lead electrode portion 28b Second lead electrode portion 30 External electrode 30a First external electrode 30b Second external electrode 32 Base electrode layer 32a First base electrode layer 32b Second base electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 50 Spacer 52 First spacer 52a First surface of first spacer 52b Second surface of first spacer 52c Third surface of first spacer 52d Fourth surface of first spacer 52e Fifth surface of first spacer 52f Sixth surface of first spacer 54 Second spacer 54a First surface of second spacer 54b Second surface of second spacer 54c Third surface of second spacer 54d Fourth surface of second spacer 54e Fifth surface of second spacer 54f Sixth surface of second spacer 56 Third spacer 60 Mounting substrate 62 Solder x Height direction (stacking direction) y First direction z Second direction (longitudinal direction) T Height direction dimension of multilayer ceramic capacitor W Second direction dimension of multilayer ceramic capacitor L Dimension t in the first direction of the multilayer ceramic capacitor s Height dimension S of the first spacer and the second spacer Mounting surface

Claims

1. A multilayer ceramic electronic component comprising: a laminate having first and second surfaces that face each other in a height direction, third and fourth surfaces that face each other in a first direction perpendicular to the height direction, and fifth and sixth surfaces that face each other in a second direction perpendicular to the height direction and the first direction; first external electrodes arranged on the second and third surfaces of the laminate; and second external electrodes arranged on the second and fourth surfaces of the laminate; a first spacer connected to the first external electrodes, a second spacer connected to the second external electrodes, and a third spacer arranged between the first and second spacers, wherein the first spacer has a central region and a peripheral region located around the central region, and the metal component ratio of the first spacer is 86.4% or more and 94.3% or less, and the metal component ratio of the peripheral region is 64.2% or more and 97.4% or less.

2. A multilayer ceramic electronic component comprising: a laminate having a first surface and a second surface opposing each other in a height direction, a third surface and a fourth surface opposing each other in a first direction perpendicular to the height direction, and a fifth surface and a sixth surface opposing each other in a second direction perpendicular to the height direction and the first direction; first external electrodes disposed on the first surface and the third surface of the laminate; and second external electrodes disposed on the first surface and the fourth surface of the laminate; a first spacer connected to the first external electrodes; a second spacer connected to the second external electrodes; and a third spacer disposed between the first spacer and the second spacer, wherein the metal component ratio of the first spacer is 86.4% or more and 94.3% or less.

3. A multilayer ceramic electronic component according to claim 1 or 2, wherein the third spacer is disposed so as to be embedded within the first spacer.

4. A multilayer ceramic electronic component according to claim 1 or 2, wherein the third spacer is disposed between the laminate and the first spacer.

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