Display panel, electronic device including same, and method for manufacturing display panel

Abstract

This display panel includes a plurality of light-emitting elements, and a plurality of pixel drivers electrically connected to the light-emitting elements, respectively. Each of the pixel drivers includes a first transistor including a first oxide semiconductor pattern, a second transistor connected to the first transistor and including a second oxide semiconductor pattern, and a capacitor electrically connected to the gate of the first transistor. The first oxide semiconductor pattern has a crystalline structure, and the second oxide semiconductor pattern has an amorphous structure.

Description

Display panel, electronic device including same, and method for manufacturing display panel

[0001] The present invention relates to a display panel, an electronic device including the same, and a method for manufacturing the display panel, and more particularly, to a display panel having improved display characteristics, an electronic device including the same, and a method for manufacturing the display panel.

[0002] A display panel may include a light-emitting element and a pixel driver for driving the light-emitting element. The pixel driver may include a switching transistor and a driving transistor. The switching transistor may have high mobility to have advantageous on-off characteristics. The driving transistor may have a wide driving range to facilitate grayscale expression.

[0003] Accordingly, the present invention aims to provide a display panel including a switching transistor having high mobility and a driving transistor having a wide driving range, an electronic device including the same, and a method for manufacturing the display panel.

[0004] In one embodiment of the present invention, a display panel includes a substrate, a plurality of light-emitting elements arranged on the substrate, and a plurality of pixel drivers electrically connected to the light-emitting elements, each of the pixel drivers including a first transistor including a first oxide semiconductor pattern, a second transistor electrically connected to the first transistor and including a second oxide semiconductor pattern, and a capacitor electrically connected to a gate of the first transistor, wherein the first oxide semiconductor pattern has a crystalline structure and the second oxide semiconductor pattern has an amorphous structure.

[0005] The first transistor may be a driving transistor and the second transistor may be a switching transistor.

[0006] The above first oxide semiconductor pattern may include at least one of indium, gallium, and zinc.

[0007] The above second oxide semiconductor pattern may include at least one of indium, tin, gallium, and zinc.

[0008] The second oxide semiconductor pattern may include indium, tin, gallium, and zinc, and may have a composition ratio of about 60-80 wt% of indium, 0.5-8 wt% of tin, 5-15 wt% of gallium, and 10-30 wt% of zinc within the second oxide semiconductor pattern.

[0009] The first oxide semiconductor pattern and the second oxide semiconductor pattern may be arranged on the same layer.

[0010] In one embodiment of the present invention, the display panel further includes a lower conductive layer disposed between the first transistor and the substrate, and a buffer layer disposed between the lower metal layer and the first oxide semiconductor pattern, wherein the first oxide semiconductor pattern and the second oxide semiconductor pattern can be disposed in the buffer layer.

[0011] The source of the first transistor may be electrically connected to the lower conductive layer.

[0012] Each of the first transistor and the second transistor may have a top-gate structure.

[0013] An electronic device according to one embodiment of the present invention includes a display panel and a processor electrically controlling the display panel, wherein the display panel includes a substrate, a light-emitting element disposed on the substrate, a driving transistor disposed on the substrate and electrically connected to the light-emitting element, and a plurality of switching transistors electrically connected to the driving transistor and the light-emitting element, wherein the driving transistor includes a first oxide semiconductor pattern having a crystalline structure, and each of the switching transistors may include a second oxide semiconductor pattern having an amorphous structure.

[0014] Each of the driving transistor and the switching transistor may have a top-gate structure.

[0015] The first oxide semiconductor pattern and the second oxide semiconductor pattern may be arranged on the same layer.

[0016] The source electrodes and drain electrodes of each of the driving transistors and the switching transistors can be arranged on the same layer.

[0017] A display device according to one embodiment of the present invention further includes a buffer layer disposed between the substrate and the driving transistor, and a lower metal layer disposed between the buffer layer and the substrate and overlapping the first oxide semiconductor pattern in a plane, wherein a source of the driving transistor can contact the lower metal layer.

[0018] The above first oxide semiconductor pattern is about 30 It can have charge mobility above.

[0019] The above second oxide semiconductor pattern can have a driving range of about 0.4 V or more.

[0020] A method for manufacturing a display panel according to one embodiment of the present invention includes the steps of forming a first thin film transistor including a first semiconductor pattern on a substrate, forming a second thin film transistor including a second semiconductor pattern spaced apart from the first semiconductor pattern on the substrate, and forming a light emitting element on the substrate, wherein the step of forming the first thin film transistor includes the steps of forming a first semiconductor layer with a first oxide semiconductor material, patterning the first semiconductor layer to form the first semiconductor pattern, and crystallizing the first semiconductor pattern, and the step of forming the second thin film transistor includes the steps of forming a second semiconductor layer with a second oxide semiconductor material on the first semiconductor pattern, and patterning the second semiconductor layer to form the second semiconductor pattern, wherein the second semiconductor pattern may have an amorphous structure.

[0021] The second semiconductor layer may be formed in contact with the first semiconductor pattern.

[0022] The step of patterning the second semiconductor layer includes a step of etching the second semiconductor layer using an etchant, and the first semiconductor pattern can be exposed to the etchant.

[0023] The source, drain, and channel of each of the first semiconductor pattern and the second semiconductor pattern can be formed simultaneously.

[0024] Switching transistors with high mobility and driving transistors with a wide operating range can be simultaneously provided. This enables stable low-gray display and facilitates the design of high-resolution display panels. Furthermore, process reliability for display panel manufacturing can be improved.

[0025] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0026] FIG. 2 is a drawing illustrating an example of a cross-section of the display device illustrated in FIG. 1.

[0027] FIG. 3 is a drawing illustrating an example of a cross-section of the display panel illustrated in FIG. 2.

[0028] Figure 4 is a block diagram of the display device shown in Figure 1.

[0029] FIGS. 5A to 5C are drawings illustrating equivalent circuits of pixels according to one embodiment of the present invention.

[0030] FIG. 6 is a timing diagram of scanning signals and emission signals for explaining the operation of the pixel shown in FIG. 5a.

[0031] Figures 7a to 7d are drawings illustrating cross-sections of some areas of the display panel as examples.

[0032] FIGS. 8A and 8B are graphs showing current-voltage characteristics of a semiconductor pattern according to one embodiment of the present invention.

[0033] FIGS. 9A to 9M are cross-sectional views illustrating a method for manufacturing a display panel according to one embodiment of the present invention.

[0034] FIG. 10 is a block diagram of an electronic device according to one embodiment.

[0035] FIG. 11 is a schematic diagram of an electronic device according to various embodiments.

[0036] In this specification, when it is said that a component (or region, layer, portion, etc.) is “on,” “connected to,” or “coupled to” another component, it means that it can be directly disposed / connected / coupled to the other component, or a third component may be disposed between them.

[0037] Identical drawing numbers indicate identical components. Furthermore, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the purpose of effectively illustrating the technical content.

[0038] “And / or” includes any combination of one or more of the associated constructs that can be defined.

[0039] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0040] Additionally, terms such as "below," "lower," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant technical context, and may be explicitly defined herein, unless interpreted in an idealized or overly formal sense.

[0042] Terms such as "include" or "have" should be understood to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but not to exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0043] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0044] FIG. 1 is a perspective view of an electronic device according to an embodiment of the present invention. As illustrated in FIG. 1, the electronic device (DD) may have long sides extending parallel to a first direction (DR1) and short sides extending parallel to a second direction (DR2) intersecting the first direction (DR1).

[0045] Hereinafter, a direction substantially perpendicular to the plane defined by the first direction (DR1) and the second direction (DR2) is defined as a third direction (DR3). In addition, in this specification, the meaning of when viewed on a plane is defined as a state viewed from the third direction (DR3).

[0046] The front surface of the electronic device (DD) may be defined as a display surface (DS) and may have a plane defined by a first direction (DR1) and a second direction (DR2). Images (IM) generated by the electronic device (DD) may be provided to a user through the display surface (DS).

[0047] The display surface (DS) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may be an area where an image is displayed, and the non-display area (NDA) may be an area where an image is not displayed. The non-display area (NDA) may be adjacent to at least one side of the display area (DA). In the present embodiment, the non-display area (NDA) may have a frame shape surrounding the display area (DA).

[0048] The electronic device (DD) may also detect inputs applied from outside the electronic device (DD). For example, the electronic device (DD) may detect a first input by a touch pen (PEN) and a second input by a touch (TC). In this case, the touch pen (PEN) may be defined as an input device, and the display area (DA) may provide the user with a detection area capable of detecting inputs in addition to displaying an image.

[0049] The touch pen (PEN) may be an active pen or an electromagnetic pen. The second input by the touch (TC) may include various forms of external input, such as a part of the user's body, light, heat, or pressure. The touch pen (PEN) includes an active pen, a passive pen, an electromagnetic pen, and the like, and is not limited to any one embodiment.

[0050] The electronic device (DD) can be used in large electronic devices such as televisions, monitors, or outdoor billboards. Furthermore, the electronic device (DD) can also be used in small and medium-sized electronic devices such as personal computers, laptop computers, personal digital assistants, car navigation systems, game consoles, smartphones, tablets, or cameras. However, this is merely an example, and the electronic device (DD) according to an embodiment of the present invention can be used in various forms and is not limited to any one embodiment.

[0051]

[0052] FIG. 2 is a drawing illustrating a cross-section of the display device illustrated in FIG. 1. FIG. 3 is a drawing illustrating a cross-section of the display panel illustrated in FIG. 2. The present invention will be described with reference to FIGS. 2 and 3.

[0053] Referring to FIG. 2, the electronic device (DD) may include a display panel (DP), an input sensing portion (ISP), an anti-reflection layer (RPL), a window (WIN), a panel protection film (PPF), and first and second adhesive layers (AL1, AL2).

[0054] A display panel (DP) according to an embodiment of the present invention may be an emissive display panel. For example, the display panel (DP) may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots or quantum rods. Hereinafter, the display panel (DP) will be described as an organic light-emitting display panel by way of example.

[0055] Referring to FIG. 3, the display panel (DP) may include a substrate (SUB), a circuit element layer (DP-CL) disposed on the substrate (SUB), a display element layer (DP-OLED) disposed on the circuit element layer (DP-CL), and a thin film encapsulation layer (TFE) disposed on the display element layer (DP-OLED).

[0056] The substrate (SUB) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The substrate (SUB) may include glass or a flexible plastic material such as polyimide (PI). A display element layer (DP-OLED) may be disposed on the display area (DA).

[0057] A plurality of pixels may be arranged on the circuit element layer (DP-CL) and the display element layer (DP-OLED). Each pixel may include a transistor arranged on the circuit element layer (DP-CL) and a light-emitting element arranged on the display element layer (DP-OLED) and connected to the transistor.

[0058] A thin film encapsulation layer (TFE) may be disposed on a circuit element layer (DP-CL) to cover a display element layer (DP-OLED). The thin film encapsulation layer (TFE) may protect pixels from moisture, oxygen, and external foreign substances. Meanwhile, in the present embodiment, the thin film encapsulation layer (TFE) is illustrated as covering the entire area of ​​the substrate (SUB), but according to an embodiment of the present invention, the substrate (SUB) may include a portion exposed from the thin film encapsulation layer (TFE). Alternatively, the area exposed from the thin film encapsulation layer (TFE) may be formed along the edge of the substrate (SUB), and is not limited to any one embodiment.

[0059] An input sensing unit (ISP) may be arranged on a display panel (DP). The input sensing unit (ISP) may include a plurality of sensing units (not shown) for sensing an external input in a capacitive manner. The input sensing unit (ISP) may be formed directly on the display panel (DP) during the manufacturing of the electronic device (DD). Specifically, a conductive pattern or an insulating layer constituting the input sensing unit (ISP) may be directly deposited or patterned on the display panel (DP). However, the present invention is not limited thereto, and the input sensing unit (ISP) may be manufactured as a separate panel from the display panel (DP) and attached to the display panel (DP) via an adhesive layer, and is not limited to any one embodiment.

[0060] An anti-reflection layer (RPL) may be disposed on an input sensing unit (ISP). The anti-reflection layer (RPL) may reduce external light reflectance of the electronic device (DD) to improve the visibility of an image displayed on the electronic device (DD). The anti-reflection layer (RPL) may include a phase retarder, a polarizer, a black matrix, a color filter, and the like, and is not limited to any one embodiment. The anti-reflection layer (RPL) may be directly formed on the input sensing unit (ISP) through a coating or deposition process, or may be provided in a film form and attached to the input sensing unit (ISP) through an adhesive layer, and is not limited to any one embodiment.

[0061] The window (WIN) can be placed on an anti-reflection layer (RPL). The window (WIN) can protect the display panel (DP), the input sensor (ISP), and the anti-reflection layer (RPL) from external scratches and impacts.

[0062] A panel protection film (PPF) may be placed under a display panel (DP). The panel protection film (PPF) may support the display panel (DP) and protect the lower portion of the display panel (DP). The panel protection film (PPF) may have insulating properties. For example, the panel protection film (PPF) may include, but is not limited to, a plastic such as polyethylene terephthalate (PET), polyimide (PI), or polypropylene (PP).

[0063] A first adhesive layer (AL1) is disposed between a display panel (DP) and a panel protection film (PPF), and the display panel (DP) and the panel protection film (PPF) can be bonded to each other by the first adhesive layer (AL1). A second adhesive layer (AL2) is disposed between a window (WIN) and an anti-reflection layer (RPL), and the window (WIN) and the anti-reflection layer (RPL) can be bonded to each other by the second adhesive layer (AL2).

[0064]

[0065] Fig. 4 is a block diagram of the display device illustrated in Fig. 1. Referring to Fig. 4, the electronic device (DD) may include a display panel (DP), a timing controller (TC), a scan driver (SDV), a data driver (DDV), an emission driver (EDV), and a voltage generator (VG).

[0066] The display panel (DP) may include a plurality of scanning lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm), a plurality of light emitting lines (EML1 to EMLm), a plurality of data lines (DL1 to DLn), and a plurality of pixels (PX). m and n are natural numbers.

[0067] The pixels (PX) can be electrically connected to scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm), emission lines (EML1 to EMLm), and data lines (DL1 to DLn), respectively. Each of the pixels (PX) can be electrically connected to four corresponding scan lines, one corresponding data line, and one corresponding emission line.

[0068] The scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) may include a plurality of initialization scan lines (GIL1 to GILm), a plurality of compensation scan lines (GCL1 to GCLm), a plurality of write scan lines (GWL1 to GWLm), and a plurality of bias scan lines (GBL1 to GBLm).

[0069] Each of the pixels (PX) can be connected to a corresponding one of the initialization scan lines (GIL1 to GILm), a corresponding one of the compensation scan lines (GCL1 to GCLm), a corresponding one of the write scan lines (GWL1 to GWLm), and a corresponding one of the bias scan lines (GBL1 to GBLm).

[0070] The scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) are connected to the scan driver (SDV), extend in a first direction (DR1), and can be arranged in a second direction (DR2). The light emitting lines (EML1 to EMLm) are connected to the light emitting driver (EDV), extend in a first direction (DR1), and can be arranged in a second direction (DR2). The data lines (DL1 to DLn) are connected to the data driver (DDV), extend in a second direction (DR2), and can be arranged in the first direction (DR1).

[0071] In the present embodiment, the scan driver (SDV), the emission driver (EDV), and the data driver (DDV) may be substantially arranged on the display panel (DP). However, this is merely an example, and at least one of the scan driver (SDV), the emission driver (EDV), and the data driver (DDV) may be provided on a separate circuit board and electrically connected to the display panel (DP) to provide electrical signals to the pixels (PX), and is not limited to any one embodiment.

[0072] The timing controller (TC) can receive a video signal (RGB) and a control signal (CTRL). The timing controller (TC) can generate a video data signal (DAS) by converting the data format of the video signal (RGB) to meet the interface specifications with the data driver (DDV). In response to the control signal (CTRL), the timing controller (TC) can output a scan control signal (SCS), a data control signal (DCS), and an emission control signal (ECS).

[0073] A voltage generator (VG) can generate voltages required for the operation of a display panel (DP). The voltage generator (VG) can generate a first driving voltage (ELVDD), a second driving voltage (ELVSS), a first initialization voltage (VINT), and a second initialization voltage (VAINT). The first driving voltage (ELVDD), the second driving voltage (ELVSS), the first initialization voltage (VINT), and the second initialization voltage (VAINT) can be applied to pixels (PX).

[0074] The scan driver (SDV) can receive a scan control signal (SCS) from a timing controller (TC). The scan driver (SDV) can output scan signals to scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) in response to the scan control signal (SCS). The scan signals can be applied to pixels (PX) through the scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm).

[0075] The data driver (DDV) can receive a data control signal (DCS) and an image data signal (DAS) from a timing controller (TC). The data driver (DDV) can convert the image data signal (DAS) into data signals and output them. The data signals can be defined as analog voltages corresponding to the grayscale levels of the image data signal (DAS). The data signals can be applied to the pixels (PX) through data lines (DL1 to DLn).

[0076] The emission driver (EDV) can receive an emission control signal (ECS) from a timing controller (TC). The emission driver (EDV) can output emission signals to the emission lines (EML1 to EMLm) in response to the emission control signal (ECS). The emission signals can be applied to the pixels (PX) through the emission lines (EML1 to EMLm).

[0077] Pixels (PX) can receive data voltages in response to scanning signals. Pixels (PX) can display images by emitting light with a brightness corresponding to the data voltages in response to light emission signals.

[0078]

[0079] FIGS. 5A to 5C are diagrams illustrating equivalent circuits of one of the pixels illustrated in FIG. 4. FIG. 6 is a timing diagram of scan signals and emission signals for explaining the operation of a pixel according to an embodiment of the present invention. For ease of explanation, FIG. 6 illustrates, by way of example, the timing diagram of the pixel illustrated in FIG. 5A. Hereinafter, the pixel will be described in more detail with reference to FIGS. 5A to 6.

[0080] For example, FIG. 5a illustrates a pixel (PXij) connected to the jth data line (DLj), the ith scan lines (GWLi, GCLi, GILi, GBLi), and the ith emission line (EMLi). i and j are natural numbers.

[0081] Referring to FIG. 5, a pixel (PXij) may include a pixel driver (PC) and a light-emitting element (OLED) connected to the pixel driver (PC). The pixel driver (PC) may drive the light-emitting element (OLED).

[0082] The pixel driver (PC) may include a plurality of transistors (T1 to T8) and a capacitor (CST). The transistors (T1 to T8) and the capacitor (CST) may control the amount of current flowing to the light-emitting element (OLED). The light-emitting element (OLED) may generate light having a predetermined brightness depending on the amount of current supplied.

[0083] The ith write scan line (GWLi) can receive the ith write scan signal (GWi), the ith compensation scan line (GCLi) can receive the ith compensation scan signal (GCi), the ith initialization scan line (GILi) can receive the ith initialization scan signal (GIi), the ith bias scan line (GBLi) can receive the ith bias scan signal (GBi), and the ith emission line (EMLi) can receive the ith emission signal (EMi).

[0084] A pixel (PXij) can be connected to a j-th data line (DLj), an i-th write scan line (GWLi), an i-th compensation scan line (GCLi), an i-th initialization scan line (GILi), an i-th bias scan line (GBLi), an i-th emission line (EMLi), a first initialization line (VIL1), a second initialization line (VIL2), a bias line (VBL), and first and second power lines (PL1, PL2).

[0085] The first initialization line (VIL1) can receive the first initialization voltage (VINT), and the second initialization line (VIL2) can receive the second initialization voltage (VAINT). The bias line (VBL) can receive the bias voltage (VBIAS). The first power line (PL1) can receive the first driving voltage (ELVDD), and the second power line (PL2) can receive the second driving voltage (ELVSS).

[0086] Each of the transistors (T1 to T8) may include a source electrode, a drain electrode, and a gate electrode. Hereinafter, in FIGS. 5A to 5C, for convenience, one of the source electrode and the drain electrode is defined as a first electrode, and the other is defined as a second electrode. In addition, the gate electrode is defined as a control electrode.

[0087] The transistors (T1 to T8) may include first to eighth transistors (T1 to T8). The first, second, and fifth to eighth transistors (T1, T2, T5 to T8) may be PMOS transistors. The third and fourth transistors (T3, T4) may be NMOS transistors.

[0088] The first transistor (T1) may be defined as a driving transistor, the second transistor (T2) may be defined as a switching transistor, the third transistor (T3) may be defined as a compensation transistor, the fourth transistor (T4) and the seventh transistor (T7) may be defined as initialization transistors, the fifth transistor (T5) and the sixth transistor (T6) may be defined as light-emitting control transistors, and the eighth transistor (T8) may be defined as a bias transistor.

[0089] The light-emitting element (OLED) may be defined as an organic light-emitting element. The light-emitting element (OLED) may include an anode (AE) and a cathode (CE). The anode (AE) may receive a first driving voltage (ELVDD) through the sixth, first, and fifth transistors (T6, T1, T5). The first driving voltage (ELVDD) may be applied to the pixel driver (PC) through the first power line (PL1).

[0090] The cathode (CE) can receive a second driving voltage (ELVSS) having a lower level than the first driving voltage (ELVDD). The second driving voltage (ELVSS) can be applied to the pixel driver (PC) through a second power line (PL2).

[0091] A first transistor (T1) is disposed between a fifth transistor (T5) and a sixth transistor (T6), and can be connected to the fifth transistor (T5) and the sixth transistor (T6). The first transistor (T1) can be connected to a first power line (PL1) through the fifth transistor (T5), and to an anode (AE) through the sixth transistor (T6).

[0092] The first transistor (T1) may include a first electrode connected to the first power line (PL1) via a fifth transistor (T5), a second electrode connected to the anode (AE) via a sixth transistor (T6), and a control electrode connected to the first node (N1).

[0093] A first electrode of a first transistor (T1) may be connected to a fifth transistor (T5), and a second electrode of the first transistor (T1) may be connected to a sixth transistor (T6). The first transistor (T1) may control the amount of current flowing to the light-emitting element (OLED) according to the voltage of the first node (N1) applied to the control electrode of the first transistor (T1).

[0094] A second transistor (T2) may be disposed between the first transistor (T1) and the j-th data line (DLj) and may be connected to the first transistor (T1) and the j-th data line (DLj). The second transistor (T2) may include a first electrode connected to the j-th data line (DLj), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the i-th write scan line (GWLi).

[0095] The second transistor (T2) can be turned on by the i-th write scan signal (GWi) applied through the i-th write scan line (GWLi) to electrically connect the j-th data line (DLj) and the first electrode of the first transistor (T1). The second transistor (T2) can perform a switching operation of providing the data voltage (VD) (corresponding to the aforementioned data signal) applied through the j-th data line (DLj) to the first electrode of the first transistor (T1).

[0096] A third transistor (T3) may be connected to the second electrode of the first transistor (T1) and the first node (N1). The third transistor (T3) may include a first electrode connected to the second electrode of the first transistor (T1), a second electrode connected to the first node (N1), and a control electrode connected to the ith compensation scan line (GCLi).

[0097] The third transistor (T3) can be turned on by the i-th compensation scan signal (GCi) applied through the i-th compensation scan line (GCLi) to electrically connect the second electrode of the first transistor (T1) and the control electrode of the first transistor (T1). When the third transistor (T3) is turned on, the first transistor (T1) and the third transistor (T3) can be connected in a diode form.

[0098] A fourth transistor (T4) may be connected to a first node (N1). The fourth transistor (T4) may include a first electrode connected to the first node (N1), a second electrode connected to a first initialization line (VIL1), and a control electrode connected to an ith initialization scan line (GILi). The fourth transistor (T4) may be turned on by an ith initialization scan signal (GIi) applied through the ith initialization scan line (GILi) and may provide a first initialization voltage (VINT) applied through the first initialization line (VIL1) to the first node (N1).

[0099] The fifth transistor (T5) may include a first electrode connected to the first power line (PL1), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the ith light emitting line (EMLi).

[0100] The sixth transistor (T6) may include a first electrode connected to the second electrode of the first transistor (T1), a second electrode connected to the anode (AE), and a control electrode connected to the ith light emitting line (EMLi).

[0101] The fifth transistor (T5) and the sixth transistor (T6) can be turned on by the ith light-emitting signal (EMi) applied through the ith light-emitting line (EMLi). The first driving voltage (ELVDD) is provided to the light-emitting element (OLED) by the turned-on fifth transistor (T5) and sixth transistor (T6), so that a driving current can flow to the light-emitting element (OLED). Therefore, the light-emitting element (OLED) can emit light.

[0102] The seventh transistor (T7) may include a first electrode connected to the anode (AE), a second electrode connected to the second initialization line (VIL2), and a control electrode connected to the ith bias scan line (GBLi). The seventh transistor (T7) may be turned on by the ith bias scan signal (GBi) applied through the ith bias scan line (GBLi), and may provide the second initialization voltage (VAINT) received through the second initialization line (VIL2) to the anode (AE) of the light-emitting element (OLED).

[0103] In an embodiment of the present invention, the second initialization voltage (VAINT) may have a different level from the first initialization voltage (VINT), but is not limited thereto and may have the same level as the first initialization voltage (VINT).

[0104] The seventh transistor (T7) can improve the black expression capability of the pixel (PXij). When the seventh transistor (T7) is turned on, the parasitic capacitor (not shown) of the light-emitting element (OLED) can be discharged. Therefore, when implementing black luminance, the light-emitting element (OLED) does not emit light due to the leakage current of the first transistor (T1), and thus the black expression capability can be improved.

[0105] The capacitor (CST) may include a first electrode connected to a first power line (PL1) and a second electrode connected to a first node (N1). When the fifth transistor (T5) and the sixth transistor (T6) are turned on, the amount of current flowing to the first transistor (T1) may be determined according to the voltage stored in the capacitor (CST).

[0106] The eighth transistor (T8) may include a first electrode connected to a bias line (VBL), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to an i-th bias scan line (GBLi).

[0107] The eighth transistor (T8) is turned on by the i-th bias scan signal (GBi) and can provide a bias voltage (VBIAS) applied through the bias line (VBL) to the first electrode of the first transistor (T1).

[0108] Referring to FIGS. 5A and 6, the i-th emission signal (EMi) can have a high level during a non-emission period (NLP) and a low level during a emission period (LP).

[0109] The activation period of each of the ith write scan signal (GWi) and the ith bias scan signal (GBi) can be defined as the low level of each of the ith write scan signal (GWi) and the ith bias scan signal (GBi).

[0110] The activation period of each of the ith compensation injection signal (GCi) and the ith initialization injection signal (GIi) can be defined as the high level of each of the ith compensation injection signal (GCi) and the ith initialization injection signal (GIi).

[0111] After the ith initialization scan signal (GIi) is activated, the ith compensation scan signal (GCi) and the ith write scan signal (GWi) may be activated. Thereafter, the ith bias scan signal (GBi) may be activated.

[0112] During the non-luminous period (NLP), the activated ith initialization scan signal (GIi), the ith compensation scan signal (GCi), the ith write scan signal (GWi), and the ith bias scan signal (GBi) can be applied to the pixel (PXij).

[0113] The ith initialization scan signal (GIi) may be applied to the fourth transistor (T4), thereby turning on the fourth transistor (T4). The first initialization voltage (VINT) may be provided to the node (N1) through the fourth transistor (T4). Accordingly, the first initialization voltage (VINT) may be applied to the control electrode of the first transistor (T1), and the first transistor (T1) may be initialized by the first initialization voltage (VINT). This operation may be defined as an initialization operation.

[0114] The ith write scan signal (GWi) may be applied to the second transistor (T2) to turn on the second transistor (T2). In addition, the ith compensation scan signal (GCi) may be applied to the third transistor (T3) to turn on the third transistor (T3).

[0115] The first transistor (T1) and the third transistor (T3) may be electrically connected to each other in a diode form. In this case, a compensation voltage (Vd-Vth) that is reduced by the threshold voltage (Vth) of the first transistor (T1) from the data voltage (VD) supplied through the data line (DLj) may be applied to the control electrode of the first transistor (T1). This operation may be defined as a write operation (or programming operation) and a compensation operation.

[0116] A first voltage (ELVDD) and a compensation voltage (Vd-Vth) can be applied to the first electrode and the second electrode of the capacitor (CST), respectively. A charge corresponding to a voltage difference between the first electrode of the capacitor (CST) and the second electrode of the capacitor (CST) can be stored in the capacitor (CST).

[0117] Thereafter, the i-th bias scan signal (GBi) may be applied to the seventh and eighth transistors (T7, T8), so that the seventh and eighth transistors (T7, T8) may be turned on. The second initialization voltage (VAINT) may be provided to the anode (AE) through the seventh transistor (T7), so that the anode (AE) may be initialized with the second initialization voltage (VAINT). The bias voltage (VBIAS) may be applied to the first electrode of the first transistor (T1) through the eighth transistor (T8).

[0118] Thereafter, during the emission period (LP), the ith emission signal (EMi) may be applied to the fifth transistor (T5) and the sixth transistor (T6) through the ith emission line (EMLi), so that the fifth transistor (T5) and the sixth transistor (T6) may be turned on. In this case, a driving current (Id) corresponding to a voltage difference between the voltage of the control electrode of the first transistor (T1) and the first voltage (ELVDD) may be generated. The driving current (Id) may be provided to the light-emitting element (OLED) through the sixth transistor (T6), so that the light-emitting element (OLED) may emit light.

[0119] During the light emission period (LP), the gate-source voltage (Vgs) of the first transistor (T1) by the capacitor (CST) can be defined as Vgs = ELVDD - (Vd-Vth). The current and voltage relationship of the first transistor (T1) is can be defined as follows. This equation is the current and voltage relationship of a general transistor.

[0120] When the gate-source voltage (Vgs) is substituted into the current and voltage relationship, the threshold voltage (Vth) is removed, and the driving current (Id) is the square of the first voltage (ELVDD) minus the data voltage (Vd), i.e., can be proportional to. Therefore, the driving current (Id) can be determined regardless of the threshold voltage (Vth) of the first transistor (T1). This operation can be defined as a threshold voltage compensation operation.

[0121] A bias voltage (VBIAS) can be applied to the first electrode of the first transistor (T1) through the eighth transistor (T8) before the light-emitting element (OLED) emits light after the threshold voltage of the first transistor (T1) is compensated. The shift of the hysteresis curve of the first transistor (T1) can be suppressed by the bias voltage (VBIAS). This operation can be defined as a bias operation.

[0122] Referring to FIG. 5b, the pixel driver (PC-1) may include six transistors (T11, T21, T31, T41, T51, T61) and two capacitors (CST, CHD).

[0123] The first transistor (T11) can be defined as a driving transistor, and the second transistor (T21) can be defined as a switching transistor.

[0124] The third transistor (T31) may be defined as a reset transistor. The third transistor (T31) provides a reference voltage (VREF) to the first node (N1) in response to a reset signal (GRi) transmitted from the scan driver (SDV, see FIG. 4). The first node (N1) is reset to the reference voltage (VREF), thereby minimizing the influence of the voltage remaining in the previous step.

[0125] The fourth transistor (T41) may be defined as an anode initialization transistor. The fourth transistor (T41) may correspond to the seventh transistor (T7, see FIG. 5A) illustrated in FIG. 5A. The fourth transistor (T41) may initialize the anode of the light-emitting element to the second initialization voltage (VAINT) in response to the initialization signal (GIi).

[0126] The fifth transistor (T51) and the sixth transistor (T61) may be defined as light emission control transistors. Meanwhile, in the present embodiment, the fifth transistor (T51) and the sixth transistor (T61) may be driven by different light emission control signals. Specifically, the fifth transistor (T51) may transmit the first voltage (ELVDD) to the first transistor (T11) in response to the first light emission signal (Emi), and the sixth transistor (T61) may be turned on in response to the second light emission signal (EMBi). According to the present invention, the fifth transistor (T51) and the sixth transistor (T61) may be turned on or off at different timings, so that independent driving may be performed. In the present embodiment, the first light emission signal (EMi) may correspond to the ith light emission signal, and the second light emission signal (EMBi) may be a signal independent of the first light emission signal (EMi). However, this is an example and the first light emitting signal (EMi) and the second light emitting signal (EMBi) may be applied at the same timing and are not limited to any one embodiment.

[0127] Referring to FIG. 5c, the pixel driver (PC-2) may include seven transistors (T12, T22, T32, T42, T52, T62, T72) and two capacitors (CST, CHD). The first transistor (T12) may be defined as a driving transistor, and the second transistor (T22) may be defined as a switching transistor. The third transistor (T32) may be defined as a reset transistor, and the fourth transistor (T42) may be defined as an anode initialization transistor. The fifth transistor (T52) and the sixth transistor (T62) may be defined as light emission control transistors.

[0128] Compared to FIG. 5B, the pixel driver (PC-2) may further include a seventh transistor (T72). The seventh transistor (T72) may be disposed between the first power voltage (ELVDD) and the drain of the first transistor (T1). The seventh transistor (T72) may provide the first power voltage (ELVDD) to the first transistor (T12) in response to the reset signal (GR). At this time, the seventh transistor (T7) and the third transistor (T32) may be turned on simultaneously at the same timing. That is, the drain of the first transistor (T12) may receive the first power voltage (ELVDD) at the timing when the first node (N1) is reset.

[0129] Meanwhile, the sixth transistor (T62) can be driven by the ith light emission signal (EMi). That is, the sixth transistor (T62) can be turned on simultaneously with the fifth transistor (T52) at the same timing. According to the present invention, the number of signals (GIi, GRi, EMi, GWi) transmitted from the scan driver (SDV) to the pixel driver (PC-2) is reduced to four, so that the circuit constituting the scan driver (SDV) can be simplified compared to the pixel circuit illustrated in FIG. 5b.

[0130]

[0131] FIGS. 7A to 7D are cross-sectional views illustrating a portion of a display panel according to an embodiment of the present invention. FIGS. 7A to 7D each illustrate an area in which three transistors (TR1, TR2, TR3) and a light-emitting element (OLED) among the configurations of each pixel (PXij) illustrated in FIGS. 5A to 5C are arranged. Referring to FIGS. 7A to 7D , the display panel (DP) may include a substrate (SUB), a driving element layer (DD-CL), a display element layer (DP-OLED), and an encapsulation layer (TFE).

[0132] The substrate (SUB) may include a glass substrate, a sapphire substrate, a plastic film, or an organic / inorganic laminated film. The substrate (SUB) may have a multilayer or single-layer structure. For example, the substrate (SUB) may have a laminated structure of a plurality of plastic films bonded with an adhesive, or may have a laminated structure of a glass substrate and a plastic film bonded with an adhesive. The substrate (SUB) may have flexibility. For example, the substrate (SUB) may include polyimide (PI). However, this is described as an example, and the substrate (SUB) may be provided in a rigid state and is not limited to any one embodiment.

[0133] The driving element layer (DD-CL) is disposed on the substrate (SUB). The driving element layer (DD-CL) may include a driving element and a plurality of insulating layers (10, 20, 30, 40, 50). The three transistors (T1, T2, T6) described above may be elements constituting the driving element layer (DD-CL). The insulating layers (10, 20, 30, 40, 50) may include first to fifth insulating layers (10, 20, 30, 40, 50) sequentially stacked on the substrate (SUB), but this is merely an example and the number of insulating layers constituting the driving element layer (DD-CL) may vary and is not limited to any one embodiment.

[0134] Three transistors (TR1, TR2, TR3) are arranged on a substrate (SUB). The three transistors (TR1, TR2, TR3) include a first driving element (TR1), a second driving element (TR2), and a third driving element (TR3). In the present embodiment, a lower conductive layer (BML) and a first insulating layer (10) may be arranged between the three transistors (TR1, TR2, TR3) and the substrate (SUB).

[0135] The first insulating layer (10) is disposed on the substrate (SUB) and covers the entire upper surface of the substrate (SUB). The first insulating layer (10) may include a barrier layer. That is, the first insulating layer (10) may prevent oxygen or moisture flowing in through the substrate (SUB) from penetrating into the pixel (PXij).

[0136] The second insulating layer (20) is disposed on the first insulating layer (10) and covers the lower conductive layer (BML). The second insulating layer (20) can cover the entire substrate (SUB). The second insulating layer (20) can include a buffer layer. That is, the second insulating layer (20) can reduce the surface energy of the surface on which the driving element layer (DP-CL) is formed so that the pixel (PXij) is stably formed on the substrate (SUB). Meanwhile, at least one of the barrier layer and the buffer layer may be provided in multiples or may be omitted. In addition, in the display panel according to one embodiment of the present invention, the first insulating layer (10) and / or the second insulating layer (20) may be omitted and are not limited to any one embodiment.

[0137] The first thin film transistor (TR1) may include a first semiconductor pattern (SP1) and a first gate (G1). The first thin film transistor (TR1) may be a driving transistor that is arranged on a current path between the first power line (PL1) described above and the light emitting element (OLED) to control the amount of current flowing to the light emitting element (OLED), but is not limited thereto. The first semiconductor pattern (SP1) includes a first source (S1), a first drain (D1), and a first channel (A1).

[0138] In the present embodiment, the first semiconductor pattern (SP1) may include an oxide semiconductor. For example, the first semiconductor pattern (SP1) may include at least one of indium, gallium, and zinc. Meanwhile, the first semiconductor pattern (SP1) may have a crystalline structure. That is, the first semiconductor pattern (SP1) may include a crystalline oxide semiconductor. The first semiconductor pattern (SP1) may be formed by crystallizing an oxide semiconductor material. The first source (S1), the first drain (D1), and the first channel (A1) may be distinguished according to conductivity. Specifically, the first channel (A1) may be a region having relatively low conductivity compared to the first source (S1) and the first drain (D1), and may be a region having semiconductor properties. Each of the first source (S1) and the first drain (D1) may be a region having high conductivity compared to the first channel (A1), and may be a region having conductive properties.

[0139] Each of the first source (S1) and the first drain (D1) may be formed through doping or reduction. For example, in a semiconductor pattern, a highly doped region having a relatively high dopant concentration may have high conductivity. Some regions of the semiconductor pattern may be doped to become sources / drains, and the remaining regions may become channels. The dopants may be P-type dopants or N-type dopants, and are not limited to any one embodiment. In the present embodiment, each of the first source (S1) and the first drain (D1) may be formed by being doped with an N-type dopant.

[0140] Alternatively, for example, in an oxide semiconductor pattern, a reduced region may have higher conductivity than a non-reduced region. Since the metal oxide constituting the oxide semiconductor pattern is precipitated into a metal through a reduction process, the region where the metal oxide is reduced may become a source / drain, and the remaining region may become a channel.

[0141] Meanwhile, in the present embodiment, the first source (S1) and the first drain (D1) may be formed on the first semiconductor pattern (SP1). However, this is merely an example, and the source / drain of the first thin film transistor (TR1) may be provided as a separate conductive pattern electrically connected to the first semiconductor pattern (SP1), and is not limited to any one embodiment.

[0142] A first gate (G1) may be disposed on a semiconductor pattern of a first thin film transistor (TR1). The first gate (G1) may overlap a first channel (A1). A first insulating pattern (31) may be disposed between the first gate (G1) and the semiconductor pattern. The first insulating pattern (31) may be patterned in a shape aligned with the first gate (G1). The first insulating pattern (31) may be a gate insulating layer, and the first thin film transistor (TR1) is illustrated as having a top-gate structure. However, this is merely an example, and the first insulating pattern (31) may be provided as a layer having an integral shape covering the entire area of ​​the substrate (SUB), and the first thin film transistor (TR1) may have a bottom-gate structure, and is not limited to any one embodiment.

[0143] The second thin film transistor (TR2) may include a second gate (G2) and a second semiconductor pattern (SP2). The second thin film transistor (TR2) may be an initialization transistor (T4: see FIG. 5a) that is turned on through the aforementioned initialization scan line (GILi) and provides the first initialization voltage (VINT) transmitted through the first initialization line (VIL1) to the pixel circuit, but is not limited thereto.

[0144] The second semiconductor pattern (SP2) may be arranged on the same layer as the first semiconductor pattern (SP1). In the present embodiment, the second semiconductor pattern (SP2) may include an amorphous oxide semiconductor. The second semiconductor pattern (SP2) may include an oxide semiconductor with high mobility. For example, the second semiconductor pattern (SP2) may have a thickness of about 30 It can have the above mobility.

[0145] The second semiconductor pattern (SP2) may include at least one of indium, tin, gallium, and zinc. For example, the second semiconductor pattern (SP2) may include indium, tin, gallium, and zinc, and may have a composition ratio of about 60-80 wt% of indium, 0.5-8 wt% of tin, 5-15 wt% of gallium, and 10-30 wt% of zinc, but is not limited thereto. The second semiconductor pattern (SP2) may include an oxide semiconductor having various compositions as long as it has high mobility, and is not limited to any one embodiment.

[0146] The second semiconductor pattern (SP2) may have a different crystal structure from the first semiconductor pattern (SP1). That is, the second semiconductor pattern (SP2) may be a metal oxide semiconductor pattern that has not undergone a crystallization process. The second semiconductor pattern (SP2) may be divided into a second source (S2) and a second drain (D2) having relatively high conductivity and conductive properties, and a second channel (A2) having relatively low conductivity and semiconductor properties. In the present embodiment, each of the second source (S2) and the second drain (D2) may be regions in which an N-type dopant concentration is formed high. Meanwhile, this is described by way of example, and a detailed description of the second semiconductor pattern (SP2) will be omitted because it overlaps with the first semiconductor pattern (SP1).

[0147] The second gate (G2) may be disposed on the second semiconductor pattern (SP2) with the second insulating pattern (32) interposed therebetween. The second gate (G2) may overlap the second channel (A2). When the second thin film transistor (TR2) is an initialization transistor (T4: see FIG. 5), the second gate (G2) may be electrically connected to a corresponding initialization scan line among the aforementioned initialization scan lines (GIL1 to GILm). A second insulating pattern (22) may be disposed between the second gate (G2) and the second semiconductor pattern (SP2). The second thin film transistor (TR2) is illustrated as having a top-gate structure. However, this is merely an example, and the second thin film transistor (TR2) may have a bottom-gate structure and is not limited to any one embodiment.

[0148] The third thin film transistor (TR3) may include a third gate (G3) and a third semiconductor pattern (SP3). The third thin film transistor (TR3) may be a light-emitting control transistor (T6: see FIG. 5a) that is arranged on a current path between the first thin film transistor (TR1) and the light-emitting element (OLED) and provides the driving current transmitted by the first thin film transistor (TR1) to the light-emitting element (OLED) in response to a signal transmitted through the above-described light-emitting line (EMLi), but is not limited thereto.

[0149] The third thin film transistor (TR3) may be provided with the same structure as the second thin film transistor (TR2). Specifically, the third thin film transistor (TR3) has a top-gate structure in which a third gate (G3) is overlapped and arranged on a third semiconductor pattern (SP3) with a third insulating pattern (33) therebetween, includes a third semiconductor pattern (SP3) arranged on the same layer as the first thin film transistor (TR1), and may include a third source (S3), a third drain (D3), and a third channel (A3) formed on the third semiconductor pattern (SP3). The third semiconductor pattern (SP3) is formed of an amorphous oxide semiconductor, and each of the third source (S3) and the third drain (D3) may include an N-type dopant. That is, the second semiconductor pattern (SP2) and the third semiconductor pattern (SP3) may include the same material and be patterned through the same process. However, this is an example, and the third semiconductor pattern (SP3) may include a different material from the second semiconductor pattern (SP2) and is not limited to any one embodiment.

[0150] According to the present embodiment, the first thin film transistor (TR1) functioning as a driving transistor can have a relatively wide driving range compared to the second and third thin film transistors (TR2, TR3) functioning as switching transistors. Since the first channel (A1) is formed of a crystalline oxide semiconductor, a relatively wide driving range can be secured compared to the second channel (A2) and the third channel (A3) formed of an amorphous oxide semiconductor. The first channel (A1) according to the present embodiment can have a driving range of about 0.39 V or more. Accordingly, the pixel (Pxij) can easily express various grayscales.

[0151] In addition, the second and third thin film transistors (TR2, TR3) functioning as switching transistors can have relatively high charge mobility and short channel length compared to the first thin film transistor (TR1) functioning as a driving transistor. By forming the second channel (A2) and the third channel (A3) with an amorphous oxide semiconductor, it is possible to secure relatively high charge mobility and short channel length compared to the first channel (A1). Each of the second channel (A2) and the third channel (A3) according to the present embodiment has a charge mobility of about 30 It can be formed with a charge mobility of about 4㎛ or less. Accordingly, leakage current can be reduced and a switching transistor with improved on-off characteristics can be provided, so that a display panel with high resolution can be easily designed.

[0152] Meanwhile, as described above, the first to third insulating patterns (31, 32, 33) may be provided in the form of a layer that is connected to each other and has an integral shape. In this case, the third insulating layer (30) may be provided as a single insulating layer having an integral shape rather than as a plurality of separate patterns (31, 32, 33), and is not limited to any one embodiment.

[0153] The driving element layer (DP-CL) may further include a plurality of connection electrodes (CN1, CN2, CN3, CN4, CN5, CN6). The first connection electrode (CN1) may be connected to the source (S1) of the first thin film transistor (TR1), and the second connection electrode (CN2) may be connected to the drain (D1) of the first thin film transistor (TR1). The third connection electrode (CN3) may be connected to the source (S2) of the second thin film transistor (TR2), and the fourth connection electrode (CN4) may be connected to the drain (D2) of the second thin film transistor (TR2). The fifth connection electrode (CN5) may be connected to the source (S3) of the third thin film transistor (TR3), and the sixth connection electrode (CN6) may be connected to the drain (D3) of the third thin film transistor (TR3).

[0154] The fifth insulating layer (50) is disposed on the fourth insulating layer (40) and covers the connection electrodes (CN1, CN2, CN3, CN4, CN5, CN6). The light-emitting element (OLED) is electrically connected to the driving element layer (DP-CL) through a contact hole formed in the fifth insulating layer (50).

[0155] In the present embodiment, each of the first to fifth insulating layers (10, 20, 30, 40, 50) may include an inorganic layer and / or an organic layer. For example, the first insulating layer (10) and the second insulating layer (20) may include silicon nitride and / or silicon oxide, and each of the first to third insulating patterns (31, 32, 33) constituting the third insulating layer (30) may include silicon oxide. The fourth insulating layer (40) may include a sequentially laminated silicon oxynitride layer and a silicon nitride layer, and the fifth insulating layer (50) may include an organic layer. However, this is merely an example, and the material or laminated form of each of the first to fifth insulating layers (10, 20, 30, 40, 50) may be variously changed and is not limited to any one embodiment.

[0156] A display element layer (DP-OLED) may be disposed on a driving element layer (DD-CL). The display element layer (DP-OLED) may include a light-emitting element (OLED) and a pixel defining layer (PDL). The light-emitting element (OLED) may include a first electrode (E1), a hole control layer (HCL), an emission layer (EML), an electron control layer (ECL), and a second electrode (E2).

[0157] The first electrode (E1) may be disposed on the fifth insulating layer (50). The first electrode (E1) may penetrate the fifth insulating layer (50) and be connected to the fifth connection electrode (CN5). Meanwhile, this is merely an example, and if the first electrode (E1) can be connected to the third thin film transistor (TR3), it may be connected through a separate additional connection electrode or directly connected to the source (S3) of the third thin film transistor (TR3), and is not limited to any one embodiment.

[0158] A pixel defining layer (PDL) may be disposed on the fifth insulating layer (50). The pixel defining layer (PDL) may expose at least a portion of the first electrode (E1). That is, an opening may be defined in the pixel defining layer (PDL) to expose a predetermined portion of the first electrode (E1).

[0159] A hole control layer (HCL) may be disposed on a first electrode (E1) and a pixel defining layer (PDL). The hole control layer (HCL) may be disposed commonly in both an emitting area and a non-emitting area. The hole control layer (HCL) may include a layer having high hole mobility to facilitate movement of holes from the first electrode (E1) to the emitting layer (EML). For example, the hole control layer (HCL) may include at least one of a hole transport layer, a hole injection layer, and an electron blocking layer, and each layer may have a single-layer or multi-layer stacked structure.

[0160] An emission layer (EML) may be disposed on a hole control layer (HCL). The emission layer (EML) may be disposed in an area corresponding to an opening of a pixel defining layer (PDL). The emission layer (EML) may include an organic material and / or an inorganic material. The emission layer (EML) may generate light of any one of red, green, and blue.

[0161] An electron control layer (ECL) may be disposed on the light emitting layer (EML) and the hole control layer (HCL). The electron control layer (ECL) may be disposed commonly in both the light emitting region and the non-light emitting region. The electron control layer (ECL) may include a layer having high electron mobility to facilitate the movement of electrons from the second electrode (E2) to the light emitting layer (EML). For example, the electron control layer (ECL) may include at least one of an electron transport layer, an electron injection layer, and a hole blocking layer, and each layer may have a single-layer or multi-layer stacked structure.

[0162] The second electrode (E2) may be disposed on the electronic control layer (ECL). The second electrode (E2) may be commonly disposed on the pixels (PX). That is, the second electrode (E2) may be formed in an integral shape on the light-emitting layers (EML) of the pixels (PX). However, this is merely an example, and the second electrode (E2) may be provided in a separate pattern for each pixel (PX) and is not limited to any one embodiment. The second electrode (E2) may be semi-transparent or transparent. The second electrode (E2) may be provided in various forms, such as a transparent conductive oxide layer, a thin-film metal layer having transparency, or a layer having a stacked structure of a metal layer / oxide layer. Meanwhile, when the light-emitting element (OLED) has a bottom-emitting structure, the second electrode (E2) may be a reflective electrode.

[0163] An encapsulation layer (TFE) may be disposed on the display element layer (DD-OLED). The encapsulation layer (TFE) may include an inorganic layer and an organic layer. In the present embodiment, the first inorganic layer (IL1), the organic layer (OL), and the second inorganic layer (IL2) are sequentially laminated, but the laminated structure of the layers constituting the encapsulation layer (TFE) may be varied.

[0164] The first inorganic layer (IL1) and the second inorganic layer (IL2) contain inorganic materials and can protect pixels from moisture / oxygen. The first inorganic layer (IL1) and the second inorganic layer (IL2) may contain the same material or different materials. The organic layer (OL) contains organic materials and can protect the light-emitting element layer (DD-OLED) or the driving element layer (DD-CL) from foreign substances.

[0165] Referring to FIG. 7B, the display panel (DP-1) may further include a lower conductive layer (BCL). The lower conductive layer (BCL) may be disposed on the first insulating layer (10). The lower conductive layer (BCL) may block light incident from below onto the first thin film transistor (TR1). The lower conductive layer (BCL) may be a light-shielding pattern and may include a black matrix or a reflective conductive material. When the lower conductive layer (BCL) includes a conductive material, the lower conductive layer (BCL) may be electrically floated or connected to the first thin film transistor (TR1).

[0166] In the present embodiment, the lower conductive layer (BCL) may be connected to the source (S1) of the first thin film transistor (TR1). That is, the first connection electrode (CN1) may be connected to the source (S1) of the first thin film transistor (TR1) and the lower conductive layer (BCL), respectively. Accordingly, the first thin film transistor (TR1) may have a source-sync structure, and the driving range of the first channel (A1) may be increased. However, this is merely an example, and the lower conductive layer (BCL) may be connected to the gate or drain of the first thin film transistor (TR1), may be electrically floated, may receive a constant voltage, or may be omitted, and is not limited to any one embodiment. Meanwhile, although not illustrated, the second thin film transistor (TR2) or the third thin film transistor (TR3) may have a gate-sync structure. Accordingly, a second thin film transistor (TR2) or a third thin film transistor (TR3) can be designed to have a reduced channel length (short channel) and thus be advantageous for high-speed operation. However, this is merely an example, and the display panel (DP-1) according to an embodiment of the present invention may have various structures and is not limited to any one embodiment.

[0167] Referring to FIG. 7c, the display panel (DP-2) may further include an upper electrode (UE). The upper electrode (UE) may be disposed on a sixth insulating layer (60) interposed between the third insulating layer (30) and the fourth insulating layer (40). The upper electrode (UE) is disposed to overlap the first gate (G1) in a plane with the sixth insulating layer (60) interposed therebetween. The sixth insulating layer (60) is disposed on the second insulating layer (20) and the third insulating layer (30) to cover the first thin film transistor (TR1).

[0168] The portion where the upper electrode (UE) and the first gate (G1) overlap on a plane can function as a capacitor (CST, see FIG. 5a) constituting a pixel circuit. According to the present invention, by forming the capacitor (CST) together with the first gate (G1) of the first thin film transistor (TR1), a high-resolution pixel circuit can be designed while securing the area of ​​the capacitor. However, this is merely an example, and the upper electrode (UE) may be omitted or the capacitor may be formed in a different location, and the present invention is not limited to any one embodiment.

[0169] Referring to FIG. 7d, in the display panel (DP-3), each of the thin film transistors (TR1, TR2, TR3) may have a bottom-gate structure. The first to third gates (G1, G2, G3) may be disposed between the first insulating layer (10) and the second insulating layer (20), and the semiconductor patterns (SP1, SP2, SP3) may be disposed between the second insulating layer (20) and the fourth insulating layer (40). At this time, the sources (S1, S2, S3) and drains (D1, D2, D3) of the semiconductor patterns (SP1, SP2, SP3) may be formed by reduction in a process of forming contact holes in the fourth insulating layer (40). The contact holes in the fourth insulating layer (40) may be holes in which each of the connection electrodes (CN1, CN2, CN3, CN4, CN5, CN6) is connected to the corresponding semiconductor patterns (SP1, SP2, SP3).

[0170] In the display panel (DP, DP-1, DP-2, DP-3) according to the present invention, the semiconductor pattern (SP1) of the first thin film transistor (TR1) functioning as a driving transistor is formed of a crystalline oxide semiconductor, and the semiconductor patterns (SP2, SP3) of the thin film transistors (TR2, TR3) functioning as switching transistors are formed of an amorphous oxide semiconductor, thereby enabling independent design according to the function of each thin film transistor. Accordingly, the first thin film transistor (TR1) can secure a high driving range, so that a display panel capable of expressing various grayscale levels can be provided. In addition, the second and third thin film transistors (TR2, TR3) are formed to have high mobility and a short channel length, so that a pixel driving circuit with reduced leakage current can be provided.

[0171]

[0172] FIGS. 8A and 8B are graphs showing current-voltage characteristics of semiconductor patterns according to one embodiment of the present invention. FIG. 8A shows the current-voltage characteristics for the second semiconductor pattern (SP2), and FIG. 8B shows the current-voltage characteristics for the first semiconductor pattern (SP1). Hereinafter, the present invention will be described with reference to FIGS. 8A and 8B.

[0173] Referring to Fig. 8a, it can be seen that by forming the second semiconductor pattern (SP2) with an amorphous oxide semiconductor material, the channel of the second thin film transistor (TR2) has high mobility. Accordingly, a fast switching operation of the second thin film transistor (TR2) can be enabled, and thus a switching transistor with improved on-off characteristics can be provided.

[0174] Referring to Fig. 8b, by forming the first semiconductor pattern (SP1) with a crystalline oxide semiconductor material, a wide driving range of the gate voltage of the first thin film transistor (TR1) can be secured. The driving range at low grayscale of the first thin film transistor (TR1) according to the present invention can be 0.45 V or more, and in particular, can be 0.9 V or more.

[0175] Fig. 8b is a graph measuring the current-voltage characteristics when the channel length is 5 μm. When the low-gray driving range is measured by the threshold voltage difference (△Vth) at which the output current can be controlled in a current range of 10 pA to 1 nA, the driving range in Fig. 8b can be approximately 0.99 V. According to the present invention, by forming the first semiconductor pattern (SP1) with a crystalline oxide semiconductor, a wide driving range can be achieved. Since the driving range of the gate voltage of the first thin film transistor (TR1) is wide, the grayscale of the light emitted from the light-emitting element can be finely controlled by changing the magnitude of the gate voltage. Accordingly, a display panel with high resolution and improved display quality can be provided. In addition, the threshold voltage difference (△Vth) measured after driving the first semiconductor pattern (SP1) for 12 hours is approximately 15.6 mV, and the threshold voltage difference (△Vth) measured after driving for 55 hours is approximately 39 mV. Therefore, the first semiconductor pattern (SP1) can have improved reliability while having a crystalline structure.

[0176]

[0177] FIGS. 9A to 9M are cross-sectional views illustrating a method for manufacturing a display panel according to an embodiment of the present invention. FIGS. 9A to 9M exemplarily illustrate a method for manufacturing the display panel (DP-1, see FIG. 7B) illustrated in FIG. 7B. Hereinafter, the present invention will be described with reference to FIGS. 9A to 9M. Components identical to those described in FIGS. 1 to 8B will be given the same reference numerals and redundant descriptions will be omitted.

[0178] Referring to FIG. 9a, a first insulating layer (10), a lower conductive layer (BCL), and a second insulating layer (20) may be formed on a substrate (SUB). The first insulating layer (10) may be formed by depositing or coating an insulating material on the substrate (SUB). The lower conductive layer (BCL) may be formed by depositing a conductive material on the first insulating layer (10) and then patterning it. However, this is merely an example, and the lower conductive layer (BCL) may be formed by a solution process such as coating in addition to deposition, and is not limited to any one embodiment. Thereafter, a second insulating layer (20) covering the lower conductive layer (BCL) may be formed by depositing or coating an insulating material.

[0179] Referring to FIGS. 9b and 9c, a first pattern (SMP1) may be formed on a second insulating layer (20). After forming a first semiconductor layer (SML1) on the second insulating layer (20), the first semiconductor layer (SML1) is patterned using a mask (MSK1). A portion of the first semiconductor layer (SML1) corresponding to the light-shielding area (BA) of the first mask (MSK1) may remain and be formed as the first pattern (SMP1), and a portion corresponding to the transmission area (TA) of the first mask (MSK1) may be removed. The first pattern (SMP1) may be formed in an area overlapping the lower conductive layer (BCL). Meanwhile, this is merely an example, and the first pattern (SMP1) may be patterned in various ways and is not limited to any one embodiment.

[0180] Referring to FIGS. 9D and 9E, a step of forming a first initial semiconductor pattern (SP1-I) by performing a first treatment (TRT1) on the first pattern (SMP1) may then be performed. The first treatment (TRT1) may be a crystallization step. The first treatment (TRT1) may be a heat treatment step, but is not limited to any one embodiment as long as the first pattern (SMP1) can be crystallized. Through the first treatment (TRT1), a crystallized first initial semiconductor pattern (SP1-I) may be formed from the first pattern (SMP1).

[0181] Referring to FIG. 9f, a second semiconductor layer (SML2) may be formed thereafter. The second semiconductor layer (SML2) may be formed by depositing a second semiconductor material on the second insulating layer (20). The second semiconductor layer (SML2) may directly cover the first initial semiconductor pattern (SP1-I). That is, the second semiconductor layer (SML2) may be formed in contact with the first initial semiconductor pattern (SP1-I).

[0182] Referring to FIGS. 9g and 9h, a second initial semiconductor pattern (SP2-I) and a third initial semiconductor pattern (SP3-I) may be formed thereafter. After forming the second semiconductor layer (SML2), the second semiconductor layer (SML2) is patterned using the second mask (MSK2). A portion of the second semiconductor layer (SML2) corresponding to the first light-shielding area (BA1) of the second mask (MSK2) remains and is formed as the second initial semiconductor pattern (SP2-I), a portion corresponding to the second light-shielding area (BA2) of the second mask (MSK2) remains and is formed as the third initial semiconductor pattern (SP3-I), and a portion corresponding to the transmission area (TA) of the second mask (MSK2) may be removed.

[0183] In the present embodiment, the second initial semiconductor pattern (SP2-I) and the third initial semiconductor pattern (SP3-I) can be formed simultaneously through one mask (MSK2). That is, the second initial semiconductor pattern (SP2-I) and the third initial semiconductor pattern (SP3-I) can be formed of the same material. Accordingly, the process of forming the second initial semiconductor pattern (SP2-I) and the third initial semiconductor pattern (SP3-I) can be simplified and the process cost can be reduced. However, this is merely an example, and the second initial semiconductor pattern (SP2-I) and the third initial semiconductor pattern (SP3-I) can be formed through separate processes through different masks or can be formed of different materials, and are not limited to any one embodiment.

[0184] Meanwhile, in the present embodiment, the second initial semiconductor pattern (SP2-I) and the third initial semiconductor pattern (SP3-I) may be formed on the same layer as the first initial semiconductor pattern (SP1-I). The first initial semiconductor pattern (SP1-I) having a crystalline structure may not be affected by an etchant used in patterning the second initial semiconductor pattern (SP2-I) and the third initial semiconductor pattern (SP3-I). The etchant may have a composition ratio including, but not limited to, about 7% nitric acid, about 5% sulfuric acid, about 0.5% corrosion inhibitor, and about 1% additive. Even when exposed to the etchant in patterning the second initial semiconductor pattern (SP2-I) and the third initial semiconductor pattern (SP3-I), only the portion of the second semiconductor layer (SMP2) that was exposed to light is removed, and the first initial semiconductor pattern (SP1-I) may remain stably. Accordingly, even if the first to third initial semiconductor patterns (SP1-I, SP2-I, SP3-I) are formed on the same layer, the first initial semiconductor pattern (SP1-I) formed first is not affected, so that process reliability can be improved. In addition, since the first to third initial semiconductor patterns (SP1-I, SP2-I, SP3-I) can be formed on the same layer, the process can be simplified and the layer structure of the display panel can be simplified. However, this is merely an example, and the second initial semiconductor pattern (SP2-I) and the third initial semiconductor pattern (SP3-I) may be formed on a different layer from the first initial semiconductor pattern (SP1-I), and are not limited to any one embodiment.

[0185] Referring to FIGS. 9i to 9k, gates (G1, G2, G3) and insulating patterns (31, 32, 33) may be formed thereafter. An initial third insulating layer (30-I) covering the first to third initial semiconductor patterns (SP1-I, SP2-I, SP3-I) and a metal layer (ML) may be sequentially formed on the second insulating layer (20). The initial third insulating layer (30-I) may be formed by depositing or coating an insulating material, and the metal layer (ML) may be formed by depositing or coating a metal material. Meanwhile, the metal layer (ML) may be formed of a conductive material other than a metal and is not limited to any one embodiment.

[0186] The first to third insulating patterns (31, 32, 33) and the first to third gates (G1, G2, G3) may be formed by performing a second process (TRT2) on the initial third insulating layer (30-I) and the metal layer (ML). The second process (TRT2) may be an etching process. The first to third gates (G1, G2, G3) may be formed from the metal layer (ML) using a mask (not shown). Thereafter, the first to third insulating patterns (31, 32, 33) may be formed using each of the first to third gates (G1, G2, G3) as a mask. Accordingly, the first to third insulating patterns (31, 32, 33) may have a shape aligned with the first to third gates (G1, G2, G3).

[0187] Meanwhile, the first to third initial semiconductor patterns (SP1-I, SP2-I, SP3-I) may be reduced by the second processing (TRT2) to form the first to third semiconductor patterns (SP1, SP2, SP3). Among the first to third initial semiconductor patterns (SP1-I, SP2-I, SP3-I), portions that are not covered by the first to third insulating patterns (31, 32, 33) and the first to third gates (G1, G2, G3) and are exposed may be reduced by the second processing (TRT2) to deposit metal. Accordingly, sources (S1, S2, S3) and drains (D1, D2, D3) having high conductivity may be formed. At this time, the sources (S1, S2, S3) and the drains (D1, D2, D3) may each be formed as regions having an N-type dopant.

[0188] The first to third initial semiconductor patterns (SP1-I, SP2-I, SP3-I) may be formed as first to third semiconductor patterns (SP1, SP2, SP3) including a source, a drain, and a channel, respectively. The channels (A1, A2, A3) of the first to third initial semiconductor patterns (SP1-I, SP2-I, SP3-I) may be formed to be aligned (self-aligned) with the gates (G1, G2, G3) and the insulating patterns (31, 32, 33). According to the present invention, the first to third thin film transistors (TR1, TR2, TR3) may be formed to include the semiconductor patterns (SP1, SP2, SP3) arranged on the same layer. However, this is merely an example, and if the first semiconductor pattern (SP1) is formed in a crystalline structure and the second and third semiconductor patterns (SP2, SP3) are formed in an amorphous structure, the first to third thin film transistors The positions and structures of the transistors (TR1, TR2, TR3) can be varied and are not limited to any one embodiment.

[0189] Thereafter, referring to FIG. 9l, a fourth insulating layer (40) may be formed. The fourth insulating layer (40) may be formed by depositing or coating an insulating material. Although not shown, the fourth insulating layer (40) may also be formed by sequentially stacking multiple insulating layers. The fourth insulating layer (40) is formed to cover the thin film transistors (TR1, TR2, TR3).

[0190] Hereafter, referring to FIG. 9m, connection electrodes (CN1, CN2, CN3, CN4, CN5, CN6) may be formed. A plurality of contact holes (CH1, CH2, CH3, CH4, CH5, CH6) are formed in the fourth insulating layer (40), and the connection electrodes (CN1, CN2, CN3, CN4, CN5, CN6) may be connected to corresponding thin film transistors (TR1, TR2, TR3) through the contact holes (CH1, CH2, CH3, CH4, CH5, CH6), respectively. Meanwhile, according to the present invention, a contact hole (CH7) penetrating the second insulating layer (20) and the fourth insulating layer (40) may be further formed. The first connection electrode (CN1) may be additionally connected to the lower conductive layer (BCL) through the contact hole (CH7). Accordingly, the source (S1) and the lower conductive layer (BCL) of the first thin film transistor (TR1) can be electrically connected. Meanwhile, this is merely an example, and the arrangement of the connection electrodes (CN1, CN2, CN3, CN4, CN5, CN6) may be varied depending on the structure of the thin film transistors (TR1, TR2, TR3), and at least some may be omitted or added, and is not limited to any one embodiment.

[0191]

[0192] Fig. 10 is a block diagram of an electronic device according to one embodiment. Referring to Fig. 10, an electronic device (EA) according to one embodiment may include a display module (DM), a processor (PR), a memory (MR), and a power module (PM).

[0193] A display module (DM) can display an image. The display module (DM) can include a display panel, or can further include other electronic modules or electronic components, such as an input detection unit or a sensor. The image displayed by the display module (DM) can include a moving image as well as a still image. The processor (PR) can include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. The processor (PR) can be configured to control the operation of the display module (DM).

[0194] The memory (MR) may store data information necessary for the operation of the processor (PR) or display module (DM). When the processor (PR) executes an application stored in the memory (MR), image data signals and / or input control signals are transmitted to the display module (DM), and the display module (DM) can process the received signals and output image information through a display screen.

[0195] A power module (PM) may include a power supply module, such as a power adapter or a battery device, and a power conversion module that converts power supplied by the power supply module to generate power required for the operation of an electronic device (EA).

[0196]

[0197] FIG. 11 is a schematic diagram of an electronic device according to various embodiments.

[0198] Referring to FIG. 11, various electronic devices to which display devices according to embodiments are applied may include not only image display electronic devices such as a smart phone (EA_1a), a tablet PC (EA_1b), a laptop (EA_1c), a TV (EA_1d), and a desk monitor (EA_1e), but also wearable electronic devices including display modules such as smart glasses (EA_2a), a head-mounted display (EA_2b), and a smart watch (EA_2c), and vehicle electronic devices (EA_3) including display modules such as a CID (Center Information Display) placed on a dashboard, center fascia, or car instrument panel, and a room mirror display. The electronic device of FIG. 11 may include the components illustrated in FIG. 10. For example, the smart phone (10_1a) may include the display module (DM), the processor (PR), the memory (MR), and the power module (PM) illustrated in FIG. 9. The smart phone (EA_1a) may further include a communication module and a battery device. Power provided by the battery device may be converted through a power module (PM) and provided to a processor (PR), a memory (MR), and a display module (DM). In one embodiment, the display device applied to the smartphone (EA_1a) includes a display module (DM) and may further include a power module (PM). The processor (PR) and memory (MR) may be provided in the form of chips mounted on a motherboard, which is an external device, but are not limited thereto.

[0199] While the present invention has been described above with reference to preferred embodiments, it will be understood by those skilled in the art or those with ordinary knowledge in the art that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the present invention as set forth in the claims below. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

[0200] The present invention provides a display panel that facilitates gradation expression and an electronic device including the same. Therefore, it has industrial applicability.

Claims

1. Substrate; a plurality of light-emitting elements arranged on the substrate; and It includes a plurality of pixel drivers each electrically connected to the light emitting elements, Each of the above pixel drivers is: A first transistor comprising a first oxide semiconductor pattern having a crystalline structure; A second transistor electrically connected to the first transistor and including a second oxide semiconductor pattern having an amorphous structure; and A display panel including a capacitor electrically connected to the gate of the first transistor.

2. In paragraph 1, A display panel in which the first transistor is a driving transistor and the second transistor is a switching transistor.

3. In paragraph 1, A display panel wherein the first oxide semiconductor pattern includes at least one of indium, gallium, and zinc.

4. In paragraph 1, A display panel wherein the second oxide semiconductor pattern includes at least one of indium, tin, gallium, and zinc.

5. In paragraph 1, A display panel in which the second oxide semiconductor pattern includes indium, tin, gallium, and zinc, and the second oxide semiconductor pattern has a composition ratio of indium in the range of about 60-80 wt%, tin in the range of 0.5-8 wt%, gallium in the range of 5-15 wt%, and zinc in the range of 10-30 wt%.

6. In paragraph 1, A display panel in which the first oxide semiconductor pattern and the second oxide semiconductor pattern are arranged on the same layer.

7. In paragraph 6, a lower conductive layer disposed between the first transistor and the substrate; and Further comprising a buffer layer disposed between the lower conductive layer and the first oxide semiconductor pattern, A display panel in which the first oxide semiconductor pattern and the second oxide semiconductor pattern are disposed on the buffer layer.

8. In paragraph 7, A display panel in which the source of the first transistor is electrically connected to the lower conductive layer.

9. In paragraph 1, A display panel wherein each of the first transistor and the second transistor has a top-gate structure.

10. Display panel; and including a processor that electrically controls the display panel; The above display panel, substrate; A light emitting element disposed on the substrate; a driving transistor disposed on the substrate and electrically connected to the light-emitting element; and It comprises a driving transistor and a plurality of switching transistors electrically connected to the light emitting element, The above driving transistor includes a first oxide semiconductor pattern having a crystalline structure, An electronic device wherein each of the above switching transistors includes a second oxide semiconductor pattern having an amorphous structure.

11. In paragraph 10, An electronic device wherein each of the driving transistor and the switching transistor has a top-gate structure.

12. In paragraph 11, An electronic device in which the first oxide semiconductor pattern and the second oxide semiconductor pattern are arranged on the same layer.

13. In paragraph 12, An electronic device in which the source electrodes and drain electrodes of each of the driving transistor and the switching transistor are arranged on the same layer.

14. In paragraph 12, a buffer layer disposed between the substrate and the driving transistor; and Further comprising a lower conductive layer disposed between the buffer layer and the substrate and overlapping the first oxide semiconductor pattern, An electronic device in which the source of the above driving transistor contacts the lower conductive layer.

15. In paragraph 10, The above first oxide semiconductor pattern is about 30 An electronic device having a charge mobility of the above.

16. In paragraph 10, The above second oxide semiconductor pattern is an electronic device having a driving range of about 0.4 V or more.

17. A step of forming a first thin film transistor including a first semiconductor pattern on a substrate; A step of forming a second thin film transistor including a second semiconductor pattern spaced apart from the first semiconductor pattern on the substrate; and Comprising a step of forming a light-emitting element on the substrate, The step of forming the first thin film transistor comprises: A step of forming a first semiconductor layer using a first oxide semiconductor material; A step of forming the first semiconductor pattern by patterning the first semiconductor layer; and comprising a step of crystallizing the first semiconductor pattern; The step of forming the second thin film transistor is: A step of forming a second semiconductor layer using a second oxide semiconductor material on the first semiconductor pattern; and A step of forming the second semiconductor pattern by patterning the second semiconductor layer is included, A method for manufacturing a display panel in which the second semiconductor pattern has an amorphous structure.

18. In paragraph 17, A method for manufacturing a display panel, wherein the second semiconductor layer is formed in contact with the first semiconductor pattern.

19. In paragraph 18, The step of patterning the second semiconductor layer includes the step of etching the second semiconductor layer using an etchant, A method for manufacturing a display panel in which the first semiconductor pattern is exposed to the etching solution.

20. In paragraph 17, A method for manufacturing a display panel, wherein the source, drain, and channel of each of the first semiconductor pattern and the second semiconductor pattern are formed simultaneously.

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