Processor reconfigurable programmable switching structure and programmable data plane chip

Abstract

The present application relates to the technical field of programmable data planes, and in particular to a processor reconfigurable programmable switching structure and a programmable data plane chip. The structure comprises: a first side path used for transmitting a data packet header vector (PHV); a second side path used for transmitting data and control signals other than the PHV; and a reconfigurable processor sequence comprising a plurality of reconfigurable processors and in communication with the first side path and the second side path, each reconfigurable processor being allowed to be reconfigured into a pipeline stage or a run-to-complete (RTC) processor, a data path for transmitting the PHV existing between every adjacent reconfigurable processors, and different connection operations being performed on the basis of the reconfigurable processors at two ends of the data path. Thus, the problems of limited architecture programmability, insufficient throughput, and high network communication delay of a programmable switching chip in the related art are solved.

Description

Processor-reconfigurable programmable switching architecture and programmable data plane chip

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202410929824.0, filed on July 11, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of programmable data plane technology, and in particular to a processor-reconfigurable programmable switching structure and a programmable data plane chip. Background Technology

[0004] Software-defined networking comprises a data plane and a control plane. The data plane is responsible for protocol parsing and inverse parsing, and packet processing, while the control plane is responsible for issuing parsing rules and flow table matching rules. From customized protocol forwarding to supporting intra-network computing applications, high-performance programmable switching chips further unlock the potential of data plane devices. Programmable switching chip architectures can be categorized into three types: pipelined, RTC (Run-To-Complete), and a hybrid architecture combining both.

[0005] Programmable switching chips employing pipelined architectures often exhibit relatively high throughput and relatively low processing latency, but they also have the following drawbacks:

[0006] 1. The number of computational steps that can be performed at each stage of the pipeline is limited;

[0007] 2. Due to the unidirectional nature of the pipeline, there is no efficient mechanism to transmit data to earlier stages;

[0008] To address the aforementioned drawbacks, if the packet processing flow meets any of the following conditions: it contains a large amount of computational requirements, the processing flow is long and cannot be parallelized due to dependencies, or it is necessary to write state data back to an earlier stage, then the pipeline architecture needs to recirculate the packets (i.e., resend the packets leaving the pipeline to the pipeline head for processing again). Recirculation will cause a significant increase in the latency of the recirculated packets, a decrease in system throughput, and the need for the recirculated packets to occupy pipeline processing capacity multiple times. This will also reduce the processing capacity of background traffic other than the recirculated traffic and create potential out-of-order issues, thus disrupting the strong state consistency of stateful applications.

[0009] If you don't use a re-loop, there are generally three solutions:

[0010] 1. Submit such tasks to the control plane for processing;

[0011] 2. Forward data packets that require this type of task to a dedicated network function server for processing;

[0012] 3. Connect an external FPGA (Field-Programmable Gate Array) or other dedicated hardware to the switching chip for processing;

[0013] All three solutions mentioned above significantly increase the cost of the solution and still fail to address the significant increase in latency caused by re-circulated packets and the potential for out-of-order delivery, which undermines the strong state consistency of stateful applications.

[0014] The RTC processor can process a data packet until the entire processing flow is complete, and can execute long and complex processing flows without forwarding it to other hardware modules. However, it also faces problems such as insufficient throughput, high latency, and difficulty in guaranteeing state consistency.

[0015] Summary of the Invention

[0016] This application provides a processor-reconfigurable programmable switching structure and a programmable data plane chip to solve the problems of limited programmability, insufficient throughput, and high latency in network communication of programmable switching chips in related technologies.

[0017] A first aspect of this application provides a processor-reconfigurable programmable switching structure, comprising: a first side path for transmitting a PHV (Packet Header Vector); a second side path for transmitting other data and control signals besides the PHV; and a reconfigurable processor sequence including multiple reconfigurable processors. The first and second side paths connect the multiple reconfigurable processors. Each of the multiple reconfigurable processors can be reconfigured into a pipeline stage or run to the completion of an RTC (Real-Time Communication) processor. A data path for transmitting the PHV exists between each adjacent reconfigurable processor. When both ends of the data path are reconfigurable processors reconfigured into pipeline stages, the data path is opened to connect the two pipeline stages to the complete pipeline. When both ends of the data path are not reconfigurable processors reconfigured into pipeline stages, the data path is closed. The reconfigurable processors reconfigured into RTC processors are connected via the first side path.

[0018] Optionally, a reconfigurable processor includes a processor that is reconfigurable in all of the following areas, or a processor that is reconfigurable in some of the following areas but not in others, or a processor that is reconfigurable in some of the following areas but not in others: Register array, used in the pipeline stage to store packet header fields, metadata, and intermediate signals; in an RTC processor, the register array serves as a register group defined by the instruction set; Data memory, used in the pipeline stage to store lookup tables and status tables. The lookup tables are used for searching as packets pass through, and the status tables are used for reading, modifying, and writing back status as packets pass through. In an RTC processor, the data memory stores packet header fields, metadata, lookup tables, status tables, and intermediate signals. If the RTC processor runs an operating system, the data memory also stores data structures related to operating system maintenance; Instruction memory, used to store instructions in both the pipeline stage and the RTC processor; ALU (Arithmetic Logic Unit), used to perform arithmetic logic calculations in both the pipeline stage and the RTC processor; SALU (Stateful Arithmetic Logic Unit). The Arithmetic Logic Unit (ALU), in the pipeline stage, reads the state from the state table in the data memory, performs arithmetic logic calculations, and writes the result back to the state table. In the RTC processor, it reads data from the data memory, performs arithmetic logic calculations, and writes the result back to the data memory. The matching module, in both the pipeline stage and the RTC processor, is used to search and match in the lookup table of the data memory based on a given keyword, and returns whether there is a matching entry and the corresponding entry content.

[0019] Optionally, when the reconfigurable processor is reconfigured into a pipeline stage, the process includes: after the PHV of a data packet is received by the current processor, it is written to the register array of the current processor; according to the keyword selection rules specified by the user program, a portion of the fields are selected to form a keyword and sent to the matching module; the matching module searches and matches in the lookup table of the data memory according to the given keyword, and when a matching entry exists, the execution operation ID (IDentification) is determined according to the content of the entry; when no matching entry exists, the default operation ID specified by the user program is used; the instruction is read from the instruction memory according to the operation ID, the instruction is parsed using a decoder, and the parsed instruction is dispatched to the ALU and SALU, wherein the ALU reads the fields involved in the calculation from the register array or instruction parameters, performs the calculation, and writes it back to the register array; the SALU reads the fields involved in the calculation from the register array or instruction parameters, and reads the status involved in the calculation from the status table in the data memory, performs the calculation, and writes it back to the register array and / or the status table in the data memory; in the processing flow, the PHV of a data packet is passed in the register array corresponding to different pipeline beats, and after processing, the corresponding PHV is sent out of the current processor.

[0020] Optionally, when the reconfigurable processor is reconfigured into an RTC processor, the process includes: after the PHV of the data packet is received by the current processor, it is written into the current processor's data memory and notified to start the processing flow; the current processor reads the instructions to be executed from the instruction register according to the program counter until the processing termination instruction is read; each instruction read is parsed by a dedicated decoder and assigned to the ALU or SALU, wherein the ALU reads the fields to be calculated from the register array or instruction parameters, calculates and writes back to the register array; the SALU reads the fields to be calculated from the register array or instruction parameters and reads the data to be calculated from the data memory, calculates and writes back to the register array and / or data memory; the matching module may or may not be connected to the RTC processor. If the matching module is connected to the RTC processor, the current processor supports matching instructions, extracts the data required by the instruction from the register array and submits it to the matching module, and the matching module writes the matching result back to the register array.

[0021] Optionally, the reconfigurable processor allows it to be reconfigured into multiple RTC cores, with the number of RTC cores determined based on the parallelism of the pipeline stages.

[0022] Optionally, it also includes: a parser, a payload buffer, an inverse parser, and a hardware load, wherein the parser and the inverse parser are connected to a first side path, the payload buffer and the hardware load are connected to a second side path, and the parser is also connected to the payload buffer for parsing data packets to obtain PHV and payload, and sending the payload to the payload buffer.

[0023] Optionally, the first side path includes multiple first-path nodes. In the first side path, after the PHV undergoes a complete pipeline processing flow, it is sent by the last reconfigurable processor in the pipeline that is reconfigured into a pipeline stage to the corresponding first-path node. Specifically, for PHVs that do not need to be sent to the RTC processor for processing, they are passed along the first path, which starts from the first-path node corresponding to the last reconfigurable processor in the pipeline that is reconfigured into a pipeline stage and is directly passed along the first side path to the first-path node corresponding to the reverse parser. For PHVs that need to be sent to the RTC processor for further processing, they are passed along the second path, which starts from the first-path node corresponding to the last reconfigurable processor in the pipeline that is reconfigured into a pipeline stage and is passed along the first side path to the first-path node corresponding to the RTC processor where the RTC core to which it is assigned is located. The PHV is then downloaded to the RTC core to which it is assigned for processing. After processing is completed, the PHV is uploaded to the first-path node corresponding to the RTC processor where the RTC core that processed the PHV is located during an idle period of the corresponding first-path node.

[0024] Optionally, the first path and the second path share a common source and sink. The source is the first path node corresponding to the last reconfigurable processor reconfigured into the pipeline stage, and the sink is the first path node corresponding to the inverse parser. The sink has a buffer to handle congestion. When the buffer meets the condition of being about to overflow, the buffer sends a target signal to the reconfigurable processor reconfigured into the RTC processor, so that no new PHV is uploaded to the second path based on the target signal.

[0025] Optionally, the second side path includes at least one second path node, and the second side path supports at least one data transfer, including: sending a request from a reconfigurable processor reconfigured as an RTC processor to read the payload of a data packet processed by the reconfigurable processor reconfigured as an RTC processor from the payload buffer, and transferring the payload back to the reconfigurable processor reconfigured as an RTC processor, wherein the payload is stored in the data memory of the reconfigurable processor reconfigured as an RTC processor for subsequent processing; sending a request from a reconfigurable processor reconfigured as an RTC processor to read data from the data memory or register array on another reconfigurable processor, and transferring the read data back to the data memory processed by the reconfigurable processor reconfigured as an RTC processor that sent the read request; sending a request from a reconfigurable processor reconfigured as an RTC processor to write data to the data memory or register array on another reconfigurable processor; and sending a request from a reconfigurable processor reconfigured as an RTC processor to send data to a hardware payload, and the hardware payload sends the processing result back to the reconfigurable processor reconfigured as an RTC processor.

[0026] A second aspect of this application provides a programmable data plane chip, including a processor-reconfigurable programmable switching structure of any of the above embodiments.

[0027] Therefore, this application has the following beneficial effects:

[0028] This application's embodiments, by reconfiguring the reconfigurable processor into a pipelined stage or RTC processor, significantly improve the programmability of the switch while consuming only a small amount of chip area. This allows network applications originally deployed on servers and middleware boxes to be offloaded to the programmable switch, reducing network communication latency, improving network service performance, and lowering the data center network's demand on server and middleware box equipment, thereby reducing the construction and maintenance costs of the data center network. Thus, it solves the problems of limited programmability, insufficient throughput, and high network communication latency inherent in related technologies' programmable switch chips.

[0029] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0030] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0031] Figure 1 is a schematic diagram of the Banzai architecture technology in related technologies;

[0032] Figure 2 is a schematic diagram of the Trio architecture technology in related technologies;

[0033] Figure 3 is a schematic diagram of the Sirius architecture technology in related technologies;

[0034] Figure 4 is a block diagram of a processor-reconfigurable programmable switching architecture according to an embodiment of this application;

[0035] Figure 5 is an example diagram of the composition structure and data path of a reconfigurable processor according to an embodiment of this application. Detailed Implementation

[0036] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0037] The following description, with reference to the accompanying drawings, describes a processor-reconfigurable programmable switching architecture and a programmable data plane chip according to embodiments of this application. Addressing the problems mentioned in the background section, this application provides a processor-reconfigurable programmable switching architecture. By reconfiguring the reconfigurable processor into a pipeline stage or an RTC processor, the programmability of the switch is significantly improved while consuming only a small amount of chip area. This allows network applications originally deployed on servers and middleware boxes to be offloaded to the programmable switch, reducing network communication latency, improving network service performance, and reducing the demand on server and middleware box equipment in data center networks, thereby lowering the construction and maintenance costs of data center networks. Thus, it solves the problems of limited programmability, insufficient throughput, and high network communication latency in related technologies' programmable switching chips.

[0038] Before introducing the specific content of this application, the relevant technical items involved in this application will be described in detail, including the following:

[0039] 1. Related Technologies

[0040] As shown in Figure 1, Banzai is the technical prototype of Intel's Tofino programmable switch. When a data packet arrives, Banzai uses a programmable parser to extract the header field and processes the header through two pipelines: one for ingress and one for egress. These two identical pipelines constitute Banzai's programmable packet processing logic. Each pipeline consists of a series of stages, or MAUs (Match-Action Units), which are the basic programmable units in this prototype. Users program the MAUs in two ways using the P4 program: which flow table the data packet needs to query at that stage, and what processing logic should be executed after the query result is obtained. In Banzai, the processing logic of each stage uses a set of parallel atomic operations, each of which can perform a "read-add / subtract-write" function.

[0041] Programmable switching chips with pipelined architecture often have high throughput and low latency, but pipelines encounter difficulties when handling the following network tasks: (1) High computational requirements. Since the processing logic in each MAU uses a set of parallel atomic operations, meaning that only one cycle in each MAU will actually perform the computation, if the packet processing flow contains a large amount of computation, the interval between two computations is the latency of an entire MAU, which seriously affects the packet processing latency. When the amount of computation reaches a certain level, the number of computations provided by the pipeline length is insufficient to accommodate the complete computation, thus requiring re-looping, resulting in a significant decrease in throughput. (2) Complex stateful functions. Due to the simplicity of atomic operations, only simple stateful functions (such as counters) can be implemented via atomic operations. For more complex functions, the logic for determining the next state may involve a series of operations and table accesses, which cannot be implemented via atomic operations. In order to avoid pipeline bottlenecks, this technical solution cannot support these stateful functions by simply extending the atomic operation circuit and enhancing the atomic operation function. Due to the unidirectional nature of the pipeline, there is no effective mechanism to write the state data back to the earlier stage. The only method is still re-looping, resulting in a significant decrease in throughput. (3) Long dependency chains between statements. Since the processing logic in each MAU uses a set of parallel atomic operations, if one statement in the packet processing flow needs the computation result of another statement (i.e., depends on this statement), these two statements cannot be executed in parallel and must be deployed in different MAUs. When the length of the dependency chain between statements reaches N, N different MAUs are needed to execute this processing flow, even if a large amount of storage and computing resources in these N MAUs are wasted. This causes serious resource waste, and for more complex packet processing flows (such as network service chains), the usual pipeline length (i.e., the number of MAUs) is insufficient to deploy the complete flow, thus requiring packet re-circulation and causing a significant decrease in throughput.

[0042] 2. Related Technology II

[0043] Trio is the technology prototype of Juniper's MX series programmable switches. The unit that processes packets in Trio is the PFE (Packet Forwarding Engine), and one PFE can be integrated onto a single chip. To expand the switch's processing capacity, multiple PFEs need to be connected through a switching network. The structure of a PFE, as shown in Figure 2, contains hundreds of PPEs (Packet Processing Engines). After a packet enters the PFE, its payload is stored in a buffer, and the header is dispatched to the target PPE via a dispatcher and a fully connected network. Each PPE is an RTC processor that can access a shared memory system (including SRAM (Static Random Access Memory) cache and off-chip DRAM (Dynamic Random Access Memory)), hardware acceleration modules such as hashing and filtering, and the buffer storing the payload through the same fully connected network. After the packet header is processed in the PPE, it is reordered by a reordering engine to ensure that the sending order matches the arrival order of the packets, and then assembled with the payload in the buffer before being sent out.

[0044] Because the PPE is an RTC processor, the processing of a single packet can continue until the entire processing flow is complete. Therefore, Trio can execute longer and more complex processing flows without being limited by pipeline length. However, it also faces the following challenges: (1) Insufficient throughput. Due to chip size and power limitations, the network throughput that a single PFE chip can support is quite limited, approximately 1-2 orders of magnitude lower than that of a pipelined programmable switch chip. (2) Higher latency. PPE accesses memory (such as looking up flow tables and state tables) through a fully connected network from a shared storage system. The latency of a single memory access is approximately 1-2 orders of magnitude lower than that of a pipelined programmable switch chip using MAU dedicated memory. For state tables that may experience read / write conflicts, synchronization mechanisms such as locking will further increase the memory access latency. (3) Difficulty in guaranteeing state consistency. Because the throughput of each PPE is very low, when processing large-scale stateful streams, the same stream may be assigned to different PPEs, resulting in the order in which the packets of the stream are processed and the order in which the packets arrive. When the application requires strong state consistency or strict bounded stale consistency, this will cause state consistency to be compromised.

[0045] 3. Related Technologies

[0046] Sirius is a technology prototype of AMD's Pensando DPU (Data Processing Unit), whose architecture, as shown in Figure 3, includes two general-purpose pipelines and three dedicated pipelines for DMA (Direct Memory Access). Each pipeline in Sirius contains a TE (Table Engine) and several MPUs (Match Processing Units). The MPU's function is similar to the MAU in Banzai, but it does not contain memory or a corresponding memory access module. When an MPU needs to access memory, it accesses its shared memory system (including SRAM cache and off-chip DRAM) via a NOC (Network on Chip) interconnect network through the TE. This NOC interconnect network also connects to the server's PCIe port, hardware accelerators for compression, encryption, CRC (Cyclic Redundancy Check), and a set of embedded ARM cores. When a data packet cannot complete its processing through the pipeline, it is sent via the NOC interconnect network to the ARM cores operating in RTC mode for processing.

[0047] By integrating pipeline and RTC architectures, Sirius separates simple tasks from complex ones. Simple tasks can be processed in a high-performance manner through the pipeline, while complex tasks can be sent to the more programmable RTC core without being limited by pipeline length. However, existing converged architectures still have the following problems: (1) Inapplicable to switch scenarios. Existing converged architectures are designed for smart NICs, DPUs, or IPUs (Infrastructure Processing Units). For example, the AMD Pensando DSC2-200 has a designed bandwidth of only 400Gbps, which cannot be used in switch scenarios. (2) Insufficient scalability. Converged architectures always connect the pipeline and RTC core through a fully interconnected bus or shared memory. These structures expand rapidly with a complexity of O(N²) as the number of access modules N increases, resulting in unacceptable chip area and power consumption. (3) Resource idleness. Due to the rapid development of software-defined networking, network switching equipment manufacturers cannot accurately predict the network services their devices will support in the future. Different network services have significantly different requirements for pipeline length and RTC cores. Services with stringent performance requirements such as throughput and latency may require longer pipelines, while services with complex processing flows may require more RTC cores. To meet user needs in different scenarios, manufacturers of converged architecture network switching equipment need to provide the longest possible pipelines and the largest number of RTC cores. However, when a user service only requires one type of computing resource, the computing resources for the other are idle, thus reducing the effective utilization of chip area.

[0048] Specifically, Figure 4 is a block diagram of a processor reconfigurable programmable switching structure provided in an embodiment of this application.

[0049] As shown in Figure 4, the reconfigurable programmable switching structure of the processor includes: a first side path, a second side path, and a reconfigurable processor sequence.

[0050] The first side path is used to transmit the data packet header vector (PHV). The PHV consists of fields that need to be processed in the data packet header and other metadata fields generated during data packet processing, arranged in a certain order, with a typical bit width of 4096 bits. The second side path is used to transmit other data and control signals besides the PHV. A reconfigurable processor sequence includes multiple reconfigurable processors. The first and second side paths connect the multiple reconfigurable processors. Each of the multiple reconfigurable processors can be reconfigured into a pipeline stage or an RTC processor. An RTC allows a data packet to run its entire processing flow on one processor until completion, without being sent to other processors, corresponding to the process in a pipeline structure where each stage processes only one step. There is a data path for transmitting the PHV between each adjacent reconfigurable processor. When both ends of the data path are reconfigurable processors reconfigured into pipeline stages, the data path is opened to connect the two pipeline stages into a complete pipeline. When both ends of the data path are not reconfigurable processors reconfigured into pipeline stages, the data path is closed, and the reconfigurable processors reconfigured into RTC processors are connected through the first side path.

[0051] In this embodiment, a reconfigurable processor is a special processor architecture that can be reconfigured into a stage of a pipeline (e.g., a MAU) or an RTC processor based on the contents of the configuration registers issued by the compiler. The structure of a reconfigurable processor is shown in Figure 5, and it includes a series of hardware components and the connections between them. When reconfigured into a pipelined or RTC architecture, specific components and their connections become valid, thereby enabling the reuse of hardware resources.

[0052] Furthermore, the embodiments of this application adopt the structure shown in Figure 4 to connect the various reconfigurable processors in series, which mainly includes a set of linearly arranged reconfigurable processor sequences, a first side path for transmitting PHV and a second side path for transmitting other data and control signals.

[0053] In this process, after the data packet passes through the parser, the parsed PHV (Prognostics Value) enters the first reconfigurable processor in the reconfigurable processor sequence (or the first node of the first side path if all reconfigurable processors are reconfigured into RTC processors). The remaining payloads are stored in the SRAM buffer. There are data paths between reconfigurable processors that can transfer PHVs. When both ends of the data path are reconfigurable processors that have been reconfigured into pipeline stages, the data path is opened to connect the two pipeline stages to the complete pipeline; when both ends of the path are not reconfigurable processors that have been reconfigured into pipeline stages, the data path is closed and no PHV is transferred. Therefore, in the entire reconfigurable processor sequence, the first few (or zero) reconfigurable processors are reconfigured into pipeline stages and connected to form a complete pipeline through the data paths between them. The last few (or zero) reconfigurable processors are reconfigured into RTC processors, each of which is relatively independent and connected only through the first side path.

[0054] It should be noted that the parallelism of the reconfigurable processor when it is reconfigured into a pipeline stage is determined to determine the number of RTC cores when it is reconfigured into an RTC processor. When the reconfigurable processor uses a larger chip area, it has greater parallelism as a pipeline stage (e.g., it can look up more tables simultaneously), and more cores as an RTC processor. This gives the embodiments of the present application good scalability. When manufacturers are willing to pay more for chip area and power consumption, performance can be linearly improved (under hardware routing capability limitations). In addition, side paths include, but are not limited to, interconnects with similar principles such as ring interconnects and unidirectional or bidirectional linear interconnects. A ring interconnect is shown in Figure 4, and the side paths in the embodiments of the present application are exemplified by the ring interconnect shown in Figure 4.

[0055] In one embodiment of this application, the reconfigurable processor includes a processor in which all of the following items are reconfigurable, or a processor in which some of the following items are reconfigurable and other items are not included in the processor, or a processor in which some of the following items are reconfigurable and other items are not reconfigurable, and further includes a register array, data memory, instruction memory, ALU, SALU, and a matching module. Each reconfigurable processor can be reconfigured into a pipeline stage or an RTC processor. The reusable components between the pipeline stage and the RTC processor in this embodiment of the application are as follows:

[0056] 1) Register Array. During the pipeline stage, the register array is used to store packet header fields, metadata, and intermediate signals used in the processing flow. To avoid pipeline congestion, this data is required to be stored in the register array rather than RAM. In RTC processors, the register array is used to store both general-purpose and special-purpose registers.

[0057] 2) Data Memory. During the pipeline stage, data memory is used to store lookup tables for data packets to be searched as they pass through, and to execute corresponding operations based on the lookup results. Data memory also stores state tables for data packets to be read, modified, and written back as they pass through. In an RTC processor, data memory stores packet header fields, metadata, lookup tables, state tables, and intermediate signals used in the processing flow. If the RTC processor has an operating system, data memory also stores data structures such as the stack maintained by the operating system.

[0058] 3) Instruction memory. Used to store instructions in both the pipeline stage and RTC processors, but the instruction formats differ.

[0059] 4) ALU. Used to perform arithmetic and logic calculations in both the pipeline stage and the RTC processor.

[0060] 5) SALU. In the pipeline stage, it is used to read the state from the state table in the data memory, perform arithmetic and logical calculations, and then write the calculation result back to the state table. In the RTC processor, it is used to read data from the data memory (not limited to the state table), perform arithmetic and logical calculations, and then write the calculation result back to the data memory.

[0061] 6) Matching Module. Used in both the pipeline stage and the RTC processor to search and match against a given keyword in the data storage lookup table, returning whether a matching entry exists and its contents.

[0062] It should be noted that, in order to achieve a reconfigurable processor, the embodiments of this application reuse the aforementioned multiple hardware components. The reuse of any one of these hardware components to achieve reconfigurability is not limited to the reuse of every reusable component mentioned in the embodiments of this application.

[0063] In one embodiment of this application, when the reconfigurable processor is reconfigured into the pipeline stage, the parsed data packet header and its carried metadata fields (i.e., PHV) are received by the current processor and written into the current processor's register array. Based on the keyword selection rules specified by the user program, a subset of fields is selected to form a keyword, which is then transmitted to the matching module. The matching module searches and matches the given keyword in the lookup table of the data storage. When a matching entry exists, the operation ID to be executed is determined based on the entry content; when no matching entry exists, the default operation ID specified by the user program is used. The corresponding instruction is read from the instruction memory based on the operation ID, parsed using a dedicated decoder, and dispatched to the ALU and SALU. The ALU reads the fields involved in the calculation from the register array or instruction parameters, performs the calculation, and writes it back to the register array. The SALU reads the fields involved in the calculation from the register array or instruction parameters, and reads the state involved in the calculation from the state table in the data storage, performs the calculation, and writes it back to the register array and / or the state table in the data storage.

[0064] In the entire processing flow described above, the PHV of a data packet is passed between registers in the register array corresponding to different pipeline beats to achieve uninterrupted pipeline functionality. After processing is complete, the corresponding PHV is sent out of the current processor.

[0065] In one embodiment of this application, when the reconfigurable processor is reconfigured into an RTC processor, the PHV is received by the current processor, written into the current processor's data memory, and the current processor is notified to begin executing the processing flow. The RTC processor continuously reads the instructions to be executed from the instruction register according to the PC (Program Counter) until it reads the processing termination instruction.

[0066] Each instruction read is parsed by a dedicated decoder and then dispatched to the ALU or SALU. The ALU reads the fields to be calculated from the register array or instruction parameters, performs the calculation, and writes it back to the register array. The SALU reads the fields to be calculated from the register array or instruction parameters, and reads the data to be calculated from the data memory, performs the calculation, and writes it back to the register array and / or data memory. Branch jump instructions in the instruction will modify the contents of the PC.

[0067] The RTC processor can write the extracted key code into a register array and submit it to the matching module via specific instructions. The matching module acts as a coprocessor and writes the result back to the register array. After reading the processing termination instruction, the corresponding PHV is sent out of the current processor.

[0068] It's important to note that a reconfigurable processor can be reconfigured into multiple RTC cores, and the number of convertible RTC cores is determined by the parallelism of the pipeline stages. During the pipeline stages, instructions may be given in VLIW (Very Long Instruction Word) form and parsed, dispatched to multiple ALUs or SALUs for parallel execution. Simultaneously, the pipeline stages provide multiple memory access channels and multiple function accelerators (such as hashes, typically integrated within the matching module). Therefore, multiple sets of parallel functional components can be allocated to different cores in the RTC processor, thus enabling the reconfiguration of a single pipeline stage into multiple RTC cores.

[0069] The RTC processor does not participate in the receiving and sending of PHVs, but can process other PHVs while receiving and sending PHVs. Each RTC core contains a PHV buffer to temporarily store received PHVs that have not yet been processed, as well as PHVs that have been processed but have not yet been sent.

[0070] It should be noted that the above content pertains to the reconfigurable processor, specifically the portion that applies both when the reconfigurable processor is reconfigured into a pipeline stage and when it is reconfigured into an RTC processor, not the entirety of the reconfigurable processor. The entirety of the reconfigurable processor includes:

[0071] 1. Instruction decoders specifically designed for the pipeline stage and instruction decoders specifically designed for RTC processors;

[0072] 2. Configuration registers dedicated to the pipeline stage and configuration registers dedicated to the RTC processor, as well as other registers (including the program counter);

[0073] 3. A circuit that connects all the above modules in a specific way;

[0074] 4. Regarding the configuration register of the above circuit, depending on the state of the configuration register, part of the circuit is connected while another part is disconnected. The circuit connected to the switching structure can enable the reconfigurable processor as a pipeline stage or the RTC processor to be connected to the entire switching structure.

[0075] Furthermore, the processor's reconfigurable programmable switching architecture also includes: a parser, a payload buffer, an inverse parser, and a hardware payload.

[0076] Specifically, the parser, the deparser, and each reconfigurable processor are connected to the first side path and hold a corresponding external path node. The first side path includes multiple first path nodes. After the PHV undergoes a complete pipeline processing flow, it is sent by the last reconfigurable processor in the pipeline to its corresponding first path node. This node determines whether the PHV needs to be sent to an RTC processor for further processing, and which RTC processor it needs to be sent to, based on a special field in the PHV.

[0077] For PHVs that do not need to be sent to the RTC processor for further processing, they start from the first path node corresponding to the last reconfigurable processor in the pipeline that is reconfigured into the pipeline stage, and are directly passed to the first path node corresponding to the inverse parser along the first side path, which is the first path.

[0078] For PHVs that need to be sent to the RTC processor for further processing, the first path node corresponding to the last reconfigurable processor in the pipeline stage is started from, and the PHV is passed to the corresponding RTC processor along the first side path. It is then downloaded to the RTC core that is assigned to it for processing. After processing is completed, the idle period of the corresponding first path node is selected, and the PHV is sent to the first path node and then passed forward to the first path node corresponding to the reverse parser, which is the second path.

[0079] Furthermore, in this embodiment, the first path and the second path share a common source and sink. The source is the first path node corresponding to the last reconfigurable processor rebuilt into the pipeline stage, and the sink is the first path node corresponding to the inverse parser. Other nodes are not shared to ensure that data packets passing through the first path that do not require complex processing can always be processed with low latency. When a reconfigurable processor is reconfigured into an RTC processor containing more than one core, a scheduling module is included at the first path node corresponding to each reconfigurable processor to schedule the PHVs sent from each RTC core on the reconfigurable processor to the first path node using a round-robin method.

[0080] Furthermore, the first and second paths in this embodiment share a common sink, namely the first path node corresponding to the inverse parser. The sink has a buffer to handle temporary congestion. When this buffer is about to overflow, it sends a signal to the reconfigurable processor, which is reconfigured as an RTC processor, requesting it to stop uploading new PHVs to the second path. This mechanism allows the data memory used to store PHVs in all RTC processors to be used as a buffer to handle sink congestion. Each time a packet enters this buffer, it means that the first path is idle for one cycle, thus allowing a packet from the second path to be scheduled. This ensures that the number of packets on the second path does not increase when this mechanism is triggered, thus guaranteeing that congestion at the sink can be resolved without packet loss.

[0081] In one embodiment of this application, each reconfigurable processor, load buffer, and other hardware loads (such as shared memory and accelerators) are connected to a second side path and hold a corresponding second-path node. The second side path includes at least one second-path node and is used for the transmission of control signals and data, supporting data transmission of at least one of the following:

[0082] 1) A request is sent from the reconfigurable processor that has been reconfigured into an RTC processor to read the payload of the data packet processed by the reconfigurable processor that has been reconfigured into an RTC processor in the payload buffer, and the payload is passed back to the reconfigurable processor that has been reconfigured into an RTC processor to implement DPI (Deep Packet Inspection). The payload is stored in the data memory of the reconfigurable processor that has been reconfigured into an RTC processor for subsequent processing.

[0083] 2) Send a request from the reconfigurable processor that has been reconfigured into an RTC processor to read data from the data memory or register array on another reconfigurable processor, and pass the read data back to the data memory processed by the reconfigurable processor that sent the read request.

[0084] 3) Send a request from the reconfigurable processor that has been reconfigured into an RTC processor to write data to the data memory or register array on other reconfigurable processors.

[0085] 4) A request is sent from the reconfigurable processor that has been reconfigured into an RTC processor to send data to the hardware workload, and the hardware workload sends the processing result back to the reconfigurable processor that has been reconfigured into an RTC processor.

[0086] The following embodiments of this application can be used as examples of on-network computing applications that are not supported by current chips but can be supported by this application, including the following application scenarios:

[0087] Application Scenario 1 (Intra-network Aggregation):

[0088] As large-scale modeling technology stands out in various artificial intelligence applications, distributed neural networks are widely deployed in data center networks. Computational nodes in the network require extensive communication to synchronize training parameters, a crucial operation being the aggregation of gradients calculated by each node. Traditionally, aggregation is performed using servers, which places a significant communication burden on the server's network interface, thus slowing down the convergence speed of the entire neural network training. ATP proposed a solution for intra-network aggregation on programmable switches, but its intra-network aggregation capability on programmable switches is limited by the current chip pipeline length. Furthermore, current chips cannot achieve effective functional isolation when used for intra-network aggregation. Processing intra-network aggregated traffic significantly reduces the programmable switch's ability to handle non-intra-network aggregated traffic, limiting other locally available bandwidth and lowering the overall service quality of the cloud data center network. While Trio technology can overcome the pipeline length limitation, it still cannot achieve functional isolation, and intra-network aggregated traffic still significantly degrades the overall switch performance. This invention overcomes the pipeline length limitation on aggregation capability by sending intra-network aggregated traffic to the RTC core for processing, and effectively isolates it from other traffic processed on the pipeline.

[0089] Application Scenario 2 (Internal Cache):

[0090] Intra-network caching technology is highly effective for accelerating query server caching. A portion of server query results are cached on the switch. If a new query packet hits the cache, the cached result is returned directly without forwarding it to the server. If the cache is not hit, the server returns the query result, which is written to the cache as it passes through the switch, replacing the outdated entry. NetCache uses a controller to handle cache replacement, creating a performance bottleneck. P4LRU implements an LRU cache replacement function in the pipeline, but due to the limitations of existing chip pipeline programmability, each LRU group can only support three entries. This results in a significantly lower hit rate compared to the ideal LRU when data locality is not ideal. Furthermore, under current technology, pipeline memory resources cannot be fully utilized to store intra-network cache entries, preventing the intra-network cache from fully leveraging the switch's memory potential. This invention uses the pipeline as a Level 1 cache, forwarding to the RTC core to search the Level 2 cache if the Level 1 cache misses. Leveraging the RTC core's ability to maintain complex data structures, the L2 cache on each core can implement better cache replacement algorithms. At the same time, the RTC core can utilize all available memory on the processor as a cache, allowing more intranet cache entries to be stored on the switch under the same resource conditions. Ultimately, this significantly improves the intranet cache hit rate, further reducing the network and computational load on the server side.

[0091] Application Scenario 3 (Network Service Integration):

[0092] In data center and edge networks, specialized middleware boxes and accelerators supporting various network functions are typically deployed to enhance network security and performance. For example, gateway switches require DDoS detection and mitigation (e.g., SYN flood detection). Other essential network functions include server load balancing and network address translation. Furthermore, telemetry and measurement aimed at improving network visibility (e.g., hit detection and in-band network telemetry) are becoming indispensable for improving efficiency and ensuring quality of service. Deploying multiple single-purpose middleware boxes is not only costly but also complicates network configuration and management. Integrating certain network functions into programmable data plane devices helps reduce costs. On existing pipelined chips, the complexity of network functions may require multiple packet loops, resulting in significant losses in throughput and latency. Similarly, on existing multi-core RTC architecture chips, chip processing performance is significantly reduced due to complex network functions. This invention achieves an organic combination of pipelined and multi-core RTC processors by dividing network services. Basic and commonly used functions applicable to all traffic are handled by the pipeline, while complex functions applicable only to selected packets are handled by the RTC core. Thanks to the reconfigurable processor design of this invention, even without prior knowledge of application and traffic distribution, the way network services are partitioned on pipelines and multi-core RTC processors can be reconfigured to achieve optimal overall processing performance.

[0093] The processor-reconfigurable programmable switching architecture proposed in this application significantly improves the programmability of the switch by reconfiguring the reconfigurable processor into a pipeline stage or an RTC processor, while consuming only a small amount of chip area. This allows network applications originally deployed on servers and middleware boxes to be offloaded to the programmable switch, reducing network communication latency, improving network service performance, and reducing the demand on server and middleware box equipment in the data center network, thereby lowering the construction and maintenance costs of the data center network. This solves the problems of limited programmability, insufficient throughput, and high network communication latency in related technologies' programmable switching chips.

[0094] This application also provides a programmable data plane chip, including the processor-reconfigurable programmable switching structure described in the above embodiments.

[0095] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0096] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0097] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0098] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any of the following techniques known in the art, or a combination thereof: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (FPGAs), field-programmable gate arrays (FPGAs), etc.

[0099] Those skilled in the art will understand that all or part of the steps of the methods implementing the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0100] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A processor-reconfigurable programmable switching architecture, characterized in that, include: The first side path is used to transmit the data packet header vector PHV; The second side path is used to transmit other data and control signals besides PHV; A reconfigurable processor sequence, comprising multiple reconfigurable processors, wherein a first side path and a second side path connect the multiple reconfigurable processors, wherein each of the multiple reconfigurable processors is allowed to be reconfigured into a pipeline stage or run to the completion of an RTC processor, and a data path for transmitting the PHV exists between each adjacent reconfigurable processor. When both ends of the data path are reconfigurable processors reconfigured into pipeline stages, the data path is opened to connect the two pipeline stages to the complete pipeline. When both ends of the data path are not reconfigurable processors reconfigured into pipeline stages, the data path is closed, and the reconfigurable processors reconfigured into RTC processors are connected through the first side path.

2. The processor-reconfigurable programmable switching architecture according to claim 1, characterized in that, The reconfigurable processor includes a processor in which all of the following items are reconfigurable, or a processor in which some of the following items are reconfigurable and other items are not included in the processor, or a processor in which some of the following items are reconfigurable and other items are not reconfigurable: In the pipeline stage, the register array is used to store data packet header fields, metadata, and intermediate signals. In the RTC processor, the register array serves as a register group defined by the instruction set. In the pipeline stage, the data memory is used to store lookup tables and status tables. The lookup tables are used for searching when data packets pass through, and the status tables are used for reading, modifying, and writing back the status when data packets pass through. In the RTC processor, the data memory is used to store data packet header fields, metadata, lookup tables, status tables, and intermediate signals. If the RTC processor is equipped with an operating system, the data memory is also used to store data structures related to operating system maintenance. Instruction memory is used to store instructions in both the pipeline stage and in RTC processors; The Arithmetic Logic Unit (ALU) is used to perform arithmetic logic calculations in both the pipeline stage and the RTC processor. The stateful arithmetic logic unit (SALU) is used in the pipeline stage to read the state from the state table of the data memory, perform arithmetic logic calculations, and write the calculation results back to the state table. In an RTC processor, it is used to read data from the data memory, perform arithmetic and logical calculations, and then write the calculation results back to the data memory. The matching module, used in both the pipeline stage and the RTC processor, is used to search and match in the lookup table of the data storage based on a given keyword, and return whether there is a matching entry and the corresponding entry content.

3. The processor-reconfigurable programmable switching architecture according to claim 2, characterized in that, When the reconfigurable processor is reconfigured into a pipeline stage, it includes: After the PHV of the data packet is received by the current processor, it is written to the register array of the current processor; according to the keyword selection rules specified by the user program, a portion of the fields are selected to form a keyword and sent to the matching module. The matching module searches and matches the given keywords in the lookup table of the data storage. When a matching entry exists, the operation ID is determined based on the entry content; when no matching entry exists, the default operation ID specified by the user program is used. The instruction is read from the instruction memory according to the operation ID, the instruction is parsed using a decoder, and the parsed instruction is assigned to the ALU and SALU. The ALU reads the fields to be calculated from the register array or instruction parameters, performs the calculation, and writes them back to the register array. The SALU reads the fields to be calculated from the register array or instruction parameters, and reads the status of the calculation from the status table in the data memory, performs the calculation, and writes them back to the status table in the register array and / or the data memory. During the processing flow, the PHV of a data packet is passed in the registers of different pipeline beats in the register array, and after processing is completed, the corresponding PHV is sent out of the current processor.

4. The processor-reconfigurable programmable switching architecture according to claim 2, characterized in that, When the reconfigurable processor is reconfigured into an RTC processor, it includes: After the PHV of the data packet is received by the current processor, it is written into the current processor's data memory and notified to start the processing flow. The current processor reads the instructions to be executed from the instruction register according to the program counter until it reads the processing termination instruction. Each instruction read is parsed by a dedicated decoder and then assigned to the ALU or SALU. The ALU reads the fields to be calculated from the register array or instruction parameters, performs the calculation, and writes them back to the register array. The SALU reads the fields to be calculated from the register array or instruction parameters and reads the data to be calculated from the data memory, performs the calculation, and writes them back to the register array and / or data memory. The matching module can be connected to or not connected to the RTC processor. If the matching module is connected to the RTC processor, the current processor supports the matching instruction, extracts the data required by the instruction from the register array and submits it to the matching module, and the matching module writes the matching result back to the register array.

5. The processor-reconfigurable programmable switching architecture according to any one of claims 1-4, characterized in that, The reconfigurable processor allows it to be reconfigured into multiple RTC cores, with the number of RTC cores determined based on the parallelism of the pipeline stages.

6. The processor-reconfigurable programmable switching architecture according to claim 1, characterized in that, Also includes: The parser, payload buffer, inverse parser, and hardware load are configured to parse data packets to obtain PHV and payload, and send the payload to the payload buffer.

7. The processor-reconfigurable programmable switching architecture according to claim 6, characterized in that, The first side path includes multiple first-path nodes. In the first side path, after the PHV undergoes a complete pipeline processing flow, it is sent to the corresponding first-path node by the last reconfigurable processor in the pipeline that is reconfigured into a pipeline stage. For PHVs that do not need to be sent to the RTC processor for processing, they are passed along the first path, which starts from the first node corresponding to the reconfigurable processor that was last reconfigured into the pipeline stage in the pipeline and is passed directly to the first node corresponding to the reverse parser along the first side path. For PHVs that need to be sent to the RTC processor for further processing, they are passed along the second path. The second path starts from the first path node corresponding to the last reconfigurable processor that is reconfigured into the pipeline stage, and is passed along the first side path to the first path node corresponding to the RTC processor where the RTC core to be processed is located. It is then downloaded to the RTC core to be processed. After processing is completed, the idle period of the corresponding first path node is selected, and it is uploaded to the first path node corresponding to the RTC processor where the RTC core to process the PHV is located.

8. The processor-reconfigurable programmable switching architecture according to claim 7, characterized in that, The first path and the second path share a common source and sink. The source is the first path node corresponding to the last reconfigurable processor reconfigured into the pipeline stage, and the sink is the first path node corresponding to the inverse parser. The sink has a buffer to handle congestion. When the buffer meets the condition of impending overflow, the buffer sends a target signal to the reconfigurable processor reconfigured into the RTC processor, so that no new PHV is uploaded to the second path based on the target signal.

9. The processor-reconfigurable programmable switching architecture according to claim 6, characterized in that, The second side path includes at least one second path node, and the second side path supports at least one data transmission, including: A request is sent from the reconfigurable processor that has been reconfigured into an RTC processor, the payload of the data packet processed by the reconfigurable processor that has been reconfigured into an RTC processor is read from the payload buffer, and the payload is passed back to the reconfigurable processor that has been reconfigured into an RTC processor, wherein the payload is stored in the data memory of the reconfigurable processor that has been reconfigured into an RTC processor for subsequent processing. The reconfigurable processor that has been reconfigured into an RTC processor sends a request to read data from the data memory or register array on another reconfigurable processor and then transfers the read data back to the data memory processed by the reconfigurable processor that has been reconfigured into an RTC processor. A request is sent from the reconfigurable processor that has been reconfigured into an RTC processor to write data to the data memory or register array on other reconfigurable processors; The reconfigurable processor, which has been reconfigured into an RTC processor, sends a request to send data to a hardware workload, which then sends the processing result back to the reconfigurable processor.

10. A programmable data plane chip, characterized in that, Includes the processor-reconfigurable programmable switching architecture as described in any one of claims 1-9.

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