Manufacturing method for thin film resistor and thin film resistor structure

Abstract

The present disclosure relates to a manufacturing method for a thin film resistor and a thin film resistor structure. The method comprises: forming a metal layer on a main surface of a wafer; forming a masking layer in contact with the metal layer; and forming a resistive material layer on the main surface, and patterning same, the patterned resistive material layer comprising a thin film resistor, and the thin film resistor being in ohmic contact with a metal connecting line in the metal layer by means of the masking layer.

Description

Manufacturing methods and structures of thin-film resistors Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and in particular to a method for manufacturing a thin-film resistor, and also to a thin-film resistor structure. Background Technology

[0002] CrSi (chromium silicon) thin-film resistors are widely used in high-precision reference circuits due to their low temperature drift and high accuracy. The temperature coefficient of resistance (TCR) of CrSi resistors fabricated using exemplary mature processes is approximately ±20 ppm / K. With market development, in addition to the demand for low-temperature drift and high-precision thin-film resistors, there is also a desire for thin-film resistors to be easily integrated into the processes used to manufacture semiconductor devices. Summary of the Invention

[0003] Therefore, it is necessary to provide a simple method for manufacturing thin-film resistors.

[0004] A method for manufacturing a thin-film resistor includes: forming a metal layer on a main surface of a wafer; forming a masking layer in contact with the metal layer; forming a resistive material layer on the main surface and patterning it, wherein the patterned resistive material layer includes a thin-film resistor, and the thin-film resistor forms an ohmic contact with a metal interconnect in the metal layer through the masking layer.

[0005] The above-mentioned method for manufacturing thin-film resistors first forms a metal layer that serves as the metal interconnects for the thin-film resistor, and then forms a masking layer and a thin-film resistor. Therefore, the etching of the metal layer and the masking layer can be carried out using dry etching without having to consider the damage to the thin-film resistor caused by dry etching, thus reducing the difficulty of the process.

[0006] In one embodiment, forming a masking layer in contact with the metal layer includes: depositing a masking layer material on the main surface; and performing photolithography using a masking layer photomask to etch the masking layer material to form the masking layer.

[0007] In one embodiment, forming and patterning a resistive material layer on the main surface includes: coating a photoresist layer on the resistive material layer; performing photolithography using a target photomask to pattern the photoresist layer to form a photoresist layer, wherein the masking layer and the resistive material layer serve as an anti-reflection layer for photolithography; and using the photoresist layer as an etch barrier layer to etch the resistive material layer to form the thin-film resistor.

[0008] In one embodiment, the resistive material layer is made of CrSi, which is doped with oxygen and / or nitrogen.

[0009] In one embodiment, the resistive material layer is formed by reactive sputtering, wherein the reactive gas in the reactive sputtering process includes oxygen and / or nitrogen, and argon is used as the protective gas in the reactive sputtering process.

[0010] In one embodiment, the sum of the atomic fractions of oxygen and nitrogen atoms in the resistive material layer is 1 at.% to 20 at.%.

[0011] In one embodiment, after forming and patterning the resistive material layer on the main surface, the method further includes annealing the thin-film resistor, wherein the annealing is performed in an atmosphere comprising nitrogen and hydrogen.

[0012] In one embodiment, forming and patterning a resistive material layer on the main surface includes: forming and patterning the resistive material layer on the main surface and the masking layer, wherein the patterned resistive material layer further includes an electrical connection layer located on the metal interconnect, the electrical connection layer being integrally connected to the thin film resistor and forming an ohmic contact with the metal interconnect through a masking layer located below the electrical connection layer and above the metal interconnect.

[0013] In one embodiment, forming a metal layer on the main surface of the wafer includes forming the metal layer on a dielectric layer of the wafer.

[0014] It is also necessary to provide a thin-film resistor structure.

[0015] A thin-film resistor structure includes: a metal layer including metal interconnects; a masking layer located on the metal interconnects; a thin-film resistor; and an electrical connection layer located on the metal interconnects, made of the same material as the thin-film resistor and integrally connected to the thin-film resistor; the electrical connection layer forms an ohmic contact with the metal interconnects through the masking layer beneath it.

[0016] In the aforementioned thin-film resistor structure, the etching of the metal layer and the masking layer can be carried out using dry etching, without having to consider the damage to the thin-film resistor caused by dry etching, thus reducing the difficulty of the process.

[0017] In one embodiment, the thin-film resistor is made of CrSi, which is doped with oxygen and / or nitrogen.

[0018] In one embodiment, the sum of the atomic fractions of oxygen and nitrogen atoms in the thin-film resistor is 1 at.% to 20 at.%.

[0019] In one embodiment, the metal layer is made of AlSiCu.

[0020] In one embodiment, the masking layer is made of TiW material.

[0021] It is also necessary to provide a thin-film resistor structure, which is manufactured using the manufacturing method described in any of the foregoing embodiments.

[0022] It is also necessary to provide an integrated circuit that includes the thin-film resistor structure described in any of the foregoing embodiments. Attached Figure Description

[0023] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0024] Figure 1 is a cross-sectional schematic diagram of a thin-film resistor structure in one embodiment of the present disclosure.

[0025] Figure 2 is a top view of a thin-film resistor structure according to an embodiment of the present disclosure.

[0026] Figure 3 is a flowchart of a method for manufacturing a thin-film resistor according to an embodiment of the present disclosure.

[0027] Figure 4 is a schematic cross-sectional view of the front side of the wafer after step S310 is completed in one embodiment of this disclosure.

[0028] Figure 5 is a top view of the front of the wafer after step S310 is completed in one embodiment of this disclosure.

[0029] Figure 6 is a schematic cross-sectional view of the front side of the wafer after step S320 is completed in one embodiment of this disclosure.

[0030] Figure 7 is a top view of the front of the wafer after step S320 is completed in one embodiment of this disclosure.

[0031] Figure 8 is a flowchart of the sub-step of step S330 in one embodiment of this disclosure. Detailed Implementation

[0032] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0034] It should be understood that when a component or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers. The term "connection" in this specification, if referring to the transmission of electrical signals or data between connected circuits, modules, units, etc., should be understood as "electrical connection," "communication connection," etc. It should be understood that although the terms first, second, third, etc., may be used to describe various components, parts, areas, layers, and / or portions, these components, parts, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one component, part, area, layer, or portion from another component, part, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0035] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be understood that “at least one” means one or more, and “a plurality” means two or more. “At least a portion of an element” means part or all of an element. It should also be understood that the terms “compose” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0037] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this disclosure. Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of this disclosure.

[0038] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0039] One exemplary CrSi thin-film resistor structure in related technologies involves drilling holes in a masking layer before depositing a metal layer for external integration. The manufacturing steps include: 1) depositing a thin-film resistor layer and a masking layer on a substrate dielectric layer using reactive sputtering; 2) removing excess thin-film resistor and masking layers using dry etching to form a resistor pattern; 3) removing excess masking layers using photolithography and etching processes, retaining the end masking layers; 4) depositing an isolation layer on the resistor pattern and etching connection holes at the resistor ends; 5) performing thin-film annealing; and 6) depositing a metal layer to fill the connection holes and bring out the resistors. However, this approach requires a connection hole photomask for etching connection holes at the resistor ends, increasing manufacturing costs. Furthermore, hole etching may damage the bottom masking layer, causing contact problems with the subsequent metal layer and increasing the difficulty of process implementation. Additionally, a chemical reaction exists between the etchant in the masking layer and the photoresist, making it impossible to guarantee accurate transfer of the photolithographic pattern.

[0040] Another exemplary CrSi thin-film resistor structure in related technologies integrates the metal interconnect layer directly deposited on the masking layer. This structure requires at least three photomasks (thin-film resistor etching / integrated via connection / integrated metal interconnect) for integration, and increases the metal layers of the original process, leading to increased costs.

[0041] This disclosure proposes an innovative inverted thin-film resistor structure, which improves resistance performance, saves costs, and greatly reduces integration difficulty. Figure 1 is a cross-sectional view of the thin-film resistor structure in one embodiment of this disclosure, and Figure 2 is a top view of the thin-film resistor structure in another embodiment of this disclosure. The thin-film resistor structure in Figure 1 is symmetrical, so only one side is labeled. In one embodiment of this disclosure, the thin-film resistor structure includes a metal layer 110, a masking layer 122, a thin-film resistor 134, and an electrical connection layer 132. The metal layer 110 includes metal interconnects 112. The masking layer 122 is located on the metal interconnects 112. The electrical connection layer 132 is located on the metal interconnects 112, has the same material as the thin-film resistor 134, and is integrally connected to the thin-film resistor 134. The electrical connection layer 132 forms an ohmic contact with the metal interconnects 112 through the masking layer 122 below it.

[0042] In Figures 1 and 2, the thin-film resistor 134 is located on the dielectric layer 10, which can be an interlayer dielectric (ILD) layer or an intermetallic dielectric (IMD) layer. The metal layer 110 is electrically connected to the device structure (e.g., the gate, source, and drain of a transistor, and metal interconnect structures electrically connected to the transistor) below the dielectric layer 10 through contact holes / vias penetrating the dielectric layer 10. In Figure 2, region A1 shows a structure in which the dielectric layer 10, the masking layer 122, and the electrical connection layer 132 are stacked sequentially, and region A2 shows a structure in which the dielectric layer 10, the metal interconnect 112, the masking layer 122, and the electrical connection layer 132 are stacked sequentially. That is, both the thin-film resistor 134 and the electrical connection layer 132 are part of the resistive material layer 130. After extending to region A1, the thin-film resistor 134 continues to extend to region A2 (the resistive material layer in region A2 is defined as the electrical connection layer 132). In region A2, it forms an ohmic contact with the metal interconnect 112 through the masking layer 122, thereby allowing the thin-film resistor 134 to be led out by the metal interconnect 112. When calculating the resistance value of the thin-film resistor 134 as a resistor, the resistive material layer 130 in regions A1 and A2 can be ignored, that is, it is not considered as part of the thin-film resistor 134.

[0043] The aforementioned thin-film resistor structure has a structure in which metal interconnect 112, masking layer 122 and electrical connection layer 132 are stacked in sequence. Therefore, the etching of metal layer 110 and masking layer 122 can be carried out by dry etching without considering the damage to thin-film resistor 134 caused by dry etching, thus reducing the process difficulty.

[0044] In one embodiment of this disclosure, the resistive material layer 130 is CrSi doped with oxygen and / or nitrogen. Specifically, N or O is doped into CrSi to obtain CrSiMx (M being N, O, or NO) as the resistive material layer 130. Further, the sum of the atomic fractions of oxygen and nitrogen atoms in this CrSiMx is 1 at.% to 20 at.%.

[0045] In one embodiment of this disclosure, the metal layer 110 is made of AlSiCu.

[0046] In one embodiment of this disclosure, the masking layer 122 is made of TiW (titanium tungsten).

[0047] This disclosure correspondingly proposes an integrated circuit that integrates the thin-film resistor structure described in any of the foregoing embodiments.

[0048] This disclosure provides a method for manufacturing a thin-film resistor, which can be used to manufacture the thin-film resistor structure described in any of the above embodiments. Figure 3 is a flowchart of a method for manufacturing a thin-film resistor according to an embodiment of this disclosure, including the following steps S310 to S330.

[0049] In step S310, a metal layer is formed on the front side of the wafer.

[0050] In one embodiment of this disclosure, metal is deposited on the dielectric layer 10 of the main surface (i.e., the front side) of the wafer, and then photolithography is performed using a metal layer photomask, followed by etching to obtain the metal layer 110. Figure 4 is a schematic cross-sectional view of the front side of the wafer after step S310 in one embodiment of this disclosure, and Figure 5 is a top view of the front side of the wafer after step S310 in one embodiment of this disclosure. In one embodiment of this disclosure, the material of the metal layer 110 is AlSiCu. The etching in step S310 requires removing the deposited metal (AlSiCu) at the location where the thin film resistor 134 is subsequently formed, that is, ensuring that no AlSiCu remains on the dielectric layer 10 in the area where the thin film resistor 134 is set.

[0051] In one embodiment of this disclosure, the etching of the metal layer 110 employs dry etching, which, compared to wet etching, yields a smaller metal layer stripe width and spacing. Since this embodiment first etches the metal layer 110 and then deposits the resistive material layer, there is no need to consider damage to the resistive material layer caused by dry etching of the metal layer 110. This allows for unrestricted compatibility with other processes that share the same metal layer, saving photomasks, simplifying the integration process, reducing integration difficulty, and without increasing the number of metal layers in the original process. Compared to the approach of first depositing the resistive material layer and then forming the metal layer, which necessitates wet etching of the metal layer, this embodiment reduces process complexity. In one embodiment of this disclosure, the metal layer 110 is made of AlSiCu.

[0052] In step S320, a masking layer in contact with the metal layer is formed.

[0053] In one embodiment of this disclosure, a masking layer material is deposited on the front side of the wafer, then photolithography is performed using a masking layer photomask, and then etching is performed to obtain the masking layer 122. Figure 6 is a schematic cross-sectional view of the front side of the wafer after step S320 in one embodiment of this disclosure, and Figure 7 is a top view of the front side of the wafer after step S320 in one embodiment of this disclosure.

[0054] In one embodiment of this disclosure, the masking layer 122 is etched using dry etching. Since this embodiment first etches the masking layer 122 and then deposits the resistive material layer, there is no need to consider the damage to the resistive material layer caused by dry etching of the masking layer 122. Compared to a scheme where the resistive material layer is deposited first and then the masking layer is formed, thus requiring wet etching of the masking layer, the dielectric layer 10 lies beneath the metal layer 110 in this embodiment, eliminating the need to consider damage to the underlying layer caused by dry etching and reducing the complexity of the process.

[0055] In step S330, a resistive material layer is formed on the front side of the wafer and patterned thereon.

[0056] A resistive material layer 130 is deposited and patterned on the front side of the wafer. The patterned resistive material layer 130 includes a thin-film resistor 134, and the thin-film resistor 134 forms an ohmic contact with the metal interconnect 112 in the metal layer 110 through the masking layer 122, thereby allowing the thin-film resistor 134 to be led out by the metal interconnect 112. The thin-film resistor structure obtained after step S330 can be referred to Figures 1 and 2. In one embodiment of this disclosure, the resistive material layer 130 is a Cr-containing thin film, and its thickness and resistance value can be adjusted during the process design stage.

[0057] The above-described method for manufacturing thin-film resistors first forms a metal layer 110 that serves as the metal interconnects of the thin-film resistor 134, and then forms a masking layer 122 and the thin-film resistor 134. Therefore, the etching of the metal layer 110 and the masking layer 122 can be carried out by dry etching without having to consider the damage to the thin-film resistor 134 caused by dry etching, thus reducing the difficulty of the process.

[0058] In one embodiment of this disclosure, the resistive material layer 130 is CrSi doped with oxygen and / or nitrogen. That is, N or O elements are doped into CrSi to obtain CrSiMx (M is N, O or NO) as the resistive material layer 130.

[0059] In one embodiment of this disclosure, step S330 involves forming a resistive material layer 130 on the front side of the wafer using a reactive sputtering process. The reactive gases include oxygen (O2) and / or nitrogen (N2), and argon (Ar) is used as the protective gas. Further, the sum of the atomic fractions of oxygen and nitrogen atoms in the CrSiMx is 1 at.% to 20 at.%.

[0060] Referring to Figure 8, in one embodiment of this disclosure, step S330, patterning the resistive material layer, includes the following steps S332 to S336.

[0061] In step S332, photoresist is coated onto the resistive material layer.

[0062] Photoresist is coated on the resistive material layer 130 formed by reactive sputtering.

[0063] In step S334, photolithography is performed using the target photomask to pattern the photoresist and form a photoresist layer.

[0064] The metal layer 110 obtained after step S330 is used as a metal interconnect. Therefore, the target photomask can be designed and formed based on the layout pattern of the metal interconnect layer. Thus, in this embodiment, adding a thin-film resistor 134 to the integrated circuit requires only two additional photomasks compared to an integrated circuit without the thin-film resistor 134. That is, the metal layer of an integrated circuit without the thin-film resistor 134 originally requires one photomask. This embodiment requires the metal layer photomask of step S310 and the masking layer photomask of step S320. The target photomask of step S330 is the same photomask as the original metal layer, and although the metal layer photomask is added, the number of metal layers in the process does not increase. In one embodiment of this disclosure, the masking layer 122 and the resistive material layer 130 serve as the anti-reflection layer for photolithography in step S334, eliminating the need to form an additional photolithographic anti-reflection layer, thereby reducing process costs.

[0065] In step S336, the photoresist layer is used as an etching barrier layer to etch the resistive material layer to form a thin film resistor.

[0066] In one embodiment of this disclosure, after etching to form the thin film resistor 134, the photoresist layer formed in step S334 can be used as an etching barrier layer to continue etching the masking layer 122 and the metal layer 110 downwards.

[0067] The function of the masking layer 122 is to enable the remaining resistive material layer 130 after patterning in step S330 to form an ohmic contact with the metal interconnect 112. In one embodiment of this disclosure, in the thin-film resistor structure obtained after step S330, the masking layer 122 is located between the metal interconnect 112 and the resistive material layer 130, and is in direct contact with both the metal interconnect 112 and the resistive material layer 130. In one embodiment of this disclosure, the masking layer 122 is made of TiW.

[0068] In one embodiment of this disclosure, the resistive material layer 130 obtained after patterning in step S330 further includes an electrical connection layer 132 located on the metal interconnect 112. The electrical connection layer 132 is integrally connected to the thin film resistor 134 and forms an ohmic contact with the metal interconnect 112 through a masking layer 122 located below the electrical connection layer 132 and above the metal interconnect 112.

[0069] In one embodiment of this disclosure, after step S330, an annealing step is further included for the thin-film resistor 134, wherein the annealing is performed in an atmosphere including nitrogen and hydrogen. Specifically, the wafer after step S330 can be placed in an atmospheric pressure furnace, nitrogen and hydrogen are introduced, and it is heated to a suitable temperature for annealing.

[0070] This disclosure, through the doping of N and / or O elements into a CrSi thin film and controlling the amount of non-metallic element doping, achieves a thin film resistor with a significantly reduced temperature drift coefficient and increased stability. The thin film resistor 134 obtained in this disclosure can achieve a stable temperature drift range of approximately ±10 ppm / K and a sheet resistance range of 100 ohms / sq to 2000 ohms / sq.

[0071] It should be understood that although the steps in the flowchart of this disclosure are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless expressly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this disclosure may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0072] In the description of this specification, references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0073] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for manufacturing a thin-film resistor, comprising: A metal layer is formed on the main surface of the wafer; A masking layer is formed in contact with the metal layer; A resistive material layer is formed on the main surface and patterned thereon. The patterned resistive material layer includes a thin film resistor, and the thin film resistor forms an ohmic contact with the metal interconnect in the metal layer through the masking layer.

2. The method for manufacturing a thin-film resistor according to claim 1, characterized in that, The masking layer formed in contact with the metal layer includes: Depositing a masking layer material on the main surface; and Photolithography is performed using a masking layer photomask to etch the masking layer material to form the masking layer.

3. The method for manufacturing a thin-film resistor according to claim 1, characterized in that, The process of forming a resistive material layer on the main surface and patterning it includes: Photoresist is coated onto the resistive material layer; Photolithography is performed using a target photomask to pattern the photoresist to form a photoresist layer. The masking layer and the resistive material layer serve as anti-reflection layers for photolithography. The photoresist layer is used as an etching barrier layer to etch the resistive material layer to form the thin film resistor.

4. The method for manufacturing a thin-film resistor according to claim 1, characterized in that, The resistive material layer is made of CrSi doped with oxygen and / or nitrogen.

5. The method for manufacturing a thin-film resistor according to claim 4, characterized in that, The resistive material layer is formed by reactive sputtering, wherein the reactive gas in the reactive sputtering process includes oxygen and / or nitrogen, and argon is used as the protective gas in the reactive sputtering process.

6. The method for manufacturing a thin-film resistor according to claim 4 or 5, characterized in that, The sum of the atomic fractions of oxygen and nitrogen atoms in the resistive material layer is 1 at.% to 20 at.%.

7. The method for manufacturing a thin-film resistor according to claim 1, characterized in that, After forming and patterning the resistive material layer on the main surface, the method further includes: The thin-film resistor is annealed, wherein the annealing is performed in an atmosphere including nitrogen and hydrogen.

8. The method for manufacturing a thin-film resistor according to claim 1, characterized in that, The process of forming a resistive material layer on the main surface and patterning it includes: The resistive material layer is formed and patterned on the main surface and the masking layer. The patterned resistive material layer also includes an electrical connection layer located on the metal interconnect. The electrical connection layer is integrated with the thin film resistor and forms an ohmic contact with the metal interconnect through the masking layer located below the electrical connection layer and above the metal interconnect.

9. The method for manufacturing a thin-film resistor according to claim 1, characterized in that, The process of forming a metal layer on the main surface of the wafer includes: The metal layer is formed on the dielectric layer of the wafer.

10. A thin-film resistor structure, comprising: Metal layer, including metal interconnects; A masking layer is located on the metal interconnect. Thin film resistor; An electrical connection layer, located on the metal interconnect, is made of the same material as the thin-film resistor and is integrally connected with the thin-film resistor; the electrical connection layer forms an ohmic contact with the metal interconnect through the masking layer below it.

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