Memory management method and memory controller

Abstract

The present invention provides a memory management method and a memory controller. The memory management method comprises: storing a valid data table to a first cache area in a buffer memory of a memory controller, to identify, by means of the valid data table, a plurality of first physical addresses corresponding to a plurality of pieces of valid data; on the basis of the plurality of first physical addresses, identifying a chip enable pin to which each piece of valid data belongs; on the basis of the valid data table and the chip enable pin to which each piece of valid data belongs, establishing at least one write mapping table in a second cache area in the buffer memory, wherein the at least one write mapping table is used for recording a plurality of pieces of address mapping information of the plurality of pieces of valid data; and on the basis of the plurality of pieces of address mapping information of the at least one write mapping table, writing the plurality of pieces of valid data into a rewritable non-volatile memory module.

Description

Memory management methods and memory controllers Technical Field

[0001] This invention relates to a memory management technology, and more particularly to a memory controller for a storage device equipped with non-volatile memory and the memory management method used therein. Background Technology

[0002] Non-volatile memory refers to computer memory that retains its data even when the current is cut off. It has advantages such as non-volatile data, low power consumption, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] However, due to the technological limitations of NAND flash memory, data corresponding to the same logical address cannot overwrite the same physical address. Instead, new data for the same logical address must be stored at a different physical address. As a result, the old data becomes invalid, occupying storage space. To reclaim this data, the memory controller performs garbage collection, but current garbage collection efficiency is low and needs improvement. Summary of the Invention

[0004] The purpose of this invention is to solve the above-mentioned problems by storing the valid data table and the write mapping table in different buffer areas for parallel processing. Furthermore, multiple write mapping tables corresponding to multiple chip enable pins (CE) can be generated to perform parallel transfer operations on valid data on different CEs.

[0005] One or more embodiments of the present invention provide a memory management method for a memory controller applicable to a memory device configured with a rewritable non-volatile memory module, comprising: storing a generated valid data table in a first cache area within a buffer memory to identify multiple first entity addresses corresponding to multiple valid data via the valid data table; identifying the storage area to which each valid data belongs based on the multiple first entity addresses; establishing at least one write mapping table in a second cache area within the buffer memory based on the valid data table, the at least one write mapping table being used to record multiple address mapping information of the multiple valid data; if the sorting of the multiple valid data in the valid data table is disordered, reorganizing the valid data in the valid data table to obtain the multiple address mapping information obtained by reorganizing the multiple valid data, and writing the multiple address mapping information to the write mapping table; and writing the multiple valid data to the rewritable non-volatile memory module based on the multiple address mapping information of the at least one write mapping table.

[0006] In one or more embodiments of the present invention, if a write mapping table is established and corresponds to multiple different storage areas, the multiple address mapping information of the write mapping table is arranged sequentially according to the corresponding storage areas; and if a write mapping table is established and corresponds to one storage area, the multiple address mapping information of the write mapping table corresponds to the same storage area.

[0007] In one or more embodiments of the present invention, the memory management method wherein the step of establishing at least one write mapping table in a second cache area within the buffer memory according to the valid data table includes: identifying the logical address of each valid data according to the valid data table; sorting multiple logical addresses corresponding to the multiple valid data according to the storage area to which each valid data belongs, to obtain multiple sorted logical addresses, wherein the multiple logical addresses corresponding to the same storage area are arranged together; setting multiple second entity addresses respectively mapped to the multiple sorted logical addresses, to obtain the multiple address mapping information, thereby establishing the write mapping table in the second cache area, wherein the write mapping table records the multiple address mapping information, each address mapping information including a sorted logical address and a mapped second entity address, the order of the multiple address mapping information being the same as the order of the multiple sorted logical addresses, wherein the established write mapping table corresponds to different multiple storage areas.

[0008] In one or more embodiments of the present invention, the step of writing the plurality of valid data to the rewritable non-volatile memory module according to the plurality of address mapping information written to the at least one mapping table includes: before writing the plurality of valid data to the rewritable non-volatile memory module, selecting target address mapping information among the plurality of address mapping information based on the arrangement order of the plurality of address mapping information; searching for a target first entity address mapped to the target logical address among the plurality of first entity addresses according to the target logical address of the target address mapping information; reading target valid data from the rewritable non-volatile memory module according to the target first entity address; and writing the read target valid data to the rewritable non-volatile memory module according to the target second entity address of the target address mapping information.

[0009] In one or more embodiments of the present invention, the step of establishing at least one write mapping table in a second cache area within the buffer memory according to the valid data table includes: identifying the logical address of each valid data according to the valid data table; obtaining a plurality of selected storage areas from the plurality of storage areas corresponding to the plurality of valid data; establishing a plurality of write mapping tables in the second cache area according to the plurality of selected storage areas, wherein the plurality of write mapping tables respectively correspond to the plurality of selected storage areas; recording a plurality of target logical addresses corresponding to the plurality of selected storage areas from the plurality of logical addresses of the plurality of valid data into the corresponding plurality of write mapping tables, wherein the selected storage area corresponding to at least one target logical address in each write mapping table is the same as the selected storage area corresponding to the write mapping table to which it belongs; setting a plurality of second entity addresses respectively mapped to the plurality of target logical addresses to obtain the plurality of address mapping information, thereby establishing the plurality of write mapping tables in the second cache area, wherein each address mapping information includes a target logical address and a mapped second entity address, wherein one established write mapping table corresponds to one storage area.

[0010] In one or more embodiments of the present invention, the method further includes: establishing, within the first buffer, a valid data table corresponding to a plurality of storage areas in the rewritable non-volatile memory module; selecting a target storage area from the plurality of storage areas in the rewritable non-volatile memory module to perform a valid data table update operation corresponding to the target storage area; obtaining a plurality of candidate entity addresses corresponding to the target storage area; determining, from the plurality of candidate entity addresses, at least one valid entity address mapped to at least one valid logical address, wherein the at least one valid entity address stores valid data, and invalid entity addresses not mapped to any valid logical address store invalid data; and recording the at least one valid logical address corresponding to the target storage area and the at least one valid entity address to the valid data table in the first buffer, completing the valid data table update operation corresponding to the target storage area, and determining whether there is at least one unselected storage area, wherein if there is at least one unselected storage area, selecting one of the at least one unselected storage area as a new target storage area to perform the valid data table update operation corresponding to the new target storage area, wherein if there is no unselected storage area, completing the generation of the valid data table.

[0011] In one or more embodiments of the present invention, the method further includes: establishing, within the first buffer, multiple valid data tables respectively corresponding to multiple storage areas in the rewritable non-volatile memory module; determining, from multiple candidate entity addresses corresponding to each storage area, at least one valid entity address mapped to at least one valid logical address, wherein the at least one valid entity address stores valid data, and invalid entity addresses not mapped to any valid logical address store invalid data; and recording the at least one valid logical address and the at least one valid entity address to the valid data table corresponding to the same storage area.

[0012] One or more embodiments of the present invention also provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module, the memory controller comprising: a memory interface control circuit for electrically connecting to the rewritable non-volatile memory module; a buffer memory; and a processor electrically connected to the memory interface control circuit and the buffer memory, wherein the processor is further electrically connected to a connection interface circuit of the storage device for electrically connecting to a host system. The processor is configured to: store the generated valid data table in a first cache area within a buffer memory to identify multiple first entity addresses corresponding to multiple valid data via the valid data table; identify the chip enable pin to which each valid data belongs based on the multiple first entity addresses; establish at least one write mapping table in a second cache area within the buffer memory based on the valid data table, the at least one write mapping table being used to record multiple address mapping information of the multiple valid data; if the sorting of the multiple valid data in the valid data table is disordered, reorganize the valid data in the valid data table to obtain the multiple address mapping information obtained after reorganizing the multiple valid data, and write the multiple address mapping information to the write mapping table; and write the multiple valid data to the rewritable non-volatile memory module based on the multiple address mapping information of the at least one write mapping table.

[0013] Based on the above, the memory management method and memory controller provided in the embodiments of the present invention can establish valid data tables and write mapping tables in different buffers of the buffer memory, and the address mapping information in the established valid data tables / write mapping tables can be arranged / grouped according to the order of the chip enable pins (memory areas) to make the transfer operation of valid data more efficient, avoid the occurrence of write delay, improve the efficiency of garbage collection operation, and thus improve the space utilization and overall working efficiency of the storage device. Attached Figure Description

[0014] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0015] Figure 1 is a block diagram of a host system and storage device according to an embodiment of the present invention;

[0016] Figure 2 is a flowchart of a memory management method according to an embodiment of the present invention;

[0017] Figure 3 is a schematic diagram of the first buffer and the second buffer of the buffer memory, which respectively store the valid data table and write the mapping table to the buffer memory according to an embodiment of the present invention;

[0018] Figure 4 is a schematic diagram of establishing a write mapping table based on the valid data table and the chip enable pin corresponding to the valid data according to an embodiment of the present invention;

[0019] Figure 5 is a schematic diagram of establishing a write mapping table based on multiple valid data tables and chip enable pins corresponding to valid data according to an embodiment of the present invention.

[0020] Figure 6 is a schematic diagram of establishing multiple write mapping tables based on the valid data table and the chip enable pin corresponding to the valid data, according to an embodiment of the present invention.

[0021] Figure 7 is a schematic diagram of establishing multiple write mapping tables based on the valid data table and the chip enable pin corresponding to the valid data according to an embodiment of the present invention;

[0022] Figure 8 is a schematic diagram illustrating the establishment of a valid data table based on the chip enable pin according to an embodiment of the present invention;

[0023] Figure 9 is a schematic diagram illustrating the creation of multiple valid data tables based on the chip enable pin according to an embodiment of the present invention.

[0024] Figure 10: Host system; 20: Storage device; 211: First processor; 110: Second processor; 120: Host memory; 130: Data transmission interface circuit; 210: Memory controller; 212: Data management circuit; 213: Memory interface control circuit; 214: Buffer memory; 2141: First buffer; 2142: Second buffer; 220: Rewritable non-volatile memory module; 230: Connection interface circuit; S210, S220, S230, S240: Flow steps of memory management method; VT1, VT2, VT3(0)~VT3(3): Valid data tables; WB, WB1, WB2(0), WB2(1), WB3(0)~WB3(3): Write to mapping tables CE0~CE3: Chip enable pins LBA1~LBA6, LBA01, LBA02, LBA12, LBA13, LBA20, LBA31: Logical addresses PBA1~PBA6, PBA01~PBA03, PBA10~PBA13, PBA20~PBA23, PBA30~PBA33: Physical addresses PBA1'~PBA6': Target physical address / second physical address T31, T51, T71, T72, T81, T91, T92, T93, T94: Tables A31, A32, A41~A45, A61~A64, A71~A76, A81~A86, A91~A96: Arrows Detailed Implementation

[0025] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0026] Figure 1 is a block diagram illustrating a host system and storage device according to an embodiment of the present invention. Referring to Figure 1, the host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on the motherboard of the host system 10.

[0027] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also referred to as a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0028] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0029] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0030] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0031] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0032] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it must be understood that the present invention is not limited thereto, and the host memory 120 may also be other suitable memories.

[0033] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to the instructions of the host system 10.

[0034] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program codes, and these control instructions / program codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data. Furthermore, in this embodiment, the control instructions / program codes can also be executed to perform data reading operations to implement the data reading method provided by this invention. The control instructions / program codes corresponding to the data reading method can also be implemented as hardware circuit units to implement the data reading method provided by this invention.

[0035] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and the present invention is not limited thereto.

[0036] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0037] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to perform data transfer. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., performing a write operation according to a write instruction from the host system 10). Another example is reading data from one or more physical units of the rewritable non-volatile memory module 220 (data can be read from one or more memory cells in one or more physical units) via the memory interface control circuit 213 and writing the read data to the host system 10 (e.g., host memory 120) via the connection interface circuit 230 (e.g., performing a read operation according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

[0038] The memory interface control circuit 213 is used to receive instructions from the processor 211 and, in conjunction with the data management circuit 212, to perform write (also known as programming) operations, read operations, or erase operations on the rewritable non-volatile memory module 220.

[0039] Furthermore, data to be written to the rewritable non-volatile memory module 220 is converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 needs to access the rewritable non-volatile memory module 220, the processor 211 will send a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0040] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages) configured for the rewritable non-volatile memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also called the logical-to-physical mapping table) to look up the physical unit mapped to a logical unit (e.g., look up the physical page mapped to a logical page; look up the physical address mapped to a logical address), and the memory controller 210 can use the physical-to-logical address mapping table (also called the physical-to-logical mapping table) to look up the logical unit mapped to a physical unit (e.g., look up the logical page mapped to a physical page; look up the logical address mapped to a physical address).

[0041] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data (e.g., various mapping tables, index tables, valid data tables) used to manage the storage device 20, allowing the processor 211 to quickly access the data, instructions, or system data from the buffer memory 214. In one embodiment, the memory controller 210 may establish one or more write mapping tables within the buffer memory 214 to indicate the target entity address for writing valid data. It should be noted that in other embodiments, the buffer memory 214 may also be configured outside the memory controller 210. Alternatively, the buffer memory 214 may be configured both inside and outside the memory controller 210.

[0042] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213) and is used to store user data sent by the host system 10.

[0043] In this embodiment, each memory die (chip) in the rewritable non-volatile memory module 220 has multiple planes, and each plane has multiple physical blocks. Each physical block includes multiple physical programming units (also called physical pages). Each physical page has multiple storage units (also called physical bytes), and each storage unit corresponds to a physical address. The physical address is used to record the physical location of the data stored in the storage unit. It should be noted that the present invention is not limited to the size of each physical page and logical page.

[0044] The chip enable (CE) signal plays a crucial role in controlling access to and operation of memory chips. It acts as a gating system, regulating when and how data is read from or written to the chip. A rewritable non-volatile memory module 220 typically includes multiple CE pins that transmit the chip enable (CE) signal, each capable of independently controlling a separate physical chip within the chip. This enables parallel processing of read and write operations, thereby increasing data transfer speeds. For example, using multiple CE pins allows data to be read from or written to multiple chips or blocks simultaneously, significantly improving data throughput. However, simultaneous read and write operations on the same CE pin can lead to data conflicts. In this embodiment, since there are multiple physical blocks / units corresponding to each CE pin, physical blocks / units corresponding to the same CE pin can also be referred to as a memory area.

[0045] Figure 2 is a flowchart of a memory management method according to an embodiment of the present invention.

[0046] Referring to Figure 2, in step S210, the memory controller 210 stores the generated valid data table in a first cache area within the buffer memory 214 to identify multiple first entity addresses corresponding to multiple valid data through the valid data table. Next, in step S220, the memory controller 210 identifies the storage area to which each valid data belongs based on the multiple first entity addresses. Next, in step S230, the memory controller 210 establishes at least one write mapping table in a second cache area within the buffer memory based on the valid data table. The write mapping table is used to record multiple address mapping information of the multiple valid data. Then, in step S240, if the multiple valid data in the valid data table is sorted haphazardly, the memory controller 210 reorganizes the valid data in the valid data table and writes it to the write mapping table to obtain the multiple address mapping information obtained after reorganizing the multiple valid data, and writes the multiple address mapping information to the write mapping table.

[0047] In one embodiment, if a write mapping table is established and corresponds to multiple different chip enable pins (e.g., examples in Figures 4 and 5), the multiple address mapping information is arranged sequentially according to the corresponding chip enable pins (memory areas). If a write mapping table is established and corresponds to a chip enable pin (e.g., examples in Figures 6 and 7), the multiple address mapping information of the write mapping table corresponds to the same chip enable pin (memory area).

[0048] Figure 3 is a schematic diagram of the first buffer and the second buffer of the buffer memory, which respectively store the valid data table and write the mapping table to the buffer memory according to an embodiment of the present invention.

[0049] Referring to Figure 3, to overcome the serial nature of the traditional method where the valid data table and write mapping table are cached in the same cache area, in one embodiment, as shown by arrows A31 and A32, the memory controller 210 stores the generated valid data table VT1 (which can be one or more) and one or more write mapping tables WB in the first buffer 2141 and the second buffer 2142 of the buffer memory 214, respectively. In this way, while generating the valid data table VT1, the address mapping information of the valid data can be looked up according to the contents of the stored valid data table VT1 to generate the write mapping table WB and store it in the second buffer 2142. This allows for the movement of valid data during garbage collection operations through the write mapping table WB. This parallel processing mechanism enhances the efficiency of garbage collection operations.

[0050] In one embodiment, the step of establishing at least one write mapping table in the second buffer area of ​​the buffer memory according to the valid data table and the chip enable pin to which each valid data belongs includes: identifying the logical address of each valid data according to the valid data table; sorting multiple logical addresses corresponding to the multiple valid data according to the chip enable pin to which each valid data belongs to obtain multiple sorted logical addresses, wherein the multiple logical addresses corresponding to the same chip enable pin will be arranged together; setting multiple second entity addresses respectively mapped to the multiple sorted logical addresses to obtain the multiple address mapping information, thereby establishing the at least one write mapping table in the second buffer area, wherein the at least one write mapping table records the multiple address mapping information, each address mapping information includes a sorted logical address and a mapped second entity address, the order of the multiple address mapping information is the same as the order of the multiple sorted logical addresses, wherein the established write mapping table corresponds to different multiple chip enable pins.

[0051] Figure 4 is a schematic diagram of establishing a write mapping table based on the valid data table and the chip enable pin corresponding to the valid data, according to an embodiment of the present invention.

[0052] For example, referring to Figure 4, assume that a valid data table VT1 has been obtained, which records six address mappings corresponding to six valid data items. It records the six logical addresses LBA1 to LBA6 of the six valid data items and the six mapped physical addresses (also called first physical addresses or source physical addresses) PBA1 to PBA6. The valid data is stored at physical addresses PBA1 to PBA6 in the rewritable non-volatile memory module 220. After the memory controller 210 identifies the logical addresses LBA1 to LBA6 and the six mapped physical addresses PBA1 to PBA6, the memory controller 210 can determine the chip enable pin (as shown by arrow A41) corresponding to each physical address according to the address content of physical addresses PBA1 to PBA6 and a predetermined addressing rule.

[0053] In this example, it is assumed that the memory controller 210 determines, based on the address contents of physical addresses PBA1 to PBA6, that physical address PBA1 belongs to chip enable pin CE3; physical address PBA2 belongs to chip enable pin CE1; physical address PBA3 belongs to chip enable pin CE0; physical address PBA4 belongs to chip enable pin CE1; physical address PBA5 belongs to chip enable pin CE0; and physical address PBA6 belongs to chip enable pin CE2.

[0054] In one embodiment, the memory controller 210 groups the address mapping information according to the corresponding chip enable pins. For example, logical addresses LBA3 and LBA5 belong to the same group, specifically chip enable pin CE0; logical addresses LBA2 and LBA4 belong to the same group, specifically chip enable pin CE1; logical address LBA6 belongs to the group for chip enable pin CE2; and logical address LBA1 belongs to the group for chip enable pin CE3. Grouping by chip enable pin allows for more efficient execution of read / write operations on the corresponding chip enable pins.

[0055] In one embodiment, as indicated by arrow A42, the memory controller 210 can further adjust the order of logical addresses LBA1 to LBA6 according to the chip enable pin numbering order (e.g., the first order from smallest to largest) to obtain multiple sorted logical addresses LBA3, LBA5, LBA2, LBA4, LBA6, and LBA1, and record these multiple sorted logical addresses LBA3, LBA5, LBA2, LBA4, LBA6, and LBA1 in the logical address field of the mapping address information in the write mapping table WB1. Next, the memory controller 210 sets the mapped entity address (also called the second entity address or target entity address) for each sorted logical address written to the mapping table WB1. Valid data corresponding to these sorted logical addresses can be stored in the rewritable non-volatile memory module 220 according to these second entity addresses.

[0056] It should be noted that, in another embodiment, the memory controller 210 may also reorder the logical addresses LBA1 to LBA6 according to the numbering order of the chip enable pins, such as a second order from largest to smallest. In another embodiment, the memory controller 210 may also reorder multiple logical addresses and record multiple sorted logical addresses into the write mapping table simply based on the rule that multiple logical addresses corresponding to the same chip enable pin group will be continuously recorded in the write mapping table (without needing to follow the first or second order).

[0057] It's worth noting that the traditional approach causes CE conflicts because, in the CE interleaving example in Figure 4, when valid data at logical address LBA2 corresponding to CE1 is being written to CE1, valid data at logical address LBA3 corresponding to CE0 is being read. Since the valid data at logical address LBA3 corresponds to a different CE0 than CE1, no CE conflict occurs. However, assuming that valid data at logical address LBA2 corresponding to CE1 is still being written to CE1, valid data at logical address LBA4 corresponding to CE1 is being read, and since the valid data at logical address LBA4 corresponds to CE1 and is currently being written, a CE conflict will occur.

[0058] However, using the method shown in Figure 4, after reordering, valid data for the corresponding CE0 can be written all at once. Furthermore, during this writing process, valid data for the next CE (CE1) can still be read without conflicting with the ongoing write operation on CE0. In this way, while writing a batch of valid data for CE0, a batch of valid data for CE1 can be read without worrying about CE conflicts (because reading and writing are performed on different CEs, avoiding CE conflicts). In other words, the provided solution allows reading and writing to be performed in parallel across different CEs, achieving beneficial technical effects.

[0059] In the above embodiment, the number of mapping tables written is 1, but the present invention is not limited thereto.

[0060] In this embodiment, to more efficiently perform parallel read or write operations on multiple CEs, the memory controller 210 may select some CEs to establish multiple write mapping tables corresponding to each of the selected CEs.

[0061] Specifically, in one embodiment, the step of establishing at least one write mapping table in the second buffer area of ​​the buffer memory according to the valid data table and the chip enable pin to which each valid data belongs includes: identifying the logical address of each valid data according to the valid data table; obtaining multiple selected chip enable pins from the multiple chip enable pins corresponding to the multiple valid data (and then selecting multiple chip enable pins as multiple selected chip enable pins); establishing multiple write mapping tables in the second buffer area according to the multiple selected chip enable pins, wherein the multiple write mapping tables respectively correspond to the multiple selected chip enable pins; recording multiple target logical addresses corresponding to the multiple selected chip enable pins from the multiple logical addresses of the multiple valid data into the corresponding multiple write mapping tables, wherein the selected chip enable pin corresponding to at least one target logical address in each write mapping table is the same as the selected chip enable pin corresponding to the write mapping table to which it belongs; setting multiple second entity addresses respectively mapped to the multiple target logical addresses to obtain the multiple address mapping information, thereby establishing the multiple write mapping tables in the second buffer area, wherein each address mapping information includes a target logical address and a mapped second entity address.

[0062] Figure 5 is a schematic diagram illustrating the creation of a write mapping table based on multiple valid data tables and corresponding chip enable pins according to an embodiment of the present invention. Referring to Figure 5, in one embodiment, multiple valid data tables are generated. The memory controller 210 can select a chip enable pin (e.g., starting from CE0) according to the order of the chip enable pins, as shown by arrow A43, traverse all valid data tables (e.g., VT1, VT2, ...), find the logical address corresponding to the selected chip enable pin (e.g., LBA13, LBA15, LBA21, LBA24 corresponding to CE0), and record it in the write mapping table WB1; as shown by arrow A44, select the next chip enable pin CE1, traverse all valid data tables (e.g., VT1, VT2, ...), and record it in the write mapping table WB1; 1. Find the logical address corresponding to the selected chip enable pin (e.g., LBA12, LBA14, LBA22, LBA23 for CE1) and record it in the write mapping table WB1; as shown by arrow A45, select the next chip enable pin CE2, traverse all valid data tables (e.g., VT1, VT2, ...), find the logical address corresponding to the selected chip enable pin (e.g., LBA16, LBA25, LBA26 for CE2), and record it in the write mapping table WB1.

[0063] In other words, through the above-described write mapping table creation operation, even with multiple valid data tables, the address mapping information recorded in the created write mapping table will be grouped and sorted according to the order of the chip enable pins. For example, multiple address mapping information in the first group will correspond to the chip enable pin CE0, multiple address mapping information in the following second group will correspond to the chip enable pin CE1, and so on, until all valid data of the chip enable pins are recorded in the write mapping table.

[0064] Figure 6 is a schematic diagram illustrating the establishment of multiple write mapping tables based on a valid data table and the chip enable pin corresponding to the valid data, according to an embodiment of the present invention. For example, referring to Figure 6, continuing the above example, assume that a valid data table VT1 has been obtained, which records six address mapping information corresponding to six valid data, respectively recording the six logical addresses LBA1 to LBA6 of the six valid data and the six mapped physical addresses PBA1 to PBA6, wherein the valid data is stored in the physical addresses PBA1 to PBA6 of the rewritable non-volatile memory module 220.

[0065] After identifying the multiple CEs to which physical addresses PBA1 to PBA6 belong, the memory controller 210 can select a portion of the CEs to establish a write mapping table. For example, it can first select two chip enable pins CE0 and CE1 (selected chip enable pins CE0 and CE1), and establish a write mapping table WB2(0) for the corresponding chip enable pin CE0 and a write mapping table WB2(1) for the corresponding chip enable pin CE1. Then, as shown by arrows A61 and A62, the memory controller 210 records the logical addresses LBA3 and LBA5 of the corresponding chip enable pin CE0 into the write mapping table WB2(0); as shown by arrows A63 and A64, the memory controller 210 records the logical addresses LBA2 and LBA4 of the corresponding chip enable pin CE1 into the write mapping table WB2(1).

[0066] Next, for the write mapping table WB2(0), the memory controller 210 sets the second physical addresses PBA3' and PBA5' mapped to logical addresses LBA3 and LBA5, wherein the address content of the second physical addresses PBA3' and PBA5' is different from the address content of the first physical addresses PBA3 and PBA5. In the write mapping table WB2(1), the memory controller 210 sets the second physical addresses PBA2' and PBA4' mapped to logical addresses LBA2 and LBA4, wherein the address content of the second physical addresses PBA2' and PBA4' is different from the address content of the first physical addresses PBA2 and PBA4.

[0067] After establishing the write mapping tables WB2(0) and WB2(1) for the selected chip enable pins CE0 and CE1, the memory controller 210 can establish corresponding write mapping tables based on the remaining unselected chip enable pins (e.g., chip enable pins CE2 and CE3). In one embodiment, after storing the corresponding valid data to a new physical address according to the write mapping tables WB2(0) and WB2(1), the memory controller 210 deletes the write mapping tables WB2(0) and WB2(1) and then establishes the write mapping tables for the remaining unselected chip enable pins.

[0068] In another embodiment, the memory controller 210 can establish corresponding write mapping tables for all chip enable pins. For example, when the host system 10 is determined to be idle, the memory controller 210 can establish multiple write mapping tables for all chip enable pins in the cache memory 214. Since the host system 10 is currently idle, the storage space of the cache memory 214 does not need to cache user data or instructions from the host system 10, and the memory controller 210 is not affected by interference from the host system 10. Therefore, during this period, multiple write mapping tables for all chip enable pins can be established to enhance the efficiency of garbage collection operations.

[0069] Figure 7 is a schematic diagram illustrating the establishment of multiple write mapping tables based on a valid data table and the chip enable pin corresponding to the valid data, according to an embodiment of the present invention. For example, referring to Figure 7, assume that a valid data table VT1 has been obtained, which records six address mapping information corresponding to six valid data items, respectively recording the six logical addresses LBA1 to LBA6 of the six valid data items and the six mapped physical addresses PBA1 to PBA6, wherein the valid data is stored at the physical addresses PBA1 to PBA6 of the rewritable non-volatile memory module 220.

[0070] In this example, after identifying the multiple CEs to which physical addresses PBA1 to PBA6 belong, the memory controller 210 can establish write mapping tables WB3(0) to WB3(3) based on all chip enable pins CE0 to 3. For example, write mapping table WB3(0) corresponding to chip enable pin CE0, write mapping table WB3(1) corresponding to chip enable pin CE1, write mapping table WB3(2) corresponding to chip enable pin CE2, and write mapping table WB3(3) corresponding to chip enable pin CE3 are established.

[0071] Next, as shown by arrows A71 and A72, the memory controller 210 records the logical addresses LBA3 and LBA5 of the corresponding chip enable pin CE0 into the write mapping table WB3 (0); as shown by arrows A73 and A74, the memory controller 210 records the logical addresses LBA2 and LBA4 of the corresponding chip enable pin CE1 into the write mapping table WB3 (1); as shown by arrow A735, the memory controller 210 records the logical address LBA6 of the corresponding chip enable pin CE2 into the write mapping table WB3 (2); as shown by arrow A76, the memory controller 210 records the logical address LBA1 of the corresponding chip enable pin CE3 into the write mapping table WB3 (3).

[0072] Next, in write mapping table WB3(0), the memory controller 210 sets the second physical addresses PBA3' and PBA5' mapped to logical addresses LBA3 and LBA5; in write mapping table WB3(1), the memory controller 210 sets the second physical addresses PBA2' and PBA4' mapped to logical addresses LBA2 and LBA4; in write mapping table WB3(2), the memory controller 210 sets the second physical address PBA6' mapped to logical address LBA6; and in write mapping table WB3(3), the memory controller 210 sets the second physical address PBA1' mapped to logical address LBA1. In this way, the generation operation of multiple write mapping tables corresponding to all chip enable pins is completed.

[0073] It should be noted that, as with the concepts in Figures 4 and 5, the methods in Figures 6 and 7 are applicable to examples where there is one or more valid data tables.

[0074] Please refer back to Figure 2. After the write mapping table is established, in step S250, the memory controller 210 writes the plurality of valid data to the rewritable non-volatile memory module 220 according to the plurality of address mapping information of the at least one write mapping table.

[0075] More specifically, the step of writing the plurality of valid data to the rewritable non-volatile memory module according to the plurality of address mapping information written to the at least one mapping table includes: before writing the plurality of valid data to the rewritable non-volatile memory module, selecting target address mapping information among the plurality of address mapping information based on the arrangement order of the plurality of address mapping information; searching for a target first entity address among the plurality of first entity addresses mapped to the target logical address according to the target logical address of the target address mapping information; reading target valid data from the rewritable non-volatile memory module according to the target first entity address; and writing the read target valid data to the rewritable non-volatile memory module 220 according to the target second entity address of the target address mapping information.

[0076] For example, referring to Figure 6, the memory controller 210 can sequentially select the target address mapping information of the corresponding logical address LBA3 from the write mapping table WB2(0) of the corresponding chip enable pin CE0. The memory controller 210 can look up the physical address (also called the target first physical address) PBA1 mapped to the logical address LBA3 from the valid data table VT1 or the logic-to-physical address mapping table. Then, the memory controller 210 reads valid data from the target first physical address PBA1 of the rewritable non-volatile memory module 220. And according to the target second physical address PBA3' of the target address mapping information in the write mapping table WB2(0), the read valid data of the corresponding chip enable pin CE0 is stored in the target second physical address PBA3' of the rewritable non-volatile memory module 220.

[0077] It is worth mentioning that during the write operation of storing the valid data of the corresponding chip enable pin CE0 into the target second physical address PBA3' of the rewritable non-volatile memory module 220, the memory controller 210 can read valid data of other corresponding chip enable pins. For example, according to the logical address LBA2 in the write mapping table WB2(1), the corresponding physical address PBA2 is found and another valid data is read from the physical address PBA2 of the corresponding chip enable pin CE1 of the rewritable non-volatile memory module 220, thereby realizing parallel read and write processing and accelerating the overall efficiency of garbage collection operation.

[0078] It can be noted that the above-mentioned valid data table was generated using conventional methods, and its address mapping information was not recorded according to the order of the chip's enable pins. Figures 8 and 9 below will illustrate how to directly generate a valid data table with address mapping information recorded according to the order of the chip's enable pins. Based on this, write mapping tables that correspond to the order of the chip's enable pins can be generated more efficiently.

[0079] Specifically, in one embodiment, for the generation operation of a valid data table, within the first buffer, the memory controller 210 establishes a valid data table corresponding to multiple chip enable pins in the rewritable non-volatile memory module; selects a target chip enable pin from the multiple chip enable pins in the rewritable non-volatile memory module to perform a valid data table update operation corresponding to the target chip enable pin; obtains multiple candidate entity addresses corresponding to the target chip enable pin; and determines at least one valid entity address mapped to at least one valid logical address from the multiple candidate entity addresses, wherein the at least one valid entity address stores valid data and has no data mapped to any valid logical address. The system stores invalid data at valid physical addresses; and records at least one valid logical address and at least one valid physical address corresponding to the target chip enable pin into the valid data table of the first cache, completes the valid data table update operation corresponding to the target chip enable pin, and determines whether there is at least one unselected chip enable pin. If there is at least one unselected chip enable pin, one of the at least one unselected chip enable pin is selected as the new target chip enable pin to perform the valid data table update operation corresponding to the new target chip enable pin. If there are no unselected chip enable pins, the generation of the valid data table is completed.

[0080] Figure 8 is a schematic diagram illustrating the establishment of a valid data table based on chip enable pins according to an embodiment of the present invention. For example, referring to Figure 8, firstly, the memory controller 210 establishes the valid data table VT2 corresponding to the plurality of chip enable pins CE0 to CE3 in the rewritable non-volatile memory module 220.

[0081] Next, the memory controller 210 selects a target chip enable pin (e.g., chip enable pin CE0) from the plurality of chip enable pins CE0 to CE3 in the rewritable non-volatile memory module 220 to perform a valid data table update operation corresponding to the target chip enable pin CE0.

[0082] Next, the memory controller 210 acquires multiple candidate entity addresses (e.g., entity addresses PBA00 to PBA03...) corresponding to the target chip enable pin CE0. These candidate entity addresses store valid or invalid data. Then, by querying the entity-to-logic mapping table (or querying the entity-to-logic mapping table), the memory controller 210 determines at least one valid entity address (e.g., valid entity addresses PBA01, PBA02) from the multiple candidate entity addresses PBA00 to PBA03... that maps to at least one valid logical address.

[0083] For example, if no valid logical address mapped to physical address PBA00 can be found for physical address PBA00, the memory controller 210 determines that physical address PBA00 is an invalid physical address, that is, invalid data is stored therein.

[0084] For example, if a logical address LBA01 (also known as a valid logical address) mapped to physical address PBA01 is found, the memory controller 210 determines that physical address PBA01 is a valid physical address, that is, valid data is stored.

[0085] After determining the valid physical addresses PBA01 and PBA02 among the multiple candidate physical addresses (e.g., physical addresses PBA00 to PBA03...) of the target chip enable pin CE0, as shown by arrows A81 and A82, the memory controller 210 records the valid physical addresses PBA01 and PBA02 and the corresponding valid logical addresses LBA01 and LBA02 into the valid data table VT2, thus completing the valid data table update operation for the target chip enable pin CE0.

[0086] If at least one chip enable pin that has not yet been selected exists (e.g., CE1 to CE3), and so on, as shown by arrows A83 and A84, the memory controller 210 records the valid physical addresses PBA12 and PBA13 and the corresponding valid logical addresses LBA12 and LBA13 of the corresponding chip enable pin CE1 into the valid data table VT2; as shown by arrow A85, the memory controller 210 records the valid physical address PBA20 and the corresponding valid logical address LBA20 of the corresponding chip enable pin CE2 into the valid data table VT2; as shown by arrow A86, the memory controller 210 records the valid physical address PBA31 and the corresponding valid logical address LBA31 of the corresponding chip enable pin CE3 into the valid data table VT2.

[0087] In this way, after all the valid data table updates for the chip enable pins are completed, the generation of the valid data table VT2 is finished. It can be seen that the address mapping information in the valid data table VT2 has been sorted according to the order of the chip enable pins, and effectively multiple address mapping information grouped according to the corresponding chip enable pins have been obtained.

[0088] It is worth mentioning that, in another embodiment, the memory controller 210 can also directly establish multiple valid data tables corresponding to all chip enable pins.

[0089] More specifically, the memory controller 210 establishes multiple valid data tables within the first buffer, each corresponding to a plurality of chip enable pins in the rewritable non-volatile memory module; determines at least one valid entity address mapped to at least one valid logical address from a plurality of candidate entity addresses corresponding to each chip enable pin, wherein the at least one valid entity address stores valid data, and invalid entity addresses not mapped to any valid logical address store invalid data; and records the at least one valid logical address and the at least one valid entity address to the valid data table corresponding to the same chip enable pin.

[0090] Figure 9 is a schematic diagram illustrating the creation of multiple valid data tables based on chip enable pins according to an embodiment of the present invention. For example, in this embodiment, the memory controller 210 first creates write mapping tables VT3(0) to VT3(3) in the buffer memory 214 according to all chip enable pins CE0 to CE3.

[0091] Similar to the method for determining valid physical addresses illustrated in Figure 8, the memory controller 210 determines the valid physical address of each chip enable pin. Then, the memory controller 210 records all valid physical addresses and corresponding valid logical addresses of each chip enable pin into the corresponding valid data table.

[0092] For example, as shown by arrows A91 and A92, the memory controller 210 records the valid physical addresses PBA01 and PBA02 and the corresponding valid logical addresses LBA01 and LBA02 of the corresponding chip enable pin CE0 into the valid data table VT3 (0); as shown by arrows A93 and A94, the memory controller 210 records the valid physical addresses PBA12 and PBA13 and the corresponding valid logical addresses LBA12 and LBA13 of the corresponding chip enable pin CE1 into the valid data table VT3 (1); as shown by arrow A95, the memory controller 210 records the valid physical address PBA20 and the corresponding valid logical address LBA20 of the corresponding chip enable pin CE2 into the valid data table VT3 (2); as shown by arrow A96, the memory controller 210 records the valid physical address PBA31 and the corresponding valid logical address LBA31 of the corresponding chip enable pin CE3 into the valid data table VT3 (3).

[0093] By using valid data tables that correspond to multiple chip enable pins, future maintenance / management of the valid data tables can be more efficient, and the corresponding target valid data table can be directly updated for the target chip enable pin. Furthermore, since the address mapping information recorded in a single valid data table all corresponds to valid data belonging to the same chip enable pin, the memory controller 210 can use a batch read method via a single valid data table to read multiple valid data entries for a single chip enable pin.

[0094] In one embodiment, after obtaining the valid data table generated by the valid data table generation method provided above, since the logical addresses in it are arranged according to the order of the chip enable pins, the memory controller 210 can directly record the logical addresses in the valid data table into the established write mapping table, and then set the corresponding target entity address to complete the establishment of the write mapping table at a faster speed, thereby accelerating the efficiency of garbage collection operation.

[0095] This embodiment also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is executed in the processor of the storage device, the processor in the storage device performs the steps of the memory management method described above. This computer program product can be implemented specifically through hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0096] Based on the above, the memory management method and memory controller provided in the embodiments of the present invention can establish valid data tables and write mapping tables in different buffers of the buffer memory, and the address mapping information in the established valid data tables / write mapping tables can be arranged / grouped according to the order of the chip enable pins, so as to make the transfer operation of valid data more efficient, avoid the occurrence of write delay, improve the efficiency of garbage collection operation, and thus improve the space utilization and overall working efficiency of the storage device.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method applicable to a memory controller of a memory device configured with a rewritable non-volatile memory module, characterized in that, include: The valid data table is stored in the first cache area of ​​the buffer memory so as to identify the multiple first entity addresses corresponding to multiple valid data through the valid data table; Based on the multiple first entity addresses, identify the storage area to which each piece of valid data belongs; At least one write mapping table is established in the second cache area of ​​the buffer memory based on the valid data table, and the at least one write mapping table is used to record multiple address mapping information of the multiple valid data. in The valid data in the valid data table is reorganized to obtain the multiple address mapping information obtained by reorganizing the multiple valid data, and the multiple address mapping information is written to the write mapping table. as well as Based on the plurality of address mapping information in the at least one write mapping table, the plurality of valid data are written to the rewritable non-volatile memory module.

2. The memory management method according to claim 1, characterized in that, If a write mapping table is established and corresponds to multiple different storage areas, the multiple address mapping information of the write mapping table are arranged in order according to the corresponding storage areas; as well as If a write mapping table corresponds to a storage area, the multiple address mapping information of the write mapping table corresponds to the same storage area.

3. The memory management method according to claim 2, characterized in that, The step of establishing the at least one write mapping table in the second cache root of the buffer memory based on the valid data table includes: Based on the valid data table, identify the logical address of each valid data item; Based on the storage area to which each valid data belongs, sort the logical addresses corresponding to the multiple valid data to obtain multiple sorted logical addresses, wherein the multiple logical addresses corresponding to the same storage area will be arranged together; and Multiple second entity addresses are assigned to the sorted logical addresses to obtain the address mapping information, thereby establishing a write mapping table within the second cache. This write mapping table records the multiple address mapping information, with each address mapping information including a sorted logical address and a mapped second entity address. The order of the multiple address mapping information is the same as the order of the sorted logical addresses. The established write mapping table corresponds to multiple different storage areas.

4. The memory management method according to claim 1, characterized in that, The step of writing the plurality of valid data to the rewritable non-volatile memory module according to the plurality of address mapping information in the at least one write mapping table includes: Before writing the plurality of valid data into the rewritable non-volatile memory module, a target address mapping information is selected from the plurality of address mapping information based on the arrangement order of the plurality of address mapping information; Based on the target logical address of the target address mapping information, find the target first entity address that is mapped to the target logical address among the plurality of first entity addresses; Read valid target data from the rewritable non-volatile memory module according to the target's first entity address; and Based on the target second entity address of the target address mapping information, the read target valid data is written to the rewritable non-volatile memory module.

5. The memory management method according to claim 1, characterized in that, The step of establishing at least one write mapping table in the second cache area of ​​the buffer memory based on the valid data table includes: Based on the valid data table, identify the logical address of each valid data item; Multiple selected storage areas are obtained from the multiple storage areas corresponding to the multiple valid data; Based on the multiple selected storage areas, multiple write mapping tables are respectively established in the second cache area, wherein the multiple write mapping tables correspond to the multiple selected storage areas respectively; The multiple target logical addresses corresponding to the multiple selected storage areas from the multiple logical addresses of the multiple valid data are recorded into the multiple corresponding write mapping tables, wherein the selected storage area corresponding to at least one target logical address in each write mapping table is the same as the selected storage area corresponding to the write mapping table to which it belongs. Multiple second entity addresses are set to be mapped to the multiple target logical addresses respectively, so as to obtain the multiple address mapping information, thereby establishing the multiple write mapping tables in the second cache area, wherein each address mapping information includes a target logical address and a mapped second entity address, and the established write mapping table corresponds to a storage area.

6. The memory management method according to claim 1, characterized in that, The method further includes: Within the first buffer, an effective data table is established, corresponding to multiple storage areas in the rewritable non-volatile memory module; Select a target storage area from among the multiple storage areas in the rewritable non-volatile memory module to perform a valid data table update operation corresponding to the target storage area; Obtain the addresses of multiple candidate entities corresponding to the target storage area; Determine at least one valid entity address from the plurality of candidate entity addresses that maps to at least one valid logical address, wherein the at least one valid entity address stores valid data, and invalid entity addresses that do not map to any valid logical address store invalid data; and Record the at least one valid logical address and the at least one valid physical address corresponding to the target storage area into the valid data table of the first cache area, complete the update operation of the valid data table corresponding to the target storage area, and determine whether there is at least one storage area that has not yet been selected. If at least one of the at least one unselected storage areas exists, one of the at least one unselected storage areas is selected as the new target storage area to perform the corresponding valid data table update operation for the new target storage area. If there are no unselected storage areas, the generation of the valid data table is complete.

7. The memory management method according to claim 1, characterized in that, The method further includes: Within the first buffer, multiple valid data tables are established, each corresponding to a different storage area in the rewritable non-volatile memory module. From a plurality of candidate entity addresses corresponding to each storage area, at least one valid entity address is determined that maps to at least one valid logical address, wherein the at least one valid entity address stores valid data, and invalid entity addresses that do not map to any valid logical address store invalid data; and Record the at least one valid logical address and the at least one valid physical address into a valid data table corresponding to the same storage area.

8. A memory controller for controlling a storage device configured with a rewritable non-volatile memory module, characterized in that, The memory controller includes: A memory interface control circuit is provided for electrical connection to the rewritable non-volatile memory module; and The processor is electrically connected to the memory interface control circuit and the buffer memory of the storage device, wherein the processor is further electrically connected to the connection interface circuit of the storage device for electrical connection to the host system. The processor is configured to: The valid data table is read into the first cache area in the buffer memory, so as to identify multiple first entity addresses corresponding to multiple valid data through the valid data table; Based on the plurality of first entity addresses, identify the chip enable pin to which each valid data belongs; At least one write mapping table is established in the second cache area of ​​the buffer memory based on the valid data table, and the at least one write mapping table is used to record multiple address mapping information of the multiple valid data; wherein The valid data table is reorganized according to the chip enable pin to which each valid data belongs, so as to generate the plurality of second address mapping information into the write mapping table via the reorganized valid data table; and Based on the plurality of address mapping information in the at least one write mapping table, the plurality of valid data are written to the rewritable non-volatile memory module.

9. The memory controller according to claim 8, characterized in that, in If a write mapping table is established and corresponds to multiple different chip enable pins, the multiple address mapping information of the write mapping table are arranged in sequence according to the corresponding chip enable pins; as well as If a write mapping table corresponds to a chip enable pin, the multiple address mapping information of the write mapping table corresponds to the same chip enable pin.

10. The memory controller according to claim 8, characterized in that, In the operation of establishing at least one write mapping table in the second cache area of ​​the buffer memory based on the valid data table and the chip enable pin to which each valid data belongs, The processor identifies the logical address of each valid data item based on the valid data table; Based on the chip enable pin to which each valid data belongs, sort the multiple logical addresses corresponding to the multiple valid data to obtain multiple sorted logical addresses, wherein the multiple logical addresses corresponding to the same chip enable pin will be arranged together; The processor sets multiple second entity addresses, each mapped to one of the multiple sorted logical addresses, to obtain the multiple address mapping information, thereby establishing a write mapping table within the second cache. The write mapping table records the multiple address mapping information, each address mapping information including a sorted logical address and a mapped second entity address. The order of the multiple address mapping information is the same as the order of the multiple sorted logical addresses. The established write mapping table corresponds to multiple different chip enable pins.

11. The memory controller according to claim 8, characterized in that, In the operation of writing multiple valid data into the rewritable non-volatile memory module according to the multiple address mapping information in the at least one write mapping table, Before writing the plurality of valid data into the rewritable non-volatile memory module, the processor selects the target address mapping information from the plurality of address mapping information based on the order of the plurality of address mapping information. The processor searches for the target first entity address mapped to the target logical address among the plurality of first entity addresses based on the target logical address of the target address mapping information; The processor reads the target valid data from the rewritable non-volatile memory module according to the target first entity address; as well as The processor writes the read target valid data into the rewritable non-volatile memory module according to the target second entity address of the target address mapping information.

12. The memory controller according to claim 8, characterized in that, In the operation of establishing at least one write mapping table in the second cache area of ​​the buffer memory based on the valid data table and the chip enable pin to which each valid data belongs, The processor identifies the logical address of each valid data item based on the valid data table; The processor obtains multiple selected chip enable pins from the multiple chip enable pins corresponding to the multiple valid data; The processor establishes multiple write mapping tables in the second cache area according to the multiple selected chip enable pins, wherein each write mapping table corresponds to a selected chip enable pin; The processor records the multiple target logical addresses corresponding to the multiple selected chip enable pins from the multiple logical addresses of the multiple valid data into the corresponding multiple write mapping tables, wherein the selected chip enable pin corresponding to at least one target logical address in each write mapping table is the same as the selected chip enable pin corresponding to the write mapping table to which it belongs. The processor sets multiple second entity addresses respectively mapped to the multiple target logical addresses to obtain the multiple address mapping information, thereby establishing multiple write mapping tables in the second cache area, wherein each address mapping information includes a target logical address and a mapped second entity address, and the established write mapping table corresponds to a chip enable pin.

13. The memory controller according to claim 8, characterized in that, The processor establishes, within the first buffer, the effective data table corresponding to multiple chip enable pins in the rewritable non-volatile memory module; The processor selects a target chip enable pin from a plurality of chip enable pins in the rewritable non-volatile memory module to perform a valid data table update operation corresponding to the target chip enable pin. The processor acquires multiple candidate entity addresses corresponding to the enable pin of the target chip; The processor determines from the plurality of candidate entity addresses at least one valid entity address that maps to at least one valid logical address, wherein the at least one valid entity address stores valid data, and invalid entity addresses that do not map to any valid logical address store invalid data. as well as The processor records at least one valid logical address and at least one valid physical address corresponding to the enable pin of the target chip into the valid data table of the first cache, completes the valid data table update operation corresponding to the enable pin of the target chip, and determines whether there is at least one chip enable pin that has not yet been selected. If at least one of the chip enable pins has not yet been selected, the processor selects one of the at least one unselected chip enable pins as a new target chip enable pin to perform the valid data table update operation corresponding to the new target chip enable pin. If there are no unselected chip enable pins, the processor completes the generation of the valid data table.

14. The memory controller according to claim 8, characterized in that, Within the first buffer, the processor establishes multiple valid data tables that correspond to multiple chip enable pins in the rewritable non-volatile memory module. The processor determines at least one valid entity address mapped to at least one valid logical address from a plurality of candidate entity addresses corresponding to each chip enable pin, wherein the at least one valid entity address stores valid data, and invalid entity addresses not mapped to any valid logical address store invalid data. as well as The processor records the at least one valid logical address and the at least one valid physical address into a valid data table corresponding to the same chip enable pin.

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