Semiconductor structure, manufacturing method for semiconductor structure, device, and apparatus

Abstract

Embodiments of the present disclosure provide a semiconductor structure, a manufacturing method for the semiconductor structure, a device, and an apparatus. The semiconductor structure comprises: a first front-side transistor and a second front-side transistor; a first back-side transistor and a second back-side transistor; a first dielectric wall structure, the first front-side transistor and the second front-side transistor being symmetrically arranged on two sides of the first dielectric wall structure; a second dielectric wall structure, the first back-side transistor and the second back-side transistor being symmetrically arranged on two sides of the second dielectric wall structure; a first power rail structure, connected to source / drain structures of the front-side transistors or source / drain structures of the back-side transistors; and a second power rail structure, connected to the source / drain structures of the back-side transistors or the source / drain structures of the front-side transistors, wherein the first power rail structure and the second power rail structure are stacked between the first dielectric wall structure and the second dielectric wall structure, and the orthographic projection of the first power rail structure overlaps the orthographic projection of the second power rail structure.

Description

Semiconductor structure, semiconductor structure fabrication methods, devices and equipment

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202410923757.1, filed on July 10, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for preparing the semiconductor structure, a device, and an apparatus. Background Technology

[0004] With Moore's Law continuing to advance, further miniaturizing transistors is a hot research topic in the industry. Stacking transistors, by integrating two or more layers of transistors in a vertical space, further increases transistor integration density and has become one of the important technologies for continuing the miniaturization of integrated circuits.

[0005] Currently, the arrangement of multiple power rails and signal lines inside a transistor on the same plane limits the miniaturization of transistor size, and the interconnection scheme inside the transistor is limited. Summary of the Invention

[0006] This disclosure provides a semiconductor structure, a method for fabricating the semiconductor structure, a device, and an apparatus.

[0007] This disclosure provides a semiconductor structure in a first aspect. The semiconductor structure includes: a front transistor; the front transistor is a fork-shaped transistor, including a first front transistor and a second front transistor; a back transistor; the back transistor is a fork-shaped transistor, including a first back transistor and a second back transistor; the front transistor and the back transistor are self-aligned in a direction perpendicular to the active region; a first dielectric wall structure; the first front transistor and the second front transistor are symmetrically disposed on both sides of the first dielectric wall structure; a second dielectric wall structure; the first back transistor and the second back transistor are symmetrically disposed on both sides of the second dielectric wall structure; a first power rail structure; the first power rail structure is connected to the source / drain structure of the front transistor or the source / drain structure of the back transistor; the first power rail structure is configured to provide a first voltage; a second power rail structure; the second power rail structure is connected to the source / drain structure of the back transistor or the source / drain structure of the front transistor; the second power rail structure is configured to provide a second voltage; wherein the first power rail structure and the second power rail structure are stacked between the first dielectric wall structure and the second dielectric wall structure; the orthographic projections of the first power rail structure and the second power rail structure overlap.

[0008] A second aspect of this disclosure provides a method for fabricating a semiconductor structure. The method includes: sequentially forming a pair of first pillar-shaped structures, a pair of sacrificial structures, and a pair of second pillar-shaped structures stacked from top to bottom on a substrate; depositing a metal material of a predetermined height in a first region to form a first power rail structure; the first region being located between the pair of sacrificial structures; forming a front-side transistor based on the pair of first pillar-shaped structures; the front-side transistor being a fork-shaped transistor, including a first front-side transistor and a second front-side transistor; flipping and removing the substrate; depositing a metal material of a predetermined height in a second region to form a second power rail structure; the second region being located between the pair of sacrificial structures; forming a back-side transistor based on the pair of second pillar-shaped structures; the back-side transistor being a fork-shaped transistor, including a first back-side transistor and a second back-side transistor; wherein the first power rail structure is connected to the source / drain structure of the front-side transistor or the source / drain structure of the back-side transistor; the first power rail structure is configured to provide a first voltage; the second power rail structure is connected to the source / drain structure of the back-side transistor or the source / drain structure of the front-side transistor; the second power rail structure is configured to provide a second voltage.

[0009] A third aspect of this disclosure provides a semiconductor device. The semiconductor device includes a plurality of semiconductor structures as described in the first aspect above.

[0010] This disclosure provides a fourth aspect of an electronic device. The electronic device includes a circuit board and a semiconductor device as described in the third aspect above, the semiconductor device being disposed on the circuit board.

[0011] In this disclosure, a semiconductor structure formed on the basis of stacked transistors and fork transistors can optimize the internal interconnection of the semiconductor structure while reducing the size of the semiconductor structure by means of a first power rail structure connected to the source-drain structure of the front transistor or the source-drain structure of the back transistor and a second power rail structure connected to the source-drain structure of the back transistor or the source-drain structure of the front transistor.

[0012] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of embodiments of this disclosure.

[0014] Figure 1 is a schematic diagram of a first type of semiconductor structure provided according to an embodiment of the present disclosure.

[0015] Figure 2 is a schematic diagram of a second semiconductor structure provided according to an embodiment of the present disclosure.

[0016] Figure 3 is a schematic diagram of a first structure of a semiconductor structure provided according to an embodiment of the present disclosure in the AA' direction.

[0017] Figure 4 is a schematic diagram of a second structure of the semiconductor structure provided according to an embodiment of the present disclosure in the AA' direction.

[0018] Figure 5 is a schematic diagram of a third semiconductor structure in the AA' direction according to an embodiment of the present disclosure.

[0019] Figure 6 is a schematic diagram of a semiconductor device provided according to an embodiment of the present disclosure in the AA' direction.

[0020] Figure 7 is a schematic flowchart of an embodiment of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0021] Reference numerals in the figures illustrate: Semiconductor structure 10; Front transistor 11; Front transistor 111; Second front transistor 112; Front source / drain metal 113; First front nanosheet structure 1111; First front gate structure 1112; First front source / drain structure 1114; First front interlayer dielectric layer 1115; First front gate dielectric layer 1116; First front metal interconnect layer 1117; Second front nanosheet structure 1121; Second front gate structure 1122; Second front source / drain structure 1124; Second front interlayer dielectric layer 1125; Second front gate dielectric layer 1126; Second front metal interconnect layer 1127; Back transistor 12; First back transistor 121; Second back transistor 122; First back source / drain metal 1213; Second back source / drain metal 1223; First back nanosheet structure 1211; First back... 1212: Front gate structure; 1214: First back-side source / drain structure; 1215: First back-side interlayer dielectric layer; 1216: First back-side gate dielectric layer; 1217: First back-side metal interconnect layer; 1221: Second back-side nanosheet structure; 1222: Second back-side gate structure; 1224: Second back-side interlayer dielectric layer; 1225: Second back-side gate dielectric layer; 1226: Second back-side metal interconnect layer; 1227: First dielectric wall structure; 131: Second dielectric wall structure; 132: First power rail structure; 141: Second power rail structure; 142: First metal via; 151: Second metal via; 152: First metal interconnect; 161: Second metal interconnect; 162: Intermediate isolation structure; 17: First gate isolation structure; 181: Second gate isolation structure; 182: Shallow trench isolation layer; 21: Second insulating layer; 22: Carrier wafer. Detailed Implementation

[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this disclosure.

[0023] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments disclosed herein. The singular forms “a,” “the,” and “the” used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0024] With Moore's Law continuously evolving, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, through three-dimensional stacking, can integrate two or more layers of transistors in a vertical space, helping to increase transistor integration density and improve circuit performance. This technology is considered one of the key technologies for continuing the miniaturization of integrated circuits. There are at least two manufacturing processes for stacked transistors: monolithic and sequential.

[0025] The characteristics of the monolithic approach include: (1) It does not use wafer bonding technology, but instead fabricates N-type metal oxide semiconductor (NMOS) transistors and P-type metal oxide semiconductor (PMOS) transistors on the same substrate, and stacks the two types of transistors vertically. This determines that the transistors in the same layer must be of the same type, i.e., NMOS or PMOS; (2) The transistors in the same layer must be strictly in the same plane space, and there is no alignment deviation. The advantage of the monolithic approach is that it has better integration density, while the disadvantages of the monolithic approach include the following: 1) The process is complex, requiring a lot of process technology development and optimization; 2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied upon to form a basic complementary metal oxide semiconductor (CMOS) circuit, resulting in poor design flexibility.

[0026] The sequential approach is characterized by wafer bonding and layer-by-layer processing to achieve vertical stacking of upper and lower transistors. Thanks to wafer bonding, the device structure, channel orientation, and even channel materials used in the upper and lower transistors can be optimized to obtain better and more matched device performance. However, the thermal process during the processing of the upper transistor may affect the lower transistor and interconnects, and the thermal budget must be strictly controlled throughout the processing. At the same time, the temperature that the subsequent interconnects can withstand is also limited, which will also limit the thermal budget. Therefore, the sequential approach currently faces the following technical challenges: (1) the fabrication of high-quality upper transistor active layers; (2) the thinning and defect control of the upper transistor bonding wafer; and (3) the alignment error between the upper and lower transistors, which requires extremely high photolithography precision.

[0027] The common technical challenges faced by the two schemes mentioned above include: (1) the thermal stability of the lower-level devices when fabricating the upper-level devices; (2) the performance of the upper-level devices under low thermal budget; and (3) the metal interconnection of transistors between layers.

[0028] Traditional interconnect schemes are based on planar interconnects, arranging multiple power rails (i.e., VDD (voltage drain) and VSS (voltage source and sink)) and multiple signal lines (i.e., metal interconnects) on the same line. Figure 1 is a schematic diagram of a first type of semiconductor structure provided according to an embodiment of the present disclosure; Figures (a) to (c) in Figure 1 show three schematic diagrams of structures in which multiple power rails and multiple signal lines are arranged on the same horizontal line. Referring to Figure 1, 1T is short for 1Track, which refers to the sum of the lengths of one signal line and one adjacent spacing; the unit height of the semiconductor structure is H1, which is the distance between the center line passing through VDD and the center line passing through VSS. As shown in Figure 1(a), because H1 is relatively large, the formed VSS, VDD and multiple signal lines occupy a large planar area, which limits the miniaturization of the semiconductor structure. As shown in Figure 1(b), optimizing the signal line arrangement in three dimensions, VDD and VSS are distributed in the front and back transistors of the stacked transistors, respectively. Since the front and back transistors only require one power rail, the structural schematic shown in Figure 1(b) results in wasted power rails. As shown in Figure 1(c), using a unipolar approach to design the semiconductor structure, only one polarity power rail is needed on the front or back of the stacked transistors. That is, one VDD can be designed in the front or back transistor, and one VSS can be designed in the back or front transistor. This reduces the unit height of the semiconductor structure. However, since VDD and VSS are set on the same horizontal plane as the signal lines, the interconnection scheme inside the semiconductor structure is relatively simple.

[0029] In some embodiments, this disclosure provides a semiconductor structure.

[0030] In some embodiments, the above-described semiconductor structure can be applied to semiconductor devices such as memory and processors.

[0031] The above-described semiconductor structure will now be described by way of example with reference to FIG2, which is a schematic diagram of a second semiconductor structure provided according to an embodiment of the present disclosure. In FIG2, (a) is a design layout of the semiconductor structure, (b) is a cross-sectional view of the semiconductor structure taken along the tangential direction of the gate structure (i.e., the AA' direction), and (c) is a cross-sectional view of the semiconductor structure taken along the tangential direction of the source-drain structure (i.e., the BB' direction).

[0032] Referring to FIG2, the semiconductor structure 10 includes: a front transistor 11; the front transistor 11 is a fork-shaped transistor, including a first front transistor 111 and a second front transistor 112; a back transistor 12; the back transistor 12 is a fork-shaped transistor, including a first back transistor 121 and a second back transistor 122; the front transistor 11 and the back transistor 12 are self-aligned in a direction perpendicular to the active region; a first dielectric wall structure 131; the first front transistor 111 and the second front transistor 112 are symmetrically disposed on both sides of the first dielectric wall structure 131; a second dielectric wall structure 132; the first back transistor 121 and the second back transistor 122 are symmetrically disposed on both sides of the second dielectric wall structure 132; a first power rail structure 141; the first power rail structure 141 is connected to the source-drain structure of the front transistor or the source-drain structure of the back transistor; the first power rail structure 141 is configured to provide a first voltage; a second power rail structure 142; the second power rail structure 142 is connected to the source-drain structure of the back transistor or the source-drain structure of the front transistor; the second power rail structure 142 is configured to provide a second voltage.

[0033] It is understandable that the first front transistor and the first back transistor are arranged in a "back-to-back" configuration to form a stacked transistor, and the second front transistor and the second back transistor also form a stacked transistor.

[0034] In some embodiments, the first voltage and the second voltage have different voltage values.

[0035] In some embodiments, the active region is a collective term for the source region, the drain region, and the channel region.

[0036] In some embodiments, as shown in FIG2, the first power rail structure 141 and the second power rail structure 142 are stacked between the first dielectric wall structure 131 and the second dielectric wall structure 132; the orthographic projection of the first power rail structure 141 and the orthographic projection of the second power rail structure 142 overlap.

[0037] In some embodiments, the first type transistor and the second type transistor represent different types of transistors, that is, in the semiconductor structure, the front transistor 11 and the back transistor 12 can be different types of transistors; for example, the first type transistor can be an NMOS and the second type transistor can be a PMOS; or, the first type transistor can be a PMOS and the second type transistor can be an NMOS. It should be noted that the first type transistor and the second type transistor are not limited to the two types of transistors listed above, and can also be other types of transistors, which are not limited in this disclosure.

[0038] In some possible implementations, taking NMOS as the first type of transistor and PMOS as the second type of transistor as an example, the front transistor 11 is an NMOS and the back transistor 12 is a PMOS; the first power rail structure 141 is connected to the front source / drain metal 113 of the front transistor 11 through the first metal via 151 provided in the first dielectric wall structure 131; the second power rail structure 142 is connected to the first back source / drain metal 1213 of the first back transistor 121 or the second back source / drain metal 1223 of the second back transistor 122 through the second metal via 152 provided in the second dielectric wall structure 132.

[0039] Understandably, the first power rail structure 141 can be the VSS corresponding to the source terminal of an NMOS transistor, and the second power rail structure 142 can be the VDD corresponding to the source terminal of a PMOS transistor. When the front transistor 11 is an NMOS and the back transistor 12 is a PMOS transistor, as shown in Figure 1, the first power rail structure 141 can be connected to the front source / drain metal 113 through the first metal via 151; the second power rail structure 142 can be connected to the first back source / drain metal 1213 of the first back transistor 121 through the second metal via 152. It should be noted that in the above case, the front source / drain metal 113 spans the first front source / drain structure of the first front transistor 111 and the second front source / drain structure of the second front transistor 112, and is in contact with both the first and second front source / drain structures; that is, the first front transistor 111 and the second front transistor 112 share the front source / drain metal 113.

[0040] In some embodiments, taking FIG2 above as an example, since the source-drain structure and the source-drain metal in the transistor are in contact with each other, and in the front transistor 11, the first power rail structure 141 is connected to the front source-drain metal 113, the first power rail structure 141 is interconnected with the front source-drain structure; correspondingly, the second power rail structure 142 is interconnected with the back source-drain structure.

[0041] In some embodiments, referring to FIG2, a first metal through-hole 151 is disposed inside the first dielectric wall structure 131, one end of the first metal through-hole 151 is connected to the first power rail structure 141, and the other end is connected to the front source / drain metal 113. A second metal through-hole 152 is disposed inside the second dielectric wall structure 132, one end of the second metal through-hole 152 is connected to the second power rail structure 142, and the other end is connected to the first back source / drain metal 1213.

[0042] In some possible implementations, taking NMOS as an example and PMOS as an example of a first type of transistor and PMOS as a second type of transistor, the front transistor 11 is a PMOS and the back transistor 12 is an NMOS; the second power rail structure 142 is connected to the first front source / drain metal of the first front transistor 111 or the second front source / drain metal of the second front transistor 112 through the first metal via 151 provided in the first dielectric wall structure 131; the first power rail structure 141 is connected to the back source / drain metal of the back transistor 12 through the second metal via 152 provided in the second dielectric wall structure 132.

[0043] In some embodiments, as shown in FIG2, a first insulating layer of a predetermined height is provided between the first power rail structure 141 and the second power rail structure 142, and the first insulating layer is used to isolate the first power rail structure 141 and the second power rail structure 142.

[0044] In some embodiments, as shown in FIG2, a shallow trench isolation layer 19 is provided between the front transistor 11 and the back transistor 12, and the shallow trench isolation layer 19 and the intermediate isolation structure 17 are used to isolate the front transistor 11 and the back transistor 12.

[0045] In some possible implementations, FIG3 is a schematic diagram of a first structure of a semiconductor structure provided according to an embodiment of the present disclosure in the AA' direction. Referring to FIG3, the semiconductor structure 10 further includes: at least four first metal interconnects 161; the first metal interconnects 161 are disposed in the front transistor 11; the first metal interconnects 161 are formed by a back-end process; at least four second metal interconnects 162; the second metal interconnects 162 are disposed in the back transistor 12; the second metal interconnects 162 are formed by a back-end process.

[0046] Referring to Figure 3, which only shows the first power rail structure 141, the second power rail structure 142, the first metal interconnect 161, and the second metal interconnect 162, the first front-side transistor and the second front-side transistor located on both sides of the first dielectric wall structure can share the first power rail structure 141; similarly, the first back-side transistor and the second back-side transistor located on both sides of the second dielectric wall structure can share the second power rail structure 142. This allows for a reduction in the area of ​​the semiconductor structure and an increase in integration density.

[0047] In some embodiments, the structural schematic diagram shown in FIG3 includes two stacked transistors, namely a stacked transistor composed of a first front transistor and a first back transistor (i.e., the first stacked transistor), and a stacked transistor composed of a second front transistor and a second back transistor (i.e., the second stacked transistor). The structural schematic diagram shown in FIG3 is a structural schematic diagram of two adjacent 2T stacked transistors, that is, the smallest unit of both the first stacked transistor and the second stacked transistor is 2T, and the first stacked transistor and the second stacked transistor share the first power rail structure 141 and the second power rail structure 142.

[0048] In some possible implementations, an intermediate isolation structure 17 is provided between the front transistor 11 and the back transistor 12; the intermediate isolation structure 17 is symmetrically distributed on both sides of the first power rail structure 141 and the second power rail structure 142; the intermediate isolation structure 17 is used to isolate the front transistor 11 and the back transistor 12.

[0049] As can be understood, referring to Figure 2, the intermediate isolation structure 17 is made of dielectric material and is located between the front transistor 11 and the back transistor 12 to achieve isolation between them. It should be noted that the term "isolation" mentioned in this embodiment can refer to physical isolation or electrical isolation, and this embodiment does not limit the meaning of the term.

[0050] In some embodiments, the first metal interconnect 161 is a signal line in the MO metal layer of the front transistor 11, used for the lead-out of the source / drain structure and the gate structure in the front transistor 11; the second metal interconnect 162 is a signal line in the MO metal layer of the back transistor 12, used for the lead-out of the source / drain structure and the gate structure in the back transistor 12.

[0051] It should be noted that the lead-out positions of the first metal interconnect 161 and the second metal interconnect 162 can be designed according to actual needs, and this embodiment does not limit this.

[0052] In some embodiments, as shown in FIG2, the first front transistor 111 in the front transistor 11 includes: a first front nanosheet structure 1111, a first front gate structure 1112, a first front source / drain structure 1114, a first front interlayer dielectric layer 1115, a first front gate dielectric layer 1116, and a first front metal interconnect layer 1117.

[0053] In some embodiments, as shown in FIG2, the second front transistor 112 in the front transistor 11 includes: a second front nanosheet structure 1121, a second front gate structure 1122, a second front source / drain structure 1124, a second front interlayer dielectric layer 1125, a second front gate dielectric layer 1126, and a second front metal interconnect layer 1127.

[0054] The first front-side transistor 111 and the second front-side transistor 112 share a common source-drain metal, namely the front-side source-drain metal 113. The first front-side gate structure 1112 and the second front-side gate structure 1122 are symmetrically distributed on both sides of the first dielectric wall structure 131 and the first gate isolation structure 181. The first gate isolation structure 181 is located between the first dielectric wall structure 131, the first front-side metal interconnect layer 1117, and the second front-side metal interconnect layer 1127, and is used to isolate the first front-side gate structure 1112 and the second front-side gate structure 1122.

[0055] It should be noted that, for ease of explanation, the first front-side source / drain structure mentioned in the embodiments of this disclosure is an abbreviation, referring to the first front-side source structure and / or the first front-side drain structure. Furthermore, the terms "second front-side source / drain structure," "first back-side source / drain structure," and "second back-side source / drain structure" mentioned in the embodiments of this disclosure all use the abbreviation for "source and / or drain."

[0056] In some embodiments, as shown in FIG2, the first back-side transistor 121 in the back-side transistor 12 includes: a first back-side nanosheet structure 1211, a first back-side gate structure 1212, a first back-side source / drain metal 1213, a first back-side source / drain structure 1214, a first back-side interlayer dielectric layer 1215, a first back-side gate dielectric layer 1216, and a first back-side metal interconnect layer 1217.

[0057] In some embodiments, as shown in FIG2, the second back transistor 122 in the back transistor 12 includes: a second back nanosheet structure 1221, a second back gate structure 1222, a second back source / drain metal 1223, a second back source / drain structure 1224, a second back interlayer dielectric layer 1225, a second back gate dielectric layer 1226, and a second back metal interconnect layer 1227.

[0058] The first back gate structure 1212 and the second back gate structure 1222 are symmetrically distributed on both sides of the second dielectric wall structure 132 and the second gate isolation structure 182. The second gate isolation structure 182 is located between the second dielectric wall structure 132, the first back metal interconnect layer 1217, and the second back metal interconnect layer 1227, and is used to isolate the first back gate structure 1212 and the second back gate structure 1222.

[0059] In some embodiments, as shown in FIG2, a second insulating layer 21 and a wafer 22 are disposed on a first surface of the front transistor 11. The first surface is the surface of the front transistor 11 that is away from the back transistor 12.

[0060] In some embodiments, FIG4 is a schematic diagram of a second structure of the semiconductor structure provided according to the present disclosure in the AA' direction. Referring to FIG4, when the front transistor 11 is a PMOS and the back transistor 12 is an NMOS, the first front transistor 111 and the second front transistor 112 located on both sides of the first dielectric wall structure can share the second power rail structure 142; the first back transistor 121 and the second back transistor 122 located on both sides of the first dielectric wall structure can share the first power rail structure 141. In this way, the area of ​​the semiconductor structure can be reduced and the integration density can be increased.

[0061] Understandably, when the front transistor 11 is a PMOS and the back transistor 12 is an NMOS, it is only necessary to change the positions of the first power rail structure 141 and the second power rail structure 142 in the design layout so that in the prepared semiconductor structure 10, the first power rail structure 141 still provides the first voltage to the NMOS and the second power rail structure 142 still provides the second voltage to the PMOS.

[0062] In some embodiments, the structural schematic diagrams shown in Figures 3 and 4 above are all 2T structures. However, the 2T structure is only an example. The stacked transistors in the semiconductor structure described in the embodiments of this disclosure can also be set as 3T structures, 4T structures, etc., according to actual needs.

[0063] In some embodiments, a 3T structure is used as an example for illustration. FIG5 is a schematic diagram of a third semiconductor structure in the AA' direction according to an embodiment of the present disclosure. Referring to FIG5, the stacked transistors in the semiconductor structure are a 3T structure. The first stacked transistor and the second stacked transistor share the first power rail structure 141 and the second power rail structure 142. It should be noted that, except for the number of metal interconnects and the width of the transistors, the semiconductor structure of the 3T structure design shown in FIG5 is the same as the semiconductor structure of the 2T structure design shown in FIG3 and FIG4 above.

[0064] In some embodiments, taking a 2T transistor structure as an example, multiple semiconductor structures can be stacked together to form a semiconductor device. Figure 6 is a schematic diagram of a semiconductor device in the AA' direction according to an embodiment of the present disclosure. Referring to Figure 6, three semiconductor structures are stacked together, and adjacent stacked transistors share a pair of power rails (i.e., the first power rail structure 141 and the second power rail structure 142). In this way, by stacking multiple semiconductor structures together using a mirror symmetry approach, the area of ​​the semiconductor device can be saved and the integration density can be increased.

[0065] In some embodiments, a semiconductor structure formed on the basis of stacked transistors and fork-shaped transistors can achieve internal interconnection of the semiconductor structure while reducing the size of the semiconductor structure by means of a first power rail structure connected to the source-drain structure of the front transistor or the source-drain structure of the back transistor and a second power rail structure connected to the source-drain structure of the back transistor or the source-drain structure of the front transistor.

[0066] In some embodiments, while optimizing the internal interconnection of the semiconductor structure, the first power rail structure and the second power rail structure can also ensure the signal distribution and transmission inside the semiconductor structure, ensure effective power supply, and realize the miniaturization of the semiconductor structure.

[0067] The following describes the fabrication method of the semiconductor structure according to an embodiment of the present disclosure, using the semiconductor structure shown in Figure 2 as an example. Figure 7 is a schematic flowchart of an implementation of the fabrication method of the semiconductor structure provided according to an embodiment of the present disclosure. Referring to Figure 7, the above-mentioned fabrication method of the semiconductor structure may include:

[0068] S701, a pair of first columnar structures, a pair of sacrificial structures and a pair of second columnar structures are sequentially formed on the substrate from top to bottom.

[0069] Understandably, a first stack, a sacrificial material layer, and a second stack are sequentially stacked on the substrate. By etching the first stack, the sacrificial material layer, and the second stack, a pair of first columnar structures, a pair of sacrificial structures, and a pair of second columnar structures can be formed. The pair of first columnar structures is formed by etching the first stack, the pair of sacrificial structures is formed by etching the sacrificial material layer, and the pair of second columnar structures is formed by etching the second stack.

[0070] In some embodiments, the first stack may be formed by alternately stacking a first semiconductor material layer and a second semiconductor material layer. For example, the first semiconductor material layer may be a silicon (Si) material layer, and the second semiconductor material layer may be a silicon-germanium (SiGe) material layer. Similarly, the second stack may also be formed by alternately stacking a first semiconductor material layer and a second semiconductor material layer.

[0071] In some embodiments, the sacrificial material layer may also be made of silicon-germanium material.

[0072] After S701 and before S702, the method may further include: depositing insulating material on a pair of first columnar structures, a pair of sacrificial structures, a pair of second columnar structures, and a substrate to form a shallow trench isolation structure; the shallow trench isolation structure enclosing the pair of first columnar structures, the pair of sacrificial structures, and the pair of second columnar structures; etching a portion of the shallow trench isolation structure until the pair of first columnar structures and the pair of sacrificial structures at a predetermined height are exposed.

[0073] Understandably, when etching shallow trench isolation structures, the etching depth should be controlled. After etching is completed, a pair of first columnar structures are exposed, and a portion of a pair of sacrificial structures are exposed to facilitate the subsequent formation of front-side transistors and first power rail structures.

[0074] In some embodiments, the insulating material forming the shallow trench isolation structure can be any of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2), or silicon oxycarbide (SiCO), etc.

[0075] In some embodiments, after forming the shallow trench isolation structure, the above method may further include performing chemical-mechanical planarization (CMP) on the shallow trench isolation structure.

[0076] In some embodiments, chemical mechanical planarization of the shallow trench isolation structure can ensure that the corrosion depth of the shallow trench isolation structure in different regions is the same when the shallow trench isolation structure is subsequently etched, thereby making the height of the exposed pair of first columnar structures and pair of sacrificial structures the same.

[0077] S702, depositing a metal material of a predetermined height in the first region to form a first power rail structure.

[0078] The first region is located between a pair of sacrificial structures.

[0079] Understandably, the first power rail structure is made of metallic material and is located on the etched shallow trench isolation structure, between a pair of sacrificial structures.

[0080] In some embodiments, S702 may include: depositing metal material on the etched shallow trench isolation structure until the height of the deposited metal material is the same as (or slightly higher / lower than) the height of the pair of first columnar structures; then, selectively etching to remove a portion of the metal material until the height of the remaining metal material meets a preset height; and etching to remove the metal material located on both sides of the pair of first columnar structures, retaining the metal material located between the pair of sacrificial structures to form a first power rail structure.

[0081] The S703 is a front-side transistor formed based on a pair of first columnar structures.

[0082] Among them, the front transistor is a fork-shaped transistor, including a first front transistor and a second front transistor.

[0083] Understandably, after forming the first power rail structure, a fork-shaped transistor (i.e., a front-side transistor) can be formed according to standard transistor fabrication processes. In the first dielectric wall structure of the front-side transistor, a metal via (i.e., a first metal via) is provided. One end of the first metal via connects to the first power rail structure, and the other end connects to the front-side source / drain metal of the front-side transistor. In this way, interconnection between the first power rail structure and the front-side source / drain structure of the front-side transistor can be achieved.

[0084] In some possible implementations, the above method may further include: depositing dielectric material between a pair of first pillar structures to form a first dielectric wall structure; the first front transistor and the second front transistor are symmetrically disposed on both sides of the first dielectric wall structure.

[0085] In one example, the process for forming a front-side transistor is as follows: After forming a first power rail structure, a dielectric material of a predetermined height is deposited in the gap between a pair of first pillar structures to form a first dielectric wall structure. Source-drain epitaxial growth is performed in the source-drain region of the front-side transistor to form a front-side source-drain structure (including a first front-side source-drain structure and a second front-side source-drain structure). The first dielectric wall structure located in the front-side source-drain region is photolithographically etched, stopping at the first power rail structure to form a groove. Metal material is filled into the groove to form a first metal via. Insulating material is deposited in the area of ​​the front-side transistor other than the front-side source-drain region to form the front-side interlayer dielectric layer of the front-side transistor (including a first front-side interlayer dielectric layer and a second front-side interlayer dielectric layer). Photolithography is used to open the front gate region of the front transistor. In the front gate region, an insulating material of a predetermined height is deposited above the first dielectric wall structure to form a first gate isolation structure. Next, the channel is released by removing the SiGe material layer from the first pillar structure, forming a front nanosheet structure (including a first front nanosheet structure and a second front nanosheet structure). Then, metal material is deposited in the front gate region to form a front gate structure (including a first front gate structure and a second front gate structure). Metal material is deposited on the front source / drain structure to form front source / drain metal, which contacts the first metal via. Subsequent processes are performed on the front interlayer dielectric layer and the front gate structure to form a front metal interconnect layer (including a first front metal interconnect layer and a second metal interconnect layer).

[0086] S704, rewind and remove substrate.

[0087] Understandably, after the front-side transistor is fabricated, it is flipped so that the substrate faces upward. Then, the substrate is removed until the surface of the shallow trench isolation structure and the second columnar structure away from the first columnar structure is exposed.

[0088] In some possible implementations, prior to S704 above, the method may further include: depositing an insulating material on the upper surface of the front transistor to form a second insulating layer; and bonding the second insulating layer to a carrier wafer.

[0089] In some embodiments, the bonded carrier wafer can provide physical support for the flipped front-side transistor after the wafer is flipped, effectively preventing the front-side transistor from being broken by external force during the fabrication of the back-side transistor.

[0090] In some embodiments, after S704 and before S705, the method may further include: removing a portion of the shallow trench isolation structure until the second columnar structure and a portion of the sacrificial structure are exposed; the unetched shallow trench isolation structure is located between the front transistor and the back transistor and serves as a shallow trench isolation layer.

[0091] S705, depositing a metal material of a predetermined height in the second region to form a second power rail structure.

[0092] The second region is located between a pair of sacrificial structures.

[0093] Understandably, the second power rail structure is made of metallic material and is located on the shallow trench isolation layer and the first power rail structure, between a pair of sacrificial structures.

[0094] In some embodiments, S705 may include: depositing metal material on a shallow trench isolation layer until the height of the deposited metal material is the same as (or slightly higher / lower than) the height of a pair of second columnar structures; then, selectively etching to remove a portion of the metal material until the height of the remaining metal material meets a preset height; and etching to remove the metal material located on both sides of the pair of second columnar structures, retaining the metal material located between the pair of sacrificial structures to form a second power rail structure.

[0095] The S706 is based on a pair of second pillar structures that form the back-side transistor.

[0096] The back-side transistor is a fork-shaped transistor, comprising a first back-side transistor and a second back-side transistor.

[0097] Understandably, after forming the second power rail structure, a forked transistor on the back side (i.e., a back-side transistor) can be formed according to standard transistor fabrication processes. In the second dielectric wall structure of the back-side transistor, a metal via (i.e., a second metal via) is provided. One end of the second metal via connects to the second power rail structure, and the other end connects to the back-side source / drain metal of the back-side transistor. In this way, interconnection between the second power rail structure and the back-side source / drain structure of the back-side transistor can be achieved.

[0098] In some possible implementations, the above method may further include: depositing dielectric material between a pair of second pillar structures to form a second dielectric wall structure; the first and second back transistors are symmetrically disposed on both sides of the second dielectric wall structure.

[0099] In one example, the process for forming the back-side transistor is as follows: After forming the second power rail structure, a dielectric material of a predetermined height is deposited in the gap between a pair of second pillar structures to form a second dielectric wall structure. Source-drain epitaxial growth is performed in the source-drain region of the back-side transistor to form a back-side source-drain structure (including a first back-side source-drain structure and a second back-side source-drain structure). Photolithography is performed on the second dielectric wall structure located in the back-side source-drain region, with etching stopping at the second power rail structure to form a groove. Metal material is filled into the groove to form a second metal via. Insulating material is deposited in the region of the back-side transistor other than the back-side source-drain region to form the back-side interlayer dielectric layer of the back-side transistor (including a first back-side interlayer dielectric layer and a second back-side interlayer dielectric layer). Photolithography is used to open the back gate region of the back transistor. In the back gate region, an insulating material of a predetermined height is deposited above the second dielectric wall structure to form a second gate isolation structure. Next, the channel is released by removing the SiGe material layer from the second pillar structure, forming a back nanosheet structure (including a first back nanosheet structure and a second back nanosheet structure). Then, metal material is deposited in the back gate region to form a back gate structure (including a first back gate structure and a second back gate structure). Metal material is deposited on the back source / drain structure to form back source / drain metals (including a first back source / drain metal and a second back source / drain metal), which contact the second metal via. Subsequent processes are performed on the back interlayer dielectric layer and the back gate structure to form a back metal interconnect layer (including a first back metal interconnect layer and a second metal interconnect layer).

[0100] It should be noted that the second metal via may only contact the first back-side source / drain metal or the second back-side source / drain metal.

[0101] In some embodiments, a first power rail structure is connected to the source / drain structure of a front transistor or a back transistor; the first power rail structure is configured to provide a first voltage; a second power rail structure is connected to the source / drain structure of a back transistor or a front transistor; the second power rail structure is configured to provide a second voltage.

[0102] In some embodiments, after wafer flipping, before forming the second power rail structure, an insulating material of a predetermined height can be deposited on the surface of the first power rail structure away from the front transistor to form a first insulating layer.

[0103] Understandably, the second power rail structure is formed on top of the first insulating layer, which is located between the first power rail structure and the second power rail structure to isolate the first power rail structure and the second power rail structure.

[0104] In some possible implementations, the above method may further include: removing a pair of sacrificial structures to form a first groove; depositing insulating material in the first groove to form an intermediate isolation structure; the intermediate isolation structure being symmetrically distributed on both sides of the first power rail structure and the second power rail structure; the intermediate isolation structure being used to isolate the front transistor and the back transistor.

[0105] Understandably, during the formation of the front-side transistor or the back-side transistor, a pair of sacrificial structures can be removed to form a first groove between the first pillar structure and the second pillar structure; filling the first groove with insulating material can form an intermediate isolation structure. The intermediate isolation structure, together with the shallow trench isolation layer, serves to isolate the front-side transistor and the back-side transistor.

[0106] The fabrication process of the semiconductor structure will be explained below with reference to the flowchart shown in Figure 7 and the semiconductor structure shown in Figure 2.

[0107] In one example, taking a front-side transistor as a PMOS and a back-side transistor as an NMOS, with the first front-side transistor, the second front-side transistor, the first back-side transistor, and the second back-side transistor all being 2T structures, the semiconductor structure fabrication process may include the following steps:

[0108] Step 1: Provide a substrate and epitaxially stack a first layer, a sacrificial material layer, and a second layer on the substrate.

[0109] The substrate is made of Si material; the first stack is a stack formed by alternating deposition of SiGe material and Si material; the sacrificial material layer is made of SiGe material; the second stack is a stack formed by alternating deposition of SiGe material and Si material; the height of the sacrificial material layer can be greater than that of the SiGe material layer in the first stack and the second stack.

[0110] Step 2: Etch the first stack, the sacrificial material layer and the second stack to form a pair of first columnar structures, a pair of sacrificial structures and a pair of second columnar structures.

[0111] Step 3: Deposit insulating material on a pair of first columnar structures, a pair of sacrificial structures, a pair of second columnar structures, and a substrate to form a shallow trench isolation structure. The shallow trench isolation structure encloses the pair of first columnar structures, the pair of sacrificial structures, and the pair of second columnar structures, and covers the substrate.

[0112] Step 4: Remove the shallow trench isolation structure at a preset height until a pair of first columnar structures and a pair of sacrificial structures at a preset height are exposed. The height of the first sacrificial structure exposed is less than half its original height.

[0113] Step 5: Deposit a metal material of a predetermined height between a pair of columnar structures to form a first power rail structure, which is VDD in the semiconductor structure.

[0114] Step 6: Deposit dielectric material between the pair of first columnar structures and on top of the first power rail structure to form a first dielectric wall structure. The pair of first columnar structures are symmetrically distributed on both sides of the first dielectric wall structure.

[0115] Step 7: Based on the first pillar structure, form the front-side source / drain structure of the front-side transistor. Perform photolithography on the first dielectric wall structure located in the front-side source / drain region, etching to stop at the first power rail structure to form a groove; deposit metal material in the groove to form a first metal via. Form the front-side interlayer dielectric layer of the front-side transistor. In the gate region of the front-side transistor, deposit insulating material on the first dielectric wall structure to form a first gate isolation structure. Remove the SiGe material layer from the first pillar structure to form a front-side nanosheet structure. Form the front-side gate structure and the front-side metal interconnect layer of the front-side transistor.

[0116] Step 8: Deposit an insulating material of a predetermined height on the front-side metal interconnect layer to form a second insulating layer. Bond the second insulating layer to the carrier wafer.

[0117] Step 9: Flip the front-side transistors and remove the substrate.

[0118] Step 10: Remove the shallow trench isolation structure of the preset height until a pair of second columnar structures are exposed; retain the shallow trench isolation structure of the preset height as a shallow trench isolation layer.

[0119] Step 11: Deposit insulating material on the first power rail structure to form a first insulating layer; the first insulating layer is used to isolate the first power rail structure and the second power rail structure; then, deposit a metal material of a predetermined height between a pair of second columnar structures to form a second power rail structure, the second power rail structure being a VSS in a semiconductor structure.

[0120] Step 12: Deposit dielectric material between the pair of second columnar structures and on top of the second power rail structure to form a second dielectric wall structure. The pair of second columnar structures are symmetrically distributed on both sides of the second dielectric wall structure.

[0121] Step 13: Remove a pair of sacrificial structures to create a gap; fill the gap with insulating material to form an intermediate isolation structure.

[0122] Step 14: Based on a pair of second pillar structures, form the back-side transistor (refer to step 7).

[0123] At this point, the semiconductor structure has been successfully fabricated.

[0124] In some embodiments, this disclosure provides a semiconductor device including a plurality of semiconductor structures as described in the above embodiments. The definition of the semiconductor structure can be found in the semiconductor structure shown in FIG2 above.

[0125] In some embodiments, this disclosure provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiments, the semiconductor device being disposed on the circuit board. The semiconductor device includes the semiconductor structure described above. The definition of the semiconductor structure can be found in FIG2 above.

[0126] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0127] The above description is merely an exemplary embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, comprising: Front-facing transistor; The front-side transistor is a fork-shaped transistor, comprising a first front-side transistor and a second front-side transistor; Backside transistor; The back-side transistor is a fork-shaped transistor, including a first back-side transistor and a second back-side transistor; the front-side transistor and the back-side transistor are self-aligned in a direction perpendicular to the active region; A first dielectric wall structure; the first front-side transistor and the second front-side transistor are symmetrically arranged on both sides of the first dielectric wall structure; Second dielectric wall structure; the first back-side transistor and the second back-side transistor are symmetrically arranged on both sides of the second dielectric wall structure; First power rail structure; the first power rail structure is connected to the source / drain structure of the front transistor or the source / drain structure of the back transistor. The first power rail structure is configured to provide a first voltage; Second power rail structure; The second power rail structure is connected to the source / drain structure of the back transistor or the source / drain structure of the front transistor. The second power rail structure is configured to provide a second voltage; The first power rail structure and the second power rail structure are stacked between the first dielectric wall structure and the second dielectric wall structure; the orthographic projections of the first power rail structure and the second power rail structure overlap.

2. The semiconductor structure according to claim 1, wherein, The front-side transistor is a first-type transistor, and the back-side transistor is a second-type transistor; The first power rail structure is connected to the front source and drain metal of the front transistor through a first metal via disposed in the first dielectric wall structure. The second power rail structure is connected to the first back source / drain metal of the first back transistor or the second back source / drain metal of the second back transistor through a second metal via disposed in the second dielectric wall structure.

3. The semiconductor structure according to claim 1, wherein, The front-side transistor is a second-type transistor, and the back-side transistor is a first-type transistor; The second power rail structure is connected to the first front source / drain metal of the first front transistor or the second front source / drain metal of the second front transistor through a first metal through-hole disposed in the first dielectric wall structure. The first power rail structure is connected to the back source / drain metal of the back transistor through a second metal via disposed in the second dielectric wall structure.

4. The semiconductor structure according to claim 1, wherein, The semiconductor structure also includes: At least four first metal interconnects; the first metal interconnects are disposed in the front-side transistor; the first metal interconnects are formed by a back-end process. At least four second metal interconnects are disposed in the back-side transistor; the second metal interconnects are formed by the back-end process.

5. The semiconductor structure according to claim 1, wherein, An intermediate isolation structure is provided between the front transistor and the back transistor; the intermediate isolation structure is symmetrically distributed on both sides of the first power rail structure and the second power rail structure. The intermediate isolation structure is used to isolate the front transistor and the back transistor.

6. A method for fabricating a semiconductor structure, the method comprising: A pair of first columnar structures, a pair of sacrificial structures, and a pair of second columnar structures are sequentially formed on the substrate from top to bottom; A metal material of a predetermined height is deposited in a first region to form a first power rail structure; the first region is located between the pair of sacrificial structures; A front-side transistor is formed based on the pair of first columnar structures; The front-side transistor is a fork-shaped transistor, comprising a first front-side transistor and a second front-side transistor; The wafer is then poured and the substrate is removed. A metal material of a predetermined height is deposited in a second region to form a second power rail structure; the second region is located between the pair of sacrificial structures. A back-side transistor is formed based on the pair of second columnar structures; the back-side transistor is a fork-shaped transistor, including a first back-side transistor and a second back-side transistor; The first power rail structure is connected to the source / drain structure of the front transistor or the source / drain structure of the back transistor; the first power rail structure is configured to provide a first voltage; the second power rail structure is connected to the source / drain structure of the back transistor or the source / drain structure of the front transistor; and the second power rail structure is configured to provide a second voltage.

7. The method according to claim 6, wherein, The method further includes: Remove the pair of sacrificial structures to form the first groove; An insulating material is deposited in the first groove to form an intermediate isolation structure; the intermediate isolation structure is symmetrically distributed on both sides of the first power rail structure and the second power rail structure; the intermediate isolation structure is used to isolate the front transistor and the back transistor.

8. The method according to claim 6, wherein, The method further includes: A dielectric material is deposited between the pair of first columnar structures to form a first dielectric wall structure; the first front-side transistor and the second front-side transistor are symmetrically disposed on both sides of the first dielectric wall structure; A dielectric material is deposited between the pair of second columnar structures to form a second dielectric wall structure; the first back-side transistor and the second back-side transistor are symmetrically arranged on both sides of the second dielectric wall structure.

9. A semiconductor device, comprising: Multiple semiconductor structures as described in any one of claims 1 to 5.

10. An electronic device, comprising: The circuit board and the semiconductor device as described in claim 9, wherein the semiconductor device is disposed on the circuit board.

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