Chip, preparation method, and electronic device

Abstract

Provided in the embodiments of the present application are a chip, a preparation method, and an electronic device. The chip comprises: a substrate and a long-channel transistor. The long-channel transistor is arranged on the substrate, and the long-channel transistor comprises a fin structure Fin, a source electrode, a drain electrode, a first spacer layer, a gate-all-around and a second spacer layer, wherein the source electrode and the drain electrode are arranged on the same side of the fin structure, or are respectively arranged on different sides of the fin structure, and a projection of the source electrode on the substrate does not overlap with a projection of the drain electrode on the substrate; in a direction parallel to the substrate, the first spacer layer, the gate-all-around and the second spacer layer are all arranged around the fin structure; and in a direction perpendicular to the substrate, the first spacer layer, the gate-all-around and the second spacer layer are sequentially stacked. The implementation of the embodiments of the present application can be compatible with a preparation process of short-channel transistors, and achieve good performance.

Description

A chip, a fabrication method, and an electronic device

[0001] This application claims priority to Chinese Patent Application No. 202410940398.0, filed on July 12, 2024, with the China National Intellectual Property Administration, entitled “A Chip, Preparation Method and Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and more particularly to a chip, a fabrication method, and an electronic device. Background Technology

[0003] With the development of technology, Vertical Transport Field Effect Transistors (VTFETs) define the critical dimension of the transistor in the vertical direction, decoupling the limitation of transistor size imposed by the Contact Gate Pitch (CGP), thereby significantly reducing the parasitic capacitance of the transistor, and thus improving chip performance and reducing chip power consumption.

[0004] In chips based on vertical transfer field-effect transistors (VTFETs), long-channel transistors can be used in digital-to-analog / analog-to-digital conversion scenarios or as transistor amplifiers, making them a core component in analog circuits. Current long-channel transistor configurations often consist of two vertical gate rings and one planar gate-controlled region, which has a significant performance disadvantage compared to full-gate ring transistors.

[0005] Therefore, how to provide a high-performance transistor is an urgent problem to be solved. Summary of the Invention

[0006] This application provides a chip, a fabrication method, and an electronic device. The long-channel transistor in the chip is compatible with the fabrication process of vertical transmission short-channel transistors and has good performance.

[0007] In a first aspect, embodiments of this application provide a chip, which includes a substrate and a long-channel transistor. The long-channel transistor is disposed on the substrate and includes a fin structure (Fin), a source, a drain, a first spacer layer, a ring gate, and a second spacer layer. The source and the drain are respectively disposed on the same side or different sides of the fin structure, and the projection of the source on the substrate does not overlap with the projection of the drain on the substrate. In a direction parallel to the substrate, the first spacer layer, the ring gate, and the second spacer layer are all disposed around the fin structure. In a direction perpendicular to the substrate, the first spacer layer, the ring gate, and the second spacer layer are stacked sequentially.

[0008] The long-channel transistors mentioned in this application can have mutually insulated source and drain electrodes formed on the top of the fin structure, or alternatively, source and drain electrodes spaced apart from each other can be formed on different sides of the fin structure. These different arrangements can meet different circuit design requirements. Regardless of whether the source and drain electrodes are located on the same or different sides of the fin structure, their projections onto the substrate do not overlap. In this case, the distance between the source and drain electrodes can be understood as the length of the channel (carrier movement) in the gate control region. Furthermore, the channel length of the long-channel transistor can be directly controlled by adjusting the distance between the source and drain electrodes in each of these different arrangements. In the embodiments of this application, the gate control region of the long-channel transistors with different configurations is composed of a single fin structure and a full-ring gate. The vertical metal ring gate surrounding the fin structure constitutes the gate control region. This ring gate surrounding the fin structure, compared to the existing long-channel transistors where the gate control region consists of two vertical ring gates corresponding to two fin structures and one planar gate control region, enhances the gate control capability, provides better electrical control of the channel, and thus better controls the movement of charge carriers in the channel, greatly improving device performance and reducing fabrication and circuit design complexity. Furthermore, in these different configurations, the top of the fin structure of the long-channel transistor is separated from the source and drain by a first spacer layer formed of insulating material, controlling the parasitic capacitance of the long-channel transistor and further improving device performance. Most importantly, since current short-channel transistors are also VTFETs formed by a single fin structure, which is similar to the long-channel transistor structure mentioned in the embodiments of this application, the fabrication process of the long-channel transistor mentioned in the embodiments of this application can be compatible with the fabrication process of current vertical transmission short-channel transistors, which greatly saves the fabrication cost and solves the problem that the fabrication processes of long-channel transistors and short-channel transistors for current vertical transmission field-effect transistors are difficult to be compatible.

[0009] In one possible implementation, the source and drain are spaced apart on the side of the fin structure away from the substrate.

[0010] In this embodiment, a source and drain that are mutually insulated are formed on the top of the fin structure. The channel length of the long-channel transistor in the chip is controlled by the horizontal spacing between the source and drain. Compared with the length control based on two vertical ring gates and one planar gate control area in the prior art, this greatly reduces the difficulty of process and circuit design.

[0011] In one possible implementation, both the source and the drain include a first region, the projection of the first region onto the substrate overlaps with the projection of the ring gate onto the substrate; the first spacer layer includes a first spacer region, which is disposed between the first region and the ring gate in a direction perpendicular to the substrate.

[0012] In this embodiment, a portion of the source and drain are disposed above the fin structure, and another portion is disposed on the first spacing region of the first spacer layer. This arrangement ensures that the distance between the source and drain is sufficiently long to meet the channel length requirements of the device, even when the fin structure is short, thus ensuring device performance. The first spacing region completely isolates the first region from the gate ring, thereby improving device reliability.

[0013] In one possible implementation, the first spacer layer further includes a second spacer region surrounding the first spacer region, the source electrode, and the drain electrode; and the material forming the first spacer region in the first spacer layer is different from the material forming the second spacer region.

[0014] In this embodiment, the first spacer layer further includes a second spacer region surrounding the first spacer region, the source electrode, and the drain electrode, to support and insulate the subsequently fabricated contact electrode from the source electrode and the drain electrode. Furthermore, the material forming the first spacer region is different from the material forming the second spacer region, which prevents etching of the first spacer region during the subsequent fabrication of the contact electrode for the second spacer region, thereby preventing leakage caused by contact between the source electrode or drain electrode and the gate ring.

[0015] In one possible implementation, a third spacer layer is provided between the source and the drain on the surface of the fin structure away from the substrate.

[0016] In this embodiment of the application, in order to isolate the source and drain and avoid short circuits in the device, a third spacer layer formed of insulating material may be provided between the source and drain.

[0017] In one possible implementation, the source electrode is disposed on the side of the fin structure close to the substrate and embedded inside the substrate, and the drain electrode is disposed on the side of the fin structure away from the substrate; or, the drain electrode is disposed on the side of the fin structure close to the substrate and embedded inside the substrate, and the source electrode is disposed on the side of the fin structure away from the substrate.

[0018] In this embodiment, the source and drain can be located on opposite sides of the fin structure. The channel length of the long-channel transistor in the chip is controlled by the spacing between the source and drain. For example, when the horizontal spacing between the source and drain is less than the vertical spacing, the channel length can be dominated by the vertical spacing; when the horizontal spacing between the source and drain is greater than the vertical spacing, the channel length can be dominated by the horizontal spacing. Compared to the length control based on two vertical ring gates and one planar gate control region in the prior art, this significantly reduces the difficulty of the manufacturing process and circuit design. Moreover, the fabrication process when the source and drain are located on different sides is more compatible with the current fabrication process of vertical transmission short-channel transistors, greatly saving fabrication costs.

[0019] In one possible implementation, in a direction perpendicular to the substrate, both the source and the drain include a first region, the projection of the first region onto the substrate overlapping the projection of the ring gate onto the substrate; the first spacer layer includes a first spacer region, and when the source is disposed on the side of the fin structure close to the substrate, in a direction perpendicular to the substrate, the first spacer region is disposed between the first region in the drain and the ring gate; a second spacer layer is disposed between the first region in the source and the ring gate.

[0020] In this embodiment, when the source is located at the bottom of the fin structure and the drain is located at the top of the fin structure, a portion of the bottom source is in contact with the second spacer layer, and another portion is in contact with the fin structure; a portion of the top drain is located above the fin structure, and another portion is located on the first spacer region of the first spacer layer. This arrangement ensures that the horizontal spacing between the source and drain is sufficiently long when the fin structure length is short, to meet the channel length of the device and ensure device performance. The first spacer region can completely isolate the first region and the gate ring to improve device reliability.

[0021] In one possible implementation, the first spacer layer further includes a second spacer region surrounding the first spacer region and the drain electrode; and the material forming the first spacer region in the first spacer layer is different from the material forming the second spacer region.

[0022] In this embodiment, when the source electrode is located at the bottom of the fin structure and the drain electrode is located at the top of the fin structure, the second spacer region in the first spacer layer can be disposed around the first spacer region and the top drain electrode to support and insulate the subsequently fabricated contact electrode from the drain electrode. Furthermore, the material forming the first spacer region is different from the material forming the second spacer region, which can prevent etching of the first spacer region during the subsequent fabrication of the contact electrode for the second spacer region, thereby preventing leakage caused by contact between the drain electrode and the gate ring.

[0023] In one possible implementation, the thickness of the first spacing region in the direction perpendicular to the substrate is greater than or equal to 5 nm and less than or equal to 50 nm.

[0024] In this embodiment, to control the parasitic capacitance of the long-channel transistor in the chip, the thickness of the first spacing region can be between 5 and 50 nm. A larger thickness of the first spacing region results in a smaller parasitic capacitance and a correspondingly smaller on-state current of the device; conversely, a smaller thickness of the first spacing region results in a larger parasitic capacitance and a correspondingly larger on-state current of the device. Therefore, a thickness value between 5 and 50 nm can be selected according to different circuit design requirements to ensure the performance of the long-channel transistor while meeting the varying requirements of different long-channel transistors for parasitic capacitance or on-state current.

[0025] In one possible implementation, the thickness of the first spacing region in the direction perpendicular to the substrate is greater than or equal to 10 nm and less than or equal to 20 nm.

[0026] In this embodiment of the application, in order to reduce the parasitic capacitance of the long-channel transistor in the chip while meeting the device’s requirements for on-state current, the thickness of the first spacing region can be set between 10-20 nm.

[0027] In one possible implementation, the thickness of the ring gate in the first direction is greater than or equal to the thickness of the first spacing region in the first direction; the length of the ring gate in the second direction is greater than or equal to the length of the first spacing region in the second direction, and the second direction is perpendicular to the first direction and parallel to the substrate.

[0028] In this embodiment, a ring gate is disposed around the four sidewalls of the fin structure. To ensure that the ring gate can properly connect to the contact electrodes and achieve gate control, the thickness of the ring gate in the first direction can be greater than or equal to the thickness of the first spacing region in the first direction. To ensure effective gate control, the length of the ring gate in the second direction can be greater than or equal to the length of the first spacing region in the second direction.

[0029] In one possible implementation, the spacing between the source and the drain is less than the length of the fin structure in the first direction, parallel to the first direction; and, when the source and the drain are disposed on the same side of the fin structure, the spacing between the source and the drain in the first direction is greater than or equal to 20 nm.

[0030] In this embodiment, the distance between the source and drain along the first direction can be less than the length of the fin structure along the first direction. For example, when the source and drain are on the same side, they can be entirely disposed above the fin structure, or partially disposed above the fin structure. The distance between the source and drain can be greater than or equal to 20 nm, and this distance is the channel length of the long-channel transistor. In this case, the channel length can be adjusted by adjusting the distance between the source and drain along the first direction. Furthermore, when the source and drain are on different sides, since the distance between the source and drain in the direction perpendicular to the substrate is the same as the height of the fin structure, the distance between the source and drain in the first direction is greater than 0 nm, which satisfies the channel length requirement of the long-channel transistor.

[0031] In one possible implementation, the length of the fin structure in the first direction is greater than or equal to 20 nm and less than or equal to 1 μm; the height of the fin structure in the direction perpendicular to the substrate is greater than or equal to 20 nm and less than or equal to 100 nm.

[0032] In this embodiment, the length of the fin structure in the first direction is between 20 nm and 1 μm, and the height in the direction perpendicular to the substrate is between 20 and 100 nm. The specific length and height of the fin structure can be determined according to the requirements of the circuit design. The longer and higher the fin structure, the longer the spacing between the source and drain can be set, and the longer the channel length of the long-channel transistor can be. The reliability of the long-channel transistor is better. Moreover, compared with short-channel transistors, long-channel transistors are better suited for high-operating-voltage applications, making them suitable for various digital-to-analog / analog-to-digital conversion scenarios, such as being used as input / output devices or as transistor amplifiers.

[0033] In one possible implementation, a high dielectric constant dielectric layer and a gate oxide dielectric layer are disposed between the aforementioned ring gate and the aforementioned fin structure, wherein the high dielectric constant dielectric layer is located between the aforementioned ring gate and the aforementioned gate oxide dielectric layer.

[0034] In the embodiments of this application, the high dielectric constant dielectric layer formed by the high dielectric constant material can reduce the thickness of the equivalent oxide thickness (EOT) of the long channel transistor in the chip.

[0035] In one possible implementation, the source and drain electrodes described above are of the same type of heavy doping, and the doping concentration corresponding to the heavy doping is greater than or equal to 10. 20 cm -3 and less than or equal to 10 22 cm -3 .

[0036] In the embodiments of this application, both the source and drain are heavily doped of the same type, for example, both are heavily doped with N-type or P-type doping, so that carriers can move when a voltage is applied to the gate ring. The doping concentrations of the source and drain can be the same or different.

[0037] Secondly, embodiments of this application provide a method for fabricating a chip, the method comprising: forming a fin structure Fin, a source electrode, and a drain electrode on a substrate, wherein, in a direction perpendicular to the substrate, the source electrode and the drain electrode are respectively disposed on the same side or different sides of the fin structure, and the projection of the source electrode on the substrate does not overlap with the projection of the drain electrode on the substrate; sequentially depositing and forming a second spacer layer, a ring gate, and a first spacer layer around the fin structure; wherein, in a direction parallel to the substrate, the first spacer layer is disposed around the fin structure, the ring gate is disposed around the fin structure, and the second spacer layer is disposed around the fin structure; and in a direction perpendicular to the substrate, the first spacer layer, the ring gate, and the second spacer layer are sequentially stacked.

[0038] In one possible implementation, when the source and drain are disposed on the same side of the fin structure perpendicular to the substrate, the fabrication of the fin structure Fin, the source, and the drain on the substrate includes: fabricating the fin structure Fin on the substrate and depositing a first dielectric layer on the surface of the fin structure away from the substrate; after sequentially depositing a second spacer layer, a ring gate, and a first spacer layer around the fin structure, etching the surface of the first dielectric layer away from the substrate to form a first opening and a second opening, fabricating a source at the first opening and a drain at the second opening; wherein the projections of the first opening and the second opening on the substrate do not overlap, the bottom of both the first opening and the second opening exposes the fin structure, and the sidewalls of both the first opening and the second opening expose the first spacer layer.

[0039] In one possible implementation, when the source and drain are disposed on different sides of the fin structure perpendicular to the substrate, the fabrication of the fin structure, source, and drain on the substrate includes: fabricating the source and fin structure on the substrate, and depositing a first dielectric layer on the surface of the fin structure away from the substrate; wherein the source is embedded inside the substrate, and a portion of the fin structure near the substrate is connected to the source; after sequentially depositing a second spacer layer, a ring gate, and a first spacer layer around the fin structure, etching the surface of the first dielectric layer away from the substrate to form a third opening, and fabricating a drain at the third opening; wherein the projection of the third opening onto the substrate does not overlap with the source, the bottom of the third opening exposes the fin structure, and the sidewalls of the third opening expose the first spacer layer.

[0040] In one possible implementation, the sequential deposition of a second spacer layer, a ring gate, and a first spacer layer around the fin structure includes: depositing a second spacer layer around the sidewall of the fin structure; sequentially depositing a gate oxide dielectric layer, a high dielectric constant dielectric layer, and the ring gate around the sidewall of the fin structure on the second spacer layer, wherein the high dielectric constant dielectric layer is located between the ring gate and the gate oxide dielectric layer; and depositing the first spacer layer around the sidewall of the fin structure and the first dielectric layer on the gate oxide dielectric layer, the high dielectric constant dielectric layer, and the ring gate.

[0041] In one possible implementation, the first spacer layer includes a first spacer region and a second spacer region, the first spacer region being disposed between the second spacer region and the fin structure, and between the second spacer region and the first dielectric layer.

[0042] Thirdly, embodiments of this application provide an electronic device, including a circuit board and a chip as provided in the first aspect above, applied to the circuit board.

[0043] It should be understood that the chip fabrication method provided in the second aspect of this application and the electronic device provided in the third aspect are consistent with the technical solution of the first aspect of this application. Their specific contents and beneficial effects can be referred to the chip provided in the first aspect above, and will not be repeated here. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0045] Figure 1 is a schematic diagram of the structure of a long-channel transistor and a short-channel transistor in the prior art provided in an embodiment of this application.

[0046] Figure 2 is a schematic diagram of the structure of a chip provided in an embodiment of this application.

[0047] Figure 3 is a cross-sectional schematic diagram of the chip shown in Figure 2 along a first direction provided by an embodiment of this application.

[0048] Figure 4 is another cross-sectional schematic diagram of the chip shown in Figure 2 along the first direction provided by an embodiment of this application.

[0049] Figure 5 is a cross-sectional schematic diagram along the first direction based on the chip shown in Figure 2, provided by an embodiment of this application.

[0050] Figure 6 is a schematic diagram of another chip structure provided in an embodiment of this application.

[0051] Figures 7 and 8 are a set of cross-sectional schematic diagrams along the first direction based on the chip shown in Figure 6, provided by embodiments of this application.

[0052] Figure 9 is a cross-sectional schematic diagram of the chip shown in Figure 6 along a first direction, provided by an embodiment of this application.

[0053] Figure 10 is a set of schematic diagrams based on the chip shown in Figure 2 along the second direction provided in an embodiment of this application.

[0054] Figure 11 is another set of cross-sectional schematic diagrams along the second direction based on the chip shown in Figure 6, provided by an embodiment of this application.

[0055] Figure 12 is another cross-sectional schematic diagram of the chip shown in Figure 6 along the first direction provided by an embodiment of this application.

[0056] Figure 13 is a cross-sectional schematic diagram comparing a set of long-channel transistors and short-channel transistors provided in an embodiment of this application.

[0057] Figure 14 is a flowchart of a chip fabrication method provided in an embodiment of this application.

[0058] Figures 15-22 are schematic cross-sectional views of a set of fabricated chips provided in the embodiments of this application.

[0059] Figure 23 is a flowchart of another chip fabrication method provided in an embodiment of this application.

[0060] Figures 24-31 are schematic cross-sectional views of a set of fabricated chips provided in the embodiments of this application. Detailed Implementation

[0061] The embodiments of this application will now be described with reference to the accompanying drawings.

[0062] The terms "first" and "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0063] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0064] For ease of description, embodiments of this application may use spatial relation terms such as "below," "below," "lower than," "below," "above," "upper," etc., to describe the relationship between an element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings. For example, if the device in the drawings is flipped, the orientation of an element described as "below," "below," or "below" other elements or features will change to "above" said other elements or features. Thus, the exemplary terms "below" and "below" can encompass both up and down directions. The device may also have other orientations (rotated 90 degrees or in other orientations), and therefore the spatial relation descriptors used herein should be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there may be one or more layers in between.

[0065] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0066] First, to facilitate understanding of the embodiments of this application, the following detailed analysis addresses the technical problems to be solved and the applicable application scenarios of the embodiments of this application.

[0067] With the development of technology, Vertical Transport Field Effect Transistors (VTFETs) define the critical dimension of transistors in the vertical direction, decoupling the size limitations of Contact Gate Pitch (CGP) transistors. This significantly reduces the parasitic capacitance of transistors, improves chip performance, and reduces chip power consumption.

[0068] Currently, chips based on vertical transmission field-effect transistors (VT-FETs) typically include chips composed of long-channel transistors and short-channel transistors. Please refer to Figure 1, which is a schematic diagram of the structure of a long-channel transistor and a short-channel transistor in the prior art provided by an embodiment of this application. As shown in Figure 1, the current vertical transmission long-channel transistor is composed of two fin structures, while the vertical transmission short-channel transistor is composed of a single fin structure; the structures of the two transistors differ significantly. The gate control region of the short-channel transistor is composed of a full-ring gate control region, resulting in good performance. The gate control region of the long-channel transistor consists of two vertical gate control regions and one planar gate control region. This combination allows for the horizontal extension of the channel length without increasing the device height. However, the inclusion of a planar gate control region in the gate control region of this long-channel transistor structure results in poorer performance compared to a full-ring gate long-channel transistor, affecting chip performance.

[0069] To address this, this application provides a chip including high-performance transistors. When the transistor is a long-channel transistor, it is also well-compatible with the current fabrication process of vertical transmission short-channel transistors. For example, the gate control region of the transistor in the chip provided in this application can be composed of a single fin structure and a full-ring gate. That is, the area surrounded by the ring gate in the fin structure is the gate control region. This full-ring gate transistor structure enhances the gate control capability, allowing for better control of carrier movement in the channel, significantly improving device performance, and thus enhancing chip performance. Moreover, the transistor structure in this chip is similar to that of vertical transmission short-channel transistors, making it compatible with the fabrication process of short-channel transistors and greatly saving fabrication costs. Furthermore, this long-channel transistor can be applied in digital-to-analog / analog-to-digital conversion scenarios in chips, or as a transistor amplifier, and is a core component in analog circuits. The specific structure of the long-channel transistor can be referred to the relevant descriptions in the following related embodiments, which will not be repeated here.

[0070] Secondly, based on the technical problems mentioned above, and in order to facilitate understanding of the embodiments of this application, several types of chips on which the embodiments of this application are based will be described below.

[0071] This application provides a chip including a substrate and a long-channel transistor disposed on the substrate. The long-channel transistor includes a fin structure (Fin), a source, a drain, a first spacer layer, a ring gate, and a second spacer layer disposed on the substrate. The source and drain can be disposed on the same side or different sides of the fin structure, and the projections of the source and drain on the substrate do not overlap. In the direction parallel to the substrate, the first spacer layer, the ring gate, and the second spacer layer surround the fin structure; and in the direction perpendicular to the substrate, the first spacer layer, the ring gate, and the second spacer layer are stacked sequentially.

[0072] For example, the source and drain can be respectively arranged at intervals on the same side of the fin structure.

[0073] In some embodiments, please refer to Figure 2, which is a schematic diagram of the structure of a chip provided in an embodiment of this application. As shown in Figure 2, an embodiment of this application provides a chip including: a substrate 10 and a long-channel transistor 20. The long-channel transistor 20 is disposed on the substrate 10 and includes a fin structure 101, a source 102, a drain 103, a first spacer layer 104, a ring gate 105, and a second spacer layer 106.

[0074] The fin structure 101 is disposed on the substrate 10. On the surface of the fin structure 101 away from the substrate 10, the source electrode 102 and the drain electrode 103 are disposed at intervals. In the direction parallel to the substrate 10, the first spacer layer 104, the ring gate 105, and the second spacer layer 106 are all disposed around the fin structure 101, that is, around the four sidewalls of the fin structure 101. In the direction perpendicular to the substrate, the first spacer layer 104, the ring gate 105, and the second spacer layer 106 are stacked sequentially. The ring gate 105 can be made of a work function metal, such as titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbon (TiAlC), titanium aluminum (TiAl), or tungsten (W). The work function metal can adjust the effective work function of the metal ring gate 105 to regulate the threshold voltage, which helps improve the performance of long-channel transistors in the chip. In addition, the material forming the first spacer layer 104 or the second spacer layer 106 can be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0075] It should be noted that in the embodiments of this application and the following related embodiments, the extension direction of the fin structure (i.e., the long side direction) is taken as the first direction, that is, the Y-axis direction as shown in Figure 2, which is also the front-back direction parallel to the surface of the substrate 10 as shown in Figure 2. The direction parallel to the surface of the substrate 10 and perpendicular to the first direction is taken as the second direction, that is, the X-axis direction as shown in Figure 2, which is also the left-right direction parallel to the surface of the substrate 10 as shown in Figure 2. The direction perpendicular to the surface of the substrate 10 as shown in Figure 2 is taken as the third direction, that is, the Z-axis direction as shown in Figure 2. Among them, the first direction, the second direction, and the third direction are perpendicular to each other.

[0076] As shown in Figure 2 above, source electrodes 102 and drain electrodes 103 are spaced apart along a first direction on the upper surface of the fin structure 101. A ring gate surrounds the fin structure 101 to achieve gate control. After applying a gate voltage, charge carriers can move within the fin structure. Referring to Figure 3, which is a cross-sectional schematic diagram along the first direction of the chip shown in Figure 2 according to an embodiment of this application, as shown in Figure 3, the spacing length G between the source electrodes 102 and drain electrodes 103 along the first direction is the channel length of the long-channel transistor in the chip. Furthermore, the relative positions of the source electrodes 102 and drain electrodes 103 can be interchanged; however, this embodiment does not specifically limit this. The fin structure 101 is a tall and thin fin-shaped semiconductor protruding on the surface of the substrate 10. In this embodiment, the structure in which the ring gate 105 surrounds and encloses the fin structure 101 enhances the gate control capability compared to the long channel transistor in the prior art, which consists of two vertical ring gates and a planar gate control region corresponding to two fin structures (Fin), respectively. This provides better electrical control of the channel, thereby better controlling the movement of charge carriers in the channel, greatly improving device performance, and reducing the difficulty of process and circuit design.

[0077] In some embodiments, the spacing between the source and the drain is less than the length of the fin structure in the first direction when parallel to the first direction, and when the source and the drain are disposed on the same side of the fin structure, the spacing between the source and the drain in the first direction is greater than or equal to 20 nm.

[0078] As shown in Figure 3 above, along the first direction, the spacing G between the source 102 and the drain 103 is less than the length L1 of the fin structure 101 in the first direction. It can be understood that the source 102 and the drain 103 are formed from heavily doped semiconductors, and part or all of the source 102 and the drain 103 can be disposed on one side of the fin structure 101. Therefore, the spacing G between the source 102 and the drain 103 is less than the length L1 of the fin structure 101 in the first direction. Furthermore, it can be understood that the channel length of this long-channel transistor is determined by the spacing G between the source 102 and the drain 103. In addition, to ensure that the channel length of the long-channel transistor meets device requirements, the spacing G between the source 102 and the drain 103 can also be greater than or equal to 20 nm.

[0079] In some embodiments, both the source 102 and the drain 103 include a first region. The projection of the first region onto the substrate 10 overlaps with the projection of the ring gate 105 onto the substrate 10. The first spacer layer 104 includes a first spacer region, which is disposed between the first region and the ring gate 105 in a direction perpendicular to the substrate. Referring to Figure 4, which is a cross-sectional view along a first direction based on the chip shown in Figure 2 according to an embodiment of this application, as shown in Figure 4, in a direction perpendicular to the substrate, the projection of the first region 1021 of the source 102 onto the substrate 10 overlaps with the projection of the ring gate 105 onto the substrate 10, and the projection of the first region 1031 of the drain 103 onto the substrate 10 overlaps with the projection of the ring gate 105 onto the substrate 10. The first spacer layer 104 includes a first spacer region 1041, which is disposed between the first region 1021 and the ring gate 105 in a direction perpendicular to the substrate (i.e., the Z-axis direction).

[0080] That is, a portion of the source 102 is disposed above the fin structure 101, and another portion (i.e., the first region 1021 of the source 102) is disposed on the first spacer region 1041 of the first spacer layer 104. A portion of the drain 103 is disposed above the fin structure 101, and another portion (i.e., the first region 1031 of the drain 103) is disposed on the first spacer region 1041 of the first spacer layer 104. It can be understood that the first spacer region 1041 is stacked on the ring gate 105 and can surround the fin structure 101. This arrangement ensures that the distance between the source and drain is sufficiently long when the fin structure length is short, to meet the channel length of the device and ensure device performance. The first spacer region can completely isolate the first region and the ring gate to improve device reliability.

[0081] In other embodiments, the first spacing region 1041 may be disposed only between the source 102 and the ring gate 105, and between the drain 103 and the ring gate 105; this embodiment of the present application does not specifically limit this. The first spacing region 1041 can separate the electrical connections between the ring gate and the source and drain, thereby reducing the parasitic capacitance of the long-channel transistor in the chip and improving device performance.

[0082] In some embodiments, the first spacer layer 104 further includes a second spacer region 1042, which surrounds the first spacer region 1041, the source 102, and the drain 103; and the material forming the first spacer region 1041 in the first spacer layer 104 is different from the material forming the second spacer region 1042.

[0083] As shown in Figure 4 above, the second spacer region 1042 is located on the sidewall surrounding the first spacer region 1041, the source electrode 102, and the drain electrode 103. The thickness H2 of the second spacer region 1042 in the direction perpendicular to the substrate can be greater than or equal to the thickness H1 of the first spacer region 1041, and less than or equal to the sum of the thickness H1 of the first spacer region 1041 and the thickness of the source electrode 102. Furthermore, it is understood that since contact electrodes need to be inserted into the source electrode 102, drain electrode 103, and gate ring 105 to connect the circuit during subsequent fabrication processes, the material forming the first spacer region 1041 in the first spacer layer 104 is different from the material forming the second spacer region 1042 to simplify the fabrication process. Moreover, using a different material for the first spacer region 1041 and the second spacer region 1042 can meet the requirements of subsequent fabrication processes, avoiding etching the first spacer region during the subsequent fabrication of contact electrodes for the second spacer region, which could cause leakage due to contact between the source or drain electrode and the gate ring.

[0084] In some embodiments, in the direction perpendicular to the substrate, i.e., the Z-axis direction, as shown in FIG. 4 above, the thickness H1 of the first spacing region 1041 is greater than or equal to 5 nm and less than or equal to 50 nm. That is, in order to control the parasitic capacitance of the long-channel transistor in the chip, the thickness H1 of the first spacing region 1041 can be between 5 and 50 nm. The larger the thickness of the first spacing region, the smaller its parasitic capacitance; the smaller the thickness of the first spacing region, the larger its parasitic capacitance. However, the smaller the thickness of the first spacing region, the larger the on-state current of the device. Therefore, for the performance of the device, the thickness H1 of the first spacing region 1041 can be adaptively selected according to the circuit design requirements while meeting the different requirements of different long-channel transistors for parasitic capacitance or on-state current. This embodiment of the application does not specifically limit this.

[0085] In other embodiments, the thickness H1 of the first spacing region 1041 in the direction perpendicular to the substrate is greater than or equal to 10 nm and less than or equal to 20 nm. For example, when the thickness H1 of the first spacing region 1041 is between 10 and 20 nm, better device performance can be obtained while satisfying the parasitic capacitance of long-channel transistors in the chip.

[0086] In some embodiments, a third spacer layer 107 is further disposed between the source 102 and the drain 103 on the surface of the fin structure 101 away from the substrate 10. Referring to Figure 5, which is a cross-sectional schematic diagram along a first direction based on the chip shown in Figure 2 according to another embodiment of this application, as shown in Figure 5, a third spacer layer 107 formed of insulating material can also be disposed between the source 102 and the drain 103. This third spacer layer 107 can be used to separate the source 102 and the drain 103, preventing short circuits in the device. It is understood that the material of the third spacer layer 107 can be the same as or different from that of the first spacer layer 104 and the second spacer layer 106, for example, it can include silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide.

[0087] In some embodiments, the length L1 of the fin structure 101 in the first direction is between 20 nm and 1 μm, that is, the length L1 of the fin structure 101 in the first direction (i.e., the Y-axis direction) is greater than or equal to 20 nm and less than or equal to 1 μm. It should be noted that the specific size of the fin structure length L1 can be determined according to the requirements of the circuit design. The longer the fin structure, the longer the spacing between the source and drain can be set, and thus the longer the channel length can be. Long-channel transistors have better reliability, and compared to short-channel transistors, they are better suited for high-voltage applications, making them suitable for various digital-to-analog / analog-to-digital conversion scenarios, such as input / output devices or transistor amplifiers. For example, when the fin structure length L1 is 100 nm, the spacing G between the source 102 and drain 103 can be less than 100 nm at most, but when the fin structure length L1 is 50 nm, the spacing G between the source 102 and drain 103 can only be less than 50 nm at most.

[0088] In other embodiments, the height H3 of the fin structure 101 in the direction perpendicular to the substrate can be between 20nm and 100nm. It should be noted that when the source 102 and drain 103 are on the same side, the height H3 of the fin structure has no significant effect on the channel length of the long channel transistor. Therefore, the specific size of the fin structure height H3 can be determined according to the requirements of the circuit design. This application does not make specific limitations on this.

[0089] In addition, the long-channel transistors in the chip mentioned in this application embodiment can form mutually insulated source and drain electrodes on the top of the fin structure, or they can form mutually spaced source and drain electrodes on different sides of the fin structure. These different arrangements can meet different circuit design requirements.

[0090] For example, the source 102 and drain 103 of the long-channel transistor can be disposed at intervals on different sides of the fin structure 101.

[0091] In some embodiments, for example, the source 102 is disposed on the side of the fin structure 101 near the substrate 10 and embedded inside the substrate 10, and the drain 103 is disposed on the side of the fin structure 101 away from the substrate 10; or, the drain 103 is disposed on the side of the fin structure 101 near the substrate 10 and embedded inside the substrate 10, and the source 102 is disposed on the side of the fin structure 101 away from the substrate 10. In this case, the channel length of the long-channel transistor in the chip is controlled by the spacing between the source 102 and the drain 103. For example, when the horizontal spacing between the source 102 and the drain 103 is less than the vertical spacing, the channel length can be mainly controlled by the vertical spacing between the source 102 and the drain 103; when the horizontal spacing between the source 102 and the drain 103 is greater than the vertical spacing, the channel length can be mainly controlled by the horizontal spacing between the source 102 and the drain 103.

[0092] The structure of the chip will be described by way of example, with the source 102 located on the side of the fin structure 101 close to the substrate 10 and the drain 103 located on the side of the fin structure 101 away from the substrate 10.

[0093] Please refer to Figure 6, which is a schematic diagram of another chip structure provided in an embodiment of this application. As shown in Figure 6, this embodiment of the application provides a chip including: a substrate 10 and a long-channel transistor 20. The long-channel transistor 20 includes a source 102 disposed inside the substrate 10, and a fin structure 101, a drain 103, a first spacer layer 104, a ring gate 105, and a second spacer layer 106 disposed on the substrate 10. The source 102 is disposed inside the substrate 10 on the side of the fin structure 101 closest to the substrate 10, and the drain 103 is disposed on the surface of the fin structure 101 away from the substrate 10. The projections of the source 102 and the drain 103 onto the substrate 10 do not overlap.

[0094] Please refer to Figures 7 and 8, which are a set of cross-sectional schematic diagrams along the first direction based on the chip shown in Figure 6 provided in the embodiments of this application. As shown in Figures 7 and 8, the source 102 is embedded inside the substrate 10, and the surface of the source 102 can be flush with the surface of the substrate 10. A portion of the source 102 can directly contact the side of the fin structure 101 near the substrate 10, and another portion can directly contact the second spacer layer 106. At this time, the drain 103 is disposed on the side of the fin structure 101 away from the substrate 10, and the projections of the source 102 and the drain 103 on the substrate do not overlap. As shown in Figure 7, the horizontal distance G between the drain 103 and the source 102 along the first direction is greater than the vertical distance (i.e., equivalent to the height of the fin structure 101 in the direction perpendicular to the substrate). At this time, the length of the horizontal distance G can dominate the channel length of the long-channel transistor in the chip. As shown in Figure 8 above, the horizontal spacing between the drain 103 and the source 102 along the first direction is less than the vertical spacing G. In this case, the length of the vertical spacing G can dominate the channel length of the long-channel transistor in the chip. It can be understood that the channel length of the long-channel transistor can be greater than or equal to 20nm.

[0095] In addition, other descriptions of the first spacer layer 104, the ring gate 105, the second spacer layer 106 and the fin structure 101 can be found in the relevant descriptions of the above embodiments, and will not be repeated in the embodiments of this application.

[0096] In some embodiments, similar to the long-channel transistor where the source 102 and drain 103 are located on the same side of the fin structure 101, when the source 102 and drain 103 are located on different sides of the fin structure 101, in the direction perpendicular to the substrate, both the source 102 and drain 103 include a first region in which the projections on the substrate 10 overlap with the projections of the ring gate 105 on the substrate 10. The first spacer layer 104 includes a first spacer region disposed between the first region away from the substrate and the ring gate; the second spacer layer is disposed between the first region near the substrate and the ring gate.

[0097] Please refer to Figure 9, which is a cross-sectional schematic diagram along a first direction based on the chip shown in Figure 6 according to an embodiment of this application. As shown in Figure 9, when the source 102 is disposed at the bottom of the fin structure 101 and the drain 103 is disposed at the top of the fin structure 101, a portion of the bottom source 102 (i.e., the first region 1021 of the source 102) contacts the second spacer layer 106, and the other portion contacts the fin structure 101; a portion of the top drain 103 is disposed above the fin structure, and the other portion (i.e., the first region 1031 of the drain 103) is disposed on the first spacer region 1041 of the first spacer layer 104. At this time, it can be understood that the first spacer region 1041 is stacked on the ring gate 105 and can be disposed around the fin structure 101. The first spacer region 1041 can completely isolate the first region disposed on the side away from the substrate and the ring gate 105 to improve the reliability of the device. For example, in some embodiments, as shown in FIG9 above, the thickness H1 of the first spacing region 1041 disposed below the drain 103 in the direction perpendicular to the substrate can be greater than or equal to 10 nm and less than or equal to 20 nm.

[0098] It should be noted that when the source and drain are located on different sides of the fin structure, in order for the source or drain located at the bottom of the fin structure to be properly connected to the contact electrode, as shown in Figure 9 above, the length of the source or drain located at the bottom of the fin structure in the first direction is greater than the length of the ring gate in the first direction. That is, the source or drain located at the bottom of the fin structure also includes a portion of region 1022 that does not coincide with the projection of the ring gate and the fin structure on the substrate.

[0099] In some embodiments, the first spacer layer 104 further includes a second spacer region 1042, which surrounds the first spacer region 1041 and the drain 103 to support and insulate the subsequently fabricated contact electrode from the drain. Furthermore, the material forming the first spacer region 1041 in the first spacer layer 104 is different from the material forming the second spacer region 1042. This prevents etching of the first spacer region during subsequent contact electrode fabrication of the second spacer region, thereby preventing leakage due to contact between the drain and the gate ring.

[0100] Additionally, it should be noted that the embodiments of this application do not impose specific limitations on the height of the first spacing region 1041 located near the top of the fin structure 101 that is not covered by the source electrode 102 or the drain electrode 103. As shown in FIG9 above, the upper surface of the first spacing region 1041 near the top of the fin structure 101 that is not covered by the source electrode 102 or the drain electrode 103 can be flush with the top of the fin structure. In other embodiments, as shown in FIG30 below, the upper surface of the first spacing region 1041 near the top of the fin structure 101 that is not covered by the source electrode 102 or the drain electrode 103 can be higher than the top of the fin structure.

[0101] It is understood that other descriptions of the first spacing region 1041 and the second spacing region 1042 of the long-channel transistor in the chip can also be referred to the above embodiments, and the embodiments of this application will not be repeated here.

[0102] It is also understood that when the source electrode 102 is disposed on the top of the fin structure 101, the second spacing region 1042 surrounds the first spacing region 1041 and the aforementioned source electrode 102. This will not be elaborated further in the embodiments of this application.

[0103] In other embodiments, for process integrity, the area of ​​the fin structure 101 away from the substrate 10 that is not covered by the source 102 or drain 103 may also be filled with a third spacer layer 107. The third spacer layer 107 may be formed of an insulating material.

[0104] For example, this applies to the chip shown in Figure 2 and the chip shown in Figure 6.

[0105] In some embodiments, the thickness of the ring gate 105 in the first direction is greater than or equal to the thickness of the first spacing region 1041 in the first direction; the length of the ring gate 105 in the second direction is greater than or equal to the length of the fin structure 101 in the second direction, the second direction being perpendicular to the first direction and parallel to the substrate 10.

[0106] A ring gate 105 is disposed around the four sidewalls of the fin structure 101. To ensure that the ring gate can be properly connected to the contact electrode to achieve gate control, the thickness of the ring gate 105 in the first direction can be greater than or equal to the thickness of the first spacing region 1041 in the first direction. Moreover, to ensure effective gate control, the length of the ring gate in the second direction can be greater than or equal to the length of the first spacing region 1041 in the second direction.

[0107] It is understood that, as shown in Figure 4 above, the thickness L2 of the ring gate 105 in the first direction is greater than or equal to 50 nm and less than or equal to 100 nm. It is also understood that this thickness L2 indicates the thickness of the ring gate 105 on one side of the fin structure in the first direction, not the thickness of the entire ring gate 105 in the first direction. Since the ring gate 105 is arranged around the fin structure, to facilitate electrical connection between the ring gate and the contact electrode and to meet circuit design requirements, the thickness of the ring gate 105 in the first direction needs to be sufficient for electrical connection with the contact electrode. Therefore, the thickness L2 of the ring gate 105 in the first direction can be between 50 and 100 nm.

[0108] Please refer to Figures 10 and 11. Figure 10 is a set of schematic diagrams based on the chip shown in Figure 2 along the second direction provided by an embodiment of this application. Figure 11 is another set of cross-sectional schematic diagrams based on the chip shown in Figure 6 along the second direction provided by an embodiment of this application. As shown in (1) of Figure 10 and (1) of Figure 11 above, the width K1 of the ring gate 105 in the second direction is greater than or equal to 20 nm and less than or equal to 50 nm. The width K1 in the second direction can be understood as the overall width of the ring gate 105. The second direction is perpendicular to the first direction and parallel to the substrate. As shown in (2) of Figure 10 and (2) of Figure 11 above, the thickness K2 of the ring gate 105 surrounding both sides of the fin structure 101 in the second direction can be greater than or equal to 5 nm and less than or equal to 15 nm.

[0109] It should be noted that when the ring gate 105 surrounds the fin structure 101, the thickness K2 on both sides in the second direction can be the same or different. That is, the thickness K2 on one side of the ring gate 105 can be 10nm and the thickness K2 on the other side can be 11nm. In this embodiment, no specific limitation is made.

[0110] In some embodiments, a high-dielectric-constant dielectric layer 108 and a gate oxide dielectric layer 109 are disposed between the ring gate 105 and the fin structure 101. As shown in FIG. 5 above, when the source 102 and drain 103 are spaced apart and disposed on the same side of the fin structure 101, a high-dielectric-constant dielectric layer 108 and a gate oxide dielectric layer 109 are disposed between the ring gate 105 and the fin structure 101. In addition, please refer to FIG. 12, which is another cross-sectional schematic diagram of the chip shown in FIG. 6 along the first direction provided by an embodiment of this application. As shown in FIG. 12, when the source 102 and drain 103 are respectively spaced apart and disposed on different sides of the fin structure 101, a high-dielectric-constant dielectric layer 108 and a gate oxide dielectric layer 109 are also disposed between the ring gate 105 and the fin structure 101.

[0111] The high dielectric constant dielectric layer 108 is located between the gate ring and the gate oxide dielectric layer 109. The gate structure formed by the gate oxide dielectric layer 109, the high dielectric constant dielectric layer 108, and the gate ring 105 can be a high-k metal gate (HKMG). In some embodiments, one or more of a work function layer and a pad layer can be disposed between the high dielectric constant dielectric layer 108 and the gate ring 105; this embodiment does not specifically limit the specific application. The high dielectric constant dielectric layer 108 can reduce the thickness of the equivalent oxide thickness (EOT) of long-channel transistors in the chip. The material forming the high dielectric constant dielectric layer 108 can be a high dielectric constant material, such as hafnium dioxide (HfO2) or hafnium silicon oxynitride (HfSiON); the material forming the gate oxide dielectric layer 109 can be silicon oxide (SiO) or silicon dioxide (SiO2).

[0112] In some embodiments, when the source 102 and drain 103 are disposed on the same side or different sides of the fin structure 101, the source and drain are of the same type of heavy doping, and the doping concentration corresponding to the heavy doping is greater than or equal to 10. 20 cm -3 and less than or equal to 10 22 cm -3 That is, both the source and drain are heavily doped of the same type, for example, both are heavily doped with N-type or P-type doping, so as to control the movement of charge carriers in the fin structure 101 when a voltage is applied to the gate ring. The doping concentrations of the source and drain can be the same or different depending on the circuit design requirements.

[0113] In addition, to better compare the structure of the long-channel transistor in the chip provided in the embodiments of this application with the short-channel transistor in the current vertical transmission field-effect transistor, as well as the compatibility of the process, please refer to Figure 13. Figure 13 is a cross-sectional schematic diagram comparing a set of long-channel transistors and short-channel transistors provided in the embodiments of this application.

[0114] As shown in Figure 13, the transistor in the chip 100 can be a long-channel transistor. The structure of the long-channel transistor can be found in the description of the relevant embodiments above, and will not be repeated in this application. The short-channel transistor 200 may include: a source 202 embedded on the surface of the substrate 20. A portion of the upper surface of the source 202 is provided with a fin structure 201 and a drain 203. The drain 203 is provided on the surface of the fin structure 201 away from the substrate 20. In the direction parallel to the substrate 20, a first spacer layer 204, a ring gate 205, and a second spacer layer 206 surround the four sides of the fin structure 201. In the direction perpendicular to the substrate, the first spacer layer 204, the ring gate 205, and the second spacer layer 206 are stacked sequentially. The first spacer layer 204 may also include a first spacer region 2041 and a second spacer region 2042.

[0115] The channel length of the chip 100 is G1, which is the horizontal spacing between the source 102 and the drain 103. The longer the fin structure 101 of the chip 100, the longer the horizontal spacing between the source 102 and the drain 103 can be, and thus the longer the channel length can be. The channel length of the short-channel transistor 200 is G2, which is the vertical spacing between the source 202 and the drain 203. The shorter the fin structure 101 of the short-channel transistor 200, the shorter the vertical spacing between the source 102 and the drain 103 can be, and thus the shorter the channel length can be.

[0116] Therefore, the fin structure with the same configuration can simultaneously meet the channel length requirements of both long-channel and short-channel transistors. Moreover, the similar configuration of the long-channel transistor and the short-channel transistor further enables the transistors of the chip provided in this application embodiment to be compatible with the fabrication process of vertical transmission short-channel transistors, greatly saving the fabrication cost and solving the current problem of the difficulty in compatibility of fabrication processes for long-channel and short-channel transistors for vertical transmission field-effect transistors.

[0117] Secondly, the embodiments of this application provide a method for fabricating a chip, which can be used to manufacture the chip mentioned in the above embodiments.

[0118] The method includes:

[0119] Step 1: A fin structure, a source, and a drain are fabricated on a substrate. The source and drain are disposed on the same side or different sides of the fin structure in a direction perpendicular to the substrate, and the projection of the source on the substrate does not overlap with the projection of the drain on the substrate.

[0120] Step 2: A second spacer layer, a ring gate, and a first spacer layer are sequentially deposited around the fin structure; wherein, in the direction parallel to the substrate, the first spacer layer is arranged around the fin structure, the ring gate is arranged around the fin structure, and the second spacer layer is arranged around the fin structure; and in the direction perpendicular to the substrate, the first spacer layer, the ring gate, and the second spacer layer are stacked sequentially.

[0121] When the source and drain are located on the same side of the fin structure perpendicular to the substrate, the chip fabrication method described above and the chip shown in FIG2 are used as an example to illustrate the chip fabrication method. Please refer to FIG14-FIG22. FIG14 is a flowchart of a chip fabrication method provided in an embodiment of this application, and FIG15-FIG22 are cross-sectional schematic diagrams of a set of fabricated chips provided in an embodiment of this application.

[0122] As shown in Figure 14, the preparation method includes:

[0123] Step S11: A fin structure is formed on a substrate, and a first dielectric layer is deposited on the surface of the fin structure away from the substrate.

[0124] Specifically, as shown in Figure 15, taking the Y-axis cross-sectional view as an example, a fin structure 101 can be formed on the substrate 10, and a first dielectric layer 111 can be deposited on the surface of the fin structure 101 away from the substrate. The material forming the first dielectric layer 111 can be an insulating material to subsequently space the source and drain.

[0125] Step S12: A second spacer layer, a ring grid, and a first spacer layer are sequentially deposited on the sidewalls of the fin structure and the first dielectric layer.

[0126] Specifically, as shown in Figure 16, a second spacer layer 106, a ring gate 105, and a first spacer layer 104 are sequentially deposited around the sidewalls of the fin structure 101 and the first dielectric layer 111. The second spacer layer 106, the ring gate 105, and the first spacer layer 104 are stacked sequentially in a direction perpendicular to the substrate, with the second spacer layer 106 and the ring gate 105 surrounding the fin structure, and the first spacer layer 104 surrounding the fin structure 101 and the first dielectric layer 111.

[0127] In some embodiments, the step of sequentially depositing a second spacer layer, a ring gate, and a first spacer layer on the sidewalls of the fin structure and the first dielectric layer includes: depositing a second spacer layer on the sidewalls of the fin structure; sequentially depositing a gate oxide dielectric layer, a high dielectric constant dielectric layer, and a metal ring gate on the second spacer layer around the sidewalls of the fin structure, wherein the high dielectric constant dielectric layer is located between the metal ring gate and the gate oxide dielectric layer; and depositing the gate oxide dielectric layer, the high dielectric constant dielectric layer, and the metal ring gate around the fin structure to form a first spacer layer on the sidewalls of the first dielectric layer.

[0128] As shown in Figure 17, a second spacer layer 106 is deposited on the bottom sidewall of the fin structure 101; a gate oxide dielectric layer 109, a high dielectric constant dielectric layer 108, and a metal ring gate 105 are sequentially deposited on the upper surface of the second spacer layer 106 (i.e., the surface away from the substrate 10) and around the middle sidewall of the fin structure 101, wherein the high dielectric constant dielectric layer 108 is located between the metal ring gate 105 and the gate oxide dielectric layer 109; a first spacer layer 104 is deposited on the gate oxide dielectric layer 109, the high dielectric constant dielectric layer 108, and the ring gate 105 around the sidewall of the fin structure 101 and the first dielectric layer 111.

[0129] In some embodiments, the first spacer layer 104 includes a first spacer region 1041 and a second spacer region 1042. As shown in FIG18, depositing the first spacer layer 104 includes depositing the first spacer region 1041 and the second spacer region 1042. The first spacer region 1041 is disposed around the sidewalls of the fin structure 101 and the first dielectric layer 111, and the second spacer region 1042 is disposed around the first spacer region 1041. That is, the first spacer region 1041 is disposed between the second spacer region 1042 and the fin structure 101, and between the second spacer region 1042 and the first dielectric layer 111. The materials used to form the first spacer region 1041 and the second spacer region 1042 are different.

[0130] Step S13: Etch the surface of the first dielectric layer away from the substrate to form a first opening and a second opening.

[0131] Specifically, as shown in Figure 19, based on the structure shown in Figure 16, after sequentially depositing and forming a second spacer layer, a ring gate, and a first spacer layer around the fin structure, the surface of the first dielectric layer 111 away from the substrate is etched to form a first opening 112 and a second opening 113. The bottom of both the first opening 112 and the second opening 113 exposes the fin structure 101, and the sidewalls of both the first opening 112 and the second opening 113 expose the first spacer layer 104. Furthermore, the bottom of the first opening 112 and the second opening 113 may selectively expose the first spacer layer 104 according to circuit requirements.

[0132] In other embodiments, as shown in FIG20, based on the structure shown in FIG18 above, the surface of the first dielectric layer 111 away from the substrate and the surface of the first spacer region 1041 are etched to form a first opening 112 and a second opening 113. The bottom of the first opening 112 and the second opening 113 expose the fin structure 101 and the first spacer region 1041, and the sidewalls of the first opening 112 and the second opening 113 expose the second spacer region 1042.

[0133] Step S14: Form a source electrode at the first opening and a drain electrode at the second opening.

[0134] Specifically, as shown in Figure 21, based on the structure shown in Figure 15, material can be deposited and doped at the first opening 112 to form the source electrode 102, and material can be deposited and doped at the second opening 113 to form the drain electrode 103, thus completing the chip fabrication. Additionally, the remaining portion of the first dielectric layer 111 can be used to form the third spacer layer 107.

[0135] It should be noted that in some other embodiments, as shown in Figure 22, contact electrodes can be inserted after the chip is fabricated to connect to the circuit.

[0136] When the source and drain are located on different sides of the fin structure perpendicular to the substrate, the chip fabrication method described above and the chip shown in FIG6 are used as an example to illustrate the chip fabrication method, with the source 102 located on the side of the fin structure 101 close to the substrate 10 and the drain 103 located on the side of the fin structure 101 away from the substrate 10.

[0137] Please refer to Figures 23-31. Figure 23 is a flowchart of another chip fabrication method provided in the embodiment of this application, and Figures 24-31 are cross-sectional schematic diagrams of a set of prepared chips provided in the embodiment of this application.

[0138] As shown in Figure 23, the preparation method includes:

[0139] Step S21: Form a source electrode and a fin structure on a substrate, and deposit a first dielectric layer on the surface of the fin structure away from the substrate.

[0140] Specifically, taking the Y-axis cross-sectional view as an example, as shown in Figure 24, a fin structure 101 can be formed on the substrate 10, and then a source electrode 102 can be formed on the side of the fin structure near the substrate through ion implantation or vapor deposition. The source electrode 102 is embedded inside the substrate, and a portion of the fin structure 101 near the substrate 10 is connected to the source electrode 102. A first dielectric layer 111 is deposited on the surface of the fin structure 101 away from the substrate. The material forming the first dielectric layer 111 can be an insulating material to subsequently space the source and drain electrodes.

[0141] Step S22: A second spacer layer, a ring grid, and a first spacer layer are sequentially deposited on the sidewalls of the fin structure and the first dielectric layer.

[0142] Specifically, as shown in Figure 25, a second spacer layer 106, a ring gate 105, and a first spacer layer 104 are sequentially deposited around the sidewalls of the fin structure 101 and the first dielectric layer 111. The second spacer layer 106, the ring gate 105, and the first spacer layer 104 are stacked sequentially in a direction perpendicular to the substrate, with the second spacer layer 106 and the ring gate 105 surrounding the fin structure, and the first spacer layer 104 surrounding the fin structure 101 and the first dielectric layer 111.

[0143] In some embodiments, as shown in FIG26, a second spacer layer 106 is deposited on the bottom sidewall of the fin structure 101; a gate oxide dielectric layer 109, a high dielectric constant dielectric layer 108, and a metal ring gate 105 are sequentially deposited on the upper surface of the second spacer layer 106 (i.e., the surface away from the substrate 10) and around the middle sidewall of the fin structure 101, wherein the high dielectric constant dielectric layer 108 is located between the metal ring gate 105 and the gate oxide dielectric layer 109; a first spacer layer 104 is deposited on the gate oxide dielectric layer 109, the high dielectric constant dielectric layer 108, and the ring gate 105 around the sidewall of the fin structure 101 and the first dielectric layer 111.

[0144] In other embodiments, as shown in FIG27, the deposition of the first spacer layer 104 includes the deposition of a first spacer region 1041 and a second spacer region 1042. The first spacer region 1041 is disposed around the sidewalls of the fin structure 101 and the first dielectric layer 111, and the second spacer region 1042 is disposed around the first spacer region 1041. That is, the first spacer region 1041 is disposed between the second spacer region 1042 and the fin structure 101, and between the second spacer region 1042 and the first dielectric layer 111. The materials used to form the first spacer region 1041 and the second spacer region 1042 are different.

[0145] Step S23: Etch the surface of the first dielectric layer away from the substrate to form a third opening.

[0146] Specifically, as shown in Figure 28, based on the structure shown in Figure 25, after sequentially depositing and forming a second spacer layer, a ring gate, and a first spacer layer around the fin structure, the surface of the first dielectric layer 111 away from the substrate is etched to form a third opening 114. The bottom of each of the third openings 114 exposes the fin structure 101, and the sidewalls of each of the third openings 114 expose the first spacer layer 104. Furthermore, the bottom of the third opening 114 may selectively expose the first spacer layer 104 according to circuit requirements.

[0147] In other embodiments, as shown in FIG29, based on the structure shown in FIG27 above, the surface of the first dielectric layer 111 away from the substrate and the surface of the first spacer region 1041 are etched to form a third opening 114. The bottom of the third opening 114 exposes the fin structure 101 and the first spacer region 1041, and the sidewalls of the third opening 114 expose the second spacer region 1042.

[0148] Step S24: Form a drain electrode at the third opening.

[0149] Specifically, as shown in Figure 30, based on the structure shown in Figure 29 above, material can be deposited and doped at the third opening 114 to form a drain 103, thus completing the fabrication of the long-channel transistor in the chip. Additionally, the remaining portion of the first dielectric layer 111 can form a third spacer layer 107.

[0150] It should be noted that, in some other embodiments, as shown in Figure 31, contact electrodes can be inserted after the long-channel transistor is fabricated, so as to connect to the circuit in the chip.

[0151] Additionally, it should be noted that, in order to insert the contact electrode of the source 102 located at the bottom of the fin structure 101, during the fabrication of the second spacer layer, the ring gate, and the first spacer layer in step S22, a second dielectric layer 110 can also be fabricated above the source region 1022 using an insulating material to support the inserted contact electrode and insulate the contact electrode from the adjacent ring gate 105. The material of the second dielectric layer 110 can be the same as or different from the material of the first spacer layer. For example, the material of the second dielectric layer 110 can be silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide, etc. This embodiment does not specifically limit the specific materials used in this application.

[0152] It should also be noted that, as can be seen from the above-described chip fabrication process and structure, the long-channel transistor in the chip of this application embodiment can not only form mutually spaced heavy doping on the top of the fin structure to prepare the source and drain, but also form mutually horizontally spaced heavy doping on both sides of the fin structure to prepare the source and drain. The fabrication process under this structure is compatible with the current fabrication process of vertical transmission short-channel transistors, greatly saving fabrication costs. Most importantly, the area surrounded by the ring gate in this long-channel transistor is the gate control region. This full-ring gate long-channel transistor structure significantly improves device performance. Moreover, compared with the prior art based on length control of two vertical ring gates and one planar gate control region, the long-channel transistor fabricated in this application embodiment greatly reduces the difficulty of process and circuit design.

[0153] This application also provides an electronic device, including a circuit and a chip as mentioned in the above embodiments applied to the circuit.

[0154] It should be understood that the chip fabrication method and electronic device provided in this application can be consistent with the chip technology solution provided in this application. The specific content and beneficial effects can be referred to the chip mentioned in the embodiments shown in Figures 2-12 above, and will not be repeated here.

[0155] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0156] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0157] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0158] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0159] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A chip, characterized in that, include: A substrate and a long-channel transistor, wherein the long-channel transistor is disposed on the substrate, and the long-channel transistor includes a fin structure Fin, a source, a drain, a first spacer layer, a ring gate, and a second spacer layer; In the direction perpendicular to the substrate, the source and the drain are respectively disposed on the same side or different sides of the fin structure, and the projection of the source on the substrate and the projection of the drain on the substrate do not overlap. In the direction parallel to the substrate, the first spacer layer is disposed around the fin structure, the ring gate is disposed around the fin structure, and the second spacer layer is disposed around the fin structure; and in the direction perpendicular to the substrate, the first spacer layer, the ring gate, and the second spacer layer are stacked sequentially.

2. The chip according to claim 1, characterized in that, The source and the drain are spaced apart on the side of the fin structure away from the substrate.

3. The chip according to claim 2, characterized in that, Both the source and the drain include a first region, and the projection of the first region onto the substrate overlaps with the projection of the ring gate onto the substrate; The first spacer layer includes a first spacer region disposed between the first region and the ring gate in a direction perpendicular to the substrate.

4. The chip according to claim 3, characterized in that, The first spacer layer further includes a second spacer region surrounding the first spacer region, the source, and the drain. Furthermore, the material forming the first spacer region in the first spacer layer is different from the material forming the second spacer region.

5. The chip according to any one of claims 2-4, characterized in that, On the surface of the fin structure away from the substrate, a third spacer layer is provided between the source and the drain.

6. The chip according to claim 1, characterized in that, The source electrode is disposed on the side of the fin structure closest to the substrate and embedded inside the substrate, while the drain electrode is disposed on the side of the fin structure furthest from the substrate; or, The drain is disposed on the side of the fin structure closest to the substrate and embedded inside the substrate, while the source is disposed on the side of the fin structure furthest from the substrate.

7. The chip according to claim 6, characterized in that, In a direction perpendicular to the substrate, both the source and the drain include a first region, the projection of the first region onto the substrate overlaps with the projection of the ring gate onto the substrate; The first spacer layer includes a first spacer region, which is disposed between a first region in the drain and the ring gate in a direction perpendicular to the substrate; A second spacer layer is provided between the first region in the source electrode and the ring gate.

8. The chip according to claim 7, characterized in that, The first spacer layer further includes a second spacer region surrounding the first spacer region and the drain electrode; Furthermore, the material forming the first spacer region in the first spacer layer is different from the material forming the second spacer region.

9. The chip according to any one of claims 3-4 or any one of claims 7-8, characterized in that, In the direction perpendicular to the substrate, the thickness of the first spacing region is greater than or equal to 5 nm and less than or equal to 50 nm.

10. The chip according to claim 9, characterized in that, The thickness of the ring grid in the first direction is greater than or equal to the thickness of the first spacing region in the first direction; The length of the ring gate in the second direction is greater than or equal to the length of the first spacing region in the second direction; wherein, the first direction is the extension direction of the fin structure, and the second direction is perpendicular to the first direction and parallel to the substrate.

11. The chip according to any one of claims 1-10, characterized in that, The distance between the source and the drain in the first direction is less than the length of the fin structure in the first direction; and, when the source and the drain are disposed on the same side of the fin structure, the distance between the source and the drain in the first direction is greater than or equal to 20 nm.

12. The chip according to claim 11, characterized in that, The length of the fin structure in the first direction is greater than or equal to 20 nm and less than or equal to 1 μm; The fin structure has a height of 20 nm or more and less than or equal to 100 nm in the direction perpendicular to the substrate.

13. The chip according to any one of claims 1-12, characterized in that, A high dielectric constant dielectric layer and a gate oxide dielectric layer are disposed between the ring gate and the fin structure, wherein the high dielectric constant dielectric layer is located between the ring gate and the gate oxide dielectric layer.

14. The chip according to any one of claims 1-10, characterized in that, The source and the drain are of the same type of heavy doping, and the doping concentration of the heavy doping is greater than or equal to 10. 20 cm -3 and less than or equal to 10 22 cm -3 .

15. A method for fabricating a chip, characterized in that, The method includes: A fin structure, a source electrode, and a drain electrode are fabricated on a substrate, wherein the source electrode and the drain electrode are respectively disposed on the same side or different sides of the fin structure in a direction perpendicular to the substrate, and the projection of the source electrode on the substrate and the projection of the drain electrode on the substrate do not overlap. A second spacer layer, a ring gate, and a first spacer layer are sequentially deposited around the fin structure; wherein, in the direction parallel to the substrate, the first spacer layer is disposed around the fin structure, the ring gate is disposed around the fin structure, and the second spacer layer is disposed around the fin structure; and in the direction perpendicular to the substrate, the first spacer layer, the ring gate, and the second spacer layer are sequentially stacked.

16. The method according to claim 15, characterized in that, When the source and the drain are disposed on the same side of the fin structure in a direction perpendicular to the substrate, the fabrication of the fin structure, the source, and the drain on the substrate includes: A fin structure is fabricated on a substrate, and a first dielectric layer is deposited on the surface of the fin structure away from the substrate: After the second spacer layer, the ring gate, and the first spacer layer are sequentially deposited around the fin structure, the surface of the first dielectric layer away from the substrate is etched to form a first opening and a second opening. A source electrode is formed at the first opening and a drain electrode is formed at the second opening. The projections of the first opening and the second opening on the substrate do not overlap. The bottom of both the first opening and the second opening exposes the fin structure, and the sidewalls of both the first opening and the second opening expose the first spacer layer.

17. The method according to claim 15, characterized in that, When the source and the drain are disposed on different sides of the fin structure in a direction perpendicular to the substrate, the fabrication of the fin structure, the source, and the drain on the substrate includes: A source electrode and a fin structure are fabricated on the substrate, and a first dielectric layer is deposited on the surface of the fin structure away from the substrate: wherein the source electrode is embedded inside the substrate, and a portion of the fin structure near the substrate is connected to the source electrode; After the second spacer layer, the ring gate, and the first spacer layer are sequentially deposited around the fin structure, the surface of the first dielectric layer away from the substrate is etched to form a third opening, and a drain electrode is formed at the third opening; wherein the projection of the third opening on the substrate does not overlap with the source electrode, the bottom of the third opening exposes the fin structure, and the sidewall of the third opening exposes the first spacer layer.

18. An electronic device, characterized in that, Includes a circuit board and a chip applied to the circuit board as described in any one of claims 1-14.

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