Bandgap reference circuit, SDM circuit, and integrated circuit chip

Abstract

A bandgap reference circuit, an SDM circuit, and an integrated circuit chip. The bandgap reference circuit comprises: a bandgap voltage generation circuit, which is configured to generate a bandgap voltage, and perform first-order and high-order temperature compensation on the generated bandgap voltage; and a bandgap buffer circuit, which is electrically connected to an output end of the bandgap voltage generation circuit, and is configured to isolate a reverse input electrical signal of a post-stage load. The bandgap reference circuit can optimize the voltage accuracy and voltage temperature coefficient of an outputted bandgap voltage.

Description

Bandgap reference circuits, SDM circuits, and integrated circuit chips

[0001] This application claims priority to Chinese patent application filed on July 11, 2024, with application number 202410932393.3 and entitled "Bandgap Reference Circuit, SDM Circuit and Integrated Circuit Chip", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic technology, and more specifically to a bandgap reference circuit, an SDM circuit, and an integrated circuit chip. Background Technology

[0003] In the design of precision signal chain products, the importance of high-precision analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) is self-evident, and the noise, accuracy, and temperature coefficient performance of the bandgap reference circuit have a significant impact on the performance of high-precision ADCs / DACs.

[0004] Currently, the main technologies for bandgap reference circuits focus on: using operational amplifier clamping to generate a positive temperature coefficient voltage, which is then superimposed with a negative temperature coefficient voltage at a certain ratio to obtain a temperature-independent bandgap reference voltage. This is the traditional continuous-time bandgap reference architecture. Its advantages are simple circuit design, easy-to-understand circuit principle, and relatively high power supply rejection ratio (PSR). Its disadvantages are poor temperature drift performance of the output reference voltage, lack of high-order temperature compensation methods, and the addition of high-order compensation circuits would lead to complex circuit structure and large area cost for 1 / f noise cancellation methods. Summary of the Invention

[0005] In view of this, this application provides a bandgap reference circuit, an SDM circuit, and an integrated circuit chip for optimizing the output voltage accuracy and voltage temperature coefficient.

[0006] In a first aspect, embodiments of this application provide a bandgap reference circuit, including:

[0007] A bandgap voltage generation circuit is used to generate a bandgap voltage and perform first-order and higher-order temperature compensation on the generated bandgap voltage.

[0008] A bandgap buffer circuit, electrically connected to the output of the bandgap voltage generation circuit, is used to isolate the reverse input electrical signal of the subsequent load.

[0009] The embodiments of this application greatly improve the accuracy and temperature characteristics of the output voltage by performing first-order and higher-order temperature compensation on the generated bandgap voltage and isolating crosstalk or influence from the downstream load.

[0010] In one possible implementation, the bandgap voltage generation circuit includes:

[0011] First operational amplifier module;

[0012] The first charge storage module, when the bandgap voltage generation circuit is in sampling mode, has its first terminal electrically connected to the first input terminal of the first operational amplifier module, and its second terminal electrically connected to the second input terminal and the output terminal of the first operational amplifier module. When the bandgap voltage generation circuit is in amplification mode, the first terminal of the first charge storage module is electrically connected to the output terminal of the first operational amplifier module, and its second terminal is electrically connected to the second input terminal of the first operational amplifier module.

[0013] The second charge storage module has its first terminal electrically connected to the second input terminal of the first operational amplifier module.

[0014] A third charge storage module, wherein the first terminal of the third charge storage module is electrically connected to the second input terminal of the first operational amplifier module;

[0015] The first charge storage module, the second charge storage module, and the third charge storage module are used to store the input noise and offset voltage of the first operational amplifier module when the bandgap voltage generation circuit is in sampling mode, and to perform first-order and higher-order temperature compensation on the generated bandgap voltage when the bandgap voltage generation circuit is in amplification mode.

[0016] This embodiment of the application stores input noise and offset voltage through a first charge storage module, a second charge storage module, and a third charge storage module, performs first-order and higher-order temperature compensation on the bandgap voltage, attenuates the influence of the operational amplifier's equivalent input offset, optimizes the output voltage accuracy, reduces the operational amplifier's equivalent input noise, optimizes the noise characteristics at 1 / f at low frequencies, and optimizes the output voltage temperature coefficient.

[0017] In one possible implementation, the bandgap voltage generation circuit further includes:

[0018] The first voltage generation module is electrically connected to the first input terminal of the first operational amplifier module and is used to output a first voltage with a positive temperature coefficient.

[0019] The second voltage generation module is electrically connected to the second terminal of the second charge storage module, and is used to output a second voltage with a positive temperature coefficient when the bandgap voltage generation circuit is in sampling mode.

[0020] The third voltage generation module is electrically connected to the second terminal of the second charge storage module and is used to output a third voltage with a positive temperature coefficient when the bandgap voltage generation circuit is in amplification mode.

[0021] The fourth voltage generation module is electrically connected to the second terminal of the third charge storage module and is used to output a fourth voltage with a positive temperature coefficient when the bandgap voltage generation circuit is in sampling mode.

[0022] The fifth voltage generation module is electrically connected to the second terminal of the third charge storage module and is used to output a fifth voltage with zero temperature coefficient when the bandgap voltage generation circuit is in amplification mode.

[0023] This application embodiment reduces the input noise and offset voltage of the first operational amplifier module by controlling the output voltage under different states of the bandgap voltage generation circuit, and performs first-order and higher-order temperature compensation on the bandgap voltage, thereby ensuring the accuracy and temperature characteristics of the output bandgap voltage.

[0024] In one possible implementation, the first voltage generating module includes a first positive temperature coefficient bias current and a first transistor. The output terminal of the first positive temperature coefficient bias current is electrically connected to the first terminal of the first transistor. The first terminal of the first transistor is electrically connected to the first input terminal of the first operational amplifier module. The control terminal of the first transistor is electrically connected to the second terminal of the first transistor. The second terminal of the first transistor is grounded.

[0025] The second voltage generation module includes a second positive temperature coefficient bias current and a second transistor. The output terminal of the second positive temperature coefficient bias current is electrically connected to the first terminal of the second transistor. The first terminal of the second transistor is electrically connected to the second terminal of the second charge storage module. The control terminal of the second transistor is electrically connected to the second terminal of the second transistor. The second terminal of the second transistor is grounded.

[0026] The third voltage generation module includes a second positive temperature coefficient bias current and a third transistor. The output terminal of the second positive temperature coefficient bias current is electrically connected to the first terminal of the third transistor. The first terminal of the third transistor is electrically connected to the second terminal of the second charge storage module. The control terminal of the third transistor is electrically connected to the second terminal of the third transistor. The second terminal of the third transistor is grounded.

[0027] The fourth voltage generation module includes a third positive temperature coefficient bias current and a fourth transistor. The output terminal of the third positive temperature coefficient bias current is electrically connected to the first terminal of the fourth transistor. The first terminal of the fourth transistor is electrically connected to the second terminal of the third charge storage module. The control terminal of the fourth transistor is electrically connected to the second terminal of the fourth transistor. The second terminal of the fourth transistor is grounded.

[0028] The fifth voltage generation module includes a zero temperature coefficient bias current and a fifth transistor. The output terminal of the zero temperature coefficient bias current is electrically connected to the first terminal of the fifth transistor. The first terminal of the fifth transistor is electrically connected to the second terminal of the third charge storage module. The control terminal of the fifth transistor is electrically connected to the second terminal of the fifth transistor. The second terminal of the fifth transistor is grounded.

[0029] In one possible implementation, the bandgap voltage generation circuit further includes:

[0030] The first switch is located on the connection line between the output terminal of the first operational amplifier module and the second input terminal of the first operational amplifier module.

[0031] The second switch is located on the connection line between the output terminal of the first operational amplifier module and the first terminal of the first charge storage module.

[0032] The third switch is located on the connection line between the first input terminal of the first operational amplifier module and the first terminal of the first charge storage module.

[0033] The fourth switch is located on the connection line between the output terminal of the second positive temperature coefficient bias current and the first terminal of the second transistor.

[0034] The fifth switch is located on the connection line between the first end of the second transistor and the second end of the second charge storage module;

[0035] The sixth switch is located on the connection line between the output terminal of the second positive temperature coefficient bias current and the first terminal of the third transistor.

[0036] The seventh switch is located on the connection line between the first end of the third transistor and the second end of the second charge storage module.

[0037] The eighth switch is located on the connection line between the first end of the fourth transistor and the second end of the third charge storage module.

[0038] The ninth switch is located on the connection line between the first terminal of the fifth transistor and the second terminal of the third charge storage module; wherein,

[0039] When the bandgap voltage generation circuit is in sampling mode, the first switch, the third switch, the fourth switch, the fifth switch and the eighth switch are in the closed state, and the second switch, the sixth switch, the seventh switch and the ninth switch are in the open state.

[0040] When the bandgap voltage generating circuit is in amplification mode, the second, sixth, seventh, and ninth switches are closed, while the first, third, fourth, fifth, and eighth switches are open.

[0041] In this embodiment, the bandgap voltage generation circuit can be adjusted to different states by switching each switch.

[0042] In one possible implementation, the relationship between the capacitance value C1 of the first charge storage module and the capacitance value C2 of the second charge storage module is as follows:

[0043] Where K is Boltzmann's constant, q is the unit charge, and I s1 I is the saturation current of the first transistor. s3 The saturation current of the third transistor, Vg0 is the reference bandgap voltage, T0 is the corresponding reference temperature point, and VBE0 is the voltage difference between the base and emitter at the corresponding reference temperature point.

[0044] In this embodiment of the application, when the capacitance value C1 of the first charge storage module and the capacitance value C2 of the second charge storage module satisfy the above relationship, the first-order temperature value in the output bandgap voltage can be eliminated, that is, the first-order temperature compensation is performed on the output bandgap voltage.

[0045] In one possible implementation, the relationship between the capacitance C1 of the first charge storage module and the capacitance C3 of the third charge storage module is: C3 = C1 × (η-1)

[0046] Wherein, η is a process parameter.

[0047] In this embodiment, when the capacitance value C1 of the first charge storage module and the capacitance value C3 of the third charge storage module satisfy the above relationship, the higher-order temperature value in the output bandgap voltage can be eliminated, that is, higher-order temperature compensation is performed on the output bandgap voltage.

[0048] In one possible implementation, the bandgap buffer circuit includes:

[0049] The second operational amplifier module has its first input terminal electrically connected to the output terminal of the bandgap voltage generation circuit.

[0050] A fourth charge storage module, wherein the first terminal of the fourth charge storage module is electrically connected to the first input terminal of the second operational amplifier module, and the second terminal of the fourth charge storage module is grounded; when the bandgap buffer circuit is in the sampling state, the fourth charge storage module is used to store the bandgap voltage; when the bandgap buffer circuit is in the amplification state, the fourth charge storage module is used to output the bandgap voltage.

[0051] The fifth charge storage module, when the bandgap buffer circuit is in sampling state, has its first terminal electrically connected to the second input terminal and the output terminal of the second operational amplifier module, and its second terminal electrically connected to the first input terminal of the second operational amplifier module. The fifth charge storage module is used to store the input noise and offset voltage of the second operational amplifier module. When the bandgap buffer circuit is in amplification state, the first terminal of the fifth charge storage module is electrically connected to the second input terminal of the second operational amplifier module, and its second terminal is electrically connected to the output terminal of the second operational amplifier module. The fifth charge storage module is used to perform voltage compensation for the second operational amplifier module.

[0052] The embodiments of this application can attenuate the influence of the offset voltage of the second operational amplifier module through the fourth charge storage module and the fifth charge storage module, optimize the output voltage accuracy, reduce the input noise of the second operational amplifier module, and optimize the noise characteristics at 1 / f at low frequencies.

[0053] In one possible implementation, the bandgap buffer circuit further includes:

[0054] The first transistor has its first terminal electrically connected to the output terminal of the bandgap voltage generation circuit, and its second terminal electrically connected to the first input terminal of the second operational amplifier module and the first terminal of the fourth charge storage module.

[0055] The second transistor has its first terminal electrically connected to the output terminal of the second operational amplifier module, and its second terminal electrically connected to the second input terminal of the second operational amplifier module and the first terminal of the fifth charge storage module.

[0056] The third transistor has its first terminal electrically connected to the output terminal of the second operational amplifier module, and its second terminal electrically connected to the second terminal of the fifth charge storage module.

[0057] The fourth transistor has its first terminal electrically connected to the second terminal of the fifth charge storage module and the second terminal of the third transistor, and its second terminal electrically connected to the first input terminal of the second operational amplifier module.

[0058] A signal absorption module is disposed on the connection circuit between the second terminal of the second transistor and the second input terminal of the second operational amplifier module, and on the connection circuit between the second terminal of the fourth transistor and the first input terminal of the second operational amplifier module, for reducing charge injection and clock feedthrough introduced by the first, second, and fourth transistors during switching; wherein,

[0059] When the bandgap buffer circuit is in the sampling state, the first transistor, the second transistor, and the fourth transistor are in the conducting state, while the third transistor and the signal absorption module are in the disconnected state.

[0060] When the bandgap buffer circuit is in the amplification state, the third transistor and the signal absorption module are in the conducting state, while the first transistor, the second transistor, and the fourth transistor are in the disconnected state.

[0061] In the embodiments of this application, the bandgap buffer circuit can be adjusted to different states by controlling each transistor, and the nonlinear effects such as clock feedthrough and charge injection in the circuit can be absorbed by the signal absorption module to further optimize the accuracy of the output voltage.

[0062] In one possible implementation, the signal absorption module includes:

[0063] The fifth transistor, wherein the first terminal and the second terminal of the fifth transistor are electrically connected to the second input terminal of the second operational amplifier module and the second terminal of the second transistor;

[0064] The sixth transistor has its first and second terminals electrically connected to the first input terminal of the second operational amplifier module and the second terminal of the fourth transistor.

[0065] In one possible implementation, the bandgap buffer circuit further includes a clock module for outputting a first clock signal and a second clock signal with opposite phases, wherein the first clock signal is used to control the on and off states of the first transistor, the second transistor, and the fourth transistor, and the second clock signal is used to control the on and off states of the fifth transistor and the sixth transistor.

[0066] The embodiments of this application can control the fifth and sixth transistors to absorb the charge injection and clock feedthrough introduced by the first, second and fourth transistors during switching using the clock signal output by the clock module. The overall control logic is simple and easy to implement.

[0067] In one possible implementation, the fifth transistor is half the size of the second transistor, and the sixth transistor is half the size of the first transistor.

[0068] Setting the size of the fifth transistor to half that of the second transistor and the size of the sixth transistor to half that of the first transistor can effectively ensure that the signal absorption module absorbs the charge injection and clock feedthrough introduced by the first, second, and fourth transistors during switching.

[0069] In one possible implementation, the fourth charge storage module and the first transistor are also used to isolate the reverse input electrical signal of the subsequent load.

[0070] The embodiments of this application can effectively isolate the crosstalk or influence of the subsequent load on the bandgap voltage generation circuit through the fourth charge storage module and the first transistor.

[0071] Secondly, embodiments of this application provide an SDM circuit, including a bandgap reference circuit as described in any of the first aspects.

[0072] Thirdly, embodiments of this application provide an integrated circuit chip, including a bandgap reference circuit as described in any of the first aspects. Attached Figure Description

[0073] Figure 1 is a circuit block diagram of a bandgap reference circuit provided in an embodiment of this application;

[0074] Figure 2 is a circuit block diagram of a bandgap voltage generation circuit provided in an embodiment of this application;

[0075] Figure 3 is a circuit block diagram of another bandgap voltage generation circuit provided in an embodiment of this application;

[0076] Figure 4 is a schematic diagram of the circuit structure of a bandgap voltage generation circuit provided in an embodiment of this application;

[0077] Figure 5 is an equivalent circuit diagram of a bandgap voltage generation circuit in the sampling state provided in an embodiment of this application;

[0078] Figure 6 is an equivalent circuit diagram of a bandgap voltage generation circuit in the amplified state provided in an embodiment of this application;

[0079] Figure 7 is a circuit block diagram of a bandgap buffer circuit provided in an embodiment of this application;

[0080] Figure 8 is a schematic diagram of the circuit structure of a bandgap buffer circuit provided in an embodiment of this application;

[0081] Figure 9 is an equivalent circuit diagram of a bandgap buffer circuit in the sampling state provided in an embodiment of this application;

[0082] Figure 10 is an equivalent circuit diagram of a bandgap buffer circuit in the amplified state provided in an embodiment of this application;

[0083] Figure 11 is a structural block diagram of an SDM circuit provided in an embodiment of this application;

[0084] Figure 12 is a structural block diagram of an integrated circuit chip provided in an embodiment of this application. Detailed Implementation

[0085] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0086] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0087] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0088] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0089] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0090] In this application, a transistor is a semiconductor device for controlling current, also known as a semiconductor transistor, bipolar junction transistor (BJT), or crystal transistor. The first and second terminals of the transistor are the high-potential and low-potential terminals on the current path, respectively. The control terminal is used to receive a drive signal to control the transistor's output current. Transistors can be classified into PNP and NPN types. In a PNP transistor, the first, second, and control terminals are the emitter, collector, and base, respectively; in an NPN transistor, the first, second, and control terminals are the collector, emitter, and base, respectively.

[0091] In this application, the transistor is a transistor operating in linear mode to provide a current path, including a type selected from bipolar transistors or field-effect transistors. The first terminal and the second terminal of the transistor are respectively a high-potential terminal and a low-potential terminal on the current path, and the control terminal is used to receive a drive signal to control the voltage drop of the transistor. The transistor can be a P-type MOSFET or an N-type MOSFET. For a P-type MOSFET, the first terminal, the second terminal, and the control terminal are the source, the drain, and the gate, respectively; for an N-type MOSFET, the first terminal, the second terminal, and the control terminal are the drain, the source, and the gate, respectively.

[0092] Currently, the technology of bandgap reference circuits mainly focuses on the following aspects:

[0093] By using operational amplifier clamping, a positive temperature coefficient voltage is generated. This voltage is then superimposed with a negative temperature coefficient voltage at a certain ratio to obtain a temperature-independent bandgap reference voltage. This is the traditional continuous-time bandgap reference architecture. Its advantages are simple circuit design, easy-to-understand circuit principle, and relatively high PSR.

[0094] However, each of the above solutions also has its own disadvantages:

[0095] Due to op-amp clamping, an offset voltage (Vos) is introduced into the op-amp's equivalent input. This Vos is multiplied by a scaling factor and reflected in the final reference voltage Vref output accuracy. The larger the Vos, the worse the Vref output voltage accuracy. Even if the voltage trimming mechanism is used to remove the effects of process corner deviations, the Vref accuracy is still affected by mismatches between components. Even if clipping stabilization technology (Chopper) + bandgap reference (BG) is used to solve the above-mentioned impact of op-amp offset on output voltage accuracy, Chopper + BG will bring the defects of large on-chip filter and large dynamic power consumption. In addition, the traditional structure does not have high-order temperature compensation methods, and the temperature drift performance of the final output reference voltage is poor, mostly around 35ppm / ℃. Adding high-order compensation circuits will make the circuit structure complex and relatively difficult to implement. 1 / f noise cancellation methods have large area costs. In other words, if the output voltage of a continuous bandgap reference circuit is to achieve a certain accuracy and temperature drift characteristics, a great deal of effort is required.

[0096] To address the aforementioned issues, this application provides a bandgap reference circuit, an SDM circuit, and an integrated circuit chip. This bandgap reference circuit effectively avoids the problems of high complexity in the output voltage temperature characteristic compensation circuit, large area cost for 1 / f noise cancellation, and high cost in accuracy and temperature drift calibration inherent in continuous bandgap reference circuits.

[0097] The following explanation is provided in conjunction with the accompanying drawings.

[0098] Referring to Figure 1, a circuit block diagram of a bandgap reference circuit provided in an embodiment of this application is shown. As shown in Figure 1, the bandgap reference circuit includes a bandgap voltage generation circuit 100 and a bandgap buffer circuit 200, wherein the output terminal of the bandgap voltage generation circuit 100 is electrically connected to the input terminal of the bandgap buffer circuit 200. During the operation of the bandgap reference circuit, the bandgap voltage generation circuit 100 is used to generate a bandgap voltage (reference voltage) and performs first-order and higher-order temperature compensation on the generated bandgap voltage to ensure that the output bandgap voltage has high accuracy and temperature characteristics. The bandgap buffer circuit 200 is used to isolate the reverse input electrical signal of the subsequent load, so that the subsequent load cannot affect or cause crosstalk to the bandgap voltage generation circuit 100.

[0099] Referring to Figure 2, a circuit block diagram of a bandgap voltage generation circuit provided in an embodiment of this application is shown. As shown in Figure 2, the bandgap voltage generation circuit 100 includes a first operational amplifier module 110, a first charge storage module 120, a second charge storage module 130, and a third charge storage module 140. When the bandgap voltage generation circuit 100 is in sampling mode, its circuit connection relationship is shown in Figure 2(a). Specifically, the first terminal of the first charge storage module 120 is electrically connected to the first input terminal of the first operational amplifier module 110, the second terminal of the first charge storage module 120 is electrically connected to the second input terminal and the output terminal of the first operational amplifier module 110, the first terminal of the second charge storage module 130 is electrically connected to the second input terminal of the first operational amplifier module 110, and the first terminal of the third charge storage module 140 is electrically connected to the second input terminal of the first operational amplifier module 110. When the bandgap voltage generation circuit is in amplification mode, its circuit connection is shown in Figure 2(b). Specifically, the first terminal of the first charge storage module 120 is electrically connected to the output terminal of the first operational amplifier module 110, the second terminal of the first charge storage module 120 is electrically connected to the second input terminal of the first operational amplifier module 110, the first terminal of the second charge storage module 130 is electrically connected to the second input terminal of the first operational amplifier module 110, and the first terminal of the third charge storage module 140 is electrically connected to the second input terminal of the first operational amplifier module 110. During the operation of the bandgap voltage generation circuit 100, the first charge storage module 120, the second charge storage module 130, and the third charge storage module 140 are used to store the input noise 1 / f and offset voltage VOS of the first operational amplifier module 110 when the bandgap voltage generation circuit 100 is in sampling mode, and to perform input noise and offset voltage VOS compensation, as well as first-order and higher-order temperature compensation, on the bandgap voltage VBG output from the output terminal of the first operational amplifier module 110 when the bandgap voltage generation circuit 100 is in amplification mode.

[0100] In one possible implementation, as shown in Figure 3, the bandgap voltage generation circuit 100 further includes a first voltage generation module 150, a second voltage generation module 160, a third voltage generation module 170, a fourth voltage generation module 180, and a fifth voltage generation module 190. When the bandgap voltage generation circuit 100 is in sampling mode, its circuit connection is shown in Figure 3(a). Specifically, the output terminal of the first voltage generation module 150 is electrically connected to the first input terminal of the first operational amplifier module 110, and is used to output a first voltage with a positive temperature coefficient; the output terminal of the second voltage generation module 160 is electrically connected to the second terminal of the second charge storage module 130, and is used to output a second voltage with a positive temperature coefficient; the output terminal of the fourth voltage generation module 180 is electrically connected to the second terminal of the third charge storage module 140, and is used to output a fourth voltage with a positive temperature coefficient. When the bandgap voltage generation circuit is in amplification mode, its circuit connection is shown in Figure 3(b). Specifically, the output terminal of the first voltage generation module 150 is electrically connected to the first input terminal of the first operational amplifier module 110 to output a first voltage with a positive temperature coefficient; the output terminal of the third voltage generation module 170 is electrically connected to the second terminal of the second charge storage module 130 to output a third voltage with a positive temperature coefficient; and the output terminal of the fifth voltage generation module 190 is electrically connected to the second terminal of the third charge storage module 140 to output a fifth voltage with a zero temperature coefficient.

[0101] The following description, in conjunction with the accompanying drawings, further explains each module in the bandgap voltage generation circuit 100.

[0102] Referring to Figure 4, a schematic diagram of the circuit structure of a bandgap voltage generation circuit provided in an embodiment of this application is shown. As shown in Figure 4, the first operational amplifier module 110 includes a first operational amplifier A1, the first charge storage module 120 includes a first capacitor C1, the second charge storage module 130 includes a second capacitor C2, the third charge storage module 140 includes a third capacitor C3, the first voltage generation module 150 includes a first positive temperature coefficient bias current I1 and a first transistor VBE1, the second voltage generation module 160 includes a second positive temperature coefficient bias current I2 and a second transistor VBE2, the third voltage generation module 170 includes a second positive temperature coefficient bias current I2 and a third transistor VBE3, the fourth voltage generation module 180 includes a third positive temperature coefficient bias current I3 and a fourth transistor VBE4, and the fifth voltage generation module 190 includes a zero temperature coefficient bias current I4 and a fifth transistor VBE5.

[0103] In specific implementation, the output terminal of the first positive temperature coefficient bias current I1 is electrically connected to the first terminal of the first transistor VBE1, the first terminal of the first transistor VBE1 is electrically connected to the positive input terminal (first input terminal) of the first operational amplifier A1, the control terminal of the first transistor VBE1 is electrically connected to the second terminal of the first transistor VBE1, and the second terminal of the first transistor VBE1 is grounded; the positive input terminal of the first operational amplifier A1 is electrically connected to the first terminal of the first capacitor C1 through the third switch S3, and the output terminal of the first operational amplifier A1 is electrically connected to the inverting input terminal (first input terminal) of the first operational amplifier A1 through the first switch S1. The first input terminal of the first capacitor C1 is electrically connected to the output terminal of the first operational amplifier A1 via the second switch S2, and the second terminal of the first capacitor C1 is electrically connected to the inverting input terminal of the first operational amplifier A1. The output terminal of the second positive temperature coefficient bias current I2 is electrically connected to the first terminal of the second transistor VBE2 via the fourth switch S4, and the first terminal of the second transistor VBE2 is electrically connected to the second terminal of the second capacitor C2 via the fifth switch S5. The control terminal of the second transistor VBE2 is electrically connected to the second terminal of the second transistor VBE2, and the second terminal of the second transistor VBE2 is grounded. The output terminal of the positive temperature coefficient bias current I2 is also electrically connected to the first terminal of the third transistor VBE3 through the sixth switch S6. The first terminal of the third transistor VBE3 is electrically connected to the second terminal of the second capacitor C2 through the seventh switch S7. The control terminal of the third transistor VBE3 is electrically connected to the second terminal of the third transistor VBE3, and the second terminal of the third transistor VBE3 is grounded. The first terminal of the second capacitor C2 is electrically connected to the inverting input terminal of the first operational amplifier A1. The output terminal of the third positive temperature coefficient bias current I3 is electrically connected to the first terminal of the fourth transistor VBE4, and the first terminal of the fourth transistor VBE4 is connected to the second terminal of the third transistor VBE3 through the seventh switch S7. The eighth switch S8 is electrically connected to the second terminal of the third capacitor C3. The control terminal of the fourth transistor VBE4 is electrically connected to the second terminal of the fourth transistor VBE4, and the second terminal of the fourth transistor VBE4 is grounded. The output terminal of the zero temperature coefficient bias current I4 is electrically connected to the first terminal of the fifth transistor VBE5. The first terminal of the fifth transistor VBE5 is electrically connected to the second terminal of the third capacitor C3. The control terminal of the fifth transistor VBE5 is electrically connected to the second terminal of the fifth transistor VBE5, and the second terminal of the fifth transistor VBE5 is grounded. The first terminal of the third capacitor C3 is electrically connected to the inverting input terminal of the first operational amplifier A1.

[0104] In specific implementation, when the bandgap voltage generation circuit 100 is in sampling mode, the first switch S1, the third switch S3, the fourth switch S4, the fifth switch S5, and the eighth switch S8 are closed, while the second switch S2, the sixth switch S6, the seventh switch S7, and the ninth switch S9 are open. At this time, the 1 / f noise and offset voltage VOS1 of the first operational amplifier A1 are stored in the first capacitor C1, the second capacitor C2, and the third capacitor C3. When the bandgap voltage generation circuit 100 is in amplification mode, the second switch S2, the sixth switch S6, the seventh switch S7, and the ninth switch S9 are closed, while the first switch S1, the third switch S3, the fourth switch S4, the fifth switch S5, and the eighth switch S8 are open. At this time, the 1 / f noise and offset voltage VOS1 stored in the first capacitor C1, the second capacitor C2, and the third capacitor C3 can be used to compensate for the output bandgap voltage VBG. Furthermore, by selecting appropriate first capacitor C1, second capacitor C2, and third capacitor C3, a temperature-independent bandgap voltage VBG can be obtained. In other words, the embodiments of this application can utilize an auto-zero circuit to attenuate the effects of operational amplifier offset and 1 / f noise. At the same time, by selecting appropriate first capacitor C1, second capacitor C2 and third capacitor C3, the first and higher order terms of the circuit temperature coefficient can be eliminated.

[0105] In this embodiment, the bandgap voltage generation circuit 100 has two operating modes: one is the sampling mode and the other is the amplification mode. The two modes are alternated to ensure the accuracy and temperature characteristics of the output bandgap voltage.

[0106] The following example illustrates the operating mode of the bandgap voltage generation circuit 100 in the sampling state.

[0107] In the sampling state, the first switch S1, the third switch S3, the fourth switch S4, the fifth switch S5, and the eighth switch S8 are closed, while the second switch S2, the sixth switch S6, the seventh switch S7, and the ninth switch S9 are open, forming the equivalent circuit diagram of the bandgap voltage generation circuit shown in Figure 5. As shown in Figure 5, the first terminal of the first capacitor C1 is electrically connected to the positive input terminal of the first operational amplifier A1, the second terminal of the first capacitor C1 is electrically connected to the inverting input terminal of the first operational amplifier A1, the output terminal of the first operational amplifier A1 is electrically connected to the inverting input terminal of the first operational amplifier A1, the first terminal of the second capacitor C2 is electrically connected to the inverting input terminal of the first operational amplifier A1, the second terminal of the second capacitor C2 is electrically connected to the output terminal of the second voltage generation module 150, the first terminal of the third capacitor C3 is electrically connected to the inverting input terminal of the first operational amplifier A1, and the second terminal of the third capacitor C3 is electrically connected to the output terminal of the fourth voltage generation module 180.

[0108] In practice, since the first positive temperature coefficient bias current I1 = the second positive temperature coefficient bias current I2 = the third positive temperature coefficient bias current I3, that is, the first transistor VBE1, the second transistor VBE2 and the fourth transistor VBE4 are biased by the same positive temperature coefficient current (PTAT), and the number m of the parallel connection of the first transistor VBE1, the second transistor VBE2 and the fourth transistor VBE4 is 1, it can be concluded that the voltage between the base and emitter of the first transistor VBE1, the second transistor VBE2 and the fourth transistor VBE4 are equal, that is, VBE1 = VBE2 = VBE4. At this time, the bandgap voltage generation circuit 100 stores the equivalent input noise 1 / f and offset voltage VOS1 of the first operational amplifier module 110. Specifically, it stores the corresponding charge on the first capacitor C1, the second capacitor C2, and the third capacitor C3. The charge generation formula is: [VBE1-(VBE1-VOS1)]C1+[VBE2-(VBE1-VOS1)]C2+[VBE4-(VBE1-VOS1)]C3=Q1 (1)

[0109] Based on VBE1=VBE2=VBE4, formula (1) is simplified to: VOS1*C1+COS1*C2+COS1*C3=Q1 (2)

[0110] The formula for obtaining VBG is: VBG=VBE-VOS1 (3)

[0111] In formula (3), VBE = VBE1 = VBE2 = VBE4.

[0112] The following example illustrates the operating mode of the bandgap voltage generation circuit 100 in the amplification state.

[0113] In the amplified state, the second switch S2, the sixth switch S6, the seventh switch S7, and the ninth switch S9 are closed, while the first switch S1, the third switch S3, the fourth switch S4, the fifth switch S5, and the eighth switch S8 are open, forming the equivalent circuit diagram of the bandgap voltage generation circuit shown in Figure 6. As shown in Figure 6, the first terminal of the first capacitor C1 is electrically connected to the output terminal of the first operational amplifier A1, and the second terminal of the first capacitor C1 is electrically connected to the inverting input terminal of the first operational amplifier A1. The first terminal of the second capacitor C2 is electrically connected to the inverting input terminal of the first operational amplifier A1, and the second terminal of the second capacitor C2 is electrically connected to the output terminal of the third voltage generation module 160. The first terminal of the third capacitor C3 is electrically connected to the inverting input terminal of the first operational amplifier A1, and the second terminal of the third capacitor C3 is electrically connected to the output terminal of the fifth voltage generation module 190.

[0114] In practice, since the bias currents of the first transistor VBE1 and the third transistor VBE3 are IPTAT positive temperature coefficient currents, and the bias current of the fifth transistor VBE5 is the zero temperature coefficient current (Complementary To Absolute Temperature, CTAT), the charge formula can be obtained as: [VBE3-(VBE1-VOS1)]C2+[VBE5-(VBE1-VOS1)]C3+[VBG-(VBE1-BOS1)]C1=Q2 (4)

[0115] Simplifying formula (4), we get: VBE3*C2+VBE5*C3+VBG*C1-VBE1*(C1+C3+C2)+VOS1*(C1+C2+C3)=Q2 (5) According to the principle of charge conservation: Q1=Q2, we can get: VBE3*C2+VBE5*C3+VBG*C1-VBE1*(C1+C3+C2)+VOS1*(C1+C2+C3) =VOS1*C1+VOS1*C2+VOS1*C3 (6)

[0116] Simplifying formula (6) yields: VBE3*C2+VBE5*C3+VBG*C1-VBE1*(C1+C2+C3)=0 (7)

[0117] Transforming formula (7), we get: VBG*C1=VBE1*C2-VBE3*C2+VBE1*C3-VBE5*C3+VBE1*C1 (8)

[0118] The formula for calculating VBE is:

[0119] In formula (9), V T The threshold voltage of the transistor is approximately 26mV, I. C I is the collector current of the transistor. S The saturation current of a transistor.

[0120] Equal positive temperature coefficient currents IPTAT are used to bias VBE1 (m=1) and VBE3 (m=24) respectively to obtain positive temperature coefficient voltages:

[0121] I s1 I is the saturation current of the first transistor. s3 The saturation current of the third transistor

[0122] The VBE recursive formula for temperature is:

[0123] In formula (11), Vg0 is the bandgap reference voltage, T0 is the corresponding reference temperature point, VBE0 is the VBE value at the corresponding reference temperature point, α represents the relationship between the collector current of the bias bipolar and the temperature, η is a process-related parameter, and T is the actual temperature.

[0124] Another formula for the bandgap reference voltage is: VBG=VBE+ΔVBE*K1 (12)

[0125] In formula (12), K1 represents the proportional coefficient, a constant related to circuit design. During the design process, the value of K1 can be finely adjusted through experimental data or simulation results to achieve the optimal temperature compensation effect. ΔVBE= It is directly proportional to temperature.

[0126] Substituting equation (11) into equation (12) and taking the partial derivative with respect to temperature:

[0127] According to formula (13), in order to obtain a reference voltage (bandgap voltage) that is independent of temperature, it is necessary to remove the first-order and higher-order terms that are related to temperature in formula (13). The circuit scheme of the present application embodiment can achieve the above objective.

[0128] Specifically, when VBE is biased by a zero-temperature current IZTAT, α = 0:

[0129] When VBE is biased by a positive temperature current IPTAT, α = 1:

[0130] In the bandgap voltage generation circuit of this application embodiment, the bias current of VBE1 is the positive temperature coefficient current (IPTAT), and the bias current of VBE5 is the zero temperature coefficient current (IZTAT). According to formulas (14) and (15), we can obtain:

[0131] Substituting formulas (17), (18), and (10) into formula (8), we get:

[0132] From formula (20), it can be seen that when the capacitance values ​​of the first capacitor C1 and the third capacitor C3 satisfy C3=C1*(η-1), the higher-order terms related to temperature in the above formula will be eliminated, and at this time we have:

[0133] Formula K is the Boltzmann constant, and q is the unit charge. Substituting these values ​​into formula (21), we get:

[0134] Taking the partial derivative of formula (22) with respect to temperature T, we get:

[0135] According to formula (22), if:

[0136] When the capacitance values ​​of the first capacitor C1 and the second capacitor C2 satisfy the relationship of formula (24), we can obtain:

[0137] Based on the above derivation, by appropriately selecting the ratio between C1, C2, and C3, a temperature-independent output voltage VBG can be obtained. The output value of VBG is:

[0138] In practical applications, although there are many non-ideal factors in circuit design, which cause the reference voltage (bandgap voltage) output by the actual circuit to still have a certain temperature coefficient, the solution of the bandgap voltage generation circuit in the embodiment of this application can greatly improve the temperature drift performance of the output voltage.

[0139] In practical applications, besides designing the bandgap voltage generation circuit itself to improve the accuracy and temperature characteristics of the output bandgap voltage, it is also necessary to pay attention to the crosstalk or influence of the downstream load on the bandgap voltage generation circuit. Based on this, embodiments of this application provide a bandgap buffer circuit to isolate the reverse input electrical signal from the downstream load.

[0140] Referring to Figure 7, a circuit block diagram of a bandgap buffer circuit provided in an embodiment of this application is shown. As shown in Figure 7, the bandgap buffer circuit 200 includes a second operational amplifier module 210, a fourth charge storage module 220, and a fifth charge storage module 230.

[0141] The first input terminal of the second operational amplifier module 210 is electrically connected to the output terminal of the bandgap voltage generation circuit 100, and is used to receive the bandgap voltage VBG output by the bandgap voltage generation circuit 100. The output terminal of the second operational amplifier module 210 is used to output voltage VOUT to the subsequent load.

[0142] The first terminal of the fourth charge storage module 220 is electrically connected to the first input terminal of the second operational amplifier module 210, and the second terminal of the fourth charge storage module 220 is grounded (not shown in the figure). When the bandgap buffer circuit 200 is in the sampling state, the fourth charge storage module 220 is used to store the bandgap voltage VBG. When the bandgap buffer circuit 200 is in the amplification state, the fourth charge storage module 200 is used to output the stored bandgap voltage VBG.

[0143] When the bandgap buffer circuit 200 is in the sampling state, as shown in Figure 7(a), the first terminal of the fifth charge storage module 230 is electrically connected to the second input terminal and the output terminal of the second operational amplifier module 210, and the second terminal of the fifth charge storage module 230 is electrically connected to the first input terminal of the second operational amplifier module 210. The fifth charge storage module 230 is used to store the input noise and offset voltage VOS2 of the second operational amplifier module 210. When the bandgap buffer circuit 200 is in the amplification state, as shown in Figure 7(b), the first terminal of the fifth charge storage module 230 is electrically connected to the second input terminal of the second operational amplifier module 210, and the second terminal of the fifth charge storage module 230 is electrically connected to the output terminal of the second operational amplifier module 210. The fifth charge storage module 230 is used to perform voltage compensation on the second operational amplifier module 210.

[0144] In a specific implementation, as shown in Figure 8, the second operational amplifier module 210 includes a second operational amplifier A2, the fourth charge storage module 220 includes a fourth capacitor C4, the fifth charge storage module 230 includes a fifth capacitor C5, and the bandgap buffer circuit 200 also includes a first transistor P1, a second transistor P2, a third transistor P3, a fourth transistor P4, and a signal absorption module 240. Specifically, the first terminal of the first transistor P1 is electrically connected to the output terminal of the bandgap voltage generation circuit 100, the second terminal of the first transistor P1 is electrically connected to the positive input terminal (first input terminal) of the second operational amplifier A2 and the first terminal of the fourth capacitor C4, the first terminal of the fourth capacitor C4 is electrically connected to the positive input terminal of the second operational amplifier A2, and the second terminal of the fourth capacitor C4 is grounded; the first terminal of the second transistor P2 is electrically connected to the output terminal of the second operational amplifier A2, the second terminal of the second transistor P2 is electrically connected to the inverting input terminal (second input terminal) of the second operational amplifier A2 and the first terminal of the fifth capacitor C5, the first terminal of the fifth capacitor C5 is also electrically connected to the inverting input terminal of the second operational amplifier A2; the first terminal of the third transistor P3 is electrically connected to the first transistor P4, the second terminal of the third transistor P2 is electrically connected to the second transistor P2, the fourth transistor P4, the fifth transistor P5, the fifth transistor P4, the fifth transistor P5, the fifth transistor P5, the fifth transistor P2 ... The output terminal of the second operational amplifier A2 is electrically connected; the second terminal of the third transistor P3 is electrically connected to the second terminal of the fifth capacitor C5; the first terminal of the fourth transistor P4 is electrically connected to the second terminal of the fifth capacitor C5 and the second terminal of the third transistor P3; the second terminal of the fourth transistor P4 is electrically connected to the positive input terminal of the second operational amplifier A2; the signal absorption module 240 is disposed on the connection circuit between the second terminal of the second transistor P2 and the inverting input terminal of the second operational amplifier A2, and on the connection circuit between the second terminal of the fourth transistor P4 and the inverting input terminal of the second operational amplifier A2. The signal absorption module 240 is used to reduce the charge injection and clock feedthrough introduced by the first transistor P1, the second transistor P2 and the fourth transistor P4 during switching.

[0145] In one possible implementation, as shown in Figure 8, the signal absorption module 240 includes a fifth transistor P5 and a sixth transistor P6. The first and second terminals of the fifth transistor P5 are electrically connected to the inverting input of the second operational amplifier A2 and the second terminal of the second transistor P2. The first and second terminals of the sixth transistor P6 are electrically connected to the positive input of the second operational amplifier A2 and the second terminal of the fourth transistor P4. Specifically, the size of the fifth transistor P5 is half that of the second transistor P2, and the size of the sixth transistor P6 is half that of the first transistor P1.

[0146] In this embodiment, the size of the fifth transistor is set to 1 / 2 of the size of the second transistor, and the size of the sixth transistor is set to 1 / 2 of the size of the first transistor. This can effectively ensure that the signal absorption module absorbs the charge injection and clock feedthrough introduced by the first, second, and fourth transistors during switching.

[0147] In one possible implementation, the bandgap buffer circuit 200 further includes a clock module (not shown in the figure), which is used to output a first clock signal and a second clock signal with opposite phases. The first clock signal is used to control the on and off states of the first transistor, the second transistor, and the fourth transistor, and the second clock signal is used to control the on and off states of the fifth transistor and the sixth transistor.

[0148] In this embodiment, the clock signal output by the clock module controls the fifth and sixth transistors to absorb the charge injection and clock feedthrough introduced by the first, second, and fourth transistors during switching. The overall control logic is simple and easy to implement.

[0149] In specific implementation, when the bandgap buffer circuit 200 is in the sampling state, the first transistor P1, the second transistor P2, and the fourth transistor P4 are in the conducting state, while the third transistor P3, the fifth transistor P5, and the sixth transistor P6 are in the off state, so that the fourth capacitor C4 stores the received bandgap voltage VBG, and the fifth capacitor C5 stores the input noise and offset voltage VOS2 of the second operational amplifier A2; when the bandgap buffer circuit 200 is in the amplification state, the third transistor P3, the fifth transistor P5, and the sixth transistor P6 are in the conducting state, while the first transistor P1, the second transistor P2, and the fourth transistor P4 are in the off state, so that the fourth capacitor C4 outputs the stored bandgap voltage VBG, and the fifth capacitor C5 performs voltage compensation on the output voltage of the second operational amplifier A2.

[0150] The embodiments of this application can attenuate the offset and 1 / f noise of the second operational amplifier module through the Auto-zero circuit, and reduce nonlinear effects such as charge injection and clock feedthrough in the bandgap buffer circuit through the signal absorption module, thereby optimizing the output voltage accuracy.

[0151] In this embodiment, the fourth capacitor C4 and the first transistor P1 can also form a filter circuit to isolate the reverse input electrical signal of the subsequent load so that the subsequent load will not cause crosstalk or affect the bandgap voltage generation circuit.

[0152] In this embodiment, the bandgap buffer 200 has two operating modes: one is the sampling mode and the other is the amplification mode. The two modes are alternated to ensure the accuracy and temperature characteristics of the output voltage VOUT.

[0153] The following example illustrates the operating mode of the bandgap buffer circuit 200 in the sampling state.

[0154] In the sampling state, the first transistor P1, the second transistor P2, and the fourth transistor P4 are turned on, while the third transistor P3, the fifth transistor P5, and the sixth transistor P6 are turned off, forming the equivalent circuit diagram of the bandgap buffer circuit shown in Figure 9. As shown in Figure 9, the first terminal of the fourth capacitor C4 is electrically connected to the bandgap voltage generation circuit and the positive input terminal of the second operational amplifier A2. The first terminal of the fifth capacitor C5 is electrically connected to the inverting input terminal and the output terminal of the second operational amplifier A2, and the second terminal of the fifth capacitor C5 is electrically connected to the positive input terminal of the second operational amplifier A2.

[0155] Specifically, when the bandgap buffer circuit is in the active state, the bandgap voltage generation circuit is in the amplification state. That is, the first transistor P1 is turned on when the bandgap voltage generation circuit is in the amplification state to sample the bandgap voltage VBG output by the bandgap voltage generation circuit. Due to the presence of the fifth capacitor C5, the input noise and offset voltage VOS2 of the second operational amplifier A2 are stored, resulting in the charge formula: [VBG-(VBG-VOS2)]C5=Q3 (27) VOUT=VBG-VOS2 (28)

[0156] The following example illustrates the operating mode of the bandgap buffer circuit 200 in the amplification state.

[0157] In amplification mode, the third transistor P3, the fifth transistor P5, and the sixth transistor P6 are turned on, and the ports of the first transistor P1, the second transistor P2, and the fourth transistor P4 form the equivalent circuit diagram of the bandgap buffer circuit shown in Figure 10. As shown in Figure 10, the first terminal of the fourth capacitor C4 is electrically connected to the positive input terminal of the second operational amplifier A2, the first terminal of the fifth capacitor C5 is electrically connected to the inverting input terminal of the second operational amplifier A2, and the second terminal of the fifth capacitor C5 is electrically connected to the output terminal of the second operational amplifier A2.

[0158] In specific implementation, when the bandgap buffer circuit 200 is in the amplification state, the first transistor P1 is turned off, and the bandgap voltage VBG sampled by the first transistor P1 is stored on the fourth capacitor C4. At this time, the charge formula is obtained: [VOUT-(V1-VOS2)]C5=Q4 (29)

[0159] According to the principle of charge conservation: Q3=Q4, we get: [VBG-(VBG-VOS2)]C5=[VOUT-(V1-VOS2)]C5 (30)

[0160] If the charge injection and clock feedthrough introduced when the first transistor P1, the second transistor P2 and the fourth transistor P4 are switched are well absorbed by the signal absorption module 240, then VB = V1. Substituting this into formula (30), we get: VOUT = V1 = VBG = Vg0 (31)

[0161] As can be seen from formula (31), the embodiment of this application absorbs the charge injection and clock feedthrough introduced when the first transistor P1, the second transistor P2 and the fourth transistor P4 are switched by the signal absorption module, attenuates the offset voltage and 1 / f noise of the second operational amplifier module by the Auto-zero circuit, and can effectively isolate the crosstalk and kickback of the subsequent load to the bandgap voltage generation circuit, so that the output voltage VOUT is no different from the high-precision, low-temperature drift and low-noise bandgap voltage VBG output by the bandgap voltage generation circuit.

[0162] In the embodiments of this application, the presentation of each state (phase) in the bandgap voltage generation circuit and / or bandgap buffer circuit requires the presence of a non-overlapping clock. The embodiments of this application control the conduction and turn-off of each switch and each transistor by creating three stages of non-overlapping clock phases, thereby realizing the state switching of the above circuit, and relying on charge conservation, finally completing the analysis and design of the bandgap reference circuit.

[0163] The bandgap reference circuit of this application embodiment not only efficiently superimposes the positive temperature term voltage, negative temperature term voltage, and higher-order temperature term voltage, but also uses the Auto-zero method to greatly attenuate the performance impact of the operational amplifier's equivalent input offset and equivalent input 1 / f noise on the output voltage. It effectively avoids the problems of high complexity of the output voltage temperature characteristic compensation circuit of continuous bandgap reference circuit, large area cost of 1 / f noise elimination method, and high cost of accuracy and temperature drift calibration.

[0164] In one possible implementation, embodiments of this application can also adjust the driving capability of the circuit by adjusting the bias current of the bandgap voltage generation circuit to adapt to different bandgap voltage loads. Specifically, the bias current can be increased to adapt to heavier loads.

[0165] Corresponding to the above embodiments, this application also provides an SDM (Sigma-Delta Modulator) circuit.

[0166] Referring to Figure 11, this is a structural block diagram of an SDM circuit provided in an embodiment of this application. As shown in Figure 11, the SDM circuit 1100 includes a bandgap reference circuit 1101. The specific details of the bandgap reference circuit 1101 can be found in the description of the above embodiments, and will not be repeated here for the sake of brevity.

[0167] In a high-precision SDM system, a low-noise, high-precision, and low-temperature-drift reference voltage source is crucial. The circuit structure of this application embodiment is used in an SDM system as a reference source for high-precision measurement, which can greatly improve the performance of the high-precision measurement system.

[0168] Corresponding to the above embodiments, this application also provides an integrated circuit chip.

[0169] Referring to Figure 12, it is a structural block diagram of an integrated circuit chip provided in an embodiment of this application. As shown in Figure 12, the integrated circuit chip 1200 includes a bandgap reference circuit 1101. The specific contents of the bandgap reference circuit 1101 can be found in the description of the above embodiments, and will not be repeated here for the sake of brevity.

[0170] In specific implementations, the microprocessor chip can be, for example, a control module, a microcontroller unit (MCU), a digital signal processor (DSP), a microprocessor unit (MPU), a micro CPU, or a miniature central control chip or system-on-a-chip that can process digital signals, analog signals, or perform signal control, instruction processing, and computation functions.

[0171] Corresponding to the above embodiments, this application also provides a computer-readable storage medium, wherein the computer-readable storage medium may store a program, wherein when the program runs, it can control the device where the computer-readable storage medium is located to execute some or all of the steps in the above method embodiments. Specifically, the computer-readable storage medium may be a magnetic disk, an optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0172] Corresponding to the above embodiments, this application also provides a computer program product containing executable instructions that, when executed on a computer, cause the computer to perform some or all of the steps in the above method embodiments.

[0173] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, the simultaneous existence of A and B, or the existence of B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0174] Those skilled in the art will recognize that the units and algorithm steps described in the embodiments disclosed herein can be implemented using electronic hardware, computer software, or a combination of electronic hardware and software. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0175] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0176] In the several embodiments provided in this application, any function, if implemented as a software functional unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0177] The above description is merely a specific implementation of the embodiments of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the protection scope of the embodiments of this application. The protection scope of the embodiments of this application should be determined by the protection scope of the claims.

Claims

A bandgap reference circuit, characterized in that, include: A bandgap voltage generation circuit is used to generate a bandgap voltage and perform first-order and higher-order temperature compensation on the generated bandgap voltage. A bandgap buffer circuit, electrically connected to the output of the bandgap voltage generation circuit, is used to isolate the reverse input electrical signal of the subsequent load. The bandgap reference circuit according to claim 1 is characterized in that, The bandgap voltage generation circuit includes: First operational amplifier module; The first charge storage module, when the bandgap voltage generation circuit is in sampling mode, has its first terminal electrically connected to the first input terminal of the first operational amplifier module, and its second terminal electrically connected to the second input terminal and the output terminal of the first operational amplifier module. When the bandgap voltage generation circuit is in amplification mode, the first terminal of the first charge storage module is electrically connected to the output terminal of the first operational amplifier module, and its second terminal is electrically connected to the second input terminal of the first operational amplifier module. The second charge storage module has its first terminal electrically connected to the second input terminal of the first operational amplifier module. A third charge storage module, wherein the first terminal of the third charge storage module is electrically connected to the second input terminal of the first operational amplifier module; The first charge storage module, the second charge storage module, and the third charge storage module are used to store the input noise and offset voltage of the first operational amplifier module when the bandgap voltage generation circuit is in sampling mode, and to perform first-order and higher-order temperature compensation on the generated bandgap voltage when the bandgap voltage generation circuit is in amplification mode. The bandgap reference circuit according to claim 2 is characterized in that, The bandgap voltage generation circuit further includes: The first voltage generation module is electrically connected to the first input terminal of the first operational amplifier module and is used to output a first voltage with a positive temperature coefficient. The second voltage generation module is electrically connected to the second terminal of the second charge storage module, and is used to output a second voltage with a positive temperature coefficient when the bandgap voltage generation circuit is in sampling mode. The third voltage generation module is electrically connected to the second terminal of the second charge storage module and is used to output a third voltage with a positive temperature coefficient when the bandgap voltage generation circuit is in amplification mode. The fourth voltage generation module is electrically connected to the second terminal of the third charge storage module and is used to output a fourth voltage with a positive temperature coefficient when the bandgap voltage generation circuit is in sampling mode. The fifth voltage generation module is electrically connected to the second terminal of the third charge storage module and is used to output a fifth voltage with zero temperature coefficient when the bandgap voltage generation circuit is in amplification mode. According to claim 3, the bandgap reference circuit is characterized in that, The first voltage generation module includes a first positive temperature coefficient bias current and a first transistor. The output terminal of the first positive temperature coefficient bias current is electrically connected to the first terminal of the first transistor. The first terminal of the first transistor is electrically connected to the first input terminal of the first operational amplifier module. The control terminal of the first transistor is electrically connected to the second terminal of the first transistor. The second terminal of the first transistor is grounded. The second voltage generation module includes a second positive temperature coefficient bias current and a second transistor. The output terminal of the second positive temperature coefficient bias current is electrically connected to the first terminal of the second transistor. The first terminal of the second transistor is electrically connected to the second terminal of the second charge storage module. The control terminal of the second transistor is electrically connected to the second terminal of the second transistor. The second terminal of the second transistor is grounded. The third voltage generation module includes a second positive temperature coefficient bias current and a third transistor. The output terminal of the second positive temperature coefficient bias current is electrically connected to the first terminal of the third transistor. The first terminal of the third transistor is electrically connected to the second terminal of the second charge storage module. The control terminal of the third transistor is electrically connected to the second terminal of the third transistor. The second terminal of the third transistor is grounded. The fourth voltage generation module includes a third positive temperature coefficient bias current and a fourth transistor. The output terminal of the third positive temperature coefficient bias current is electrically connected to the first terminal of the fourth transistor. The first terminal of the fourth transistor is electrically connected to the second terminal of the third charge storage module. The control terminal of the fourth transistor is electrically connected to the second terminal of the fourth transistor. The second terminal of the fourth transistor is grounded. The fifth voltage generation module includes a zero temperature coefficient bias current and a fifth transistor. The output terminal of the zero temperature coefficient bias current is electrically connected to the first terminal of the fifth transistor. The first terminal of the fifth transistor is electrically connected to the second terminal of the third charge storage module. The control terminal of the fifth transistor is electrically connected to the second terminal of the fifth transistor. The second terminal of the fifth transistor is grounded. The bandgap reference circuit according to claim 4 is characterized in that, The bandgap voltage generation circuit further includes: The first switch is located on the connection line between the output terminal of the first operational amplifier module and the second input terminal of the first operational amplifier module. The second switch is located on the connection line between the output terminal of the first operational amplifier module and the first terminal of the first charge storage module. The third switch is located on the connection line between the first input terminal of the first operational amplifier module and the first terminal of the first charge storage module. The fourth switch is located on the connection line between the output terminal of the second positive temperature coefficient bias current and the first terminal of the second transistor. The fifth switch is located on the connection line between the first end of the second transistor and the second end of the second charge storage module; The sixth switch is located on the connection line between the output terminal of the second positive temperature coefficient bias current and the first terminal of the third transistor. The seventh switch is located on the connection line between the first end of the third transistor and the second end of the second charge storage module. The eighth switch is located on the connection line between the first end of the fourth transistor and the second end of the third charge storage module. The ninth switch is located on the connection line between the first terminal of the fifth transistor and the second terminal of the third charge storage module; wherein, When the bandgap voltage generation circuit is in sampling mode, the first switch, the third switch, the fourth switch, the fifth switch and the eighth switch are in the closed state, and the second switch, the sixth switch, the seventh switch and the ninth switch are in the open state. When the bandgap voltage generating circuit is in amplification mode, the second, sixth, seventh, and ninth switches are closed, while the first, third, fourth, fifth, and eighth switches are open. The bandgap reference circuit according to claim 4 is characterized in that, The relationship between the capacitance value C1 of the first charge storage module and the capacitance value C2 of the second charge storage module is as follows: Where K is Boltzmann's constant, q is the unit charge, and I s1 I is the saturation current of the first transistor. s3 The saturation current of the third transistor, Vg0 is the reference bandgap voltage, T0 is the corresponding reference temperature point, and VBE0 is the voltage difference between the base and emitter at the corresponding reference temperature point. The bandgap reference circuit according to claim 2 is characterized in that, The relationship between the capacitance value C1 of the first charge storage module and the capacitance value C3 of the third charge storage module is as follows: C3 = C1 × (η - 1) Wherein, η is a process parameter. The bandgap reference circuit according to claim 2 is characterized in that, The bandgap buffer circuit includes: The second operational amplifier module has its first input terminal electrically connected to the output terminal of the bandgap voltage generation circuit. A fourth charge storage module, wherein the first terminal of the fourth charge storage module is electrically connected to the first input terminal of the second operational amplifier module, and the second terminal of the fourth charge storage module is grounded; when the bandgap buffer circuit is in the sampling state, the fourth charge storage module is used to store the bandgap voltage; when the bandgap buffer circuit is in the amplification state, the fourth charge storage module is used to output the bandgap voltage. The fifth charge storage module, when the bandgap buffer circuit is in sampling state, has its first terminal electrically connected to the second input terminal and the output terminal of the second operational amplifier module, and its second terminal electrically connected to the first input terminal of the second operational amplifier module. The fifth charge storage module is used to store the input noise and offset voltage of the second operational amplifier module. When the bandgap buffer circuit is in amplification state, the first terminal of the fifth charge storage module is electrically connected to the second input terminal of the second operational amplifier module, and its second terminal is electrically connected to the output terminal of the second operational amplifier module. The fifth charge storage module is used to perform voltage compensation for the second operational amplifier module. The bandgap reference circuit according to claim 8 is characterized in that, The bandgap buffer circuit further includes: The first transistor has its first terminal electrically connected to the output terminal of the bandgap voltage generation circuit, and its second terminal electrically connected to the first input terminal of the second operational amplifier module and the first terminal of the fourth charge storage module. The second transistor has its first terminal electrically connected to the output terminal of the second operational amplifier module, and its second terminal electrically connected to the second input terminal of the second operational amplifier module and the first terminal of the fifth charge storage module. The third transistor has its first terminal electrically connected to the output terminal of the second operational amplifier module, and its second terminal electrically connected to the second terminal of the fifth charge storage module. The fourth transistor has its first terminal electrically connected to the second terminal of the fifth charge storage module and the second terminal of the third transistor, and its second terminal electrically connected to the first input terminal of the second operational amplifier module. A signal absorption module is disposed on the connection circuit between the second terminal of the second transistor and the second input terminal of the second operational amplifier module, and on the connection circuit between the second terminal of the fourth transistor and the first input terminal of the second operational amplifier module, for reducing charge injection and clock feedthrough introduced by the first, second, and fourth transistors during switching; wherein, When the bandgap buffer circuit is in the sampling state, the first transistor, the second transistor, and the fourth transistor are in the conducting state, while the third transistor and the signal absorption module are in the disconnected state. When the bandgap buffer circuit is in the amplification state, the third transistor and the signal absorption module are in the conducting state, while the first transistor, the second transistor, and the fourth transistor are in the disconnected state. The bandgap reference circuit according to claim 9 is characterized in that, The signal absorption module includes: The fifth transistor, wherein the first terminal and the second terminal of the fifth transistor are electrically connected to the second input terminal of the second operational amplifier module and the second terminal of the second transistor; The sixth transistor has its first and second terminals electrically connected to the first input terminal of the second operational amplifier module and the second terminal of the fourth transistor. The bandgap reference circuit according to claim 10 is characterized in that, The bandgap buffer circuit further includes a clock module, which is used to output a first clock signal and a second clock signal with opposite phases. The first clock signal is used to control the on and off states of the first transistor, the second transistor, and the fourth transistor, and the second clock signal is used to control the on and off states of the fifth transistor and the sixth transistor. The bandgap reference circuit according to claim 10 is characterized in that, The fifth transistor is half the size of the second transistor, and the sixth transistor is half the size of the first transistor. The bandgap reference circuit according to claim 9 is characterized in that, The fourth charge storage module and the first transistor are also used to isolate the reverse input electrical signal of the subsequent load. An SDM circuit, characterized in that, Includes the bandgap reference circuit as described in any one of claims 1-13. An integrated circuit chip, characterized in that, Includes the bandgap reference circuit as described in any one of claims 1-13.

Images