Reconfigurable pipelined SDAC-LDAC SAR ADC stage

Abstract

A pipelined SAR ADC (26, 46) stage is configurable to operate in two modes: a first mode featuring high resolution but high power consumption, and a second mode that consumes lower power, but has lower resolution The ADC (26, 46) stage comprises a Small capacitive DAC (SDAC) in the SAR decision circuitry, and a Large capacitive DAC (LDAC) that, in the first mode, generates a residual voltage, which is amplified and propagated to further pipeline stages. The LDAC has a larger capacitance than the SDAC. The LDAC operates with a high SNDR, but due to high capacitive loading, it has high power consumption. In the second mode, the LDAC and its residual amplifier are disabled, and the SDAC generates the residual voltage. Because the SDAC does not load the input buffer or voltage references as much, the SDAC consumes less power than the LDAC, but the residual voltage it generates is more noisy and less linear.

Description

[0001] RECONFIGURABLE PIPELINED SDAC-LDAC SAR ADC STAGE

[0002] TECHNICAL FIELD

[0003] The present disclosure relates generally to Analog to Digital Converter (ADC) circuits, and in particular to a reconfigurable stage in a pipelined Successive Approximation Register ADC having Digital to Analog Converter (DAC) circuits of different sizes.

[0004] BACKGROUND

[0005] Many modern electronic devices receive or acquire information in the form of analog signals (e.g., optical signals, acoustic signals, electro-magnetic (EM) waves, and the like), and transform the information to the digital domain for processing by digital circuitry, such as Digital Signal Processors (DSP). Fast, accurate, low-power (particularly for battery operated devices) Analog to Digital Converters (ADC) are thus critical circuits in many devices.

[0006] In many applications, the required properties and operating parameters of the ADC may be dynamic. As a non-limiting example considered herein, User Equipment (UE) and corresponding base station circuitry in the Radio Access Network (RAN) of a wireless communication network exchange control- and user-plane data across an air interface by transmitting and receiving modulated Radio Frequency (RF) carrier waves. In particular, the most recent technical standards defining such networks, such as the Fifth Generation (5G) standard promulgated by the 3rdGeneration Partnership Project, define two bands of frequencies: FR1 (4.1 GHz to 7.125 GHz) and FR2 (24.25 GHz to 52.6 GHz). Operation in these bands place different requirements on the resolution of ADCs in receiver front-end circuits. Furthermore, a receiver operating within any given frequency range is subject to a dynamically varying radio environment, wherein the full resolution of an ADC may not be strictly required at all times, e.g., when advanced modulation and coding reduce the Signal to Noise and Distortion Ratio (SNDR) requirements. Another example is the overprovisioning of dynamic range typically implemented to receive a desired weak signal in presence of a strong interfering signal - when the interfering signal is weaker, the dynamic range requirement reduces accordingly. Where a high-precision, wide dynamic range ADC is not strictly required, it would be advantageous to operate the ADC in a mode that sacrifices resolution for power savings.

[0007] Numerous architectures for ADCs are known in the art, including pipelined Successive Approximation Register (SAR) ADCs. Attempts in the prior art to make such circuits reconfigurable, so that their operation may be tailored to the operating environment, suffer various deficiencies.

[0008] The Background section of this document is provided to place aspects of the present disclosure in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Approaches described in the Background section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.

[0009] SUMMARY

[0010] The following presents a simplified summary of the disclosure in order to provide a basic understanding to those of skill in the art. This summary is not an extensive overview of the disclosure and is not intended to identify key / critical elements of aspects of the disclosure or to delineate the scope of the disclosure. The sole purpose of this summary is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.

[0011] According to aspects of the present disclosure described and claimed herein, a pipelined SAR ADC stage is configurable to operate in two modes: a first, high resolution and high power mode, and a second, low resolution and low power mode. The ADC stage comprises a Small Digital to Analog Converter (SDAC) in the SAR decision circuitry, and a Large DAC (LDAC) that, in the first mode, generates a residual voltage (input voltage minus DAC voltage), which is amplified and propagated to further pipeline stages. The LDAC is physically larger than the SDAC, e.g., it has 4x larger corresponding capacitors. The LDAC operates with a high SNDR, but high power consumption. In situations where a high SNDR is not required, the ADC enters the second mode, where the LDAC and residual amplifier are disabled, and the SDAC generates the residual voltage. Because it does not load the input buffer providing the input signal to the ADC or voltage references which determine the input signal range of the ADC as much, the SDAC consumes less power than the LDAC, but the residual voltage it generates is more noisy and less linear. The SDAC residual voltage may be directly output to a downstream stage, or amplified with an additional residue amplifier. This amplifier consumes low power since its noise and linearity is optimized for low resolution. A separate SDAC residual amplifier allows for a parallel pipeline where all stages are scaled down in power.

[0012] One aspect relates to a stage in a pipelined Successive Approximation Register (SAR) Analog to Digital Converter (ADC). The stage includes an input presenting a stable analog input voltage; an approximation register configured to output a successively more accurate digital approximation of the input voltage in each of a plurality of decision cycles in response to input from a comparator; and a Small capacitive Digital to Analog Converter (SDAC) configured to generate an SDAC voltage representation of the approximation register output. The comparator is configured to determine whether the SDAC voltage is greater or less than the analog input voltage, and output an indication to the approximation register. The ADC stage further includes a Large capacitive Digital to Analog Converter (LDAC) configured to generate an LDAC voltage representation of the approximation register output that is more accurate than the SDAC voltage representation of the approximation register output. The LDAC has a larger capacitance than the SDAC. The ADC stage also includes LDAC subtraction circuitry configured to subtract the LDAC voltage from the input voltage, yielding an LDAC residual voltage; and an LDAC residual amplifier configured to amplify the LDAC residual voltage for a subsequent stage in the pipeline. The ADC stage is configured to operate in one of a first mode, wherein the LDAC, LDAC subtraction circuitry, and LDAC residual amplifier are enabled and operative, and a second mode, wherein the LDAC, LDAC subtraction circuitry, and LDAC residual amplifier are disabled and inoperative.

[0013] Another aspect relates to a method 100 of operating a pipelined SDAC-LDAC SAR ADC stage. The stage comprises an SDAC configured to generate an SDAC voltage representation of an approximation register output in a SAR decision circuit, and an LDAC configured to generate an LDAC voltage representation of the approximation register output that is more accurate than the SDAC voltage representation of the approximation register output. Both the SDAC and LDAC are capacitive DACs. The LDAC has a larger capacitance than the SDAC. A high resolution residual voltage generation circuit is operatively connected to the SAR decision circuit, and comprises the LDAC and an LDAC residual voltage amplifier. A digital output of the approximation register in the SAR decision circuit is successively updated in a predetermined number of decision cycles, such that the SDAC voltage more closely matches an analog input voltage. In a first mode, in each or the last decision cycle, the LDAC voltage is subtracted from the input voltage in the high resolution residual voltage generation circuit to generate an LDAC residual voltage. The LDAC residual voltage is amplified for use by a subsequent stage of an ADC pipeline. In a second mode, operation of at least the LDAC and the LDAC amplifier in the high resolution residual voltage generation circuit are disabled.

[0014] Yet another aspect relates to a User Equipment (UE) operative in a wireless communication network. The UE includes a transceiver comprising a pipelined ADC including at least the SAR ADC stage described above. The UE also includes processing circuitry operatively connected to the transceiver, and configured to perform the method described above.

[0015] Still another aspect relates to a base station operative in a wireless communication network. The base station includes a transceiver comprising a pipelined ADC including at least the SAR ADC stage described above. The base station also includes processing circuitry operatively connected to the transceiver, and configured to perform the method of described above.

[0016] Still another aspect relates to a computer program product comprising machine readable instructions configured to, when executed on processing circuitry, cause the SAR DAC stage described above to execute the method described above.

[0017] BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which aspects of the disclosure are shown. However, this disclosure should not be construed as limited to the aspects set forth herein. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout.

[0019] FIG. 1 is a block diagram of a SAR ADC.

[0020] FIG. 2 is a graph showing the operation of a SAR ADC.

[0021] FIG. 3 is a more detailed block diagram of two stages of a pipelined SAR ADC.

[0022] FIG. 4 is a block diagram of a SDAC-LDAC SAR ADC stage.

[0023] FIG. 5 is a simplified block diagram of the SDAC-LDAC SAR ADC stage of FIG. 4.

[0024] FIG. 6 is a block diagram of a SDAC-LDAC SAR ADC stage according to a first aspect of the present disclosure.

[0025] FIG. 7 is a block diagram of a SDAC-LDAC SAR ADC stage according to a second aspect of the present disclosure

[0026] FIG. 8 is a block diagram of a SDAC-LDAC SAR ADC stage according to a third aspect of the present disclosure

[0027] FIG. 9 is a schematic diagram showing disable circuitry for the LDAC.

[0028] FIG. 10 is a flow diagram of a method of operating a pipelined SDAC-LDAC SAR ADC.

[0029] FIG. 11A is a diagram of wireless communication in a wireless communication network.

[0030] FIG. 11 B is a hardware block diagram of a User Equipment operative in a wireless communication network.

[0031] FIG. 11C is a hardware block diagram of a base station operative in a wireless communication network.

[0032] DETAILED DESCRIPTION

[0033] For simplicity and illustrative purposes, the present disclosure is described by referring mainly to an exemplary aspect thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be readily apparent to one of ordinary skill in the art that the present disclosure may be practiced without limitation to these specific details. In this description, well known methods and structures have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0034] At high sample rates, e.g., above 100 MHz, the most power-efficient ADCs architecture is the successive-approximation register (SAR) technique, often in combination with other techniques like pipelining and time-interleaving to improve sampling rates. FIG. 1 depicts the basic components of a conventional N-bit SAR DAC. A Sample-and-Hold (S / H) circuit acquires an analog input voltage vm and maintains it at a stable value. An analog voltage comparator compares the analog input voltage vm with the output Vd of a Digital to Analog Converter (DAC), and outputs the binary result to an approximation register - that is, an indication of whether the DAC voltage Vd is above or below the input voltage. In each successive decision cycle, the approximation register changes its digital output, converging on a digital representation of the analog input voltage. Although many conversion strategies are known, for a digital SAR ADC, a common one is to initially set the Most Significant Bit (MSB) of the approximation register to 1, and all other bits to zero. This outputs a voltage from the DAC that is half of the ADC’s range. The comparator output indicates whether the analog input voltage is above or below this midpoint. If it is above, for the next decision cycle, the approximation register maintains the MSB at 1 , and switches only the next-least-significant bit to 1 , which divides the upper half of the voltage range in half, and again compares this value to the input voltage. This process continues through N decision cycles for an N-bit SAR ADC stage.

[0035] FIG. 2 depicts the process for a simple, 4-bit SAR ADC. The bold line represents the DAC output voltage Vd, the (constant) thin line is the input voltage vm, and the SAR ADC output is the digital code below the abscissa. Initially, the 4-bit approximation register is set to 1000, and vm is compared to VREF / 2. Since vm < REF / 2, the MSB is cleared to “0”. The approximation register is then set to 0100, and vm is compared to VREF / 4 (the center of the subrange O-VREF / 2 selected in the preceding decision cycle). Because vm > VREF / 4, the “1” is retained for this bit position, and the next lower bit is set to one, yielding 0110, which compares the input voltage to Vd = 3 REF / 8. The input voltage vm is below this value, so this bit value is cleared, and the last bit is tested with the approximation register being set to 0101 , for Vd = 7VREF / 16. Because VIN exceeds this value, the “1” is retained for the LSB, and the SAR ADC output is 0101 for this value of Vin.

[0036] To relax the speed requirements of each SAR ADC stage, it is known to pipeline them. Additional circuitry required is shown in FIG. 1 with dashed lines. In this case, the first SAR DAC stage resolves and stores a few of the MSBs, then subtracts the final DAC output Vd from the input voltage, yielding a “residual” voltage, or the unquantified portion of the input voltage. This residual is buffered and passed to a successive stage of a pipeline, which captures the residual voltage level in a S / H circuit and proceeds to resolve a few more bits. Meanwhile, the first SAR ADC samples a new analog voltage value, and proceeds to resolve a digital representation of the MSBs of the new sample. Control circuitry tracks the progress of each input sample through the pipeline, and assembles the full digital representation of each.

[0037] Another way to perform the comparison between vm and Vd, which can be performed in a capacitive DAC without any adder circuitry, is to subtract the DAC output from the analog input voltage in each decision cycle, generating a series of residual voltages. The input voltage is initially sampled and retained. During subsequent cycles, parts of the capacitor bank are connected to a reference voltage REF or common mode voltage CM, in response to the Also known as “sample and adjust,” the capacitors in the DAC are all charged to the input voltage at the beginning of each decision cycle. As the DAC then adjusts its output according to the approximation register output di. The DAC then it outputs the residual voltage vm - Vd. In this case, the comparator only determines whether the residual voltage is positive or negative, which yields the same information for the approximation register to make a more accurate digital approximation in the next decision cycle. In this technique, the initial approximation register output di may be set to 0, and the comparator determines the polarity of the analog input voltage during the first decision cycle. This is the form of SAR ADC that will be used for discussion herein; however, those of skill in the art will readily appreciate that performing the comparison between input voltage and DAC output is design choice that can be implemented several ways within the scope of the claims.

[0038] FIG. 3 depicts a two-stage pipelined SAR ADC. A S / H circuit captures an input sample vmi and subtracts from it the output of a DAC, yielding a residual voltage vri(the adder is shown to indicate functionality; as discussed above, the subtraction takes place within the DAC). A comparator (cmp) can be implemented in many ways; in one aspect, a binary comparator is used to detect the sign of the residue vri. Each decision element then has a trinary value {1 ,0,-1} where the value 0 represents the case when no decision has been made for a given cycle. In each comparison cycle, the cmp output informs an approximation register (reg), which outputs a digital value d, = ^d1 0,d ,...,d1 Nbi iJ that converges towards VM within a predetermined level of accuracy defined by the number of decision cycles Nbi , and weights wi = ] 'nthe DAC. When the Nbi cycles have been completed, the residue vriis amplified in a residual amplifier (RA) having a gain A. The amplified residue vm2 then serve as input sample to the next stage in the ADC (SAR2) that continues the conversion by performing a further Nb2 decision cycles on the input sample v / n2 through a DAC with weights

[0039] Nbi

[0040] The digital output ui of the first SAR ADC stage is formed by • d,kwhere k=Q

[0041] Wj = ^WI0, WI I , ..., WIWM IJ . Here, Wj is a digital representation of the DAC weights Wj and ideally Wj = aiwi. In practice, the actual weights of the DAC Wj may differ slightly from , e.g., due to mismatches introduced in manufacturing. When the weights are binary-scaled the calculation of the SAR ADC becomes trivial.

[0042] The second SAR ADC stage SAR2 operates as the first SAR1 stage, with DAC weights w2and having Nb2 decision cycles. Due to the residue amplification, the output U2 is scaled by \ / A before being combined with the output of the first stage ui, to yield the combined . Ideally, A = A but due to errors introduced, e.g., in manufacturing, there will be a deviation.

[0043] In one pipelined SAR ADC architecture, the decision loop and the residue generation for a subsequent stage in a pipelined SAR ADC are separated. See, e.g., V. Tripathi and B. Murmann, "A 160 MS / S, 11.1 mW, single-channel pipelined SAR ADC with 68.3 dB SNDR," published in the Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014, pp. 1-4, and W. Jiang, Y. Zhu, M. Zhang, C. -H. Chan and R. P. Martins, "3.2

[0044] A 7.6mW 1GS / s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature- Compensated Dynamic Gm-R-Based Amplifier," published in the 2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, pp. 60-62, the disclosures of both of which are incorporated herein by reference in their entireties.

[0045] FIG. 4 depicts an example of this architecture, referred to herein as Small-DAC Large- DAC, or SDAC-LDAC. Small and large refer to physical size. For example, in a capacitive DAC (as is commonly used in SAR ADCs), the LDAC is structured the same as the SDAC, but each corresponding capacitor is larger. The lower portion, also referred to herein as a SAR decision circuit, contains the same SAR ADC topology as depicted in the SAR1 stage of FIG. 3, and includes an SDAC (with internal subtraction). In addition, there is a separate LDAC (with internal subtraction) operatively connected to the approximation register of the SAR ADC stage. The LDAC output is subtracted from the input to yield a residue vm for residue amplification and further conversion in subsequent stages. An optional logic block (as indicated by dashed lines) separates the two. The logic block may, for example, implement dynamic element matching to randomize weight errors in the LDAC, and / or other functions. The LDAC, v -i residue amplifier, and optional logic block are also referred to herein as a high resolution residual voltage generation circuit.

[0046] The SDAC-LDAC architecture presents several advantages. A faster, less accurate, lower power SDAC SAR ADC can be used for decisioning without affecting linearity and noise of an ADC with at least one subsequent conversion stage. In particular, due to its smaller capacitors, the SDAC settles faster (stable vSri). This allows for clocking the comparator earlier and leads to faster bit conversion, i.e., higher sample rate. Additionally, there is no comparator loading the LDAC path. This means both that there is no comparator kickback affecting the integrity of the residue VLH-, and there is less signal attenuation, resulting in higher SNR.

[0047] The errors introduced by the small DAC SAR ADC will only lead to an increase in residue. Additionally, signal levels in the SDAC SAR ADC and LDAC can be decoupled. The SDAC SAR ADC can operate with higher signal levels than the LDAC to lower the impact from comparator offset, kickback, and noise, while introducing moderate errors due to nonlinear distortion through a preceding gain stage (^s).

[0048] Finally, there is an opportunity of introducing a middle layer of logic layer when propagating di from the SDAC SAR ADC to the LDAC. This logic layer and its delay is outside the timing critical loop, leading to a higher sample rate.

[0049] The SDAC-LDAC architecture can but used in any, or all, of the stages in a pipelined SAR ADC.

[0050] There are gain blocks introduced for the SDAC and LDAC paths, respectively represented by gains gLand gs. These are optional; they may be used solely to represent differences in the gains of respective paths for modeling purposes. Alternatively, at least one of gain blocks may represent an actual amplifier or buffer, e.g., to differentiate the signal levels between the SDAC and LDAC signal paths.

[0051] FIG. 5 shows a simplified block diagram view of the SDAC-LDAC architecture, also showing the difference in capacitance between the SDAC and LDAC. As discussed above, the subtractions of the DAC voltages from the input voltage occur internally to the DACs, which output residual voltages.

[0052] In a paper by Q. Yu et al., "A 9.08 ENOB 10b 400MS / S Subranging SAR ADC with Subsetted CDAC and PDAS in 40nm CMOS," published in the ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021 , pp. 391-394, the disclosure of which is incorporated herein by reference in its entirety, it is recognized that the imbalance of the parasitic capacitance at the top-plate of two DACs, as well as the input capacitance of the comparator, results in gain mismatch, which is handled by the authors using redundancy. Further, this work uses a detect-and-skip (DAS) logic layer between the SDAC SAR ADC and the LDAC to optimize the switching process of the LDAC, whereby unnecessary switching is skipped.

[0053] In summary, the SDAC-LDAC SAR ADC architecture provides numerous benefits, including increased sample rate and higher SNR.

[0054] As discussed above, in many applications there is a need to reconfigure an ADC for lower resolution (fewer Effective Number Of Bits, or ENOB), and / or lower SNR, that achieves power savings and does not impose deleterious effects on the high-resolution operation of the

[0055] ADC.

[0056] Reconfigurable ADCs built on other techniques are known in the art - configuring both the number of bits converted and the amount of capacitance. One way to control capacitance per unit cell is described in Figure 3 of the paper by M. Ding, P. Harpe, Y. -H. Liu, B. Busze, K. Philips and H. de Groot, "26.2 A 5.5fJ / conv-step 6.4MS / S 13b SAR ADC utilizing a redundancy- facilitated background error-detection-and-correction scheme," published in the 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, San Francisco, CA, USA, 2015, pp. 1-3, the disclosure of which is incorporated herein by reference in its entirety. The capacitance reconfigurability is used to calibrate for mismatch between bit weights, rather than reconfiguring for a higher SNR. In general, in an optimized and thermal noise-limited design, it is expected that scaling up capacitance by 4x will yield a 6 dB increase in SNR, per bit of resolution, but at the cost of 4x the power consumption.

[0057] Other examples of reconfigurable SAR ADCs include the papers by S. O'Driscoll and T. H. Meng, "Adaptive resolution ADC array for neural implant," published in the 2009 Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Minneapolis,

[0058] MN, USA, 2009, pp. 1053-1056; P. Harpe, Y. Zhang, G. Dolmans, K. Philips and H. De Groot, "A 7-to-10b 0-to-4MS / s flexible SAR ADC with 6.5-to-16fJ / conversion-step," published in the 2012 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 2012, pp. 472-474; and M. Yip and A. P. Chandrakasan, "A resolution-reconfigurable 5-to-10b 0.4-to- 1V power scalable SAR ADC," published in the 2011 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 2011 , pp. 190-192.

[0059] In particular, in O’Driscoll, et al., 8 to 3 bit resolution reconfiguration is supported. The (input) sampling capacitance and resolution are digitally controllable through two extra switches in series per bit weight capacitor for the 5 MSBs. The power consumption is reduced only by 2x going from 8b to 6b resolution (1uWto 0.4uW).

[0060] In Harpe, et al., the resolution is 10-7 bits, with less reconfigurability resulting in fewer switches in series with the input signal. Thus, only two modes of input capacitance are supported: either 225 fF for 10 / 9 bits or 70 fF for 8 / 7 bits. That is, the input capacitance scales only 3x from 10 bits to 8 bits. The comparator noise and power consumption are reconfigured. Also here, the power consumption only scales 2x going from 10 bit to 8 bit resolution

[0061] In Yip et al., 10-5 bit resolution reconfiguration is supported. From 10 bits to 8 bits, the input capacitance scales 4x while power consumption scales poorly, only 30%.

[0062] The prior art SAR ADCs discussed above all operate at a low sample rate (0.1-4 MSps). The power consumption and input capacitance scales poorly with the number of bits. A 1 bit lower resolution is implemented by simply disabling the MSB conversion and its capacitor (because capacitive DAC steps are a ratio between a binary weighted capacitor and the sum of all capacitors, the second MSB simply assumes the role of MSB). This yields 6 dB worse SNR but only half the input capacitance. To have a power efficient scaling, the total capacitance needs to be scaled down 4x. This also applies to the comparator noise power and power consumption, and other surrounding circuitry such as logic, buffers, and the like.

[0063] Additionally, these prior art SAR ADCs require several switches in series with the signal path for reconfigurability. These switches are present in the high resolution mode, when performance is most important, and disabled for lower resolution modes. The switches will degrade the linearity (spurious-free dynamic range, or SFDR) of the converter and are problematic to implement at higher sample rates.

[0064] The prior art reconfigurable SAR ADCs are deficient in several respects. For the input buffer, the power consumption and linearity is worsened by the capacitive load from the capacitive DAC. The ripple on the voltage references is also dependent on the capacitive load. The prior art SAR ADCs have both SDAC and LDAC capacitor banks loading both the input buffer and the voltage references. The prior art SDAC-LDAC SAR ADCs do not reconfigure the SDAC-LDAC capacitor banks and RA for power reduction. It is not possible to fully disable the LDAC, since the LDAC residue is used for the RA and subsequent stages. Reconfiguring the LDAC for lower resolution adds switches that impact the high resolution mode. Prior art designs use only one RA, the topology of which is chosen based on excellent linearity and noise, and thus is not optimal for a low resolution mode. The LDAC itself has a speed and power penalty. The LDAC is optimized for linearity using special techniques, such as bottom-plate sampling and Dynamic Element Matching (DEM). This functionality is not easy to reconfigure, disable, or bypass while maintaining conversion speed.

[0065] A split of the LDAC into smaller unit cells that are reconfigurable leads to area overhead and speed penalty, because the LDAC is designed for high linearity with certain unit capacitors that are not easily split and reconfigured. Furthermore, the unit cell Metal-Oxide-Metal (MOM) capacitors are based on several metal layers to be area efficient. Having reconfigurability in number of layers adds complexity and an area penalty. Thus, there is a limit to how small the unit cell can be reconfigured. The scaling of capacitance in the LDAC is ultimately limited by the unit capacitor size. This implies that the minimum capacitance of the LDAC is at best equal to the SDAC. Thus, the input buffer and reference voltages will see at least 2xSDAC in capacitance.

[0066] There is no prior-art high-speed SAR ADC that adopts the SDAC-LDAC solution and has reconfigurable resolution. As discussed above, reconfigurability is desirable, as high SNR is not always required, and reduced power consumption is an ongoing goal in battery-powered devices to prolong device operative life, and in fixed station electronics to reduce heat dissipation.

[0067] FIG. 6 depicts a pipelined SDAC-LDAC SAR ADC stage according to one aspect of the present disclosure. For convenience, the SDAC-LDAC SAR ADC stage is described in the first stage in a single or two parallel pipelines, although in general it could be deployed as any pipeline stage. As noted, the LDAC has 4x the size / capacitance of the SDAC, although this ratio is representative only and is not limiting. In general, the size / capacitance ratio is constrained on the high side by total area and how small the SDAC can be fabricated. On the low side, a ratio much below 4x yields diminishing value. As compared to, e.g., FIG. 5, a control block (control) and one or more SDAC residual voltage amplifiers (RAs) are added. The biggest difference is in functionality, controlled by the control block. The SDAC-LDAC SAR ADC operates in two alternative modes.

[0068] In a first, high precision mode, the LDAC block (including LDAC and adder), and the LDAC RA are enabled and operative, and the circuit operates as described above. Briefly, the analog input voltage vmi is sampled on both the LDAC and SDAC. After that, the conversion of bits in the SDAC SAR ADC proceeds. Sequentially the comparator takes decisions and updates the approximation register based on those decisions. During the decisioning, or after all decisions are taken, the decisions (di) are output to the LDAC (optionally via a logic layer). The LDAC produces a residual voltage (vLri) that is amplified by RAL and sampled by the next stage as Vm2. The operation is then repeated for the next sample.

[0069] In a second, low resolution and low power consumption mode, the LDAC and residual amplifier RAL are disabled and inoperative, and RAs is enabled. The input signal is sampled only on the SDAC. After that, the conversion of bits in the SDAC proceeds, where sequentially the comparator takes decisions and updates the approximation register based on those decisions. After all decisions are completed, the residual voltage vSriis available in the SDAC. The residual voltage vsri is amplified by RAs and output to the next stage, as v / n2. The procedure is then repeated for the next sample.

[0070] Using the nomenclature defined above, in the first mode, both the SAR decision circuit and the high resolution residual voltage generation circuit are enabled and operational, generating high resolution residual voltage levels for subsequent pipeline stages. In the second mode, the high resolution residual voltage generation circuit is disabled and inoperative, and a residual voltage (or just the digital output of the approximation register) is instead generated in the SAR decision circuit.

[0071] The Signal to Noise and Distortion Ratio (SNDR) in the first mode is primarily determined by kT / C noise from the LDAC and noise from RAL. Similarly, SNDR in the second mode is set by kT / C noise of the SDAC and noise from RAs. Here, the 4x smaller capacitance of the SDAC leads to 4x larger noise power and 6dB lower SNDR. Thus, the noise power of RAs can scale up 4x and its size scale down 4x, with 4x lower power consumption of the RA. Furthermore, a different RA topology can be chosen, that is optimized for speed and power, rather than high linearity and low noise.

[0072] The second mode has significant benefits, compared to the first (conventional) mode, when high resolution and high SNDR are not required. The input buffer and voltage references see only a total capacitance of 1C instead of 5C. Thus, the input buffer and voltage references can be reconfigured for 5x lower power consumption. The switching power of circuits in the LDAC and the logic layer is zero. The total DAC power consumption is about 5x lower, depending on the implementation details of the LDAC and SDAC. The residue amplifier power consumption is 4x lower. The RA typically dominates the power consumption of a LDAC-SDAC SAR ADC.

[0073] FIG. 7 shows a SDAC-LDAC SAR ADC according to another aspect of the present disclosure. In this aspect, the residual voltage vSrifrom the SDAC is connected to the next stage of a second path, node v / ns2. The residual voltage is amplified by RAs and sampled and converted into bits by one or multiple subsequent stages, which may comprise one or more similar or identical pipeline stages, a SAR converter, or any type of ADC. In other variations, residual voltage vSrican be directly connected to the next stage (v / ns2) from the SDAC and bypass RAs, or RAs can have unity gain (A=1), because of the low requirements. This second path is tailored for low resolution (low SNDR), e.g., scaled down in power and size. Hence, the SDAC-LDAC SAR ADC of FIG. 7 may be the first stage in parallel pipelines, with concomitant power savings, and SNDR penalty, at each stage when operated in the second mode. Achieving this benefit in the aspect depicted in FIG. 6 would require circuitry and / or switches to reconfigure the stage(s) in low power mode. Such circuitry would be in the main path and thus would impact the performance in the first, high SNDR mode. FIG. 8 depicts a SDAC-LDAC SAR ADC according to yet another aspect of the present disclosure. In this aspect, there is no additional RA or second path. In the second, low resolution mode, the LDAC and RAL are disabled an inoperative, and the bits from the approximation register (di) are taken as the only output. This is feasible, depending on how many bits are converted in the SDAC and the resolution requirement in the second, low resolution mode.

[0074] Figure 9 shows an example of a 5 bit LDAC, where the input sampling and DAC switching is disabled using AND gates and an enable signal (en). The disable logic is not on the critical path in the first, high resolution mode, which is the SDAC bit decisioning. This delay occurs for each bit decision. In contrast, the disable logic timing penalty occurs only once, and in any event may be merged with necessary buffer circuity.

[0075] Figure 10 depicts the steps in a method 100 of operating a pipelined SDAC-LDAC SAR ADC stage according to aspects of the present disclosure discussed herein. The stage comprises an SDAC configured to generate an SDAC voltage representation of an approximation register output in a SAR decision circuit, and an LDAC configured to generate an LDAC voltage representation of the approximation register output that is more accurate than the SDAC voltage representation of the approximation register output. The LDAC is physically larger than the SDAC. A high resolution residual voltage generation circuit is operatively connected to the SAR decision circuit, and comprises the LDAC and an LDAC residual voltage amplifier.

[0076] A digital output of the approximation register in the SAR decision circuit is successively updated in a predetermined number of decision cycles, such that the SDAC voltage more closely matches an analog input voltage (block 102). In a first mode (block 104), in each or the last decision cycle, the LDAC voltage is subtracted from the input voltage in the high resolution residual voltage generation circuit to generate an LDAC residual voltage (block 106). The LDAC residual voltage is amplified for use by a subsequent stage of an ADC pipeline (block 108). In a second mode (block 104), operation of at least the LDAC and the LDAC amplifier in the high resolution residual voltage generation circuit are disabled (block 110).

[0077] Figure 11A is a diagram of transmissions over the air interface of Radio Access Network (RAN) of a wireless communication network 10, such as a 3GPP 4G (Long Term Evolution, or LTE) or 5G (New Radio, or NR) network. A User Equipment (UE) 20, such as a smartphone, receives and transmits modulated Radio Frequency (RF) signals, over one or more antennas, from and to a base station 40, such as an LTE eNB or an NR gNB.

[0078] At each of the UE 20 and base station 40, at least one transceiver receives and transmits RF signals. At least the receiving function of these transceivers requires high-speed ADC. However, depending on the channel quality, presence of interfering RF signals, modulation and coding scheme (MCS) employed, and the like, high-resolution ADC may not always be required. Low power consumption, however, is always a requirement of a battery- powered UE 20, and is preferred at the base station 40 to reduce heat dissipation. Accordingly, one or both of the UE 20 and base station 40 may employ a reconfigurable pipelined SDAC- LDAC SAR ADC as described herein.

[0079] Figure 11 B is a block diagram of the UE 20 of Figure 11 A. As used herein, the term UE may refer to a user-operated telephony terminal, a machine-to-machine (M2M) device, a machine-type communications (MTC) device, a Narrowband Internet of Things (NB-loT) device (in particular a UE implementing the 3GPP standard for NB-loT), etc. A UE 20 may also be referred to as a radio device, a radio communication device, a wireless communication device, a wireless terminal, or simply a terminal - unless the context indicates otherwise, the use of any of these terms is intended to include device-to-device UEs or devices, machine-type devices or devices capable of machine-to-machine communication, sensors equipped with a radio network device, wireless-enabled table computers, mobile terminals, smartphones, laptop-embedded equipped (LEE), laptop-mounted equipment (LME), USB dongles, wireless customer-premises equipment (CPE), and the like.

[0080] The UE 20 transmits and receives RF signals on at least one antenna 24, which may be internal or external, as indicated by dashed lines. The RF signals are generated, and received, by one or more transceiver circuits 22, which includes one or more reconfigurable pipelined SDAC-LDAC SAR ADCs. The transceiver circuits 22, as well as other components of the UE 20, are controlled by processing circuitry 28. Memory 30 operatively connected to the processing circuitry 28 stores software in the form of computer instructions operative to cause the processing circuitry 28 to execute the method 100 described herein. A user interface 32 may include output devices such as a display and speakers (and / or a wired or wireless connection to audio devices such as ear buds), and / or input devices such as buttons, a keypad, a touchscreen, and the like. As indicated by the dashed lines, the user interface 32 may not be present in all UEs 20; for example, UEs 20 designed for Machine Type Communications (MTC) such as Internet of Things (loT) devices, may perform dedicated functions such as sensing / measuring, monitoring, meter reading, and the like, and may not have any user interface 32 features.

[0081] Figure 11C is a block diagram of the base station 40 of Figure 11 A. A base station 40 - known in various network implementations as a Radio Base Station (RBS), Base Transceiver Station (BTS), Node B (NB), enhanced Node B (eNB), Next Generation Node B (gNB), or the like - is a node of a wireless communication network that implements a Radio Access Network (RAN) in a defined geographic area called a cell, by providing radio transceivers to communicate wirelessly with a plurality of UEs 20.

[0082] The base station 40 transmits and receives RF signals on a plurality of antennas 44. As indicated by the broken line, the antennas 44 may be located remotely from the base station 40, such as on a tower or building. The RF signals are generated, and received, by one or more transceiver circuits 42. The transceiver circuits 42, as well as other components of the base station 40, are controlled by processing circuitry 48. Memory 50 operatively connected to the processing circuitry 48 stores instructions operative to cause the processing circuitry 48 to execute the method 100 described herein. Although the memory 50 is depicted as being separate from the processing circuitry 48, those of skill in the art understand that the processing circuitry 48 includes internal memory, such as a cache memory or register file. Those of skill in the art additionally understand that virtualization techniques allow some functions nominally executed by the processing circuitry 48 to actually be executed by other hardware, perhaps remotely located (e.g., in the so-called “cloud”). Communication circuitry 52 provides one or more communication links to one or more other network nodes, propagating communications to and from UEs 20, from and to other network nodes or other networks, such as telephony networks or the Internet.

[0083] In all aspects, the processing circuitry 28, 48 may comprise any sequential state machine operative to execute machine instructions stored as machine-readable computer programs in memory 30, 50, such as one or more hardware-implemented state machines (e.g., in discrete logic, FPGA, ASIC, etc.)-, programmable logic together with appropriate firmware; one or more stored-program, general-purpose processors, such as a microprocessor or Digital Signal Processor (DSP), together with appropriate software; or any combination of the above.

[0084] In all aspects, the memory 30, 50 may comprise any non-transitory machine- readable media known in the art or that may be developed, including but not limited to magnetic media (e.g., floppy disc, hard disc drive, etc.), optical media (e.g., CD-ROM, DVD-ROM, etc.), solid state media (e.g., SRAM, DRAM, DDRAM, ROM, PROM, EPROM, Flash memory, solid state disc, etc.), or the like.

[0085] In all aspects, the transceiver circuits 22, 42 are operative to communicate with one or more other transceivers via a Radio Access Network (RAN) according to one or more communication protocols known in the art or that may be developed, such as IEEE 802. xx, CDMA, WCDMA, GSM, LTE, UTRAN, WiMax, NB-loT, or the like. The transceiver 22, 42 implements transmitter and receiver functionality appropriate to the RAN links (e.g., frequency allocations and the like). The transmitter and receiver functions may share circuit components and / or software, or alternatively may be implemented separately.

[0086] In all aspects, the communication circuitry 52 may comprise a receiver and transmitter interface used to communicate with one or more other nodes over a communication network according to one or more communication protocols known in the art or that may be developed, such as Ethernet, TCP / IP, SONET, ATM, IMS, SIP, or the like. The communication circuits 52 implement receiver and transmitter functionality appropriate to the communication network links (e.g., optical, electrical, and the like). The transmitter and receiver functions may share circuit components and / or software, or alternatively may be implemented separately. Although not shown in FIG. 11 C, the communication circuitry 52 may also include one or more reconfigurable pipelined SDAC-LDAC SAR ADCs according to aspects of the present disclosure. Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and / or is implied from the context in which it is used. All references to a / an / the element, apparatus, component, means, step, etc., are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and / or where it is implicit that a step must follow or precede another step. Any feature of any of the aspects disclosed herein may be applied to any other aspect, wherever appropriate. Likewise, any advantage of any of the aspects may apply to any other aspects, and vice versa. Other objectives, features and advantages of the enclosed aspects will be apparent from the description.

[0087] The term “unit” may have conventional meaning in the field of electronics, electrical devices and / or electronic devices and may include, for example, electrical and / or electronic circuitry, devices, modules, processors, memories, logic solid state and / or discrete devices, computer programs or instructions for carrying out respective tasks, procedures, computations, outputs, and / or displaying functions, and so on, as such as those that are described herein.

[0088] As used herein, the term “configured to” means set up, organized, adapted, or arranged to operate in a particular way; the term is synonymous with “designed to,” or with respect to processing circuitry, “programmed to.”

[0089] Some of the aspects contemplated herein are described more fully with reference to the accompanying drawings. Other aspects, however, are contained within the scope of the subject matter disclosed herein. The disclosed subject matter should not be construed as limited to only the aspects set forth herein; rather, these aspects are provided by way of example to convey the scope of the subject matter to those skilled in the art.

[0090] The present disclosure may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the disclosure. The present aspects are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended aspects are intended to be embraced therein.

Claims

CLAIMSWhat is claimed is:

1. A stage in a pipelined Successive Approximation Register, SAR, Analog to Digital Converter, ADC (26, 46), comprising: an input presenting a stable analog input voltage (V ; an approximation register (reg) configured to output a successively more accurate digital approximation (di) of the input voltage in each of a plurality of decision cycles in response to input from a comparator (cmp); a Small capacitive Digital to Analog Converter, SDAC, configured to generate an SDAC voltage representation of the approximation register (reg) output; wherein the comparator (cmp) is configured to determine whether the SDAC voltage is greater or less than the analog input voltage (V , and output an indication to the approximation register (reg); a Large capacitive Digital to Analog Converter, LDAC, configured to generate an LDAC voltage representation of the approximation register output (di) that is more accurate than the SDAC voltage representation of the approximation register output, wherein the LDAC has a larger capacitance than the SDAC;LDAC subtraction circuitry configured to subtract the LDAC voltage from the input voltage (V , yielding an LDAC residual voltage (VL^); and an LDAC residual amplifier (RAL) configured to amplify the LDAC residual voltage (VL^) for a subsequent stage in the pipeline; wherein the pipelined SAR ADC stage is configured to operate in one of a first mode wherein the LDAC, LDAC subtraction circuitry, and LDAC residual amplifier (RAL) are enabled and operative, and a second mode wherein the LDAC, LDAC subtraction circuitry, and LDAC residual amplifier (RAL) are disabled and inoperative.

2. The SAR ADC stage of claim 1 wherein the SDAC is configured to output the SDAC voltage; and the comparator (cmp) is configured to compare the input voltage and SDAC voltage; and the indication output from the comparator (cmp) to the approximation register (reg) is a digital value.

3. The SAR ADC stage of claim 1 wherein the SDAC voltage is internal to the SDAC; the SDAC includes subtraction circuitry configured to subtract the SDAC voltage from the input voltage, yielding an unquantified SDAC residual voltage (Vsrt)', the SDAC is configured to output the SDAC residual voltage (Vsrt)', andthe comparator (cmp) is configured to determine whether the SDAC residual voltage (Vsrt) is positive or negative.

4. The SAR ADC stage of claim 3 wherein the indication output by the comparator (cmp) to the approximation register (reg) is a trinary value of -1 , 0, or 1 , wherein 0 indicates that no decision has been made for the current cycle.

5. The SAR ADC stage of any preceding claim wherein, in the second mode, the output of the SAR DAC stage is the digital output (di) of the approximation register after a predetermined number of decision cycles.

6. The SAR ADC stage of any of claims 1-4 further comprising:SDAC subtraction circuitry configured to subtract the SDAC voltage from the input voltage, yielding an unquantified SDAC residual voltage; and an SDAC residual amplifier (RAs) configured, in the second mode, to amplify the SDAC residual voltage (Vsrt) for a subsequent stage in the pipeline.

7. The SAR ADC stage of claim 6 wherein the outputs of the LDAC residual amplifier (RAL) and the SDAC residual amplifier (RAs) are connected together, and wherein in the first mode, the SDAC residual amplifier is disabled and inoperative.

8. The SAR ADC stage of claim 6 wherein the outputs of the LDAC residual amplifier (RAL) and the SDAC residual amplifier (RAs) are separate.

9. A method of operating a pipelined Successive Approximation Register, SAR, Analog to Digital Converter, ADC (26, 46), comprising a Small capacitive Digital to Analog Converter, SDAC, configured to generate an SDAC voltage representation of an approximation register (reg) output (di) in a SAR decision circuit, and a Large capacitive Digital to Analog Converter, LDAC, configured to generate an LDAC voltage representation of the approximation register output that is more accurate than the SDAC voltage representation of the approximation register (reg) output (di), wherein the LDAC has a larger capacitance than the SDAC, in a high resolution residual voltage generation circuit operatively connected to the SAR decision circuit, the method comprising: successively updating (102) a digital output (di) of the approximation register (reg) in the SAR decision circuit in a predetermined number of decision cycles, such that the SDAC voltage more closely matches an analog input voltage (V ; in a first mode (104),in each or the last decision cycle, subtracting (106) the LDAC voltage from the input voltage (Vmi) in the high resolution residual voltage generation circuit to generate an LDAC residual voltage, and amplifying (108) the LDAC residual voltage for use by a subsequent stage of an ADC pipeline; and in a second mode (104), disabling (110) operation of at least the LDAC and the LDAC amplifier (RAL) in the high resolution residual voltage generation circuit.

10. The method of claim 9 wherein the SDAC is configured to output the SDAC voltage; and wherein successively updating a digital output (di) of the approximation register (reg) comprises comparing the input voltage (Vmi) and SDAC voltage; and providing a digital indication to the approximation register (reg) of which voltage is greater.

11. The method of claim 9 wherein the SDAC voltage is internal to the SDAC; and wherein successively updating a digital output (di) of the approximation register (reg) comprises: subtracting the SDAC voltage from the input voltage, yielding an unquantified SDAC residual voltage (Vsrt)', determining whether the SDAC residual voltage (Vsrt) is positive or negative; and providing an indication to the approximation register (reg) whether the residual voltage (Vsrt) is positive or negative.

12. The method of claim 11 wherein providing an indication to the approximation register (reg) whether the residual voltage (Vsrt) is positive or negative comprises providing a trinary value of -1 , 0, or 1 , wherein 0 indicates that no decision has been made for the current cycle.

13. The method of any of claims 9-12 further comprising, in the second mode, outputting the digital output (di) of the approximation register (reg) after a predetermined number of decision cycles.

14. The method of any of claims 9-12 further comprising: subtracting the SDAC voltage from the input voltage (V , yielding an unquantified SDAC residual voltage (Vsrt)', and amplifying the SDAC residual voltage (Vsrt) for a subsequent stage in the pipeline.

15. A User Equipment (20) operative in a wireless communication network (10), comprising: a transceiver (22) comprising a pipelined ADC (26) including at least the SAR DAC stage of any of claims 1-8; and processing circuitry (28) operatively connected to the transceiver (22), and configured to perform the method (100) of any of claims 9-14.

16. A base station (40) operative in a wireless communication network (10), comprising: a transceiver (42) comprising a pipelined DAC including at least the SAR ADC (46) stage of any of claims 1-8; and processing circuitry (48) operatively connected to the transceiver (42), and configured to perform the method (100) of any of claims 9-14.

17. A computer program product comprising machine readable instructions configured to, when executed on processing circuitry, cause the SAR ADC (26, 46) stage of any of claims 1-8 to execute the method (100) of any of claims 9-14.

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